From 1b5816a206016d06128bd5e9afa7fbf8f09b0847 Mon Sep 17 00:00:00 2001 From: Scott Larson Date: Wed, 30 Sep 2020 15:42:41 -0700 Subject: [PATCH] 6.1 minor release --- LICENSED-HARDWARE.txt | 2 +- README.md | 3 +- cmake/linux.cmake | 31 + cmake/win32.cmake | 15 + common/inc/tx_api.h | 21 +- common/inc/tx_block_pool.h | 4 +- common/inc/tx_byte_pool.h | 4 +- common/inc/tx_event_flags.h | 4 +- common/inc/tx_initialize.h | 4 +- common/inc/tx_mutex.h | 4 +- common/inc/tx_queue.h | 4 +- common/inc/tx_semaphore.h | 4 +- common/inc/tx_thread.h | 4 +- common/inc/tx_timer.h | 4 +- common/inc/tx_trace.h | 4 +- common/inc/tx_user_sample.h | 6 +- common/src/tx_block_allocate.c | 4 +- common/src/tx_block_pool_cleanup.c | 4 +- common/src/tx_block_pool_create.c | 4 +- common/src/tx_block_pool_delete.c | 4 +- common/src/tx_block_pool_info_get.c | 4 +- common/src/tx_block_pool_initialize.c | 10 +- .../src/tx_block_pool_performance_info_get.c | 4 +- ...x_block_pool_performance_system_info_get.c | 4 +- common/src/tx_block_pool_prioritize.c | 4 +- common/src/tx_block_release.c | 4 +- common/src/tx_byte_allocate.c | 4 +- common/src/tx_byte_pool_cleanup.c | 4 +- common/src/tx_byte_pool_create.c | 4 +- common/src/tx_byte_pool_delete.c | 4 +- common/src/tx_byte_pool_info_get.c | 4 +- common/src/tx_byte_pool_initialize.c | 10 +- .../src/tx_byte_pool_performance_info_get.c | 4 +- ...tx_byte_pool_performance_system_info_get.c | 4 +- common/src/tx_byte_pool_prioritize.c | 4 +- common/src/tx_byte_pool_search.c | 4 +- common/src/tx_byte_release.c | 4 +- common/src/tx_event_flags_cleanup.c | 4 +- common/src/tx_event_flags_create.c | 4 +- common/src/tx_event_flags_delete.c | 4 +- common/src/tx_event_flags_get.c | 4 +- common/src/tx_event_flags_info_get.c | 4 +- common/src/tx_event_flags_initialize.c | 10 +- .../src/tx_event_flags_performance_info_get.c | 4 +- ..._event_flags_performance_system_info_get.c | 4 +- common/src/tx_event_flags_set.c | 4 +- common/src/tx_event_flags_set_notify.c | 4 +- common/src/tx_initialize_high_level.c | 4 +- common/src/tx_initialize_kernel_enter.c | 4 +- common/src/tx_initialize_kernel_setup.c | 4 +- common/src/tx_misra.c | 17 +- common/src/tx_mutex_cleanup.c | 8 +- common/src/tx_mutex_create.c | 4 +- common/src/tx_mutex_delete.c | 4 +- common/src/tx_mutex_get.c | 4 +- common/src/tx_mutex_info_get.c | 4 +- common/src/tx_mutex_initialize.c | 10 +- common/src/tx_mutex_performance_info_get.c | 4 +- .../tx_mutex_performance_system_info_get.c | 4 +- common/src/tx_mutex_prioritize.c | 4 +- common/src/tx_mutex_priority_change.c | 17 +- common/src/tx_mutex_put.c | 4 +- common/src/tx_queue_cleanup.c | 4 +- common/src/tx_queue_create.c | 4 +- common/src/tx_queue_delete.c | 4 +- common/src/tx_queue_flush.c | 4 +- common/src/tx_queue_front_send.c | 4 +- common/src/tx_queue_info_get.c | 4 +- common/src/tx_queue_initialize.c | 10 +- common/src/tx_queue_performance_info_get.c | 4 +- .../tx_queue_performance_system_info_get.c | 4 +- common/src/tx_queue_prioritize.c | 4 +- common/src/tx_queue_receive.c | 4 +- common/src/tx_queue_send.c | 4 +- common/src/tx_queue_send_notify.c | 4 +- common/src/tx_semaphore_ceiling_put.c | 4 +- common/src/tx_semaphore_cleanup.c | 4 +- common/src/tx_semaphore_create.c | 4 +- common/src/tx_semaphore_delete.c | 4 +- common/src/tx_semaphore_get.c | 4 +- common/src/tx_semaphore_info_get.c | 4 +- common/src/tx_semaphore_initialize.c | 10 +- .../src/tx_semaphore_performance_info_get.c | 4 +- ...tx_semaphore_performance_system_info_get.c | 4 +- common/src/tx_semaphore_prioritize.c | 4 +- common/src/tx_semaphore_put.c | 4 +- common/src/tx_semaphore_put_notify.c | 4 +- common/src/tx_thread_create.c | 14 +- common/src/tx_thread_delete.c | 4 +- common/src/tx_thread_entry_exit_notify.c | 4 +- common/src/tx_thread_identify.c | 4 +- common/src/tx_thread_info_get.c | 4 +- common/src/tx_thread_initialize.c | 4 +- common/src/tx_thread_performance_info_get.c | 4 +- .../tx_thread_performance_system_info_get.c | 4 +- common/src/tx_thread_preemption_change.c | 4 +- common/src/tx_thread_priority_change.c | 13 +- common/src/tx_thread_relinquish.c | 4 +- common/src/tx_thread_reset.c | 4 +- common/src/tx_thread_resume.c | 4 +- common/src/tx_thread_shell_entry.c | 4 +- common/src/tx_thread_sleep.c | 4 +- common/src/tx_thread_stack_analyze.c | 4 +- common/src/tx_thread_stack_error_handler.c | 7 +- common/src/tx_thread_stack_error_notify.c | 4 +- common/src/tx_thread_suspend.c | 4 +- common/src/tx_thread_system_preempt_check.c | 4 +- common/src/tx_thread_system_resume.c | 4 +- common/src/tx_thread_system_suspend.c | 4 +- common/src/tx_thread_terminate.c | 4 +- common/src/tx_thread_time_slice.c | 8 +- common/src/tx_thread_time_slice_change.c | 4 +- common/src/tx_thread_timeout.c | 4 +- common/src/tx_thread_wait_abort.c | 4 +- common/src/tx_time_get.c | 4 +- common/src/tx_time_set.c | 4 +- common/src/tx_timer_activate.c | 4 +- common/src/tx_timer_change.c | 4 +- common/src/tx_timer_create.c | 4 +- common/src/tx_timer_deactivate.c | 4 +- common/src/tx_timer_delete.c | 4 +- common/src/tx_timer_expiration_process.c | 8 +- common/src/tx_timer_info_get.c | 4 +- common/src/tx_timer_initialize.c | 4 +- common/src/tx_timer_performance_info_get.c | 4 +- .../tx_timer_performance_system_info_get.c | 4 +- common/src/tx_timer_system_activate.c | 8 +- common/src/tx_timer_system_deactivate.c | 4 +- common/src/tx_timer_thread_entry.c | 4 +- common/src/tx_trace_buffer_full_notify.c | 4 +- common/src/tx_trace_disable.c | 4 +- common/src/tx_trace_enable.c | 4 +- common/src/tx_trace_event_filter.c | 4 +- common/src/tx_trace_event_unfilter.c | 4 +- common/src/tx_trace_initialize.c | 4 +- common/src/tx_trace_interrupt_control.c | 4 +- common/src/tx_trace_isr_enter_insert.c | 4 +- common/src/tx_trace_isr_exit_insert.c | 4 +- common/src/tx_trace_object_register.c | 4 +- common/src/tx_trace_object_unregister.c | 4 +- common/src/tx_trace_user_event_insert.c | 4 +- common/src/txe_block_allocate.c | 4 +- common/src/txe_block_pool_create.c | 4 +- common/src/txe_block_pool_delete.c | 4 +- common/src/txe_block_pool_info_get.c | 4 +- common/src/txe_block_pool_prioritize.c | 4 +- common/src/txe_block_release.c | 4 +- common/src/txe_byte_allocate.c | 4 +- common/src/txe_byte_pool_create.c | 4 +- common/src/txe_byte_pool_delete.c | 4 +- common/src/txe_byte_pool_info_get.c | 4 +- common/src/txe_byte_pool_prioritize.c | 4 +- common/src/txe_byte_release.c | 4 +- common/src/txe_event_flags_create.c | 4 +- common/src/txe_event_flags_delete.c | 4 +- common/src/txe_event_flags_get.c | 4 +- common/src/txe_event_flags_info_get.c | 4 +- common/src/txe_event_flags_set.c | 4 +- common/src/txe_event_flags_set_notify.c | 4 +- common/src/txe_mutex_create.c | 4 +- common/src/txe_mutex_delete.c | 4 +- common/src/txe_mutex_get.c | 4 +- common/src/txe_mutex_info_get.c | 4 +- common/src/txe_mutex_prioritize.c | 4 +- common/src/txe_mutex_put.c | 4 +- common/src/txe_queue_create.c | 4 +- common/src/txe_queue_delete.c | 4 +- common/src/txe_queue_flush.c | 4 +- common/src/txe_queue_front_send.c | 4 +- common/src/txe_queue_info_get.c | 4 +- common/src/txe_queue_prioritize.c | 4 +- common/src/txe_queue_receive.c | 4 +- common/src/txe_queue_send.c | 4 +- common/src/txe_queue_send_notify.c | 4 +- common/src/txe_semaphore_ceiling_put.c | 4 +- common/src/txe_semaphore_create.c | 4 +- common/src/txe_semaphore_delete.c | 4 +- common/src/txe_semaphore_get.c | 4 +- common/src/txe_semaphore_info_get.c | 4 +- common/src/txe_semaphore_prioritize.c | 4 +- common/src/txe_semaphore_put.c | 4 +- common/src/txe_semaphore_put_notify.c | 4 +- common/src/txe_thread_create.c | 4 +- common/src/txe_thread_delete.c | 4 +- common/src/txe_thread_entry_exit_notify.c | 4 +- common/src/txe_thread_info_get.c | 4 +- common/src/txe_thread_preemption_change.c | 4 +- common/src/txe_thread_priority_change.c | 4 +- common/src/txe_thread_relinquish.c | 4 +- common/src/txe_thread_reset.c | 4 +- common/src/txe_thread_resume.c | 4 +- common/src/txe_thread_suspend.c | 4 +- common/src/txe_thread_terminate.c | 4 +- common/src/txe_thread_time_slice_change.c | 4 +- common/src/txe_thread_wait_abort.c | 4 +- common/src/txe_timer_activate.c | 4 +- common/src/txe_timer_change.c | 4 +- common/src/txe_timer_create.c | 4 +- common/src/txe_timer_deactivate.c | 4 +- common/src/txe_timer_delete.c | 4 +- common/src/txe_timer_info_get.c | 4 +- common_modules/inc/txm_module.h | 4 +- common_modules/inc/txm_module_user.h | 4 +- .../module_lib/src/txm_block_allocate.c | 4 +- .../module_lib/src/txm_block_pool_create.c | 4 +- .../module_lib/src/txm_block_pool_delete.c | 4 +- .../module_lib/src/txm_block_pool_info_get.c | 4 +- .../src/txm_block_pool_performance_info_get.c | 4 +- ...m_block_pool_performance_system_info_get.c | 4 +- .../src/txm_block_pool_prioritize.c | 4 +- .../module_lib/src/txm_block_release.c | 4 +- .../module_lib/src/txm_byte_allocate.c | 4 +- .../module_lib/src/txm_byte_pool_create.c | 4 +- .../module_lib/src/txm_byte_pool_delete.c | 4 +- .../module_lib/src/txm_byte_pool_info_get.c | 4 +- .../src/txm_byte_pool_performance_info_get.c | 4 +- ...xm_byte_pool_performance_system_info_get.c | 4 +- .../module_lib/src/txm_byte_pool_prioritize.c | 4 +- .../module_lib/src/txm_byte_release.c | 4 +- .../module_lib/src/txm_event_flags_create.c | 4 +- .../module_lib/src/txm_event_flags_delete.c | 4 +- .../module_lib/src/txm_event_flags_get.c | 4 +- .../module_lib/src/txm_event_flags_info_get.c | 4 +- .../txm_event_flags_performance_info_get.c | 4 +- ..._event_flags_performance_system_info_get.c | 4 +- .../module_lib/src/txm_event_flags_set.c | 4 +- .../src/txm_event_flags_set_notify.c | 4 +- .../src/txm_module_application_request.c | 4 +- ...txm_module_callback_request_thread_entry.c | 4 +- .../src/txm_module_object_allocate.c | 4 +- .../src/txm_module_object_deallocate.c | 4 +- .../src/txm_module_object_pointer_get.c | 4 +- .../txm_module_object_pointer_get_extended.c | 4 +- .../src/txm_module_thread_system_suspend.c | 4 +- .../module_lib/src/txm_mutex_create.c | 4 +- .../module_lib/src/txm_mutex_delete.c | 4 +- common_modules/module_lib/src/txm_mutex_get.c | 4 +- .../module_lib/src/txm_mutex_info_get.c | 4 +- .../src/txm_mutex_performance_info_get.c | 4 +- .../txm_mutex_performance_system_info_get.c | 4 +- .../module_lib/src/txm_mutex_prioritize.c | 4 +- common_modules/module_lib/src/txm_mutex_put.c | 4 +- .../module_lib/src/txm_queue_create.c | 4 +- .../module_lib/src/txm_queue_delete.c | 4 +- .../module_lib/src/txm_queue_flush.c | 4 +- .../module_lib/src/txm_queue_front_send.c | 4 +- .../module_lib/src/txm_queue_info_get.c | 4 +- .../src/txm_queue_performance_info_get.c | 4 +- .../txm_queue_performance_system_info_get.c | 4 +- .../module_lib/src/txm_queue_prioritize.c | 4 +- .../module_lib/src/txm_queue_receive.c | 4 +- .../module_lib/src/txm_queue_send.c | 4 +- .../module_lib/src/txm_queue_send_notify.c | 4 +- .../src/txm_semaphore_ceiling_put.c | 4 +- .../module_lib/src/txm_semaphore_create.c | 4 +- .../module_lib/src/txm_semaphore_delete.c | 4 +- .../module_lib/src/txm_semaphore_get.c | 4 +- .../module_lib/src/txm_semaphore_info_get.c | 4 +- .../src/txm_semaphore_performance_info_get.c | 4 +- ...xm_semaphore_performance_system_info_get.c | 4 +- .../module_lib/src/txm_semaphore_prioritize.c | 4 +- .../module_lib/src/txm_semaphore_put.c | 4 +- .../module_lib/src/txm_semaphore_put_notify.c | 4 +- .../module_lib/src/txm_thread_create.c | 4 +- .../module_lib/src/txm_thread_delete.c | 4 +- .../src/txm_thread_entry_exit_notify.c | 4 +- .../module_lib/src/txm_thread_identify.c | 4 +- .../module_lib/src/txm_thread_info_get.c | 4 +- .../src/txm_thread_interrupt_control.c | 4 +- .../src/txm_thread_performance_info_get.c | 4 +- .../txm_thread_performance_system_info_get.c | 4 +- .../src/txm_thread_preemption_change.c | 4 +- .../src/txm_thread_priority_change.c | 4 +- .../module_lib/src/txm_thread_relinquish.c | 4 +- .../module_lib/src/txm_thread_reset.c | 4 +- .../module_lib/src/txm_thread_resume.c | 4 +- .../module_lib/src/txm_thread_sleep.c | 4 +- .../src/txm_thread_stack_error_notify.c | 4 +- .../module_lib/src/txm_thread_suspend.c | 4 +- .../module_lib/src/txm_thread_terminate.c | 4 +- .../src/txm_thread_time_slice_change.c | 4 +- .../module_lib/src/txm_thread_wait_abort.c | 4 +- common_modules/module_lib/src/txm_time_get.c | 4 +- common_modules/module_lib/src/txm_time_set.c | 4 +- .../module_lib/src/txm_timer_activate.c | 4 +- .../module_lib/src/txm_timer_change.c | 4 +- .../module_lib/src/txm_timer_create.c | 4 +- .../module_lib/src/txm_timer_deactivate.c | 4 +- .../module_lib/src/txm_timer_delete.c | 4 +- .../module_lib/src/txm_timer_info_get.c | 4 +- .../src/txm_timer_performance_info_get.c | 4 +- .../txm_timer_performance_system_info_get.c | 4 +- .../src/txm_trace_buffer_full_notify.c | 4 +- .../module_lib/src/txm_trace_disable.c | 4 +- .../module_lib/src/txm_trace_enable.c | 4 +- .../module_lib/src/txm_trace_event_filter.c | 4 +- .../module_lib/src/txm_trace_event_unfilter.c | 4 +- .../src/txm_trace_interrupt_control.c | 4 +- .../src/txm_trace_isr_enter_insert.c | 4 +- .../src/txm_trace_isr_exit_insert.c | 4 +- .../src/txm_trace_user_event_insert.c | 4 +- .../inc/txm_module_manager_util.h | 81 +- .../txm_module_manager_application_request.c | 4 +- .../src/txm_module_manager_callback_request.c | 4 +- ...le_manager_event_flags_notify_trampoline.c | 4 +- .../src/txm_module_manager_file_load.c | 4 +- .../src/txm_module_manager_in_place_load.c | 4 +- .../src/txm_module_manager_initialize.c | 4 +- .../src/txm_module_manager_internal_load.c | 4 +- .../src/txm_module_manager_kernel_dispatch.c | 4 +- ...dule_manager_maximum_module_priority_set.c | 4 +- .../src/txm_module_manager_memory_load.c | 4 +- .../src/txm_module_manager_object_allocate.c | 4 +- .../txm_module_manager_object_deallocate.c | 4 +- .../txm_module_manager_object_pointer_get.c | 4 +- ...dule_manager_object_pointer_get_extended.c | 4 +- .../txm_module_manager_object_pool_create.c | 4 +- .../src/txm_module_manager_properties_get.c | 4 +- ...m_module_manager_queue_notify_trampoline.c | 4 +- ...dule_manager_semaphore_notify_trampoline.c | 4 +- .../src/txm_module_manager_start.c | 4 +- .../src/txm_module_manager_stop.c | 4 +- .../src/txm_module_manager_thread_create.c | 4 +- ..._module_manager_thread_notify_trampoline.c | 4 +- .../src/txm_module_manager_thread_reset.c | 4 +- ...m_module_manager_timer_notify_trampoline.c | 4 +- .../src/txm_module_manager_unload.c | 4 +- .../src/txm_module_manager_util.c | 20 +- common_smp/inc/tx_api.h | 16 +- common_smp/inc/tx_block_pool.h | 4 +- common_smp/inc/tx_byte_pool.h | 4 +- common_smp/inc/tx_event_flags.h | 4 +- common_smp/inc/tx_initialize.h | 4 +- common_smp/inc/tx_mutex.h | 4 +- common_smp/inc/tx_queue.h | 4 +- common_smp/inc/tx_semaphore.h | 4 +- common_smp/inc/tx_thread.h | 4 +- common_smp/inc/tx_timer.h | 4 +- common_smp/inc/tx_trace.h | 6 +- common_smp/inc/tx_user_sample.h | 257 + common_smp/src/tx_block_allocate.c | 4 +- common_smp/src/tx_block_pool_cleanup.c | 4 +- common_smp/src/tx_block_pool_create.c | 4 +- common_smp/src/tx_block_pool_delete.c | 4 +- common_smp/src/tx_block_pool_info_get.c | 4 +- common_smp/src/tx_block_pool_initialize.c | 7 +- .../src/tx_block_pool_performance_info_get.c | 4 +- ...x_block_pool_performance_system_info_get.c | 4 +- common_smp/src/tx_block_pool_prioritize.c | 4 +- common_smp/src/tx_block_release.c | 4 +- common_smp/src/tx_byte_allocate.c | 4 +- common_smp/src/tx_byte_pool_cleanup.c | 4 +- common_smp/src/tx_byte_pool_create.c | 4 +- common_smp/src/tx_byte_pool_delete.c | 4 +- common_smp/src/tx_byte_pool_info_get.c | 4 +- common_smp/src/tx_byte_pool_initialize.c | 7 +- .../src/tx_byte_pool_performance_info_get.c | 4 +- ...tx_byte_pool_performance_system_info_get.c | 4 +- common_smp/src/tx_byte_pool_prioritize.c | 4 +- common_smp/src/tx_byte_pool_search.c | 4 +- common_smp/src/tx_byte_release.c | 4 +- common_smp/src/tx_event_flags_cleanup.c | 4 +- common_smp/src/tx_event_flags_create.c | 4 +- common_smp/src/tx_event_flags_delete.c | 4 +- common_smp/src/tx_event_flags_get.c | 4 +- common_smp/src/tx_event_flags_info_get.c | 4 +- common_smp/src/tx_event_flags_initialize.c | 7 +- .../src/tx_event_flags_performance_info_get.c | 4 +- ..._event_flags_performance_system_info_get.c | 4 +- common_smp/src/tx_event_flags_set.c | 4 +- common_smp/src/tx_event_flags_set_notify.c | 4 +- common_smp/src/tx_initialize_high_level.c | 4 +- common_smp/src/tx_initialize_kernel_enter.c | 4 +- common_smp/src/tx_initialize_kernel_setup.c | 4 +- common_smp/src/tx_misra.c | 4 +- common_smp/src/tx_mutex_cleanup.c | 8 +- common_smp/src/tx_mutex_create.c | 4 +- common_smp/src/tx_mutex_delete.c | 4 +- common_smp/src/tx_mutex_get.c | 4 +- common_smp/src/tx_mutex_info_get.c | 4 +- common_smp/src/tx_mutex_initialize.c | 7 +- .../src/tx_mutex_performance_info_get.c | 4 +- .../tx_mutex_performance_system_info_get.c | 4 +- common_smp/src/tx_mutex_prioritize.c | 4 +- common_smp/src/tx_mutex_priority_change.c | 35 +- common_smp/src/tx_mutex_put.c | 4 +- common_smp/src/tx_queue_cleanup.c | 4 +- common_smp/src/tx_queue_create.c | 4 +- common_smp/src/tx_queue_delete.c | 4 +- common_smp/src/tx_queue_flush.c | 4 +- common_smp/src/tx_queue_front_send.c | 4 +- common_smp/src/tx_queue_info_get.c | 4 +- common_smp/src/tx_queue_initialize.c | 7 +- .../src/tx_queue_performance_info_get.c | 4 +- .../tx_queue_performance_system_info_get.c | 4 +- common_smp/src/tx_queue_prioritize.c | 4 +- common_smp/src/tx_queue_receive.c | 4 +- common_smp/src/tx_queue_send.c | 4 +- common_smp/src/tx_queue_send_notify.c | 4 +- common_smp/src/tx_semaphore_ceiling_put.c | 4 +- common_smp/src/tx_semaphore_cleanup.c | 4 +- common_smp/src/tx_semaphore_create.c | 4 +- common_smp/src/tx_semaphore_delete.c | 4 +- common_smp/src/tx_semaphore_get.c | 4 +- common_smp/src/tx_semaphore_info_get.c | 4 +- common_smp/src/tx_semaphore_initialize.c | 7 +- .../src/tx_semaphore_performance_info_get.c | 4 +- ...tx_semaphore_performance_system_info_get.c | 4 +- common_smp/src/tx_semaphore_prioritize.c | 4 +- common_smp/src/tx_semaphore_put.c | 4 +- common_smp/src/tx_semaphore_put_notify.c | 4 +- common_smp/src/tx_thread_create.c | 61 +- common_smp/src/tx_thread_delete.c | 4 +- common_smp/src/tx_thread_entry_exit_notify.c | 4 +- common_smp/src/tx_thread_identify.c | 4 +- common_smp/src/tx_thread_info_get.c | 4 +- common_smp/src/tx_thread_initialize.c | 4 +- .../src/tx_thread_performance_info_get.c | 4 +- .../tx_thread_performance_system_info_get.c | 4 +- common_smp/src/tx_thread_preemption_change.c | 14 +- common_smp/src/tx_thread_priority_change.c | 35 +- common_smp/src/tx_thread_relinquish.c | 6 +- common_smp/src/tx_thread_reset.c | 4 +- common_smp/src/tx_thread_resume.c | 4 +- common_smp/src/tx_thread_shell_entry.c | 4 +- common_smp/src/tx_thread_sleep.c | 4 +- common_smp/src/tx_thread_smp_core_exclude.c | 4 +- .../src/tx_thread_smp_core_exclude_get.c | 4 +- .../src/tx_thread_smp_current_state_set.c | 4 +- .../src/tx_thread_smp_debug_entry_insert.c | 4 +- .../src/tx_thread_smp_high_level_initialize.c | 4 +- .../tx_thread_smp_rebalance_execute_list.c | 4 +- common_smp/src/tx_thread_stack_analyze.c | 4 +- .../src/tx_thread_stack_error_handler.c | 6 +- common_smp/src/tx_thread_stack_error_notify.c | 4 +- common_smp/src/tx_thread_suspend.c | 4 +- .../src/tx_thread_system_preempt_check.c | 4 +- common_smp/src/tx_thread_system_resume.c | 4 +- common_smp/src/tx_thread_system_suspend.c | 69 +- common_smp/src/tx_thread_terminate.c | 4 +- common_smp/src/tx_thread_time_slice.c | 4 +- common_smp/src/tx_thread_time_slice_change.c | 4 +- common_smp/src/tx_thread_timeout.c | 4 +- common_smp/src/tx_thread_wait_abort.c | 4 +- common_smp/src/tx_time_get.c | 6 +- common_smp/src/tx_time_set.c | 4 +- common_smp/src/tx_timer_activate.c | 4 +- common_smp/src/tx_timer_change.c | 4 +- common_smp/src/tx_timer_create.c | 4 +- common_smp/src/tx_timer_deactivate.c | 4 +- common_smp/src/tx_timer_delete.c | 4 +- common_smp/src/tx_timer_expiration_process.c | 4 +- common_smp/src/tx_timer_info_get.c | 4 +- common_smp/src/tx_timer_initialize.c | 4 +- .../src/tx_timer_performance_info_get.c | 4 +- .../tx_timer_performance_system_info_get.c | 4 +- common_smp/src/tx_timer_smp_core_exclude.c | 4 +- .../src/tx_timer_smp_core_exclude_get.c | 4 +- common_smp/src/tx_timer_system_activate.c | 4 +- common_smp/src/tx_timer_system_deactivate.c | 4 +- common_smp/src/tx_timer_thread_entry.c | 4 +- common_smp/src/tx_trace_buffer_full_notify.c | 4 +- common_smp/src/tx_trace_disable.c | 4 +- common_smp/src/tx_trace_enable.c | 4 +- common_smp/src/tx_trace_event_filter.c | 4 +- common_smp/src/tx_trace_event_unfilter.c | 4 +- common_smp/src/tx_trace_initialize.c | 4 +- common_smp/src/tx_trace_interrupt_control.c | 4 +- common_smp/src/tx_trace_isr_enter_insert.c | 4 +- common_smp/src/tx_trace_isr_exit_insert.c | 4 +- common_smp/src/tx_trace_object_register.c | 4 +- common_smp/src/tx_trace_object_unregister.c | 4 +- common_smp/src/tx_trace_user_event_insert.c | 4 +- common_smp/src/txe_block_allocate.c | 4 +- common_smp/src/txe_block_pool_create.c | 4 +- common_smp/src/txe_block_pool_delete.c | 4 +- common_smp/src/txe_block_pool_info_get.c | 4 +- common_smp/src/txe_block_pool_prioritize.c | 4 +- common_smp/src/txe_block_release.c | 4 +- common_smp/src/txe_byte_allocate.c | 4 +- common_smp/src/txe_byte_pool_create.c | 4 +- common_smp/src/txe_byte_pool_delete.c | 4 +- common_smp/src/txe_byte_pool_info_get.c | 4 +- common_smp/src/txe_byte_pool_prioritize.c | 4 +- common_smp/src/txe_byte_release.c | 4 +- common_smp/src/txe_event_flags_create.c | 4 +- common_smp/src/txe_event_flags_delete.c | 4 +- common_smp/src/txe_event_flags_get.c | 4 +- common_smp/src/txe_event_flags_info_get.c | 4 +- common_smp/src/txe_event_flags_set.c | 4 +- common_smp/src/txe_event_flags_set_notify.c | 4 +- common_smp/src/txe_mutex_create.c | 4 +- common_smp/src/txe_mutex_delete.c | 4 +- common_smp/src/txe_mutex_get.c | 4 +- common_smp/src/txe_mutex_info_get.c | 4 +- common_smp/src/txe_mutex_prioritize.c | 4 +- common_smp/src/txe_mutex_put.c | 4 +- common_smp/src/txe_queue_create.c | 4 +- common_smp/src/txe_queue_delete.c | 4 +- common_smp/src/txe_queue_flush.c | 4 +- common_smp/src/txe_queue_front_send.c | 4 +- common_smp/src/txe_queue_info_get.c | 4 +- common_smp/src/txe_queue_prioritize.c | 4 +- common_smp/src/txe_queue_receive.c | 4 +- common_smp/src/txe_queue_send.c | 4 +- common_smp/src/txe_queue_send_notify.c | 4 +- common_smp/src/txe_semaphore_ceiling_put.c | 4 +- common_smp/src/txe_semaphore_create.c | 4 +- common_smp/src/txe_semaphore_delete.c | 4 +- common_smp/src/txe_semaphore_get.c | 4 +- common_smp/src/txe_semaphore_info_get.c | 4 +- common_smp/src/txe_semaphore_prioritize.c | 4 +- common_smp/src/txe_semaphore_put.c | 4 +- common_smp/src/txe_semaphore_put_notify.c | 4 +- common_smp/src/txe_thread_create.c | 4 +- common_smp/src/txe_thread_delete.c | 4 +- common_smp/src/txe_thread_entry_exit_notify.c | 4 +- common_smp/src/txe_thread_info_get.c | 4 +- common_smp/src/txe_thread_preemption_change.c | 4 +- common_smp/src/txe_thread_priority_change.c | 4 +- common_smp/src/txe_thread_relinquish.c | 4 +- common_smp/src/txe_thread_reset.c | 4 +- common_smp/src/txe_thread_resume.c | 4 +- common_smp/src/txe_thread_suspend.c | 4 +- common_smp/src/txe_thread_terminate.c | 4 +- common_smp/src/txe_thread_time_slice_change.c | 4 +- common_smp/src/txe_thread_wait_abort.c | 4 +- common_smp/src/txe_timer_activate.c | 4 +- common_smp/src/txe_timer_change.c | 4 +- common_smp/src/txe_timer_create.c | 4 +- common_smp/src/txe_timer_deactivate.c | 4 +- common_smp/src/txe_timer_delete.c | 4 +- common_smp/src/txe_timer_info_get.c | 4 +- .../sample_threadx/tx_initialize_low_level.s | 4 +- ports/arc_em/metaware/inc/tx_port.h | 6 +- ports/arc_em/metaware/readme_threadx.txt | 2 +- .../metaware/src/tx_initialize_low_level.s | 4 +- .../metaware/src/tx_thread_context_restore.s | 4 +- .../metaware/src/tx_thread_context_save.s | 4 +- .../src/tx_thread_interrupt_control.s | 4 +- .../arc_em/metaware/src/tx_thread_schedule.s | 4 +- .../metaware/src/tx_thread_stack_build.s | 4 +- .../metaware/src/tx_thread_system_return.s | 4 +- .../arc_em/metaware/src/tx_timer_interrupt.s | 4 +- .../sample_threadx/tx_initialize_low_level.s | 4 +- ports/arc_hs/metaware/inc/tx_port.h | 6 +- ports/arc_hs/metaware/readme_threadx.txt | 2 +- .../src/tx_initialize_fast_interrupt_setup.s | 4 +- .../src/tx_thread_context_fast_restore.s | 4 +- .../src/tx_thread_context_fast_save.s | 4 +- .../metaware/src/tx_thread_context_restore.s | 4 +- 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ports/arm11/gnu/src/tx_thread_schedule.S | 4 +- ports/arm11/gnu/src/tx_thread_stack_build.S | 4 +- ports/arm11/gnu/src/tx_thread_system_return.S | 4 +- .../gnu/src/tx_thread_vectored_context_save.S | 4 +- ports/arm11/gnu/src/tx_timer_interrupt.S | 4 +- .../example_build/tx_initialize_low_level.s | 32 +- ports/arm11/iar/inc/tx_port.h | 37 +- ports/arm11/iar/readme_threadx.txt | 2 +- ports/arm11/iar/src/tx_iar.c | 26 +- .../arm11/iar/src/tx_thread_context_restore.s | 33 +- ports/arm11/iar/src/tx_thread_context_save.s | 33 +- .../iar/src/tx_thread_fiq_context_restore.s | 33 +- .../iar/src/tx_thread_fiq_context_save.s | 34 +- .../arm11/iar/src/tx_thread_fiq_nesting_end.s | 32 +- .../iar/src/tx_thread_fiq_nesting_start.s | 32 +- .../iar/src/tx_thread_interrupt_control.s | 32 +- .../iar/src/tx_thread_interrupt_disable.s | 32 +- .../iar/src/tx_thread_interrupt_restore.s | 32 +- .../arm11/iar/src/tx_thread_irq_nesting_end.s | 32 +- .../iar/src/tx_thread_irq_nesting_start.s | 32 +- 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ports_smp/cortex_a9_smp/gnu/src/tx_thread_context_restore.S create mode 100644 ports_smp/cortex_a9_smp/gnu/src/tx_thread_context_save.S create mode 100644 ports_smp/cortex_a9_smp/gnu/src/tx_thread_interrupt_control.S create mode 100644 ports_smp/cortex_a9_smp/gnu/src/tx_thread_interrupt_disable.S create mode 100644 ports_smp/cortex_a9_smp/gnu/src/tx_thread_interrupt_restore.S create mode 100644 ports_smp/cortex_a9_smp/gnu/src/tx_thread_irq_nesting_end.S create mode 100644 ports_smp/cortex_a9_smp/gnu/src/tx_thread_irq_nesting_start.S create mode 100644 ports_smp/cortex_a9_smp/gnu/src/tx_thread_schedule.S create mode 100644 ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_core_get.S create mode 100644 ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_core_preempt.S create mode 100644 ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_current_state_get.S create mode 100644 ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_current_thread_get.S create mode 100644 ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_initialize_wait.S create mode 100644 ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_low_level_initialize.S create mode 100644 ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_protect.S create mode 100644 ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h create mode 100644 ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_time_get.S create mode 100644 ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_unprotect.S create mode 100644 ports_smp/cortex_a9_smp/gnu/src/tx_thread_stack_build.S create mode 100644 ports_smp/cortex_a9_smp/gnu/src/tx_thread_system_return.S create mode 100644 ports_smp/cortex_a9_smp/gnu/src/tx_thread_vectored_context_save.S create mode 100644 ports_smp/cortex_a9_smp/gnu/src/tx_timer_interrupt.S create mode 100644 ports_smp/linux/gnu/example_build/file_list.mk create mode 100644 ports_smp/linux/gnu/example_build/sample_threadx.c create mode 100644 ports_smp/linux/gnu/inc/tx_port.h create mode 100644 ports_smp/linux/gnu/readme_threadx.txt create mode 100644 ports_smp/linux/gnu/src/tx_initialize_low_level.c create mode 100644 ports_smp/linux/gnu/src/tx_thread_context_restore.c create mode 100644 ports_smp/linux/gnu/src/tx_thread_context_save.c create mode 100644 ports_smp/linux/gnu/src/tx_thread_interrupt_control.c create mode 100644 ports_smp/linux/gnu/src/tx_thread_schedule.c create mode 100644 ports_smp/linux/gnu/src/tx_thread_smp_core_get.c create mode 100644 ports_smp/linux/gnu/src/tx_thread_smp_core_preempt.c create mode 100644 ports_smp/linux/gnu/src/tx_thread_smp_current_state_get.c create mode 100644 ports_smp/linux/gnu/src/tx_thread_smp_current_thread_get.c create mode 100644 ports_smp/linux/gnu/src/tx_thread_smp_initialize_wait.c create mode 100644 ports_smp/linux/gnu/src/tx_thread_smp_low_level_initialize.c create mode 100644 ports_smp/linux/gnu/src/tx_thread_smp_protect.c create mode 100644 ports_smp/linux/gnu/src/tx_thread_smp_time_get.c create mode 100644 ports_smp/linux/gnu/src/tx_thread_smp_unprotect.c create mode 100644 ports_smp/linux/gnu/src/tx_thread_stack_build.c create mode 100644 ports_smp/linux/gnu/src/tx_thread_system_return.c create mode 100644 ports_smp/linux/gnu/src/tx_timer_interrupt.c diff --git a/LICENSED-HARDWARE.txt b/LICENSED-HARDWARE.txt index fd9627c2..93a21d08 100644 --- a/LICENSED-HARDWARE.txt +++ b/LICENSED-HARDWARE.txt @@ -25,4 +25,4 @@ Renesas: -------------------------------------------------------------------------------- -More coming soon. Please check back frequently for updates. +More coming soon. Please check back frequently for updates. \ No newline at end of file diff --git a/README.md b/README.md index e74975a3..6f75fe49 100644 --- a/README.md +++ b/README.md @@ -102,10 +102,9 @@ Professional support plans (https://azure.microsoft.com/en-us/support/options/) The following are references to additional Azure RTOS and Azure IoT in general: | | | |---|---| -| TraceX Installer | https://aka.ms/azrtos-tracex-installer | | Azure RTOS Documenation and Guides: | https://docs.microsoft.com/azure/rtos | | Azure RTOS Website: | https://azure.microsoft.com/services/rtos/ | | Azure RTOS Sales Questions: | https://azure-rtos.ms-iot-contact.com/ | | For technical questions check out Microsoft Q/A for Azure IoT: | https://aka.ms/QnA/azure-rtos | | Internet of Things Show for latest announcements and online training: | https://aka.ms/iotshow | -| IoT Tech Community: | https://aka.ms/community/azure-rtos | +| IoT Tech Community: | https://aka.ms/community/azure-rtos | \ No newline at end of file diff --git a/cmake/linux.cmake b/cmake/linux.cmake new file mode 100644 index 00000000..192425c6 --- /dev/null +++ b/cmake/linux.cmake @@ -0,0 +1,31 @@ +set(CMAKE_SYSTEM_NAME Linux) +set(CMAKE_SYSTEM_PROCESSOR x86_64) + +set(CMAKE_C_COMPILER gcc) +set(CMAKE_CXX_COMPILER g++) +set(AS as) +set(AR ar) +set(OBJCOPY objcopy) +set(OBJDUMP objdump) +set(SIZE size) + +set(THREADX_ARCH "linux") +set(THREADX_TOOLCHAIN "gnu") + +set(LINUX_FLAGS "-g -pthread") + +set(CMAKE_C_FLAGS "${LINUX_FLAGS} " CACHE INTERNAL "c compiler flags") +set(CMAKE_CXX_FLAGS "${LINUX_FLAGS} -fno-rtti -fno-exceptions" CACHE INTERNAL "cxx compiler flags") +set(CMAKE_ASM_FLAGS "${LINUX_FLAGS} -x assembler-with-cpp" CACHE INTERNAL "asm compiler flags") +set(CMAKE_EXE_LINKER_FLAGS "${LINUX_FLAGS} ${LD_FLAGS} -Wl,--gc-sections" CACHE INTERNAL "exe link flags") + +SET(CMAKE_C_FLAGS_DEBUG "-Og -g -ggdb3" CACHE INTERNAL "c debug compiler flags") +SET(CMAKE_CXX_FLAGS_DEBUG "-Og -g -ggdb3" CACHE INTERNAL "cxx debug compiler flags") +SET(CMAKE_ASM_FLAGS_DEBUG "-g -ggdb3" CACHE INTERNAL "asm debug compiler flags") + +SET(CMAKE_C_FLAGS_RELEASE "-O3" CACHE INTERNAL "c release compiler flags") +SET(CMAKE_CXX_FLAGS_RELEASE "-O3" CACHE INTERNAL "cxx release compiler flags") +SET(CMAKE_ASM_FLAGS_RELEASE "" CACHE INTERNAL "asm release compiler flags") + +# this makes the test compiles use static library option so that we don't need to pre-set linker flags and scripts +set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) diff --git a/cmake/win32.cmake b/cmake/win32.cmake new file mode 100644 index 00000000..974107ad --- /dev/null +++ b/cmake/win32.cmake @@ -0,0 +1,15 @@ +set(CMAKE_SYSTEM_NAME Windows) +set(CMAKE_SYSTEM_PROCESSOR x86_64) + +set(THREADX_ARCH "win32") +set(THREADX_TOOLCHAIN "vs_2019") + +set(WIN32_FLAGS "") + +set(CMAKE_C_FLAGS "${WIN32_FLAGS} " CACHE INTERNAL "c compiler flags") +set(CMAKE_CXX_FLAGS "${WIN32_FLAGS} -fno-rtti -fno-exceptions" CACHE INTERNAL "cxx compiler flags") +set(CMAKE_ASM_FLAGS "${WIN32_FLAGS} -x assembler-with-cpp" CACHE INTERNAL "asm compiler flags") +set(CMAKE_EXE_LINKER_FLAGS "${WIN32_FLAGS} ${LD_FLAGS}" CACHE INTERNAL "exe link flags") + +# this makes the test compiles use static library option so that we don't need to pre-set linker flags and scripts +set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) diff --git a/common/inc/tx_api.h b/common/inc/tx_api.h index 7aa923b3..2397552d 100644 --- a/common/inc/tx_api.h +++ b/common/inc/tx_api.h @@ -26,7 +26,7 @@ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ /* tx_api.h PORTABLE C */ -/* 6.0.2 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -44,12 +44,13 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 06-30-2020 William E. Lamie Modified comment(s), and */ +/* 09-30-2020 William E. Lamie Modified comment(s), and */ /* updated product constants, */ -/* resulting in version 6.0.1 */ -/* 08-14-2020 Scott Larson Modified comment(s), and */ -/* updated product constants, */ -/* resulting in version 6.0.2 */ +/* added new thread execution */ +/* state TX_PRIORITY_CHANGE, */ +/* added macros for casting */ +/* pointers to ALIGN_TYPE, */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ @@ -81,12 +82,13 @@ extern "C" { #define AZURE_RTOS_THREADX #define THREADX_MAJOR_VERSION 6 -#define THREADX_MINOR_VERSION 0 -#define THREADX_PATCH_VERSION 2 +#define THREADX_MINOR_VERSION 1 +#define THREADX_PATCH_VERSION 0 /* Define the following symbol for backward compatibility */ #define EL_PRODUCT_THREADX + /* API input parameters and general constants. */ #define TX_NO_WAIT ((ULONG) 0) @@ -135,6 +137,7 @@ extern "C" { #define TX_FILE ((UINT) 11) #define TX_TCP_IP ((UINT) 12) #define TX_MUTEX_SUSP ((UINT) 13) +#define TX_PRIORITY_CHANGE ((UINT) 14) /* API return values. */ @@ -1883,6 +1886,8 @@ VOID _tx_misra_thread_entry_exit_notify_not_used(VOID (*threa #define TX_ULONG_POINTER_DIF(a,b) ((ULONG)(((ULONG *) (a)) - ((ULONG *) (b)))) #define TX_POINTER_TO_ULONG_CONVERT(a) ((ULONG) ((VOID *) (a))) #define TX_ULONG_TO_POINTER_CONVERT(a) ((VOID *) ((ULONG) (a))) +#define TX_POINTER_TO_ALIGN_TYPE_CONVERT(a) ((ALIGN_TYPE) ((VOID *) (a))) +#define TX_ALIGN_TYPE_TO_POINTER_CONVERT(a) ((VOID *) ((ALIGN_TYPE) (a))) #define TX_TIMER_POINTER_DIF(a,b) ((ULONG)(((TX_TIMER_INTERNAL **) (a)) - ((TX_TIMER_INTERNAL **) (b)))) #define TX_TIMER_POINTER_ADD(a,b) (((TX_TIMER_INTERNAL **) (a)) + ((ULONG) (b))) #define TX_USER_TIMER_POINTER_GET(a,b) { \ diff --git a/common/inc/tx_block_pool.h b/common/inc/tx_block_pool.h index 1000c4b6..2f72cf81 100644 --- a/common/inc/tx_block_pool.h +++ b/common/inc/tx_block_pool.h @@ -26,7 +26,7 @@ /* COMPONENT DEFINITION RELEASE */ /* */ /* tx_block_pool.h PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -42,6 +42,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ diff --git a/common/inc/tx_byte_pool.h b/common/inc/tx_byte_pool.h index 408a0924..35320931 100644 --- a/common/inc/tx_byte_pool.h +++ b/common/inc/tx_byte_pool.h @@ -26,7 +26,7 @@ /* COMPONENT DEFINITION RELEASE */ /* */ /* tx_byte_pool.h PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -42,6 +42,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ diff --git a/common/inc/tx_event_flags.h b/common/inc/tx_event_flags.h index c3fa8e44..dceb17eb 100644 --- a/common/inc/tx_event_flags.h +++ b/common/inc/tx_event_flags.h @@ -26,7 +26,7 @@ /* COMPONENT DEFINITION RELEASE */ /* */ /* tx_event_flags.h PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -42,6 +42,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ diff --git a/common/inc/tx_initialize.h b/common/inc/tx_initialize.h index f41eee48..79e5761d 100644 --- a/common/inc/tx_initialize.h +++ b/common/inc/tx_initialize.h @@ -26,7 +26,7 @@ /* COMPONENT DEFINITION RELEASE */ /* */ /* tx_initialize.h PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -42,6 +42,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ diff --git a/common/inc/tx_mutex.h b/common/inc/tx_mutex.h index 4ee63e55..8d2b0ab5 100644 --- a/common/inc/tx_mutex.h +++ b/common/inc/tx_mutex.h @@ -26,7 +26,7 @@ /* COMPONENT DEFINITION RELEASE */ /* */ /* tx_mutex.h PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -42,6 +42,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ diff --git a/common/inc/tx_queue.h b/common/inc/tx_queue.h index d6997cbc..d74ce797 100644 --- a/common/inc/tx_queue.h +++ b/common/inc/tx_queue.h @@ -26,7 +26,7 @@ /* COMPONENT DEFINITION RELEASE */ /* */ /* tx_queue.h PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -42,6 +42,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ diff --git a/common/inc/tx_semaphore.h b/common/inc/tx_semaphore.h index 78a2f78f..3a50fa0f 100644 --- a/common/inc/tx_semaphore.h +++ b/common/inc/tx_semaphore.h @@ -26,7 +26,7 @@ /* COMPONENT DEFINITION RELEASE */ /* */ /* tx_semaphore.h PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -42,6 +42,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ diff --git a/common/inc/tx_thread.h b/common/inc/tx_thread.h index f7e462b7..7ea159c3 100644 --- a/common/inc/tx_thread.h +++ b/common/inc/tx_thread.h @@ -26,7 +26,7 @@ /* COMPONENT DEFINITION RELEASE */ /* */ /* tx_thread.h PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -42,6 +42,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ diff --git a/common/inc/tx_timer.h b/common/inc/tx_timer.h index 9d0522c9..ebd4f55c 100644 --- a/common/inc/tx_timer.h +++ b/common/inc/tx_timer.h @@ -26,7 +26,7 @@ /* COMPONENT DEFINITION RELEASE */ /* */ /* tx_timer.h PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -42,6 +42,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ diff --git a/common/inc/tx_trace.h b/common/inc/tx_trace.h index 868e7f99..03e7d134 100644 --- a/common/inc/tx_trace.h +++ b/common/inc/tx_trace.h @@ -25,7 +25,7 @@ /* COMPONENT DEFINITION RELEASE */ /* */ /* tx_trace.h PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -41,6 +41,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ diff --git a/common/inc/tx_user_sample.h b/common/inc/tx_user_sample.h index 8a2e5166..113d189f 100644 --- a/common/inc/tx_user_sample.h +++ b/common/inc/tx_user_sample.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_user.h PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -45,6 +45,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ @@ -153,7 +155,7 @@ processing when not needed. The user will also have to comment out the call to tx_timer_interrupt, which is typically made from assembly language in tx_initialize_low_level. Note: if TX_NO_TIMER is used, the define TX_TIMER_PROCESS_IN_ISR - must also be used. */ + must also be used and tx_timer_initialize must be removed from ThreadX library. */ /* #define TX_NO_TIMER diff --git a/common/src/tx_block_allocate.c b/common/src/tx_block_allocate.c index 1035e681..d5731c77 100644 --- a/common/src/tx_block_allocate.c +++ b/common/src/tx_block_allocate.c @@ -38,7 +38,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_block_allocate PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -73,6 +73,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_block_allocate(TX_BLOCK_POOL *pool_ptr, VOID **block_ptr, ULONG wait_option) diff --git a/common/src/tx_block_pool_cleanup.c b/common/src/tx_block_pool_cleanup.c index 6578e5c5..4feacb8f 100644 --- a/common/src/tx_block_pool_cleanup.c +++ b/common/src/tx_block_pool_cleanup.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_block_pool_cleanup PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -71,6 +71,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ VOID _tx_block_pool_cleanup(TX_THREAD *thread_ptr, ULONG suspension_sequence) diff --git a/common/src/tx_block_pool_create.c b/common/src/tx_block_pool_create.c index 4d74cc03..be222888 100644 --- a/common/src/tx_block_pool_create.c +++ b/common/src/tx_block_pool_create.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_block_pool_create PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,6 +70,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_block_pool_create(TX_BLOCK_POOL *pool_ptr, CHAR *name_ptr, ULONG block_size, diff --git a/common/src/tx_block_pool_delete.c b/common/src/tx_block_pool_delete.c index 8e52e444..72a080f0 100644 --- a/common/src/tx_block_pool_delete.c +++ b/common/src/tx_block_pool_delete.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_block_pool_delete PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,6 +70,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_block_pool_delete(TX_BLOCK_POOL *pool_ptr) diff --git a/common/src/tx_block_pool_info_get.c b/common/src/tx_block_pool_info_get.c index 20b2d130..ca733500 100644 --- a/common/src/tx_block_pool_info_get.c +++ b/common/src/tx_block_pool_info_get.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_block_pool_info_get PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -73,6 +73,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_block_pool_info_get(TX_BLOCK_POOL *pool_ptr, CHAR **name, ULONG *available_blocks, diff --git a/common/src/tx_block_pool_initialize.c b/common/src/tx_block_pool_initialize.c index 26c6a561..ae062a49 100644 --- a/common/src/tx_block_pool_initialize.c +++ b/common/src/tx_block_pool_initialize.c @@ -65,7 +65,6 @@ ULONG _tx_block_pool_performance_suspension_count; ULONG _tx_block_pool_performance_timeout_count; #endif -#endif /**************************************************************************/ @@ -73,7 +72,7 @@ ULONG _tx_block_pool_performance_timeout_count; /* FUNCTION RELEASE */ /* */ /* _tx_block pool_initialize PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -104,6 +103,11 @@ ULONG _tx_block_pool_performance_timeout_count; /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* opt out of function when */ +/* TX_INLINE_INITIALIZATION is */ +/* defined, */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ VOID _tx_block_pool_initialize(VOID) @@ -126,4 +130,4 @@ VOID _tx_block_pool_initialize(VOID) #endif #endif } - +#endif diff --git a/common/src/tx_block_pool_performance_info_get.c b/common/src/tx_block_pool_performance_info_get.c index 9c0cf098..cedbbadd 100644 --- a/common/src/tx_block_pool_performance_info_get.c +++ b/common/src/tx_block_pool_performance_info_get.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_block_pool_performance_info_get PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -76,6 +76,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_block_pool_performance_info_get(TX_BLOCK_POOL *pool_ptr, ULONG *allocates, ULONG *releases, diff --git a/common/src/tx_block_pool_performance_system_info_get.c b/common/src/tx_block_pool_performance_system_info_get.c index 317003b9..eaf3f749 100644 --- a/common/src/tx_block_pool_performance_system_info_get.c +++ b/common/src/tx_block_pool_performance_system_info_get.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_block_pool_performance_system_info_get PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -73,6 +73,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_block_pool_performance_system_info_get(ULONG *allocates, ULONG *releases, ULONG *suspensions, ULONG *timeouts) diff --git a/common/src/tx_block_pool_prioritize.c b/common/src/tx_block_pool_prioritize.c index d78f53e5..89b7a45b 100644 --- a/common/src/tx_block_pool_prioritize.c +++ b/common/src/tx_block_pool_prioritize.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_block_pool_prioritize PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,6 +68,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_block_pool_prioritize(TX_BLOCK_POOL *pool_ptr) diff --git a/common/src/tx_block_release.c b/common/src/tx_block_release.c index ce69a53f..59f7b3ad 100644 --- a/common/src/tx_block_release.c +++ b/common/src/tx_block_release.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_block_release PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,6 +68,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_block_release(VOID *block_ptr) diff --git a/common/src/tx_byte_allocate.c b/common/src/tx_byte_allocate.c index caa15f4c..b4f173b7 100644 --- a/common/src/tx_byte_allocate.c +++ b/common/src/tx_byte_allocate.c @@ -38,7 +38,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_byte_allocate PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -75,6 +75,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_byte_allocate(TX_BYTE_POOL *pool_ptr, VOID **memory_ptr, ULONG memory_size, ULONG wait_option) diff --git a/common/src/tx_byte_pool_cleanup.c b/common/src/tx_byte_pool_cleanup.c index c013c2ae..5047ca57 100644 --- a/common/src/tx_byte_pool_cleanup.c +++ b/common/src/tx_byte_pool_cleanup.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_byte_pool_cleanup PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -71,6 +71,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ VOID _tx_byte_pool_cleanup(TX_THREAD *thread_ptr, ULONG suspension_sequence) diff --git a/common/src/tx_byte_pool_create.c b/common/src/tx_byte_pool_create.c index 7c19823c..2225e61b 100644 --- a/common/src/tx_byte_pool_create.c +++ b/common/src/tx_byte_pool_create.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_byte_pool_create PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,6 +69,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_byte_pool_create(TX_BYTE_POOL *pool_ptr, CHAR *name_ptr, VOID *pool_start, ULONG pool_size) diff --git a/common/src/tx_byte_pool_delete.c b/common/src/tx_byte_pool_delete.c index 5e63ad45..a8de3773 100644 --- a/common/src/tx_byte_pool_delete.c +++ b/common/src/tx_byte_pool_delete.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_byte_pool_delete PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -74,6 +74,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_byte_pool_delete(TX_BYTE_POOL *pool_ptr) diff --git a/common/src/tx_byte_pool_info_get.c b/common/src/tx_byte_pool_info_get.c index 6797263c..296adf72 100644 --- a/common/src/tx_byte_pool_info_get.c +++ b/common/src/tx_byte_pool_info_get.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_byte_pool_info_get PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -73,6 +73,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_byte_pool_info_get(TX_BYTE_POOL *pool_ptr, CHAR **name, ULONG *available_bytes, diff --git a/common/src/tx_byte_pool_initialize.c b/common/src/tx_byte_pool_initialize.c index 7b1ce011..92b6b106 100644 --- a/common/src/tx_byte_pool_initialize.c +++ b/common/src/tx_byte_pool_initialize.c @@ -80,7 +80,6 @@ ULONG _tx_byte_pool_performance_suspension_count; ULONG _tx_byte_pool_performance_timeout_count; #endif -#endif /**************************************************************************/ @@ -88,7 +87,7 @@ ULONG _tx_byte_pool_performance_timeout_count; /* FUNCTION RELEASE */ /* */ /* _tx_byte_pool_initialize PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -119,6 +118,11 @@ ULONG _tx_byte_pool_performance_timeout_count; /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* opt out of function when */ +/* TX_INLINE_INITIALIZATION is */ +/* defined, */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ VOID _tx_byte_pool_initialize(VOID) @@ -144,4 +148,4 @@ VOID _tx_byte_pool_initialize(VOID) #endif #endif } - +#endif diff --git a/common/src/tx_byte_pool_performance_info_get.c b/common/src/tx_byte_pool_performance_info_get.c index 53af8211..69968769 100644 --- a/common/src/tx_byte_pool_performance_info_get.c +++ b/common/src/tx_byte_pool_performance_info_get.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_byte_pool_performance_info_get PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -84,6 +84,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_byte_pool_performance_info_get(TX_BYTE_POOL *pool_ptr, ULONG *allocates, ULONG *releases, diff --git a/common/src/tx_byte_pool_performance_system_info_get.c b/common/src/tx_byte_pool_performance_system_info_get.c index 02d0cc5b..d873e60a 100644 --- a/common/src/tx_byte_pool_performance_system_info_get.c +++ b/common/src/tx_byte_pool_performance_system_info_get.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_byte_pool_performance_system_info_get PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -81,6 +81,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_byte_pool_performance_system_info_get(ULONG *allocates, ULONG *releases, diff --git a/common/src/tx_byte_pool_prioritize.c b/common/src/tx_byte_pool_prioritize.c index b39d6214..0e8d2868 100644 --- a/common/src/tx_byte_pool_prioritize.c +++ b/common/src/tx_byte_pool_prioritize.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_byte_pool_prioritize PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,6 +68,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_byte_pool_prioritize(TX_BYTE_POOL *pool_ptr) diff --git a/common/src/tx_byte_pool_search.c b/common/src/tx_byte_pool_search.c index 3455d5f1..79e20095 100644 --- a/common/src/tx_byte_pool_search.c +++ b/common/src/tx_byte_pool_search.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_byte_pool_search PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -77,6 +77,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UCHAR *_tx_byte_pool_search(TX_BYTE_POOL *pool_ptr, ULONG memory_size) diff --git a/common/src/tx_byte_release.c b/common/src/tx_byte_release.c index 404f1eb0..a60d4f49 100644 --- a/common/src/tx_byte_release.c +++ b/common/src/tx_byte_release.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_byte_release PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,6 +70,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_byte_release(VOID *memory_ptr) diff --git a/common/src/tx_event_flags_cleanup.c b/common/src/tx_event_flags_cleanup.c index 1b58df24..df71e741 100644 --- a/common/src/tx_event_flags_cleanup.c +++ b/common/src/tx_event_flags_cleanup.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_event_flags_cleanup PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -71,6 +71,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ VOID _tx_event_flags_cleanup(TX_THREAD *thread_ptr, ULONG suspension_sequence) diff --git a/common/src/tx_event_flags_create.c b/common/src/tx_event_flags_create.c index aa0e7269..13e2e69a 100644 --- a/common/src/tx_event_flags_create.c +++ b/common/src/tx_event_flags_create.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_event_flags_create PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,6 +68,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_event_flags_create(TX_EVENT_FLAGS_GROUP *group_ptr, CHAR *name_ptr) diff --git a/common/src/tx_event_flags_delete.c b/common/src/tx_event_flags_delete.c index d495c938..b384d4bb 100644 --- a/common/src/tx_event_flags_delete.c +++ b/common/src/tx_event_flags_delete.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_event_flags_delete PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,6 +70,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_event_flags_delete(TX_EVENT_FLAGS_GROUP *group_ptr) diff --git a/common/src/tx_event_flags_get.c b/common/src/tx_event_flags_get.c index ed3bba20..33b5c344 100644 --- a/common/src/tx_event_flags_get.c +++ b/common/src/tx_event_flags_get.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_event_flags_get PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -74,6 +74,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_event_flags_get(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG requested_flags, diff --git a/common/src/tx_event_flags_info_get.c b/common/src/tx_event_flags_info_get.c index 608be7df..05437417 100644 --- a/common/src/tx_event_flags_info_get.c +++ b/common/src/tx_event_flags_info_get.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_event_flags_info_get PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -75,6 +75,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_event_flags_info_get(TX_EVENT_FLAGS_GROUP *group_ptr, CHAR **name, ULONG *current_flags, diff --git a/common/src/tx_event_flags_initialize.c b/common/src/tx_event_flags_initialize.c index 99800fe1..867e684f 100644 --- a/common/src/tx_event_flags_initialize.c +++ b/common/src/tx_event_flags_initialize.c @@ -65,7 +65,6 @@ ULONG _tx_event_flags_performance_timeout_count; #endif -#endif @@ -74,7 +73,7 @@ ULONG _tx_event_flags_performance_timeout_count; /* FUNCTION RELEASE */ /* */ /* _tx_event_flags_initialize PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -105,6 +104,11 @@ ULONG _tx_event_flags_performance_timeout_count; /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* opt out of function when */ +/* TX_INLINE_INITIALIZATION is */ +/* defined, */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ VOID _tx_event_flags_initialize(VOID) @@ -127,4 +131,4 @@ VOID _tx_event_flags_initialize(VOID) #endif #endif } - +#endif diff --git a/common/src/tx_event_flags_performance_info_get.c b/common/src/tx_event_flags_performance_info_get.c index 5607469d..508756f1 100644 --- a/common/src/tx_event_flags_performance_info_get.c +++ b/common/src/tx_event_flags_performance_info_get.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_event_flags_performance_info_get PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -77,6 +77,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_event_flags_performance_info_get(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG *sets, ULONG *gets, diff --git a/common/src/tx_event_flags_performance_system_info_get.c b/common/src/tx_event_flags_performance_system_info_get.c index b421dd77..9d8dd0ad 100644 --- a/common/src/tx_event_flags_performance_system_info_get.c +++ b/common/src/tx_event_flags_performance_system_info_get.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_event_flags_performance_system_info_get PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -74,6 +74,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_event_flags_performance_system_info_get(ULONG *sets, ULONG *gets, ULONG *suspensions, ULONG *timeouts) diff --git a/common/src/tx_event_flags_set.c b/common/src/tx_event_flags_set.c index aebe7d19..1fb30f9a 100644 --- a/common/src/tx_event_flags_set.c +++ b/common/src/tx_event_flags_set.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_event_flags_set PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -73,6 +73,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_event_flags_set(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG flags_to_set, UINT set_option) diff --git a/common/src/tx_event_flags_set_notify.c b/common/src/tx_event_flags_set_notify.c index b65cd30b..1dc1cb49 100644 --- a/common/src/tx_event_flags_set_notify.c +++ b/common/src/tx_event_flags_set_notify.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_event_flags_set_notify PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,6 +68,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_event_flags_set_notify(TX_EVENT_FLAGS_GROUP *group_ptr, VOID (*events_set_notify)(TX_EVENT_FLAGS_GROUP *notify_group_ptr)) diff --git a/common/src/tx_initialize_high_level.c b/common/src/tx_initialize_high_level.c index 12dbd143..e9d90324 100644 --- a/common/src/tx_initialize_high_level.c +++ b/common/src/tx_initialize_high_level.c @@ -57,7 +57,7 @@ VOID *_tx_initialize_unused_memory; /* FUNCTION RELEASE */ /* */ /* _tx_initialize_high_level PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -106,6 +106,8 @@ VOID *_tx_initialize_unused_memory; /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ VOID _tx_initialize_high_level(VOID) diff --git a/common/src/tx_initialize_kernel_enter.c b/common/src/tx_initialize_kernel_enter.c index 5f9af949..5f27db43 100644 --- a/common/src/tx_initialize_kernel_enter.c +++ b/common/src/tx_initialize_kernel_enter.c @@ -46,7 +46,7 @@ TX_SAFETY_CRITICAL_EXCEPTION_HANDLER /* FUNCTION RELEASE */ /* */ /* _tx_initialize_kernel_enter PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -85,6 +85,8 @@ TX_SAFETY_CRITICAL_EXCEPTION_HANDLER /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ VOID _tx_initialize_kernel_enter(VOID) diff --git a/common/src/tx_initialize_kernel_setup.c b/common/src/tx_initialize_kernel_setup.c index b961007e..c8dc3fa0 100644 --- a/common/src/tx_initialize_kernel_setup.c +++ b/common/src/tx_initialize_kernel_setup.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_initialize_kernel_setup PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,6 +69,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ VOID _tx_initialize_kernel_setup(VOID) diff --git a/common/src/tx_misra.c b/common/src/tx_misra.c index 814205a7..ad463d3a 100644 --- a/common/src/tx_misra.c +++ b/common/src/tx_misra.c @@ -29,10 +29,11 @@ /**************************************************************************/ /**************************************************************************/ -#ifdef TX_MISRA_ENABLE +#ifndef TX_MISRA_ENABLE +#include "tx_api.h" +#else #define TX_THREAD_INIT -//CHAR _tx_version_id[100] = "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX 6.0 MISRA C Compliant *"; -#endif +//CHAR _tx_version_id[100] = "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX 6.1 MISRA C Compliant *"; #include "tx_api.h" #include "tx_thread.h" @@ -48,7 +49,7 @@ /**************************************************************************/ VOID _tx_misra_memset(VOID *ptr, UINT value, UINT size) { - memset(ptr, value, size); + memset(ptr, (INT)value, size); } @@ -92,7 +93,7 @@ ULONG _tx_misra_uchar_pointer_dif(UCHAR *ptr1, UCHAR *ptr2) ULONG value; - value = ptr1 - ptr2; + value = (ULONG)(ptr1 - ptr2); return(value); } @@ -150,7 +151,7 @@ ULONG _tx_misra_ulong_pointer_dif(ULONG *ptr1, ULONG *ptr2) { ULONG value; - value = ptr1 - ptr2; + value = (ULONG)(ptr1 - ptr2); return(value); } @@ -220,7 +221,7 @@ ULONG _tx_misra_timer_pointer_dif(TX_TIMER_INTERNAL **ptr1, TX_TIMER_INTERNAL * ULONG value; - value = ptr1 - ptr2; + value = (ULONG)(ptr1 - ptr2); return(value); } @@ -625,6 +626,7 @@ TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer) /**************************************************************************/ UINT _tx_misra_status_get(UINT status) { + (VOID)status; /* Return a successful status. */ return(TX_SUCCESS); @@ -830,4 +832,5 @@ UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer) } +#endif diff --git a/common/src/tx_mutex_cleanup.c b/common/src/tx_mutex_cleanup.c index f076c772..aac2950c 100644 --- a/common/src/tx_mutex_cleanup.c +++ b/common/src/tx_mutex_cleanup.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_mutex_cleanup PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -71,6 +71,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ VOID _tx_mutex_cleanup(TX_THREAD *thread_ptr, ULONG suspension_sequence) @@ -218,7 +220,7 @@ TX_THREAD *previous_thread; /* FUNCTION RELEASE */ /* */ /* _tx_mutex_thread_release PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -250,6 +252,8 @@ TX_THREAD *previous_thread; /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ VOID _tx_mutex_thread_release(TX_THREAD *thread_ptr) diff --git a/common/src/tx_mutex_create.c b/common/src/tx_mutex_create.c index 3b70289d..7925528a 100644 --- a/common/src/tx_mutex_create.c +++ b/common/src/tx_mutex_create.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_mutex_create PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,6 +69,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_mutex_create(TX_MUTEX *mutex_ptr, CHAR *name_ptr, UINT inherit) diff --git a/common/src/tx_mutex_delete.c b/common/src/tx_mutex_delete.c index 0b2dc079..7c3becc0 100644 --- a/common/src/tx_mutex_delete.c +++ b/common/src/tx_mutex_delete.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_mutex_delete PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -71,6 +71,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_mutex_delete(TX_MUTEX *mutex_ptr) diff --git a/common/src/tx_mutex_get.c b/common/src/tx_mutex_get.c index 1d805c84..83c438a2 100644 --- a/common/src/tx_mutex_get.c +++ b/common/src/tx_mutex_get.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_mutex_get PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,6 +70,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_mutex_get(TX_MUTEX *mutex_ptr, ULONG wait_option) diff --git a/common/src/tx_mutex_info_get.c b/common/src/tx_mutex_info_get.c index a148850b..f43e96e5 100644 --- a/common/src/tx_mutex_info_get.c +++ b/common/src/tx_mutex_info_get.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_mutex_info_get PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -74,6 +74,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_mutex_info_get(TX_MUTEX *mutex_ptr, CHAR **name, ULONG *count, TX_THREAD **owner, diff --git a/common/src/tx_mutex_initialize.c b/common/src/tx_mutex_initialize.c index 3b546ee7..941912b3 100644 --- a/common/src/tx_mutex_initialize.c +++ b/common/src/tx_mutex_initialize.c @@ -75,7 +75,6 @@ ULONG _tx_mutex_performance_priority_inversion_count; ULONG _tx_mutex_performance__priority_inheritance_count; #endif -#endif /**************************************************************************/ @@ -83,7 +82,7 @@ ULONG _tx_mutex_performance__priority_inheritance_count; /* FUNCTION RELEASE */ /* */ /* _tx_mutex_initialize PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -114,6 +113,11 @@ ULONG _tx_mutex_performance__priority_inheritance_count; /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* opt out of function when */ +/* TX_INLINE_INITIALIZATION is */ +/* defined, */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ VOID _tx_mutex_initialize(VOID) @@ -138,4 +142,4 @@ VOID _tx_mutex_initialize(VOID) #endif #endif } - +#endif diff --git a/common/src/tx_mutex_performance_info_get.c b/common/src/tx_mutex_performance_info_get.c index 3dbd35e4..b154f15e 100644 --- a/common/src/tx_mutex_performance_info_get.c +++ b/common/src/tx_mutex_performance_info_get.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_mutex_performance_info_get PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -79,6 +79,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_mutex_performance_info_get(TX_MUTEX *mutex_ptr, ULONG *puts, ULONG *gets, diff --git a/common/src/tx_mutex_performance_system_info_get.c b/common/src/tx_mutex_performance_system_info_get.c index f2cb61fb..a06c228c 100644 --- a/common/src/tx_mutex_performance_system_info_get.c +++ b/common/src/tx_mutex_performance_system_info_get.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_mutex_performance_system_info_get PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -78,6 +78,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_mutex_performance_system_info_get(ULONG *puts, ULONG *gets, ULONG *suspensions, diff --git a/common/src/tx_mutex_prioritize.c b/common/src/tx_mutex_prioritize.c index dddc7e54..5de8641a 100644 --- a/common/src/tx_mutex_prioritize.c +++ b/common/src/tx_mutex_prioritize.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_mutex_prioritize PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,6 +68,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_mutex_prioritize(TX_MUTEX *mutex_ptr) diff --git a/common/src/tx_mutex_priority_change.c b/common/src/tx_mutex_priority_change.c index 6bb905d1..c5f58869 100644 --- a/common/src/tx_mutex_priority_change.c +++ b/common/src/tx_mutex_priority_change.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_mutex_priority_change PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -71,6 +71,13 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), and */ +/* change thread state from */ +/* TX_SUSPENDED to */ +/* TX_PRIORITY_CHANGE before */ +/* calling */ +/* _tx_thread_system_suspend, */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ VOID _tx_mutex_priority_change(TX_THREAD *thread_ptr, UINT new_priority) @@ -139,8 +146,8 @@ UINT map_index; /* Increment the preempt disable flag. */ _tx_thread_preempt_disable++; - /* Set the state to suspended. */ - thread_ptr -> tx_thread_state = TX_SUSPENDED; + /* Set the state to priority change. */ + thread_ptr -> tx_thread_state = TX_PRIORITY_CHANGE; /* Call actual non-interruptable thread suspension routine. */ _tx_thread_system_ni_suspend(thread_ptr, ((ULONG) 0)); @@ -175,8 +182,8 @@ UINT map_index; /* Increment the preempt disable flag. */ _tx_thread_preempt_disable = _tx_thread_preempt_disable + ((UINT) 2); - /* Set the state to suspended. */ - thread_ptr -> tx_thread_state = TX_SUSPENDED; + /* Set the state to priority change. */ + thread_ptr -> tx_thread_state = TX_PRIORITY_CHANGE; /* Set the suspending flag. */ thread_ptr -> tx_thread_suspending = TX_TRUE; diff --git a/common/src/tx_mutex_put.c b/common/src/tx_mutex_put.c index 93cfad07..fe3a49fd 100644 --- a/common/src/tx_mutex_put.c +++ b/common/src/tx_mutex_put.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_mutex_put PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -73,6 +73,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_mutex_put(TX_MUTEX *mutex_ptr) diff --git a/common/src/tx_queue_cleanup.c b/common/src/tx_queue_cleanup.c index 6583ec6e..93e24e04 100644 --- a/common/src/tx_queue_cleanup.c +++ b/common/src/tx_queue_cleanup.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_queue_cleanup PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -71,6 +71,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ VOID _tx_queue_cleanup(TX_THREAD *thread_ptr, ULONG suspension_sequence) diff --git a/common/src/tx_queue_create.c b/common/src/tx_queue_create.c index ae105019..522075e5 100644 --- a/common/src/tx_queue_create.c +++ b/common/src/tx_queue_create.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_queue_create PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,6 +70,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_queue_create(TX_QUEUE *queue_ptr, CHAR *name_ptr, UINT message_size, diff --git a/common/src/tx_queue_delete.c b/common/src/tx_queue_delete.c index 343af731..32c6e49a 100644 --- a/common/src/tx_queue_delete.c +++ b/common/src/tx_queue_delete.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_queue_delete PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,6 +69,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_queue_delete(TX_QUEUE *queue_ptr) diff --git a/common/src/tx_queue_flush.c b/common/src/tx_queue_flush.c index ca338e8a..35855806 100644 --- a/common/src/tx_queue_flush.c +++ b/common/src/tx_queue_flush.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_queue_flush PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,6 +70,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_queue_flush(TX_QUEUE *queue_ptr) diff --git a/common/src/tx_queue_front_send.c b/common/src/tx_queue_front_send.c index 3becd09d..f183cba7 100644 --- a/common/src/tx_queue_front_send.c +++ b/common/src/tx_queue_front_send.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_queue_front_send PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -73,6 +73,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_queue_front_send(TX_QUEUE *queue_ptr, VOID *source_ptr, ULONG wait_option) diff --git a/common/src/tx_queue_info_get.c b/common/src/tx_queue_info_get.c index e0496929..5e94d41e 100644 --- a/common/src/tx_queue_info_get.c +++ b/common/src/tx_queue_info_get.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_queue_info_get PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -73,6 +73,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_queue_info_get(TX_QUEUE *queue_ptr, CHAR **name, ULONG *enqueued, ULONG *available_storage, diff --git a/common/src/tx_queue_initialize.c b/common/src/tx_queue_initialize.c index 0e9bb622..41fb6fa1 100644 --- a/common/src/tx_queue_initialize.c +++ b/common/src/tx_queue_initialize.c @@ -73,7 +73,6 @@ ULONG _tx_queue_performance_full_error_count; ULONG _tx_queue_performance_timeout_count; #endif -#endif /**************************************************************************/ @@ -81,7 +80,7 @@ ULONG _tx_queue_performance_timeout_count; /* FUNCTION RELEASE */ /* */ /* _tx_queue_initialize PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -112,6 +111,11 @@ ULONG _tx_queue_performance_timeout_count; /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* opt out of function when */ +/* TX_INLINE_INITIALIZATION is */ +/* defined, */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ VOID _tx_queue_initialize(VOID) @@ -135,4 +139,4 @@ VOID _tx_queue_initialize(VOID) #endif #endif } - +#endif diff --git a/common/src/tx_queue_performance_info_get.c b/common/src/tx_queue_performance_info_get.c index 48d561b4..74d40f11 100644 --- a/common/src/tx_queue_performance_info_get.c +++ b/common/src/tx_queue_performance_info_get.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_queue_performance_info_get PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -78,6 +78,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_queue_performance_info_get(TX_QUEUE *queue_ptr, ULONG *messages_sent, ULONG *messages_received, diff --git a/common/src/tx_queue_performance_system_info_get.c b/common/src/tx_queue_performance_system_info_get.c index ebc58815..6846d3cc 100644 --- a/common/src/tx_queue_performance_system_info_get.c +++ b/common/src/tx_queue_performance_system_info_get.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_queue_performance_system_info_get PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -78,6 +78,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_queue_performance_system_info_get(ULONG *messages_sent, ULONG *messages_received, diff --git a/common/src/tx_queue_prioritize.c b/common/src/tx_queue_prioritize.c index 632e03b6..0768aa02 100644 --- a/common/src/tx_queue_prioritize.c +++ b/common/src/tx_queue_prioritize.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_queue_prioritize PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,6 +68,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_queue_prioritize(TX_QUEUE *queue_ptr) diff --git a/common/src/tx_queue_receive.c b/common/src/tx_queue_receive.c index 72555df8..3cb2ea5a 100644 --- a/common/src/tx_queue_receive.c +++ b/common/src/tx_queue_receive.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_queue_receive PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -75,6 +75,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_queue_receive(TX_QUEUE *queue_ptr, VOID *destination_ptr, ULONG wait_option) diff --git a/common/src/tx_queue_send.c b/common/src/tx_queue_send.c index 4d242947..bdf60b97 100644 --- a/common/src/tx_queue_send.c +++ b/common/src/tx_queue_send.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_queue_send PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -73,6 +73,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_queue_send(TX_QUEUE *queue_ptr, VOID *source_ptr, ULONG wait_option) diff --git a/common/src/tx_queue_send_notify.c b/common/src/tx_queue_send_notify.c index 67b26dea..a0bbf527 100644 --- a/common/src/tx_queue_send_notify.c +++ b/common/src/tx_queue_send_notify.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_queue_send_notify PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,6 +68,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_queue_send_notify(TX_QUEUE *queue_ptr, VOID (*queue_send_notify)(TX_QUEUE *notify_queue_ptr)) diff --git a/common/src/tx_semaphore_ceiling_put.c b/common/src/tx_semaphore_ceiling_put.c index 7b101228..30668683 100644 --- a/common/src/tx_semaphore_ceiling_put.c +++ b/common/src/tx_semaphore_ceiling_put.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_semaphore_ceiling_put PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,6 +70,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_semaphore_ceiling_put(TX_SEMAPHORE *semaphore_ptr, ULONG ceiling) diff --git a/common/src/tx_semaphore_cleanup.c b/common/src/tx_semaphore_cleanup.c index 498f9d7d..abe23046 100644 --- a/common/src/tx_semaphore_cleanup.c +++ b/common/src/tx_semaphore_cleanup.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_semaphore_cleanup PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -71,6 +71,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ VOID _tx_semaphore_cleanup(TX_THREAD *thread_ptr, ULONG suspension_sequence) diff --git a/common/src/tx_semaphore_create.c b/common/src/tx_semaphore_create.c index 377a7777..028dcab0 100644 --- a/common/src/tx_semaphore_create.c +++ b/common/src/tx_semaphore_create.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_semaphore_create PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,6 +68,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_semaphore_create(TX_SEMAPHORE *semaphore_ptr, CHAR *name_ptr, ULONG initial_count) diff --git a/common/src/tx_semaphore_delete.c b/common/src/tx_semaphore_delete.c index a8297463..857a0fc5 100644 --- a/common/src/tx_semaphore_delete.c +++ b/common/src/tx_semaphore_delete.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_semaphore_delete PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,6 +70,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_semaphore_delete(TX_SEMAPHORE *semaphore_ptr) diff --git a/common/src/tx_semaphore_get.c b/common/src/tx_semaphore_get.c index 9e1072dc..ff5dd93b 100644 --- a/common/src/tx_semaphore_get.c +++ b/common/src/tx_semaphore_get.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_semaphore_get PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,6 +69,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_semaphore_get(TX_SEMAPHORE *semaphore_ptr, ULONG wait_option) diff --git a/common/src/tx_semaphore_info_get.c b/common/src/tx_semaphore_info_get.c index 8f983072..8ca99ef3 100644 --- a/common/src/tx_semaphore_info_get.c +++ b/common/src/tx_semaphore_info_get.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_semaphore_info_get PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -73,6 +73,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_semaphore_info_get(TX_SEMAPHORE *semaphore_ptr, CHAR **name, ULONG *current_value, diff --git a/common/src/tx_semaphore_initialize.c b/common/src/tx_semaphore_initialize.c index ff97845c..a304e54b 100644 --- a/common/src/tx_semaphore_initialize.c +++ b/common/src/tx_semaphore_initialize.c @@ -65,7 +65,6 @@ ULONG _tx_semaphore_performance_suspension_count; ULONG _tx_semaphore_performance_timeout_count; #endif -#endif /**************************************************************************/ @@ -73,7 +72,7 @@ ULONG _tx_semaphore_performance_timeout_count; /* FUNCTION RELEASE */ /* */ /* _tx_semaphore_initialize PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -104,6 +103,11 @@ ULONG _tx_semaphore_performance_timeout_count; /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* opt out of function when */ +/* TX_INLINE_INITIALIZATION is */ +/* defined, */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ VOID _tx_semaphore_initialize(VOID) @@ -126,4 +130,4 @@ VOID _tx_semaphore_initialize(VOID) #endif #endif } - +#endif diff --git a/common/src/tx_semaphore_performance_info_get.c b/common/src/tx_semaphore_performance_info_get.c index fcef0321..5e792e95 100644 --- a/common/src/tx_semaphore_performance_info_get.c +++ b/common/src/tx_semaphore_performance_info_get.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_semaphore_performance_info_get PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -76,6 +76,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_semaphore_performance_info_get(TX_SEMAPHORE *semaphore_ptr, ULONG *puts, ULONG *gets, diff --git a/common/src/tx_semaphore_performance_system_info_get.c b/common/src/tx_semaphore_performance_system_info_get.c index 6d37b310..4bdb0d19 100644 --- a/common/src/tx_semaphore_performance_system_info_get.c +++ b/common/src/tx_semaphore_performance_system_info_get.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_semaphore_performance_system_info_get PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -74,6 +74,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_semaphore_performance_system_info_get(ULONG *puts, ULONG *gets, ULONG *suspensions, ULONG *timeouts) diff --git a/common/src/tx_semaphore_prioritize.c b/common/src/tx_semaphore_prioritize.c index 0072b7e6..de20e1f8 100644 --- a/common/src/tx_semaphore_prioritize.c +++ b/common/src/tx_semaphore_prioritize.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_semaphore_prioritize PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,6 +68,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_semaphore_prioritize(TX_SEMAPHORE *semaphore_ptr) diff --git a/common/src/tx_semaphore_put.c b/common/src/tx_semaphore_put.c index 09ae09cb..dbd973df 100644 --- a/common/src/tx_semaphore_put.c +++ b/common/src/tx_semaphore_put.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_semaphore_put PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,6 +68,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_semaphore_put(TX_SEMAPHORE *semaphore_ptr) diff --git a/common/src/tx_semaphore_put_notify.c b/common/src/tx_semaphore_put_notify.c index b5b71e7f..5fb7c709 100644 --- a/common/src/tx_semaphore_put_notify.c +++ b/common/src/tx_semaphore_put_notify.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_semaphore_put_notify PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,6 +68,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_semaphore_put_notify(TX_SEMAPHORE *semaphore_ptr, VOID (*semaphore_put_notify)(TX_SEMAPHORE *notify_semaphore_ptr)) diff --git a/common/src/tx_thread_create.c b/common/src/tx_thread_create.c index 4169d362..6af34e3c 100644 --- a/common/src/tx_thread_create.c +++ b/common/src/tx_thread_create.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_create PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -80,6 +80,10 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), and */ +/* changed stack calculations */ +/* to use ALIGN_TYPE integers, */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_create(TX_THREAD *thread_ptr, CHAR *name_ptr, VOID (*entry_function)(ULONG id), ULONG entry_input, @@ -96,8 +100,8 @@ UINT saved_threshold = ((UINT) 0); UCHAR *temp_ptr; #ifdef TX_ENABLE_STACK_CHECKING -ULONG new_stack_start; -ULONG updated_stack_start; +ALIGN_TYPE new_stack_start; +ALIGN_TYPE updated_stack_start; #endif #ifndef TX_DISABLE_STACK_FILLING @@ -116,7 +120,7 @@ ULONG updated_stack_start; stack_size = ((stack_size/(sizeof(ULONG))) * (sizeof(ULONG))) - (sizeof(ULONG)); /* Ensure the starting stack address is evenly aligned. */ - new_stack_start = TX_POINTER_TO_ULONG_CONVERT(stack_start); + new_stack_start = TX_POINTER_TO_ALIGN_TYPE_CONVERT(stack_start); updated_stack_start = ((((ULONG) new_stack_start) + ((sizeof(ULONG)) - ((ULONG) 1)) ) & (~((sizeof(ULONG)) - ((ULONG) 1)))); /* Determine if the starting stack address is different. */ @@ -128,7 +132,7 @@ ULONG updated_stack_start; } /* Update the starting stack pointer. */ - stack_start = TX_ULONG_TO_POINTER_CONVERT(updated_stack_start); + stack_start = TX_ALIGN_TYPE_TO_POINTER_CONVERT(updated_stack_start); #endif /* Prepare the thread control block prior to placing it on the created diff --git a/common/src/tx_thread_delete.c b/common/src/tx_thread_delete.c index 3d384966..a3a5572b 100644 --- a/common/src/tx_thread_delete.c +++ b/common/src/tx_thread_delete.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_delete PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,6 +67,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_delete(TX_THREAD *thread_ptr) diff --git a/common/src/tx_thread_entry_exit_notify.c b/common/src/tx_thread_entry_exit_notify.c index 273864f2..b8c69a61 100644 --- a/common/src/tx_thread_entry_exit_notify.c +++ b/common/src/tx_thread_entry_exit_notify.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_entry_exit_notify PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,6 +70,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_entry_exit_notify(TX_THREAD *thread_ptr, VOID (*thread_entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT id)) diff --git a/common/src/tx_thread_identify.c b/common/src/tx_thread_identify.c index 49f9b338..80145a0f 100644 --- a/common/src/tx_thread_identify.c +++ b/common/src/tx_thread_identify.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_identify PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,6 +69,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ TX_THREAD *_tx_thread_identify(VOID) diff --git a/common/src/tx_thread_info_get.c b/common/src/tx_thread_info_get.c index 1f0acc83..2597050d 100644 --- a/common/src/tx_thread_info_get.c +++ b/common/src/tx_thread_info_get.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_info_get PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -76,6 +76,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_info_get(TX_THREAD *thread_ptr, CHAR **name, UINT *state, ULONG *run_count, diff --git a/common/src/tx_thread_initialize.c b/common/src/tx_thread_initialize.c index 99127066..9ced1ccd 100644 --- a/common/src/tx_thread_initialize.c +++ b/common/src/tx_thread_initialize.c @@ -277,7 +277,7 @@ const CHAR _tx_thread_special_string[] = /* FUNCTION RELEASE */ /* */ /* _tx_thread_initialize PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -308,6 +308,8 @@ const CHAR _tx_thread_special_string[] = /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_initialize(VOID) diff --git a/common/src/tx_thread_performance_info_get.c b/common/src/tx_thread_performance_info_get.c index ba22b346..f61ed3d8 100644 --- a/common/src/tx_thread_performance_info_get.c +++ b/common/src/tx_thread_performance_info_get.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_performance_info_get PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -93,6 +93,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_performance_info_get(TX_THREAD *thread_ptr, ULONG *resumptions, ULONG *suspensions, diff --git a/common/src/tx_thread_performance_system_info_get.c b/common/src/tx_thread_performance_system_info_get.c index 0d85cc10..c027ea1b 100644 --- a/common/src/tx_thread_performance_system_info_get.c +++ b/common/src/tx_thread_performance_system_info_get.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_performance_system_info_get PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -93,6 +93,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_performance_system_info_get(ULONG *resumptions, ULONG *suspensions, diff --git a/common/src/tx_thread_preemption_change.c b/common/src/tx_thread_preemption_change.c index 3c6dd51e..9b323e2b 100644 --- a/common/src/tx_thread_preemption_change.c +++ b/common/src/tx_thread_preemption_change.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_preemption_change PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,6 +70,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_preemption_change(TX_THREAD *thread_ptr, UINT new_threshold, UINT *old_threshold) diff --git a/common/src/tx_thread_priority_change.c b/common/src/tx_thread_priority_change.c index 8a18fb4b..967867b1 100644 --- a/common/src/tx_thread_priority_change.c +++ b/common/src/tx_thread_priority_change.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_priority_change PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -77,6 +77,13 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), and */ +/* change thread state from */ +/* TX_SUSPENDED to */ +/* TX_PRIORITY_CHANGE before */ +/* calling */ +/* _tx_thread_system_suspend, */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_priority_change(TX_THREAD *thread_ptr, UINT new_priority, UINT *old_priority) @@ -133,8 +140,8 @@ UINT original_priority; else { - /* Set the state to suspended. */ - thread_ptr -> tx_thread_state = TX_SUSPENDED; + /* Set the state to priority change. */ + thread_ptr -> tx_thread_state = TX_PRIORITY_CHANGE; /* Pickup the next thread to execute. */ execute_ptr = _tx_thread_execute_ptr; diff --git a/common/src/tx_thread_relinquish.c b/common/src/tx_thread_relinquish.c index 4dcfb76c..b2606601 100644 --- a/common/src/tx_thread_relinquish.c +++ b/common/src/tx_thread_relinquish.c @@ -38,7 +38,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_relinquish PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -71,6 +71,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_relinquish(VOID) diff --git a/common/src/tx_thread_reset.c b/common/src/tx_thread_reset.c index 5eca80d3..6c98c2b1 100644 --- a/common/src/tx_thread_reset.c +++ b/common/src/tx_thread_reset.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_reset PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,6 +68,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_reset(TX_THREAD *thread_ptr) diff --git a/common/src/tx_thread_resume.c b/common/src/tx_thread_resume.c index 43e789f7..bb111592 100644 --- a/common/src/tx_thread_resume.c +++ b/common/src/tx_thread_resume.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_resume PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,6 +68,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_resume(TX_THREAD *thread_ptr) diff --git a/common/src/tx_thread_shell_entry.c b/common/src/tx_thread_shell_entry.c index 67d61a40..ef106c5c 100644 --- a/common/src/tx_thread_shell_entry.c +++ b/common/src/tx_thread_shell_entry.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_shell_entry PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,6 +69,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_shell_entry(VOID) diff --git a/common/src/tx_thread_sleep.c b/common/src/tx_thread_sleep.c index 2f24c438..e4b92c57 100644 --- a/common/src/tx_thread_sleep.c +++ b/common/src/tx_thread_sleep.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_sleep PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,6 +67,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_sleep(ULONG timer_ticks) diff --git a/common/src/tx_thread_stack_analyze.c b/common/src/tx_thread_stack_analyze.c index c690724d..7a75ab30 100644 --- a/common/src/tx_thread_stack_analyze.c +++ b/common/src/tx_thread_stack_analyze.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_analyze PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -66,6 +66,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_stack_analyze(TX_THREAD *thread_ptr) diff --git a/common/src/tx_thread_stack_error_handler.c b/common/src/tx_thread_stack_error_handler.c index 46235137..9c90b1a7 100644 --- a/common/src/tx_thread_stack_error_handler.c +++ b/common/src/tx_thread_stack_error_handler.c @@ -26,6 +26,7 @@ /* Include necessary system files. */ #include "tx_api.h" +#ifdef TX_MISRA_ENABLE #include "tx_thread.h" @@ -34,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_error_handler PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -65,6 +66,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* update misra support, */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) @@ -102,4 +106,5 @@ TX_INTERRUPT_SAVE_AREA } #endif } +#endif /* TX_MISRA_ENABLE */ diff --git a/common/src/tx_thread_stack_error_notify.c b/common/src/tx_thread_stack_error_notify.c index abd456d2..a66eab56 100644 --- a/common/src/tx_thread_stack_error_notify.c +++ b/common/src/tx_thread_stack_error_notify.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_error_notify PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -72,6 +72,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr)) diff --git a/common/src/tx_thread_suspend.c b/common/src/tx_thread_suspend.c index 20c83415..764158b7 100644 --- a/common/src/tx_thread_suspend.c +++ b/common/src/tx_thread_suspend.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_suspend PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,6 +68,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_suspend(TX_THREAD *thread_ptr) diff --git a/common/src/tx_thread_system_preempt_check.c b/common/src/tx_thread_system_preempt_check.c index 0b92bb8b..8f1d00a1 100644 --- a/common/src/tx_thread_system_preempt_check.c +++ b/common/src/tx_thread_system_preempt_check.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_preempt_check PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -66,6 +66,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_system_preempt_check(VOID) diff --git a/common/src/tx_thread_system_resume.c b/common/src/tx_thread_system_resume.c index b81b5d70..278e9b11 100644 --- a/common/src/tx_thread_system_resume.c +++ b/common/src/tx_thread_system_resume.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_resume PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -74,6 +74,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_system_resume(TX_THREAD *thread_ptr) diff --git a/common/src/tx_thread_system_suspend.c b/common/src/tx_thread_system_suspend.c index f3880e24..56dc710f 100644 --- a/common/src/tx_thread_system_suspend.c +++ b/common/src/tx_thread_system_suspend.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_suspend PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -76,6 +76,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_system_suspend(TX_THREAD *thread_ptr) diff --git a/common/src/tx_thread_terminate.c b/common/src/tx_thread_terminate.c index 012d128e..a1037da2 100644 --- a/common/src/tx_thread_terminate.c +++ b/common/src/tx_thread_terminate.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_terminate PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -73,6 +73,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_terminate(TX_THREAD *thread_ptr) diff --git a/common/src/tx_thread_time_slice.c b/common/src/tx_thread_time_slice.c index d629ab9a..ebcd41b5 100644 --- a/common/src/tx_thread_time_slice.c +++ b/common/src/tx_thread_time_slice.c @@ -22,6 +22,7 @@ #define TX_SOURCE_CODE +#ifndef TX_NO_TIMER /* Include necessary system files. */ @@ -36,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_time_slice PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,6 +70,10 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Scott Larson Modified comment(s), and */ +/* opt out of function when */ +/* TX_NO_TIMER is defined, */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_time_slice(VOID) @@ -182,3 +187,4 @@ UINT preempt_disable; #endif } +#endif diff --git a/common/src/tx_thread_time_slice_change.c b/common/src/tx_thread_time_slice_change.c index 19ca83fc..8e834b2c 100644 --- a/common/src/tx_thread_time_slice_change.c +++ b/common/src/tx_thread_time_slice_change.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_time_slice_change PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -71,6 +71,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_time_slice_change(TX_THREAD *thread_ptr, ULONG new_time_slice, ULONG *old_time_slice) diff --git a/common/src/tx_thread_timeout.c b/common/src/tx_thread_timeout.c index 0ac5c022..01e69e7a 100644 --- a/common/src/tx_thread_timeout.c +++ b/common/src/tx_thread_timeout.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_timeout PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -72,6 +72,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_timeout(ULONG timeout_input) diff --git a/common/src/tx_thread_wait_abort.c b/common/src/tx_thread_wait_abort.c index c590e17a..5893e667 100644 --- a/common/src/tx_thread_wait_abort.c +++ b/common/src/tx_thread_wait_abort.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_wait_abort PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,6 +69,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_wait_abort(TX_THREAD *thread_ptr) diff --git a/common/src/tx_time_get.c b/common/src/tx_time_get.c index 2bc69bc0..db44bdb5 100644 --- a/common/src/tx_time_get.c +++ b/common/src/tx_time_get.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_time_get PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -66,6 +66,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ ULONG _tx_time_get(VOID) diff --git a/common/src/tx_time_set.c b/common/src/tx_time_set.c index 83522f7d..13856cef 100644 --- a/common/src/tx_time_set.c +++ b/common/src/tx_time_set.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_time_set PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -66,6 +66,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ VOID _tx_time_set(ULONG new_time) diff --git a/common/src/tx_timer_activate.c b/common/src/tx_timer_activate.c index 69580545..9529c462 100644 --- a/common/src/tx_timer_activate.c +++ b/common/src/tx_timer_activate.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_activate PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,6 +67,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_timer_activate(TX_TIMER *timer_ptr) diff --git a/common/src/tx_timer_change.c b/common/src/tx_timer_change.c index ca796a3f..b1748061 100644 --- a/common/src/tx_timer_change.c +++ b/common/src/tx_timer_change.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_change PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,6 +68,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_timer_change(TX_TIMER *timer_ptr, ULONG initial_ticks, ULONG reschedule_ticks) diff --git a/common/src/tx_timer_create.c b/common/src/tx_timer_create.c index a394fcf2..b4eb949d 100644 --- a/common/src/tx_timer_create.c +++ b/common/src/tx_timer_create.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_create PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -71,6 +71,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_timer_create(TX_TIMER *timer_ptr, CHAR *name_ptr, diff --git a/common/src/tx_timer_deactivate.c b/common/src/tx_timer_deactivate.c index b93c2785..0ae1e448 100644 --- a/common/src/tx_timer_deactivate.c +++ b/common/src/tx_timer_deactivate.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_deactivate PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -65,6 +65,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_timer_deactivate(TX_TIMER *timer_ptr) diff --git a/common/src/tx_timer_delete.c b/common/src/tx_timer_delete.c index c5f444b0..3a7a89b5 100644 --- a/common/src/tx_timer_delete.c +++ b/common/src/tx_timer_delete.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_delete PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -65,6 +65,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_timer_delete(TX_TIMER *timer_ptr) diff --git a/common/src/tx_timer_expiration_process.c b/common/src/tx_timer_expiration_process.c index ffe9ba81..38cce3df 100644 --- a/common/src/tx_timer_expiration_process.c +++ b/common/src/tx_timer_expiration_process.c @@ -22,6 +22,7 @@ #define TX_SOURCE_CODE +#ifndef TX_NO_TIMER /* Include necessary system files. */ @@ -35,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_expiration_process PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -72,6 +73,10 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Scott Larson Modified comment(s), and */ +/* opt out of function when */ +/* TX_NO_TIMER is defined, */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ VOID _tx_timer_expiration_process(VOID) @@ -475,3 +480,4 @@ TX_TIMER *timer_ptr; #endif } +#endif diff --git a/common/src/tx_timer_info_get.c b/common/src/tx_timer_info_get.c index d422910b..62b47fca 100644 --- a/common/src/tx_timer_info_get.c +++ b/common/src/tx_timer_info_get.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_info_get PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -72,6 +72,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_timer_info_get(TX_TIMER *timer_ptr, CHAR **name, UINT *active, ULONG *remaining_ticks, diff --git a/common/src/tx_timer_initialize.c b/common/src/tx_timer_initialize.c index f86498f4..8532b1e6 100644 --- a/common/src/tx_timer_initialize.c +++ b/common/src/tx_timer_initialize.c @@ -167,7 +167,7 @@ ULONG _tx_timer_time_slice; /* FUNCTION RELEASE */ /* */ /* _tx_timer_initialize PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -198,6 +198,8 @@ ULONG _tx_timer_time_slice; /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ VOID _tx_timer_initialize(VOID) diff --git a/common/src/tx_timer_performance_info_get.c b/common/src/tx_timer_performance_info_get.c index e765abc9..39e60b44 100644 --- a/common/src/tx_timer_performance_info_get.c +++ b/common/src/tx_timer_performance_info_get.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_performance_info_get PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -79,6 +79,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_timer_performance_info_get(TX_TIMER *timer_ptr, ULONG *activates, ULONG *reactivates, diff --git a/common/src/tx_timer_performance_system_info_get.c b/common/src/tx_timer_performance_system_info_get.c index 5439864d..498cee30 100644 --- a/common/src/tx_timer_performance_system_info_get.c +++ b/common/src/tx_timer_performance_system_info_get.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_performance_system_info_get PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -76,6 +76,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_timer_performance_system_info_get(ULONG *activates, ULONG *reactivates, diff --git a/common/src/tx_timer_system_activate.c b/common/src/tx_timer_system_activate.c index a4b844d3..d0617a8d 100644 --- a/common/src/tx_timer_system_activate.c +++ b/common/src/tx_timer_system_activate.c @@ -22,6 +22,7 @@ #define TX_SOURCE_CODE +#ifndef TX_NO_TIMER /* Include necessary system files. */ @@ -34,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_system_activate PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,6 +70,10 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Scott Larson Modified comment(s), and */ +/* opt out of function when */ +/* TX_NO_TIMER is defined, */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ VOID _tx_timer_system_activate(TX_TIMER_INTERNAL *timer_ptr) @@ -162,3 +167,4 @@ ULONG expiration_time; } } +#endif diff --git a/common/src/tx_timer_system_deactivate.c b/common/src/tx_timer_system_deactivate.c index b951791f..909bf458 100644 --- a/common/src/tx_timer_system_deactivate.c +++ b/common/src/tx_timer_system_deactivate.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_system_deactivate PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,6 +67,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ VOID _tx_timer_system_deactivate(TX_TIMER_INTERNAL *timer_ptr) diff --git a/common/src/tx_timer_thread_entry.c b/common/src/tx_timer_thread_entry.c index cc8b036c..8b1a262d 100644 --- a/common/src/tx_timer_thread_entry.c +++ b/common/src/tx_timer_thread_entry.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_thread_entry PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,6 +69,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ #ifndef TX_TIMER_PROCESS_IN_ISR diff --git a/common/src/tx_trace_buffer_full_notify.c b/common/src/tx_trace_buffer_full_notify.c index e8723870..d0901e0e 100644 --- a/common/src/tx_trace_buffer_full_notify.c +++ b/common/src/tx_trace_buffer_full_notify.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_trace_buffer_full_notify PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,6 +70,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_trace_buffer_full_notify(VOID (*full_buffer_callback)(VOID *buffer)) diff --git a/common/src/tx_trace_disable.c b/common/src/tx_trace_disable.c index 61881ce2..ef1df303 100644 --- a/common/src/tx_trace_disable.c +++ b/common/src/tx_trace_disable.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_trace_disable PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -64,6 +64,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_trace_disable(VOID) diff --git a/common/src/tx_trace_enable.c b/common/src/tx_trace_enable.c index 079500fd..8278d5e5 100644 --- a/common/src/tx_trace_enable.c +++ b/common/src/tx_trace_enable.c @@ -44,7 +44,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_trace_enable PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -79,6 +79,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_trace_enable(VOID *trace_buffer_start, ULONG trace_buffer_size, ULONG registry_entries) diff --git a/common/src/tx_trace_event_filter.c b/common/src/tx_trace_event_filter.c index 82c23789..4bcedafa 100644 --- a/common/src/tx_trace_event_filter.c +++ b/common/src/tx_trace_event_filter.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_trace_event_filter PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,6 +67,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_trace_event_filter(ULONG event_filter_bits) diff --git a/common/src/tx_trace_event_unfilter.c b/common/src/tx_trace_event_unfilter.c index 6c2e8011..5dc5c085 100644 --- a/common/src/tx_trace_event_unfilter.c +++ b/common/src/tx_trace_event_unfilter.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_trace_event_unfilter PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,6 +67,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_trace_event_unfilter(ULONG event_unfilter_bits) diff --git a/common/src/tx_trace_initialize.c b/common/src/tx_trace_initialize.c index 1be5408c..18d24feb 100644 --- a/common/src/tx_trace_initialize.c +++ b/common/src/tx_trace_initialize.c @@ -100,7 +100,7 @@ ULONG _tx_trace_registry_search_start; /* FUNCTION RELEASE */ /* */ /* _tx_trace_initialize PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -131,6 +131,8 @@ ULONG _tx_trace_registry_search_start; /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ VOID _tx_trace_initialize(VOID) diff --git a/common/src/tx_trace_interrupt_control.c b/common/src/tx_trace_interrupt_control.c index 3f8addc4..d3020e67 100644 --- a/common/src/tx_trace_interrupt_control.c +++ b/common/src/tx_trace_interrupt_control.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_trace_interrupt_control PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -66,6 +66,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_trace_interrupt_control(UINT new_posture) diff --git a/common/src/tx_trace_isr_enter_insert.c b/common/src/tx_trace_isr_enter_insert.c index 9ab427c2..32a5efa9 100644 --- a/common/src/tx_trace_isr_enter_insert.c +++ b/common/src/tx_trace_isr_enter_insert.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_trace_isr_enter_insert PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,6 +68,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ VOID _tx_trace_isr_enter_insert(ULONG isr_id) diff --git a/common/src/tx_trace_isr_exit_insert.c b/common/src/tx_trace_isr_exit_insert.c index ef484c3b..5b6866a6 100644 --- a/common/src/tx_trace_isr_exit_insert.c +++ b/common/src/tx_trace_isr_exit_insert.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_trace_isr_exit_insert PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,6 +68,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ VOID _tx_trace_isr_exit_insert(ULONG isr_id) diff --git a/common/src/tx_trace_object_register.c b/common/src/tx_trace_object_register.c index f4cee525..e0d24981 100644 --- a/common/src/tx_trace_object_register.c +++ b/common/src/tx_trace_object_register.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_trace_object_register PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,6 +70,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ VOID _tx_trace_object_register(UCHAR object_type, VOID *object_ptr, CHAR *object_name, ULONG parameter_1, ULONG parameter_2) diff --git a/common/src/tx_trace_object_unregister.c b/common/src/tx_trace_object_unregister.c index abdc4bc1..ea90e75b 100644 --- a/common/src/tx_trace_object_unregister.c +++ b/common/src/tx_trace_object_unregister.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_trace_object_unregister PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -65,6 +65,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ VOID _tx_trace_object_unregister(VOID *object_ptr) diff --git a/common/src/tx_trace_user_event_insert.c b/common/src/tx_trace_user_event_insert.c index 5e21ff64..51ad9c3f 100644 --- a/common/src/tx_trace_user_event_insert.c +++ b/common/src/tx_trace_user_event_insert.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_trace_user_event_insert PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,6 +68,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _tx_trace_user_event_insert(ULONG event_id, ULONG info_field_1, ULONG info_field_2, ULONG info_field_3, ULONG info_field_4) diff --git a/common/src/txe_block_allocate.c b/common/src/txe_block_allocate.c index e100758f..0ce09d99 100644 --- a/common/src/txe_block_allocate.c +++ b/common/src/txe_block_allocate.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_block_allocate PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -73,6 +73,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_block_allocate(TX_BLOCK_POOL *pool_ptr, VOID **block_ptr, ULONG wait_option) diff --git a/common/src/txe_block_pool_create.c b/common/src/txe_block_pool_create.c index 7aba85ac..07146e36 100644 --- a/common/src/txe_block_pool_create.c +++ b/common/src/txe_block_pool_create.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_block_pool_create PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -78,6 +78,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_block_pool_create(TX_BLOCK_POOL *pool_ptr, CHAR *name_ptr, ULONG block_size, diff --git a/common/src/txe_block_pool_delete.c b/common/src/txe_block_pool_delete.c index dc18a69a..42342568 100644 --- a/common/src/txe_block_pool_delete.c +++ b/common/src/txe_block_pool_delete.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_block_pool_delete PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,6 +69,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_block_pool_delete(TX_BLOCK_POOL *pool_ptr) diff --git a/common/src/txe_block_pool_info_get.c b/common/src/txe_block_pool_info_get.c index 631a5529..d03a8c6d 100644 --- a/common/src/txe_block_pool_info_get.c +++ b/common/src/txe_block_pool_info_get.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_block_pool_info_get PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -74,6 +74,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_block_pool_info_get(TX_BLOCK_POOL *pool_ptr, CHAR **name, ULONG *available_blocks, diff --git a/common/src/txe_block_pool_prioritize.c b/common/src/txe_block_pool_prioritize.c index da32a9e8..5d9088d5 100644 --- a/common/src/txe_block_pool_prioritize.c +++ b/common/src/txe_block_pool_prioritize.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_block_pool_prioritize PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -65,6 +65,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_block_pool_prioritize(TX_BLOCK_POOL *pool_ptr) diff --git a/common/src/txe_block_release.c b/common/src/txe_block_release.c index 54914be0..908e3f6f 100644 --- a/common/src/txe_block_release.c +++ b/common/src/txe_block_release.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_block_release PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -65,6 +65,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_block_release(VOID *block_ptr) diff --git a/common/src/txe_byte_allocate.c b/common/src/txe_byte_allocate.c index 5f374024..5f48dbc6 100644 --- a/common/src/txe_byte_allocate.c +++ b/common/src/txe_byte_allocate.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_byte_allocate PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -76,6 +76,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_byte_allocate(TX_BYTE_POOL *pool_ptr, VOID **memory_ptr, diff --git a/common/src/txe_byte_pool_create.c b/common/src/txe_byte_pool_create.c index 9a45d76b..324160b8 100644 --- a/common/src/txe_byte_pool_create.c +++ b/common/src/txe_byte_pool_create.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_byte_pool_create PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -77,6 +77,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_byte_pool_create(TX_BYTE_POOL *pool_ptr, CHAR *name_ptr, VOID *pool_start, ULONG pool_size, UINT pool_control_block_size) diff --git a/common/src/txe_byte_pool_delete.c b/common/src/txe_byte_pool_delete.c index b3d8a505..29e3d30b 100644 --- a/common/src/txe_byte_pool_delete.c +++ b/common/src/txe_byte_pool_delete.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_byte_pool_delete PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,6 +69,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_byte_pool_delete(TX_BYTE_POOL *pool_ptr) diff --git a/common/src/txe_byte_pool_info_get.c b/common/src/txe_byte_pool_info_get.c index cd735df8..b2b97096 100644 --- a/common/src/txe_byte_pool_info_get.c +++ b/common/src/txe_byte_pool_info_get.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_byte_pool_info_get PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -74,6 +74,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_byte_pool_info_get(TX_BYTE_POOL *pool_ptr, CHAR **name, ULONG *available_bytes, diff --git a/common/src/txe_byte_pool_prioritize.c b/common/src/txe_byte_pool_prioritize.c index 18e7e4b4..aa64f7c3 100644 --- a/common/src/txe_byte_pool_prioritize.c +++ b/common/src/txe_byte_pool_prioritize.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_byte_pool_prioritize PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -65,6 +65,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_byte_pool_prioritize(TX_BYTE_POOL *pool_ptr) diff --git a/common/src/txe_byte_release.c b/common/src/txe_byte_release.c index c7a11714..4a181145 100644 --- a/common/src/txe_byte_release.c +++ b/common/src/txe_byte_release.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_byte_release PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,6 +69,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_byte_release(VOID *memory_ptr) diff --git a/common/src/txe_event_flags_create.c b/common/src/txe_event_flags_create.c index ed2038ee..8ee2f44a 100644 --- a/common/src/txe_event_flags_create.c +++ b/common/src/txe_event_flags_create.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_event_flags_create PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -74,6 +74,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_event_flags_create(TX_EVENT_FLAGS_GROUP *group_ptr, CHAR *name_ptr, UINT event_control_block_size) diff --git a/common/src/txe_event_flags_delete.c b/common/src/txe_event_flags_delete.c index ebe73938..0a4fc127 100644 --- a/common/src/txe_event_flags_delete.c +++ b/common/src/txe_event_flags_delete.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_event_flags_delete PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,6 +69,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_event_flags_delete(TX_EVENT_FLAGS_GROUP *group_ptr) diff --git a/common/src/txe_event_flags_get.c b/common/src/txe_event_flags_get.c index 3ded965f..c67becce 100644 --- a/common/src/txe_event_flags_get.c +++ b/common/src/txe_event_flags_get.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_event_flags_get PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -77,6 +77,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_event_flags_get(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG requested_flags, diff --git a/common/src/txe_event_flags_info_get.c b/common/src/txe_event_flags_info_get.c index 6abfeb79..ac96f7ee 100644 --- a/common/src/txe_event_flags_info_get.c +++ b/common/src/txe_event_flags_info_get.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_event_flags_info_get PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -76,6 +76,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_event_flags_info_get(TX_EVENT_FLAGS_GROUP *group_ptr, CHAR **name, ULONG *current_flags, diff --git a/common/src/txe_event_flags_set.c b/common/src/txe_event_flags_set.c index a0e97bb8..bafdf020 100644 --- a/common/src/txe_event_flags_set.c +++ b/common/src/txe_event_flags_set.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_event_flags_set PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,6 +70,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_event_flags_set(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG flags_to_set, UINT set_option) diff --git a/common/src/txe_event_flags_set_notify.c b/common/src/txe_event_flags_set_notify.c index 621848be..23d59010 100644 --- a/common/src/txe_event_flags_set_notify.c +++ b/common/src/txe_event_flags_set_notify.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_event_flags_set_notify PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,6 +68,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_event_flags_set_notify(TX_EVENT_FLAGS_GROUP *group_ptr, VOID (*events_set_notify)(TX_EVENT_FLAGS_GROUP *notify_group_ptr)) diff --git a/common/src/txe_mutex_create.c b/common/src/txe_mutex_create.c index 76f9a215..64ae1e28 100644 --- a/common/src/txe_mutex_create.c +++ b/common/src/txe_mutex_create.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_mutex_create PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -75,6 +75,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_mutex_create(TX_MUTEX *mutex_ptr, CHAR *name_ptr, UINT inherit, UINT mutex_control_block_size) diff --git a/common/src/txe_mutex_delete.c b/common/src/txe_mutex_delete.c index de5ff718..8f174f0a 100644 --- a/common/src/txe_mutex_delete.c +++ b/common/src/txe_mutex_delete.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_mutex_delete PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,6 +69,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_mutex_delete(TX_MUTEX *mutex_ptr) diff --git a/common/src/txe_mutex_get.c b/common/src/txe_mutex_get.c index c1a81601..3ca1a1b3 100644 --- a/common/src/txe_mutex_get.c +++ b/common/src/txe_mutex_get.c @@ -39,7 +39,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_mutex_get PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -72,6 +72,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_mutex_get(TX_MUTEX *mutex_ptr, ULONG wait_option) diff --git a/common/src/txe_mutex_info_get.c b/common/src/txe_mutex_info_get.c index 853c7470..439295b3 100644 --- a/common/src/txe_mutex_info_get.c +++ b/common/src/txe_mutex_info_get.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_mutex_info_get PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -75,6 +75,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_mutex_info_get(TX_MUTEX *mutex_ptr, CHAR **name, ULONG *count, TX_THREAD **owner, diff --git a/common/src/txe_mutex_prioritize.c b/common/src/txe_mutex_prioritize.c index 9df7065a..cf230eb8 100644 --- a/common/src/txe_mutex_prioritize.c +++ b/common/src/txe_mutex_prioritize.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_mutex_prioritize PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -65,6 +65,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_mutex_prioritize(TX_MUTEX *mutex_ptr) diff --git a/common/src/txe_mutex_put.c b/common/src/txe_mutex_put.c index 16de56e1..e7b711a3 100644 --- a/common/src/txe_mutex_put.c +++ b/common/src/txe_mutex_put.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_mutex_put PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,6 +67,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_mutex_put(TX_MUTEX *mutex_ptr) diff --git a/common/src/txe_queue_create.c b/common/src/txe_queue_create.c index 006386f3..8a7d0beb 100644 --- a/common/src/txe_queue_create.c +++ b/common/src/txe_queue_create.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_queue_create PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -76,6 +76,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_queue_create(TX_QUEUE *queue_ptr, CHAR *name_ptr, UINT message_size, diff --git a/common/src/txe_queue_delete.c b/common/src/txe_queue_delete.c index 75a63778..df897d7f 100644 --- a/common/src/txe_queue_delete.c +++ b/common/src/txe_queue_delete.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_queue_delete PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,6 +68,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_queue_delete(TX_QUEUE *queue_ptr) diff --git a/common/src/txe_queue_flush.c b/common/src/txe_queue_flush.c index 09a658f4..87f3469e 100644 --- a/common/src/txe_queue_flush.c +++ b/common/src/txe_queue_flush.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_queue_flush PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -66,6 +66,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_queue_flush(TX_QUEUE *queue_ptr) diff --git a/common/src/txe_queue_front_send.c b/common/src/txe_queue_front_send.c index 91c1eee0..aa0361d2 100644 --- a/common/src/txe_queue_front_send.c +++ b/common/src/txe_queue_front_send.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_queue_front_send PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -71,6 +71,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_queue_front_send(TX_QUEUE *queue_ptr, VOID *source_ptr, ULONG wait_option) diff --git a/common/src/txe_queue_info_get.c b/common/src/txe_queue_info_get.c index 0e05cf5a..256c186a 100644 --- a/common/src/txe_queue_info_get.c +++ b/common/src/txe_queue_info_get.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_queue_info_get PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -74,6 +74,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_queue_info_get(TX_QUEUE *queue_ptr, CHAR **name, ULONG *enqueued, ULONG *available_storage, diff --git a/common/src/txe_queue_prioritize.c b/common/src/txe_queue_prioritize.c index 2a40fe36..ca91c762 100644 --- a/common/src/txe_queue_prioritize.c +++ b/common/src/txe_queue_prioritize.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_queue_prioritize PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -64,6 +64,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_queue_prioritize(TX_QUEUE *queue_ptr) diff --git a/common/src/txe_queue_receive.c b/common/src/txe_queue_receive.c index 93af544d..5373d1ef 100644 --- a/common/src/txe_queue_receive.c +++ b/common/src/txe_queue_receive.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_queue_receive PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -73,6 +73,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_queue_receive(TX_QUEUE *queue_ptr, VOID *destination_ptr, ULONG wait_option) diff --git a/common/src/txe_queue_send.c b/common/src/txe_queue_send.c index 2a568742..660ea7fe 100644 --- a/common/src/txe_queue_send.c +++ b/common/src/txe_queue_send.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_queue_send PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -71,6 +71,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_queue_send(TX_QUEUE *queue_ptr, VOID *source_ptr, ULONG wait_option) diff --git a/common/src/txe_queue_send_notify.c b/common/src/txe_queue_send_notify.c index a6c0d746..b90ff386 100644 --- a/common/src/txe_queue_send_notify.c +++ b/common/src/txe_queue_send_notify.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_queue_send_notify PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,6 +67,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_queue_send_notify(TX_QUEUE *queue_ptr, VOID (*queue_send_notify)(TX_QUEUE *notify_queue_ptr)) diff --git a/common/src/txe_semaphore_ceiling_put.c b/common/src/txe_semaphore_ceiling_put.c index e404d4c7..1cfcc7cb 100644 --- a/common/src/txe_semaphore_ceiling_put.c +++ b/common/src/txe_semaphore_ceiling_put.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_semaphore_ceiling_put PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,6 +69,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_semaphore_ceiling_put(TX_SEMAPHORE *semaphore_ptr, ULONG ceiling) diff --git a/common/src/txe_semaphore_create.c b/common/src/txe_semaphore_create.c index 9cb9ac61..290cb4fb 100644 --- a/common/src/txe_semaphore_create.c +++ b/common/src/txe_semaphore_create.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_semaphore_create PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -74,6 +74,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_semaphore_create(TX_SEMAPHORE *semaphore_ptr, CHAR *name_ptr, ULONG initial_count, UINT semaphore_control_block_size) diff --git a/common/src/txe_semaphore_delete.c b/common/src/txe_semaphore_delete.c index 9036373d..0b4a3293 100644 --- a/common/src/txe_semaphore_delete.c +++ b/common/src/txe_semaphore_delete.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_semaphore_delete PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,6 +69,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_semaphore_delete(TX_SEMAPHORE *semaphore_ptr) diff --git a/common/src/txe_semaphore_get.c b/common/src/txe_semaphore_get.c index 10f37e59..90092173 100644 --- a/common/src/txe_semaphore_get.c +++ b/common/src/txe_semaphore_get.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_semaphore_get PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,6 +69,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_semaphore_get(TX_SEMAPHORE *semaphore_ptr, ULONG wait_option) diff --git a/common/src/txe_semaphore_info_get.c b/common/src/txe_semaphore_info_get.c index 35e88f79..85fd11b9 100644 --- a/common/src/txe_semaphore_info_get.c +++ b/common/src/txe_semaphore_info_get.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_semaphore_info_get PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -74,6 +74,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_semaphore_info_get(TX_SEMAPHORE *semaphore_ptr, CHAR **name, ULONG *current_value, diff --git a/common/src/txe_semaphore_prioritize.c b/common/src/txe_semaphore_prioritize.c index eb980d21..3672a485 100644 --- a/common/src/txe_semaphore_prioritize.c +++ b/common/src/txe_semaphore_prioritize.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_semaphore_prioritize PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -65,6 +65,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_semaphore_prioritize(TX_SEMAPHORE *semaphore_ptr) diff --git a/common/src/txe_semaphore_put.c b/common/src/txe_semaphore_put.c index dd35addd..42b00240 100644 --- a/common/src/txe_semaphore_put.c +++ b/common/src/txe_semaphore_put.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_semaphore_put PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -65,6 +65,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_semaphore_put(TX_SEMAPHORE *semaphore_ptr) diff --git a/common/src/txe_semaphore_put_notify.c b/common/src/txe_semaphore_put_notify.c index d9794f5a..b6faa50e 100644 --- a/common/src/txe_semaphore_put_notify.c +++ b/common/src/txe_semaphore_put_notify.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_semaphore_put_notify PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,6 +68,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_semaphore_put_notify(TX_SEMAPHORE *semaphore_ptr, VOID (*semaphore_put_notify)(TX_SEMAPHORE *notify_semaphore_ptr)) diff --git a/common/src/txe_thread_create.c b/common/src/txe_thread_create.c index 12b67017..9eaa7b27 100644 --- a/common/src/txe_thread_create.c +++ b/common/src/txe_thread_create.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_create PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -83,6 +83,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_create(TX_THREAD *thread_ptr, CHAR *name_ptr, diff --git a/common/src/txe_thread_delete.c b/common/src/txe_thread_delete.c index f85209be..55b98abe 100644 --- a/common/src/txe_thread_delete.c +++ b/common/src/txe_thread_delete.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_delete PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -66,6 +66,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_delete(TX_THREAD *thread_ptr) diff --git a/common/src/txe_thread_entry_exit_notify.c b/common/src/txe_thread_entry_exit_notify.c index 1f71e3ff..84e359e0 100644 --- a/common/src/txe_thread_entry_exit_notify.c +++ b/common/src/txe_thread_entry_exit_notify.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_entry_exit_notify PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,6 +68,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_entry_exit_notify(TX_THREAD *thread_ptr, VOID (*thread_entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT type)) diff --git a/common/src/txe_thread_info_get.c b/common/src/txe_thread_info_get.c index 24365329..5cd51539 100644 --- a/common/src/txe_thread_info_get.c +++ b/common/src/txe_thread_info_get.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_info_get PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -78,6 +78,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_info_get(TX_THREAD *thread_ptr, CHAR **name, UINT *state, ULONG *run_count, diff --git a/common/src/txe_thread_preemption_change.c b/common/src/txe_thread_preemption_change.c index d3cc4fd3..ab813372 100644 --- a/common/src/txe_thread_preemption_change.c +++ b/common/src/txe_thread_preemption_change.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_preemption_change PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,6 +70,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_preemption_change(TX_THREAD *thread_ptr, UINT new_threshold, UINT *old_threshold) diff --git a/common/src/txe_thread_priority_change.c b/common/src/txe_thread_priority_change.c index f4160d13..5e0bda5c 100644 --- a/common/src/txe_thread_priority_change.c +++ b/common/src/txe_thread_priority_change.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_priority_change PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -71,6 +71,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_priority_change(TX_THREAD *thread_ptr, UINT new_priority, UINT *old_priority) diff --git a/common/src/txe_thread_relinquish.c b/common/src/txe_thread_relinquish.c index 6f7733c4..09569fe3 100644 --- a/common/src/txe_thread_relinquish.c +++ b/common/src/txe_thread_relinquish.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_relinquish PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -65,6 +65,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ VOID _txe_thread_relinquish(VOID) diff --git a/common/src/txe_thread_reset.c b/common/src/txe_thread_reset.c index bef5fa8c..59a1a806 100644 --- a/common/src/txe_thread_reset.c +++ b/common/src/txe_thread_reset.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_reset PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,6 +67,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_reset(TX_THREAD *thread_ptr) diff --git a/common/src/txe_thread_resume.c b/common/src/txe_thread_resume.c index 04255304..20b1b124 100644 --- a/common/src/txe_thread_resume.c +++ b/common/src/txe_thread_resume.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_resume PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -65,6 +65,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_resume(TX_THREAD *thread_ptr) diff --git a/common/src/txe_thread_suspend.c b/common/src/txe_thread_suspend.c index eb8e24c3..f368d4ea 100644 --- a/common/src/txe_thread_suspend.c +++ b/common/src/txe_thread_suspend.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_suspend PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,6 +67,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_suspend(TX_THREAD *thread_ptr) diff --git a/common/src/txe_thread_terminate.c b/common/src/txe_thread_terminate.c index 5531a378..2c4ab926 100644 --- a/common/src/txe_thread_terminate.c +++ b/common/src/txe_thread_terminate.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_terminate PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,6 +68,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_terminate(TX_THREAD *thread_ptr) diff --git a/common/src/txe_thread_time_slice_change.c b/common/src/txe_thread_time_slice_change.c index e024dd13..a4b4df83 100644 --- a/common/src/txe_thread_time_slice_change.c +++ b/common/src/txe_thread_time_slice_change.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_time_slice_change PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,6 +70,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_time_slice_change(TX_THREAD *thread_ptr, ULONG new_time_slice, ULONG *old_time_slice) diff --git a/common/src/txe_thread_wait_abort.c b/common/src/txe_thread_wait_abort.c index 831b3f84..45dc9394 100644 --- a/common/src/txe_thread_wait_abort.c +++ b/common/src/txe_thread_wait_abort.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_wait_abort PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -65,6 +65,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_wait_abort(TX_THREAD *thread_ptr) diff --git a/common/src/txe_timer_activate.c b/common/src/txe_timer_activate.c index 5938a428..76a8062e 100644 --- a/common/src/txe_timer_activate.c +++ b/common/src/txe_timer_activate.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_timer_activate PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,6 +67,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_timer_activate(TX_TIMER *timer_ptr) diff --git a/common/src/txe_timer_change.c b/common/src/txe_timer_change.c index 7be337f9..a13affcb 100644 --- a/common/src/txe_timer_change.c +++ b/common/src/txe_timer_change.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_timer_change PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -72,6 +72,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_timer_change(TX_TIMER *timer_ptr, ULONG initial_ticks, ULONG reschedule_ticks) diff --git a/common/src/txe_timer_create.c b/common/src/txe_timer_create.c index 6397a801..7d7d469f 100644 --- a/common/src/txe_timer_create.c +++ b/common/src/txe_timer_create.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_timer_create PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -78,6 +78,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_timer_create(TX_TIMER *timer_ptr, CHAR *name_ptr, diff --git a/common/src/txe_timer_deactivate.c b/common/src/txe_timer_deactivate.c index 5c1e620b..b6ddcd24 100644 --- a/common/src/txe_timer_deactivate.c +++ b/common/src/txe_timer_deactivate.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_timer_deactivate PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -66,6 +66,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_timer_deactivate(TX_TIMER *timer_ptr) diff --git a/common/src/txe_timer_delete.c b/common/src/txe_timer_delete.c index 21debdf1..29a40683 100644 --- a/common/src/txe_timer_delete.c +++ b/common/src/txe_timer_delete.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_timer_delete PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,6 +68,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_timer_delete(TX_TIMER *timer_ptr) diff --git a/common/src/txe_timer_info_get.c b/common/src/txe_timer_info_get.c index 66d311c1..d4840e67 100644 --- a/common/src/txe_timer_info_get.c +++ b/common/src/txe_timer_info_get.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_timer_info_get PORTABLE C */ -/* 6.0 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -73,6 +73,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ UINT _txe_timer_info_get(TX_TIMER *timer_ptr, CHAR **name, UINT *active, ULONG *remaining_ticks, diff --git a/common_modules/inc/txm_module.h b/common_modules/inc/txm_module.h index 8625cf40..bac2c581 100644 --- a/common_modules/inc/txm_module.h +++ b/common_modules/inc/txm_module.h @@ -26,7 +26,7 @@ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ /* txm_module.h PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -40,7 +40,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ diff --git a/common_modules/inc/txm_module_user.h b/common_modules/inc/txm_module_user.h index b6cf1788..3587eea3 100644 --- a/common_modules/inc/txm_module_user.h +++ b/common_modules/inc/txm_module_user.h @@ -26,7 +26,7 @@ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ /* txm_module_user.h PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -44,7 +44,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ diff --git a/common_modules/module_lib/src/txm_block_allocate.c b/common_modules/module_lib/src/txm_block_allocate.c index 9c1e1054..c3a8d92a 100644 --- a/common_modules/module_lib/src/txm_block_allocate.c +++ b/common_modules/module_lib/src/txm_block_allocate.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_block_allocate PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -64,7 +64,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_block_allocate(TX_BLOCK_POOL *pool_ptr, VOID **block_ptr, ULONG wait_option) diff --git a/common_modules/module_lib/src/txm_block_pool_create.c b/common_modules/module_lib/src/txm_block_pool_create.c index 897a863e..5b550aaa 100644 --- a/common_modules/module_lib/src/txm_block_pool_create.c +++ b/common_modules/module_lib/src/txm_block_pool_create.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_block_pool_create PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -67,7 +67,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_block_pool_create(TX_BLOCK_POOL *pool_ptr, CHAR *name_ptr, ULONG block_size, VOID *pool_start, ULONG pool_size, UINT pool_control_block_size) diff --git a/common_modules/module_lib/src/txm_block_pool_delete.c b/common_modules/module_lib/src/txm_block_pool_delete.c index 9b0436eb..89b1d064 100644 --- a/common_modules/module_lib/src/txm_block_pool_delete.c +++ b/common_modules/module_lib/src/txm_block_pool_delete.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_block_pool_delete PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_block_pool_delete(TX_BLOCK_POOL *pool_ptr) diff --git a/common_modules/module_lib/src/txm_block_pool_info_get.c b/common_modules/module_lib/src/txm_block_pool_info_get.c index 40489186..f5a221b2 100644 --- a/common_modules/module_lib/src/txm_block_pool_info_get.c +++ b/common_modules/module_lib/src/txm_block_pool_info_get.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_block_pool_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -67,7 +67,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_block_pool_info_get(TX_BLOCK_POOL *pool_ptr, CHAR **name, ULONG *available_blocks, ULONG *total_blocks, TX_THREAD **first_suspended, ULONG *suspended_count, TX_BLOCK_POOL **next_pool) diff --git a/common_modules/module_lib/src/txm_block_pool_performance_info_get.c b/common_modules/module_lib/src/txm_block_pool_performance_info_get.c index 7441e4aa..4d040bb1 100644 --- a/common_modules/module_lib/src/txm_block_pool_performance_info_get.c +++ b/common_modules/module_lib/src/txm_block_pool_performance_info_get.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_block_pool_performance_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -66,7 +66,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_block_pool_performance_info_get(TX_BLOCK_POOL *pool_ptr, ULONG *allocates, ULONG *releases, ULONG *suspensions, ULONG *timeouts) diff --git a/common_modules/module_lib/src/txm_block_pool_performance_system_info_get.c b/common_modules/module_lib/src/txm_block_pool_performance_system_info_get.c index d37da4e8..0603a960 100644 --- a/common_modules/module_lib/src/txm_block_pool_performance_system_info_get.c +++ b/common_modules/module_lib/src/txm_block_pool_performance_system_info_get.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_block_pool_performance_system_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -64,7 +64,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_block_pool_performance_system_info_get(ULONG *allocates, ULONG *releases, ULONG *suspensions, ULONG *timeouts) diff --git a/common_modules/module_lib/src/txm_block_pool_prioritize.c b/common_modules/module_lib/src/txm_block_pool_prioritize.c index 05c2bbd8..67b0b4a2 100644 --- a/common_modules/module_lib/src/txm_block_pool_prioritize.c +++ b/common_modules/module_lib/src/txm_block_pool_prioritize.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_block_pool_prioritize PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -57,7 +57,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_block_pool_prioritize(TX_BLOCK_POOL *pool_ptr) diff --git a/common_modules/module_lib/src/txm_block_release.c b/common_modules/module_lib/src/txm_block_release.c index 2b644943..370f8821 100644 --- a/common_modules/module_lib/src/txm_block_release.c +++ b/common_modules/module_lib/src/txm_block_release.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_block_release PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_block_release(VOID *block_ptr) diff --git a/common_modules/module_lib/src/txm_byte_allocate.c b/common_modules/module_lib/src/txm_byte_allocate.c index bf9da24d..193c7868 100644 --- a/common_modules/module_lib/src/txm_byte_allocate.c +++ b/common_modules/module_lib/src/txm_byte_allocate.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_byte_allocate PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -66,7 +66,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_byte_allocate(TX_BYTE_POOL *pool_ptr, VOID **memory_ptr, ULONG memory_size, ULONG wait_option) diff --git a/common_modules/module_lib/src/txm_byte_pool_create.c b/common_modules/module_lib/src/txm_byte_pool_create.c index c2b02c0b..170892ad 100644 --- a/common_modules/module_lib/src/txm_byte_pool_create.c +++ b/common_modules/module_lib/src/txm_byte_pool_create.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_byte_pool_create PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -66,7 +66,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_byte_pool_create(TX_BYTE_POOL *pool_ptr, CHAR *name_ptr, VOID *pool_start, ULONG pool_size, UINT pool_control_block_size) diff --git a/common_modules/module_lib/src/txm_byte_pool_delete.c b/common_modules/module_lib/src/txm_byte_pool_delete.c index 5616cfb4..3160fa91 100644 --- a/common_modules/module_lib/src/txm_byte_pool_delete.c +++ b/common_modules/module_lib/src/txm_byte_pool_delete.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_byte_pool_delete PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_byte_pool_delete(TX_BYTE_POOL *pool_ptr) diff --git a/common_modules/module_lib/src/txm_byte_pool_info_get.c b/common_modules/module_lib/src/txm_byte_pool_info_get.c index 2ff97682..29d246c7 100644 --- a/common_modules/module_lib/src/txm_byte_pool_info_get.c +++ b/common_modules/module_lib/src/txm_byte_pool_info_get.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_byte_pool_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -67,7 +67,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_byte_pool_info_get(TX_BYTE_POOL *pool_ptr, CHAR **name, ULONG *available_bytes, ULONG *fragments, TX_THREAD **first_suspended, ULONG *suspended_count, TX_BYTE_POOL **next_pool) diff --git a/common_modules/module_lib/src/txm_byte_pool_performance_info_get.c b/common_modules/module_lib/src/txm_byte_pool_performance_info_get.c index 2ac466b7..fde49fdb 100644 --- a/common_modules/module_lib/src/txm_byte_pool_performance_info_get.c +++ b/common_modules/module_lib/src/txm_byte_pool_performance_info_get.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_byte_pool_performance_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -74,7 +74,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_byte_pool_performance_info_get(TX_BYTE_POOL *pool_ptr, ULONG *allocates, ULONG *releases, ULONG *fragments_searched, ULONG *merges, ULONG *splits, ULONG *suspensions, ULONG *timeouts) diff --git a/common_modules/module_lib/src/txm_byte_pool_performance_system_info_get.c b/common_modules/module_lib/src/txm_byte_pool_performance_system_info_get.c index 3b3b8b59..3bceabfa 100644 --- a/common_modules/module_lib/src/txm_byte_pool_performance_system_info_get.c +++ b/common_modules/module_lib/src/txm_byte_pool_performance_system_info_get.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_byte_pool_performance_system_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -72,7 +72,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_byte_pool_performance_system_info_get(ULONG *allocates, ULONG *releases, ULONG *fragments_searched, ULONG *merges, ULONG *splits, ULONG *suspensions, ULONG *timeouts) diff --git a/common_modules/module_lib/src/txm_byte_pool_prioritize.c b/common_modules/module_lib/src/txm_byte_pool_prioritize.c index 94dfa607..268a6f2f 100644 --- a/common_modules/module_lib/src/txm_byte_pool_prioritize.c +++ b/common_modules/module_lib/src/txm_byte_pool_prioritize.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_byte_pool_prioritize PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -57,7 +57,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_byte_pool_prioritize(TX_BYTE_POOL *pool_ptr) diff --git a/common_modules/module_lib/src/txm_byte_release.c b/common_modules/module_lib/src/txm_byte_release.c index 31b32848..2dbb8998 100644 --- a/common_modules/module_lib/src/txm_byte_release.c +++ b/common_modules/module_lib/src/txm_byte_release.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_byte_release PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,7 +59,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_byte_release(VOID *memory_ptr) diff --git a/common_modules/module_lib/src/txm_event_flags_create.c b/common_modules/module_lib/src/txm_event_flags_create.c index a0ae4eb6..cec86527 100644 --- a/common_modules/module_lib/src/txm_event_flags_create.c +++ b/common_modules/module_lib/src/txm_event_flags_create.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_event_flags_create PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -63,7 +63,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_event_flags_create(TX_EVENT_FLAGS_GROUP *group_ptr, CHAR *name_ptr, UINT event_control_block_size) diff --git a/common_modules/module_lib/src/txm_event_flags_delete.c b/common_modules/module_lib/src/txm_event_flags_delete.c index fccb74b0..e69270c5 100644 --- a/common_modules/module_lib/src/txm_event_flags_delete.c +++ b/common_modules/module_lib/src/txm_event_flags_delete.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_event_flags_delete PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_event_flags_delete(TX_EVENT_FLAGS_GROUP *group_ptr) diff --git a/common_modules/module_lib/src/txm_event_flags_get.c b/common_modules/module_lib/src/txm_event_flags_get.c index 792826d5..7006bbe8 100644 --- a/common_modules/module_lib/src/txm_event_flags_get.c +++ b/common_modules/module_lib/src/txm_event_flags_get.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_event_flags_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_event_flags_get(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG requested_flags, UINT get_option, ULONG *actual_flags_ptr, ULONG wait_option) diff --git a/common_modules/module_lib/src/txm_event_flags_info_get.c b/common_modules/module_lib/src/txm_event_flags_info_get.c index 5242503e..9861dab1 100644 --- a/common_modules/module_lib/src/txm_event_flags_info_get.c +++ b/common_modules/module_lib/src/txm_event_flags_info_get.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_event_flags_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_event_flags_info_get(TX_EVENT_FLAGS_GROUP *group_ptr, CHAR **name, ULONG *current_flags, TX_THREAD **first_suspended, ULONG *suspended_count, TX_EVENT_FLAGS_GROUP **next_group) diff --git a/common_modules/module_lib/src/txm_event_flags_performance_info_get.c b/common_modules/module_lib/src/txm_event_flags_performance_info_get.c index dfc6b0fa..43a7cf26 100644 --- a/common_modules/module_lib/src/txm_event_flags_performance_info_get.c +++ b/common_modules/module_lib/src/txm_event_flags_performance_info_get.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_event_flags_performance_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -67,7 +67,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_event_flags_performance_info_get(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG *sets, ULONG *gets, ULONG *suspensions, ULONG *timeouts) diff --git a/common_modules/module_lib/src/txm_event_flags_performance_system_info_get.c b/common_modules/module_lib/src/txm_event_flags_performance_system_info_get.c index 840f2d00..387cd262 100644 --- a/common_modules/module_lib/src/txm_event_flags_performance_system_info_get.c +++ b/common_modules/module_lib/src/txm_event_flags_performance_system_info_get.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_event_flags_performance_system_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -64,7 +64,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_event_flags_performance_system_info_get(ULONG *sets, ULONG *gets, ULONG *suspensions, ULONG *timeouts) diff --git a/common_modules/module_lib/src/txm_event_flags_set.c b/common_modules/module_lib/src/txm_event_flags_set.c index 182e4eed..5d204ec0 100644 --- a/common_modules/module_lib/src/txm_event_flags_set.c +++ b/common_modules/module_lib/src/txm_event_flags_set.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_event_flags_set PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -63,7 +63,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_event_flags_set(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG flags_to_set, UINT set_option) diff --git a/common_modules/module_lib/src/txm_event_flags_set_notify.c b/common_modules/module_lib/src/txm_event_flags_set_notify.c index 99816859..f72b92a6 100644 --- a/common_modules/module_lib/src/txm_event_flags_set_notify.c +++ b/common_modules/module_lib/src/txm_event_flags_set_notify.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_event_flags_set_notify PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_event_flags_set_notify(TX_EVENT_FLAGS_GROUP *group_ptr, VOID (*events_set_notify)(TX_EVENT_FLAGS_GROUP *)) diff --git a/common_modules/module_lib/src/txm_module_application_request.c b/common_modules/module_lib/src/txm_module_application_request.c index 8e397c89..b84b8f2c 100644 --- a/common_modules/module_lib/src/txm_module_application_request.c +++ b/common_modules/module_lib/src/txm_module_application_request.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* txm_module_application_request PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT txm_module_application_request(ULONG request, ALIGN_TYPE param_1, ALIGN_TYPE param_2, ALIGN_TYPE param_3) diff --git a/common_modules/module_lib/src/txm_module_callback_request_thread_entry.c b/common_modules/module_lib/src/txm_module_callback_request_thread_entry.c index e8ba684d..bbd51104 100644 --- a/common_modules/module_lib/src/txm_module_callback_request_thread_entry.c +++ b/common_modules/module_lib/src/txm_module_callback_request_thread_entry.c @@ -47,7 +47,7 @@ extern TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; /* FUNCTION RELEASE */ /* */ /* _txm_module_callback_request_thread_entry PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -79,7 +79,7 @@ extern TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_callback_request_thread_entry(ULONG id) diff --git a/common_modules/module_lib/src/txm_module_object_allocate.c b/common_modules/module_lib/src/txm_module_object_allocate.c index 3ae4c91f..32757926 100644 --- a/common_modules/module_lib/src/txm_module_object_allocate.c +++ b/common_modules/module_lib/src/txm_module_object_allocate.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_object_allocate PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -63,7 +63,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_object_allocate(VOID **object_ptr, ULONG object_size) diff --git a/common_modules/module_lib/src/txm_module_object_deallocate.c b/common_modules/module_lib/src/txm_module_object_deallocate.c index e3e39bb8..3936a4d8 100644 --- a/common_modules/module_lib/src/txm_module_object_deallocate.c +++ b/common_modules/module_lib/src/txm_module_object_deallocate.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_object_deallocate PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -57,7 +57,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_object_deallocate(VOID *object_ptr) diff --git a/common_modules/module_lib/src/txm_module_object_pointer_get.c b/common_modules/module_lib/src/txm_module_object_pointer_get.c index 81e5fd9b..45160b09 100644 --- a/common_modules/module_lib/src/txm_module_object_pointer_get.c +++ b/common_modules/module_lib/src/txm_module_object_pointer_get.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_object_pointer_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -73,7 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_object_pointer_get(UINT object_type, CHAR *name, VOID **object_ptr) diff --git a/common_modules/module_lib/src/txm_module_object_pointer_get_extended.c b/common_modules/module_lib/src/txm_module_object_pointer_get_extended.c index 987de28a..350ca3af 100644 --- a/common_modules/module_lib/src/txm_module_object_pointer_get_extended.c +++ b/common_modules/module_lib/src/txm_module_object_pointer_get_extended.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_object_pointer_get_extended PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -76,7 +76,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_object_pointer_get_extended(UINT object_type, CHAR *name, UINT name_length, VOID **object_ptr) diff --git a/common_modules/module_lib/src/txm_module_thread_system_suspend.c b/common_modules/module_lib/src/txm_module_thread_system_suspend.c index a94d3863..8121ca4a 100644 --- a/common_modules/module_lib/src/txm_module_thread_system_suspend.c +++ b/common_modules/module_lib/src/txm_module_thread_system_suspend.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_suspend PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -65,7 +65,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_thread_system_suspend(TX_THREAD *thread_ptr) diff --git a/common_modules/module_lib/src/txm_mutex_create.c b/common_modules/module_lib/src/txm_mutex_create.c index 458b964e..a3a89d69 100644 --- a/common_modules/module_lib/src/txm_mutex_create.c +++ b/common_modules/module_lib/src/txm_mutex_create.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_mutex_create PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -64,7 +64,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_mutex_create(TX_MUTEX *mutex_ptr, CHAR *name_ptr, UINT inherit, UINT mutex_control_block_size) diff --git a/common_modules/module_lib/src/txm_mutex_delete.c b/common_modules/module_lib/src/txm_mutex_delete.c index 4773c9c1..6b720f3e 100644 --- a/common_modules/module_lib/src/txm_mutex_delete.c +++ b/common_modules/module_lib/src/txm_mutex_delete.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_mutex_delete PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_mutex_delete(TX_MUTEX *mutex_ptr) diff --git a/common_modules/module_lib/src/txm_mutex_get.c b/common_modules/module_lib/src/txm_mutex_get.c index 2c48dacd..2d7da6ba 100644 --- a/common_modules/module_lib/src/txm_mutex_get.c +++ b/common_modules/module_lib/src/txm_mutex_get.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_mutex_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_mutex_get(TX_MUTEX *mutex_ptr, ULONG wait_option) diff --git a/common_modules/module_lib/src/txm_mutex_info_get.c b/common_modules/module_lib/src/txm_mutex_info_get.c index 9f9c45f9..ea1d1ceb 100644 --- a/common_modules/module_lib/src/txm_mutex_info_get.c +++ b/common_modules/module_lib/src/txm_mutex_info_get.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_mutex_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_mutex_info_get(TX_MUTEX *mutex_ptr, CHAR **name, ULONG *count, TX_THREAD **owner, TX_THREAD **first_suspended, ULONG *suspended_count, TX_MUTEX **next_mutex) diff --git a/common_modules/module_lib/src/txm_mutex_performance_info_get.c b/common_modules/module_lib/src/txm_mutex_performance_info_get.c index 4a7c518b..f6c68e6b 100644 --- a/common_modules/module_lib/src/txm_mutex_performance_info_get.c +++ b/common_modules/module_lib/src/txm_mutex_performance_info_get.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_mutex_performance_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_mutex_performance_info_get(TX_MUTEX *mutex_ptr, ULONG *puts, ULONG *gets, ULONG *suspensions, ULONG *timeouts, ULONG *inversions, ULONG *inheritances) diff --git a/common_modules/module_lib/src/txm_mutex_performance_system_info_get.c b/common_modules/module_lib/src/txm_mutex_performance_system_info_get.c index 09df71e3..577b35e8 100644 --- a/common_modules/module_lib/src/txm_mutex_performance_system_info_get.c +++ b/common_modules/module_lib/src/txm_mutex_performance_system_info_get.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_mutex_performance_system_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_mutex_performance_system_info_get(ULONG *puts, ULONG *gets, ULONG *suspensions, ULONG *timeouts, ULONG *inversions, ULONG *inheritances) diff --git a/common_modules/module_lib/src/txm_mutex_prioritize.c b/common_modules/module_lib/src/txm_mutex_prioritize.c index a499ecfb..a15e8cbb 100644 --- a/common_modules/module_lib/src/txm_mutex_prioritize.c +++ b/common_modules/module_lib/src/txm_mutex_prioritize.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_mutex_prioritize PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -57,7 +57,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_mutex_prioritize(TX_MUTEX *mutex_ptr) diff --git a/common_modules/module_lib/src/txm_mutex_put.c b/common_modules/module_lib/src/txm_mutex_put.c index b49a5ed5..738d08c6 100644 --- a/common_modules/module_lib/src/txm_mutex_put.c +++ b/common_modules/module_lib/src/txm_mutex_put.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_mutex_put PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_mutex_put(TX_MUTEX *mutex_ptr) diff --git a/common_modules/module_lib/src/txm_queue_create.c b/common_modules/module_lib/src/txm_queue_create.c index ea61f29c..a84e8398 100644 --- a/common_modules/module_lib/src/txm_queue_create.c +++ b/common_modules/module_lib/src/txm_queue_create.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_queue_create PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -65,7 +65,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_queue_create(TX_QUEUE *queue_ptr, CHAR *name_ptr, UINT message_size, VOID *queue_start, ULONG queue_size, UINT queue_control_block_size) diff --git a/common_modules/module_lib/src/txm_queue_delete.c b/common_modules/module_lib/src/txm_queue_delete.c index d277e3c0..aae1004e 100644 --- a/common_modules/module_lib/src/txm_queue_delete.c +++ b/common_modules/module_lib/src/txm_queue_delete.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_queue_delete PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,7 +59,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_queue_delete(TX_QUEUE *queue_ptr) diff --git a/common_modules/module_lib/src/txm_queue_flush.c b/common_modules/module_lib/src/txm_queue_flush.c index 22ba4f48..c660e19f 100644 --- a/common_modules/module_lib/src/txm_queue_flush.c +++ b/common_modules/module_lib/src/txm_queue_flush.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_queue_flush PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,7 +59,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_queue_flush(TX_QUEUE *queue_ptr) diff --git a/common_modules/module_lib/src/txm_queue_front_send.c b/common_modules/module_lib/src/txm_queue_front_send.c index 88b847ff..47232930 100644 --- a/common_modules/module_lib/src/txm_queue_front_send.c +++ b/common_modules/module_lib/src/txm_queue_front_send.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_queue_front_send PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -62,7 +62,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_queue_front_send(TX_QUEUE *queue_ptr, VOID *source_ptr, ULONG wait_option) diff --git a/common_modules/module_lib/src/txm_queue_info_get.c b/common_modules/module_lib/src/txm_queue_info_get.c index 5c4147a9..045dd26d 100644 --- a/common_modules/module_lib/src/txm_queue_info_get.c +++ b/common_modules/module_lib/src/txm_queue_info_get.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_queue_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -67,7 +67,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_queue_info_get(TX_QUEUE *queue_ptr, CHAR **name, ULONG *enqueued, ULONG *available_storage, TX_THREAD **first_suspended, ULONG *suspended_count, TX_QUEUE **next_queue) diff --git a/common_modules/module_lib/src/txm_queue_performance_info_get.c b/common_modules/module_lib/src/txm_queue_performance_info_get.c index ace108b6..d68998e9 100644 --- a/common_modules/module_lib/src/txm_queue_performance_info_get.c +++ b/common_modules/module_lib/src/txm_queue_performance_info_get.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_queue_performance_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_queue_performance_info_get(TX_QUEUE *queue_ptr, ULONG *messages_sent, ULONG *messages_received, ULONG *empty_suspensions, ULONG *full_suspensions, ULONG *full_errors, ULONG *timeouts) diff --git a/common_modules/module_lib/src/txm_queue_performance_system_info_get.c b/common_modules/module_lib/src/txm_queue_performance_system_info_get.c index 78840480..8ef7459f 100644 --- a/common_modules/module_lib/src/txm_queue_performance_system_info_get.c +++ b/common_modules/module_lib/src/txm_queue_performance_system_info_get.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_queue_performance_system_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_queue_performance_system_info_get(ULONG *messages_sent, ULONG *messages_received, ULONG *empty_suspensions, ULONG *full_suspensions, ULONG *full_errors, ULONG *timeouts) diff --git a/common_modules/module_lib/src/txm_queue_prioritize.c b/common_modules/module_lib/src/txm_queue_prioritize.c index 8d368808..bd2c1d1d 100644 --- a/common_modules/module_lib/src/txm_queue_prioritize.c +++ b/common_modules/module_lib/src/txm_queue_prioritize.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_queue_prioritize PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -57,7 +57,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_queue_prioritize(TX_QUEUE *queue_ptr) diff --git a/common_modules/module_lib/src/txm_queue_receive.c b/common_modules/module_lib/src/txm_queue_receive.c index dea6bfcd..eaa4fa77 100644 --- a/common_modules/module_lib/src/txm_queue_receive.c +++ b/common_modules/module_lib/src/txm_queue_receive.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_queue_receive PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -64,7 +64,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_queue_receive(TX_QUEUE *queue_ptr, VOID *destination_ptr, ULONG wait_option) diff --git a/common_modules/module_lib/src/txm_queue_send.c b/common_modules/module_lib/src/txm_queue_send.c index 00f9b344..23f97fc2 100644 --- a/common_modules/module_lib/src/txm_queue_send.c +++ b/common_modules/module_lib/src/txm_queue_send.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_queue_send PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -62,7 +62,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_queue_send(TX_QUEUE *queue_ptr, VOID *source_ptr, ULONG wait_option) diff --git a/common_modules/module_lib/src/txm_queue_send_notify.c b/common_modules/module_lib/src/txm_queue_send_notify.c index c4be8e51..fece5a5a 100644 --- a/common_modules/module_lib/src/txm_queue_send_notify.c +++ b/common_modules/module_lib/src/txm_queue_send_notify.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_queue_send_notify PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_queue_send_notify(TX_QUEUE *queue_ptr, VOID (*queue_send_notify)(TX_QUEUE *notify_queue_ptr)) diff --git a/common_modules/module_lib/src/txm_semaphore_ceiling_put.c b/common_modules/module_lib/src/txm_semaphore_ceiling_put.c index 1c7c5967..0b325d72 100644 --- a/common_modules/module_lib/src/txm_semaphore_ceiling_put.c +++ b/common_modules/module_lib/src/txm_semaphore_ceiling_put.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_semaphore_ceiling_put PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_semaphore_ceiling_put(TX_SEMAPHORE *semaphore_ptr, ULONG ceiling) diff --git a/common_modules/module_lib/src/txm_semaphore_create.c b/common_modules/module_lib/src/txm_semaphore_create.c index 31ae876a..c20ac76d 100644 --- a/common_modules/module_lib/src/txm_semaphore_create.c +++ b/common_modules/module_lib/src/txm_semaphore_create.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_semaphore_create PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -63,7 +63,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_semaphore_create(TX_SEMAPHORE *semaphore_ptr, CHAR *name_ptr, ULONG initial_count, UINT semaphore_control_block_size) diff --git a/common_modules/module_lib/src/txm_semaphore_delete.c b/common_modules/module_lib/src/txm_semaphore_delete.c index 7180584a..1fa5bf5f 100644 --- a/common_modules/module_lib/src/txm_semaphore_delete.c +++ b/common_modules/module_lib/src/txm_semaphore_delete.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_semaphore_delete PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_semaphore_delete(TX_SEMAPHORE *semaphore_ptr) diff --git a/common_modules/module_lib/src/txm_semaphore_get.c b/common_modules/module_lib/src/txm_semaphore_get.c index b447d32f..f7ecd3e5 100644 --- a/common_modules/module_lib/src/txm_semaphore_get.c +++ b/common_modules/module_lib/src/txm_semaphore_get.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_semaphore_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_semaphore_get(TX_SEMAPHORE *semaphore_ptr, ULONG wait_option) diff --git a/common_modules/module_lib/src/txm_semaphore_info_get.c b/common_modules/module_lib/src/txm_semaphore_info_get.c index 7c82c619..cd2cac80 100644 --- a/common_modules/module_lib/src/txm_semaphore_info_get.c +++ b/common_modules/module_lib/src/txm_semaphore_info_get.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_semaphore_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -67,7 +67,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_semaphore_info_get(TX_SEMAPHORE *semaphore_ptr, CHAR **name, ULONG *current_value, TX_THREAD **first_suspended, ULONG *suspended_count, TX_SEMAPHORE **next_semaphore) diff --git a/common_modules/module_lib/src/txm_semaphore_performance_info_get.c b/common_modules/module_lib/src/txm_semaphore_performance_info_get.c index f845afe0..f227f84a 100644 --- a/common_modules/module_lib/src/txm_semaphore_performance_info_get.c +++ b/common_modules/module_lib/src/txm_semaphore_performance_info_get.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_semaphore_performance_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -66,7 +66,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_semaphore_performance_info_get(TX_SEMAPHORE *semaphore_ptr, ULONG *puts, ULONG *gets, ULONG *suspensions, ULONG *timeouts) diff --git a/common_modules/module_lib/src/txm_semaphore_performance_system_info_get.c b/common_modules/module_lib/src/txm_semaphore_performance_system_info_get.c index f2db0a7c..372bab2c 100644 --- a/common_modules/module_lib/src/txm_semaphore_performance_system_info_get.c +++ b/common_modules/module_lib/src/txm_semaphore_performance_system_info_get.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_semaphore_performance_system_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -64,7 +64,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_semaphore_performance_system_info_get(ULONG *puts, ULONG *gets, ULONG *suspensions, ULONG *timeouts) diff --git a/common_modules/module_lib/src/txm_semaphore_prioritize.c b/common_modules/module_lib/src/txm_semaphore_prioritize.c index 505937d1..142696aa 100644 --- a/common_modules/module_lib/src/txm_semaphore_prioritize.c +++ b/common_modules/module_lib/src/txm_semaphore_prioritize.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_semaphore_prioritize PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -57,7 +57,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_semaphore_prioritize(TX_SEMAPHORE *semaphore_ptr) diff --git a/common_modules/module_lib/src/txm_semaphore_put.c b/common_modules/module_lib/src/txm_semaphore_put.c index 0233b166..e92c459b 100644 --- a/common_modules/module_lib/src/txm_semaphore_put.c +++ b/common_modules/module_lib/src/txm_semaphore_put.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_semaphore_put PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_semaphore_put(TX_SEMAPHORE *semaphore_ptr) diff --git a/common_modules/module_lib/src/txm_semaphore_put_notify.c b/common_modules/module_lib/src/txm_semaphore_put_notify.c index 7a884677..a58991e0 100644 --- a/common_modules/module_lib/src/txm_semaphore_put_notify.c +++ b/common_modules/module_lib/src/txm_semaphore_put_notify.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_semaphore_put_notify PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_semaphore_put_notify(TX_SEMAPHORE *semaphore_ptr, VOID (*semaphore_put_notify)(TX_SEMAPHORE *notify_semaphore_ptr)) diff --git a/common_modules/module_lib/src/txm_thread_create.c b/common_modules/module_lib/src/txm_thread_create.c index 1a756ea7..bd910e6b 100644 --- a/common_modules/module_lib/src/txm_thread_create.c +++ b/common_modules/module_lib/src/txm_thread_create.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_create PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -73,7 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_create(TX_THREAD *thread_ptr, CHAR *name_ptr, VOID (*entry_function)(ULONG entry_input), ULONG entry_input, VOID *stack_start, ULONG stack_size, UINT priority, UINT preempt_threshold, ULONG time_slice, UINT auto_start, UINT thread_control_block_size) diff --git a/common_modules/module_lib/src/txm_thread_delete.c b/common_modules/module_lib/src/txm_thread_delete.c index d8812755..6e1e6b76 100644 --- a/common_modules/module_lib/src/txm_thread_delete.c +++ b/common_modules/module_lib/src/txm_thread_delete.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_delete PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,7 +59,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_delete(TX_THREAD *thread_ptr) diff --git a/common_modules/module_lib/src/txm_thread_entry_exit_notify.c b/common_modules/module_lib/src/txm_thread_entry_exit_notify.c index 163b666f..e8fa8b08 100644 --- a/common_modules/module_lib/src/txm_thread_entry_exit_notify.c +++ b/common_modules/module_lib/src/txm_thread_entry_exit_notify.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_entry_exit_notify PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_entry_exit_notify(TX_THREAD *thread_ptr, VOID (*thread_entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT type)) diff --git a/common_modules/module_lib/src/txm_thread_identify.c b/common_modules/module_lib/src/txm_thread_identify.c index b2c5eb10..7dc4297d 100644 --- a/common_modules/module_lib/src/txm_thread_identify.c +++ b/common_modules/module_lib/src/txm_thread_identify.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_identify PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ TX_THREAD *_tx_thread_identify(VOID) diff --git a/common_modules/module_lib/src/txm_thread_info_get.c b/common_modules/module_lib/src/txm_thread_info_get.c index a8ecc93c..ca9f4684 100644 --- a/common_modules/module_lib/src/txm_thread_info_get.c +++ b/common_modules/module_lib/src/txm_thread_info_get.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_info_get(TX_THREAD *thread_ptr, CHAR **name, UINT *state, ULONG *run_count, UINT *priority, UINT *preemption_threshold, ULONG *time_slice, TX_THREAD **next_thread, TX_THREAD **next_suspended_thread) diff --git a/common_modules/module_lib/src/txm_thread_interrupt_control.c b/common_modules/module_lib/src/txm_thread_interrupt_control.c index a3df15ed..628672d3 100644 --- a/common_modules/module_lib/src/txm_thread_interrupt_control.c +++ b/common_modules/module_lib/src/txm_thread_interrupt_control.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/common_modules/module_lib/src/txm_thread_performance_info_get.c b/common_modules/module_lib/src/txm_thread_performance_info_get.c index af58f66f..c1cac33c 100644 --- a/common_modules/module_lib/src/txm_thread_performance_info_get.c +++ b/common_modules/module_lib/src/txm_thread_performance_info_get.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_performance_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -83,7 +83,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_performance_info_get(TX_THREAD *thread_ptr, ULONG *resumptions, ULONG *suspensions, ULONG *solicited_preemptions, ULONG *interrupt_preemptions, ULONG *priority_inversions, ULONG *time_slices, ULONG *relinquishes, ULONG *timeouts, ULONG *wait_aborts, TX_THREAD **last_preempted_by) diff --git a/common_modules/module_lib/src/txm_thread_performance_system_info_get.c b/common_modules/module_lib/src/txm_thread_performance_system_info_get.c index a696f74c..5e67e96e 100644 --- a/common_modules/module_lib/src/txm_thread_performance_system_info_get.c +++ b/common_modules/module_lib/src/txm_thread_performance_system_info_get.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_performance_system_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -83,7 +83,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_performance_system_info_get(ULONG *resumptions, ULONG *suspensions, ULONG *solicited_preemptions, ULONG *interrupt_preemptions, ULONG *priority_inversions, ULONG *time_slices, ULONG *relinquishes, ULONG *timeouts, ULONG *wait_aborts, ULONG *non_idle_returns, ULONG *idle_returns) diff --git a/common_modules/module_lib/src/txm_thread_preemption_change.c b/common_modules/module_lib/src/txm_thread_preemption_change.c index ef9195ef..9111c15f 100644 --- a/common_modules/module_lib/src/txm_thread_preemption_change.c +++ b/common_modules/module_lib/src/txm_thread_preemption_change.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_preemption_change PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -63,7 +63,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_preemption_change(TX_THREAD *thread_ptr, UINT new_threshold, UINT *old_threshold) diff --git a/common_modules/module_lib/src/txm_thread_priority_change.c b/common_modules/module_lib/src/txm_thread_priority_change.c index 08da0b00..4ee47893 100644 --- a/common_modules/module_lib/src/txm_thread_priority_change.c +++ b/common_modules/module_lib/src/txm_thread_priority_change.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_priority_change PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -63,7 +63,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_priority_change(TX_THREAD *thread_ptr, UINT new_priority, UINT *old_priority) diff --git a/common_modules/module_lib/src/txm_thread_relinquish.c b/common_modules/module_lib/src/txm_thread_relinquish.c index cc7acc9a..8e34e235 100644 --- a/common_modules/module_lib/src/txm_thread_relinquish.c +++ b/common_modules/module_lib/src/txm_thread_relinquish.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_relinquish PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txe_thread_relinquish(VOID) diff --git a/common_modules/module_lib/src/txm_thread_reset.c b/common_modules/module_lib/src/txm_thread_reset.c index b907f30d..54ea25f7 100644 --- a/common_modules/module_lib/src/txm_thread_reset.c +++ b/common_modules/module_lib/src/txm_thread_reset.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_reset PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,7 +59,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_reset(TX_THREAD *thread_ptr) diff --git a/common_modules/module_lib/src/txm_thread_resume.c b/common_modules/module_lib/src/txm_thread_resume.c index 8738f346..0c92b154 100644 --- a/common_modules/module_lib/src/txm_thread_resume.c +++ b/common_modules/module_lib/src/txm_thread_resume.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_resume PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_resume(TX_THREAD *thread_ptr) diff --git a/common_modules/module_lib/src/txm_thread_sleep.c b/common_modules/module_lib/src/txm_thread_sleep.c index f9e9a291..2da82b7d 100644 --- a/common_modules/module_lib/src/txm_thread_sleep.c +++ b/common_modules/module_lib/src/txm_thread_sleep.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_sleep PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_sleep(ULONG timer_ticks) diff --git a/common_modules/module_lib/src/txm_thread_stack_error_notify.c b/common_modules/module_lib/src/txm_thread_stack_error_notify.c index f982ed29..fbad1da7 100644 --- a/common_modules/module_lib/src/txm_thread_stack_error_notify.c +++ b/common_modules/module_lib/src/txm_thread_stack_error_notify.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_error_notify PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -62,7 +62,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr)) diff --git a/common_modules/module_lib/src/txm_thread_suspend.c b/common_modules/module_lib/src/txm_thread_suspend.c index a1a496da..a8a25ff1 100644 --- a/common_modules/module_lib/src/txm_thread_suspend.c +++ b/common_modules/module_lib/src/txm_thread_suspend.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_suspend PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_suspend(TX_THREAD *thread_ptr) diff --git a/common_modules/module_lib/src/txm_thread_terminate.c b/common_modules/module_lib/src/txm_thread_terminate.c index a082e45b..50acf59f 100644 --- a/common_modules/module_lib/src/txm_thread_terminate.c +++ b/common_modules/module_lib/src/txm_thread_terminate.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_terminate PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_terminate(TX_THREAD *thread_ptr) diff --git a/common_modules/module_lib/src/txm_thread_time_slice_change.c b/common_modules/module_lib/src/txm_thread_time_slice_change.c index 8fbb892e..7183b4c8 100644 --- a/common_modules/module_lib/src/txm_thread_time_slice_change.c +++ b/common_modules/module_lib/src/txm_thread_time_slice_change.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_time_slice_change PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -62,7 +62,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_time_slice_change(TX_THREAD *thread_ptr, ULONG new_time_slice, ULONG *old_time_slice) diff --git a/common_modules/module_lib/src/txm_thread_wait_abort.c b/common_modules/module_lib/src/txm_thread_wait_abort.c index ba2da979..3177165a 100644 --- a/common_modules/module_lib/src/txm_thread_wait_abort.c +++ b/common_modules/module_lib/src/txm_thread_wait_abort.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_wait_abort PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_wait_abort(TX_THREAD *thread_ptr) diff --git a/common_modules/module_lib/src/txm_time_get.c b/common_modules/module_lib/src/txm_time_get.c index 679acaca..0d4751c5 100644 --- a/common_modules/module_lib/src/txm_time_get.c +++ b/common_modules/module_lib/src/txm_time_get.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_time_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _tx_time_get(VOID) diff --git a/common_modules/module_lib/src/txm_time_set.c b/common_modules/module_lib/src/txm_time_set.c index 6e081b5a..bb80fcb5 100644 --- a/common_modules/module_lib/src/txm_time_set.c +++ b/common_modules/module_lib/src/txm_time_set.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_time_set PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_time_set(ULONG new_time) diff --git a/common_modules/module_lib/src/txm_timer_activate.c b/common_modules/module_lib/src/txm_timer_activate.c index cf13e61d..54d09673 100644 --- a/common_modules/module_lib/src/txm_timer_activate.c +++ b/common_modules/module_lib/src/txm_timer_activate.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_timer_activate PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_timer_activate(TX_TIMER *timer_ptr) diff --git a/common_modules/module_lib/src/txm_timer_change.c b/common_modules/module_lib/src/txm_timer_change.c index 31da4ac9..f3bf5c1a 100644 --- a/common_modules/module_lib/src/txm_timer_change.c +++ b/common_modules/module_lib/src/txm_timer_change.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_timer_change PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -63,7 +63,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_timer_change(TX_TIMER *timer_ptr, ULONG initial_ticks, ULONG reschedule_ticks) diff --git a/common_modules/module_lib/src/txm_timer_create.c b/common_modules/module_lib/src/txm_timer_create.c index b70abd0a..7e9958fd 100644 --- a/common_modules/module_lib/src/txm_timer_create.c +++ b/common_modules/module_lib/src/txm_timer_create.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_timer_create PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_timer_create(TX_TIMER *timer_ptr, CHAR *name_ptr, VOID (*expiration_function)(ULONG), ULONG expiration_input, ULONG initial_ticks, ULONG reschedule_ticks, UINT auto_activate, UINT timer_control_block_size) diff --git a/common_modules/module_lib/src/txm_timer_deactivate.c b/common_modules/module_lib/src/txm_timer_deactivate.c index 7f74bc5c..7ba926a9 100644 --- a/common_modules/module_lib/src/txm_timer_deactivate.c +++ b/common_modules/module_lib/src/txm_timer_deactivate.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_timer_deactivate PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,7 +59,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_timer_deactivate(TX_TIMER *timer_ptr) diff --git a/common_modules/module_lib/src/txm_timer_delete.c b/common_modules/module_lib/src/txm_timer_delete.c index df7421bc..2127304f 100644 --- a/common_modules/module_lib/src/txm_timer_delete.c +++ b/common_modules/module_lib/src/txm_timer_delete.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_timer_delete PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_timer_delete(TX_TIMER *timer_ptr) diff --git a/common_modules/module_lib/src/txm_timer_info_get.c b/common_modules/module_lib/src/txm_timer_info_get.c index 890df7f5..f9f2c92d 100644 --- a/common_modules/module_lib/src/txm_timer_info_get.c +++ b/common_modules/module_lib/src/txm_timer_info_get.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_timer_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -66,7 +66,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_timer_info_get(TX_TIMER *timer_ptr, CHAR **name, UINT *active, ULONG *remaining_ticks, ULONG *reschedule_ticks, TX_TIMER **next_timer) diff --git a/common_modules/module_lib/src/txm_timer_performance_info_get.c b/common_modules/module_lib/src/txm_timer_performance_info_get.c index 1896f344..b1900704 100644 --- a/common_modules/module_lib/src/txm_timer_performance_info_get.c +++ b/common_modules/module_lib/src/txm_timer_performance_info_get.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_performance_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -69,7 +69,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_timer_performance_info_get(TX_TIMER *timer_ptr, ULONG *activates, ULONG *reactivates, ULONG *deactivates, ULONG *expirations, ULONG *expiration_adjusts) diff --git a/common_modules/module_lib/src/txm_timer_performance_system_info_get.c b/common_modules/module_lib/src/txm_timer_performance_system_info_get.c index 43a00acf..1a507602 100644 --- a/common_modules/module_lib/src/txm_timer_performance_system_info_get.c +++ b/common_modules/module_lib/src/txm_timer_performance_system_info_get.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_performance_system_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -66,7 +66,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_timer_performance_system_info_get(ULONG *activates, ULONG *reactivates, ULONG *deactivates, ULONG *expirations, ULONG *expiration_adjusts) diff --git a/common_modules/module_lib/src/txm_trace_buffer_full_notify.c b/common_modules/module_lib/src/txm_trace_buffer_full_notify.c index 703cade7..f6641544 100644 --- a/common_modules/module_lib/src/txm_trace_buffer_full_notify.c +++ b/common_modules/module_lib/src/txm_trace_buffer_full_notify.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_trace_buffer_full_notify PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_trace_buffer_full_notify(VOID (*full_buffer_callback)(VOID *buffer)) diff --git a/common_modules/module_lib/src/txm_trace_disable.c b/common_modules/module_lib/src/txm_trace_disable.c index 9e5ab99b..b958db9e 100644 --- a/common_modules/module_lib/src/txm_trace_disable.c +++ b/common_modules/module_lib/src/txm_trace_disable.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_trace_disable PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -57,7 +57,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_trace_disable(VOID) diff --git a/common_modules/module_lib/src/txm_trace_enable.c b/common_modules/module_lib/src/txm_trace_enable.c index 2e14265c..1960e0b4 100644 --- a/common_modules/module_lib/src/txm_trace_enable.c +++ b/common_modules/module_lib/src/txm_trace_enable.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_trace_enable PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_trace_enable(VOID *trace_buffer_start, ULONG trace_buffer_size, ULONG registry_entries) diff --git a/common_modules/module_lib/src/txm_trace_event_filter.c b/common_modules/module_lib/src/txm_trace_event_filter.c index dda12e36..8a8b4dc9 100644 --- a/common_modules/module_lib/src/txm_trace_event_filter.c +++ b/common_modules/module_lib/src/txm_trace_event_filter.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_trace_event_filter PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_trace_event_filter(ULONG event_filter_bits) diff --git a/common_modules/module_lib/src/txm_trace_event_unfilter.c b/common_modules/module_lib/src/txm_trace_event_unfilter.c index fcff4a38..5afa77a4 100644 --- a/common_modules/module_lib/src/txm_trace_event_unfilter.c +++ b/common_modules/module_lib/src/txm_trace_event_unfilter.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_trace_event_unfilter PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_trace_event_unfilter(ULONG event_unfilter_bits) diff --git a/common_modules/module_lib/src/txm_trace_interrupt_control.c b/common_modules/module_lib/src/txm_trace_interrupt_control.c index 76cb7ebb..6533ae28 100644 --- a/common_modules/module_lib/src/txm_trace_interrupt_control.c +++ b/common_modules/module_lib/src/txm_trace_interrupt_control.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_trace_interrupt_control PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_trace_interrupt_control(UINT new_posture) diff --git a/common_modules/module_lib/src/txm_trace_isr_enter_insert.c b/common_modules/module_lib/src/txm_trace_isr_enter_insert.c index 734aaa61..730c8c9b 100644 --- a/common_modules/module_lib/src/txm_trace_isr_enter_insert.c +++ b/common_modules/module_lib/src/txm_trace_isr_enter_insert.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_trace_isr_enter_insert PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_trace_isr_enter_insert(ULONG isr_id) diff --git a/common_modules/module_lib/src/txm_trace_isr_exit_insert.c b/common_modules/module_lib/src/txm_trace_isr_exit_insert.c index 9d79c1e4..078831de 100644 --- a/common_modules/module_lib/src/txm_trace_isr_exit_insert.c +++ b/common_modules/module_lib/src/txm_trace_isr_exit_insert.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_trace_isr_exit_insert PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,7 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_trace_isr_exit_insert(ULONG isr_id) diff --git a/common_modules/module_lib/src/txm_trace_user_event_insert.c b/common_modules/module_lib/src/txm_trace_user_event_insert.c index 156d0b94..56cc5554 100644 --- a/common_modules/module_lib/src/txm_trace_user_event_insert.c +++ b/common_modules/module_lib/src/txm_trace_user_event_insert.c @@ -28,7 +28,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_trace_user_event_insert PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_trace_user_event_insert(ULONG event_id, ULONG info_field_1, ULONG info_field_2, ULONG info_field_3, ULONG info_field_4) diff --git a/common_modules/module_manager/inc/txm_module_manager_util.h b/common_modules/module_manager/inc/txm_module_manager_util.h index 05543294..1eef6440 100644 --- a/common_modules/module_manager/inc/txm_module_manager_util.h +++ b/common_modules/module_manager/inc/txm_module_manager_util.h @@ -26,7 +26,7 @@ /* COMPONENT DEFINITION RELEASE */ /* */ /* txm_module_manager_util.h PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -40,102 +40,45 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ #ifndef TXM_MODULE_MANAGER_UTIL_H #define TXM_MODULE_MANAGER_UTIL_H -/* Define utility macros. */ - -/* Define inside/outside check macros. The _INCLUSIVE/_EXCLUSIVE suffix applies only to range_end. */ - -#define TXM_MODULE_MANAGER_CHECK_OUTSIDE_RANGE_INCLUSIVE(range_start, range_end, obj_start, obj_size) \ - ((obj_start) > (ALIGN_TYPE) (range_end) || \ - ((obj_start) + (obj_size)) <= (ALIGN_TYPE) (range_start)) - -#define TXM_MODULE_MANAGER_CHECK_OUTSIDE_RANGE_EXCLUSIVE(range_start, range_end, obj_start, obj_size) \ - ((obj_start) >= (ALIGN_TYPE) (range_end) || \ - ((obj_start) + (obj_size)) <= (ALIGN_TYPE) (range_start)) - -#define TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_INCLUSIVE(range_start, range_end, obj_start, obj_size) \ - (((obj_start) >= (ALIGN_TYPE) (range_start)) && \ - (((obj_start) + (obj_size)) <= (ALIGN_TYPE) (range_end) + 1)) - -#define TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_INCLUSIVE_BYTE(range_start, range_end, byte_ptr) \ - (((byte_ptr) >= (ALIGN_TYPE) (range_start)) && \ - ((byte_ptr) <= (ALIGN_TYPE) (range_end))) - -#define TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_EXCLUSIVE(range_start, range_end, obj_start, obj_size) \ - (((obj_start) >= (ALIGN_TYPE) (range_start)) && \ - (((obj_start) + (obj_size)) <= (ALIGN_TYPE) (range_end))) - -#define TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_EXCLUSIVE_BYTE(range_start, range_end, byte_ptr) \ - (((byte_ptr) >= (ALIGN_TYPE) (range_start)) && \ - ((byte_ptr) < (ALIGN_TYPE) (range_end))) - /* Define check macros for modules. */ #define TXM_MODULE_MANAGER_CHECK_OUTSIDE_DATA(module_instance, obj_ptr, obj_size) \ - TXM_MODULE_MANAGER_CHECK_OUTSIDE_RANGE_INCLUSIVE(module_instance -> txm_module_instance_data_start, \ - module_instance -> txm_module_instance_data_end, \ - obj_ptr, obj_size) - -#define TXM_MODULE_MANAGER_CHECK_OUTSIDE_CODE(module_instance, obj_ptr, obj_size) \ - TXM_MODULE_MANAGER_CHECK_OUTSIDE_RANGE_INCLUSIVE(module_instance -> txm_module_instance_code_start, \ - module_instance -> txm_module_instance_code_end, \ - obj_ptr, obj_size) - -#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ - TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_INCLUSIVE(module_instance -> txm_module_instance_data_start, \ - module_instance -> txm_module_instance_data_end, \ - obj_ptr, obj_size) - -#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA_BYTE(module_instance, byte_ptr) \ - TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_INCLUSIVE_BYTE(module_instance -> txm_module_instance_data_start, \ - module_instance -> txm_module_instance_data_end, \ - byte_ptr) + (!(TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size))) #define TXM_MODULE_MANAGER_CHECK_INSIDE_CODE(module_instance, obj_ptr, obj_size) \ - TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_INCLUSIVE(module_instance -> txm_module_instance_code_start, \ - module_instance -> txm_module_instance_code_end, \ - obj_ptr, obj_size) + (((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_code_start) && \ + (((obj_ptr) + (obj_size)) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_code_end + 1))) -#define TXM_MODULE_MANAGER_CHECK_INSIDE_CODE_BYTE(module_instance, byte_ptr) \ - TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_INCLUSIVE_BYTE(module_instance -> txm_module_instance_code_start, \ - module_instance -> txm_module_instance_code_end, \ - byte_ptr) +#define TXM_MODULE_MANAGER_CHECK_OUTSIDE_CODE(module_instance, obj_ptr, obj_size) \ + (!(TXM_MODULE_MANAGER_CHECK_INSIDE_CODE(module_instance, obj_ptr, obj_size))) #define TXM_MODULE_MANAGER_CHECK_INSIDE_OBJ_POOL(module_instance, obj_ptr, obj_size) \ ((_txm_module_manager_object_pool_created == TX_TRUE) && \ - TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_EXCLUSIVE(_txm_module_manager_object_pool.tx_byte_pool_start, \ - _txm_module_manager_object_pool.tx_byte_pool_start + _txm_module_manager_object_pool.tx_byte_pool_size, \ - obj_ptr, obj_size)) + (((obj_ptr) >= (ALIGN_TYPE) _txm_module_manager_object_pool.tx_byte_pool_start) && \ + (((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (_txm_module_manager_object_pool.tx_byte_pool_start + _txm_module_manager_object_pool.tx_byte_pool_size)))) /* Define macros for module. */ #define TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE(module_instance, obj_ptr, obj_size) \ (TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) || \ - _txm_module_manager_shared_memory_check_inside(module_instance, (ALIGN_TYPE) obj_ptr, obj_size) || \ TXM_MODULE_MANAGER_CHECK_INSIDE_CODE(module_instance, obj_ptr, obj_size)) -#define TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_BYTE(module_instance, byte_ptr) \ - (TXM_MODULE_MANAGER_CHECK_INSIDE_DATA_BYTE(module_instance, byte_ptr) || \ - _txm_module_manager_shared_memory_check_inside_byte(module_instance, (ALIGN_TYPE) byte_ptr) || \ - TXM_MODULE_MANAGER_CHECK_INSIDE_CODE_BYTE(module_instance, byte_ptr)) - #define TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, obj_ptr, obj_size) \ - (TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) || \ - _txm_module_manager_shared_memory_check_inside(module_instance, (ALIGN_TYPE) obj_ptr, obj_size)) + TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) #define TXM_MODULE_MANAGER_ENSURE_OUTSIDE_MODULE(module_instance, obj_ptr, obj_size) \ (TXM_MODULE_MANAGER_CHECK_OUTSIDE_DATA(module_instance, obj_ptr, obj_size) && \ - _txm_module_manager_shared_memory_check_outside(module_instance, (ALIGN_TYPE) obj_ptr, obj_size) && \ TXM_MODULE_MANAGER_CHECK_OUTSIDE_CODE(module_instance, obj_ptr, obj_size)) #define TXM_MODULE_MANAGER_ENSURE_INSIDE_OBJ_POOL(module_instance, obj_ptr, obj_size) \ - (TXM_MODULE_MANAGER_CHECK_INSIDE_OBJ_POOL(module_instance, obj_ptr, obj_size)) + TXM_MODULE_MANAGER_CHECK_INSIDE_OBJ_POOL(module_instance, obj_ptr, obj_size) /* Define macros for parameter types. */ @@ -163,7 +106,7 @@ /* Strings we dereference can be in RW/RO/Shared areas. */ #define TXM_MODULE_MANAGER_PARAM_CHECK_DEREFERENCE_STRING(module_instance, string_ptr) \ (((void *) (string_ptr) == TX_NULL) || \ - (TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_BYTE(module_instance, string_ptr))) + (TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE(module_instance, string_ptr, 1))) #define TXM_MODULE_MANAGER_UTIL_MAX_VALUE_OF_TYPE_UNSIGNED(type) ((1ULL << (sizeof(type) * 8)) - 1) diff --git a/common_modules/module_manager/src/txm_module_manager_application_request.c b/common_modules/module_manager/src/txm_module_manager_application_request.c index af7db561..7e3491dd 100644 --- a/common_modules/module_manager/src/txm_module_manager_application_request.c +++ b/common_modules/module_manager/src/txm_module_manager_application_request.c @@ -32,7 +32,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_application_request PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -67,7 +67,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_application_request(ULONG request_id, ALIGN_TYPE param_1, ALIGN_TYPE param_2, ALIGN_TYPE param_3) diff --git a/common_modules/module_manager/src/txm_module_manager_callback_request.c b/common_modules/module_manager/src/txm_module_manager_callback_request.c index ae7e8f15..efb6f8b5 100644 --- a/common_modules/module_manager/src/txm_module_manager_callback_request.c +++ b/common_modules/module_manager/src/txm_module_manager_callback_request.c @@ -33,7 +33,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_callback_request PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -64,7 +64,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_callback_request(TX_QUEUE *module_callback_queue, TXM_MODULE_CALLBACK_MESSAGE *callback_message) diff --git a/common_modules/module_manager/src/txm_module_manager_event_flags_notify_trampoline.c b/common_modules/module_manager/src/txm_module_manager_event_flags_notify_trampoline.c index afaa9480..b86c9e32 100644 --- a/common_modules/module_manager/src/txm_module_manager_event_flags_notify_trampoline.c +++ b/common_modules/module_manager/src/txm_module_manager_event_flags_notify_trampoline.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_event_flags_notify_trampoline PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -65,7 +65,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_event_flags_notify_trampoline(TX_EVENT_FLAGS_GROUP *group_ptr) diff --git a/common_modules/module_manager/src/txm_module_manager_file_load.c b/common_modules/module_manager/src/txm_module_manager_file_load.c index 4508ec6c..34053393 100644 --- a/common_modules/module_manager/src/txm_module_manager_file_load.c +++ b/common_modules/module_manager/src/txm_module_manager_file_load.c @@ -39,7 +39,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_file_load PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -80,7 +80,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_file_load(TXM_MODULE_INSTANCE *module_instance, CHAR *module_name, FX_MEDIA *media_ptr, CHAR *file_name) diff --git a/common_modules/module_manager/src/txm_module_manager_in_place_load.c b/common_modules/module_manager/src/txm_module_manager_in_place_load.c index d5ee4b55..ae482ec1 100644 --- a/common_modules/module_manager/src/txm_module_manager_in_place_load.c +++ b/common_modules/module_manager/src/txm_module_manager_in_place_load.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_in_place_load PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_in_place_load(TXM_MODULE_INSTANCE *module_instance, CHAR *module_name, VOID *module_location) diff --git a/common_modules/module_manager/src/txm_module_manager_initialize.c b/common_modules/module_manager/src/txm_module_manager_initialize.c index 1d9f19ab..a9190454 100644 --- a/common_modules/module_manager/src/txm_module_manager_initialize.c +++ b/common_modules/module_manager/src/txm_module_manager_initialize.c @@ -102,7 +102,7 @@ ULONG _txm_module_manager_callback_error_count; /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_initialize PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -134,7 +134,7 @@ ULONG _txm_module_manager_callback_error_count; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_initialize(VOID *module_memory_start, ULONG module_memory_size) diff --git a/common_modules/module_manager/src/txm_module_manager_internal_load.c b/common_modules/module_manager/src/txm_module_manager_internal_load.c index 3ba46d82..6b5ae54f 100644 --- a/common_modules/module_manager/src/txm_module_manager_internal_load.c +++ b/common_modules/module_manager/src/txm_module_manager_internal_load.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_internal_load PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -73,7 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_internal_load(TXM_MODULE_INSTANCE *module_instance, CHAR *module_name, VOID *module_location, diff --git a/common_modules/module_manager/src/txm_module_manager_kernel_dispatch.c b/common_modules/module_manager/src/txm_module_manager_kernel_dispatch.c index 08761e17..63c1acc5 100644 --- a/common_modules/module_manager/src/txm_module_manager_kernel_dispatch.c +++ b/common_modules/module_manager/src/txm_module_manager_kernel_dispatch.c @@ -41,7 +41,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_kernel_dispatch PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -79,7 +79,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ALIGN_TYPE _txm_module_manager_kernel_dispatch(ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) diff --git a/common_modules/module_manager/src/txm_module_manager_maximum_module_priority_set.c b/common_modules/module_manager/src/txm_module_manager_maximum_module_priority_set.c index dff40f9d..d725faf2 100644 --- a/common_modules/module_manager/src/txm_module_manager_maximum_module_priority_set.c +++ b/common_modules/module_manager/src/txm_module_manager_maximum_module_priority_set.c @@ -32,7 +32,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_maximum_module_priority_set PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -63,7 +63,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_maximum_module_priority_set(TXM_MODULE_INSTANCE *module_instance, UINT priority) diff --git a/common_modules/module_manager/src/txm_module_manager_memory_load.c b/common_modules/module_manager/src/txm_module_manager_memory_load.c index dba896e7..e35f01b9 100644 --- a/common_modules/module_manager/src/txm_module_manager_memory_load.c +++ b/common_modules/module_manager/src/txm_module_manager_memory_load.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_memory_load PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -71,7 +71,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_load(TXM_MODULE_INSTANCE *module_instance, CHAR *module_name, VOID *module_location) diff --git a/common_modules/module_manager/src/txm_module_manager_object_allocate.c b/common_modules/module_manager/src/txm_module_manager_object_allocate.c index 8b7dfadf..829dbb1f 100644 --- a/common_modules/module_manager/src/txm_module_manager_object_allocate.c +++ b/common_modules/module_manager/src/txm_module_manager_object_allocate.c @@ -29,7 +29,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_object_allocate PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -66,7 +66,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_object_allocate(VOID **object_ptr_ptr, ULONG object_size, TXM_MODULE_INSTANCE *module_instance) diff --git a/common_modules/module_manager/src/txm_module_manager_object_deallocate.c b/common_modules/module_manager/src/txm_module_manager_object_deallocate.c index c2a40185..5b90b995 100644 --- a/common_modules/module_manager/src/txm_module_manager_object_deallocate.c +++ b/common_modules/module_manager/src/txm_module_manager_object_deallocate.c @@ -31,7 +31,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_object_deallocate PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -63,7 +63,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_object_deallocate(VOID *object_ptr) diff --git a/common_modules/module_manager/src/txm_module_manager_object_pointer_get.c b/common_modules/module_manager/src/txm_module_manager_object_pointer_get.c index c1a95599..6a7927ea 100644 --- a/common_modules/module_manager/src/txm_module_manager_object_pointer_get.c +++ b/common_modules/module_manager/src/txm_module_manager_object_pointer_get.c @@ -30,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_object_pointer_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -76,7 +76,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_object_pointer_get(UINT object_type, CHAR *name, VOID **object_ptr) diff --git a/common_modules/module_manager/src/txm_module_manager_object_pointer_get_extended.c b/common_modules/module_manager/src/txm_module_manager_object_pointer_get_extended.c index 08583450..b62081ac 100644 --- a/common_modules/module_manager/src/txm_module_manager_object_pointer_get_extended.c +++ b/common_modules/module_manager/src/txm_module_manager_object_pointer_get_extended.c @@ -41,7 +41,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_object_pointer_get_extended PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -93,7 +93,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_object_pointer_get_extended(UINT object_type, CHAR *search_name, UINT search_name_length, VOID **object_ptr) diff --git a/common_modules/module_manager/src/txm_module_manager_object_pool_create.c b/common_modules/module_manager/src/txm_module_manager_object_pool_create.c index 9794ec98..25a91340 100644 --- a/common_modules/module_manager/src/txm_module_manager_object_pool_create.c +++ b/common_modules/module_manager/src/txm_module_manager_object_pool_create.c @@ -31,7 +31,7 @@ /* FUNCTION RELEASE */ /* */ /* txm_module_manager_object_pool_create PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -64,7 +64,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_object_pool_create(VOID *object_memory, ULONG object_memory_size) diff --git a/common_modules/module_manager/src/txm_module_manager_properties_get.c b/common_modules/module_manager/src/txm_module_manager_properties_get.c index f2f803c5..3a91812d 100644 --- a/common_modules/module_manager/src/txm_module_manager_properties_get.c +++ b/common_modules/module_manager/src/txm_module_manager_properties_get.c @@ -30,7 +30,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_properties_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_properties_get(TXM_MODULE_INSTANCE *module_instance, ULONG *module_properties_ptr) diff --git a/common_modules/module_manager/src/txm_module_manager_queue_notify_trampoline.c b/common_modules/module_manager/src/txm_module_manager_queue_notify_trampoline.c index 50166517..436bec4e 100644 --- a/common_modules/module_manager/src/txm_module_manager_queue_notify_trampoline.c +++ b/common_modules/module_manager/src/txm_module_manager_queue_notify_trampoline.c @@ -33,7 +33,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_queue_notify_trampoline PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -62,7 +62,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_queue_notify_trampoline(TX_QUEUE *queue_ptr) diff --git a/common_modules/module_manager/src/txm_module_manager_semaphore_notify_trampoline.c b/common_modules/module_manager/src/txm_module_manager_semaphore_notify_trampoline.c index 78f6f157..e90fd28c 100644 --- a/common_modules/module_manager/src/txm_module_manager_semaphore_notify_trampoline.c +++ b/common_modules/module_manager/src/txm_module_manager_semaphore_notify_trampoline.c @@ -33,7 +33,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_semaphore_notify_trampoline PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -63,7 +63,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_semaphore_notify_trampoline(TX_SEMAPHORE *semaphore_ptr) diff --git a/common_modules/module_manager/src/txm_module_manager_start.c b/common_modules/module_manager/src/txm_module_manager_start.c index df689247..e793e8ef 100644 --- a/common_modules/module_manager/src/txm_module_manager_start.c +++ b/common_modules/module_manager/src/txm_module_manager_start.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_start PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -69,7 +69,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_start(TXM_MODULE_INSTANCE *module_instance) diff --git a/common_modules/module_manager/src/txm_module_manager_stop.c b/common_modules/module_manager/src/txm_module_manager_stop.c index b9682a1d..557ee726 100644 --- a/common_modules/module_manager/src/txm_module_manager_stop.c +++ b/common_modules/module_manager/src/txm_module_manager_stop.c @@ -60,7 +60,7 @@ extern UINT _txm_module_manager_usbx_stop(TXM_MODULE_INSTANCE *module_instance) /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_stop PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -108,7 +108,7 @@ extern UINT _txm_module_manager_usbx_stop(TXM_MODULE_INSTANCE *module_instance) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_stop(TXM_MODULE_INSTANCE *module_instance) diff --git a/common_modules/module_manager/src/txm_module_manager_thread_create.c b/common_modules/module_manager/src/txm_module_manager_thread_create.c index 52dae4a5..9a36d25d 100644 --- a/common_modules/module_manager/src/txm_module_manager_thread_create.c +++ b/common_modules/module_manager/src/txm_module_manager_thread_create.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_thread_create PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -81,7 +81,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_thread_create(TX_THREAD *thread_ptr, CHAR *name, VOID (*shell_function)(TX_THREAD *, TXM_MODULE_INSTANCE *), diff --git a/common_modules/module_manager/src/txm_module_manager_thread_notify_trampoline.c b/common_modules/module_manager/src/txm_module_manager_thread_notify_trampoline.c index 569d03f5..d70ff718 100644 --- a/common_modules/module_manager/src/txm_module_manager_thread_notify_trampoline.c +++ b/common_modules/module_manager/src/txm_module_manager_thread_notify_trampoline.c @@ -33,7 +33,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_thread_notify_trampoline PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -64,7 +64,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_thread_notify_trampoline(TX_THREAD *thread_ptr, UINT type) diff --git a/common_modules/module_manager/src/txm_module_manager_thread_reset.c b/common_modules/module_manager/src/txm_module_manager_thread_reset.c index c75be7b6..0fd0b2af 100644 --- a/common_modules/module_manager/src/txm_module_manager_thread_reset.c +++ b/common_modules/module_manager/src/txm_module_manager_thread_reset.c @@ -32,7 +32,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_thread_reset PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -65,7 +65,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_thread_reset(TX_THREAD *thread_ptr) diff --git a/common_modules/module_manager/src/txm_module_manager_timer_notify_trampoline.c b/common_modules/module_manager/src/txm_module_manager_timer_notify_trampoline.c index 2a11f146..9bcdd5d9 100644 --- a/common_modules/module_manager/src/txm_module_manager_timer_notify_trampoline.c +++ b/common_modules/module_manager/src/txm_module_manager_timer_notify_trampoline.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_timer_notify_trampoline PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -63,7 +63,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_timer_notify_trampoline(ULONG id) diff --git a/common_modules/module_manager/src/txm_module_manager_unload.c b/common_modules/module_manager/src/txm_module_manager_unload.c index 3689afd4..4f83f726 100644 --- a/common_modules/module_manager/src/txm_module_manager_unload.c +++ b/common_modules/module_manager/src/txm_module_manager_unload.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_unload PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -66,7 +66,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_unload(TXM_MODULE_INSTANCE *module_instance) diff --git a/common_modules/module_manager/src/txm_module_manager_util.c b/common_modules/module_manager/src/txm_module_manager_util.c index e2f5bb44..8511fce6 100644 --- a/common_modules/module_manager/src/txm_module_manager_util.c +++ b/common_modules/module_manager/src/txm_module_manager_util.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_object_memory_check PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_object_memory_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE object_ptr, ULONG object_size) @@ -105,7 +105,7 @@ UINT _txm_module_manager_object_memory_check(TXM_MODULE_INSTANCE *module_instan /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_created_object_check PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -137,7 +137,7 @@ UINT _txm_module_manager_object_memory_check(TXM_MODULE_INSTANCE *module_instan /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UCHAR _txm_module_manager_created_object_check(TXM_MODULE_INSTANCE *module_instance, VOID *object_ptr) @@ -184,7 +184,7 @@ TXM_MODULE_ALLOCATED_OBJECT *allocated_object_ptr; /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_object_size_check PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -216,7 +216,7 @@ TXM_MODULE_ALLOCATED_OBJECT *allocated_object_ptr; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_object_size_check(ALIGN_TYPE object_ptr, ULONG object_size) @@ -242,7 +242,7 @@ UINT return_value; /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_name_compare PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -275,7 +275,7 @@ UINT return_value; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_object_name_compare(CHAR *search_name, UINT search_name_length, CHAR *object_name) @@ -343,7 +343,7 @@ CHAR object_name_char; /* */ /* _txm_module_manager_util_code_allocation_size_and_alignment_get */ /* PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -378,7 +378,7 @@ CHAR object_name_char; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_util_code_allocation_size_and_alignment_get(TXM_MODULE_PREAMBLE *module_preamble, diff --git a/common_smp/inc/tx_api.h b/common_smp/inc/tx_api.h index 75daa1c2..4dc3a839 100644 --- a/common_smp/inc/tx_api.h +++ b/common_smp/inc/tx_api.h @@ -26,7 +26,7 @@ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ /* tx_api.h PORTABLE SMP */ -/* 6.0.2 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -43,10 +43,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -/* 08-14-2020 William E. Lamie Modified comment(s), and */ -/* updated product constants, */ -/* resulting in version 6.0.2 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -85,8 +82,8 @@ extern "C" { #define AZURE_RTOS_THREADX #define THREADX_MAJOR_VERSION 6 -#define THREADX_MINOR_VERSION 0 -#define THREADX_PATCH_VERSION 2 +#define THREADX_MINOR_VERSION 1 +#define THREADX_PATCH_VERSION 0 /* Define the following symbol for backward compatibility */ #define EL_PRODUCT_THREADX @@ -140,6 +137,7 @@ extern "C" { #define TX_FILE ((UINT) 11) #define TX_TCP_IP ((UINT) 12) #define TX_MUTEX_SUSP ((UINT) 13) +#define TX_PRIORITY_CHANGE ((UINT) 14) /* API return values. */ @@ -192,7 +190,7 @@ extern "C" { #endif -/* Event numbers 0 through 4095 are reserved by Express Logic. Specific event assignments are: +/* Event numbers 0 through 4095 are reserved by Azure RTOS. Specific event assignments are: ThreadX events: 1-199 FileX events: 200-299 @@ -1887,6 +1885,8 @@ VOID _tx_misra_thread_entry_exit_notify_not_used(VOID (*threa #define TX_ULONG_POINTER_DIF(a,b) ((ULONG)(((ULONG *) (a)) - ((ULONG *) (b)))) #define TX_POINTER_TO_ULONG_CONVERT(a) ((ULONG) ((VOID *) (a))) #define TX_ULONG_TO_POINTER_CONVERT(a) ((VOID *) ((ULONG) (a))) +#define TX_POINTER_TO_ALIGN_TYPE_CONVERT(a) ((ALIGN_TYPE) ((VOID *) (a))) +#define TX_ALIGN_TYPE_TO_POINTER_CONVERT(a) ((VOID *) ((ALIGN_TYPE) (a))) #define TX_TIMER_POINTER_DIF(a,b) ((ULONG)(((TX_TIMER_INTERNAL **) (a)) - ((TX_TIMER_INTERNAL **) (b)))) #define TX_TIMER_POINTER_ADD(a,b) (((TX_TIMER_INTERNAL **) (a)) + ((ULONG) (b))) #define TX_USER_TIMER_POINTER_GET(a,b) { \ diff --git a/common_smp/inc/tx_block_pool.h b/common_smp/inc/tx_block_pool.h index 698a2937..aa234be3 100644 --- a/common_smp/inc/tx_block_pool.h +++ b/common_smp/inc/tx_block_pool.h @@ -26,7 +26,7 @@ /* COMPONENT DEFINITION RELEASE */ /* */ /* tx_block_pool.h PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -41,7 +41,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ diff --git a/common_smp/inc/tx_byte_pool.h b/common_smp/inc/tx_byte_pool.h index e3b4047c..66487134 100644 --- a/common_smp/inc/tx_byte_pool.h +++ b/common_smp/inc/tx_byte_pool.h @@ -26,7 +26,7 @@ /* COMPONENT DEFINITION RELEASE */ /* */ /* tx_byte_pool.h PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -41,7 +41,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ diff --git a/common_smp/inc/tx_event_flags.h b/common_smp/inc/tx_event_flags.h index f663d7d8..63c77854 100644 --- a/common_smp/inc/tx_event_flags.h +++ b/common_smp/inc/tx_event_flags.h @@ -26,7 +26,7 @@ /* COMPONENT DEFINITION RELEASE */ /* */ /* tx_event_flags.h PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -41,7 +41,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ diff --git a/common_smp/inc/tx_initialize.h b/common_smp/inc/tx_initialize.h index ddc1c7d8..51d6435e 100644 --- a/common_smp/inc/tx_initialize.h +++ b/common_smp/inc/tx_initialize.h @@ -26,7 +26,7 @@ /* COMPONENT DEFINITION RELEASE */ /* */ /* tx_initialize.h PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -41,7 +41,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ diff --git a/common_smp/inc/tx_mutex.h b/common_smp/inc/tx_mutex.h index 17592e66..712327b8 100644 --- a/common_smp/inc/tx_mutex.h +++ b/common_smp/inc/tx_mutex.h @@ -26,7 +26,7 @@ /* COMPONENT DEFINITION RELEASE */ /* */ /* tx_mutex.h PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -41,7 +41,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ diff --git a/common_smp/inc/tx_queue.h b/common_smp/inc/tx_queue.h index c5d0868a..809ab928 100644 --- a/common_smp/inc/tx_queue.h +++ b/common_smp/inc/tx_queue.h @@ -26,7 +26,7 @@ /* COMPONENT DEFINITION RELEASE */ /* */ /* tx_queue.h PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -41,7 +41,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ diff --git a/common_smp/inc/tx_semaphore.h b/common_smp/inc/tx_semaphore.h index 4a5a3e43..1e2acff2 100644 --- a/common_smp/inc/tx_semaphore.h +++ b/common_smp/inc/tx_semaphore.h @@ -26,7 +26,7 @@ /* COMPONENT DEFINITION RELEASE */ /* */ /* tx_semaphore.h PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -41,7 +41,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ diff --git a/common_smp/inc/tx_thread.h b/common_smp/inc/tx_thread.h index b38b0f6d..3f90323c 100644 --- a/common_smp/inc/tx_thread.h +++ b/common_smp/inc/tx_thread.h @@ -26,7 +26,7 @@ /* COMPONENT DEFINITION RELEASE */ /* */ /* tx_thread.h PORTABLE SMP */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -41,7 +41,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ diff --git a/common_smp/inc/tx_timer.h b/common_smp/inc/tx_timer.h index eb531921..e8bc7059 100644 --- a/common_smp/inc/tx_timer.h +++ b/common_smp/inc/tx_timer.h @@ -26,7 +26,7 @@ /* COMPONENT DEFINITION RELEASE */ /* */ /* tx_timer.h PORTABLE SMP */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -41,7 +41,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ diff --git a/common_smp/inc/tx_trace.h b/common_smp/inc/tx_trace.h index 8baf85cb..9acdb0af 100644 --- a/common_smp/inc/tx_trace.h +++ b/common_smp/inc/tx_trace.h @@ -25,7 +25,7 @@ /* COMPONENT DEFINITION RELEASE */ /* */ /* tx_trace.h PORTABLE SMP */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -40,7 +40,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -242,7 +242,7 @@ typedef struct TX_TRACE_OBJECT_ENTRY_STRUCT /* Define ThreadX Trace Events, along with a brief description of the additional information fields, where I1 -> Information Field 1, I2 -> Information Field 2, etc. */ -/* Event numbers 0 through 4095 are reserved by Express Logic. Specific event assignments are: +/* Event numbers 0 through 4095 are reserved by Azure RTOS. Specific event assignments are: ThreadX events: 1-199 FileX events: 200-299 diff --git a/common_smp/inc/tx_user_sample.h b/common_smp/inc/tx_user_sample.h new file mode 100644 index 00000000..f76be32b --- /dev/null +++ b/common_smp/inc/tx_user_sample.h @@ -0,0 +1,257 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** User Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_user.h PORTABLE C */ +/* 6.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains user defines for configuring ThreadX in specific */ +/* ways. This file will have an effect only if the application and */ +/* ThreadX library are built with TX_INCLUDE_USER_DEFINE_FILE defined. */ +/* Note that all the defines in this file may also be made on the */ +/* command line when building ThreadX library and application objects. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_USER_H +#define TX_USER_H + + +/* Define various build options for the ThreadX port. The application should either make changes + here by commenting or un-commenting the conditional compilation defined OR supply the defines + though the compiler's equivalent of the -D option. + + For maximum speed, the following should be defined: + + TX_MAX_PRIORITIES 32 + TX_DISABLE_PREEMPTION_THRESHOLD + TX_DISABLE_REDUNDANT_CLEARING + TX_DISABLE_NOTIFY_CALLBACKS + TX_NOT_INTERRUPTABLE + TX_TIMER_PROCESS_IN_ISR + TX_REACTIVATE_INLINE + TX_DISABLE_STACK_FILLING + TX_INLINE_THREAD_RESUME_SUSPEND + + For minimum size, the following should be defined: + + TX_MAX_PRIORITIES 32 + TX_DISABLE_PREEMPTION_THRESHOLD + TX_DISABLE_REDUNDANT_CLEARING + TX_DISABLE_NOTIFY_CALLBACKS + TX_NOT_INTERRUPTABLE + TX_TIMER_PROCESS_IN_ISR + + Of course, many of these defines reduce functionality and/or change the behavior of the + system in ways that may not be worth the trade-off. For example, the TX_TIMER_PROCESS_IN_ISR + results in faster and smaller code, however, it increases the amount of processing in the ISR. + In addition, some services that are available in timers are not available from ISRs and will + therefore return an error if this option is used. This may or may not be desirable for a + given application. */ + + +/* Override various options with default values already assigned in tx_port.h. Please also refer + to tx_port.h for descriptions on each of these options. */ + +/* +#define TX_MAX_PRIORITIES 32 +#define TX_MINIMUM_STACK ???? +#define TX_THREAD_USER_EXTENSION ???? +#define TX_TIMER_THREAD_STACK_SIZE ???? +#define TX_TIMER_THREAD_PRIORITY ???? +*/ + +/* Determine if timer expirations (application timers, timeouts, and tx_thread_sleep calls + should be processed within the a system timer thread or directly in the timer ISR. + By default, the timer thread is used. When the following is defined, the timer expiration + processing is done directly from the timer ISR, thereby eliminating the timer thread control + block, stack, and context switching to activate it. */ + +/* +#define TX_TIMER_PROCESS_IN_ISR +*/ + +/* Determine if in-line timer reactivation should be used within the timer expiration processing. + By default, this is disabled and a function call is used. When the following is defined, + reactivating is performed in-line resulting in faster timer processing but slightly larger + code size. */ + +/* +#define TX_REACTIVATE_INLINE +*/ + +/* Determine is stack filling is enabled. By default, ThreadX stack filling is enabled, + which places an 0xEF pattern in each byte of each thread's stack. This is used by + debuggers with ThreadX-awareness and by the ThreadX run-time stack checking feature. */ + +/* +#define TX_DISABLE_STACK_FILLING +*/ + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +/* +#define TX_ENABLE_STACK_CHECKING +*/ + +/* Determine if preemption-threshold should be disabled. By default, preemption-threshold is + enabled. If the application does not use preemption-threshold, it may be disabled to reduce + code size and improve performance. */ + +/* +#define TX_DISABLE_PREEMPTION_THRESHOLD +*/ + +/* Determine if global ThreadX variables should be cleared. If the compiler startup code clears + the .bss section prior to ThreadX running, the define can be used to eliminate unnecessary + clearing of ThreadX global variables. */ + +/* +#define TX_DISABLE_REDUNDANT_CLEARING +*/ + +/* Determine if no timer processing is required. This option will help eliminate the timer + processing when not needed. The user will also have to comment out the call to + tx_timer_interrupt, which is typically made from assembly language in + tx_initialize_low_level. Note: if TX_NO_TIMER is used, the define TX_TIMER_PROCESS_IN_ISR + must also be used. */ + +/* +#define TX_NO_TIMER +#ifndef TX_TIMER_PROCESS_IN_ISR +#define TX_TIMER_PROCESS_IN_ISR +#endif +*/ + +/* Determine if the notify callback option should be disabled. By default, notify callbacks are + enabled. If the application does not use notify callbacks, they may be disabled to reduce + code size and improve performance. */ + +/* +#define TX_DISABLE_NOTIFY_CALLBACKS +*/ + + +/* Determine if the tx_thread_resume and tx_thread_suspend services should have their internal + code in-line. This results in a larger image, but improves the performance of the thread + resume and suspend services. */ + +/* +#define TX_INLINE_THREAD_RESUME_SUSPEND +*/ + + +/* Determine if the internal ThreadX code is non-interruptable. This results in smaller code + size and less processing overhead, but increases the interrupt lockout time. */ + +/* +#define TX_NOT_INTERRUPTABLE +*/ + + +/* Determine if the trace event logging code should be enabled. This causes slight increases in + code size and overhead, but provides the ability to generate system trace information which + is available for viewing in TraceX. */ + +/* +#define TX_ENABLE_EVENT_TRACE +*/ + + +/* Determine if block pool performance gathering is required by the application. When the following is + defined, ThreadX gathers various block pool performance information. */ + +/* +#define TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if byte pool performance gathering is required by the application. When the following is + defined, ThreadX gathers various byte pool performance information. */ + +/* +#define TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if event flags performance gathering is required by the application. When the following is + defined, ThreadX gathers various event flags performance information. */ + +/* +#define TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if mutex performance gathering is required by the application. When the following is + defined, ThreadX gathers various mutex performance information. */ + +/* +#define TX_MUTEX_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if queue performance gathering is required by the application. When the following is + defined, ThreadX gathers various queue performance information. */ + +/* +#define TX_QUEUE_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if semaphore performance gathering is required by the application. When the following is + defined, ThreadX gathers various semaphore performance information. */ + +/* +#define TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if thread performance gathering is required by the application. When the following is + defined, ThreadX gathers various thread performance information. */ + +/* +#define TX_THREAD_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if timer performance gathering is required by the application. When the following is + defined, ThreadX gathers various timer performance information. */ + +/* +#define TX_TIMER_ENABLE_PERFORMANCE_INFO +*/ + +#endif + diff --git a/common_smp/src/tx_block_allocate.c b/common_smp/src/tx_block_allocate.c index 63bd5313..b27737b8 100644 --- a/common_smp/src/tx_block_allocate.c +++ b/common_smp/src/tx_block_allocate.c @@ -38,7 +38,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_block_allocate PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_block_allocate(TX_BLOCK_POOL *pool_ptr, VOID **block_ptr, ULONG wait_option) diff --git a/common_smp/src/tx_block_pool_cleanup.c b/common_smp/src/tx_block_pool_cleanup.c index ea18c8f9..8b37c8af 100644 --- a/common_smp/src/tx_block_pool_cleanup.c +++ b/common_smp/src/tx_block_pool_cleanup.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_block_pool_cleanup PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_block_pool_cleanup(TX_THREAD *thread_ptr, ULONG suspension_sequence) diff --git a/common_smp/src/tx_block_pool_create.c b/common_smp/src/tx_block_pool_create.c index 4d9f1d91..3f3beb75 100644 --- a/common_smp/src/tx_block_pool_create.c +++ b/common_smp/src/tx_block_pool_create.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_block_pool_create PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,7 +69,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_block_pool_create(TX_BLOCK_POOL *pool_ptr, CHAR *name_ptr, ULONG block_size, diff --git a/common_smp/src/tx_block_pool_delete.c b/common_smp/src/tx_block_pool_delete.c index 27ac2c24..87086e53 100644 --- a/common_smp/src/tx_block_pool_delete.c +++ b/common_smp/src/tx_block_pool_delete.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_block_pool_delete PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,7 +69,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_block_pool_delete(TX_BLOCK_POOL *pool_ptr) diff --git a/common_smp/src/tx_block_pool_info_get.c b/common_smp/src/tx_block_pool_info_get.c index 78930c36..1564e6dd 100644 --- a/common_smp/src/tx_block_pool_info_get.c +++ b/common_smp/src/tx_block_pool_info_get.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_block_pool_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_block_pool_info_get(TX_BLOCK_POOL *pool_ptr, CHAR **name, ULONG *available_blocks, diff --git a/common_smp/src/tx_block_pool_initialize.c b/common_smp/src/tx_block_pool_initialize.c index 0edb9786..9494a0e3 100644 --- a/common_smp/src/tx_block_pool_initialize.c +++ b/common_smp/src/tx_block_pool_initialize.c @@ -65,7 +65,6 @@ ULONG _tx_block_pool_performance_suspension_count; ULONG _tx_block_pool_performance_timeout_count; #endif -#endif /**************************************************************************/ @@ -73,7 +72,7 @@ ULONG _tx_block_pool_performance_timeout_count; /* FUNCTION RELEASE */ /* */ /* _tx_block pool_initialize PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -103,7 +102,7 @@ ULONG _tx_block_pool_performance_timeout_count; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_block_pool_initialize(VOID) @@ -126,4 +125,4 @@ VOID _tx_block_pool_initialize(VOID) #endif #endif } - +#endif diff --git a/common_smp/src/tx_block_pool_performance_info_get.c b/common_smp/src/tx_block_pool_performance_info_get.c index 65a31e0b..5a41661e 100644 --- a/common_smp/src/tx_block_pool_performance_info_get.c +++ b/common_smp/src/tx_block_pool_performance_info_get.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_block_pool_performance_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -75,7 +75,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_block_pool_performance_info_get(TX_BLOCK_POOL *pool_ptr, ULONG *allocates, ULONG *releases, diff --git a/common_smp/src/tx_block_pool_performance_system_info_get.c b/common_smp/src/tx_block_pool_performance_system_info_get.c index 383f91ba..300fd8fe 100644 --- a/common_smp/src/tx_block_pool_performance_system_info_get.c +++ b/common_smp/src/tx_block_pool_performance_system_info_get.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_block_pool_performance_system_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_block_pool_performance_system_info_get(ULONG *allocates, ULONG *releases, ULONG *suspensions, ULONG *timeouts) diff --git a/common_smp/src/tx_block_pool_prioritize.c b/common_smp/src/tx_block_pool_prioritize.c index e51932b1..92c75eaa 100644 --- a/common_smp/src/tx_block_pool_prioritize.c +++ b/common_smp/src/tx_block_pool_prioritize.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_block_pool_prioritize PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,7 +67,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_block_pool_prioritize(TX_BLOCK_POOL *pool_ptr) diff --git a/common_smp/src/tx_block_release.c b/common_smp/src/tx_block_release.c index 69e1d442..bb610900 100644 --- a/common_smp/src/tx_block_release.c +++ b/common_smp/src/tx_block_release.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_block_release PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,7 +67,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_block_release(VOID *block_ptr) diff --git a/common_smp/src/tx_byte_allocate.c b/common_smp/src/tx_byte_allocate.c index a4cbadf4..427ad9e0 100644 --- a/common_smp/src/tx_byte_allocate.c +++ b/common_smp/src/tx_byte_allocate.c @@ -38,7 +38,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_byte_allocate PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -74,7 +74,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_byte_allocate(TX_BYTE_POOL *pool_ptr, VOID **memory_ptr, ULONG memory_size, ULONG wait_option) diff --git a/common_smp/src/tx_byte_pool_cleanup.c b/common_smp/src/tx_byte_pool_cleanup.c index 6beca7c2..1ad620ce 100644 --- a/common_smp/src/tx_byte_pool_cleanup.c +++ b/common_smp/src/tx_byte_pool_cleanup.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_byte_pool_cleanup PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_byte_pool_cleanup(TX_THREAD *thread_ptr, ULONG suspension_sequence) diff --git a/common_smp/src/tx_byte_pool_create.c b/common_smp/src/tx_byte_pool_create.c index 25075458..4819f7a8 100644 --- a/common_smp/src/tx_byte_pool_create.c +++ b/common_smp/src/tx_byte_pool_create.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_byte_pool_create PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_byte_pool_create(TX_BYTE_POOL *pool_ptr, CHAR *name_ptr, VOID *pool_start, ULONG pool_size) diff --git a/common_smp/src/tx_byte_pool_delete.c b/common_smp/src/tx_byte_pool_delete.c index c4c84e38..8595ec1f 100644 --- a/common_smp/src/tx_byte_pool_delete.c +++ b/common_smp/src/tx_byte_pool_delete.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_byte_pool_delete PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -73,7 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_byte_pool_delete(TX_BYTE_POOL *pool_ptr) diff --git a/common_smp/src/tx_byte_pool_info_get.c b/common_smp/src/tx_byte_pool_info_get.c index 028c251b..c5b18b07 100644 --- a/common_smp/src/tx_byte_pool_info_get.c +++ b/common_smp/src/tx_byte_pool_info_get.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_byte_pool_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_byte_pool_info_get(TX_BYTE_POOL *pool_ptr, CHAR **name, ULONG *available_bytes, diff --git a/common_smp/src/tx_byte_pool_initialize.c b/common_smp/src/tx_byte_pool_initialize.c index 5ad4c1cb..f77b33c5 100644 --- a/common_smp/src/tx_byte_pool_initialize.c +++ b/common_smp/src/tx_byte_pool_initialize.c @@ -80,7 +80,6 @@ ULONG _tx_byte_pool_performance_suspension_count; ULONG _tx_byte_pool_performance_timeout_count; #endif -#endif /**************************************************************************/ @@ -88,7 +87,7 @@ ULONG _tx_byte_pool_performance_timeout_count; /* FUNCTION RELEASE */ /* */ /* _tx_byte_pool_initialize PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -118,7 +117,7 @@ ULONG _tx_byte_pool_performance_timeout_count; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_byte_pool_initialize(VOID) @@ -144,4 +143,4 @@ VOID _tx_byte_pool_initialize(VOID) #endif #endif } - +#endif diff --git a/common_smp/src/tx_byte_pool_performance_info_get.c b/common_smp/src/tx_byte_pool_performance_info_get.c index 0c93e270..e78eb356 100644 --- a/common_smp/src/tx_byte_pool_performance_info_get.c +++ b/common_smp/src/tx_byte_pool_performance_info_get.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_byte_pool_performance_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -83,7 +83,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_byte_pool_performance_info_get(TX_BYTE_POOL *pool_ptr, ULONG *allocates, ULONG *releases, diff --git a/common_smp/src/tx_byte_pool_performance_system_info_get.c b/common_smp/src/tx_byte_pool_performance_system_info_get.c index 67c84cbf..6f2bce3e 100644 --- a/common_smp/src/tx_byte_pool_performance_system_info_get.c +++ b/common_smp/src/tx_byte_pool_performance_system_info_get.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_byte_pool_performance_system_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -80,7 +80,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_byte_pool_performance_system_info_get(ULONG *allocates, ULONG *releases, diff --git a/common_smp/src/tx_byte_pool_prioritize.c b/common_smp/src/tx_byte_pool_prioritize.c index 516bd67e..a72d6290 100644 --- a/common_smp/src/tx_byte_pool_prioritize.c +++ b/common_smp/src/tx_byte_pool_prioritize.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_byte_pool_prioritize PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,7 +67,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_byte_pool_prioritize(TX_BYTE_POOL *pool_ptr) diff --git a/common_smp/src/tx_byte_pool_search.c b/common_smp/src/tx_byte_pool_search.c index 18dbe2b8..57ef5288 100644 --- a/common_smp/src/tx_byte_pool_search.c +++ b/common_smp/src/tx_byte_pool_search.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_byte_pool_search PORTABLE SMP */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -76,7 +76,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UCHAR *_tx_byte_pool_search(TX_BYTE_POOL *pool_ptr, ULONG memory_size) diff --git a/common_smp/src/tx_byte_release.c b/common_smp/src/tx_byte_release.c index c1e5d702..7b8b50d8 100644 --- a/common_smp/src/tx_byte_release.c +++ b/common_smp/src/tx_byte_release.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_byte_release PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,7 +69,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_byte_release(VOID *memory_ptr) diff --git a/common_smp/src/tx_event_flags_cleanup.c b/common_smp/src/tx_event_flags_cleanup.c index 53fc8d34..3700b0fa 100644 --- a/common_smp/src/tx_event_flags_cleanup.c +++ b/common_smp/src/tx_event_flags_cleanup.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_event_flags_cleanup PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_event_flags_cleanup(TX_THREAD *thread_ptr, ULONG suspension_sequence) diff --git a/common_smp/src/tx_event_flags_create.c b/common_smp/src/tx_event_flags_create.c index bb52b670..cc06e755 100644 --- a/common_smp/src/tx_event_flags_create.c +++ b/common_smp/src/tx_event_flags_create.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_event_flags_create PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,7 +67,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_event_flags_create(TX_EVENT_FLAGS_GROUP *group_ptr, CHAR *name_ptr) diff --git a/common_smp/src/tx_event_flags_delete.c b/common_smp/src/tx_event_flags_delete.c index 392b5f04..c0368223 100644 --- a/common_smp/src/tx_event_flags_delete.c +++ b/common_smp/src/tx_event_flags_delete.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_event_flags_delete PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,7 +69,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_event_flags_delete(TX_EVENT_FLAGS_GROUP *group_ptr) diff --git a/common_smp/src/tx_event_flags_get.c b/common_smp/src/tx_event_flags_get.c index aafe244e..c991fc08 100644 --- a/common_smp/src/tx_event_flags_get.c +++ b/common_smp/src/tx_event_flags_get.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_event_flags_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -73,7 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_event_flags_get(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG requested_flags, diff --git a/common_smp/src/tx_event_flags_info_get.c b/common_smp/src/tx_event_flags_info_get.c index 5e5524fd..a474ea2e 100644 --- a/common_smp/src/tx_event_flags_info_get.c +++ b/common_smp/src/tx_event_flags_info_get.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_event_flags_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -74,7 +74,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_event_flags_info_get(TX_EVENT_FLAGS_GROUP *group_ptr, CHAR **name, ULONG *current_flags, diff --git a/common_smp/src/tx_event_flags_initialize.c b/common_smp/src/tx_event_flags_initialize.c index f9f4ab5d..96f8ee00 100644 --- a/common_smp/src/tx_event_flags_initialize.c +++ b/common_smp/src/tx_event_flags_initialize.c @@ -65,7 +65,6 @@ ULONG _tx_event_flags_performance_timeout_count; #endif -#endif @@ -74,7 +73,7 @@ ULONG _tx_event_flags_performance_timeout_count; /* FUNCTION RELEASE */ /* */ /* _tx_event_flags_initialize PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -104,7 +103,7 @@ ULONG _tx_event_flags_performance_timeout_count; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_event_flags_initialize(VOID) @@ -127,4 +126,4 @@ VOID _tx_event_flags_initialize(VOID) #endif #endif } - +#endif diff --git a/common_smp/src/tx_event_flags_performance_info_get.c b/common_smp/src/tx_event_flags_performance_info_get.c index 6c410cf6..2e15c9fc 100644 --- a/common_smp/src/tx_event_flags_performance_info_get.c +++ b/common_smp/src/tx_event_flags_performance_info_get.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_event_flags_performance_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -76,7 +76,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_event_flags_performance_info_get(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG *sets, ULONG *gets, diff --git a/common_smp/src/tx_event_flags_performance_system_info_get.c b/common_smp/src/tx_event_flags_performance_system_info_get.c index 65c33973..d9803a4f 100644 --- a/common_smp/src/tx_event_flags_performance_system_info_get.c +++ b/common_smp/src/tx_event_flags_performance_system_info_get.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_event_flags_performance_system_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -73,7 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_event_flags_performance_system_info_get(ULONG *sets, ULONG *gets, ULONG *suspensions, ULONG *timeouts) diff --git a/common_smp/src/tx_event_flags_set.c b/common_smp/src/tx_event_flags_set.c index 7710be6b..b1212810 100644 --- a/common_smp/src/tx_event_flags_set.c +++ b/common_smp/src/tx_event_flags_set.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_event_flags_set PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_event_flags_set(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG flags_to_set, UINT set_option) diff --git a/common_smp/src/tx_event_flags_set_notify.c b/common_smp/src/tx_event_flags_set_notify.c index 3168c876..47e8e598 100644 --- a/common_smp/src/tx_event_flags_set_notify.c +++ b/common_smp/src/tx_event_flags_set_notify.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_event_flags_set_notify PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,7 +67,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_event_flags_set_notify(TX_EVENT_FLAGS_GROUP *group_ptr, VOID (*events_set_notify)(TX_EVENT_FLAGS_GROUP *notify_group_ptr)) diff --git a/common_smp/src/tx_initialize_high_level.c b/common_smp/src/tx_initialize_high_level.c index fe4f2965..2e4d6262 100644 --- a/common_smp/src/tx_initialize_high_level.c +++ b/common_smp/src/tx_initialize_high_level.c @@ -57,7 +57,7 @@ VOID *_tx_initialize_unused_memory; /* FUNCTION RELEASE */ /* */ /* _tx_initialize_high_level PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -105,7 +105,7 @@ VOID *_tx_initialize_unused_memory; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_initialize_high_level(VOID) diff --git a/common_smp/src/tx_initialize_kernel_enter.c b/common_smp/src/tx_initialize_kernel_enter.c index 990bea11..9b31a0d5 100644 --- a/common_smp/src/tx_initialize_kernel_enter.c +++ b/common_smp/src/tx_initialize_kernel_enter.c @@ -47,7 +47,7 @@ TX_SAFETY_CRITICAL_EXCEPTION_HANDLER /* FUNCTION RELEASE */ /* */ /* _tx_initialize_kernel_enter PORTABLE SMP */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -87,7 +87,7 @@ TX_SAFETY_CRITICAL_EXCEPTION_HANDLER /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_initialize_kernel_enter(VOID) diff --git a/common_smp/src/tx_initialize_kernel_setup.c b/common_smp/src/tx_initialize_kernel_setup.c index c00bb592..73474a3b 100644 --- a/common_smp/src/tx_initialize_kernel_setup.c +++ b/common_smp/src/tx_initialize_kernel_setup.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_initialize_kernel_setup PORTABLE SMP */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_initialize_kernel_setup(VOID) diff --git a/common_smp/src/tx_misra.c b/common_smp/src/tx_misra.c index 291ff091..ae2280ef 100644 --- a/common_smp/src/tx_misra.c +++ b/common_smp/src/tx_misra.c @@ -31,8 +31,7 @@ #ifdef TX_MISRA_ENABLE #define TX_THREAD_INIT -//CHAR _tx_version_id[100] = "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX 6.0.1 MISRA C Compliant *"; -#endif +//CHAR _tx_version_id[100] = "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX 6.1 MISRA C Compliant *"; #include "tx_api.h" #include "tx_thread.h" @@ -830,4 +829,5 @@ UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer) } +#endif diff --git a/common_smp/src/tx_mutex_cleanup.c b/common_smp/src/tx_mutex_cleanup.c index 88d6e313..09ca5904 100644 --- a/common_smp/src/tx_mutex_cleanup.c +++ b/common_smp/src/tx_mutex_cleanup.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_mutex_cleanup PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_mutex_cleanup(TX_THREAD *thread_ptr, ULONG suspension_sequence) @@ -218,7 +218,7 @@ TX_THREAD *previous_thread; /* FUNCTION RELEASE */ /* */ /* _tx_mutex_thread_release PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -249,7 +249,7 @@ TX_THREAD *previous_thread; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_mutex_thread_release(TX_THREAD *thread_ptr) diff --git a/common_smp/src/tx_mutex_create.c b/common_smp/src/tx_mutex_create.c index ea53fe2d..4b459f33 100644 --- a/common_smp/src/tx_mutex_create.c +++ b/common_smp/src/tx_mutex_create.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_mutex_create PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_mutex_create(TX_MUTEX *mutex_ptr, CHAR *name_ptr, UINT inherit) diff --git a/common_smp/src/tx_mutex_delete.c b/common_smp/src/tx_mutex_delete.c index 0f91ed3f..c7ea53c9 100644 --- a/common_smp/src/tx_mutex_delete.c +++ b/common_smp/src/tx_mutex_delete.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_mutex_delete PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_mutex_delete(TX_MUTEX *mutex_ptr) diff --git a/common_smp/src/tx_mutex_get.c b/common_smp/src/tx_mutex_get.c index 98b019d2..14f91d4e 100644 --- a/common_smp/src/tx_mutex_get.c +++ b/common_smp/src/tx_mutex_get.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_mutex_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,7 +69,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_mutex_get(TX_MUTEX *mutex_ptr, ULONG wait_option) diff --git a/common_smp/src/tx_mutex_info_get.c b/common_smp/src/tx_mutex_info_get.c index 769ce02d..5774798e 100644 --- a/common_smp/src/tx_mutex_info_get.c +++ b/common_smp/src/tx_mutex_info_get.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_mutex_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -73,7 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_mutex_info_get(TX_MUTEX *mutex_ptr, CHAR **name, ULONG *count, TX_THREAD **owner, diff --git a/common_smp/src/tx_mutex_initialize.c b/common_smp/src/tx_mutex_initialize.c index 3d53a99e..39057e28 100644 --- a/common_smp/src/tx_mutex_initialize.c +++ b/common_smp/src/tx_mutex_initialize.c @@ -75,7 +75,6 @@ ULONG _tx_mutex_performance_priority_inversion_count; ULONG _tx_mutex_performance__priority_inheritance_count; #endif -#endif /**************************************************************************/ @@ -83,7 +82,7 @@ ULONG _tx_mutex_performance__priority_inheritance_count; /* FUNCTION RELEASE */ /* */ /* _tx_mutex_initialize PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -113,7 +112,7 @@ ULONG _tx_mutex_performance__priority_inheritance_count; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_mutex_initialize(VOID) @@ -138,4 +137,4 @@ VOID _tx_mutex_initialize(VOID) #endif #endif } - +#endif diff --git a/common_smp/src/tx_mutex_performance_info_get.c b/common_smp/src/tx_mutex_performance_info_get.c index 2ae2849d..496be285 100644 --- a/common_smp/src/tx_mutex_performance_info_get.c +++ b/common_smp/src/tx_mutex_performance_info_get.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_mutex_performance_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -78,7 +78,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_mutex_performance_info_get(TX_MUTEX *mutex_ptr, ULONG *puts, ULONG *gets, diff --git a/common_smp/src/tx_mutex_performance_system_info_get.c b/common_smp/src/tx_mutex_performance_system_info_get.c index df385b5e..9c4155f4 100644 --- a/common_smp/src/tx_mutex_performance_system_info_get.c +++ b/common_smp/src/tx_mutex_performance_system_info_get.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_mutex_performance_system_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_mutex_performance_system_info_get(ULONG *puts, ULONG *gets, ULONG *suspensions, diff --git a/common_smp/src/tx_mutex_prioritize.c b/common_smp/src/tx_mutex_prioritize.c index 38664b97..dd38d1b4 100644 --- a/common_smp/src/tx_mutex_prioritize.c +++ b/common_smp/src/tx_mutex_prioritize.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_mutex_prioritize PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,7 +67,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_mutex_prioritize(TX_MUTEX *mutex_ptr) diff --git a/common_smp/src/tx_mutex_priority_change.c b/common_smp/src/tx_mutex_priority_change.c index 0c5c705b..5a5587af 100644 --- a/common_smp/src/tx_mutex_priority_change.c +++ b/common_smp/src/tx_mutex_priority_change.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_mutex_priority_change PORTABLE SMP */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -76,7 +76,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_mutex_priority_change(TX_THREAD *thread_ptr, UINT new_priority) @@ -236,8 +236,8 @@ UINT finished; /* Increment the preempt disable flag. */ _tx_thread_preempt_disable++; - /* Set the state to suspended. */ - thread_ptr -> tx_thread_state = TX_SUSPENDED; + /* Set the state to priority change. */ + thread_ptr -> tx_thread_state = TX_PRIORITY_CHANGE; /* Call actual non-interruptable thread suspension routine. */ _tx_thread_system_ni_suspend(thread_ptr, ((ULONG) 0)); @@ -283,8 +283,8 @@ UINT finished; /* Increment the preempt disable flag. */ _tx_thread_preempt_disable = _tx_thread_preempt_disable + ((UINT) 2); - /* Set the state to suspended. */ - thread_ptr -> tx_thread_state = TX_SUSPENDED; + /* Set the state to priority change. */ + thread_ptr -> tx_thread_state = TX_PRIORITY_CHANGE; /* Set the suspending flag. */ thread_ptr -> tx_thread_suspending = TX_TRUE; @@ -353,19 +353,24 @@ UINT finished; if (thread_ptr == execute_ptr) { -#ifndef TX_DISABLE_PREEMPTION_THRESHOLD - /* Determine if preemption-threshold is in force at the new priority level. */ - if (_tx_thread_preemption_threshold_list[thread_ptr -> tx_thread_priority] == TX_NULL) + /* Make sure the thread is still ready. */ + if (thread_ptr -> tx_thread_state == TX_READY) { - - /* Ensure that this thread is placed at the front of the priority list. */ - _tx_thread_priority_list[thread_ptr -> tx_thread_priority] = thread_ptr; - } + +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD + /* Determine if preemption-threshold is in force at the new priority level. */ + if (_tx_thread_preemption_threshold_list[thread_ptr -> tx_thread_priority] == TX_NULL) + { + + /* Ensure that this thread is placed at the front of the priority list. */ + _tx_thread_priority_list[thread_ptr -> tx_thread_priority] = thread_ptr; + } #else - /* Ensure that this thread is placed at the front of the priority list. */ - _tx_thread_priority_list[thread_ptr -> tx_thread_priority] = thread_ptr; + /* Ensure that this thread is placed at the front of the priority list. */ + _tx_thread_priority_list[thread_ptr -> tx_thread_priority] = thread_ptr; #endif + } } /* Pickup the core index. */ diff --git a/common_smp/src/tx_mutex_put.c b/common_smp/src/tx_mutex_put.c index 45cb1c4b..4f1aebd2 100644 --- a/common_smp/src/tx_mutex_put.c +++ b/common_smp/src/tx_mutex_put.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_mutex_put PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_mutex_put(TX_MUTEX *mutex_ptr) diff --git a/common_smp/src/tx_queue_cleanup.c b/common_smp/src/tx_queue_cleanup.c index 43dc3341..0d289404 100644 --- a/common_smp/src/tx_queue_cleanup.c +++ b/common_smp/src/tx_queue_cleanup.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_queue_cleanup PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_queue_cleanup(TX_THREAD *thread_ptr, ULONG suspension_sequence) diff --git a/common_smp/src/tx_queue_create.c b/common_smp/src/tx_queue_create.c index 698d4548..5f700843 100644 --- a/common_smp/src/tx_queue_create.c +++ b/common_smp/src/tx_queue_create.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_queue_create PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,7 +69,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_queue_create(TX_QUEUE *queue_ptr, CHAR *name_ptr, UINT message_size, diff --git a/common_smp/src/tx_queue_delete.c b/common_smp/src/tx_queue_delete.c index 067e7655..a2755a50 100644 --- a/common_smp/src/tx_queue_delete.c +++ b/common_smp/src/tx_queue_delete.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_queue_delete PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_queue_delete(TX_QUEUE *queue_ptr) diff --git a/common_smp/src/tx_queue_flush.c b/common_smp/src/tx_queue_flush.c index cd0acf12..99bdb407 100644 --- a/common_smp/src/tx_queue_flush.c +++ b/common_smp/src/tx_queue_flush.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_queue_flush PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,7 +69,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_queue_flush(TX_QUEUE *queue_ptr) diff --git a/common_smp/src/tx_queue_front_send.c b/common_smp/src/tx_queue_front_send.c index 45edb803..1f14bce6 100644 --- a/common_smp/src/tx_queue_front_send.c +++ b/common_smp/src/tx_queue_front_send.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_queue_front_send PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_queue_front_send(TX_QUEUE *queue_ptr, VOID *source_ptr, ULONG wait_option) diff --git a/common_smp/src/tx_queue_info_get.c b/common_smp/src/tx_queue_info_get.c index 2a9dce14..0e388450 100644 --- a/common_smp/src/tx_queue_info_get.c +++ b/common_smp/src/tx_queue_info_get.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_queue_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_queue_info_get(TX_QUEUE *queue_ptr, CHAR **name, ULONG *enqueued, ULONG *available_storage, diff --git a/common_smp/src/tx_queue_initialize.c b/common_smp/src/tx_queue_initialize.c index e594d946..90b1b9bd 100644 --- a/common_smp/src/tx_queue_initialize.c +++ b/common_smp/src/tx_queue_initialize.c @@ -73,7 +73,6 @@ ULONG _tx_queue_performance_full_error_count; ULONG _tx_queue_performance_timeout_count; #endif -#endif /**************************************************************************/ @@ -81,7 +80,7 @@ ULONG _tx_queue_performance_timeout_count; /* FUNCTION RELEASE */ /* */ /* _tx_queue_initialize PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -111,7 +110,7 @@ ULONG _tx_queue_performance_timeout_count; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_queue_initialize(VOID) @@ -135,4 +134,4 @@ VOID _tx_queue_initialize(VOID) #endif #endif } - +#endif diff --git a/common_smp/src/tx_queue_performance_info_get.c b/common_smp/src/tx_queue_performance_info_get.c index 6c34a3a3..7d333efb 100644 --- a/common_smp/src/tx_queue_performance_info_get.c +++ b/common_smp/src/tx_queue_performance_info_get.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_queue_performance_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_queue_performance_info_get(TX_QUEUE *queue_ptr, ULONG *messages_sent, ULONG *messages_received, diff --git a/common_smp/src/tx_queue_performance_system_info_get.c b/common_smp/src/tx_queue_performance_system_info_get.c index edba3b41..68b6f4b0 100644 --- a/common_smp/src/tx_queue_performance_system_info_get.c +++ b/common_smp/src/tx_queue_performance_system_info_get.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_queue_performance_system_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_queue_performance_system_info_get(ULONG *messages_sent, ULONG *messages_received, diff --git a/common_smp/src/tx_queue_prioritize.c b/common_smp/src/tx_queue_prioritize.c index 98fde588..54132aa4 100644 --- a/common_smp/src/tx_queue_prioritize.c +++ b/common_smp/src/tx_queue_prioritize.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_queue_prioritize PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,7 +67,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_queue_prioritize(TX_QUEUE *queue_ptr) diff --git a/common_smp/src/tx_queue_receive.c b/common_smp/src/tx_queue_receive.c index 56094f92..5d4b2282 100644 --- a/common_smp/src/tx_queue_receive.c +++ b/common_smp/src/tx_queue_receive.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_queue_receive PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -74,7 +74,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_queue_receive(TX_QUEUE *queue_ptr, VOID *destination_ptr, ULONG wait_option) diff --git a/common_smp/src/tx_queue_send.c b/common_smp/src/tx_queue_send.c index 61f48c47..8163350a 100644 --- a/common_smp/src/tx_queue_send.c +++ b/common_smp/src/tx_queue_send.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_queue_send PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_queue_send(TX_QUEUE *queue_ptr, VOID *source_ptr, ULONG wait_option) diff --git a/common_smp/src/tx_queue_send_notify.c b/common_smp/src/tx_queue_send_notify.c index 8bbf26ce..17784bcb 100644 --- a/common_smp/src/tx_queue_send_notify.c +++ b/common_smp/src/tx_queue_send_notify.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_queue_send_notify PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,7 +67,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_queue_send_notify(TX_QUEUE *queue_ptr, VOID (*queue_send_notify)(TX_QUEUE *notify_queue_ptr)) diff --git a/common_smp/src/tx_semaphore_ceiling_put.c b/common_smp/src/tx_semaphore_ceiling_put.c index 8c41a336..c79dd89c 100644 --- a/common_smp/src/tx_semaphore_ceiling_put.c +++ b/common_smp/src/tx_semaphore_ceiling_put.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_semaphore_ceiling_put PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,7 +69,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_semaphore_ceiling_put(TX_SEMAPHORE *semaphore_ptr, ULONG ceiling) diff --git a/common_smp/src/tx_semaphore_cleanup.c b/common_smp/src/tx_semaphore_cleanup.c index 711a5bb4..7ba868b9 100644 --- a/common_smp/src/tx_semaphore_cleanup.c +++ b/common_smp/src/tx_semaphore_cleanup.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_semaphore_cleanup PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_semaphore_cleanup(TX_THREAD *thread_ptr, ULONG suspension_sequence) diff --git a/common_smp/src/tx_semaphore_create.c b/common_smp/src/tx_semaphore_create.c index 0a0d6d3c..26db171b 100644 --- a/common_smp/src/tx_semaphore_create.c +++ b/common_smp/src/tx_semaphore_create.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_semaphore_create PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,7 +67,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_semaphore_create(TX_SEMAPHORE *semaphore_ptr, CHAR *name_ptr, ULONG initial_count) diff --git a/common_smp/src/tx_semaphore_delete.c b/common_smp/src/tx_semaphore_delete.c index 962c78b9..20b5fe09 100644 --- a/common_smp/src/tx_semaphore_delete.c +++ b/common_smp/src/tx_semaphore_delete.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_semaphore_delete PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,7 +69,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_semaphore_delete(TX_SEMAPHORE *semaphore_ptr) diff --git a/common_smp/src/tx_semaphore_get.c b/common_smp/src/tx_semaphore_get.c index 0cec8daa..36149566 100644 --- a/common_smp/src/tx_semaphore_get.c +++ b/common_smp/src/tx_semaphore_get.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_semaphore_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_semaphore_get(TX_SEMAPHORE *semaphore_ptr, ULONG wait_option) diff --git a/common_smp/src/tx_semaphore_info_get.c b/common_smp/src/tx_semaphore_info_get.c index 42fb990d..23d1fa35 100644 --- a/common_smp/src/tx_semaphore_info_get.c +++ b/common_smp/src/tx_semaphore_info_get.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_semaphore_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_semaphore_info_get(TX_SEMAPHORE *semaphore_ptr, CHAR **name, ULONG *current_value, diff --git a/common_smp/src/tx_semaphore_initialize.c b/common_smp/src/tx_semaphore_initialize.c index b86dfe02..338d9f1a 100644 --- a/common_smp/src/tx_semaphore_initialize.c +++ b/common_smp/src/tx_semaphore_initialize.c @@ -65,7 +65,6 @@ ULONG _tx_semaphore_performance_suspension_count; ULONG _tx_semaphore_performance_timeout_count; #endif -#endif /**************************************************************************/ @@ -73,7 +72,7 @@ ULONG _tx_semaphore_performance_timeout_count; /* FUNCTION RELEASE */ /* */ /* _tx_semaphore_initialize PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -103,7 +102,7 @@ ULONG _tx_semaphore_performance_timeout_count; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_semaphore_initialize(VOID) @@ -126,4 +125,4 @@ VOID _tx_semaphore_initialize(VOID) #endif #endif } - +#endif diff --git a/common_smp/src/tx_semaphore_performance_info_get.c b/common_smp/src/tx_semaphore_performance_info_get.c index 7457ae89..5dcac91e 100644 --- a/common_smp/src/tx_semaphore_performance_info_get.c +++ b/common_smp/src/tx_semaphore_performance_info_get.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_semaphore_performance_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -75,7 +75,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_semaphore_performance_info_get(TX_SEMAPHORE *semaphore_ptr, ULONG *puts, ULONG *gets, diff --git a/common_smp/src/tx_semaphore_performance_system_info_get.c b/common_smp/src/tx_semaphore_performance_system_info_get.c index c1fe425c..22aef065 100644 --- a/common_smp/src/tx_semaphore_performance_system_info_get.c +++ b/common_smp/src/tx_semaphore_performance_system_info_get.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_semaphore_performance_system_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -73,7 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_semaphore_performance_system_info_get(ULONG *puts, ULONG *gets, ULONG *suspensions, ULONG *timeouts) diff --git a/common_smp/src/tx_semaphore_prioritize.c b/common_smp/src/tx_semaphore_prioritize.c index 41e60988..c3bd686b 100644 --- a/common_smp/src/tx_semaphore_prioritize.c +++ b/common_smp/src/tx_semaphore_prioritize.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_semaphore_prioritize PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,7 +67,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_semaphore_prioritize(TX_SEMAPHORE *semaphore_ptr) diff --git a/common_smp/src/tx_semaphore_put.c b/common_smp/src/tx_semaphore_put.c index b2b37568..53748cf1 100644 --- a/common_smp/src/tx_semaphore_put.c +++ b/common_smp/src/tx_semaphore_put.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_semaphore_put PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,7 +67,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_semaphore_put(TX_SEMAPHORE *semaphore_ptr) diff --git a/common_smp/src/tx_semaphore_put_notify.c b/common_smp/src/tx_semaphore_put_notify.c index f2918aa0..9425b22e 100644 --- a/common_smp/src/tx_semaphore_put_notify.c +++ b/common_smp/src/tx_semaphore_put_notify.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_semaphore_put_notify PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,7 +67,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_semaphore_put_notify(TX_SEMAPHORE *semaphore_ptr, VOID (*semaphore_put_notify)(TX_SEMAPHORE *notify_semaphore_ptr)) diff --git a/common_smp/src/tx_thread_create.c b/common_smp/src/tx_thread_create.c index f92e8381..63440bcc 100644 --- a/common_smp/src/tx_thread_create.c +++ b/common_smp/src/tx_thread_create.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_create PORTABLE SMP */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -80,7 +80,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_create(TX_THREAD *thread_ptr, CHAR *name_ptr, VOID (*entry_function)(ULONG id), ULONG entry_input, @@ -95,8 +95,8 @@ TX_THREAD *next_thread; TX_THREAD *previous_thread; UCHAR *temp_ptr; #ifdef TX_ENABLE_STACK_CHECKING -ULONG new_stack_start; -ULONG updated_stack_start; +ALIGN_TYPE new_stack_start; +ALIGN_TYPE updated_stack_start; #endif @@ -116,7 +116,7 @@ ULONG updated_stack_start; stack_size = ((stack_size/(sizeof(ULONG))) * (sizeof(ULONG))) - (sizeof(ULONG)); /* Ensure the starting stack address is evenly aligned. */ - new_stack_start = TX_POINTER_TO_ULONG_CONVERT(stack_start); + new_stack_start = TX_POINTER_TO_ALIGN_TYPE_CONVERT(stack_start); updated_stack_start = ((((ULONG) new_stack_start) + ((sizeof(ULONG)) - ((ULONG) 1)) ) & (~((sizeof(ULONG)) - ((ULONG) 1)))); /* Determine if the starting stack address is different. */ @@ -128,7 +128,7 @@ ULONG updated_stack_start; } /* Update the starting stack pointer. */ - stack_start = TX_ULONG_TO_POINTER_CONVERT(updated_stack_start); + stack_start = TX_ALIGN_TYPE_TO_POINTER_CONVERT(updated_stack_start); #endif /* Prepare the thread control block prior to placing it on the created @@ -266,6 +266,12 @@ ULONG updated_stack_start; /* Log this kernel call. */ TX_EL_THREAD_CREATE_INSERT + +#ifndef TX_NOT_INTERRUPTABLE + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; +#endif /* Determine if an automatic start was requested. If so, call the resume thread function and then check for a preemption condition. */ @@ -282,9 +288,6 @@ ULONG updated_stack_start; #else - /* Temporarily disable preemption. */ - _tx_thread_preempt_disable++; - /* Restore previous interrupt posture. */ TX_RESTORE @@ -335,10 +338,44 @@ ULONG updated_stack_start; _tx_thread_smp_debug_entry_insert(13, 0, thread_ptr); #endif } - } - /* Restore interrupts. */ - TX_RESTORE +#ifndef TX_NOT_INTERRUPTABLE + + /* Restore interrupts. */ + TX_RESTORE +#endif + } + else + { + +#ifdef TX_NOT_INTERRUPTABLE + + /* Perform any additional activities for tool or user purpose. */ + TX_THREAD_CREATE_EXTENSION(thread_ptr) + + /* Restore interrupts. */ + TX_RESTORE +#else + + /* Restore interrupts. */ + TX_RESTORE + + /* Perform any additional activities for tool or user purpose. */ + TX_THREAD_CREATE_EXTENSION(thread_ptr) + + /* Disable interrupts. */ + TX_DISABLE + + /* Re-enable preemption. */ + _tx_thread_preempt_disable--; + + /* Restore interrupts. */ + TX_RESTORE + + /* Check for preemption. */ + _tx_thread_system_preempt_check(); +#endif + } /* Always return a success. */ return(TX_SUCCESS); diff --git a/common_smp/src/tx_thread_delete.c b/common_smp/src/tx_thread_delete.c index 1fcaa482..f5519ab9 100644 --- a/common_smp/src/tx_thread_delete.c +++ b/common_smp/src/tx_thread_delete.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_delete PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -66,7 +66,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_delete(TX_THREAD *thread_ptr) diff --git a/common_smp/src/tx_thread_entry_exit_notify.c b/common_smp/src/tx_thread_entry_exit_notify.c index 1625ba25..a32e5bdb 100644 --- a/common_smp/src/tx_thread_entry_exit_notify.c +++ b/common_smp/src/tx_thread_entry_exit_notify.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_entry_exit_notify PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,7 +69,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_entry_exit_notify(TX_THREAD *thread_ptr, VOID (*thread_entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT id)) diff --git a/common_smp/src/tx_thread_identify.c b/common_smp/src/tx_thread_identify.c index 21116f4e..04592a90 100644 --- a/common_smp/src/tx_thread_identify.c +++ b/common_smp/src/tx_thread_identify.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_identify PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ TX_THREAD *_tx_thread_identify(VOID) diff --git a/common_smp/src/tx_thread_info_get.c b/common_smp/src/tx_thread_info_get.c index a4068920..b509445a 100644 --- a/common_smp/src/tx_thread_info_get.c +++ b/common_smp/src/tx_thread_info_get.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -75,7 +75,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_info_get(TX_THREAD *thread_ptr, CHAR **name, UINT *state, ULONG *run_count, diff --git a/common_smp/src/tx_thread_initialize.c b/common_smp/src/tx_thread_initialize.c index 7aa9b221..2e3e521e 100644 --- a/common_smp/src/tx_thread_initialize.c +++ b/common_smp/src/tx_thread_initialize.c @@ -316,7 +316,7 @@ const CHAR _tx_thread_special_string[] = /* FUNCTION RELEASE */ /* */ /* _tx_thread_initialize PORTABLE SMP */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -346,7 +346,7 @@ const CHAR _tx_thread_special_string[] = /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_initialize(VOID) diff --git a/common_smp/src/tx_thread_performance_info_get.c b/common_smp/src/tx_thread_performance_info_get.c index 718fecf6..d7a9c84a 100644 --- a/common_smp/src/tx_thread_performance_info_get.c +++ b/common_smp/src/tx_thread_performance_info_get.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_performance_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -92,7 +92,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_performance_info_get(TX_THREAD *thread_ptr, ULONG *resumptions, ULONG *suspensions, diff --git a/common_smp/src/tx_thread_performance_system_info_get.c b/common_smp/src/tx_thread_performance_system_info_get.c index 8f4d776e..3f8a5608 100644 --- a/common_smp/src/tx_thread_performance_system_info_get.c +++ b/common_smp/src/tx_thread_performance_system_info_get.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_performance_system_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -92,7 +92,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_performance_system_info_get(ULONG *resumptions, ULONG *suspensions, diff --git a/common_smp/src/tx_thread_preemption_change.c b/common_smp/src/tx_thread_preemption_change.c index a43cb21f..f0330b25 100644 --- a/common_smp/src/tx_thread_preemption_change.c +++ b/common_smp/src/tx_thread_preemption_change.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_preemption_change PORTABLE SMP */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_preemption_change(TX_THREAD *thread_ptr, UINT new_threshold, UINT *old_threshold) @@ -173,21 +173,21 @@ UINT status; /* Yes, preemption-threshold is being disabled. */ /* Determine if this thread was scheduled with preemption-threshold in force. */ - if (_tx_thread_preemption_threshold_list[thread_ptr -> tx_thread_user_priority] == thread_ptr) + if (_tx_thread_preemption_threshold_list[thread_ptr -> tx_thread_priority] == thread_ptr) { /* Clear the entry in the preempted list. */ - _tx_thread_preemption_threshold_list[thread_ptr -> tx_thread_user_priority] = TX_NULL; + _tx_thread_preemption_threshold_list[thread_ptr -> tx_thread_priority] = TX_NULL; #if TX_MAX_PRIORITIES > 32 /* Calculate the index into the bit map array. */ - map_index = (thread_ptr -> tx_thread_user_priority)/((UINT) 32); + map_index = (thread_ptr -> tx_thread_priority)/((UINT) 32); #endif /* Yes, this thread is at the front of the list. Make sure the preempted bit is cleared for this thread. */ - TX_MOD32_BIT_SET(thread_ptr -> tx_thread_user_priority, priority_bit) + TX_MOD32_BIT_SET(thread_ptr -> tx_thread_priority, priority_bit) _tx_thread_preempted_maps[MAP_INDEX] = _tx_thread_preempted_maps[MAP_INDEX] & (~(priority_bit)); #if TX_MAX_PRIORITIES > 32 @@ -197,7 +197,7 @@ UINT status; { /* No, clear the active bit to signify this preempt map has nothing set. */ - TX_DIV32_BIT_SET(thread_ptr -> tx_thread_user_priority, priority_bit) + TX_DIV32_BIT_SET(thread_ptr -> tx_thread_priority, priority_bit) _tx_thread_preempted_map_active = _tx_thread_preempted_map_active & (~(priority_bit)); } #endif diff --git a/common_smp/src/tx_thread_priority_change.c b/common_smp/src/tx_thread_priority_change.c index 56d4cdf5..69e907d0 100644 --- a/common_smp/src/tx_thread_priority_change.c +++ b/common_smp/src/tx_thread_priority_change.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_priority_change PORTABLE SMP */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -79,7 +79,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_priority_change(TX_THREAD *thread_ptr, UINT new_priority, UINT *old_priority) @@ -270,8 +270,8 @@ UINT status; /* Increment the preempt disable flag. */ _tx_thread_preempt_disable++; - /* Set the state to suspended. */ - thread_ptr -> tx_thread_state = TX_SUSPENDED; + /* Set the state to priority change. */ + thread_ptr -> tx_thread_state = TX_PRIORITY_CHANGE; /* Call actual non-interruptable thread suspension routine. */ _tx_thread_system_ni_suspend(thread_ptr, ((ULONG) 0)); @@ -310,8 +310,8 @@ UINT status; /* Increment the preempt disable flag. */ _tx_thread_preempt_disable = _tx_thread_preempt_disable + ((UINT) 3); - /* Set the state to suspended. */ - thread_ptr -> tx_thread_state = TX_SUSPENDED; + /* Set the state to priority change. */ + thread_ptr -> tx_thread_state = TX_PRIORITY_CHANGE; /* Set the suspending flag. */ thread_ptr -> tx_thread_suspending = TX_TRUE; @@ -376,19 +376,24 @@ UINT status; if (thread_ptr == execute_ptr) { -#ifndef TX_DISABLE_PREEMPTION_THRESHOLD - /* Determine if preemption-threshold is in force at the new priority level. */ - if (_tx_thread_preemption_threshold_list[thread_ptr -> tx_thread_priority] == TX_NULL) + /* Make sure the thread is still ready. */ + if (thread_ptr -> tx_thread_state == TX_READY) { - - /* Ensure that this thread is placed at the front of the priority list. */ - _tx_thread_priority_list[thread_ptr -> tx_thread_priority] = thread_ptr; - } + +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD + /* Determine if preemption-threshold is in force at the new priority level. */ + if (_tx_thread_preemption_threshold_list[thread_ptr -> tx_thread_priority] == TX_NULL) + { + + /* Ensure that this thread is placed at the front of the priority list. */ + _tx_thread_priority_list[thread_ptr -> tx_thread_priority] = thread_ptr; + } #else - /* Ensure that this thread is placed at the front of the priority list. */ - _tx_thread_priority_list[thread_ptr -> tx_thread_priority] = thread_ptr; + /* Ensure that this thread is placed at the front of the priority list. */ + _tx_thread_priority_list[thread_ptr -> tx_thread_priority] = thread_ptr; #endif + } } /* Pickup the core index. */ diff --git a/common_smp/src/tx_thread_relinquish.c b/common_smp/src/tx_thread_relinquish.c index 20a5a165..1cdaf846 100644 --- a/common_smp/src/tx_thread_relinquish.c +++ b/common_smp/src/tx_thread_relinquish.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_relinquish PORTABLE SMP */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_relinquish(VOID) @@ -197,7 +197,7 @@ UINT finished; this thread to the end of the priority list. */ /* Set the rebalance flag to true. */ - rebalance = TX_FALSE; + rebalance = TX_TRUE; } /* Determine if preemption-threshold is in force. */ diff --git a/common_smp/src/tx_thread_reset.c b/common_smp/src/tx_thread_reset.c index 8c6c0794..f80a2463 100644 --- a/common_smp/src/tx_thread_reset.c +++ b/common_smp/src/tx_thread_reset.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_reset PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,7 +67,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_reset(TX_THREAD *thread_ptr) diff --git a/common_smp/src/tx_thread_resume.c b/common_smp/src/tx_thread_resume.c index 993dbe84..123a884e 100644 --- a/common_smp/src/tx_thread_resume.c +++ b/common_smp/src/tx_thread_resume.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_resume PORTABLE SMP */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,7 +69,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_resume(TX_THREAD *thread_ptr) diff --git a/common_smp/src/tx_thread_shell_entry.c b/common_smp/src/tx_thread_shell_entry.c index ca4647ad..bf4f2f5c 100644 --- a/common_smp/src/tx_thread_shell_entry.c +++ b/common_smp/src/tx_thread_shell_entry.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_shell_entry PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_shell_entry(VOID) diff --git a/common_smp/src/tx_thread_sleep.c b/common_smp/src/tx_thread_sleep.c index 833f83ec..6b0eb434 100644 --- a/common_smp/src/tx_thread_sleep.c +++ b/common_smp/src/tx_thread_sleep.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_sleep PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -66,7 +66,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_sleep(ULONG timer_ticks) diff --git a/common_smp/src/tx_thread_smp_core_exclude.c b/common_smp/src/tx_thread_smp_core_exclude.c index 61e843e5..cc973565 100644 --- a/common_smp/src/tx_thread_smp_core_exclude.c +++ b/common_smp/src/tx_thread_smp_core_exclude.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_core_exclude PORTABLE SMP */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_smp_core_exclude(TX_THREAD *thread_ptr, ULONG exclusion_map) diff --git a/common_smp/src/tx_thread_smp_core_exclude_get.c b/common_smp/src/tx_thread_smp_core_exclude_get.c index 2ffce8b3..37e6c82a 100644 --- a/common_smp/src/tx_thread_smp_core_exclude_get.c +++ b/common_smp/src/tx_thread_smp_core_exclude_get.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_core_exclude_get PROTABLE SMP */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_smp_core_exclude_get(TX_THREAD *thread_ptr, ULONG *exclusion_map_ptr) diff --git a/common_smp/src/tx_thread_smp_current_state_set.c b/common_smp/src/tx_thread_smp_current_state_set.c index e1c0236d..5d4df849 100644 --- a/common_smp/src/tx_thread_smp_current_state_set.c +++ b/common_smp/src/tx_thread_smp_current_state_set.c @@ -38,7 +38,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_current_state_set PORTABLE SMP */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,7 +67,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ void _tx_thread_smp_current_state_set(ULONG new_state) diff --git a/common_smp/src/tx_thread_smp_debug_entry_insert.c b/common_smp/src/tx_thread_smp_debug_entry_insert.c index 4472dba5..11213833 100644 --- a/common_smp/src/tx_thread_smp_debug_entry_insert.c +++ b/common_smp/src/tx_thread_smp_debug_entry_insert.c @@ -90,7 +90,7 @@ ULONG _tx_thread_smp_debug_info_current_index; /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_debug_entry_insert PORTABLE SMP */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -123,7 +123,7 @@ ULONG _tx_thread_smp_debug_info_current_index; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ void _tx_thread_smp_debug_entry_insert(ULONG id, ULONG suspend, VOID *thread_void_ptr) diff --git a/common_smp/src/tx_thread_smp_high_level_initialize.c b/common_smp/src/tx_thread_smp_high_level_initialize.c index dd8d6547..4dd63dce 100644 --- a/common_smp/src/tx_thread_smp_high_level_initialize.c +++ b/common_smp/src/tx_thread_smp_high_level_initialize.c @@ -38,7 +38,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_high_level_initialize PORTABLE SMP */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ void _tx_thread_smp_high_level_initialize(void) diff --git a/common_smp/src/tx_thread_smp_rebalance_execute_list.c b/common_smp/src/tx_thread_smp_rebalance_execute_list.c index 04be5d8d..e5518eb5 100644 --- a/common_smp/src/tx_thread_smp_rebalance_execute_list.c +++ b/common_smp/src/tx_thread_smp_rebalance_execute_list.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_rebalance_execute_list PORTABLE SMP */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -87,7 +87,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ void _tx_thread_smp_rebalance_execute_list(UINT core_index) diff --git a/common_smp/src/tx_thread_stack_analyze.c b/common_smp/src/tx_thread_stack_analyze.c index 2cc67691..70fd4838 100644 --- a/common_smp/src/tx_thread_stack_analyze.c +++ b/common_smp/src/tx_thread_stack_analyze.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_analyze PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -65,7 +65,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_stack_analyze(TX_THREAD *thread_ptr) diff --git a/common_smp/src/tx_thread_stack_error_handler.c b/common_smp/src/tx_thread_stack_error_handler.c index bc1465b2..219df6de 100644 --- a/common_smp/src/tx_thread_stack_error_handler.c +++ b/common_smp/src/tx_thread_stack_error_handler.c @@ -26,6 +26,7 @@ /* Include necessary system files. */ #include "tx_api.h" +#ifdef TX_MISRA_ENABLE #include "tx_thread.h" @@ -34,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_error_handler PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -64,7 +65,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) @@ -102,4 +103,5 @@ TX_INTERRUPT_SAVE_AREA } #endif } +#endif /* TX_MISRA_ENABLE */ diff --git a/common_smp/src/tx_thread_stack_error_notify.c b/common_smp/src/tx_thread_stack_error_notify.c index 72cb2c09..957bff06 100644 --- a/common_smp/src/tx_thread_stack_error_notify.c +++ b/common_smp/src/tx_thread_stack_error_notify.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_error_notify PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr)) diff --git a/common_smp/src/tx_thread_suspend.c b/common_smp/src/tx_thread_suspend.c index fd12d755..5aab3796 100644 --- a/common_smp/src/tx_thread_suspend.c +++ b/common_smp/src/tx_thread_suspend.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_suspend PORTABLE SMP */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_suspend(TX_THREAD *thread_ptr) diff --git a/common_smp/src/tx_thread_system_preempt_check.c b/common_smp/src/tx_thread_system_preempt_check.c index 24e18274..d69ddbc0 100644 --- a/common_smp/src/tx_thread_system_preempt_check.c +++ b/common_smp/src/tx_thread_system_preempt_check.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_preempt_check PORTABLE SMP */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -66,7 +66,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_system_preempt_check(VOID) diff --git a/common_smp/src/tx_thread_system_resume.c b/common_smp/src/tx_thread_system_resume.c index 70700c77..fea06599 100644 --- a/common_smp/src/tx_thread_system_resume.c +++ b/common_smp/src/tx_thread_system_resume.c @@ -38,7 +38,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_resume PORTABLE SMP */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -95,7 +95,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_system_resume(TX_THREAD *thread_ptr) diff --git a/common_smp/src/tx_thread_system_suspend.c b/common_smp/src/tx_thread_system_suspend.c index bed18d4e..5707ecca 100644 --- a/common_smp/src/tx_thread_system_suspend.c +++ b/common_smp/src/tx_thread_system_suspend.c @@ -38,7 +38,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_suspend PORTABLE SMP */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -87,7 +87,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_system_suspend(TX_THREAD *thread_ptr) @@ -514,38 +514,35 @@ UINT processing_complete; /* Check to see if the thread is in the execute list. */ i = thread_ptr -> tx_thread_smp_core_mapped; - if (_tx_thread_execute_ptr[i] == thread_ptr) - { - - /* Clear the entry in the thread execution list. */ - _tx_thread_execute_ptr[i] = TX_NULL; + + /* Clear the entry in the thread execution list. */ + _tx_thread_execute_ptr[i] = TX_NULL; #ifdef TX_THREAD_SMP_INTER_CORE_INTERRUPT - /* Determine if we need to preempt the core. */ - if (i != core_index) - { - - if (_tx_thread_system_state[i] < TX_INITIALIZE_IN_PROGRESS) - { + /* Determine if we need to preempt the core. */ + if (i != core_index) + { - /* Preempt the mapped thread. */ - _tx_thread_smp_core_preempt(i); - } + if (_tx_thread_system_state[i] < TX_INITIALIZE_IN_PROGRESS) + { + + /* Preempt the mapped thread. */ + _tx_thread_smp_core_preempt(i); } + } #endif #ifdef TX_THREAD_SMP_WAKEUP_LOGIC - /* Does this need to be waked up? */ - if ((i != core_index) && (_tx_thread_execute_ptr[i] != TX_NULL)) - { + /* Does this need to be waked up? */ + if ((i != core_index) && (_tx_thread_execute_ptr[i] != TX_NULL)) + { - /* Wakeup based on application's macro. */ - TX_THREAD_SMP_WAKEUP(i); - } -#endif + /* Wakeup based on application's macro. */ + TX_THREAD_SMP_WAKEUP(i); } +#endif #ifdef TX_THREAD_SMP_DEBUG_ENABLE @@ -892,32 +889,6 @@ UINT processing_complete; if (_tx_thread_current_ptr[core_index] != _tx_thread_execute_ptr[core_index]) { -#ifdef TX_THREAD_SMP_WAKEUP_LOGIC - - /* Loop to wakeup any cores that have a thread ready to schedule. */ - i = ((UINT) 0); -#ifndef TX_THREAD_SMP_DYNAMIC_CORE_MAX - - while (i < ((UINT) TX_THREAD_SMP_MAX_CORES)) -#else - - while (i < _tx_thread_smp_max_cores) -#endif - { - - /* Is there a thread for this core? */ - if (_tx_thread_execute_ptr[i] != NULL) - { - - /* Yes, wake it up! */ - TX_THREAD_SMP_WAKEUP(i); - } - - /* Move to next entry. */ - i++; - } -#endif - #ifdef TX_ENABLE_STACK_CHECKING /* Pickup the next execute pointer. */ diff --git a/common_smp/src/tx_thread_terminate.c b/common_smp/src/tx_thread_terminate.c index 54fc2076..9badb490 100644 --- a/common_smp/src/tx_thread_terminate.c +++ b/common_smp/src/tx_thread_terminate.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_terminate PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_terminate(TX_THREAD *thread_ptr) diff --git a/common_smp/src/tx_thread_time_slice.c b/common_smp/src/tx_thread_time_slice.c index 1c2796b9..fae9102a 100644 --- a/common_smp/src/tx_thread_time_slice.c +++ b/common_smp/src/tx_thread_time_slice.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_time_slice PORTABLE SMP */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,7 +69,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_time_slice(VOID) diff --git a/common_smp/src/tx_thread_time_slice_change.c b/common_smp/src/tx_thread_time_slice_change.c index 9a7813c0..2f7cd59a 100644 --- a/common_smp/src/tx_thread_time_slice_change.c +++ b/common_smp/src/tx_thread_time_slice_change.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_time_slice_change PORTABLE SMP */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_time_slice_change(TX_THREAD *thread_ptr, ULONG new_time_slice, ULONG *old_time_slice) diff --git a/common_smp/src/tx_thread_timeout.c b/common_smp/src/tx_thread_timeout.c index e96989e5..3e1ce704 100644 --- a/common_smp/src/tx_thread_timeout.c +++ b/common_smp/src/tx_thread_timeout.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_timeout PORTABLE SMP */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_timeout(ULONG timeout_input) diff --git a/common_smp/src/tx_thread_wait_abort.c b/common_smp/src/tx_thread_wait_abort.c index d0513175..e16b51c8 100644 --- a/common_smp/src/tx_thread_wait_abort.c +++ b/common_smp/src/tx_thread_wait_abort.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_wait_abort PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_wait_abort(TX_THREAD *thread_ptr) diff --git a/common_smp/src/tx_time_get.c b/common_smp/src/tx_time_get.c index 72697778..695b502b 100644 --- a/common_smp/src/tx_time_get.c +++ b/common_smp/src/tx_time_get.c @@ -26,6 +26,7 @@ /* Include necessary system files. */ #include "tx_api.h" +#ifdef TX_MISRA_ENABLE #include "tx_trace.h" #include "tx_timer.h" @@ -35,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_time_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -65,7 +66,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _tx_time_get(VOID) @@ -97,4 +98,5 @@ ULONG temp_time; /* Return the time. */ return(temp_time); } +#endif /* TX_MISRA_ENABLE */ diff --git a/common_smp/src/tx_time_set.c b/common_smp/src/tx_time_set.c index 053a540a..8dc392ed 100644 --- a/common_smp/src/tx_time_set.c +++ b/common_smp/src/tx_time_set.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_time_set PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -65,7 +65,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_time_set(ULONG new_time) diff --git a/common_smp/src/tx_timer_activate.c b/common_smp/src/tx_timer_activate.c index b529c109..2c97cbbb 100644 --- a/common_smp/src/tx_timer_activate.c +++ b/common_smp/src/tx_timer_activate.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_activate PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -66,7 +66,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_timer_activate(TX_TIMER *timer_ptr) diff --git a/common_smp/src/tx_timer_change.c b/common_smp/src/tx_timer_change.c index b097012e..7ebc1989 100644 --- a/common_smp/src/tx_timer_change.c +++ b/common_smp/src/tx_timer_change.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_change PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,7 +67,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_timer_change(TX_TIMER *timer_ptr, ULONG initial_ticks, ULONG reschedule_ticks) diff --git a/common_smp/src/tx_timer_create.c b/common_smp/src/tx_timer_create.c index 97b2b2e5..fb612ebb 100644 --- a/common_smp/src/tx_timer_create.c +++ b/common_smp/src/tx_timer_create.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_create PORTABLE SMP */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_timer_create(TX_TIMER *timer_ptr, CHAR *name_ptr, diff --git a/common_smp/src/tx_timer_deactivate.c b/common_smp/src/tx_timer_deactivate.c index d48798ef..9dd6bb5b 100644 --- a/common_smp/src/tx_timer_deactivate.c +++ b/common_smp/src/tx_timer_deactivate.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_deactivate PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -64,7 +64,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_timer_deactivate(TX_TIMER *timer_ptr) diff --git a/common_smp/src/tx_timer_delete.c b/common_smp/src/tx_timer_delete.c index 49074bc2..c2f11260 100644 --- a/common_smp/src/tx_timer_delete.c +++ b/common_smp/src/tx_timer_delete.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_delete PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -64,7 +64,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_timer_delete(TX_TIMER *timer_ptr) diff --git a/common_smp/src/tx_timer_expiration_process.c b/common_smp/src/tx_timer_expiration_process.c index 998aa5e4..235d82ca 100644 --- a/common_smp/src/tx_timer_expiration_process.c +++ b/common_smp/src/tx_timer_expiration_process.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_expiration_process PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_timer_expiration_process(VOID) diff --git a/common_smp/src/tx_timer_info_get.c b/common_smp/src/tx_timer_info_get.c index 4a6457cb..af849260 100644 --- a/common_smp/src/tx_timer_info_get.c +++ b/common_smp/src/tx_timer_info_get.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_timer_info_get(TX_TIMER *timer_ptr, CHAR **name, UINT *active, ULONG *remaining_ticks, diff --git a/common_smp/src/tx_timer_initialize.c b/common_smp/src/tx_timer_initialize.c index 5872b744..47074d77 100644 --- a/common_smp/src/tx_timer_initialize.c +++ b/common_smp/src/tx_timer_initialize.c @@ -174,7 +174,7 @@ ULONG _tx_timer_time_slice[TX_THREAD_SMP_MAX_CORES]; /* FUNCTION RELEASE */ /* */ /* _tx_timer_initialize PORTABLE SMP */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -204,7 +204,7 @@ ULONG _tx_timer_time_slice[TX_THREAD_SMP_MAX_CORES]; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_timer_initialize(VOID) diff --git a/common_smp/src/tx_timer_performance_info_get.c b/common_smp/src/tx_timer_performance_info_get.c index cd0ac3db..1304ff40 100644 --- a/common_smp/src/tx_timer_performance_info_get.c +++ b/common_smp/src/tx_timer_performance_info_get.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_performance_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -78,7 +78,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_timer_performance_info_get(TX_TIMER *timer_ptr, ULONG *activates, ULONG *reactivates, diff --git a/common_smp/src/tx_timer_performance_system_info_get.c b/common_smp/src/tx_timer_performance_system_info_get.c index 80e23529..49536fcc 100644 --- a/common_smp/src/tx_timer_performance_system_info_get.c +++ b/common_smp/src/tx_timer_performance_system_info_get.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_performance_system_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -75,7 +75,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_timer_performance_system_info_get(ULONG *activates, ULONG *reactivates, diff --git a/common_smp/src/tx_timer_smp_core_exclude.c b/common_smp/src/tx_timer_smp_core_exclude.c index 01e59e2c..88a75231 100644 --- a/common_smp/src/tx_timer_smp_core_exclude.c +++ b/common_smp/src/tx_timer_smp_core_exclude.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_smp_core_exclude PORTABLE SMP */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_timer_smp_core_exclude(TX_TIMER *timer_ptr, ULONG exclusion_map) diff --git a/common_smp/src/tx_timer_smp_core_exclude_get.c b/common_smp/src/tx_timer_smp_core_exclude_get.c index 31d7a288..51d9ae27 100644 --- a/common_smp/src/tx_timer_smp_core_exclude_get.c +++ b/common_smp/src/tx_timer_smp_core_exclude_get.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_smp_core_exclude_get PROTABLE SMP */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_timer_smp_core_exclude_get(TX_TIMER *timer_ptr, ULONG *exclusion_map_ptr) diff --git a/common_smp/src/tx_timer_system_activate.c b/common_smp/src/tx_timer_system_activate.c index 505257db..d54211b4 100644 --- a/common_smp/src/tx_timer_system_activate.c +++ b/common_smp/src/tx_timer_system_activate.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_system_activate PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_timer_system_activate(TX_TIMER_INTERNAL *timer_ptr) diff --git a/common_smp/src/tx_timer_system_deactivate.c b/common_smp/src/tx_timer_system_deactivate.c index 72cf3045..cfc97e7b 100644 --- a/common_smp/src/tx_timer_system_deactivate.c +++ b/common_smp/src/tx_timer_system_deactivate.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_system_deactivate PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -66,7 +66,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_timer_system_deactivate(TX_TIMER_INTERNAL *timer_ptr) diff --git a/common_smp/src/tx_timer_thread_entry.c b/common_smp/src/tx_timer_thread_entry.c index 32c3f300..f2cfa3aa 100644 --- a/common_smp/src/tx_timer_thread_entry.c +++ b/common_smp/src/tx_timer_thread_entry.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_thread_entry PORTABLE SMP */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ #ifndef TX_TIMER_PROCESS_IN_ISR diff --git a/common_smp/src/tx_trace_buffer_full_notify.c b/common_smp/src/tx_trace_buffer_full_notify.c index 90a47e7f..5be36eba 100644 --- a/common_smp/src/tx_trace_buffer_full_notify.c +++ b/common_smp/src/tx_trace_buffer_full_notify.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_trace_buffer_full_notify PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,7 +69,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_trace_buffer_full_notify(VOID (*full_buffer_callback)(VOID *buffer)) diff --git a/common_smp/src/tx_trace_disable.c b/common_smp/src/tx_trace_disable.c index 1b65aa2a..202fadb0 100644 --- a/common_smp/src/tx_trace_disable.c +++ b/common_smp/src/tx_trace_disable.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_trace_disable PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -63,7 +63,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_trace_disable(VOID) diff --git a/common_smp/src/tx_trace_enable.c b/common_smp/src/tx_trace_enable.c index ab90bf56..086a3dea 100644 --- a/common_smp/src/tx_trace_enable.c +++ b/common_smp/src/tx_trace_enable.c @@ -44,7 +44,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_trace_enable PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -78,7 +78,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_trace_enable(VOID *trace_buffer_start, ULONG trace_buffer_size, ULONG registry_entries) diff --git a/common_smp/src/tx_trace_event_filter.c b/common_smp/src/tx_trace_event_filter.c index b4e7f41f..0534d3a5 100644 --- a/common_smp/src/tx_trace_event_filter.c +++ b/common_smp/src/tx_trace_event_filter.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_trace_event_filter PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -66,7 +66,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_trace_event_filter(ULONG event_filter_bits) diff --git a/common_smp/src/tx_trace_event_unfilter.c b/common_smp/src/tx_trace_event_unfilter.c index cb8bc74d..fa01bb1f 100644 --- a/common_smp/src/tx_trace_event_unfilter.c +++ b/common_smp/src/tx_trace_event_unfilter.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_trace_event_unfilter PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -66,7 +66,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_trace_event_unfilter(ULONG event_unfilter_bits) diff --git a/common_smp/src/tx_trace_initialize.c b/common_smp/src/tx_trace_initialize.c index 16458b87..f9b477cb 100644 --- a/common_smp/src/tx_trace_initialize.c +++ b/common_smp/src/tx_trace_initialize.c @@ -100,7 +100,7 @@ ULONG _tx_trace_registry_search_start; /* FUNCTION RELEASE */ /* */ /* _tx_trace_initialize PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -130,7 +130,7 @@ ULONG _tx_trace_registry_search_start; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_trace_initialize(VOID) diff --git a/common_smp/src/tx_trace_interrupt_control.c b/common_smp/src/tx_trace_interrupt_control.c index f07dfa50..d729c829 100644 --- a/common_smp/src/tx_trace_interrupt_control.c +++ b/common_smp/src/tx_trace_interrupt_control.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_trace_interrupt_control PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -65,7 +65,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_trace_interrupt_control(UINT new_posture) diff --git a/common_smp/src/tx_trace_isr_enter_insert.c b/common_smp/src/tx_trace_isr_enter_insert.c index 08d758e5..29042de7 100644 --- a/common_smp/src/tx_trace_isr_enter_insert.c +++ b/common_smp/src/tx_trace_isr_enter_insert.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_trace_isr_enter_insert PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,7 +67,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_trace_isr_enter_insert(ULONG isr_id) diff --git a/common_smp/src/tx_trace_isr_exit_insert.c b/common_smp/src/tx_trace_isr_exit_insert.c index f070491d..5b9bf0f2 100644 --- a/common_smp/src/tx_trace_isr_exit_insert.c +++ b/common_smp/src/tx_trace_isr_exit_insert.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_trace_isr_exit_insert PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,7 +67,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_trace_isr_exit_insert(ULONG isr_id) diff --git a/common_smp/src/tx_trace_object_register.c b/common_smp/src/tx_trace_object_register.c index de201edd..aa297e8b 100644 --- a/common_smp/src/tx_trace_object_register.c +++ b/common_smp/src/tx_trace_object_register.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_trace_object_register PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,7 +69,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_trace_object_register(UCHAR object_type, VOID *object_ptr, CHAR *object_name, ULONG parameter_1, ULONG parameter_2) diff --git a/common_smp/src/tx_trace_object_unregister.c b/common_smp/src/tx_trace_object_unregister.c index e72e919c..0bcf98cf 100644 --- a/common_smp/src/tx_trace_object_unregister.c +++ b/common_smp/src/tx_trace_object_unregister.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_trace_object_unregister PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -64,7 +64,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_trace_object_unregister(VOID *object_ptr) diff --git a/common_smp/src/tx_trace_user_event_insert.c b/common_smp/src/tx_trace_user_event_insert.c index 09573ba9..cac68502 100644 --- a/common_smp/src/tx_trace_user_event_insert.c +++ b/common_smp/src/tx_trace_user_event_insert.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_trace_user_event_insert PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,7 +67,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_trace_user_event_insert(ULONG event_id, ULONG info_field_1, ULONG info_field_2, ULONG info_field_3, ULONG info_field_4) diff --git a/common_smp/src/txe_block_allocate.c b/common_smp/src/txe_block_allocate.c index 995e8028..81e02e28 100644 --- a/common_smp/src/txe_block_allocate.c +++ b/common_smp/src/txe_block_allocate.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_block_allocate PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_block_allocate(TX_BLOCK_POOL *pool_ptr, VOID **block_ptr, ULONG wait_option) diff --git a/common_smp/src/txe_block_pool_create.c b/common_smp/src/txe_block_pool_create.c index 04253534..3f9b8fe9 100644 --- a/common_smp/src/txe_block_pool_create.c +++ b/common_smp/src/txe_block_pool_create.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_block_pool_create PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_block_pool_create(TX_BLOCK_POOL *pool_ptr, CHAR *name_ptr, ULONG block_size, diff --git a/common_smp/src/txe_block_pool_delete.c b/common_smp/src/txe_block_pool_delete.c index 91324624..52316fb1 100644 --- a/common_smp/src/txe_block_pool_delete.c +++ b/common_smp/src/txe_block_pool_delete.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_block_pool_delete PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_block_pool_delete(TX_BLOCK_POOL *pool_ptr) diff --git a/common_smp/src/txe_block_pool_info_get.c b/common_smp/src/txe_block_pool_info_get.c index 3486363d..82659892 100644 --- a/common_smp/src/txe_block_pool_info_get.c +++ b/common_smp/src/txe_block_pool_info_get.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_block_pool_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -73,7 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_block_pool_info_get(TX_BLOCK_POOL *pool_ptr, CHAR **name, ULONG *available_blocks, diff --git a/common_smp/src/txe_block_pool_prioritize.c b/common_smp/src/txe_block_pool_prioritize.c index b5331595..2caed6a3 100644 --- a/common_smp/src/txe_block_pool_prioritize.c +++ b/common_smp/src/txe_block_pool_prioritize.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_block_pool_prioritize PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -64,7 +64,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_block_pool_prioritize(TX_BLOCK_POOL *pool_ptr) diff --git a/common_smp/src/txe_block_release.c b/common_smp/src/txe_block_release.c index 60f2a9b0..614b7eee 100644 --- a/common_smp/src/txe_block_release.c +++ b/common_smp/src/txe_block_release.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_block_release PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -64,7 +64,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_block_release(VOID *block_ptr) diff --git a/common_smp/src/txe_byte_allocate.c b/common_smp/src/txe_byte_allocate.c index a93fac01..3c226c11 100644 --- a/common_smp/src/txe_byte_allocate.c +++ b/common_smp/src/txe_byte_allocate.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_byte_allocate PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -75,7 +75,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_byte_allocate(TX_BYTE_POOL *pool_ptr, VOID **memory_ptr, diff --git a/common_smp/src/txe_byte_pool_create.c b/common_smp/src/txe_byte_pool_create.c index 429d401c..55659b42 100644 --- a/common_smp/src/txe_byte_pool_create.c +++ b/common_smp/src/txe_byte_pool_create.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_byte_pool_create PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -76,7 +76,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_byte_pool_create(TX_BYTE_POOL *pool_ptr, CHAR *name_ptr, VOID *pool_start, ULONG pool_size, UINT pool_control_block_size) diff --git a/common_smp/src/txe_byte_pool_delete.c b/common_smp/src/txe_byte_pool_delete.c index 22d2a347..98793495 100644 --- a/common_smp/src/txe_byte_pool_delete.c +++ b/common_smp/src/txe_byte_pool_delete.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_byte_pool_delete PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_byte_pool_delete(TX_BYTE_POOL *pool_ptr) diff --git a/common_smp/src/txe_byte_pool_info_get.c b/common_smp/src/txe_byte_pool_info_get.c index d7d33391..6596a45c 100644 --- a/common_smp/src/txe_byte_pool_info_get.c +++ b/common_smp/src/txe_byte_pool_info_get.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_byte_pool_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -73,7 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_byte_pool_info_get(TX_BYTE_POOL *pool_ptr, CHAR **name, ULONG *available_bytes, diff --git a/common_smp/src/txe_byte_pool_prioritize.c b/common_smp/src/txe_byte_pool_prioritize.c index 9eec66a0..cf239aae 100644 --- a/common_smp/src/txe_byte_pool_prioritize.c +++ b/common_smp/src/txe_byte_pool_prioritize.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_byte_pool_prioritize PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -64,7 +64,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_byte_pool_prioritize(TX_BYTE_POOL *pool_ptr) diff --git a/common_smp/src/txe_byte_release.c b/common_smp/src/txe_byte_release.c index 3e83a83c..4268c804 100644 --- a/common_smp/src/txe_byte_release.c +++ b/common_smp/src/txe_byte_release.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_byte_release PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_byte_release(VOID *memory_ptr) diff --git a/common_smp/src/txe_event_flags_create.c b/common_smp/src/txe_event_flags_create.c index 4a0805c9..be730563 100644 --- a/common_smp/src/txe_event_flags_create.c +++ b/common_smp/src/txe_event_flags_create.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_event_flags_create PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -73,7 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_event_flags_create(TX_EVENT_FLAGS_GROUP *group_ptr, CHAR *name_ptr, UINT event_control_block_size) diff --git a/common_smp/src/txe_event_flags_delete.c b/common_smp/src/txe_event_flags_delete.c index ac3548e3..159f192e 100644 --- a/common_smp/src/txe_event_flags_delete.c +++ b/common_smp/src/txe_event_flags_delete.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_event_flags_delete PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_event_flags_delete(TX_EVENT_FLAGS_GROUP *group_ptr) diff --git a/common_smp/src/txe_event_flags_get.c b/common_smp/src/txe_event_flags_get.c index 45aa735f..3a1d0164 100644 --- a/common_smp/src/txe_event_flags_get.c +++ b/common_smp/src/txe_event_flags_get.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_event_flags_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -76,7 +76,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_event_flags_get(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG requested_flags, diff --git a/common_smp/src/txe_event_flags_info_get.c b/common_smp/src/txe_event_flags_info_get.c index 111da89e..49080b0f 100644 --- a/common_smp/src/txe_event_flags_info_get.c +++ b/common_smp/src/txe_event_flags_info_get.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_event_flags_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -75,7 +75,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_event_flags_info_get(TX_EVENT_FLAGS_GROUP *group_ptr, CHAR **name, ULONG *current_flags, diff --git a/common_smp/src/txe_event_flags_set.c b/common_smp/src/txe_event_flags_set.c index a4a4b5e9..6d7e6fd7 100644 --- a/common_smp/src/txe_event_flags_set.c +++ b/common_smp/src/txe_event_flags_set.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_event_flags_set PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,7 +69,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_event_flags_set(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG flags_to_set, UINT set_option) diff --git a/common_smp/src/txe_event_flags_set_notify.c b/common_smp/src/txe_event_flags_set_notify.c index 84f7fc3c..8b7a1e10 100644 --- a/common_smp/src/txe_event_flags_set_notify.c +++ b/common_smp/src/txe_event_flags_set_notify.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_event_flags_set_notify PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,7 +67,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_event_flags_set_notify(TX_EVENT_FLAGS_GROUP *group_ptr, VOID (*events_set_notify)(TX_EVENT_FLAGS_GROUP *notify_group_ptr)) diff --git a/common_smp/src/txe_mutex_create.c b/common_smp/src/txe_mutex_create.c index 18f8ca9c..e99713d8 100644 --- a/common_smp/src/txe_mutex_create.c +++ b/common_smp/src/txe_mutex_create.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_mutex_create PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -74,7 +74,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_mutex_create(TX_MUTEX *mutex_ptr, CHAR *name_ptr, UINT inherit, UINT mutex_control_block_size) diff --git a/common_smp/src/txe_mutex_delete.c b/common_smp/src/txe_mutex_delete.c index 83b6df14..64b8a471 100644 --- a/common_smp/src/txe_mutex_delete.c +++ b/common_smp/src/txe_mutex_delete.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_mutex_delete PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_mutex_delete(TX_MUTEX *mutex_ptr) diff --git a/common_smp/src/txe_mutex_get.c b/common_smp/src/txe_mutex_get.c index b4fe3b8b..752da15f 100644 --- a/common_smp/src/txe_mutex_get.c +++ b/common_smp/src/txe_mutex_get.c @@ -39,7 +39,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_mutex_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_mutex_get(TX_MUTEX *mutex_ptr, ULONG wait_option) diff --git a/common_smp/src/txe_mutex_info_get.c b/common_smp/src/txe_mutex_info_get.c index 5b27cafd..b093db78 100644 --- a/common_smp/src/txe_mutex_info_get.c +++ b/common_smp/src/txe_mutex_info_get.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_mutex_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -74,7 +74,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_mutex_info_get(TX_MUTEX *mutex_ptr, CHAR **name, ULONG *count, TX_THREAD **owner, diff --git a/common_smp/src/txe_mutex_prioritize.c b/common_smp/src/txe_mutex_prioritize.c index e7bdc24a..7fa7706e 100644 --- a/common_smp/src/txe_mutex_prioritize.c +++ b/common_smp/src/txe_mutex_prioritize.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_mutex_prioritize PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -64,7 +64,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_mutex_prioritize(TX_MUTEX *mutex_ptr) diff --git a/common_smp/src/txe_mutex_put.c b/common_smp/src/txe_mutex_put.c index 2f4e9712..12266f48 100644 --- a/common_smp/src/txe_mutex_put.c +++ b/common_smp/src/txe_mutex_put.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_mutex_put PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -66,7 +66,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_mutex_put(TX_MUTEX *mutex_ptr) diff --git a/common_smp/src/txe_queue_create.c b/common_smp/src/txe_queue_create.c index 5cd7e0ee..b3b2021f 100644 --- a/common_smp/src/txe_queue_create.c +++ b/common_smp/src/txe_queue_create.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_queue_create PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -75,7 +75,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_queue_create(TX_QUEUE *queue_ptr, CHAR *name_ptr, UINT message_size, diff --git a/common_smp/src/txe_queue_delete.c b/common_smp/src/txe_queue_delete.c index 32b730d5..75ba2ee0 100644 --- a/common_smp/src/txe_queue_delete.c +++ b/common_smp/src/txe_queue_delete.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_queue_delete PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,7 +67,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_queue_delete(TX_QUEUE *queue_ptr) diff --git a/common_smp/src/txe_queue_flush.c b/common_smp/src/txe_queue_flush.c index ad7be5f1..e0eaeee7 100644 --- a/common_smp/src/txe_queue_flush.c +++ b/common_smp/src/txe_queue_flush.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_queue_flush PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -65,7 +65,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_queue_flush(TX_QUEUE *queue_ptr) diff --git a/common_smp/src/txe_queue_front_send.c b/common_smp/src/txe_queue_front_send.c index e9b6d4a4..2a4332d2 100644 --- a/common_smp/src/txe_queue_front_send.c +++ b/common_smp/src/txe_queue_front_send.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_queue_front_send PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_queue_front_send(TX_QUEUE *queue_ptr, VOID *source_ptr, ULONG wait_option) diff --git a/common_smp/src/txe_queue_info_get.c b/common_smp/src/txe_queue_info_get.c index 2616749c..286cbd75 100644 --- a/common_smp/src/txe_queue_info_get.c +++ b/common_smp/src/txe_queue_info_get.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_queue_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -73,7 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_queue_info_get(TX_QUEUE *queue_ptr, CHAR **name, ULONG *enqueued, ULONG *available_storage, diff --git a/common_smp/src/txe_queue_prioritize.c b/common_smp/src/txe_queue_prioritize.c index 82e83b4c..947ac49e 100644 --- a/common_smp/src/txe_queue_prioritize.c +++ b/common_smp/src/txe_queue_prioritize.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_queue_prioritize PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -63,7 +63,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_queue_prioritize(TX_QUEUE *queue_ptr) diff --git a/common_smp/src/txe_queue_receive.c b/common_smp/src/txe_queue_receive.c index 80f0f36d..ecd02878 100644 --- a/common_smp/src/txe_queue_receive.c +++ b/common_smp/src/txe_queue_receive.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_queue_receive PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_queue_receive(TX_QUEUE *queue_ptr, VOID *destination_ptr, ULONG wait_option) diff --git a/common_smp/src/txe_queue_send.c b/common_smp/src/txe_queue_send.c index dc3f258a..5f07af11 100644 --- a/common_smp/src/txe_queue_send.c +++ b/common_smp/src/txe_queue_send.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_queue_send PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_queue_send(TX_QUEUE *queue_ptr, VOID *source_ptr, ULONG wait_option) diff --git a/common_smp/src/txe_queue_send_notify.c b/common_smp/src/txe_queue_send_notify.c index d07dcc9c..0716470a 100644 --- a/common_smp/src/txe_queue_send_notify.c +++ b/common_smp/src/txe_queue_send_notify.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_queue_send_notify PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -66,7 +66,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_queue_send_notify(TX_QUEUE *queue_ptr, VOID (*queue_send_notify)(TX_QUEUE *notify_queue_ptr)) diff --git a/common_smp/src/txe_semaphore_ceiling_put.c b/common_smp/src/txe_semaphore_ceiling_put.c index 1a6d7f74..86f052f0 100644 --- a/common_smp/src/txe_semaphore_ceiling_put.c +++ b/common_smp/src/txe_semaphore_ceiling_put.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_semaphore_ceiling_put PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_semaphore_ceiling_put(TX_SEMAPHORE *semaphore_ptr, ULONG ceiling) diff --git a/common_smp/src/txe_semaphore_create.c b/common_smp/src/txe_semaphore_create.c index 92a18824..d8d306bc 100644 --- a/common_smp/src/txe_semaphore_create.c +++ b/common_smp/src/txe_semaphore_create.c @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_semaphore_create PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -73,7 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_semaphore_create(TX_SEMAPHORE *semaphore_ptr, CHAR *name_ptr, ULONG initial_count, UINT semaphore_control_block_size) diff --git a/common_smp/src/txe_semaphore_delete.c b/common_smp/src/txe_semaphore_delete.c index ea08847b..7436c8e1 100644 --- a/common_smp/src/txe_semaphore_delete.c +++ b/common_smp/src/txe_semaphore_delete.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_semaphore_delete PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_semaphore_delete(TX_SEMAPHORE *semaphore_ptr) diff --git a/common_smp/src/txe_semaphore_get.c b/common_smp/src/txe_semaphore_get.c index 56e666db..03dd492f 100644 --- a/common_smp/src/txe_semaphore_get.c +++ b/common_smp/src/txe_semaphore_get.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_semaphore_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_semaphore_get(TX_SEMAPHORE *semaphore_ptr, ULONG wait_option) diff --git a/common_smp/src/txe_semaphore_info_get.c b/common_smp/src/txe_semaphore_info_get.c index b0d466df..c3fac5fd 100644 --- a/common_smp/src/txe_semaphore_info_get.c +++ b/common_smp/src/txe_semaphore_info_get.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_semaphore_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -73,7 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_semaphore_info_get(TX_SEMAPHORE *semaphore_ptr, CHAR **name, ULONG *current_value, diff --git a/common_smp/src/txe_semaphore_prioritize.c b/common_smp/src/txe_semaphore_prioritize.c index f7cea5c2..d8fea7e4 100644 --- a/common_smp/src/txe_semaphore_prioritize.c +++ b/common_smp/src/txe_semaphore_prioritize.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_semaphore_prioritize PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -64,7 +64,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_semaphore_prioritize(TX_SEMAPHORE *semaphore_ptr) diff --git a/common_smp/src/txe_semaphore_put.c b/common_smp/src/txe_semaphore_put.c index 6c8ab95b..04679cc0 100644 --- a/common_smp/src/txe_semaphore_put.c +++ b/common_smp/src/txe_semaphore_put.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_semaphore_put PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -64,7 +64,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_semaphore_put(TX_SEMAPHORE *semaphore_ptr) diff --git a/common_smp/src/txe_semaphore_put_notify.c b/common_smp/src/txe_semaphore_put_notify.c index 133c1550..b8198270 100644 --- a/common_smp/src/txe_semaphore_put_notify.c +++ b/common_smp/src/txe_semaphore_put_notify.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_semaphore_put_notify PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,7 +67,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_semaphore_put_notify(TX_SEMAPHORE *semaphore_ptr, VOID (*semaphore_put_notify)(TX_SEMAPHORE *notify_semaphore_ptr)) diff --git a/common_smp/src/txe_thread_create.c b/common_smp/src/txe_thread_create.c index 57b57013..40e1b0dd 100644 --- a/common_smp/src/txe_thread_create.c +++ b/common_smp/src/txe_thread_create.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_create PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_create(TX_THREAD *thread_ptr, CHAR *name_ptr, diff --git a/common_smp/src/txe_thread_delete.c b/common_smp/src/txe_thread_delete.c index 6431d20e..4c7a1b04 100644 --- a/common_smp/src/txe_thread_delete.c +++ b/common_smp/src/txe_thread_delete.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_delete PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -65,7 +65,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_delete(TX_THREAD *thread_ptr) diff --git a/common_smp/src/txe_thread_entry_exit_notify.c b/common_smp/src/txe_thread_entry_exit_notify.c index efe635be..061f77c3 100644 --- a/common_smp/src/txe_thread_entry_exit_notify.c +++ b/common_smp/src/txe_thread_entry_exit_notify.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_entry_exit_notify PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,7 +67,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_entry_exit_notify(TX_THREAD *thread_ptr, VOID (*thread_entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT type)) diff --git a/common_smp/src/txe_thread_info_get.c b/common_smp/src/txe_thread_info_get.c index 7652c811..ba8f5acf 100644 --- a/common_smp/src/txe_thread_info_get.c +++ b/common_smp/src/txe_thread_info_get.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_info_get(TX_THREAD *thread_ptr, CHAR **name, UINT *state, ULONG *run_count, diff --git a/common_smp/src/txe_thread_preemption_change.c b/common_smp/src/txe_thread_preemption_change.c index 1b33e30d..a10244d3 100644 --- a/common_smp/src/txe_thread_preemption_change.c +++ b/common_smp/src/txe_thread_preemption_change.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_preemption_change PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,7 +69,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_preemption_change(TX_THREAD *thread_ptr, UINT new_threshold, UINT *old_threshold) diff --git a/common_smp/src/txe_thread_priority_change.c b/common_smp/src/txe_thread_priority_change.c index 63f27fa2..6b7445cf 100644 --- a/common_smp/src/txe_thread_priority_change.c +++ b/common_smp/src/txe_thread_priority_change.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_priority_change PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_priority_change(TX_THREAD *thread_ptr, UINT new_priority, UINT *old_priority) diff --git a/common_smp/src/txe_thread_relinquish.c b/common_smp/src/txe_thread_relinquish.c index 696c19e0..378f122c 100644 --- a/common_smp/src/txe_thread_relinquish.c +++ b/common_smp/src/txe_thread_relinquish.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_relinquish PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -64,7 +64,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txe_thread_relinquish(VOID) diff --git a/common_smp/src/txe_thread_reset.c b/common_smp/src/txe_thread_reset.c index 9ff00215..544e45f8 100644 --- a/common_smp/src/txe_thread_reset.c +++ b/common_smp/src/txe_thread_reset.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_reset PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -66,7 +66,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_reset(TX_THREAD *thread_ptr) diff --git a/common_smp/src/txe_thread_resume.c b/common_smp/src/txe_thread_resume.c index 1fd65890..2028e43a 100644 --- a/common_smp/src/txe_thread_resume.c +++ b/common_smp/src/txe_thread_resume.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_resume PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -64,7 +64,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_resume(TX_THREAD *thread_ptr) diff --git a/common_smp/src/txe_thread_suspend.c b/common_smp/src/txe_thread_suspend.c index d8899c37..a673d891 100644 --- a/common_smp/src/txe_thread_suspend.c +++ b/common_smp/src/txe_thread_suspend.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_suspend PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -66,7 +66,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_suspend(TX_THREAD *thread_ptr) diff --git a/common_smp/src/txe_thread_terminate.c b/common_smp/src/txe_thread_terminate.c index e20b0dd5..f5c08ce6 100644 --- a/common_smp/src/txe_thread_terminate.c +++ b/common_smp/src/txe_thread_terminate.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_terminate PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,7 +67,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_terminate(TX_THREAD *thread_ptr) diff --git a/common_smp/src/txe_thread_time_slice_change.c b/common_smp/src/txe_thread_time_slice_change.c index e4d1d69c..f124b3f9 100644 --- a/common_smp/src/txe_thread_time_slice_change.c +++ b/common_smp/src/txe_thread_time_slice_change.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_time_slice_change PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,7 +69,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_time_slice_change(TX_THREAD *thread_ptr, ULONG new_time_slice, ULONG *old_time_slice) diff --git a/common_smp/src/txe_thread_wait_abort.c b/common_smp/src/txe_thread_wait_abort.c index e614b45a..14dc5fe3 100644 --- a/common_smp/src/txe_thread_wait_abort.c +++ b/common_smp/src/txe_thread_wait_abort.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_wait_abort PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -64,7 +64,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_wait_abort(TX_THREAD *thread_ptr) diff --git a/common_smp/src/txe_timer_activate.c b/common_smp/src/txe_timer_activate.c index a0af5532..d3186f3d 100644 --- a/common_smp/src/txe_timer_activate.c +++ b/common_smp/src/txe_timer_activate.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_timer_activate PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -66,7 +66,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_timer_activate(TX_TIMER *timer_ptr) diff --git a/common_smp/src/txe_timer_change.c b/common_smp/src/txe_timer_change.c index a71e509f..d3a1eb17 100644 --- a/common_smp/src/txe_timer_change.c +++ b/common_smp/src/txe_timer_change.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_timer_change PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_timer_change(TX_TIMER *timer_ptr, ULONG initial_ticks, ULONG reschedule_ticks) diff --git a/common_smp/src/txe_timer_create.c b/common_smp/src/txe_timer_create.c index 5fe04bc2..08352974 100644 --- a/common_smp/src/txe_timer_create.c +++ b/common_smp/src/txe_timer_create.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_timer_create PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_timer_create(TX_TIMER *timer_ptr, CHAR *name_ptr, diff --git a/common_smp/src/txe_timer_deactivate.c b/common_smp/src/txe_timer_deactivate.c index 9becb629..58c66d81 100644 --- a/common_smp/src/txe_timer_deactivate.c +++ b/common_smp/src/txe_timer_deactivate.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_timer_deactivate PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -65,7 +65,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_timer_deactivate(TX_TIMER *timer_ptr) diff --git a/common_smp/src/txe_timer_delete.c b/common_smp/src/txe_timer_delete.c index cfb0fd94..aee1b34c 100644 --- a/common_smp/src/txe_timer_delete.c +++ b/common_smp/src/txe_timer_delete.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_timer_delete PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,7 +67,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_timer_delete(TX_TIMER *timer_ptr) diff --git a/common_smp/src/txe_timer_info_get.c b/common_smp/src/txe_timer_info_get.c index 7dc07cdc..a53a7885 100644 --- a/common_smp/src/txe_timer_info_get.c +++ b/common_smp/src/txe_timer_info_get.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_timer_info_get PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_timer_info_get(TX_TIMER *timer_ptr, CHAR **name, UINT *active, ULONG *remaining_ticks, diff --git a/ports/arc_em/metaware/example_build/sample_threadx/tx_initialize_low_level.s b/ports/arc_em/metaware/example_build/sample_threadx/tx_initialize_low_level.s index 8b75bf9f..bcd91dff 100644 --- a/ports/arc_em/metaware/example_build/sample_threadx/tx_initialize_low_level.s +++ b/ports/arc_em/metaware/example_build/sample_threadx/tx_initialize_low_level.s @@ -61,7 +61,7 @@ _tx_system_stack_base_address: ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level ARCv2_EM/MetaWare */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -94,7 +94,7 @@ _tx_system_stack_base_address: ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports/arc_em/metaware/inc/tx_port.h b/ports/arc_em/metaware/inc/tx_port.h index 0a197ab6..2fee779d 100644 --- a/ports/arc_em/metaware/inc/tx_port.h +++ b/ports/arc_em/metaware/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h ARCv2_EM/MetaWare */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -308,7 +308,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARCv2_EM/MetaWare Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARCv2_EM/MetaWare Version 6.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/arc_em/metaware/readme_threadx.txt b/ports/arc_em/metaware/readme_threadx.txt index dcba11a8..d7791171 100644 --- a/ports/arc_em/metaware/readme_threadx.txt +++ b/ports/arc_em/metaware/readme_threadx.txt @@ -209,7 +209,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX 6.0.1 for ARCv2 EM using MetaWare tools. +09-30-2020 Initial ThreadX 6.1 for ARCv2 EM using MetaWare tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/arc_em/metaware/src/tx_initialize_low_level.s b/ports/arc_em/metaware/src/tx_initialize_low_level.s index 8b75bf9f..bcd91dff 100644 --- a/ports/arc_em/metaware/src/tx_initialize_low_level.s +++ b/ports/arc_em/metaware/src/tx_initialize_low_level.s @@ -61,7 +61,7 @@ _tx_system_stack_base_address: ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level ARCv2_EM/MetaWare */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -94,7 +94,7 @@ _tx_system_stack_base_address: ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports/arc_em/metaware/src/tx_thread_context_restore.s b/ports/arc_em/metaware/src/tx_thread_context_restore.s index 8bc31394..882b306c 100644 --- a/ports/arc_em/metaware/src/tx_thread_context_restore.s +++ b/ports/arc_em/metaware/src/tx_thread_context_restore.s @@ -40,7 +40,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore ARCv2_EM/MetaWare */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports/arc_em/metaware/src/tx_thread_context_save.s b/ports/arc_em/metaware/src/tx_thread_context_save.s index e60bc856..e67cdd80 100644 --- a/ports/arc_em/metaware/src/tx_thread_context_save.s +++ b/ports/arc_em/metaware/src/tx_thread_context_save.s @@ -40,7 +40,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save ARCv2_EM/MetaWare */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) diff --git a/ports/arc_em/metaware/src/tx_thread_interrupt_control.s b/ports/arc_em/metaware/src/tx_thread_interrupt_control.s index 5bdf3ccb..e032d6d8 100644 --- a/ports/arc_em/metaware/src/tx_thread_interrupt_control.s +++ b/ports/arc_em/metaware/src/tx_thread_interrupt_control.s @@ -34,7 +34,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control ARCv2_EM/MetaWare */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -64,7 +64,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/arc_em/metaware/src/tx_thread_schedule.s b/ports/arc_em/metaware/src/tx_thread_schedule.s index 2a310a16..bb50e563 100644 --- a/ports/arc_em/metaware/src/tx_thread_schedule.s +++ b/ports/arc_em/metaware/src/tx_thread_schedule.s @@ -41,7 +41,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule ARCv2_EM/MetaWare */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -74,7 +74,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) diff --git a/ports/arc_em/metaware/src/tx_thread_stack_build.s b/ports/arc_em/metaware/src/tx_thread_stack_build.s index ecda6a4d..b576b0ff 100644 --- a/ports/arc_em/metaware/src/tx_thread_stack_build.s +++ b/ports/arc_em/metaware/src/tx_thread_stack_build.s @@ -39,7 +39,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build ARCv2_EM/MetaWare */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/arc_em/metaware/src/tx_thread_system_return.s b/ports/arc_em/metaware/src/tx_thread_system_return.s index 61120d49..fa061e1c 100644 --- a/ports/arc_em/metaware/src/tx_thread_system_return.s +++ b/ports/arc_em/metaware/src/tx_thread_system_return.s @@ -38,7 +38,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return ARCv2_EM/MetaWare */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -70,7 +70,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) diff --git a/ports/arc_em/metaware/src/tx_timer_interrupt.s b/ports/arc_em/metaware/src/tx_timer_interrupt.s index 4c5e241c..67b06941 100644 --- a/ports/arc_em/metaware/src/tx_timer_interrupt.s +++ b/ports/arc_em/metaware/src/tx_timer_interrupt.s @@ -35,7 +35,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt ARCv2_EM/MetaWare */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) diff --git a/ports/arc_hs/metaware/example_build/sample_threadx/tx_initialize_low_level.s b/ports/arc_hs/metaware/example_build/sample_threadx/tx_initialize_low_level.s index da17b687..6b1a76b0 100644 --- a/ports/arc_hs/metaware/example_build/sample_threadx/tx_initialize_low_level.s +++ b/ports/arc_hs/metaware/example_build/sample_threadx/tx_initialize_low_level.s @@ -41,7 +41,7 @@ _tx_first_free_address: ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level ARC_HS/MetaWare */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -74,7 +74,7 @@ _tx_first_free_address: ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports/arc_hs/metaware/inc/tx_port.h b/ports/arc_hs/metaware/inc/tx_port.h index b531615c..db08784e 100644 --- a/ports/arc_hs/metaware/inc/tx_port.h +++ b/ports/arc_hs/metaware/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h ARC_HS/MetaWare */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -322,7 +322,7 @@ VOID tx_thread_register_bank_assign(VOID *thread_ptr, UINT register_bank); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARC_HS/MetaWare Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARC_HS/MetaWare Version 6.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/arc_hs/metaware/readme_threadx.txt b/ports/arc_hs/metaware/readme_threadx.txt index 7f7e1716..92b604b6 100644 --- a/ports/arc_hs/metaware/readme_threadx.txt +++ b/ports/arc_hs/metaware/readme_threadx.txt @@ -241,7 +241,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX 6.0.1 for ARC HS using MetaWare tools. +09-30-2020 Initial ThreadX 6.1 for ARC HS using MetaWare tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/arc_hs/metaware/src/tx_initialize_fast_interrupt_setup.s b/ports/arc_hs/metaware/src/tx_initialize_fast_interrupt_setup.s index 4effd106..7a2c8549 100644 --- a/ports/arc_hs/metaware/src/tx_initialize_fast_interrupt_setup.s +++ b/ports/arc_hs/metaware/src/tx_initialize_fast_interrupt_setup.s @@ -35,7 +35,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_fast_interrupt_setup ARC_HS/MetaWare */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -66,7 +66,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_fast_interrupt_setup(VOID *stack_ptr) diff --git a/ports/arc_hs/metaware/src/tx_thread_context_fast_restore.s b/ports/arc_hs/metaware/src/tx_thread_context_fast_restore.s index 9b5e71b2..1181d9e3 100644 --- a/ports/arc_hs/metaware/src/tx_thread_context_fast_restore.s +++ b/ports/arc_hs/metaware/src/tx_thread_context_fast_restore.s @@ -37,7 +37,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_fast_restore ARC_HS/MetaWare */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -69,7 +69,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_fast_restore(VOID) diff --git a/ports/arc_hs/metaware/src/tx_thread_context_fast_save.s b/ports/arc_hs/metaware/src/tx_thread_context_fast_save.s index c25f39bb..ceb1cb44 100644 --- a/ports/arc_hs/metaware/src/tx_thread_context_fast_save.s +++ b/ports/arc_hs/metaware/src/tx_thread_context_fast_save.s @@ -36,7 +36,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_fast_save ARC_HS/MetaWare */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_fast_save(VOID) diff --git a/ports/arc_hs/metaware/src/tx_thread_context_restore.s b/ports/arc_hs/metaware/src/tx_thread_context_restore.s index 497aec43..e88df32d 100644 --- a/ports/arc_hs/metaware/src/tx_thread_context_restore.s +++ b/ports/arc_hs/metaware/src/tx_thread_context_restore.s @@ -37,7 +37,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore ARC_HS/MetaWare */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -69,7 +69,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports/arc_hs/metaware/src/tx_thread_context_save.s b/ports/arc_hs/metaware/src/tx_thread_context_save.s index b24cc042..937d60ed 100644 --- a/ports/arc_hs/metaware/src/tx_thread_context_save.s +++ b/ports/arc_hs/metaware/src/tx_thread_context_save.s @@ -37,7 +37,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save ARC_HS/MetaWare */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -68,7 +68,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) diff --git a/ports/arc_hs/metaware/src/tx_thread_interrupt_control.s b/ports/arc_hs/metaware/src/tx_thread_interrupt_control.s index cfa6221b..4054553f 100644 --- a/ports/arc_hs/metaware/src/tx_thread_interrupt_control.s +++ b/ports/arc_hs/metaware/src/tx_thread_interrupt_control.s @@ -34,7 +34,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control ARC_HS/MetaWare */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -64,7 +64,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/arc_hs/metaware/src/tx_thread_register_bank_assign.s b/ports/arc_hs/metaware/src/tx_thread_register_bank_assign.s index 172a7f31..560afc7f 100644 --- a/ports/arc_hs/metaware/src/tx_thread_register_bank_assign.s +++ b/ports/arc_hs/metaware/src/tx_thread_register_bank_assign.s @@ -35,7 +35,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_register_bank_assign ARC_HS/MetaWare */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -68,7 +68,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_register_bank_assign(VOID *thread_ptr, UINT register_bank) diff --git a/ports/arc_hs/metaware/src/tx_thread_schedule.s b/ports/arc_hs/metaware/src/tx_thread_schedule.s index 7560e34f..cdcde52d 100644 --- a/ports/arc_hs/metaware/src/tx_thread_schedule.s +++ b/ports/arc_hs/metaware/src/tx_thread_schedule.s @@ -38,7 +38,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule ARC_HS/MetaWare */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) diff --git a/ports/arc_hs/metaware/src/tx_thread_stack_build.s b/ports/arc_hs/metaware/src/tx_thread_stack_build.s index 4562db37..f5c45195 100644 --- a/ports/arc_hs/metaware/src/tx_thread_stack_build.s +++ b/ports/arc_hs/metaware/src/tx_thread_stack_build.s @@ -39,7 +39,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build ARC_HS/MetaWare */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/arc_hs/metaware/src/tx_thread_system_return.s b/ports/arc_hs/metaware/src/tx_thread_system_return.s index 7d661965..ed59fb42 100644 --- a/ports/arc_hs/metaware/src/tx_thread_system_return.s +++ b/ports/arc_hs/metaware/src/tx_thread_system_return.s @@ -35,7 +35,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return ARC_HS/MetaWare */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -67,7 +67,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) diff --git a/ports/arc_hs/metaware/src/tx_timer_interrupt.s b/ports/arc_hs/metaware/src/tx_timer_interrupt.s index 4edc1aa4..663e9060 100644 --- a/ports/arc_hs/metaware/src/tx_timer_interrupt.s +++ b/ports/arc_hs/metaware/src/tx_timer_interrupt.s @@ -35,7 +35,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt ARC_HS/MetaWare */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) diff --git a/ports/arm11/ac5/example_build/tx_initialize_low_level.s b/ports/arm11/ac5/example_build/tx_initialize_low_level.s index a7bd0a35..f8642359 100644 --- a/ports/arm11/ac5/example_build/tx_initialize_low_level.s +++ b/ports/arm11/ac5/example_build/tx_initialize_low_level.s @@ -119,7 +119,7 @@ __vectors ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level ARM11/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -152,7 +152,7 @@ __vectors ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports/arm11/ac5/inc/tx_port.h b/ports/arm11/ac5/inc/tx_port.h index 90145158..0c873cc1 100644 --- a/ports/arm11/ac5/inc/tx_port.h +++ b/ports/arm11/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h ARM11/AC5 */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -317,7 +317,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARM11/AC5 Version 6.0.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARM11/AC5 Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/arm11/ac5/readme_threadx.txt b/ports/arm11/ac5/readme_threadx.txt index 836a2e01..114b5089 100644 --- a/ports/arm11/ac5/readme_threadx.txt +++ b/ports/arm11/ac5/readme_threadx.txt @@ -524,7 +524,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A5 using AC5 tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-A5 using AC5 tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/arm11/ac5/src/tx_thread_context_restore.s b/ports/arm11/ac5/src/tx_thread_context_restore.s index 1d6cd60f..8074c6b3 100644 --- a/ports/arm11/ac5/src/tx_thread_context_restore.s +++ b/ports/arm11/ac5/src/tx_thread_context_restore.s @@ -61,7 +61,7 @@ SVC_MODE_BITS EQU 0x13 ; SVC mode value ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore ARM11/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -93,7 +93,7 @@ SVC_MODE_BITS EQU 0x13 ; SVC mode value ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports/arm11/ac5/src/tx_thread_context_save.s b/ports/arm11/ac5/src/tx_thread_context_save.s index 6ce74590..56a8ea84 100644 --- a/ports/arm11/ac5/src/tx_thread_context_save.s +++ b/ports/arm11/ac5/src/tx_thread_context_save.s @@ -51,7 +51,7 @@ DISABLE_INTS EQU 0x80 ; IRQ interrupts disabled ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save ARM11/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ DISABLE_INTS EQU 0x80 ; IRQ interrupts disabled ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) diff --git a/ports/arm11/ac5/src/tx_thread_fiq_context_restore.s b/ports/arm11/ac5/src/tx_thread_fiq_context_restore.s index a183032b..1747d38a 100644 --- a/ports/arm11/ac5/src/tx_thread_fiq_context_restore.s +++ b/ports/arm11/ac5/src/tx_thread_fiq_context_restore.s @@ -63,7 +63,7 @@ SVC_MODE_BITS EQU 0x13 ; SVC mode value ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_context_restore ARM11/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -95,7 +95,7 @@ SVC_MODE_BITS EQU 0x13 ; SVC mode value ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_context_restore(VOID) diff --git a/ports/arm11/ac5/src/tx_thread_fiq_context_save.s b/ports/arm11/ac5/src/tx_thread_fiq_context_save.s index 370e0946..c3a50830 100644 --- a/ports/arm11/ac5/src/tx_thread_fiq_context_save.s +++ b/ports/arm11/ac5/src/tx_thread_fiq_context_save.s @@ -45,7 +45,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_context_save ARM11/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -76,7 +76,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ; VOID _tx_thread_fiq_context_save(VOID) diff --git a/ports/arm11/ac5/src/tx_thread_fiq_nesting_end.s b/ports/arm11/ac5/src/tx_thread_fiq_nesting_end.s index 5d81879d..f3f755c2 100644 --- a/ports/arm11/ac5/src/tx_thread_fiq_nesting_end.s +++ b/ports/arm11/ac5/src/tx_thread_fiq_nesting_end.s @@ -45,7 +45,7 @@ FIQ_MODE_BITS EQU 0x11 ; FIQ mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_nesting_end ARM11/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -84,7 +84,7 @@ FIQ_MODE_BITS EQU 0x11 ; FIQ mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_end(VOID) diff --git a/ports/arm11/ac5/src/tx_thread_fiq_nesting_start.s b/ports/arm11/ac5/src/tx_thread_fiq_nesting_start.s index 32c1b258..75a85f61 100644 --- a/ports/arm11/ac5/src/tx_thread_fiq_nesting_start.s +++ b/ports/arm11/ac5/src/tx_thread_fiq_nesting_start.s @@ -41,7 +41,7 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_nesting_start ARM11/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/arm11/ac5/src/tx_thread_interrupt_control.s b/ports/arm11/ac5/src/tx_thread_interrupt_control.s index f11c820e..47e55cd4 100644 --- a/ports/arm11/ac5/src/tx_thread_interrupt_control.s +++ b/ports/arm11/ac5/src/tx_thread_interrupt_control.s @@ -42,7 +42,7 @@ INT_MASK EQU 0x80 ; Interrupt bit mask ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control ARM11/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ INT_MASK EQU 0x80 ; Interrupt bit mask ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/arm11/ac5/src/tx_thread_interrupt_disable.s b/ports/arm11/ac5/src/tx_thread_interrupt_disable.s index a3145dab..114c4714 100644 --- a/ports/arm11/ac5/src/tx_thread_interrupt_disable.s +++ b/ports/arm11/ac5/src/tx_thread_interrupt_disable.s @@ -42,7 +42,7 @@ DISABLE_INTS EQU 0x80 ; IRQ interrupts disabled ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_disable ARM11/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ DISABLE_INTS EQU 0x80 ; IRQ interrupts disabled ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(void) diff --git a/ports/arm11/ac5/src/tx_thread_interrupt_restore.s b/ports/arm11/ac5/src/tx_thread_interrupt_restore.s index aad4e743..e3e6f66f 100644 --- a/ports/arm11/ac5/src/tx_thread_interrupt_restore.s +++ b/ports/arm11/ac5/src/tx_thread_interrupt_restore.s @@ -35,7 +35,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore ARM11/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -65,7 +65,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/arm11/ac5/src/tx_thread_irq_nesting_end.s b/ports/arm11/ac5/src/tx_thread_irq_nesting_end.s index 415d6152..cb90e280 100644 --- a/ports/arm11/ac5/src/tx_thread_irq_nesting_end.s +++ b/ports/arm11/ac5/src/tx_thread_irq_nesting_end.s @@ -45,7 +45,7 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_irq_nesting_end ARM11/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -84,7 +84,7 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports/arm11/ac5/src/tx_thread_irq_nesting_start.s b/ports/arm11/ac5/src/tx_thread_irq_nesting_start.s index 417235dd..244d1d82 100644 --- a/ports/arm11/ac5/src/tx_thread_irq_nesting_start.s +++ b/ports/arm11/ac5/src/tx_thread_irq_nesting_start.s @@ -41,7 +41,7 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_irq_nesting_start ARM11/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/arm11/ac5/src/tx_thread_schedule.s b/ports/arm11/ac5/src/tx_thread_schedule.s index 0347394e..46fc59b7 100644 --- a/ports/arm11/ac5/src/tx_thread_schedule.s +++ b/ports/arm11/ac5/src/tx_thread_schedule.s @@ -53,7 +53,7 @@ ENABLE_INTS EQU 0x80 ; IRQ Interrupts enabled mask ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule ARM11/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -86,7 +86,7 @@ ENABLE_INTS EQU 0x80 ; IRQ Interrupts enabled mask ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) diff --git a/ports/arm11/ac5/src/tx_thread_stack_build.s b/ports/arm11/ac5/src/tx_thread_stack_build.s index d9b68fa9..de0d22e0 100644 --- a/ports/arm11/ac5/src/tx_thread_stack_build.s +++ b/ports/arm11/ac5/src/tx_thread_stack_build.s @@ -44,7 +44,7 @@ CPSR_MASK EQU 0x9F ; Mask initial CPSR, IRQ ints en ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build ARM11/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -76,7 +76,7 @@ CPSR_MASK EQU 0x9F ; Mask initial CPSR, IRQ ints en ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/arm11/ac5/src/tx_thread_system_return.s b/ports/arm11/ac5/src/tx_thread_system_return.s index 9bfd95d9..8ddc8f1f 100644 --- a/ports/arm11/ac5/src/tx_thread_system_return.s +++ b/ports/arm11/ac5/src/tx_thread_system_return.s @@ -52,7 +52,7 @@ DISABLE_INTS EQU 0x80 ; IRQ interrupts disabled ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return ARM11/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -84,7 +84,7 @@ DISABLE_INTS EQU 0x80 ; IRQ interrupts disabled ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) diff --git a/ports/arm11/ac5/src/tx_thread_vectored_context_save.s b/ports/arm11/ac5/src/tx_thread_vectored_context_save.s index f318ff3d..5d55ed6a 100644 --- a/ports/arm11/ac5/src/tx_thread_vectored_context_save.s +++ b/ports/arm11/ac5/src/tx_thread_vectored_context_save.s @@ -51,7 +51,7 @@ DISABLE_INTS EQU 0x80 ; IRQ interrupts disabled ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_vectored_context_save ARM11/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ DISABLE_INTS EQU 0x80 ; IRQ interrupts disabled ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) diff --git a/ports/arm11/ac5/src/tx_timer_interrupt.s b/ports/arm11/ac5/src/tx_timer_interrupt.s index 158f6930..81eff98d 100644 --- a/ports/arm11/ac5/src/tx_timer_interrupt.s +++ b/ports/arm11/ac5/src/tx_timer_interrupt.s @@ -50,7 +50,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt ARM11/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -84,7 +84,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) diff --git a/ports/arm11/gnu/example_build/tx_initialize_low_level.S b/ports/arm11/gnu/example_build/tx_initialize_low_level.S index 1cce43f6..7b9929c3 100644 --- a/ports/arm11/gnu/example_build/tx_initialize_low_level.S +++ b/ports/arm11/gnu/example_build/tx_initialize_low_level.S @@ -78,7 +78,7 @@ $_tx_initialize_low_level: @/* FUNCTION RELEASE */ @/* */ @/* _tx_initialize_low_level ARM11/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -111,7 +111,7 @@ $_tx_initialize_low_level: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) diff --git a/ports/arm11/gnu/inc/tx_port.h b/ports/arm11/gnu/inc/tx_port.h index 3b8e85bf..09c52000 100644 --- a/ports/arm11/gnu/inc/tx_port.h +++ b/ports/arm11/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h ARM11/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -306,7 +306,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARM11/GNU Version 6.0.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARM11/GNU Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/arm11/gnu/readme_threadx.txt b/ports/arm11/gnu/readme_threadx.txt index 5f36d8ed..6c502efd 100644 --- a/ports/arm11/gnu/readme_threadx.txt +++ b/ports/arm11/gnu/readme_threadx.txt @@ -486,7 +486,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX 6.0.1 version for ARM11 using GNU tools. +09-30-2020 Initial ThreadX 6.1 version for ARM11 using GNU tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/arm11/gnu/src/tx_thread_context_restore.S b/ports/arm11/gnu/src/tx_thread_context_restore.S index 9e116197..307bbee8 100644 --- a/ports/arm11/gnu/src/tx_thread_context_restore.S +++ b/ports/arm11/gnu/src/tx_thread_context_restore.S @@ -60,7 +60,7 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_restore ARM11/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -92,7 +92,7 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) diff --git a/ports/arm11/gnu/src/tx_thread_context_save.S b/ports/arm11/gnu/src/tx_thread_context_save.S index 8a072cf5..29da6606 100644 --- a/ports/arm11/gnu/src/tx_thread_context_save.S +++ b/ports/arm11/gnu/src/tx_thread_context_save.S @@ -53,7 +53,7 @@ DISABLE_INTS = 0x80 @ IRQ interrupts disabled @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_save ARM11/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -84,7 +84,7 @@ DISABLE_INTS = 0x80 @ IRQ interrupts disabled @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) diff --git a/ports/arm11/gnu/src/tx_thread_fiq_context_restore.S b/ports/arm11/gnu/src/tx_thread_fiq_context_restore.S index 44acd526..6db8a024 100644 --- a/ports/arm11/gnu/src/tx_thread_fiq_context_restore.S +++ b/ports/arm11/gnu/src/tx_thread_fiq_context_restore.S @@ -61,7 +61,7 @@ SVC_MODE_BITS = 0x13 @ SVC mode value @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_context_restore ARM11/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -93,7 +93,7 @@ SVC_MODE_BITS = 0x13 @ SVC mode value @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_context_restore(VOID) diff --git a/ports/arm11/gnu/src/tx_thread_fiq_context_save.S b/ports/arm11/gnu/src/tx_thread_fiq_context_save.S index 53b12f9b..a2b1ee3d 100644 --- a/ports/arm11/gnu/src/tx_thread_fiq_context_save.S +++ b/ports/arm11/gnu/src/tx_thread_fiq_context_save.S @@ -47,7 +47,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_context_save ARM11/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -78,7 +78,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @ VOID _tx_thread_fiq_context_save(VOID) diff --git a/ports/arm11/gnu/src/tx_thread_fiq_nesting_end.S b/ports/arm11/gnu/src/tx_thread_fiq_nesting_end.S index cc0d4991..8fb04d73 100644 --- a/ports/arm11/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/arm11/gnu/src/tx_thread_fiq_nesting_end.S @@ -50,7 +50,7 @@ FIQ_MODE_BITS = 0x11 @ FIQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_nesting_end ARM11/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -89,7 +89,7 @@ FIQ_MODE_BITS = 0x11 @ FIQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_end(VOID) diff --git a/ports/arm11/gnu/src/tx_thread_fiq_nesting_start.S b/ports/arm11/gnu/src/tx_thread_fiq_nesting_start.S index b9dda19e..9cc647b6 100644 --- a/ports/arm11/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/arm11/gnu/src/tx_thread_fiq_nesting_start.S @@ -46,7 +46,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_nesting_start ARM11/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/arm11/gnu/src/tx_thread_interrupt_control.S b/ports/arm11/gnu/src/tx_thread_interrupt_control.S index 4cf397c9..fa19f085 100644 --- a/ports/arm11/gnu/src/tx_thread_interrupt_control.S +++ b/ports/arm11/gnu/src/tx_thread_interrupt_control.S @@ -56,7 +56,7 @@ $_tx_thread_interrupt_control: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_control ARM11/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -86,7 +86,7 @@ $_tx_thread_interrupt_control: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/arm11/gnu/src/tx_thread_interrupt_disable.S b/ports/arm11/gnu/src/tx_thread_interrupt_disable.S index 9d460e24..471eb459 100644 --- a/ports/arm11/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/arm11/gnu/src/tx_thread_interrupt_disable.S @@ -60,7 +60,7 @@ $_tx_thread_interrupt_disable: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_disable ARM11/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -89,7 +89,7 @@ $_tx_thread_interrupt_disable: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_disable(void) diff --git a/ports/arm11/gnu/src/tx_thread_interrupt_restore.S b/ports/arm11/gnu/src/tx_thread_interrupt_restore.S index 0a06d5ea..d3b01c55 100644 --- a/ports/arm11/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/arm11/gnu/src/tx_thread_interrupt_restore.S @@ -53,7 +53,7 @@ $_tx_thread_interrupt_restore: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_restore ARM11/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -83,7 +83,7 @@ $_tx_thread_interrupt_restore: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/arm11/gnu/src/tx_thread_irq_nesting_end.S b/ports/arm11/gnu/src/tx_thread_irq_nesting_end.S index 3fda4dae..397be0ed 100644 --- a/ports/arm11/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/arm11/gnu/src/tx_thread_irq_nesting_end.S @@ -50,7 +50,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_irq_nesting_end ARM11/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -89,7 +89,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports/arm11/gnu/src/tx_thread_irq_nesting_start.S b/ports/arm11/gnu/src/tx_thread_irq_nesting_start.S index f8e4a134..0d04422f 100644 --- a/ports/arm11/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/arm11/gnu/src/tx_thread_irq_nesting_start.S @@ -46,7 +46,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_irq_nesting_start ARM11/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/arm11/gnu/src/tx_thread_schedule.S b/ports/arm11/gnu/src/tx_thread_schedule.S index 09692e98..2f386b0d 100644 --- a/ports/arm11/gnu/src/tx_thread_schedule.S +++ b/ports/arm11/gnu/src/tx_thread_schedule.S @@ -68,7 +68,7 @@ $_tx_thread_schedule: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule ARM11/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -101,7 +101,7 @@ $_tx_thread_schedule: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) diff --git a/ports/arm11/gnu/src/tx_thread_stack_build.S b/ports/arm11/gnu/src/tx_thread_stack_build.S index ea34e6c2..9117d22e 100644 --- a/ports/arm11/gnu/src/tx_thread_stack_build.S +++ b/ports/arm11/gnu/src/tx_thread_stack_build.S @@ -64,7 +64,7 @@ $_tx_thread_stack_build: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_stack_build ARM11/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -96,7 +96,7 @@ $_tx_thread_stack_build: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/arm11/gnu/src/tx_thread_system_return.S b/ports/arm11/gnu/src/tx_thread_system_return.S index 87bef5aa..05024c46 100644 --- a/ports/arm11/gnu/src/tx_thread_system_return.S +++ b/ports/arm11/gnu/src/tx_thread_system_return.S @@ -70,7 +70,7 @@ $_tx_thread_system_return: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_system_return ARM11/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -102,7 +102,7 @@ $_tx_thread_system_return: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_system_return(VOID) diff --git a/ports/arm11/gnu/src/tx_thread_vectored_context_save.S b/ports/arm11/gnu/src/tx_thread_vectored_context_save.S index 3ac517ac..515bd9ca 100644 --- a/ports/arm11/gnu/src/tx_thread_vectored_context_save.S +++ b/ports/arm11/gnu/src/tx_thread_vectored_context_save.S @@ -54,7 +54,7 @@ DISABLE_INTS = 0x80 @ IRQ interrupts disabled @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_vectored_context_save ARM11/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -85,7 +85,7 @@ DISABLE_INTS = 0x80 @ IRQ interrupts disabled @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_vectored_context_save(VOID) diff --git a/ports/arm11/gnu/src/tx_timer_interrupt.S b/ports/arm11/gnu/src/tx_timer_interrupt.S index 60632a32..66705b94 100644 --- a/ports/arm11/gnu/src/tx_timer_interrupt.S +++ b/ports/arm11/gnu/src/tx_timer_interrupt.S @@ -71,7 +71,7 @@ $_tx_timer_interrupt: @/* FUNCTION RELEASE */ @/* */ @/* _tx_timer_interrupt ARM11/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -105,7 +105,7 @@ $_tx_timer_interrupt: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) diff --git a/ports/arm11/iar/example_build/tx_initialize_low_level.s b/ports/arm11/iar/example_build/tx_initialize_low_level.s index 1ff234c9..6166f0ef 100644 --- a/ports/arm11/iar/example_build/tx_initialize_low_level.s +++ b/ports/arm11/iar/example_build/tx_initialize_low_level.s @@ -1,23 +1,11 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) 1996-2018 by Express Logic Inc. */ -;/* */ -;/* This software is copyrighted by and is the sole property of Express */ -;/* Logic, Inc. All rights, title, ownership, or other interests */ -;/* in the software remain the property of Express Logic, Inc. This */ -;/* software may only be used in accordance with the corresponding */ -;/* license agreement. Any unauthorized use, duplication, transmission, */ -;/* distribution, or disclosure of this software is expressly forbidden. */ +;/**************************************************************************/ ;/* */ -;/* This Copyright notice may not be removed or modified without prior */ -;/* written consent of Express Logic, Inc. */ -;/* */ -;/* Express Logic, Inc. reserves the right to modify this software */ -;/* without notice. */ -;/* */ -;/* Express Logic, Inc. info@expresslogic.com */ -;/* 11423 West Bernardo Court http://www.expresslogic.com */ -;/* San Diego, CA 92127 */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ ;/* */ ;/**************************************************************************/ ; @@ -93,10 +81,10 @@ __tx_free_memory_start ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level ARM11/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ -;/* William E. Lamie, Express Logic, Inc. */ +;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ @@ -126,7 +114,7 @@ __tx_free_memory_start ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports/arm11/iar/inc/tx_port.h b/ports/arm11/iar/inc/tx_port.h index 9a305c69..150c0578 100644 --- a/ports/arm11/iar/inc/tx_port.h +++ b/ports/arm11/iar/inc/tx_port.h @@ -1,23 +1,11 @@ -/**************************************************************************/ -/* */ -/* Copyright (c) 1996-2018 by Express Logic Inc. */ -/* */ -/* This software is copyrighted by and is the sole property of Express */ -/* Logic, Inc. All rights, title, ownership, or other interests */ -/* in the software remain the property of Express Logic, Inc. This */ -/* software may only be used in accordance with the corresponding */ -/* license agreement. Any unauthorized use, duplication, transmission, */ -/* distribution, or disclosure of this software is expressly forbidden. */ +/**************************************************************************/ /* */ -/* This Copyright notice may not be removed or modified without prior */ -/* written consent of Express Logic, Inc. */ -/* */ -/* Express Logic, Inc. reserves the right to modify this software */ -/* without notice. */ -/* */ -/* Express Logic, Inc. info@expresslogic.com */ -/* 11423 West Bernardo Court http://www.expresslogic.com */ -/* San Diego, CA 92127 */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ /* */ /**************************************************************************/ @@ -37,12 +25,12 @@ /* */ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ -/* tx_port.h ARM11/IAR */ -/* 6.0.1 */ +/* tx_port.h ARM11/IAR */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ -/* William E. Lamie, Express Logic, Inc. */ +/* William E. Lamie, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ @@ -59,8 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial ARM11 IAR */ -/* Support Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -385,7 +372,7 @@ void _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARM11/IAR Version 6.0.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARM11/IAR Version 6.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/arm11/iar/readme_threadx.txt b/ports/arm11/iar/readme_threadx.txt index d585f517..7b0400af 100644 --- a/ports/arm11/iar/readme_threadx.txt +++ b/ports/arm11/iar/readme_threadx.txt @@ -517,7 +517,7 @@ The project options "General Options -> Library Configuration" should also have 11. Revision History -06/30/2020 Initial ThreadX 6.0.1 version for ARM11 using IAR's ARM tools. +09-30-2020 Initial ThreadX 6.1 version for ARM11 using IAR's ARM tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/arm11/iar/src/tx_iar.c b/ports/arm11/iar/src/tx_iar.c index 95592d4b..11fcefb3 100644 --- a/ports/arm11/iar/src/tx_iar.c +++ b/ports/arm11/iar/src/tx_iar.c @@ -1,23 +1,11 @@ -/**************************************************************************/ -/* */ -/* Copyright (c) 1996-2018 by Express Logic Inc. */ -/* */ -/* This software is copyrighted by and is the sole property of Express */ -/* Logic, Inc. All rights, title, ownership, or other interests */ -/* in the software remain the property of Express Logic, Inc. This */ -/* software may only be used in accordance with the corresponding */ -/* license agreement. Any unauthorized use, duplication, transmission, */ -/* distribution, or disclosure of this software is expressly forbidden. */ +/**************************************************************************/ /* */ -/* This Copyright notice may not be removed or modified without prior */ -/* written consent of Express Logic, Inc. */ -/* */ -/* Express Logic, Inc. reserves the right to modify this software */ -/* without notice. */ -/* */ -/* Express Logic, Inc. info@expresslogic.com */ -/* 11423 West Bernardo Court www.expresslogic.com */ -/* San Diego, CA 92127 */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ /* */ /**************************************************************************/ diff --git a/ports/arm11/iar/src/tx_thread_context_restore.s b/ports/arm11/iar/src/tx_thread_context_restore.s index a66ecdc5..c4a67206 100644 --- a/ports/arm11/iar/src/tx_thread_context_restore.s +++ b/ports/arm11/iar/src/tx_thread_context_restore.s @@ -1,23 +1,12 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) 1996-2018 by Express Logic Inc. */ -;/* */ -;/* This software is copyrighted by and is the sole property of Express */ -;/* Logic, Inc. All rights, title, ownership, or other interests */ -;/* in the software remain the property of Express Logic, Inc. This */ -;/* software may only be used in accordance with the corresponding */ -;/* license agreement. Any unauthorized use, duplication, transmission, */ -;/* distribution, or disclosure of this software is expressly forbidden. */ + +;/**************************************************************************/ ;/* */ -;/* This Copyright notice may not be removed or modified without prior */ -;/* written consent of Express Logic, Inc. */ -;/* */ -;/* Express Logic, Inc. reserves the right to modify this software */ -;/* without notice. */ -;/* */ -;/* Express Logic, Inc. info@expresslogic.com */ -;/* 11423 West Bernardo Court http://www.expresslogic.com */ -;/* San Diego, CA 92127 */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ ;/* */ ;/**************************************************************************/ ; @@ -69,10 +58,10 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore ARM11/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ -;/* William E. Lamie, Express Logic, Inc. */ +;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ @@ -101,7 +90,7 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports/arm11/iar/src/tx_thread_context_save.s b/ports/arm11/iar/src/tx_thread_context_save.s index 71d7347e..9416bc86 100644 --- a/ports/arm11/iar/src/tx_thread_context_save.s +++ b/ports/arm11/iar/src/tx_thread_context_save.s @@ -1,23 +1,12 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) 1996-2018 by Express Logic Inc. */ -;/* */ -;/* This software is copyrighted by and is the sole property of Express */ -;/* Logic, Inc. All rights, title, ownership, or other interests */ -;/* in the software remain the property of Express Logic, Inc. This */ -;/* software may only be used in accordance with the corresponding */ -;/* license agreement. Any unauthorized use, duplication, transmission, */ -;/* distribution, or disclosure of this software is expressly forbidden. */ + +;/**************************************************************************/ ;/* */ -;/* This Copyright notice may not be removed or modified without prior */ -;/* written consent of Express Logic, Inc. */ -;/* */ -;/* Express Logic, Inc. reserves the right to modify this software */ -;/* without notice. */ -;/* */ -;/* Express Logic, Inc. info@expresslogic.com */ -;/* 11423 West Bernardo Court http://www.expresslogic.com */ -;/* San Diego, CA 92127 */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ ;/* */ ;/**************************************************************************/ ; @@ -61,10 +50,10 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save ARM11/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ -;/* William E. Lamie, Express Logic, Inc. */ +;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ @@ -92,7 +81,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) diff --git a/ports/arm11/iar/src/tx_thread_fiq_context_restore.s b/ports/arm11/iar/src/tx_thread_fiq_context_restore.s index a8f9f0bd..b3a06804 100644 --- a/ports/arm11/iar/src/tx_thread_fiq_context_restore.s +++ b/ports/arm11/iar/src/tx_thread_fiq_context_restore.s @@ -1,23 +1,12 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) 1996-2018 by Express Logic Inc. */ -;/* */ -;/* This software is copyrighted by and is the sole property of Express */ -;/* Logic, Inc. All rights, title, ownership, or other interests */ -;/* in the software remain the property of Express Logic, Inc. This */ -;/* software may only be used in accordance with the corresponding */ -;/* license agreement. Any unauthorized use, duplication, transmission, */ -;/* distribution, or disclosure of this software is expressly forbidden. */ + +;/**************************************************************************/ ;/* */ -;/* This Copyright notice may not be removed or modified without prior */ -;/* written consent of Express Logic, Inc. */ -;/* */ -;/* Express Logic, Inc. reserves the right to modify this software */ -;/* without notice. */ -;/* */ -;/* Express Logic, Inc. info@expresslogic.com */ -;/* 11423 West Bernardo Court http://www.expresslogic.com */ -;/* San Diego, CA 92127 */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ ;/* */ ;/**************************************************************************/ ; @@ -70,10 +59,10 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_context_restore ARM11/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ -;/* William E. Lamie, Express Logic, Inc. */ +;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ @@ -102,7 +91,7 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_context_restore(VOID) diff --git a/ports/arm11/iar/src/tx_thread_fiq_context_save.s b/ports/arm11/iar/src/tx_thread_fiq_context_save.s index 7745f756..f7fa73ad 100644 --- a/ports/arm11/iar/src/tx_thread_fiq_context_save.s +++ b/ports/arm11/iar/src/tx_thread_fiq_context_save.s @@ -1,27 +1,15 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) 1996-2018 by Express Logic Inc. */ -;/* */ -;/* This software is copyrighted by and is the sole property of Express */ -;/* Logic, Inc. All rights, title, ownership, or other interests */ -;/* in the software remain the property of Express Logic, Inc. This */ -;/* software may only be used in accordance with the corresponding */ -;/* license agreement. Any unauthorized use, duplication, transmission, */ -;/* distribution, or disclosure of this software is expressly forbidden. */ + +;/**************************************************************************/ ;/* */ -;/* This Copyright notice may not be removed or modified without prior */ -;/* written consent of Express Logic, Inc. */ -;/* */ -;/* Express Logic, Inc. reserves the right to modify this software */ -;/* without notice. */ -;/* */ -;/* Express Logic, Inc. info@expresslogic.com */ -;/* 11423 West Bernardo Court http://www.expresslogic.com */ -;/* San Diego, CA 92127 */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ ;/* */ ;/**************************************************************************/ ; -; ;/**************************************************************************/ ;/**************************************************************************/ ;/** */ @@ -54,10 +42,10 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_context_save ARM11/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ -;/* William E. Lamie, Express Logic, Inc. */ +;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ @@ -85,7 +73,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ; VOID _tx_thread_fiq_context_save(VOID) diff --git a/ports/arm11/iar/src/tx_thread_fiq_nesting_end.s b/ports/arm11/iar/src/tx_thread_fiq_nesting_end.s index 008b3b40..20854d6e 100644 --- a/ports/arm11/iar/src/tx_thread_fiq_nesting_end.s +++ b/ports/arm11/iar/src/tx_thread_fiq_nesting_end.s @@ -1,23 +1,11 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) 1996-2018 by Express Logic Inc. */ -;/* */ -;/* This software is copyrighted by and is the sole property of Express */ -;/* Logic, Inc. All rights, title, ownership, or other interests */ -;/* in the software remain the property of Express Logic, Inc. This */ -;/* software may only be used in accordance with the corresponding */ -;/* license agreement. Any unauthorized use, duplication, transmission, */ -;/* distribution, or disclosure of this software is expressly forbidden. */ +;/**************************************************************************/ ;/* */ -;/* This Copyright notice may not be removed or modified without prior */ -;/* written consent of Express Logic, Inc. */ -;/* */ -;/* Express Logic, Inc. reserves the right to modify this software */ -;/* without notice. */ -;/* */ -;/* Express Logic, Inc. info@expresslogic.com */ -;/* 11423 West Bernardo Court http://www.expresslogic.com */ -;/* San Diego, CA 92127 */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ ;/* */ ;/**************************************************************************/ ; @@ -56,10 +44,10 @@ FIQ_MODE_BITS DEFINE 0x11 ; FIQ mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_nesting_end ARM11/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ -;/* William E. Lamie, Express Logic, Inc. */ +;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ @@ -95,7 +83,7 @@ FIQ_MODE_BITS DEFINE 0x11 ; FIQ mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_end(VOID) diff --git a/ports/arm11/iar/src/tx_thread_fiq_nesting_start.s b/ports/arm11/iar/src/tx_thread_fiq_nesting_start.s index f4411d08..e7fe031d 100644 --- a/ports/arm11/iar/src/tx_thread_fiq_nesting_start.s +++ b/ports/arm11/iar/src/tx_thread_fiq_nesting_start.s @@ -1,23 +1,11 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) 1996-2018 by Express Logic Inc. */ -;/* */ -;/* This software is copyrighted by and is the sole property of Express */ -;/* Logic, Inc. All rights, title, ownership, or other interests */ -;/* in the software remain the property of Express Logic, Inc. This */ -;/* software may only be used in accordance with the corresponding */ -;/* license agreement. Any unauthorized use, duplication, transmission, */ -;/* distribution, or disclosure of this software is expressly forbidden. */ +;/**************************************************************************/ ;/* */ -;/* This Copyright notice may not be removed or modified without prior */ -;/* written consent of Express Logic, Inc. */ -;/* */ -;/* Express Logic, Inc. reserves the right to modify this software */ -;/* without notice. */ -;/* */ -;/* Express Logic, Inc. info@expresslogic.com */ -;/* 11423 West Bernardo Court http://www.expresslogic.com */ -;/* San Diego, CA 92127 */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ ;/* */ ;/**************************************************************************/ ; @@ -53,10 +41,10 @@ SYS_MODE_BITS DEFINE 0x1F ; System mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_nesting_start ARM11/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ -;/* William E. Lamie, Express Logic, Inc. */ +;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ @@ -89,7 +77,7 @@ SYS_MODE_BITS DEFINE 0x1F ; System mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/arm11/iar/src/tx_thread_interrupt_control.s b/ports/arm11/iar/src/tx_thread_interrupt_control.s index f80e31d8..ed898210 100644 --- a/ports/arm11/iar/src/tx_thread_interrupt_control.s +++ b/ports/arm11/iar/src/tx_thread_interrupt_control.s @@ -1,23 +1,11 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) 1996-2018 by Express Logic Inc. */ -;/* */ -;/* This software is copyrighted by and is the sole property of Express */ -;/* Logic, Inc. All rights, title, ownership, or other interests */ -;/* in the software remain the property of Express Logic, Inc. This */ -;/* software may only be used in accordance with the corresponding */ -;/* license agreement. Any unauthorized use, duplication, transmission, */ -;/* distribution, or disclosure of this software is expressly forbidden. */ +;/**************************************************************************/ ;/* */ -;/* This Copyright notice may not be removed or modified without prior */ -;/* written consent of Express Logic, Inc. */ -;/* */ -;/* Express Logic, Inc. reserves the right to modify this software */ -;/* without notice. */ -;/* */ -;/* Express Logic, Inc. info@expresslogic.com */ -;/* 11423 West Bernardo Court http://www.expresslogic.com */ -;/* San Diego, CA 92127 */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ ;/* */ ;/**************************************************************************/ ; @@ -53,10 +41,10 @@ INT_MASK DEFINE 0x80 ; Interrupt bit mask ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control ARM11/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ -;/* William E. Lamie, Express Logic, Inc. */ +;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ @@ -83,7 +71,7 @@ INT_MASK DEFINE 0x80 ; Interrupt bit mask ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/arm11/iar/src/tx_thread_interrupt_disable.s b/ports/arm11/iar/src/tx_thread_interrupt_disable.s index e3029ecb..373440d0 100644 --- a/ports/arm11/iar/src/tx_thread_interrupt_disable.s +++ b/ports/arm11/iar/src/tx_thread_interrupt_disable.s @@ -1,23 +1,11 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) 1996-2018 by Express Logic Inc. */ -;/* */ -;/* This software is copyrighted by and is the sole property of Express */ -;/* Logic, Inc. All rights, title, ownership, or other interests */ -;/* in the software remain the property of Express Logic, Inc. This */ -;/* software may only be used in accordance with the corresponding */ -;/* license agreement. Any unauthorized use, duplication, transmission, */ -;/* distribution, or disclosure of this software is expressly forbidden. */ +;/**************************************************************************/ ;/* */ -;/* This Copyright notice may not be removed or modified without prior */ -;/* written consent of Express Logic, Inc. */ -;/* */ -;/* Express Logic, Inc. reserves the right to modify this software */ -;/* without notice. */ -;/* */ -;/* Express Logic, Inc. info@expresslogic.com */ -;/* 11423 West Bernardo Court http://www.expresslogic.com */ -;/* San Diego, CA 92127 */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ ;/* */ ;/**************************************************************************/ ; @@ -54,10 +42,10 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_disable ARM11/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ -;/* William E. Lamie, Express Logic, Inc. */ +;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ @@ -83,7 +71,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports/arm11/iar/src/tx_thread_interrupt_restore.s b/ports/arm11/iar/src/tx_thread_interrupt_restore.s index 0c0fdef0..df974303 100644 --- a/ports/arm11/iar/src/tx_thread_interrupt_restore.s +++ b/ports/arm11/iar/src/tx_thread_interrupt_restore.s @@ -1,23 +1,11 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) 1996-2018 by Express Logic Inc. */ -;/* */ -;/* This software is copyrighted by and is the sole property of Express */ -;/* Logic, Inc. All rights, title, ownership, or other interests */ -;/* in the software remain the property of Express Logic, Inc. This */ -;/* software may only be used in accordance with the corresponding */ -;/* license agreement. Any unauthorized use, duplication, transmission, */ -;/* distribution, or disclosure of this software is expressly forbidden. */ +;/**************************************************************************/ ;/* */ -;/* This Copyright notice may not be removed or modified without prior */ -;/* written consent of Express Logic, Inc. */ -;/* */ -;/* Express Logic, Inc. reserves the right to modify this software */ -;/* without notice. */ -;/* */ -;/* Express Logic, Inc. info@expresslogic.com */ -;/* 11423 West Bernardo Court http://www.expresslogic.com */ -;/* San Diego, CA 92127 */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ ;/* */ ;/**************************************************************************/ ; @@ -46,10 +34,10 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore ARM11/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ -;/* William E. Lamie, Express Logic, Inc. */ +;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ @@ -76,7 +64,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;void _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/arm11/iar/src/tx_thread_irq_nesting_end.s b/ports/arm11/iar/src/tx_thread_irq_nesting_end.s index 50da22c4..8e750ea1 100644 --- a/ports/arm11/iar/src/tx_thread_irq_nesting_end.s +++ b/ports/arm11/iar/src/tx_thread_irq_nesting_end.s @@ -1,23 +1,11 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) 1996-2018 by Express Logic Inc. */ -;/* */ -;/* This software is copyrighted by and is the sole property of Express */ -;/* Logic, Inc. All rights, title, ownership, or other interests */ -;/* in the software remain the property of Express Logic, Inc. This */ -;/* software may only be used in accordance with the corresponding */ -;/* license agreement. Any unauthorized use, duplication, transmission, */ -;/* distribution, or disclosure of this software is expressly forbidden. */ +;/**************************************************************************/ ;/* */ -;/* This Copyright notice may not be removed or modified without prior */ -;/* written consent of Express Logic, Inc. */ -;/* */ -;/* Express Logic, Inc. reserves the right to modify this software */ -;/* without notice. */ -;/* */ -;/* Express Logic, Inc. info@expresslogic.com */ -;/* 11423 West Bernardo Court http://www.expresslogic.com */ -;/* San Diego, CA 92127 */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ ;/* */ ;/**************************************************************************/ ; @@ -57,10 +45,10 @@ IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_irq_nesting_end ARM11/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ -;/* William E. Lamie, Express Logic, Inc. */ +;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ @@ -96,7 +84,7 @@ IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports/arm11/iar/src/tx_thread_irq_nesting_start.s b/ports/arm11/iar/src/tx_thread_irq_nesting_start.s index eb1977cc..cd3a8788 100644 --- a/ports/arm11/iar/src/tx_thread_irq_nesting_start.s +++ b/ports/arm11/iar/src/tx_thread_irq_nesting_start.s @@ -1,23 +1,11 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) 1996-2018 by Express Logic Inc. */ -;/* */ -;/* This software is copyrighted by and is the sole property of Express */ -;/* Logic, Inc. All rights, title, ownership, or other interests */ -;/* in the software remain the property of Express Logic, Inc. This */ -;/* software may only be used in accordance with the corresponding */ -;/* license agreement. Any unauthorized use, duplication, transmission, */ -;/* distribution, or disclosure of this software is expressly forbidden. */ +;/**************************************************************************/ ;/* */ -;/* This Copyright notice may not be removed or modified without prior */ -;/* written consent of Express Logic, Inc. */ -;/* */ -;/* Express Logic, Inc. reserves the right to modify this software */ -;/* without notice. */ -;/* */ -;/* Express Logic, Inc. info@expresslogic.com */ -;/* 11423 West Bernardo Court http://www.expresslogic.com */ -;/* San Diego, CA 92127 */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ ;/* */ ;/**************************************************************************/ ; @@ -53,10 +41,10 @@ SYS_MODE_BITS DEFINE 0x1F ; System mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_irq_nesting_start ARM11/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ -;/* William E. Lamie, Express Logic, Inc. */ +;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ @@ -89,7 +77,7 @@ SYS_MODE_BITS DEFINE 0x1F ; System mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/arm11/iar/src/tx_thread_schedule.s b/ports/arm11/iar/src/tx_thread_schedule.s index db2d2591..186d8a3f 100644 --- a/ports/arm11/iar/src/tx_thread_schedule.s +++ b/ports/arm11/iar/src/tx_thread_schedule.s @@ -1,23 +1,11 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) 1996-2018 by Express Logic Inc. */ -;/* */ -;/* This software is copyrighted by and is the sole property of Express */ -;/* Logic, Inc. All rights, title, ownership, or other interests */ -;/* in the software remain the property of Express Logic, Inc. This */ -;/* software may only be used in accordance with the corresponding */ -;/* license agreement. Any unauthorized use, duplication, transmission, */ -;/* distribution, or disclosure of this software is expressly forbidden. */ +;/**************************************************************************/ ;/* */ -;/* This Copyright notice may not be removed or modified without prior */ -;/* written consent of Express Logic, Inc. */ -;/* */ -;/* Express Logic, Inc. reserves the right to modify this software */ -;/* without notice. */ -;/* */ -;/* Express Logic, Inc. info@expresslogic.com */ -;/* 11423 West Bernardo Court http://www.expresslogic.com */ -;/* San Diego, CA 92127 */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ ;/* */ ;/**************************************************************************/ ; @@ -61,10 +49,10 @@ ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule ARM11/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ -;/* William E. Lamie, Express Logic, Inc. */ +;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ @@ -94,7 +82,7 @@ ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) diff --git a/ports/arm11/iar/src/tx_thread_stack_build.s b/ports/arm11/iar/src/tx_thread_stack_build.s index 61b3f8a1..3816952c 100644 --- a/ports/arm11/iar/src/tx_thread_stack_build.s +++ b/ports/arm11/iar/src/tx_thread_stack_build.s @@ -1,23 +1,11 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) 1996-2018 by Express Logic Inc. */ -;/* */ -;/* This software is copyrighted by and is the sole property of Express */ -;/* Logic, Inc. All rights, title, ownership, or other interests */ -;/* in the software remain the property of Express Logic, Inc. This */ -;/* software may only be used in accordance with the corresponding */ -;/* license agreement. Any unauthorized use, duplication, transmission, */ -;/* distribution, or disclosure of this software is expressly forbidden. */ +;/**************************************************************************/ ;/* */ -;/* This Copyright notice may not be removed or modified without prior */ -;/* written consent of Express Logic, Inc. */ -;/* */ -;/* Express Logic, Inc. reserves the right to modify this software */ -;/* without notice. */ -;/* */ -;/* Express Logic, Inc. info@expresslogic.com */ -;/* 11423 West Bernardo Court http://www.expresslogic.com */ -;/* San Diego, CA 92127 */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ ;/* */ ;/**************************************************************************/ ; @@ -55,10 +43,10 @@ CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints en ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build ARM11/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ -;/* William E. Lamie, Express Logic, Inc. */ +;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ @@ -87,7 +75,7 @@ CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints en ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/arm11/iar/src/tx_thread_system_return.s b/ports/arm11/iar/src/tx_thread_system_return.s index 0c6198af..8f61ef24 100644 --- a/ports/arm11/iar/src/tx_thread_system_return.s +++ b/ports/arm11/iar/src/tx_thread_system_return.s @@ -1,23 +1,11 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) 1996-2018 by Express Logic Inc. */ -;/* */ -;/* This software is copyrighted by and is the sole property of Express */ -;/* Logic, Inc. All rights, title, ownership, or other interests */ -;/* in the software remain the property of Express Logic, Inc. This */ -;/* software may only be used in accordance with the corresponding */ -;/* license agreement. Any unauthorized use, duplication, transmission, */ -;/* distribution, or disclosure of this software is expressly forbidden. */ +;/**************************************************************************/ ;/* */ -;/* This Copyright notice may not be removed or modified without prior */ -;/* written consent of Express Logic, Inc. */ -;/* */ -;/* Express Logic, Inc. reserves the right to modify this software */ -;/* without notice. */ -;/* */ -;/* Express Logic, Inc. info@expresslogic.com */ -;/* 11423 West Bernardo Court http://www.expresslogic.com */ -;/* San Diego, CA 92127 */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ ;/* */ ;/**************************************************************************/ ; @@ -60,10 +48,10 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return ARM11/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ -;/* William E. Lamie, Express Logic, Inc. */ +;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ @@ -92,7 +80,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) diff --git a/ports/arm11/iar/src/tx_thread_vectored_context_save.s b/ports/arm11/iar/src/tx_thread_vectored_context_save.s index 6bf9209c..cf8f2412 100644 --- a/ports/arm11/iar/src/tx_thread_vectored_context_save.s +++ b/ports/arm11/iar/src/tx_thread_vectored_context_save.s @@ -1,23 +1,11 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) 1996-2018 by Express Logic Inc. */ -;/* */ -;/* This software is copyrighted by and is the sole property of Express */ -;/* Logic, Inc. All rights, title, ownership, or other interests */ -;/* in the software remain the property of Express Logic, Inc. This */ -;/* software may only be used in accordance with the corresponding */ -;/* license agreement. Any unauthorized use, duplication, transmission, */ -;/* distribution, or disclosure of this software is expressly forbidden. */ +;/**************************************************************************/ ;/* */ -;/* This Copyright notice may not be removed or modified without prior */ -;/* written consent of Express Logic, Inc. */ -;/* */ -;/* Express Logic, Inc. reserves the right to modify this software */ -;/* without notice. */ -;/* */ -;/* Express Logic, Inc. info@expresslogic.com */ -;/* 11423 West Bernardo Court http://www.expresslogic.com */ -;/* San Diego, CA 92127 */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ ;/* */ ;/**************************************************************************/ ; @@ -59,10 +47,10 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_vectored_context_save ARM11/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ -;/* William E. Lamie, Express Logic, Inc. */ +;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ @@ -90,7 +78,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) diff --git a/ports/arm11/iar/src/tx_timer_interrupt.s b/ports/arm11/iar/src/tx_timer_interrupt.s index 7bb4f09f..9ed9af04 100644 --- a/ports/arm11/iar/src/tx_timer_interrupt.s +++ b/ports/arm11/iar/src/tx_timer_interrupt.s @@ -1,23 +1,13 @@ -;/**************************************************************************/ -;/* */ -;/* Copyright (c) 1996-2018 by Express Logic Inc. */ -;/* */ -;/* This software is copyrighted by and is the sole property of Express */ -;/* Logic, Inc. All rights, title, ownership, or other interests */ -;/* in the software remain the property of Express Logic, Inc. This */ -;/* software may only be used in accordance with the corresponding */ -;/* license agreement. Any unauthorized use, duplication, transmission, */ -;/* distribution, or disclosure of this software is expressly forbidden. */ -;/* */ -;/* This Copyright notice may not be removed or modified without prior */ -;/* written consent of Express Logic, Inc. */ -;/* */ -;/* Express Logic, Inc. reserves the right to modify this software */ -;/* without notice. */ -;/* */ -;/* Express Logic, Inc. info@expresslogic.com */ -;/* 11423 West Bernardo Court http://www.expresslogic.com */ -;/* San Diego, CA 92127 */ + + +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ ;/* */ ;/**************************************************************************/ ; @@ -61,10 +51,10 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt ARM11/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ -;/* William E. Lamie, Express Logic, Inc. */ +;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ @@ -95,7 +85,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) diff --git a/ports/arm9/ac5/example_build/tx_initialize_low_level.s b/ports/arm9/ac5/example_build/tx_initialize_low_level.s index 0aa438f5..ea757d18 100644 --- a/ports/arm9/ac5/example_build/tx_initialize_low_level.s +++ b/ports/arm9/ac5/example_build/tx_initialize_low_level.s @@ -119,7 +119,7 @@ __vectors ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level ARM9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -152,7 +152,7 @@ __vectors ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports/arm9/ac5/inc/tx_port.h b/ports/arm9/ac5/inc/tx_port.h index eb445bef..0d5c2ac3 100644 --- a/ports/arm9/ac5/inc/tx_port.h +++ b/ports/arm9/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h ARM9/AC5 */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -319,7 +319,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARM9/AC5 Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARM9/AC5 Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/arm9/ac5/readme_threadx.txt b/ports/arm9/ac5/readme_threadx.txt index 3fab29c2..47272b53 100644 --- a/ports/arm9/ac5/readme_threadx.txt +++ b/ports/arm9/ac5/readme_threadx.txt @@ -508,7 +508,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX 6.0.1 version for ARM9 using AC5 tools. +09-30-2020 Initial ThreadX 6.1 version for ARM9 using AC5 tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/arm9/ac5/src/tx_thread_context_restore.s b/ports/arm9/ac5/src/tx_thread_context_restore.s index 1e5f4566..c85a219d 100644 --- a/ports/arm9/ac5/src/tx_thread_context_restore.s +++ b/ports/arm9/ac5/src/tx_thread_context_restore.s @@ -61,7 +61,7 @@ SVC_MODE_BITS EQU 0x13 ; SVC mode value ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore ARM9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -93,7 +93,7 @@ SVC_MODE_BITS EQU 0x13 ; SVC mode value ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports/arm9/ac5/src/tx_thread_context_save.s b/ports/arm9/ac5/src/tx_thread_context_save.s index 07efa1a6..b8a9206a 100644 --- a/ports/arm9/ac5/src/tx_thread_context_save.s +++ b/ports/arm9/ac5/src/tx_thread_context_save.s @@ -51,7 +51,7 @@ DISABLE_INTS EQU 0x80 ; IRQ interrupts disabled ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save ARM9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ DISABLE_INTS EQU 0x80 ; IRQ interrupts disabled ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) diff --git a/ports/arm9/ac5/src/tx_thread_fiq_context_restore.s b/ports/arm9/ac5/src/tx_thread_fiq_context_restore.s index 5cd93433..af55e3a7 100644 --- a/ports/arm9/ac5/src/tx_thread_fiq_context_restore.s +++ b/ports/arm9/ac5/src/tx_thread_fiq_context_restore.s @@ -63,7 +63,7 @@ SVC_MODE_BITS EQU 0x13 ; SVC mode value ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_context_restore ARM9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -95,7 +95,7 @@ SVC_MODE_BITS EQU 0x13 ; SVC mode value ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_context_restore(VOID) diff --git a/ports/arm9/ac5/src/tx_thread_fiq_context_save.s b/ports/arm9/ac5/src/tx_thread_fiq_context_save.s index 941ae79b..fbe86984 100644 --- a/ports/arm9/ac5/src/tx_thread_fiq_context_save.s +++ b/ports/arm9/ac5/src/tx_thread_fiq_context_save.s @@ -45,7 +45,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_context_save ARM9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -76,7 +76,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ; VOID _tx_thread_fiq_context_save(VOID) diff --git a/ports/arm9/ac5/src/tx_thread_fiq_nesting_end.s b/ports/arm9/ac5/src/tx_thread_fiq_nesting_end.s index 87d9bcc1..fd96332c 100644 --- a/ports/arm9/ac5/src/tx_thread_fiq_nesting_end.s +++ b/ports/arm9/ac5/src/tx_thread_fiq_nesting_end.s @@ -45,7 +45,7 @@ FIQ_MODE_BITS EQU 0x11 ; FIQ mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_nesting_end ARM9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -84,7 +84,7 @@ FIQ_MODE_BITS EQU 0x11 ; FIQ mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_end(VOID) diff --git a/ports/arm9/ac5/src/tx_thread_fiq_nesting_start.s b/ports/arm9/ac5/src/tx_thread_fiq_nesting_start.s index f06e9ec2..f201437e 100644 --- a/ports/arm9/ac5/src/tx_thread_fiq_nesting_start.s +++ b/ports/arm9/ac5/src/tx_thread_fiq_nesting_start.s @@ -41,7 +41,7 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_nesting_start ARM9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/arm9/ac5/src/tx_thread_interrupt_control.s b/ports/arm9/ac5/src/tx_thread_interrupt_control.s index c21d687d..1d380c5e 100644 --- a/ports/arm9/ac5/src/tx_thread_interrupt_control.s +++ b/ports/arm9/ac5/src/tx_thread_interrupt_control.s @@ -42,7 +42,7 @@ INT_MASK EQU 0x80 ; Interrupt bit mask ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control ARM9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ INT_MASK EQU 0x80 ; Interrupt bit mask ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/arm9/ac5/src/tx_thread_interrupt_disable.s b/ports/arm9/ac5/src/tx_thread_interrupt_disable.s index efe72d25..efdb56f7 100644 --- a/ports/arm9/ac5/src/tx_thread_interrupt_disable.s +++ b/ports/arm9/ac5/src/tx_thread_interrupt_disable.s @@ -42,7 +42,7 @@ DISABLE_INTS EQU 0x80 ; IRQ interrupts disabled ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_disable ARM9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ DISABLE_INTS EQU 0x80 ; IRQ interrupts disabled ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(void) diff --git a/ports/arm9/ac5/src/tx_thread_interrupt_restore.s b/ports/arm9/ac5/src/tx_thread_interrupt_restore.s index eac71e91..d23e338f 100644 --- a/ports/arm9/ac5/src/tx_thread_interrupt_restore.s +++ b/ports/arm9/ac5/src/tx_thread_interrupt_restore.s @@ -35,7 +35,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore ARM9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -65,7 +65,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/arm9/ac5/src/tx_thread_irq_nesting_end.s b/ports/arm9/ac5/src/tx_thread_irq_nesting_end.s index a1bd87ed..36ec1e35 100644 --- a/ports/arm9/ac5/src/tx_thread_irq_nesting_end.s +++ b/ports/arm9/ac5/src/tx_thread_irq_nesting_end.s @@ -45,7 +45,7 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_irq_nesting_end ARM9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -84,7 +84,7 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports/arm9/ac5/src/tx_thread_irq_nesting_start.s b/ports/arm9/ac5/src/tx_thread_irq_nesting_start.s index 1fc8b2dd..503a6323 100644 --- a/ports/arm9/ac5/src/tx_thread_irq_nesting_start.s +++ b/ports/arm9/ac5/src/tx_thread_irq_nesting_start.s @@ -41,7 +41,7 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_irq_nesting_start ARM9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/arm9/ac5/src/tx_thread_schedule.s b/ports/arm9/ac5/src/tx_thread_schedule.s index fa1eef18..f2c5879d 100644 --- a/ports/arm9/ac5/src/tx_thread_schedule.s +++ b/ports/arm9/ac5/src/tx_thread_schedule.s @@ -53,7 +53,7 @@ ENABLE_INTS EQU 0x80 ; IRQ Interrupts enabled mask ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule ARM9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -86,7 +86,7 @@ ENABLE_INTS EQU 0x80 ; IRQ Interrupts enabled mask ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) diff --git a/ports/arm9/ac5/src/tx_thread_stack_build.s b/ports/arm9/ac5/src/tx_thread_stack_build.s index 2da5649c..936bb94a 100644 --- a/ports/arm9/ac5/src/tx_thread_stack_build.s +++ b/ports/arm9/ac5/src/tx_thread_stack_build.s @@ -44,7 +44,7 @@ CPSR_MASK EQU 0x9F ; Mask initial CPSR, IRQ ints en ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build ARM9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -76,7 +76,7 @@ CPSR_MASK EQU 0x9F ; Mask initial CPSR, IRQ ints en ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/arm9/ac5/src/tx_thread_system_return.s b/ports/arm9/ac5/src/tx_thread_system_return.s index 697085a3..ecc053ed 100644 --- a/ports/arm9/ac5/src/tx_thread_system_return.s +++ b/ports/arm9/ac5/src/tx_thread_system_return.s @@ -52,7 +52,7 @@ DISABLE_INTS EQU 0x80 ; IRQ interrupts disabled ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return ARM9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -84,7 +84,7 @@ DISABLE_INTS EQU 0x80 ; IRQ interrupts disabled ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) diff --git a/ports/arm9/ac5/src/tx_thread_vectored_context_save.s b/ports/arm9/ac5/src/tx_thread_vectored_context_save.s index c5e1e9f8..de563d0f 100644 --- a/ports/arm9/ac5/src/tx_thread_vectored_context_save.s +++ b/ports/arm9/ac5/src/tx_thread_vectored_context_save.s @@ -51,7 +51,7 @@ DISABLE_INTS EQU 0x80 ; IRQ interrupts disabled ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_vectored_context_save ARM9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ DISABLE_INTS EQU 0x80 ; IRQ interrupts disabled ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) diff --git a/ports/arm9/ac5/src/tx_timer_interrupt.s b/ports/arm9/ac5/src/tx_timer_interrupt.s index 7997d994..1664f840 100644 --- a/ports/arm9/ac5/src/tx_timer_interrupt.s +++ b/ports/arm9/ac5/src/tx_timer_interrupt.s @@ -50,7 +50,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt ARM9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -84,7 +84,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) diff --git a/ports/arm9/gnu/example_build/tx_initialize_low_level.S b/ports/arm9/gnu/example_build/tx_initialize_low_level.S index 00e46e0c..6374fd32 100644 --- a/ports/arm9/gnu/example_build/tx_initialize_low_level.S +++ b/ports/arm9/gnu/example_build/tx_initialize_low_level.S @@ -78,7 +78,7 @@ $_tx_initialize_low_level: @/* FUNCTION RELEASE */ @/* */ @/* _tx_initialize_low_level ARM9/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -111,7 +111,7 @@ $_tx_initialize_low_level: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) diff --git a/ports/arm9/gnu/inc/tx_port.h b/ports/arm9/gnu/inc/tx_port.h index a255e792..3535f75f 100644 --- a/ports/arm9/gnu/inc/tx_port.h +++ b/ports/arm9/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h ARM9/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -306,7 +306,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARM9/GNU Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARM9/GNU Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/arm9/gnu/readme_threadx.txt b/ports/arm9/gnu/readme_threadx.txt index 262760e6..41572f18 100644 --- a/ports/arm9/gnu/readme_threadx.txt +++ b/ports/arm9/gnu/readme_threadx.txt @@ -486,7 +486,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX 6.0.1 version for ARM9 using GNU tools. +09-30-2020 Initial ThreadX 6.1 version for ARM9 using GNU tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/arm9/gnu/src/tx_thread_context_restore.S b/ports/arm9/gnu/src/tx_thread_context_restore.S index a6876848..325ec259 100644 --- a/ports/arm9/gnu/src/tx_thread_context_restore.S +++ b/ports/arm9/gnu/src/tx_thread_context_restore.S @@ -60,7 +60,7 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_restore ARM9/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -92,7 +92,7 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) diff --git a/ports/arm9/gnu/src/tx_thread_context_save.S b/ports/arm9/gnu/src/tx_thread_context_save.S index a1552e86..9ec36b9b 100644 --- a/ports/arm9/gnu/src/tx_thread_context_save.S +++ b/ports/arm9/gnu/src/tx_thread_context_save.S @@ -53,7 +53,7 @@ DISABLE_INTS = 0x80 @ IRQ interrupts disabled @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_save ARM9/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -84,7 +84,7 @@ DISABLE_INTS = 0x80 @ IRQ interrupts disabled @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) diff --git a/ports/arm9/gnu/src/tx_thread_fiq_context_restore.S b/ports/arm9/gnu/src/tx_thread_fiq_context_restore.S index 81e3299b..06d7723f 100644 --- a/ports/arm9/gnu/src/tx_thread_fiq_context_restore.S +++ b/ports/arm9/gnu/src/tx_thread_fiq_context_restore.S @@ -61,7 +61,7 @@ SVC_MODE_BITS = 0x13 @ SVC mode value @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_context_restore ARM9/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -93,7 +93,7 @@ SVC_MODE_BITS = 0x13 @ SVC mode value @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_context_restore(VOID) diff --git a/ports/arm9/gnu/src/tx_thread_fiq_context_save.S b/ports/arm9/gnu/src/tx_thread_fiq_context_save.S index 88ad7e79..e3a033ec 100644 --- a/ports/arm9/gnu/src/tx_thread_fiq_context_save.S +++ b/ports/arm9/gnu/src/tx_thread_fiq_context_save.S @@ -47,7 +47,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_context_save ARM9/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -78,7 +78,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @ VOID _tx_thread_fiq_context_save(VOID) diff --git a/ports/arm9/gnu/src/tx_thread_fiq_nesting_end.S b/ports/arm9/gnu/src/tx_thread_fiq_nesting_end.S index 9705cca4..dffe020a 100644 --- a/ports/arm9/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/arm9/gnu/src/tx_thread_fiq_nesting_end.S @@ -50,7 +50,7 @@ FIQ_MODE_BITS = 0x11 @ FIQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_nesting_end ARM9/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -89,7 +89,7 @@ FIQ_MODE_BITS = 0x11 @ FIQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_end(VOID) diff --git a/ports/arm9/gnu/src/tx_thread_fiq_nesting_start.S b/ports/arm9/gnu/src/tx_thread_fiq_nesting_start.S index fd498616..ced2cfff 100644 --- a/ports/arm9/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/arm9/gnu/src/tx_thread_fiq_nesting_start.S @@ -46,7 +46,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_nesting_start ARM9/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/arm9/gnu/src/tx_thread_interrupt_control.S b/ports/arm9/gnu/src/tx_thread_interrupt_control.S index ca95b8ac..c8dfb2e3 100644 --- a/ports/arm9/gnu/src/tx_thread_interrupt_control.S +++ b/ports/arm9/gnu/src/tx_thread_interrupt_control.S @@ -56,7 +56,7 @@ $_tx_thread_interrupt_control: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_control ARM9/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -86,7 +86,7 @@ $_tx_thread_interrupt_control: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/arm9/gnu/src/tx_thread_interrupt_disable.S b/ports/arm9/gnu/src/tx_thread_interrupt_disable.S index 76570a20..be4541b9 100644 --- a/ports/arm9/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/arm9/gnu/src/tx_thread_interrupt_disable.S @@ -60,7 +60,7 @@ $_tx_thread_interrupt_disable: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_disable ARM9/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -89,7 +89,7 @@ $_tx_thread_interrupt_disable: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_disable(void) diff --git a/ports/arm9/gnu/src/tx_thread_interrupt_restore.S b/ports/arm9/gnu/src/tx_thread_interrupt_restore.S index 65e01e32..6665fde2 100644 --- a/ports/arm9/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/arm9/gnu/src/tx_thread_interrupt_restore.S @@ -53,7 +53,7 @@ $_tx_thread_interrupt_restore: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_restore ARM9/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -83,7 +83,7 @@ $_tx_thread_interrupt_restore: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/arm9/gnu/src/tx_thread_irq_nesting_end.S b/ports/arm9/gnu/src/tx_thread_irq_nesting_end.S index 8ee9b216..7d6c2d7b 100644 --- a/ports/arm9/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/arm9/gnu/src/tx_thread_irq_nesting_end.S @@ -50,7 +50,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_irq_nesting_end ARM9/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -89,7 +89,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports/arm9/gnu/src/tx_thread_irq_nesting_start.S b/ports/arm9/gnu/src/tx_thread_irq_nesting_start.S index 7174dc11..bad43158 100644 --- a/ports/arm9/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/arm9/gnu/src/tx_thread_irq_nesting_start.S @@ -46,7 +46,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_irq_nesting_start ARM9/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/arm9/gnu/src/tx_thread_schedule.S b/ports/arm9/gnu/src/tx_thread_schedule.S index fde52ec5..726943e8 100644 --- a/ports/arm9/gnu/src/tx_thread_schedule.S +++ b/ports/arm9/gnu/src/tx_thread_schedule.S @@ -68,7 +68,7 @@ $_tx_thread_schedule: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule ARM9/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -101,7 +101,7 @@ $_tx_thread_schedule: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) diff --git a/ports/arm9/gnu/src/tx_thread_stack_build.S b/ports/arm9/gnu/src/tx_thread_stack_build.S index 7d6f47bb..7f691a42 100644 --- a/ports/arm9/gnu/src/tx_thread_stack_build.S +++ b/ports/arm9/gnu/src/tx_thread_stack_build.S @@ -64,7 +64,7 @@ $_tx_thread_stack_build: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_stack_build ARM9/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -96,7 +96,7 @@ $_tx_thread_stack_build: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/arm9/gnu/src/tx_thread_system_return.S b/ports/arm9/gnu/src/tx_thread_system_return.S index aa1599a6..6e442ad8 100644 --- a/ports/arm9/gnu/src/tx_thread_system_return.S +++ b/ports/arm9/gnu/src/tx_thread_system_return.S @@ -70,7 +70,7 @@ $_tx_thread_system_return: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_system_return ARM9/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -102,7 +102,7 @@ $_tx_thread_system_return: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_system_return(VOID) diff --git a/ports/arm9/gnu/src/tx_thread_vectored_context_save.S b/ports/arm9/gnu/src/tx_thread_vectored_context_save.S index f69abcd9..76db3030 100644 --- a/ports/arm9/gnu/src/tx_thread_vectored_context_save.S +++ b/ports/arm9/gnu/src/tx_thread_vectored_context_save.S @@ -54,7 +54,7 @@ DISABLE_INTS = 0x80 @ IRQ interrupts disabled @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_vectored_context_save ARM9/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -85,7 +85,7 @@ DISABLE_INTS = 0x80 @ IRQ interrupts disabled @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_vectored_context_save(VOID) diff --git a/ports/arm9/gnu/src/tx_timer_interrupt.S b/ports/arm9/gnu/src/tx_timer_interrupt.S index 7871d1bc..a44f9b10 100644 --- a/ports/arm9/gnu/src/tx_timer_interrupt.S +++ b/ports/arm9/gnu/src/tx_timer_interrupt.S @@ -71,7 +71,7 @@ $_tx_timer_interrupt: @/* FUNCTION RELEASE */ @/* */ @/* _tx_timer_interrupt ARM9/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -105,7 +105,7 @@ $_tx_timer_interrupt: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) diff --git a/ports/arm9/iar/example_build/tx_initialize_low_level.s b/ports/arm9/iar/example_build/tx_initialize_low_level.s index 36bcc6a3..9af62bff 100644 --- a/ports/arm9/iar/example_build/tx_initialize_low_level.s +++ b/ports/arm9/iar/example_build/tx_initialize_low_level.s @@ -81,7 +81,7 @@ __tx_free_memory_start ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level ARM9/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -114,7 +114,7 @@ __tx_free_memory_start ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports/arm9/iar/inc/tx_port.h b/ports/arm9/iar/inc/tx_port.h index ed501c4b..2c14c396 100644 --- a/ports/arm9/iar/inc/tx_port.h +++ b/ports/arm9/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h ARM9/IAR */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -372,7 +372,7 @@ void _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARM9/IAR Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARM9/IAR Version 6.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/arm9/iar/readme_threadx.txt b/ports/arm9/iar/readme_threadx.txt index 67ea7d01..dd7b087a 100644 --- a/ports/arm9/iar/readme_threadx.txt +++ b/ports/arm9/iar/readme_threadx.txt @@ -518,7 +518,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX version 6.0.1 for ARM9 using IAR's ARM tools. +09-30-2020 Initial ThreadX version 6.1 for ARM9 using IAR's ARM tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/arm9/iar/src/tx_thread_context_restore.s b/ports/arm9/iar/src/tx_thread_context_restore.s index 8f8f4047..d118a511 100644 --- a/ports/arm9/iar/src/tx_thread_context_restore.s +++ b/ports/arm9/iar/src/tx_thread_context_restore.s @@ -56,7 +56,7 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore ARM9/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -88,7 +88,7 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports/arm9/iar/src/tx_thread_context_save.s b/ports/arm9/iar/src/tx_thread_context_save.s index 8d39c7f0..ad99f00d 100644 --- a/ports/arm9/iar/src/tx_thread_context_save.s +++ b/ports/arm9/iar/src/tx_thread_context_save.s @@ -50,7 +50,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save ARM9/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -81,7 +81,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) diff --git a/ports/arm9/iar/src/tx_thread_fiq_context_restore.s b/ports/arm9/iar/src/tx_thread_fiq_context_restore.s index 3d9b735f..cee2a251 100644 --- a/ports/arm9/iar/src/tx_thread_fiq_context_restore.s +++ b/ports/arm9/iar/src/tx_thread_fiq_context_restore.s @@ -58,7 +58,7 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_context_restore ARM9/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -90,7 +90,7 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_context_restore(VOID) diff --git a/ports/arm9/iar/src/tx_thread_fiq_context_save.s b/ports/arm9/iar/src/tx_thread_fiq_context_save.s index 3c65cda2..ae9dd1a7 100644 --- a/ports/arm9/iar/src/tx_thread_fiq_context_save.s +++ b/ports/arm9/iar/src/tx_thread_fiq_context_save.s @@ -42,7 +42,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_context_save ARM9/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -73,7 +73,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ; VOID _tx_thread_fiq_context_save(VOID) diff --git a/ports/arm9/iar/src/tx_thread_fiq_nesting_end.s b/ports/arm9/iar/src/tx_thread_fiq_nesting_end.s index 673c912a..cca6e6f1 100644 --- a/ports/arm9/iar/src/tx_thread_fiq_nesting_end.s +++ b/ports/arm9/iar/src/tx_thread_fiq_nesting_end.s @@ -44,7 +44,7 @@ FIQ_MODE_BITS DEFINE 0x11 ; FIQ mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_nesting_end ARM9/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -83,7 +83,7 @@ FIQ_MODE_BITS DEFINE 0x11 ; FIQ mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_end(VOID) diff --git a/ports/arm9/iar/src/tx_thread_fiq_nesting_start.s b/ports/arm9/iar/src/tx_thread_fiq_nesting_start.s index b4bd8c67..18416413 100644 --- a/ports/arm9/iar/src/tx_thread_fiq_nesting_start.s +++ b/ports/arm9/iar/src/tx_thread_fiq_nesting_start.s @@ -41,7 +41,7 @@ SYS_MODE_BITS DEFINE 0x1F ; System mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_nesting_start ARM9/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ SYS_MODE_BITS DEFINE 0x1F ; System mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/arm9/iar/src/tx_thread_interrupt_control.s b/ports/arm9/iar/src/tx_thread_interrupt_control.s index 6c02c8e3..0d14e383 100644 --- a/ports/arm9/iar/src/tx_thread_interrupt_control.s +++ b/ports/arm9/iar/src/tx_thread_interrupt_control.s @@ -41,7 +41,7 @@ INT_MASK DEFINE 0x80 ; Interrupt bit mask ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control ARM9/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ INT_MASK DEFINE 0x80 ; Interrupt bit mask ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/arm9/iar/src/tx_thread_interrupt_disable.s b/ports/arm9/iar/src/tx_thread_interrupt_disable.s index 4b36594c..527a94cb 100644 --- a/ports/arm9/iar/src/tx_thread_interrupt_disable.s +++ b/ports/arm9/iar/src/tx_thread_interrupt_disable.s @@ -42,7 +42,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_disable ARM9/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports/arm9/iar/src/tx_thread_interrupt_restore.s b/ports/arm9/iar/src/tx_thread_interrupt_restore.s index 0a929e6d..21cb0515 100644 --- a/ports/arm9/iar/src/tx_thread_interrupt_restore.s +++ b/ports/arm9/iar/src/tx_thread_interrupt_restore.s @@ -34,7 +34,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore ARM9/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -64,7 +64,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;void _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/arm9/iar/src/tx_thread_irq_nesting_end.s b/ports/arm9/iar/src/tx_thread_irq_nesting_end.s index 93db4900..1bb1689e 100644 --- a/ports/arm9/iar/src/tx_thread_irq_nesting_end.s +++ b/ports/arm9/iar/src/tx_thread_irq_nesting_end.s @@ -45,7 +45,7 @@ IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_irq_nesting_end ARM9/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -84,7 +84,7 @@ IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports/arm9/iar/src/tx_thread_irq_nesting_start.s b/ports/arm9/iar/src/tx_thread_irq_nesting_start.s index 300f7838..c0cf1e4b 100644 --- a/ports/arm9/iar/src/tx_thread_irq_nesting_start.s +++ b/ports/arm9/iar/src/tx_thread_irq_nesting_start.s @@ -41,7 +41,7 @@ SYS_MODE_BITS DEFINE 0x1F ; System mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_irq_nesting_start ARM9/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ SYS_MODE_BITS DEFINE 0x1F ; System mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/arm9/iar/src/tx_thread_schedule.s b/ports/arm9/iar/src/tx_thread_schedule.s index 09e832e1..d6bd3edf 100644 --- a/ports/arm9/iar/src/tx_thread_schedule.s +++ b/ports/arm9/iar/src/tx_thread_schedule.s @@ -49,7 +49,7 @@ ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule ARM9/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) diff --git a/ports/arm9/iar/src/tx_thread_stack_build.s b/ports/arm9/iar/src/tx_thread_stack_build.s index fcf39a3f..8a1a421c 100644 --- a/ports/arm9/iar/src/tx_thread_stack_build.s +++ b/ports/arm9/iar/src/tx_thread_stack_build.s @@ -43,7 +43,7 @@ CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints en ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build ARM9/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -75,7 +75,7 @@ CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints en ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/arm9/iar/src/tx_thread_system_return.s b/ports/arm9/iar/src/tx_thread_system_return.s index 5212168d..9ecff88e 100644 --- a/ports/arm9/iar/src/tx_thread_system_return.s +++ b/ports/arm9/iar/src/tx_thread_system_return.s @@ -48,7 +48,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return ARM9/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -80,7 +80,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) diff --git a/ports/arm9/iar/src/tx_thread_vectored_context_save.s b/ports/arm9/iar/src/tx_thread_vectored_context_save.s index cf11f910..e7bb8363 100644 --- a/ports/arm9/iar/src/tx_thread_vectored_context_save.s +++ b/ports/arm9/iar/src/tx_thread_vectored_context_save.s @@ -47,7 +47,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_vectored_context_save ARM9/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -78,7 +78,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) diff --git a/ports/arm9/iar/src/tx_timer_interrupt.s b/ports/arm9/iar/src/tx_timer_interrupt.s index 1a508c6a..70987063 100644 --- a/ports/arm9/iar/src/tx_timer_interrupt.s +++ b/ports/arm9/iar/src/tx_timer_interrupt.s @@ -49,7 +49,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt ARM9/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -83,7 +83,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) diff --git a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/tx_initialize_low_level.asm b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/tx_initialize_low_level.asm index cdc14f20..6cffa707 100644 --- a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/tx_initialize_low_level.asm +++ b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/tx_initialize_low_level.asm @@ -117,7 +117,7 @@ TX_INTERRUPT_EXIT .macro ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level C667x/TI */ -;/* 6.0 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -150,7 +150,7 @@ TX_INTERRUPT_EXIT .macro ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/tx_initialize_low_level.asm b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/tx_initialize_low_level.asm index de902350..7257b91a 100644 --- a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/tx_initialize_low_level.asm +++ b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/tx_initialize_low_level.asm @@ -117,7 +117,7 @@ TX_INTERRUPT_EXIT .macro ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level C667x+/TI */ -;/* 6.0 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -150,7 +150,7 @@ TX_INTERRUPT_EXIT .macro ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports/c667x/ccs/inc/tx_port.h b/ports/c667x/ccs/inc/tx_port.h index a5c8defb..03feeac8 100644 --- a/ports/c667x/ccs/inc/tx_port.h +++ b/ports/c667x/ccs/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h C667x/TI */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -264,7 +264,7 @@ unsigned int _tx_thread_interrupt_control(unsigned int); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX C667x/TI Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX C667x/TI Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/c667x/ccs/readme_threadx.txt b/ports/c667x/ccs/readme_threadx.txt index d78707c7..c5cffbd4 100644 --- a/ports/c667x/ccs/readme_threadx.txt +++ b/ports/c667x/ccs/readme_threadx.txt @@ -238,7 +238,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX 6.0.1 version for TMS320C667x using TI Code Composer tools. +09-30-2020 Initial ThreadX 6.1 version for TMS320C667x using TI Code Composer tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/c667x/ccs/src/tx_thread_context_restore.asm b/ports/c667x/ccs/src/tx_thread_context_restore.asm index 58861b58..7bf3a215 100644 --- a/ports/c667x/ccs/src/tx_thread_context_restore.asm +++ b/ports/c667x/ccs/src/tx_thread_context_restore.asm @@ -49,7 +49,7 @@ SP .set B15 ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore C667x/TI */ -;/* 6.0 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -81,7 +81,7 @@ SP .set B15 ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports/c667x/ccs/src/tx_thread_context_save.asm b/ports/c667x/ccs/src/tx_thread_context_save.asm index ea455f8f..e03334dc 100644 --- a/ports/c667x/ccs/src/tx_thread_context_save.asm +++ b/ports/c667x/ccs/src/tx_thread_context_save.asm @@ -45,7 +45,7 @@ SP .set B15 ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save C667x/TI */ -;/* 6.0 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -76,7 +76,7 @@ SP .set B15 ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) diff --git a/ports/c667x/ccs/src/tx_thread_interrupt_control.asm b/ports/c667x/ccs/src/tx_thread_interrupt_control.asm index ac7d467d..cce68b0e 100644 --- a/ports/c667x/ccs/src/tx_thread_interrupt_control.asm +++ b/ports/c667x/ccs/src/tx_thread_interrupt_control.asm @@ -40,7 +40,7 @@ SP .set B15 ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control C667x/TI */ -;/* 6.0 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -70,7 +70,7 @@ SP .set B15 ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/c667x/ccs/src/tx_thread_schedule.asm b/ports/c667x/ccs/src/tx_thread_schedule.asm index 57da66d1..a5f29b04 100644 --- a/ports/c667x/ccs/src/tx_thread_schedule.asm +++ b/ports/c667x/ccs/src/tx_thread_schedule.asm @@ -46,7 +46,7 @@ SP .set B15 ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule C667x/TI */ -;/* 6.0 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -79,7 +79,7 @@ SP .set B15 ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) diff --git a/ports/c667x/ccs/src/tx_thread_stack_build.asm b/ports/c667x/ccs/src/tx_thread_stack_build.asm index 8e6c0559..cc70981a 100644 --- a/ports/c667x/ccs/src/tx_thread_stack_build.asm +++ b/ports/c667x/ccs/src/tx_thread_stack_build.asm @@ -40,7 +40,7 @@ ADDRESS_MSK .set 0xFFFFFFF0 ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build C667x/TI */ -;/* 6.0 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ ADDRESS_MSK .set 0xFFFFFFF0 ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/c667x/ccs/src/tx_thread_system_return.asm b/ports/c667x/ccs/src/tx_thread_system_return.asm index 67de8e21..4a47e262 100644 --- a/ports/c667x/ccs/src/tx_thread_system_return.asm +++ b/ports/c667x/ccs/src/tx_thread_system_return.asm @@ -46,7 +46,7 @@ SP .set B15 ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return C667x/TI */ -;/* 6.0 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -78,7 +78,7 @@ SP .set B15 ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) diff --git a/ports/c667x/ccs/src/tx_timer_interrupt.asm b/ports/c667x/ccs/src/tx_timer_interrupt.asm index b6a2f0a1..761f9b5c 100644 --- a/ports/c667x/ccs/src/tx_timer_interrupt.asm +++ b/ports/c667x/ccs/src/tx_timer_interrupt.asm @@ -54,7 +54,7 @@ SP .set B15 ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt C667x/TI */ -;/* 6.0 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -90,7 +90,7 @@ SP .set B15 ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_a15/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_a15/ac6/example_build/sample_threadx/tx_initialize_low_level.S index f8196b27..7ea1cf8c 100644 --- a/ports/cortex_a15/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports/cortex_a15/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -75,7 +75,7 @@ $_tx_initialize_low_level: @/* FUNCTION RELEASE */ @/* */ @/* _tx_initialize_low_level Cortex-A15/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -108,7 +108,7 @@ $_tx_initialize_low_level: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_a15/ac6/inc/tx_port.h b/ports/cortex_a15/ac6/inc/tx_port.h index 709e6151..59659cf0 100644 --- a/ports/cortex_a15/ac6/inc/tx_port.h +++ b/ports/cortex_a15/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A15/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -313,7 +313,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A15/AC6 Version 6.0.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A15/AC6 Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a15/ac6/readme_threadx.txt b/ports/cortex_a15/ac6/readme_threadx.txt index 3504587d..27a3c8f4 100644 --- a/ports/cortex_a15/ac6/readme_threadx.txt +++ b/ports/cortex_a15/ac6/readme_threadx.txt @@ -332,7 +332,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A15 using AC6 tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-A15 using AC6 tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_a15/ac6/src/tx_thread_context_restore.S b/ports/cortex_a15/ac6/src/tx_thread_context_restore.S index 8244cb9e..f95d19d6 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_a15/ac6/src/tx_thread_context_restore.S @@ -59,7 +59,7 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_restore Cortex-A15/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -91,7 +91,7 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_a15/ac6/src/tx_thread_context_save.S b/ports/cortex_a15/ac6/src/tx_thread_context_save.S index 2592ab22..2901bbfb 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_a15/ac6/src/tx_thread_context_save.S @@ -47,7 +47,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_save Cortex-A15/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -78,7 +78,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_a15/ac6/src/tx_thread_fiq_context_restore.S b/ports/cortex_a15/ac6/src/tx_thread_fiq_context_restore.S index fb1b9069..ffccab5d 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_a15/ac6/src/tx_thread_fiq_context_restore.S @@ -58,7 +58,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_context_restore Cortex-A15/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -90,7 +90,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_context_restore(VOID) diff --git a/ports/cortex_a15/ac6/src/tx_thread_fiq_context_save.S b/ports/cortex_a15/ac6/src/tx_thread_fiq_context_save.S index 435b9d6c..8cd749b0 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_a15/ac6/src/tx_thread_fiq_context_save.S @@ -46,7 +46,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_context_save Cortex-A15/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @ VOID _tx_thread_fiq_context_save(VOID) diff --git a/ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_end.S index 2e904342..2cf49fc3 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_end.S @@ -50,7 +50,7 @@ FIQ_MODE_BITS = 0x11 @ FIQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_nesting_end Cortex-A15/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -89,7 +89,7 @@ FIQ_MODE_BITS = 0x11 @ FIQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_end(VOID) diff --git a/ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_start.S index 093fdbd1..c26e173f 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_start.S @@ -46,7 +46,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_nesting_start Cortex-A15/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/cortex_a15/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a15/ac6/src/tx_thread_interrupt_control.S index a2eaab23..6e7b9dee 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a15/ac6/src/tx_thread_interrupt_control.S @@ -56,7 +56,7 @@ $_tx_thread_interrupt_control: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_control Cortex-A15/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -86,7 +86,7 @@ $_tx_thread_interrupt_control: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a15/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a15/ac6/src/tx_thread_interrupt_disable.S index 2e1b80b3..f0833f65 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a15/ac6/src/tx_thread_interrupt_disable.S @@ -53,7 +53,7 @@ $_tx_thread_interrupt_disable: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_disable Cortex-A15/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ $_tx_thread_interrupt_disable: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_disable(void) diff --git a/ports/cortex_a15/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a15/ac6/src/tx_thread_interrupt_restore.S index e03d69e7..0f0a4b06 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a15/ac6/src/tx_thread_interrupt_restore.S @@ -53,7 +53,7 @@ $_tx_thread_interrupt_restore: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_restore Cortex-A15/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -83,7 +83,7 @@ $_tx_thread_interrupt_restore: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a15/ac6/src/tx_thread_irq_nesting_end.S b/ports/cortex_a15/ac6/src/tx_thread_irq_nesting_end.S index a1c16c1a..40a9c386 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a15/ac6/src/tx_thread_irq_nesting_end.S @@ -50,7 +50,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_irq_nesting_end Cortex-A15/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -89,7 +89,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports/cortex_a15/ac6/src/tx_thread_irq_nesting_start.S b/ports/cortex_a15/ac6/src/tx_thread_irq_nesting_start.S index 34c18567..9a6d4370 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a15/ac6/src/tx_thread_irq_nesting_start.S @@ -46,7 +46,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_irq_nesting_start Cortex-A15/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_a15/ac6/src/tx_thread_schedule.S b/ports/cortex_a15/ac6/src/tx_thread_schedule.S index 4249d532..1d9d03fc 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a15/ac6/src/tx_thread_schedule.S @@ -61,7 +61,7 @@ $_tx_thread_schedule: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule Cortex-A15/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -94,7 +94,7 @@ $_tx_thread_schedule: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_a15/ac6/src/tx_thread_stack_build.S b/ports/cortex_a15/ac6/src/tx_thread_stack_build.S index c09745df..df648838 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_a15/ac6/src/tx_thread_stack_build.S @@ -64,7 +64,7 @@ $_tx_thread_stack_build: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_stack_build Cortex-A15/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -96,7 +96,7 @@ $_tx_thread_stack_build: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_a15/ac6/src/tx_thread_system_return.S b/ports/cortex_a15/ac6/src/tx_thread_system_return.S index 7cb9450b..c7a765ff 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a15/ac6/src/tx_thread_system_return.S @@ -63,7 +63,7 @@ $_tx_thread_system_return: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_system_return Cortex-A15/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -95,7 +95,7 @@ $_tx_thread_system_return: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_a15/ac6/src/tx_thread_vectored_context_save.S b/ports/cortex_a15/ac6/src/tx_thread_vectored_context_save.S index 91a9c7b8..defb6f28 100644 --- a/ports/cortex_a15/ac6/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_a15/ac6/src/tx_thread_vectored_context_save.S @@ -46,7 +46,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_vectored_context_save Cortex-A15/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_vectored_context_save(VOID) diff --git a/ports/cortex_a15/ac6/src/tx_timer_interrupt.S b/ports/cortex_a15/ac6/src/tx_timer_interrupt.S index 41a7a83b..73285451 100644 --- a/ports/cortex_a15/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_a15/ac6/src/tx_timer_interrupt.S @@ -71,7 +71,7 @@ $_tx_timer_interrupt: @/* FUNCTION RELEASE */ @/* */ @/* _tx_timer_interrupt Cortex-A15/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -105,7 +105,7 @@ $_tx_timer_interrupt: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_a15/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_a15/gnu/example_build/tx_initialize_low_level.S index d441ec20..bf53179c 100644 --- a/ports/cortex_a15/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_a15/gnu/example_build/tx_initialize_low_level.S @@ -78,7 +78,7 @@ $_tx_initialize_low_level: @/* FUNCTION RELEASE */ @/* */ @/* _tx_initialize_low_level Cortex-A15/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -111,7 +111,7 @@ $_tx_initialize_low_level: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_a15/gnu/inc/tx_port.h b/ports/cortex_a15/gnu/inc/tx_port.h index fd663938..507f69ed 100644 --- a/ports/cortex_a15/gnu/inc/tx_port.h +++ b/ports/cortex_a15/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A15/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -313,7 +313,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A15/GNU Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A15/GNU Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a15/gnu/readme_threadx.txt b/ports/cortex_a15/gnu/readme_threadx.txt index 45fabd8e..b060b1b8 100644 --- a/ports/cortex_a15/gnu/readme_threadx.txt +++ b/ports/cortex_a15/gnu/readme_threadx.txt @@ -503,7 +503,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A15 using GNU tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-A15 using GNU tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_a15/gnu/src/tx_thread_context_restore.S b/ports/cortex_a15/gnu/src/tx_thread_context_restore.S index d491780a..e9a1a3d5 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a15/gnu/src/tx_thread_context_restore.S @@ -60,7 +60,7 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_restore Cortex-A15/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -92,7 +92,7 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_a15/gnu/src/tx_thread_context_save.S b/ports/cortex_a15/gnu/src/tx_thread_context_save.S index c62862cf..ba052e3b 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a15/gnu/src/tx_thread_context_save.S @@ -48,7 +48,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_save Cortex-A15/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -79,7 +79,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_a15/gnu/src/tx_thread_fiq_context_restore.S b/ports/cortex_a15/gnu/src/tx_thread_fiq_context_restore.S index 7a49178d..2f1a43a9 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_a15/gnu/src/tx_thread_fiq_context_restore.S @@ -59,7 +59,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_context_restore Cortex-A15/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -91,7 +91,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_context_restore(VOID) diff --git a/ports/cortex_a15/gnu/src/tx_thread_fiq_context_save.S b/ports/cortex_a15/gnu/src/tx_thread_fiq_context_save.S index 2ce9dc46..1b2445cb 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_a15/gnu/src/tx_thread_fiq_context_save.S @@ -47,7 +47,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_context_save Cortex-A15/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -78,7 +78,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @ VOID _tx_thread_fiq_context_save(VOID) diff --git a/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_end.S index d1f31183..7ddb0f7f 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_end.S @@ -50,7 +50,7 @@ FIQ_MODE_BITS = 0x11 @ FIQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_nesting_end Cortex-A15/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -89,7 +89,7 @@ FIQ_MODE_BITS = 0x11 @ FIQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_end(VOID) diff --git a/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_start.S index 8f6c34bf..a2f0471e 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_start.S @@ -46,7 +46,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_nesting_start Cortex-A15/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/cortex_a15/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a15/gnu/src/tx_thread_interrupt_control.S index 7ca32c7b..bb919207 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a15/gnu/src/tx_thread_interrupt_control.S @@ -56,7 +56,7 @@ $_tx_thread_interrupt_control: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_control Cortex-A15/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -86,7 +86,7 @@ $_tx_thread_interrupt_control: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a15/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a15/gnu/src/tx_thread_interrupt_disable.S index 78a89b80..549423c5 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a15/gnu/src/tx_thread_interrupt_disable.S @@ -53,7 +53,7 @@ $_tx_thread_interrupt_disable: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_disable Cortex-A15/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ $_tx_thread_interrupt_disable: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_disable(void) diff --git a/ports/cortex_a15/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a15/gnu/src/tx_thread_interrupt_restore.S index 8614e43a..0f5a7b0a 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a15/gnu/src/tx_thread_interrupt_restore.S @@ -53,7 +53,7 @@ $_tx_thread_interrupt_restore: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_restore Cortex-A15/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -83,7 +83,7 @@ $_tx_thread_interrupt_restore: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_end.S index c414ab0b..0ae02793 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_end.S @@ -50,7 +50,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_irq_nesting_end Cortex-A15/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -89,7 +89,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_start.S index 6c433de5..222d348f 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_start.S @@ -46,7 +46,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_irq_nesting_start Cortex-A15/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_a15/gnu/src/tx_thread_schedule.S b/ports/cortex_a15/gnu/src/tx_thread_schedule.S index 550e71ac..357200b9 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a15/gnu/src/tx_thread_schedule.S @@ -62,7 +62,7 @@ $_tx_thread_schedule: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule Cortex-A15/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -95,7 +95,7 @@ $_tx_thread_schedule: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_a15/gnu/src/tx_thread_stack_build.S b/ports/cortex_a15/gnu/src/tx_thread_stack_build.S index 3b3b75b4..cad38249 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a15/gnu/src/tx_thread_stack_build.S @@ -64,7 +64,7 @@ $_tx_thread_stack_build: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_stack_build Cortex-A15/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -96,7 +96,7 @@ $_tx_thread_stack_build: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_a15/gnu/src/tx_thread_system_return.S b/ports/cortex_a15/gnu/src/tx_thread_system_return.S index b3a3fe65..cc4c7cf0 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a15/gnu/src/tx_thread_system_return.S @@ -64,7 +64,7 @@ $_tx_thread_system_return: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_system_return Cortex-A15/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -96,7 +96,7 @@ $_tx_thread_system_return: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_a15/gnu/src/tx_thread_vectored_context_save.S b/ports/cortex_a15/gnu/src/tx_thread_vectored_context_save.S index 7b7a5d9f..6105dcb7 100644 --- a/ports/cortex_a15/gnu/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_a15/gnu/src/tx_thread_vectored_context_save.S @@ -47,7 +47,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_vectored_context_save Cortex-A15/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -78,7 +78,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_vectored_context_save(VOID) diff --git a/ports/cortex_a15/gnu/src/tx_timer_interrupt.S b/ports/cortex_a15/gnu/src/tx_timer_interrupt.S index 1dc0e511..2b2fc012 100644 --- a/ports/cortex_a15/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a15/gnu/src/tx_timer_interrupt.S @@ -71,7 +71,7 @@ $_tx_timer_interrupt: @/* FUNCTION RELEASE */ @/* */ @/* _tx_timer_interrupt Cortex-A15/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -105,7 +105,7 @@ $_tx_timer_interrupt: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_a15/iar/example_build/azure_rtos.eww b/ports/cortex_a15/iar/example_build/azure_rtos.eww new file mode 100644 index 00000000..17e0d329 --- /dev/null +++ b/ports/cortex_a15/iar/example_build/azure_rtos.eww @@ -0,0 +1,13 @@ + + + + + $WS_DIR$\sample_threadx.ewp + + + $WS_DIR$\tx.ewp + + + + + diff --git a/ports/cortex_a15/iar/example_build/cstartup.s b/ports/cortex_a15/iar/example_build/cstartup.s new file mode 100644 index 00000000..647de2e8 --- /dev/null +++ b/ports/cortex_a15/iar/example_build/cstartup.s @@ -0,0 +1,156 @@ + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Part one of the system initialization code, +;; contains low-level +;; initialization. +;; +;; Copyright 2007 IAR Systems. All rights reserved. +;; +;; $Revision: 14520 $ +;; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION IRQ_STACK:DATA:NOROOT(3) + SECTION FIQ_STACK:DATA:NOROOT(3) + SECTION CSTACK:DATA:NOROOT(3) + +; +; The module in this file are included in the libraries, and may be +; replaced by any user-defined modules that define the PUBLIC symbol +; __iar_program_start or a user defined start symbol. +; +; To override the cstartup defined in the library, simply add your +; modified version to the workbench project. + + SECTION .intvec:CODE:NOROOT(2) + + PUBLIC __vector + PUBLIC __vector_0x14 + PUBLIC __iar_program_start + EXTERN __tx_undefined + EXTERN __tx_swi_interrupt + EXTERN __tx_prefetch_handler + EXTERN __tx_abort_handler + EXTERN __tx_irq_handler + EXTERN __tx_fiq_handler + + ARM +__vector: + ; All default exception handlers (except reset) are + ; defined as weak symbol definitions. + ; If a handler is defined by the application it will take precedence. + LDR PC,Reset_Addr ; Reset + LDR PC,Undefined_Addr ; Undefined instructions + LDR PC,SWI_Addr ; Software interrupt (SWI/SVC) + LDR PC,Prefetch_Addr ; Prefetch abort + LDR PC,Abort_Addr ; Data abort +__vector_0x14: + DCD 0 ; RESERVED + LDR PC,IRQ_Addr ; IRQ + LDR PC,FIQ_Addr ; FIQ + +Reset_Addr: DCD __iar_program_start +Undefined_Addr: DCD __tx_undefined +SWI_Addr: DCD __tx_swi_interrupt +Prefetch_Addr: DCD __tx_prefetch_handler +Abort_Addr: DCD __tx_abort_handler +IRQ_Addr: DCD __tx_irq_handler +FIQ_Addr: DCD __tx_fiq_handler + +; -------------------------------------------------- +; ?cstartup -- low-level system initialization code. +; +; After a reser execution starts here, the mode is ARM, supervisor +; with interrupts disabled. +; + + + + SECTION .text:CODE:NOROOT(2) + +; PUBLIC ?cstartup + EXTERN ?main + REQUIRE __vector + + ARM + +__iar_program_start: +?cstartup: + +; +; Add initialization needed before setup of stackpointers here. +; + +; +; Initialize the stack pointers. +; The pattern below can be used for any of the exception stacks: +; FIQ, IRQ, SVC, ABT, UND, SYS. +; The USR mode uses the same stack as SYS. +; The stack segments must be defined in the linker command file, +; and be declared above. +; + + +; -------------------- +; Mode, correspords to bits 0-5 in CPSR + +MODE_MSK DEFINE 0x1F ; Bit mask for mode bits in CPSR + +USR_MODE DEFINE 0x10 ; User mode +FIQ_MODE DEFINE 0x11 ; Fast Interrupt Request mode +IRQ_MODE DEFINE 0x12 ; Interrupt Request mode +SVC_MODE DEFINE 0x13 ; Supervisor mode +ABT_MODE DEFINE 0x17 ; Abort mode +UND_MODE DEFINE 0x1B ; Undefined Instruction mode +SYS_MODE DEFINE 0x1F ; System mode + + + MRS r0, cpsr ; Original PSR value + + ;; Set up the interrupt stack pointer. + + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK + + ;; Set up the fast interrupt stack pointer. + + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #FIQ_MODE ; Set FIR mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK + + ;; Set up the normal stack pointer. + + BIC r0 ,r0, #MODE_MSK ; Clear the mode bits + ORR r0 ,r0, #SYS_MODE ; Set System mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(CSTACK) ; End of CSTACK + +#ifdef __ARMVFP__ + MRC p15, 0, r1, c1, c0, 2 ; r1 = Access Control Register + ORR r1, r1, #(0xf << 20) ; Enable full access for p10,11 + MCR p15, 0, r1, c1, c0, 2 ; Access Control Register = r1 + MOV r1, #0 + MCR p15, 0, r1, c7, c5, 4 ; Flush prefetch buffer because of FMXR below and + ; CP 10 & 11 were only just enabled + MOV r0, #0x40000000 ; Enable VFP itself + FMXR FPEXC, r0 ; FPEXC = r0 +#endif + +; +; Add more initialization here +; + +; Continue to ?main for C-level initialization. + + B ?main + + END + + + diff --git a/ports/cortex_a15/iar/example_build/sample_threadx.c b/ports/cortex_a15/iar/example_build/sample_threadx.c new file mode 100644 index 00000000..c7c300cb --- /dev/null +++ b/ports/cortex_a15/iar/example_build/sample_threadx.c @@ -0,0 +1,372 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +UCHAR memory_pool[DEMO_BYTE_POOL_SIZE]; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_pool, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_a15/iar/example_build/sample_threadx.ewd b/ports/cortex_a15/iar/example_build/sample_threadx.ewd new file mode 100644 index 00000000..50ce68b2 --- /dev/null +++ b/ports/cortex_a15/iar/example_build/sample_threadx.ewd @@ -0,0 +1,2974 @@ + + + 3 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 32 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\RemedyRtosViewer\RemedyRtosViewer.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8b.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8bBE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 1 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + 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$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8b.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8bBE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/ports/cortex_a15/iar/example_build/sample_threadx.ewp b/ports/cortex_a15/iar/example_build/sample_threadx.ewp new file mode 100644 index 00000000..35130720 --- /dev/null +++ b/ports/cortex_a15/iar/example_build/sample_threadx.ewp @@ -0,0 +1,2136 @@ + + + 3 + + Debug + + ARM + + 1 + + General + 3 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 36 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 23 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 36 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + 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b/ports/cortex_a15/iar/example_build/sample_threadx.icf @@ -0,0 +1,49 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x80; +define symbol __ICFEDIT_region_ROM_end__ = 0x1FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x100000; +define symbol __ICFEDIT_region_RAM_end__ = 0x1FFFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x2000; +define symbol __ICFEDIT_size_svcstack__ = 0x100; +define symbol __ICFEDIT_size_irqstack__ = 0x100; +define symbol __ICFEDIT_size_fiqstack__ = 0x100; +define symbol __ICFEDIT_size_undstack__ = 0x100; +define symbol __ICFEDIT_size_abtstack__ = 0x100; +define symbol __ICFEDIT_size_heap__ = 0x8000; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __ICFEDIT_size_freemem__ = 0x100000; + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region RAM_freemem = mem:[from 0x200000 to 0x300000]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; +define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; +define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + + +initialize by copy { readwrite }; +initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, + block UND_STACK, block ABT_STACK, block HEAP}; + +place in RAM_region { last section FREE_MEM}; \ No newline at end of file diff --git a/ports/cortex_a15/iar/example_build/tx.ewp b/ports/cortex_a15/iar/example_build/tx.ewp new file mode 100644 index 00000000..0e4bca80 --- /dev/null +++ b/ports/cortex_a15/iar/example_build/tx.ewp @@ -0,0 +1,2766 @@ + + + 3 + + Debug + + ARM + + 1 + + General + 3 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 36 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_cleanup.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_initialize.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_performance_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_performance_system_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_prioritize.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_block_release.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_allocate.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_cleanup.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_initialize.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_performance_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_performance_system_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_prioritize.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_search.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_release.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_cleanup.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_initialize.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_performance_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_performance_system_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_set.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_set_notify.c + + + $PROJ_DIR$\..\src\tx_iar.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_initialize_high_level.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_initialize_kernel_enter.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_initialize_kernel_setup.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_misra.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_cleanup.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_initialize.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_performance_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_performance_system_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_prioritize.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_priority_change.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_put.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_queue_cleanup.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_queue_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_queue_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_queue_flush.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_queue_front_send.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_queue_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_queue_initialize.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_queue_performance_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_queue_performance_system_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_queue_prioritize.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_queue_receive.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_queue_send.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_queue_send_notify.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_semaphore_ceiling_put.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_semaphore_cleanup.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_semaphore_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_semaphore_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_semaphore_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_semaphore_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_semaphore_initialize.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_semaphore_performance_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_semaphore_performance_system_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_semaphore_prioritize.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_semaphore_put.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_semaphore_put_notify.c + + + $PROJ_DIR$\..\src\tx_thread_context_restore.s + + + $PROJ_DIR$\..\src\tx_thread_context_save.s + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_entry_exit_notify.c + + + $PROJ_DIR$\..\src\tx_thread_fiq_context_restore.s + + + $PROJ_DIR$\..\src\tx_thread_fiq_context_save.s + + + $PROJ_DIR$\..\src\tx_thread_fiq_nesting_end.s + + + $PROJ_DIR$\..\src\tx_thread_fiq_nesting_start.s + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_identify.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_initialize.c + + + $PROJ_DIR$\..\src\tx_thread_interrupt_control.s + + + $PROJ_DIR$\..\src\tx_thread_interrupt_disable.s + + + $PROJ_DIR$\..\src\tx_thread_interrupt_restore.s + + + $PROJ_DIR$\..\src\tx_thread_irq_nesting_end.s + + + $PROJ_DIR$\..\src\tx_thread_irq_nesting_start.s + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_performance_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_performance_system_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_preemption_change.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_priority_change.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_relinquish.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_reset.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_resume.c + + + $PROJ_DIR$\..\src\tx_thread_schedule.s + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_shell_entry.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_sleep.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_stack_analyze.c + + + $PROJ_DIR$\..\src\tx_thread_stack_build.s + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_stack_error_handler.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_stack_error_notify.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_suspend.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_system_preempt_check.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_system_resume.c + + + $PROJ_DIR$\..\src\tx_thread_system_return.s + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_system_suspend.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_terminate.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_time_slice.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_time_slice_change.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_timeout.c + + + $PROJ_DIR$\..\src\tx_thread_vectored_context_save.s + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_wait_abort.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_time_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_time_set.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_timer_activate.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_timer_change.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_timer_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_timer_deactivate.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_timer_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_timer_expiration_process.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_timer_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_timer_initialize.c + + + $PROJ_DIR$\..\src\tx_timer_interrupt.s + + + $PROJ_DIR$\..\..\..\..\common\src\tx_timer_performance_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_timer_performance_system_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_timer_system_activate.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_timer_system_deactivate.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_timer_thread_entry.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_trace_buffer_full_notify.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_trace_disable.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_trace_enable.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_trace_event_filter.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_trace_event_unfilter.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_trace_initialize.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_trace_interrupt_control.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_trace_isr_enter_insert.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_trace_isr_exit_insert.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_trace_object_register.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_trace_object_unregister.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_trace_user_event_insert.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_block_allocate.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_block_pool_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_block_pool_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_block_pool_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_block_pool_prioritize.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_block_release.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_byte_allocate.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_byte_pool_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_byte_pool_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_byte_pool_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_byte_pool_prioritize.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_byte_release.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_set.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_set_notify.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_prioritize.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_put.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_queue_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_queue_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_queue_flush.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_queue_front_send.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_queue_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_queue_prioritize.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_queue_receive.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_queue_send.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_queue_send_notify.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_ceiling_put.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_prioritize.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_put.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_put_notify.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_entry_exit_notify.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_preemption_change.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_priority_change.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_relinquish.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_reset.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_resume.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_suspend.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_terminate.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_time_slice_change.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_wait_abort.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_activate.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_change.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_deactivate.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_info_get.c + + + diff --git a/ports/cortex_a15/iar/example_build/tx_initialize_low_level.s b/ports/cortex_a15/iar/example_build/tx_initialize_low_level.s new file mode 100644 index 00000000..2eeef43b --- /dev/null +++ b/ports/cortex_a15/iar/example_build/tx_initialize_low_level.s @@ -0,0 +1,321 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_initialize.h" +;#include "tx_thread.h" +;#include "tx_timer.h" + +SVC_MODE DEFINE 0xD3 ; Disable IRQ/FIQ SVC mode +IRQ_MODE DEFINE 0xD2 ; Disable IRQ/FIQ IRQ mode +FIQ_MODE DEFINE 0xD1 ; Disable IRQ/FIQ FIQ mode +SYS_MODE DEFINE 0xDF ; Disable IRQ/FIQ SYS mode +FIQ_STACK_SIZE DEFINE 512 ; FIQ stack size +IRQ_STACK_SIZE DEFINE 1024 ; IRQ stack size +SYS_STACK_SIZE DEFINE 1024 ; System stack size +; +; + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_initialize_unused_memory + EXTERN _tx_thread_context_save + EXTERN _tx_thread_context_restore + EXTERN _tx_timer_interrupt + EXTERN _end + EXTERN _sp + EXTERN _stack_bottom + EXTERN _tx_build_options + EXTERN _tx_version_id +; +; +; +;/* Define the FREE_MEM segment that will specify where free memory is +; defined. This must also be located in at the end of other RAM segments +; in the linker control file. The value of this segment is what is passed +; to tx_application_define. */ +; + RSEG FREE_MEM:DATA + PUBLIC __tx_free_memory_start +__tx_free_memory_start + DS32 4 +; +; +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-A15/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_initialize_low_level + CODE32 +_tx_initialize_low_level +; +; /****** NOTE ****** The IAR 4.11a and above releases call main in SYS mode. */ +; +; /* Remember the stack pointer, link register, and switch to SVC mode. */ +; + MOV r0, sp ; Remember the SP + MOV r1, lr ; Remember the LR + MOV r3, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_cxsf, r3 ; Switch to SVC mode + MOV sp, r0 ; Inherit the stack pointer setup by cstartup + MOV lr, r1 ; Inherit the link register +; +; /* Pickup the start of free memory. */ +; + LDR r0, =__tx_free_memory_start ; Get end of non-initialized RAM area +; +; /* Save the system stack pointer. */ +; _tx_thread_system_stack_ptr = (VOID_PTR) (sp); +; +; /* Save the first available memory address. */ +; _tx_initialize_unused_memory = (VOID_PTR) FREE_MEM; +; + LDR r2, =_tx_initialize_unused_memory ; Pickup unused memory ptr address + STR r0, [r2, #0] ; Save first free memory address +; +; /* Setup Timer for periodic interrupts. */ +; +; /* Done, return to caller. */ +; +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +;} +; +; +;/* Define shells for each of the interrupt vectors. */ +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_undefined +__tx_undefined + B __tx_undefined ; Undefined handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_swi_interrupt +__tx_swi_interrupt + B __tx_swi_interrupt ; Software interrupt handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_prefetch_handler +__tx_prefetch_handler + B __tx_prefetch_handler ; Prefetch exception handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_abort_handler +__tx_abort_handler + B __tx_abort_handler ; Abort exception handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_reserved_handler +__tx_reserved_handler + B __tx_reserved_handler ; Reserved exception handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_irq_processing_return + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_irq_handler +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. In +; addition, IRQ interrupts may be re-enabled - with certain restrictions - +; if nested IRQ interrupts are desired. Interrupts may be re-enabled over +; small code sequences where lr is saved before enabling interrupts and +; restored after interrupts are again disabled. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; from IRQ mode with interrupts disabled. This routine switches to the +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared +; prior to enabling nested IRQ interrupts. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_start +#endif +; +; /* For debug purpose, execute the timer interrupt processing here. In +; a real system, some kind of status indication would have to be checked +; before the timer interrupt handler could be called. */ +; + BL _tx_timer_interrupt ; Timer interrupt handler +; +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_context_restore. +; This routine returns in processing in IRQ mode with interrupts disabled. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_end +#endif +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore +; +; +; /* This is an example of a vectored IRQ handler. */ +; +; .global __tx_example_vectored_irq_handler +;__tx_example_vectored_irq_handler: +; +; +; /* Save initial context and call context save to prepare for +; vectored ISR execution. */ +; +; STMDB sp!, {r0-r3} ; Save some scratch registers +; MRS r0, SPSR ; Pickup saved SPSR +; SUB lr, lr, #4 ; Adjust point of interrupt +; STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers +; BL _tx_thread_vectored_context_save ; Vectored context save +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. In +; addition, IRQ interrupts may be re-enabled - with certain restrictions - +; if nested IRQ interrupts are desired. Interrupts may be re-enabled over +; small code sequences where lr is saved before enabling interrupts and +; restored after interrupts are again disabled. */ +; +; +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; from IRQ mode with interrupts disabled. This routine switches to the +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared +; prior to enabling nested IRQ interrupts. */ +;#ifdef TX_ENABLE_IRQ_NESTING +; BL _tx_thread_irq_nesting_start +;#endif +; +; /* Application IRQ handlers can be called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_context_restore. +; This routine returns in processing in IRQ mode with interrupts disabled. */ +;#ifdef TX_ENABLE_IRQ_NESTING +; BL _tx_thread_irq_nesting_end +;#endif +; +; /* Jump to context restore to restore system context. */ +; B _tx_thread_context_restore +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_processing_return + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_handler +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +; from FIQ mode with interrupts disabled. This routine switches to the +; system mode and returns with FIQ interrupts enabled. +; +; NOTE: It is very important to ensure all FIQ interrupts are cleared +; prior to enabling nested FIQ interrupts. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_start +#endif +; +; /* Application FIQ handlers can be called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_fiq_context_restore. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_end +#endif +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore +; +; +#else + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_handler +__tx_fiq_handler + B __tx_fiq_handler ; FIQ interrupt handler +#endif +; +; +BUILD_OPTIONS + DC32 _tx_build_options ; Reference to bring in +VERSION_ID + DC32 _tx_version_id ; Reference to bring in + + END + diff --git a/ports/cortex_a15/iar/inc/tx_port.h b/ports/cortex_a15/iar/inc/tx_port.h new file mode 100644 index 00000000..7529be75 --- /dev/null +++ b/ports/cortex_a15/iar/inc/tx_port.h @@ -0,0 +1,398 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A15/IAR */ +/* 6.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include +#include +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#else +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif + +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ + VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; +#endif +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#if (__VER__ < 8000000) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); +#else +void *_tx_iar_create_per_thread_tls_area(void); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); +void __iar_Initlocks(void); + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#endif +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#if __CORE__ > __ARM4TM__ + +#if __CPU_MODE__ == 2 + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + b = (UINT) __CLZ(m); \ + b = 31 - b; +#endif +#endif +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + + +/* First, check and see what mode the file is being compiled in. The IAR compiler + defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode + is present. If ARM 32-bit mode is present, the fast CPSR manipulation macros + are available. Otherwise, if Thumb mode is present, we must use function calls. */ + +#ifdef TX_DISABLE_INLINE + +UINT _tx_thread_interrupt_disable(void); +void _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else +#if __CPU_MODE__ == 2 + +#if (__VER__ < 8002000) +__intrinsic unsigned long __get_CPSR(); +__intrinsic void __set_CPSR( unsigned long ); +#endif + + +#if (__VER__ < 8002000) +#define TX_INTERRUPT_SAVE_AREA unsigned long interrupt_save; +#else +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#endif + + +#define TX_DISABLE interrupt_save = __get_CPSR(); \ + __set_CPSR(interrupt_save | TX_INT_DISABLE); +#define TX_RESTORE __set_CPSR(interrupt_save); + +#else + +UINT _tx_thread_interrupt_disable(void); +void _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#endif +#endif + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define VFP extension for the Cortex-A15. Each is assumed to be called in the context of the executing + thread. */ + +void tx_thread_vfp_enable(void); +void tx_thread_vfp_disable(void); + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A15/IAR Version 6.1 *"; +#else +#ifdef TX_MISRA_ENABLE +extern CHAR _tx_version_id[100]; +#else +extern CHAR _tx_version_id[]; +#endif +#endif + + +#endif + + + diff --git a/ports/cortex_a15/iar/readme_threadx.txt b/ports/cortex_a15/iar/readme_threadx.txt new file mode 100644 index 00000000..f7b0f20e --- /dev/null +++ b/ports/cortex_a15/iar/readme_threadx.txt @@ -0,0 +1,544 @@ + Microsoft's Azure RTOS ThreadX for Cortex-A15 + + Thumb & 32-bit Mode + + Using the IAR Tools + +1. Building the ThreadX run-time Library + +Building the ThreadX library is easy. First, open the Azure RTOS workspace +azure_rtos.eww. Next, make the TX project the "active project" in the +IAR Embedded Workbench and select the "Make" button. You should observe +assembly and compilation of a series of ThreadX source files. This +results in the ThreadX run-time library file tx.a, which is needed by +the application. + + +2. Demonstration System + +The ThreadX demonstration is designed to execute under the IAR +Windows-based Cortex-A15 simulator. + +Building the demonstration is easy; simply make the sample_threadx.ewp project +the "active project" in the IAR Embedded Workbench and select the +"Make" button. + +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.out is a +binary file that can be downloaded and executed on IAR's Cortex-A15 simulator. + + +3. System Initialization + +The entry point in ThreadX for the Cortex-A15 using IAR tools is at label +?cstartup. This is defined within the IAR compiler's startup code. In +addition, this is where all static and global preset C variable +initialization processing takes place. + +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, and a periodic timer interrupt source. +By default, the vector area is defined at the top of cstartup.s, which is +a slightly modified from the base IAR file. + +The _tx_initialize_low_level function inside of tx_initialize_low_level.s +also determines the first available address for use by the application, which +is supplied as the sole input parameter to your application definition function, +tx_application_define. To accomplish this, a section is created in +tx_initialize_low_level.s called FREE_MEM, which must be located after all +other RAM sections in memory. + + +4. Register Usage and Stack Frames + +The IAR ARM compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are +scratch registers for each function. All other registers used by a C function +must be preserved by the function. ThreadX takes advantage of this in +situations where a context switch happens as a result of making a ThreadX +service call (which is itself a C function). In such cases, the saved +context of a thread is only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 CPSR CPSR + 0x08 r0 (a1) r4 (v1) + 0x0C r1 (a2) r5 (v2) + 0x10 r2 (a3) r6 (v3) + 0x14 r3 (a4) r7 (v4) + 0x18 r4 (v1) r8 (v5) + 0x1C r5 (v2) r9 (v6) + 0x20 r6 (v3) r10 (v7) + 0x24 r7 (v4) r11 (fp) + 0x28 r8 (v5) r14 (lr) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) + 0x3C r14 (lr) + 0x40 PC + + +5. Conditional Compilation Switches + +The following are conditional compilation options for building the ThreadX library +and application: + + + TX_ENABLE_FIQ_SUPPORT This assembler/compiler define enables + FIQ interrupt handling support in the + ThreadX assembly files. If used, + it should be used on all assembly + files and the generic C source of + ThreadX should be compiled with + TX_ENABLE_FIQ_SUPPORT defined as well. + + TX_ENABLE_IRQ_NESTING This assembler define enables IRQ + nested support. If IRQ nested + interrupt support is needed, this + define should be applied to + tx_initialize_low_level.s. + + TX_ENABLE_FIQ_NESTING This assembler define enables FIQ + nested support. If FIQ nested + interrupt support is needed, this + define should be applied to + tx_initialize_low_level.s. In addition, + IRQ nesting should also be enabled. + + TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, + this define causes basic ThreadX error + checking to be disabled. Please see + Chapter 2 in the "ThreadX User Guide" + for more details. + + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By + default, this value is set to 32 priority levels. + + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found + in tx_port.h. + + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default + value is port-specific and is found in tx_port.h. + + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined + in tx_port.h. + + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. + By default, this option is not defined. + + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. + By default, this option is not defined. + + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is + not defined. + + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. + By default, this option is not defined. + + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. + By default, this option is not defined. + + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. + By default, this option is not defined. + + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size + and improves performance. + + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is + not defined. + + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is + not defined. + + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option + is not defined. + + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is + not defined. + + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is + not defined. + + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is + not defined. + + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is + not defined. + + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is + not defined. + + TX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace + feature. The trace buffer is supplied at a later time + via an application call to tx_trace_enable. + + TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is + built with TX_ENABLE_EVENT_TRACE defined. + + TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX + library is built with TX_ENABLE_EVENT_TRACE defined. + + TX_THUMB Defined, this option enables the BX LR calling return sequence + in assembly files, to ensure correct operation on systems that + use both ARM and Thumb mode. By default, this option is + not defined + + + + + +6. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the ThreadX library +project to enable various compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-A15 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +7.1 Vector Area + +The Cortex-A15 vectors start at address zero. The demonstration system startup +cstartup.s file contains the vectors and is loaded at address zero. +On actual hardware platforms, this area might have to be copied to address 0. + + +7.2 IRQ ISRs + +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested +IRQ interrupts. The following sub-sections define the IRQ capabilities. + + +7.2.1 Standard IRQ ISRs + +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +is the default IRQ handler defined in tx_initialize_low_level.s: + + PUBLIC __tx_irq_handler + PUBLIC __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Application ISR dispatch call goes here! */ +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.2 Vectored IRQ ISRs + +The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified +by the particular implementation. The following is an example IRQ handler defined in +tx_initialize_low_level.s: + + + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_example_vectored_irq_handler +__tx_example_vectored_irq_handler +; +; /* Jump to context save to save system context. */ + STMDB sp!, {r0-r3} ; Save some scratch registers + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers + BL _tx_thread_vectored_context_save +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Application ISR dispatch call goes here! */ +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.3 Nested IRQ Support + +By default, nested IRQ interrupt support is not enabled. To enable nested +IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING +defined. With this defined, two new IRQ interrupt management services are +available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. +These function should be called between the IRQ context save and restore +calls. + +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +by switching from IRQ mode to SYS mode and enabling IRQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in +preparation for the IRQ context restore service. + +The following is an example of enabling IRQ nested interrupts in a standard +IRQ handler: + + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_irq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; from IRQ mode with interrupts disabled. This routine switches to the +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared +; prior to enabling nested IRQ interrupts. */ +; + BL _tx_thread_irq_nesting_start + +; /* Application ISR dispatch call goes here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_context_restore. +; This routine returns in processing in IRQ mode with interrupts disabled. */ +; + BL _tx_thread_irq_nesting_end +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.3 FIQ Interrupts + +By default, Cortex-A15 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made +from default FIQ ISRs, which is located in tx_initialize_low_level.s. + + +7.3.1 Managed FIQ Interrupts + +Full ThreadX management of FIQ interrupts is provided if the ThreadX sources +are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built +this way, the FIQ interrupt handlers are very similar to the IRQ interrupt +handlers defined previously. The following is default FIQ handler +defined in tx_initialize_low_level.s: + + + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Application FIQ dispatch call goes here! */ +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + + +7.3.1.1 Nested FIQ Support + +By default, nested FIQ interrupt support is not enabled. To enable nested +FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING +defined. With this defined, two new FIQ interrupt management services are +available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. +These function should be called between the FIQ context save and restore +calls. + +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +by switching from FIQ mode to SYS mode and enabling FIQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested FIQ interrupts are no +longer required, calling the _tx_thread_fiq_nesting_end service disables +nesting by disabling FIQ interrupts and switching back to FIQ mode in +preparation for the FIQ context restore service. + +The following is an example of enabling FIQ nested interrupts in the +typical FIQ handler: + + + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Enable nested FIQ interrupts. NOTE: Since this service returns +; with FIQ interrupts enabled, all FIQ interrupt sources must be +; cleared prior to calling this service. */ + BL _tx_thread_fiq_nesting_start +; +; /* Application FIQ dispatch call goes here! */ +; +; /* Disable nested FIQ interrupts. The mode is switched back to +; FIQ mode and FIQ interrupts are disable upon return. */ + BL _tx_thread_fiq_nesting_end +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +8. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional. However, all other +ThreadX services are operational without a periodic timer source. + +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt +in the IRQ processing. + + +9. Thumb/Cortex-A15 Mixed Mode + +By default, ThreadX is setup for running in Cortex-A15 32-bit mode. This is +also true for the demonstration system. It is possible to build any +ThreadX file and/or the application in Thumb mode. The only exception +to this is the file tx_thread_shell_entry.c. This file must always be +built in 32-bit mode. In addition, if any Thumb code is used the entire +ThreadX assembly source should be built with TX_THUMB defined. + + +10. IAR Thread-safe Library Support + +Thread-safe support for the IAR tools is easily enabled by building the ThreadX library +and the application with TX_ENABLE_IAR_LIBRARY_SUPPORT. Also, the linker control file +should have the following line added (if not already in place): + +initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application + +The project options "General Options -> Library Configuration" should also have the +"Enable thread support in library" box selected. + + +11. VFP Support + +By default, VFP support is disabled for each thread. If saving the context of the VFP registers +is needed, the following API call must be made from the context of the application thread - before +the VFP usage: + +void tx_thread_vfp_enable(void); + +After this API is called in the application, VFP registers will be saved/restored for this thread if it +is preempted via an interrupt. All other suspension of the this thread will not require the VFP registers +to be saved/restored. + +To disable VFP register context saving, simply call the following API: + +void tx_thread_vfp_disable(void); + + + +12. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +09-30-2020 Initial ThreadX version 6.1 for Cortex-A15 using IAR's ARM tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_a15/iar/src/tx_iar.c b/ports/cortex_a15/iar/src/tx_iar.c new file mode 100644 index 00000000..11fcefb3 --- /dev/null +++ b/ports/cortex_a15/iar/src/tx_iar.c @@ -0,0 +1,804 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** IAR Multithreaded Library Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Define IAR library for tools prior to version 8. */ + +#if (__VER__ < 8000000) + + +/* IAR version 7 and below. */ + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_mutex.h" + + +/* This implementation requires that the following macros are defined in the + tx_port.h file and is included with the following code segments: + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. + + Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. +*/ + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT + +#include + + +#if _MULTI_THREAD + +TX_MUTEX __tx_iar_system_lock_mutexes[_MAX_LOCK]; +UINT __tx_iar_system_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_system_lock_no_mutexes; +UINT __tx_iar_system_lock_internal_errors; +UINT __tx_iar_system_lock_isr_caller; + + +/* Define the TLS access function for the IAR library. */ + +void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) +{ + +char _DLIB_TLS_MEMORY *p = 0; + + /* Is there a current thread? */ + if (_tx_thread_current_ptr) + p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; + else + p = (void _DLIB_TLS_MEMORY *) __segment_begin("__DLIB_PERTHREAD"); + p += __IAR_DLIB_PERTHREAD_SYMBOL_OFFSET(symbp); + return (void _DLIB_TLS_MEMORY *) p; +} + + +/* Define mutexes for IAR library. */ + +void __iar_system_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_LOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_system_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_system_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_system_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_system_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_system_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } +} + +void __iar_system_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } +} + + +#if _DLIB_FILE_DESCRIPTOR + +TX_MUTEX __tx_iar_file_lock_mutexes[_MAX_FLOCK]; +UINT __tx_iar_file_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_file_lock_no_mutexes; +UINT __tx_iar_file_lock_internal_errors; +UINT __tx_iar_file_lock_isr_caller; + + +void __iar_file_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_FLOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_file_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_file_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_file_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_file_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_file_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} + +void __iar_file_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} +#endif /* _DLIB_FILE_DESCRIPTOR */ + +#endif /* _MULTI_THREAD */ + +#endif /* TX_ENABLE_IAR_LIBRARY_SUPPORT */ + +#else /* IAR version 8 and above. */ + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_mutex.h" + +/* This implementation requires that the following macros are defined in the + tx_port.h file and is included with the following code segments: + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +void *_tx_iar_create_per_thread_tls_area(void); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); +void __iar_Initlocks(void); + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. + + Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. +*/ + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT + +#include + + +void * __aeabi_read_tp(); + +void* _tx_iar_create_per_thread_tls_area(); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); + +#pragma section="__iar_tls$$DATA" + +/* Define the TLS access function for the IAR library. */ +void * __aeabi_read_tp(void) +{ + void *p = 0; + TX_THREAD *thread_ptr = _tx_thread_current_ptr; + if (thread_ptr) + { + p = thread_ptr->tx_thread_iar_tls_pointer; + } + else + { + p = __section_begin("__iar_tls$$DATA"); + } + return p; +} + +/* Define the TLS creation and destruction to use malloc/free. */ + +void* _tx_iar_create_per_thread_tls_area() +{ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ + void *p = malloc(tls_size); + + /* Initialize TLS-area and run constructors for objects in TLS */ + __iar_tls_init(p); + return p; +} + +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) +{ + /* Destroy objects living in TLS */ + __call_thread_dtors(); + free(tls_ptr); +} + +#ifndef _MAX_LOCK +#define _MAX_LOCK 4 +#endif + +static TX_MUTEX __tx_iar_system_lock_mutexes[_MAX_LOCK]; +static UINT __tx_iar_system_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_system_lock_no_mutexes; +UINT __tx_iar_system_lock_internal_errors; +UINT __tx_iar_system_lock_isr_caller; + + +/* Define mutexes for IAR library. */ + +void __iar_system_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_LOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_system_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_system_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_system_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_system_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_system_Mtxlock(__iar_Rmtx *m) +{ + if (*m) + { + UINT status; + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } + } +} + +void __iar_system_Mtxunlock(__iar_Rmtx *m) +{ + if (*m) + { + UINT status; + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } + } +} + + +#if _DLIB_FILE_DESCRIPTOR + +#include /* Added to get access to FOPEN_MAX */ +#ifndef _MAX_FLOCK +#define _MAX_FLOCK FOPEN_MAX /* Define _MAX_FLOCK as the maximum number of open files */ +#endif + + +TX_MUTEX __tx_iar_file_lock_mutexes[_MAX_FLOCK]; +UINT __tx_iar_file_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_file_lock_no_mutexes; +UINT __tx_iar_file_lock_internal_errors; +UINT __tx_iar_file_lock_isr_caller; + + +void __iar_file_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_FLOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_file_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_file_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_file_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_file_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_file_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} + +void __iar_file_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} +#endif /* _DLIB_FILE_DESCRIPTOR */ + +#endif /* TX_ENABLE_IAR_LIBRARY_SUPPORT */ + +#endif /* IAR version 8 and above. */ diff --git a/ports/cortex_a15/iar/src/tx_thread_context_restore.s b/ports/cortex_a15/iar/src/tx_thread_context_restore.s new file mode 100644 index 00000000..777558ae --- /dev/null +++ b/ports/cortex_a15/iar/src/tx_thread_context_restore.s @@ -0,0 +1,251 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +#ifdef TX_ENABLE_FIQ_SUPPORT +SVC_MODE DEFINE 0xD3 ; Disable IRQ/FIQ, SVC mode +IRQ_MODE DEFINE 0xD2 ; Disable IRQ/FIQ, IRQ mode +#else +SVC_MODE DEFINE 0x93 ; Disable IRQ, SVC mode +IRQ_MODE DEFINE 0x92 ; Disable IRQ, IRQ mode +#endif +; + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_schedule + EXTERN _tx_thread_preempt_disable + EXTERN _tx_execution_isr_exit +; +; + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-A15/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_context_restore + CODE32 +_tx_thread_context_restore +; +; /* Lockout interrupts. */ +; +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts +#else + CPSID i ; Disable IRQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + BL _tx_execution_isr_exit ; Call the ISR exit function +#endif +; +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state) +; { +; + LDR r3, =_tx_thread_system_state ; Pickup address of system state variable + LDR r2, [r3, #0] ; Pickup system state + SUB r2, r2, #1 ; Decrement the counter + STR r2, [r3, #0] ; Store the counter + CMP r2, #0 ; Was this the first interrupt? + BEQ __tx_thread_not_nested_restore ; If so, not a nested restore +; +; /* Interrupts are nested. */ +; +; /* Just recover the saved registers and return to the point of +; interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +__tx_thread_not_nested_restore +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; || (_tx_thread_preempt_disable)) +; { +; + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup actual current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_restore ; Yes, idle system was interrupted +; + LDR r3, =_tx_thread_preempt_disable ; Pickup preempt disable address + LDR r2, [r3, #0] ; Pickup actual preempt disable flag + CMP r2, #0 ; Is it set? + BNE __tx_thread_no_preempt_restore ; Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr ; Pickup address of execute thread ptr + LDR r2, [r3, #0] ; Pickup actual execute thread pointer + CMP r0, r2 ; Is the same thread highest priority? + BNE __tx_thread_preempt_restore ; No, preemption needs to happen +; +; +__tx_thread_no_preempt_restore +; +; /* Restore interrupted thread or ISR. */ +; +; /* Pickup the saved stack pointer. */ +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; +; /* Recover the saved context and return to the point of interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +; else +; { +__tx_thread_preempt_restore +; + LDMIA sp!, {r3, r10, r12, lr} ; Recover temporarily saved registers + MOV r1, lr ; Save lr (point of interrupt) + MOV r2, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r2 ; Enter SVC mode + STR r1, [sp, #-4]! ; Save point of interrupt + STMDB sp!, {r4-r12, lr} ; Save upper half of registers + MOV r4, r3 ; Save SPSR in r4 + MOV r2, #IRQ_MODE ; Build IRQ mode CPSR + MSR CPSR_c, r2 ; Enter IRQ mode + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOV r5, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r5 ; Enter SVC mode + STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + +#ifdef __ARMVFP__ + LDR r2, [r0, #144] ; Pickup the VFP enabled flag + CMP r2, #0 ; Is the VFP enabled? + BEQ _tx_skip_irq_vfp_save ; No, skip VFP IRQ save + VMRS r2, FPSCR ; Pickup the FPSCR + STR r2, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D0-D15} ; Save D0-D15 +_tx_skip_irq_vfp_save +#endif + + MOV r3, #1 ; Build interrupt stack type + STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR + STR sp, [r0, #8] ; Save stack pointer in thread control + ; block +; +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup time-slice variable address + LDR r2, [r3, #0] ; Pickup time-slice + CMP r2, #0 ; Is it active? + BEQ __tx_thread_dont_save_ts ; No, don't save it +; +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r2, [r0, #24] ; Save thread's time-slice + MOV r2, #0 ; Clear value + STR r2, [r3, #0] ; Disable global time-slice flag +; +; } +__tx_thread_dont_save_ts +; +; +; /* Clear the current task pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + MOV r0, #0 ; NULL value + STR r0, [r1, #0] ; Clear current thread pointer +; +; /* Return to the scheduler. */ +; _tx_thread_schedule(); +; + B _tx_thread_schedule ; Return to scheduler +; } +; +__tx_thread_idle_system_restore +; +; /* Just return back to the scheduler! */ +; + MOV r0, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r0 ; Enter SVC mode + B _tx_thread_schedule ; Return to scheduler +;} + + END + diff --git a/ports/cortex_a15/iar/src/tx_thread_context_save.s b/ports/cortex_a15/iar/src/tx_thread_context_save.s new file mode 100644 index 00000000..b8a9074a --- /dev/null +++ b/ports/cortex_a15/iar/src/tx_thread_context_save.s @@ -0,0 +1,199 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN __tx_irq_processing_return + EXTERN _tx_execution_isr_enter +; +; + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-A15/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_context_save + CODE32 +_tx_thread_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + STMDB sp!, {r0-r3} ; Save some working registers +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable FIQ interrupts +#endif + LDR r3, =_tx_thread_system_state ; Pickup address of system state variable + LDR r2, [r3, #0] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Save the rest of the scratch registers on the stack and return to the +; calling ISR. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + B __tx_irq_processing_return ; Continue IRQ processing +; +__tx_thread_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + ; scheduling loop - nothing needs saving! +; +; /* Save minimal context of interrupted thread. */ +; + MRS r2, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r2, r10, r12, lr} ; Store other registers +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr@ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + B __tx_irq_processing_return ; Continue IRQ processing +; +; } +; else +; { +; +__tx_thread_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; processing. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + ADD sp, sp, #16 ; Recover saved registers + B __tx_irq_processing_return ; Continue IRQ processing +; +; } +;} + + END + diff --git a/ports/cortex_a15/iar/src/tx_thread_fiq_context_restore.s b/ports/cortex_a15/iar/src/tx_thread_fiq_context_restore.s new file mode 100644 index 00000000..77496ffb --- /dev/null +++ b/ports/cortex_a15/iar/src/tx_thread_fiq_context_restore.s @@ -0,0 +1,258 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +SVC_MODE DEFINE 0xD3 ; SVC mode +FIQ_MODE DEFINE 0xD1 ; FIQ mode +MODE_MASK DEFINE 0x1F ; Mode mask +THUMB_MASK DEFINE 0x20 ; Thumb bit mask +IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits +; +; + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_schedule + EXTERN _tx_thread_preempt_disable + EXTERN _tx_execution_isr_exit +; +; + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_restore Cortex-A15/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the fiq interrupt context when processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* FIQ ISR Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_context_restore(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_fiq_context_restore + CODE32 +_tx_thread_fiq_context_restore +; +; /* Lockout interrupts. */ +; + CPSID if ; Disable IRQ and FIQ interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + BL _tx_execution_isr_exit ; Call the ISR exit function +#endif +; +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state) +; { +; + LDR r3, =_tx_thread_system_state ; Pickup address of system state variable + LDR r2, [r3, #0] ; Pickup system state + SUB r2, r2, #1 ; Decrement the counter + STR r2, [r3, #0] ; Store the counter + CMP r2, #0 ; Was this the first interrupt? + BEQ __tx_thread_fiq_not_nested_restore ; If so, not a nested restore +; +; /* Interrupts are nested. */ +; +; /* Just recover the saved registers and return to the point of +; interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +__tx_thread_fiq_not_nested_restore +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; || (_tx_thread_preempt_disable)) +; { +; + LDR r1, [sp] ; Pickup the saved SPSR + MOV r2, #MODE_MASK ; Build mask to isolate the interrupted mode + AND r1, r1, r2 ; Isolate mode bits + CMP r1, #IRQ_MODE_BITS ; Was an interrupt taken in IRQ mode before we + ; got to context save? */ + BEQ __tx_thread_fiq_no_preempt_restore ; Yes, just go back to point of interrupt + + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup actual current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_fiq_idle_system_restore ; Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable ; Pickup preempt disable address + LDR r2, [r3, #0] ; Pickup actual preempt disable flag + CMP r2, #0 ; Is it set? + BNE __tx_thread_fiq_no_preempt_restore ; Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr ; Pickup address of execute thread ptr + LDR r2, [r3, #0] ; Pickup actual execute thread pointer + CMP r0, r2 ; Is the same thread highest priority? + BNE __tx_thread_fiq_preempt_restore ; No, preemption needs to happen + + +__tx_thread_fiq_no_preempt_restore +; +; /* Restore interrupted thread or ISR. */ +; +; /* Pickup the saved stack pointer. */ +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; +; /* Recover the saved context and return to the point of interrupt. */ +; + LDMIA sp!, {r0, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +; else +; { +__tx_thread_fiq_preempt_restore +; + LDMIA sp!, {r3, lr} ; Recover temporarily saved registers + MOV r1, lr ; Save lr (point of interrupt) + MOV r2, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r2 ; Enter SVC mode + STR r1, [sp, #-4]! ; Save point of interrupt + STMDB sp!, {r4-r12, lr} ; Save upper half of registers + MOV r4, r3 ; Save SPSR in r4 + MOV r2, #FIQ_MODE ; Build FIQ mode CPSR + MSR CPSR_c, r2 ; Reenter FIQ mode + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOV r5, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r5 ; Enter SVC mode + STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + +#ifdef __ARMVFP__ + LDR r2, [r0, #144] ; Pickup the VFP enabled flag + CMP r2, #0 ; Is the VFP enabled? + BEQ _tx_skip_fiq_vfp_save ; No, skip VFP IRQ save + VMRS r2, FPSCR ; Pickup the FPSCR + STR r2, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D0-D15} ; Save D0-D15 +_tx_skip_fiq_vfp_save +#endif + + MOV r3, #1 ; Build interrupt stack type + STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR + STR sp, [r0, #8] ; Save stack pointer in thread control + ; block */ +; +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup time-slice variable address + LDR r2, [r3, #0] ; Pickup time-slice + CMP r2, #0 ; Is it active? + BEQ __tx_thread_fiq_dont_save_ts ; No, don't save it +; +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r2, [r0, #24] ; Save thread's time-slice + MOV r2, #0 ; Clear value + STR r2, [r3, #0] ; Disable global time-slice flag +; +; } +__tx_thread_fiq_dont_save_ts +; +; +; /* Clear the current task pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + MOV r0, #0 ; NULL value + STR r0, [r1, #0] ; Clear current thread pointer +; +; /* Return to the scheduler. */ +; _tx_thread_schedule(); +; + B _tx_thread_schedule ; Return to scheduler +; } +; +__tx_thread_fiq_idle_system_restore +; +; /* Just return back to the scheduler! */ +; + ADD sp, sp, #24 ; Recover FIQ stack space + MOV r3, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r3 ; Lockout interrupts + B _tx_thread_schedule ; Return to scheduler +; +;} + + END + diff --git a/ports/cortex_a15/iar/src/tx_thread_fiq_context_save.s b/ports/cortex_a15/iar/src/tx_thread_fiq_context_save.s new file mode 100644 index 00000000..4ad1e337 --- /dev/null +++ b/ports/cortex_a15/iar/src/tx_thread_fiq_context_save.s @@ -0,0 +1,202 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN __tx_fiq_processing_return + EXTERN _tx_execution_isr_enter +; +; + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_save Cortex-A15/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +; VOID _tx_thread_fiq_context_save(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_fiq_context_save + CODE32 +_tx_thread_fiq_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + STMDB sp!, {r0-r3} ; Save some working registers + LDR r3, =_tx_thread_system_state ; Pickup address of system state variable + LDR r2, [r3, #0] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_fiq_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Save the rest of the scratch registers on the stack and return to the +; calling ISR. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + B __tx_fiq_processing_return ; Continue FIQ processing +; +__tx_thread_fiq_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in +; ; scheduling loop - nothing needs saving! +; +; /* Save minimal context of interrupted thread. */ +; + MRS r2, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r2, lr} ; Store other registers, Note that we don't +; ; need to save sl and ip since FIQ has +; ; copies of these registers. Nested +; ; interrupt processing does need to save +; ; these registers. +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + B __tx_fiq_processing_return ; Continue FIQ processing +; +; } +; else +; { +; +__tx_thread_fiq_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif +; +; /* Not much to do here, save the current SPSR and LR for possible +; use in IRQ interrupted in idle system conditions, and return to +; FIQ interrupt processing. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, lr} ; Store other registers that will get used +; ; or stripped off the stack in context +; ; restore + B __tx_fiq_processing_return ; Continue FIQ processing +; +; } +;} + + END + diff --git a/ports/cortex_a15/iar/src/tx_thread_fiq_nesting_end.s b/ports/cortex_a15/iar/src/tx_thread_fiq_nesting_end.s new file mode 100644 index 00000000..078659be --- /dev/null +++ b/ports/cortex_a15/iar/src/tx_thread_fiq_nesting_end.s @@ -0,0 +1,114 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; Disable IRQ/FIQ interrupts +#else +DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts +#endif +MODE_MASK DEFINE 0x1F ; Mode mask +FIQ_MODE_BITS DEFINE 0x11 ; FIQ mode bits +; +; + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_end Cortex-A15/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +;/* processing from system mode back to FIQ mode prior to the ISR */ +;/* calling _tx_thread_fiq_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_nesting_end(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_fiq_nesting_end + CODE32 +_tx_thread_fiq_nesting_end + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value + MSR CPSR_c, r0 ; Disable interrupts + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + ; 8-byte alignment logic) + BIC r0, r0, #MODE_MASK ; Clear mode bits + ORR r0, r0, #FIQ_MODE_BITS ; Build IRQ mode CPSR + MSR CPSR_c, r0 ; Reenter IRQ mode + +#ifdef TX_THUMB + BX r3 ; Return to caller +#else + MOV pc, r3 ; Return to caller +#endif +;} + + END + diff --git a/ports/cortex_a15/iar/src/tx_thread_fiq_nesting_start.s b/ports/cortex_a15/iar/src/tx_thread_fiq_nesting_start.s new file mode 100644 index 00000000..c92384c4 --- /dev/null +++ b/ports/cortex_a15/iar/src/tx_thread_fiq_nesting_start.s @@ -0,0 +1,106 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +FIQ_DISABLE DEFINE 0x40 ; FIQ disable bit +MODE_MASK DEFINE 0x1F ; Mode mask +SYS_MODE_BITS DEFINE 0x1F ; System mode bits +; +; + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_start Cortex-A15/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +;/* processing to the system mode so nested FIQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_nesting_start(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_fiq_nesting_start + CODE32 +_tx_thread_fiq_nesting_start + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + BIC r0, r0, #MODE_MASK ; Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS ; Build system mode CPSR + MSR CPSR_c, r0 ; Enter system mode + STMDB sp!, {r1, lr} ; Push the system mode lr on the system mode stack + ; and push r1 just to keep 8-byte alignment + BIC r0, r0, #FIQ_DISABLE ; Build enable FIQ CPSR + MSR CPSR_c, r0 ; Enter system mode +#ifdef TX_THUMB + BX r3 ; Return to caller +#else + MOV pc, r3 ; Return to caller +#endif +;} + + END + diff --git a/ports/cortex_a15/iar/src/tx_thread_interrupt_control.s b/ports/cortex_a15/iar/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..8b7a3ac9 --- /dev/null +++ b/ports/cortex_a15/iar/src/tx_thread_interrupt_control.s @@ -0,0 +1,98 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" */ +; + +INT_MASK = 0x03F + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-A15/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_interrupt_control + CODE32 +_tx_thread_interrupt_control +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r3, CPSR ; Pickup current CPSR + MOV r2, #INT_MASK ; Build interrupt mask + AND r1, r3, r2 ; Clear interrupt lockout bits + ORR r1, r1, r0 ; Or-in new interrupt lockout bits +; +; /* Apply the new interrupt posture. */ +; + MSR CPSR_c, r1 ; Setup new CPSR + BIC r0, r3, r2 ; Return previous interrupt mask +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +;} + + END + diff --git a/ports/cortex_a15/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_a15/iar/src/tx_thread_interrupt_disable.s new file mode 100644 index 00000000..b0d5bcf0 --- /dev/null +++ b/ports/cortex_a15/iar/src/tx_thread_interrupt_disable.s @@ -0,0 +1,95 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-A15/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_disable(void) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_interrupt_disable + CODE32 +_tx_thread_interrupt_disable +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r0, CPSR ; Pickup current CPSR +; +; /* Mask interrupts. */ +; +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ +#else + CPSID i ; Disable IRQ +#endif + +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +;} + + END + diff --git a/ports/cortex_a15/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_a15/iar/src/tx_thread_interrupt_restore.s new file mode 100644 index 00000000..982aae9a --- /dev/null +++ b/ports/cortex_a15/iar/src/tx_thread_interrupt_restore.s @@ -0,0 +1,87 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-A15/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for restoring interrupts to the state */ +;/* returned by a previous _tx_thread_interrupt_disable call. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_restore(UINT old_posture) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_interrupt_restore + CODE32 +_tx_thread_interrupt_restore +; +; /* Apply the new interrupt posture. */ +; + MSR CPSR_c, r0 ; Setup new CPSR +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +;} + + END + diff --git a/ports/cortex_a15/iar/src/tx_thread_irq_nesting_end.s b/ports/cortex_a15/iar/src/tx_thread_irq_nesting_end.s new file mode 100644 index 00000000..0bf06449 --- /dev/null +++ b/ports/cortex_a15/iar/src/tx_thread_irq_nesting_end.s @@ -0,0 +1,113 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; Disable IRQ/FIQ interrupts +#else +DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts +#endif +MODE_MASK DEFINE 0x1F ; Mode mask +IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits +; +; + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end Cortex-A15/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_irq_nesting_end(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_irq_nesting_end + CODE32 +_tx_thread_irq_nesting_end + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value + MSR CPSR_c, r0 ; Disable interrupts + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + ; 8-byte alignment logic) + BIC r0, r0, #MODE_MASK ; Clear mode bits + ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR + MSR CPSR_c, r0 ; Reenter IRQ mode +#ifdef TX_THUMB + BX r3 ; Return to caller +#else + MOV pc, r3 ; Return to caller +#endif +;} + + END + diff --git a/ports/cortex_a15/iar/src/tx_thread_irq_nesting_start.s b/ports/cortex_a15/iar/src/tx_thread_irq_nesting_start.s new file mode 100644 index 00000000..73ff1bcb --- /dev/null +++ b/ports/cortex_a15/iar/src/tx_thread_irq_nesting_start.s @@ -0,0 +1,106 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +IRQ_DISABLE DEFINE 0x80 ; IRQ disable bit +MODE_MASK DEFINE 0x1F ; Mode mask +SYS_MODE_BITS DEFINE 0x1F ; System mode bits +; +; + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start Cortex-A15/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_irq_nesting_start(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_irq_nesting_start + CODE32 +_tx_thread_irq_nesting_start + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + BIC r0, r0, #MODE_MASK ; Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS ; Build system mode CPSR + MSR CPSR_c, r0 ; Enter system mode + STMDB sp!, {r1, lr} ; Push the system mode lr on the system mode stack + ; and push r1 just to keep 8-byte alignment + BIC r0, r0, #IRQ_DISABLE ; Build enable IRQ CPSR + MSR CPSR_c, r0 ; Enter system mode +#ifdef TX_THUMB + BX r3 ; Return to caller +#else + MOV pc, r3 ; Return to caller +#endif +;} + + END + diff --git a/ports/cortex_a15/iar/src/tx_thread_schedule.s b/ports/cortex_a15/iar/src/tx_thread_schedule.s new file mode 100644 index 00000000..727ecb89 --- /dev/null +++ b/ports/cortex_a15/iar/src/tx_thread_schedule.s @@ -0,0 +1,239 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + EXTERN _tx_thread_execute_ptr + EXTERN _tx_thread_current_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_execution_thread_enter +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-A15/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_schedule + CODE32 +_tx_thread_schedule +; +; /* Enable interrupts. */ +; +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSIE if ; Enable IRQ and FIQ interrupts +#else + CPSIE i ; Enable IRQ interrupts +#endif +; +; /* Wait for a thread to execute. */ +; do +; { + LDR r1, =_tx_thread_execute_ptr ; Address of thread execute ptr +; +__tx_thread_schedule_loop +; + LDR r0, [r1, #0] ; Pickup next thread to execute + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_schedule_loop ; If so, keep looking for a thread +; +; } +; while(_tx_thread_execute_ptr == TX_NULL); +; +; /* Yes! We have a thread to execute. Lockout interrupts and +; transfer control to it. */ +; +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts +#else + CPSID i ; Disable IRQ interrupts +#endif +; +; /* Setup the current thread pointer. */ +; _tx_thread_current_ptr = _tx_thread_execute_ptr; +; + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread + STR r0, [r1, #0] ; Setup current thread pointer +; +; /* Increment the run count for this thread. */ +; _tx_thread_current_ptr -> tx_thread_run_count++; +; + LDR r2, [r0, #4] ; Pickup run counter + LDR r3, [r0, #24] ; Pickup time-slice for this thread + ADD r2, r2, #1 ; Increment thread run-counter + STR r2, [r0, #4] ; Store the new run counter +; +; /* Setup time-slice, if present. */ +; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; +; + LDR r2, =_tx_timer_time_slice ; Pickup address of time-slice + ; variable + LDR sp, [r0, #8] ; Switch stack pointers + STR r3, [r2, #0] ; Setup time-slice +; +; /* Switch to the thread's stack. */ +; sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; +; +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + MOV r5, r0 ; Save r0 + BL _tx_execution_thread_enter ; Call the thread execution enter function + MOV r0, r5 ; Restore r0 +#endif +; +; /* Determine if an interrupt frame or a synchronous task suspension frame +; is present. */ +; + LDMIA sp!, {r4, r5} ; Pickup the stack type and saved CPSR + CMP r4, #0 ; Check for synchronous context switch + BEQ _tx_solicited_return + MSR SPSR_cxsf, r5 ; Setup SPSR for return +#ifdef __ARMVFP__ + LDR r1, [r0, #144] ; Pickup the VFP enabled flag + CMP r1, #0 ; Is the VFP enabled? + BEQ _tx_skip_interrupt_vfp_restore ; No, skip VFP interrupt restore + VLDMIA sp!, {D0-D15} ; Recover D0-D15 + VLDMIA sp!, {D16-D31} ; Recover D16-D31 + LDR r4, [sp], #4 ; Pickup FPSCR + VMSR FPSCR, r4 ; Restore FPSCR +_tx_skip_interrupt_vfp_restore +#endif + LDMIA sp!, {r0-r12, lr, pc}^ ; Return to point of thread interrupt + +_tx_solicited_return + +#ifdef __ARMVFP__ + LDR r1, [r0, #144] ; Pickup the VFP enabled flag + CMP r1, #0 ; Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_restore ; No, skip VFP solicited restore + VLDMIA sp!, {D8-D15} ; Recover D8-D15 + VLDMIA sp!, {D16-D31} ; Recover D16-D31 + LDR r4, [sp], #4 ; Pickup FPSCR + VMSR FPSCR, r4 ; Restore FPSCR +_tx_skip_solicited_vfp_restore +#endif + MSR CPSR_cxsf, r5 ; Recover CPSR + LDMIA sp!, {r4-r11, lr} ; Return to thread synchronously +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +; +;} +; + +#ifdef __ARMVFP__ + + RSEG .text:CODE:NOROOT(2) + PUBLIC tx_thread_vfp_enable + CODE32 +tx_thread_vfp_enable + MRS r2, CPSR ; Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if ; Enable IRQ and FIQ interrupts +#else + CPSID i ; Enable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0, #0] ; Pickup current thread pointer + CMP r1, #0 ; Check for NULL thread pointer + BEQ __tx_no_thread_to_enable ; If NULL, skip VFP enable + MOV r0, #1 ; Build enable value + STR r0, [r1, #144] ; Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_enable + MSR CPSR_cxsf, r2 ; Recover CPSR + BX LR ; Return to caller + + RSEG .text:CODE:NOROOT(2) + PUBLIC tx_thread_vfp_disable + CODE32 +tx_thread_vfp_disable + MRS r2, CPSR ; Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if ; Enable IRQ and FIQ interrupts +#else + CPSID i ; Enable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0, #0] ; Pickup current thread pointer + CMP r1, #0 ; Check for NULL thread pointer + BEQ __tx_no_thread_to_disable ; If NULL, skip VFP disable + MOV r0, #0 ; Build disable value + STR r0, [r1, #144] ; Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_disable + MSR CPSR_cxsf, r2 ; Recover CPSR + BX LR ; Return to caller + +#endif + + END + diff --git a/ports/cortex_a15/iar/src/tx_thread_stack_build.s b/ports/cortex_a15/iar/src/tx_thread_stack_build.s new file mode 100644 index 00000000..36be0f2d --- /dev/null +++ b/ports/cortex_a15/iar/src/tx_thread_stack_build.s @@ -0,0 +1,160 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +SVC_MODE DEFINE 0x13 ; SVC mode +#ifdef TX_ENABLE_FIQ_SUPPORT +CPSR_MASK DEFINE 0xDF ; Mask initial CPSR, IRQ & FIQ interrupts enabled +#else +CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ interrupts enabled +#endif + + EXTERN _tx_thread_schedule + +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-A15/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_stack_build + CODE32 +_tx_thread_stack_build +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-A15 should look like the following after it is built: +; +; Stack Top: 1 Interrupt stack frame type +; CPSR Initial value for CPSR +; a1 (r0) Initial value for a1 +; a2 (r1) Initial value for a2 +; a3 (r2) Initial value for a3 +; a4 (r3) Initial value for a4 +; v1 (r4) Initial value for v1 +; v2 (r5) Initial value for v2 +; v3 (r6) Initial value for v3 +; v4 (r7) Initial value for v4 +; v5 (r8) Initial value for v5 +; sb (r9) Initial value for sb +; sl (r10) Initial value for sl +; fp (r11) Initial value for fp +; ip (r12) Initial value for ip +; lr (r14) Initial value for lr +; pc (r15) Initial value for pc +; 0 For stack backtracing +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #7 ; Ensure 8-byte alignment + SUB r2, r2, #76 ; Allocate space for the stack frame +; +; /* Actually build the stack frame. */ +; + MOV r3, #1 ; Build interrupt stack type + STR r3, [r2, #0] ; Store stack type + MOV r3, #0 ; Build initial register value + STR r3, [r2, #8] ; Store initial r0 + STR r3, [r2, #12] ; Store initial r1 + STR r3, [r2, #16] ; Store initial r2 + STR r3, [r2, #20] ; Store initial r3 + STR r3, [r2, #24] ; Store initial r4 + STR r3, [r2, #28] ; Store initial r5 + STR r3, [r2, #32] ; Store initial r6 + STR r3, [r2, #36] ; Store initial r7 + STR r3, [r2, #40] ; Store initial r8 + STR r3, [r2, #44] ; Store initial r9 + LDR r3, [r0, #12] ; Pickup stack starting address + STR r3, [r2, #48] ; Store initial r10 + LDR r3,=_tx_thread_schedule ; Pickup address of _tx_thread_schedule for GDB backtrace + STR r3, [r2, #60] ; Store initial r14 (lr) + MOV r3, #0 ; Build initial register value + STR r3, [r2, #52] ; Store initial r11 + STR r3, [r2, #56] ; Store initial r12 + STR r1, [r2, #64] ; Store initial pc + STR r3, [r2, #68] ; 0 for back-trace + MRS r1, CPSR ; Pickup CPSR + BIC r1, r1, #CPSR_MASK ; Mask mode bits of CPSR + ORR r3, r1, #SVC_MODE ; Build CPSR, SVC mode, interrupts enabled + STR r3, [r2, #4] ; Store initial CPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +;} + + END + diff --git a/ports/cortex_a15/iar/src/tx_thread_system_return.s b/ports/cortex_a15/iar/src/tx_thread_system_return.s new file mode 100644 index 00000000..b64edbb1 --- /dev/null +++ b/ports/cortex_a15/iar/src/tx_thread_system_return.s @@ -0,0 +1,161 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +; + EXTERN _tx_thread_current_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_schedule + EXTERN _tx_execution_thread_exit +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-A15/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_system_return + CODE32 +_tx_thread_system_return +; +; /* Save minimal context on the stack. */ +; + STMDB sp!, {r4-r11, lr} ; Save minimal context + + LDR r4, =_tx_thread_current_ptr ; Pickup address of current ptr + LDR r5, [r4, #0] ; Pickup current thread pointer + +#ifdef __ARMVFP__ + LDR r1, [r5, #144] ; Pickup the VFP enabled flag + CMP r1, #0 ; Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_save ; No, skip VFP solicited save + VMRS r1, FPSCR ; Pickup the FPSCR + STR r1, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D8-D15} ; Save D8-D15 +_tx_skip_solicited_vfp_save +#endif + + MOV r0, #0 ; Build a solicited stack type + MRS r1, CPSR ; Pickup the CPSR + STMDB sp!, {r0-r1} ; Save type and CPSR +; +; /* Lockout interrupts. */ +; +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts +#else + CPSID i ; Disable IRQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + BL _tx_execution_thread_exit ; Call the thread exit function +#endif + MOV r3, r4 ; Pickup address of current ptr + MOV r0, r5 ; Pickup current thread pointer + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + LDR r1, [r2, #0] ; Pickup current time slice +; +; /* Save current stack and switch to system stack. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; sp = _tx_thread_system_stack_ptr; +; + STR sp, [r0, #8] ; Save thread stack pointer +; +; /* Determine if the time-slice is active. */ +; if (_tx_timer_time_slice) +; { +; + MOV r4, #0 ; Build clear value + CMP r1, #0 ; Is a time-slice active? + BEQ __tx_thread_dont_save_ts ; No, don't save the time-slice +; +; /* Save time-slice for the thread and clear the current time-slice. */ +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r4, [r2, #0] ; Clear time-slice + STR r1, [r0, #24] ; Save current time-slice +; +; } +__tx_thread_dont_save_ts +; +; /* Clear the current thread pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + STR r4, [r3, #0] ; Clear current thread pointer + B _tx_thread_schedule ; Jump to scheduler! +; +;} + + END + diff --git a/ports/cortex_a15/iar/src/tx_thread_vectored_context_save.s b/ports/cortex_a15/iar/src/tx_thread_vectored_context_save.s new file mode 100644 index 00000000..8b83e988 --- /dev/null +++ b/ports/cortex_a15/iar/src/tx_thread_vectored_context_save.s @@ -0,0 +1,188 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN _tx_execution_isr_enter +; +; +; + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save Cortex-A15/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_vectored_context_save(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_vectored_context_save + CODE32 +_tx_thread_vectored_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts +#endif + LDR r3, =_tx_thread_system_state ; Pickup address of system state variable + LDR r2, [r3, #0] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Note: Minimal context of interrupted thread is already saved. */ +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + MOV pc, lr ; Return to caller +; +__tx_thread_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + ; scheduling loop - nothing needs saving! +; +; /* Note: Minimal context of interrupted thread is already saved. */ +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + MOV pc, lr ; Return to caller +; +; } +; else +; { +; +__tx_thread_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; processing. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + ADD sp, sp, #32 ; Recover saved registers + MOV pc, lr ; Return to caller +; +; } +;} + + END + diff --git a/ports/cortex_a15/iar/src/tx_timer_interrupt.s b/ports/cortex_a15/iar/src/tx_timer_interrupt.s new file mode 100644 index 00000000..580fc9f9 --- /dev/null +++ b/ports/cortex_a15/iar/src/tx_timer_interrupt.s @@ -0,0 +1,260 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_timer.h" +;#include "tx_thread.h" +; +; +; +;/* Define Assembly language external references... */ +; + EXTERN _tx_timer_time_slice + EXTERN _tx_timer_system_clock + EXTERN _tx_timer_current_ptr + EXTERN _tx_timer_list_start + EXTERN _tx_timer_list_end + EXTERN _tx_timer_expiration_process + EXTERN _tx_timer_expired_time_slice + EXTERN _tx_timer_expired + EXTERN _tx_thread_time_slice +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-A15/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_timer_interrupt + CODE32 +_tx_timer_interrupt +; +; /* Upon entry to this routine, it is assumed that context save has already +; been called, and therefore the compiler scratch registers are available +; for use. */ +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + LDR r1, =_tx_timer_system_clock ; Pickup address of system clock + LDR r0, [r1, #0] ; Pickup system clock + ADD r0, r0, #1 ; Increment system clock + STR r0, [r1, #0] ; Store new system clock +; +; /* Test for time-slice expiration. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r2, [r3, #0] ; Pickup time-slice + CMP r2, #0 ; Is it non-active? + BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing +; +; /* Decrement the time_slice. */ +; _tx_timer_time_slice--; +; + SUB r2, r2, #1 ; Decrement the time-slice + STR r2, [r3, #0] ; Store new time-slice value +; +; /* Check for expiration. */ +; if (__tx_timer_time_slice == 0) +; + CMP r2, #0 ; Has it expired? + BNE __tx_timer_no_time_slice ; No, skip expiration processing +; +; /* Set the time-slice expired flag. */ +; _tx_timer_expired_time_slice = TX_TRUE; +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup address of expired flag + MOV r0, #1 ; Build expired value + STR r0, [r3, #0] ; Set time-slice expiration flag +; +; } +; +__tx_timer_no_time_slice +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + LDR r1, =_tx_timer_current_ptr ; Pickup current timer pointer address + LDR r0, [r1, #0] ; Pickup current timer + LDR r2, [r0, #0] ; Pickup timer list entry + CMP r2, #0 ; Is there anything in the list? + BEQ __tx_timer_no_timer ; No, just increment the timer +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + LDR r3, =_tx_timer_expired ; Pickup expiration flag address + MOV r2, #1 ; Build expired value + STR r2, [r3, #0] ; Set expired flag + B __tx_timer_done ; Finished timer processing +; +; } +; else +; { +__tx_timer_no_timer +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ADD r0, r0, #4 ; Move to next timer +; +; /* Check for wraparound. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + LDR r3, =_tx_timer_list_end ; Pickup address of timer list end + LDR r2, [r3, #0] ; Pickup list end + CMP r0, r2 ; Are we at list end? + BNE __tx_timer_skip_wrap ; No, skip wraparound logic +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + LDR r3, =_tx_timer_list_start ; Pickup address of timer list start + LDR r0, [r3, #0] ; Set current pointer to list start +; +__tx_timer_skip_wrap +; + STR r0, [r1, #0] ; Store new current timer pointer +; } +; +__tx_timer_done +; +; +; /* See if anything has expired. */ +; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup address of expired flag + LDR r2, [r3, #0] ; Pickup time-slice expired flag + CMP r2, #0 ; Did a time-slice expire? + BNE __tx_something_expired ; If non-zero, time-slice expired + LDR r1, =_tx_timer_expired ; Pickup address of other expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Did a timer expire? + BEQ __tx_timer_nothing_expired ; No, nothing expired +; +__tx_something_expired +; +; + STMDB sp!, {r0, lr} ; Save the lr register on the stack + ; and save r0 just to keep 8-byte alignment +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + LDR r1, =_tx_timer_expired ; Pickup address of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Check for timer expiration + BEQ __tx_timer_dont_activate ; If not set, skip timer activation +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + BL _tx_timer_expiration_process ; Call the timer expiration handling routine +; +; } +__tx_timer_dont_activate +; +; /* Did time slice expire? */ +; if (_tx_timer_expired_time_slice) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup address of time-slice expired + LDR r2, [r3, #0] ; Pickup the actual flag + CMP r2, #0 ; See if the flag is set + BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing +; +; /* Time slice interrupted thread. */ +; _tx_thread_time_slice(); +; + BL _tx_thread_time_slice ; Call time-slice processing +; +; } +; +__tx_timer_not_ts_expiration +; + LDMIA sp!, {r0, lr} ; Recover lr register (r0 is just there for + ; the 8-byte stack alignment +; +; } +; +__tx_timer_nothing_expired +; +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +; +;} + + END + diff --git a/ports/cortex_a35/ac6/example_build/sample_threadx/.cproject b/ports/cortex_a35/ac6/example_build/sample_threadx/.cproject new file mode 100644 index 00000000..61a52f7b --- /dev/null +++ b/ports/cortex_a35/ac6/example_build/sample_threadx/.cproject @@ -0,0 +1,230 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_a35/ac6/example_build/sample_threadx/.project b/ports/cortex_a35/ac6/example_build/sample_threadx/.project new file mode 100644 index 00000000..a1b15572 --- /dev/null +++ b/ports/cortex_a35/ac6/example_build/sample_threadx/.project @@ -0,0 +1,26 @@ + + + sample_threadx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/ports/cortex_a35/ac6/example_build/sample_threadx/.settings/language.settings.xml b/ports/cortex_a35/ac6/example_build/sample_threadx/.settings/language.settings.xml new file mode 100644 index 00000000..16ac1af8 --- /dev/null +++ b/ports/cortex_a35/ac6/example_build/sample_threadx/.settings/language.settings.xml @@ -0,0 +1,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_a35/ac6/example_build/sample_threadx/GICv3.h b/ports/cortex_a35/ac6/example_build/sample_threadx/GICv3.h new file mode 100644 index 00000000..23bc7fd8 --- /dev/null +++ b/ports/cortex_a35/ac6/example_build/sample_threadx/GICv3.h @@ -0,0 +1,561 @@ +/* + * GICv3.h - data types and function prototypes for GICv3 utility routines + * + * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. + * Use, modification and redistribution of this file is subject to your possession of a + * valid End User License Agreement for the Arm Product of which these examples are part of + * and your compliance with all applicable terms and conditions of such licence agreement. + */ +#ifndef GICV3_h +#define GICV3_h + +#include + +/* + * extra flags for GICD enable + */ +typedef enum +{ + gicdctlr_EnableGrp0 = (1 << 0), + gicdctlr_EnableGrp1NS = (1 << 1), + gicdctlr_EnableGrp1A = (1 << 1), + gicdctlr_EnableGrp1S = (1 << 2), + gicdctlr_EnableAll = (1 << 2) | (1 << 1) | (1 << 0), + gicdctlr_ARE_S = (1 << 4), /* Enable Secure state affinity routing */ + gicdctlr_ARE_NS = (1 << 5), /* Enable Non-Secure state affinity routing */ + gicdctlr_DS = (1 << 6), /* Disable Security support */ + gicdctlr_E1NWF = (1 << 7) /* Enable "1-of-N" wakeup model */ +} GICDCTLRFlags_t; + +/* + * modes for SPI routing + */ +typedef enum +{ + gicdirouter_ModeSpecific = 0, + gicdirouter_ModeAny = (1 << 31) +} GICDIROUTERBits_t; + +typedef enum +{ + gicdicfgr_Level = 0, + gicdicfgr_Edge = (1 << 1) +} GICDICFGRBits_t; + +typedef enum +{ + gicigroupr_G0S = 0, + gicigroupr_G1NS = (1 << 0), + gicigroupr_G1S = (1 << 2) +} GICIGROUPRBits_t; + +typedef enum +{ + gicrwaker_ProcessorSleep = (1 << 1), + gicrwaker_ChildrenAsleep = (1 << 2) +} GICRWAKERBits_t; + +/**********************************************************************/ + +/* + * Utility macros & functions + */ +#define RANGE_LIMIT(x) ((sizeof(x) / sizeof((x)[0])) - 1) + +static inline uint64_t gicv3PackAffinity(uint32_t aff3, uint32_t aff2, + uint32_t aff1, uint32_t aff0) +{ + /* + * only need to cast aff3 to get type promotion for all affinities + */ + return ((((uint64_t)aff3 & 0xff) << 32) | + ((aff2 & 0xff) << 16) | + ((aff1 & 0xff) << 8) | aff0); +} + +/**********************************************************************/ + +/* + * GIC Distributor Function Prototypes + */ + +/* + * ConfigGICD - configure GIC Distributor prior to enabling it + * + * Inputs: + * + * control - control flags + * + * Returns: + * + * + * + * NOTE: + * + * ConfigGICD() will set an absolute flags value, whereas + * {En,Dis}ableGICD() will only {set,clear} the flag bits + * passed as a parameter + */ +void ConfigGICD(GICDCTLRFlags_t flags); + +/* + * EnableGICD - top-level enable for GIC Distributor + * + * Inputs: + * + * flags - new control flags to set + * + * Returns: + * + * + * + * NOTE: + * + * ConfigGICD() will set an absolute flags value, whereas + * {En,Dis}ableGICD() will only {set,clear} the flag bits + * passed as a parameter + */ +void EnableGICD(GICDCTLRFlags_t flags); + +/* + * DisableGICD - top-level disable for GIC Distributor + * + * Inputs + * + * flags - control flags to clear + * + * Returns + * + * + * + * NOTE: + * + * ConfigGICD() will set an absolute flags value, whereas + * {En,Dis}ableGICD() will only {set,clear} the flag bits + * passed as a parameter + */ +void DisableGICD(GICDCTLRFlags_t flags); + +/* + * SyncAREinGICD - synchronise GICD Address Routing Enable bits + * + * Inputs + * + * flags - absolute flag bits to set in GIC Distributor + * + * dosync - flag whether to wait for ARE bits to match passed + * flag field (dosync = true), or whether to set absolute + * flag bits (dosync = false) + * + * Returns + * + * + * + * NOTE: + * + * This function is used to resolve a race in an MP system whereby secondary + * CPUs cannot reliably program all Redistributor registers until the + * primary CPU has enabled Address Routing. The primary CPU will call this + * function with dosync = false, while the secondaries will call it with + * dosync = true. + */ +void SyncAREinGICD(GICDCTLRFlags_t flags, uint32_t dosync); + +/* + * EnableSPI - enable a specific shared peripheral interrupt + * + * Inputs: + * + * id - which interrupt to enable + * + * Returns: + * + * + */ +void EnableSPI(uint32_t id); + +/* + * DisableSPI - disable a specific shared peripheral interrupt + * + * Inputs: + * + * id - which interrupt to disable + * + * Returns: + * + * + */ +void DisableSPI(uint32_t id); + +/* + * SetSPIPriority - configure the priority for a shared peripheral interrupt + * + * Inputs: + * + * id - interrupt identifier + * + * priority - 8-bit priority to program (see note below) + * + * Returns: + * + * + * + * Note: + * + * The GICv3 architecture makes this function sensitive to the Security + * context in terms of what effect it has on the programmed priority: no + * attempt is made to adjust for the reduced priority range available + * when making Non-Secure accesses to the GIC + */ +void SetSPIPriority(uint32_t id, uint32_t priority); + +/* + * GetSPIPriority - determine the priority for a shared peripheral interrupt + * + * Inputs: + * + * id - interrupt identifier + * + * Returns: + * + * interrupt priority in the range 0 - 0xff + */ +uint32_t GetSPIPriority(uint32_t id); + +/* + * SetSPIRoute - specify interrupt routing when gicdctlr_ARE is enabled + * + * Inputs: + * + * id - interrupt identifier + * + * affinity - prepacked "dotted quad" affinity routing. NOTE: use the + * gicv3PackAffinity() helper routine to generate this input + * + * mode - select routing mode (specific affinity, or any recipient) + * + * Returns: + * + * + */ +void SetSPIRoute(uint32_t id, uint64_t affinity, GICDIROUTERBits_t mode); + +/* + * GetSPIRoute - read ARE-enabled interrupt routing information + * + * Inputs: + * + * id - interrupt identifier + * + * Returns: + * + * routing configuration + */ +uint64_t GetSPIRoute(uint32_t id); + +/* + * SetSPITarget - configure the set of processor targets for an interrupt + * + * Inputs + * + * id - interrupt identifier + * + * target - 8-bit target bitmap + * + * Returns + * + * + */ +void SetSPITarget(uint32_t id, uint32_t target); + +/* + * GetSPITarget - read the set of processor targets for an interrupt + * + * Inputs + * + * id - interrupt identifier + * + * Returns + * + * 8-bit target bitmap + */ +uint32_t GetSPITarget(uint32_t id); + +/* + * ConfigureSPI - setup an interrupt as edge- or level-triggered + * + * Inputs + * + * id - interrupt identifier + * + * config - desired configuration + * + * Returns + * + * + */ +void ConfigureSPI(uint32_t id, GICDICFGRBits_t config); + +/* + * SetSPIPending - mark an interrupt as pending + * + * Inputs + * + * id - interrupt identifier + * + * Returns + * + * + */ +void SetSPIPending(uint32_t id); + +/* + * ClearSPIPending - mark an interrupt as not pending + * + * Inputs + * + * id - interrupt identifier + * + * Returns + * + * + */ +void ClearSPIPending(uint32_t id); + +/* + * GetSPIPending - query whether an interrupt is pending + * + * Inputs + * + * id - interrupt identifier + * + * Returns + * + * pending status + */ +uint32_t GetSPIPending(uint32_t id); + +/* + * SetSPISecurity - mark a shared peripheral interrupt as + * security + * + * Inputs + * + * id - which interrupt to mark + * + * group - the group for the interrupt + * + * Returns + * + * + */ +void SetSPISecurity(uint32_t id, GICIGROUPRBits_t group); + +/* + * SetSPISecurityBlock - mark a block of 32 shared peripheral + * interrupts as security + * + * Inputs: + * + * block - which block to mark (e.g. 1 = Ints 32-63) + * + * group - the group for the interrupts + * + * Returns: + * + * + */ +void SetSPISecurityBlock(uint32_t block, GICIGROUPRBits_t group); + +/* + * SetSPISecurityAll - mark all shared peripheral interrupts + * as security + * + * Inputs: + * + * group - the group for the interrupts + * + * Returns: + * + * + */ +void SetSPISecurityAll(GICIGROUPRBits_t group); + +/**********************************************************************/ + +/* + * GIC Re-Distributor Function Prototypes + * + * The model for calling Redistributor functions is that, rather than + * identifying the target redistributor with every function call, the + * SelectRedistributor() function is used to identify which redistributor + * is to be used for all functions until a different redistributor is + * explicitly selected + */ + +/* + * WakeupGICR - wake up a Redistributor + * + * Inputs: + * + * gicr - which Redistributor to wakeup + * + * Returns: + * + * + */ +void WakeupGICR(uint32_t gicr); + +/* + * EnablePrivateInt - enable a private (SGI/PPI) interrupt + * + * Inputs: + * + * gicr - which Redistributor to program + * + * id - which interrupt to enable + * + * Returns: + * + * + */ +void EnablePrivateInt(uint32_t gicr, uint32_t id); + +/* + * DisablePrivateInt - disable a private (SGI/PPI) interrupt + * + * Inputs: + * + * gicr - which Redistributor to program + * + * id - which interrupt to disable + * + * Returns: + * + * + */ +void DisablePrivateInt(uint32_t gicr, uint32_t id); + +/* + * SetPrivateIntPriority - configure the priority for a private + * (SGI/PPI) interrupt + * + * Inputs: + * + * gicr - which Redistributor to program + * + * id - interrupt identifier + * + * priority - 8-bit priority to program (see note below) + * + * Returns: + * + * + * + * Note: + * + * The GICv3 architecture makes this function sensitive to the Security + * context in terms of what effect it has on the programmed priority: no + * attempt is made to adjust for the reduced priority range available + * when making Non-Secure accesses to the GIC + */ +void SetPrivateIntPriority(uint32_t gicr, uint32_t id, uint32_t priority); + +/* + * GetPrivateIntPriority - configure the priority for a private + * (SGI/PPI) interrupt + * + * Inputs: + * + * gicr - which Redistributor to program + * + * id - interrupt identifier + * + * Returns: + * + * Int priority + */ +uint32_t GetPrivateIntPriority(uint32_t gicr, uint32_t id); + +/* + * SetPrivateIntPending - mark a private (SGI/PPI) interrupt as pending + * + * Inputs + * + * gicr - which Redistributor to program + * + * id - interrupt identifier + * + * Returns + * + * + */ +void SetPrivateIntPending(uint32_t gicr, uint32_t id); + +/* + * ClearPrivateIntPending - mark a private (SGI/PPI) interrupt as not pending + * + * Inputs + * + * gicr - which Redistributor to program + * + * id - interrupt identifier + * + * Returns + * + * + */ +void ClearPrivateIntPending(uint32_t gicr, uint32_t id); + +/* + * GetPrivateIntPending - query whether a private (SGI/PPI) interrupt is pending + * + * Inputs + * + * gicr - which Redistributor to program + * + * id - interrupt identifier + * + * Returns + * + * pending status + */ +uint32_t GetPrivateIntPending(uint32_t gicr, uint32_t id); + +/* + * SetPrivateIntSecurity - mark a private (SGI/PPI) interrupt as + * security + * + * Inputs + * + * gicr - which Redistributor to program + * + * id - which interrupt to mark + * + * group - the group for the interrupt + * + * Returns + * + * + */ +void SetPrivateIntSecurity(uint32_t gicr, uint32_t id, GICIGROUPRBits_t group); + +/* + * SetPrivateIntSecurityBlock - mark all 32 private (SGI/PPI) + * interrupts as security + * + * Inputs: + * + * gicr - which Redistributor to program + * + * group - the group for the interrupt + * + * Returns: + * + * + */ +void SetPrivateIntSecurityBlock(uint32_t gicr, GICIGROUPRBits_t group); + +#endif /* ndef GICV3_h */ + +/* EOF GICv3.h */ diff --git a/ports/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicc.h b/ports/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicc.h new file mode 100644 index 00000000..8e6f0acc --- /dev/null +++ b/ports/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicc.h @@ -0,0 +1,249 @@ +/* + * GICv3_gicc.h - prototypes and inline functions for GICC system register operations + * + * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. + * Use, modification and redistribution of this file is subject to your possession of a + * valid End User License Agreement for the Arm Product of which these examples are part of + * and your compliance with all applicable terms and conditions of such licence agreement. + */ +#ifndef GICV3_gicc_h +#define GICV3_gicc_h + +/**********************************************************************/ + +typedef enum +{ + sreSRE = (1 << 0), + sreDFB = (1 << 1), + sreDIB = (1 << 2), + sreEnable = (1 << 3) +} ICC_SREBits_t; + +static inline void setICC_SRE_EL1(ICC_SREBits_t mode) +{ + asm("msr ICC_SRE_EL1, %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline uint64_t getICC_SRE_EL1(void) +{ + uint64_t retc; + + asm("mrs %0, ICC_SRE_EL1\n" : "=r" (retc)); + + return retc; +} + +static inline void setICC_SRE_EL2(ICC_SREBits_t mode) +{ + asm("msr ICC_SRE_EL2, %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline uint64_t getICC_SRE_EL2(void) +{ + uint64_t retc; + + asm("mrs %0, ICC_SRE_EL2\n" : "=r" (retc)); + + return retc; +} + +static inline void setICC_SRE_EL3(ICC_SREBits_t mode) +{ + asm("msr ICC_SRE_EL3, %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline uint64_t getICC_SRE_EL3(void) +{ + uint64_t retc; + + asm("mrs %0, ICC_SRE_EL3\n" : "=r" (retc)); + + return retc; +} + +/**********************************************************************/ + +typedef enum +{ + igrpEnable = (1 << 0), + igrpEnableGrp1NS = (1 << 0), + igrpEnableGrp1S = (1 << 2) +} ICC_IGRPBits_t; + +static inline void setICC_IGRPEN0_EL1(ICC_IGRPBits_t mode) +{ + asm("msr ICC_IGRPEN0_EL1, %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline void setICC_IGRPEN1_EL1(ICC_IGRPBits_t mode) +{ + asm("msr ICC_IGRPEN1_EL1, %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline void setICC_IGRPEN1_EL3(ICC_IGRPBits_t mode) +{ + asm("msr ICC_IGRPEN1_EL3, %0\n; isb" :: "r" ((uint64_t)mode)); +} + +/**********************************************************************/ + +typedef enum +{ + ctlrCBPR = (1 << 0), + ctlrCBPR_EL1S = (1 << 0), + ctlrEOImode = (1 << 1), + ctlrCBPR_EL1NS = (1 << 1), + ctlrEOImode_EL3 = (1 << 2), + ctlrEOImode_EL1S = (1 << 3), + ctlrEOImode_EL1NS = (1 << 4), + ctlrRM = (1 << 5), + ctlrPMHE = (1 << 6) +} ICC_CTLRBits_t; + +static inline void setICC_CTLR_EL1(ICC_CTLRBits_t mode) +{ + asm("msr ICC_CTLR_EL1, %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline uint64_t getICC_CTLR_EL1(void) +{ + uint64_t retc; + + asm("mrs %0, ICC_CTLR_EL1\n" : "=r" (retc)); + + return retc; +} + +static inline void setICC_CTLR_EL3(ICC_CTLRBits_t mode) +{ + asm("msr ICC_CTLR_EL3, %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline uint64_t getICC_CTLR_EL3(void) +{ + uint64_t retc; + + asm("mrs %0, ICC_CTLR_EL3\n" : "=r" (retc)); + + return retc; +} + +/**********************************************************************/ + +static inline uint64_t getICC_IAR0(void) +{ + uint64_t retc; + + asm("mrs %0, ICC_IAR0_EL1\n" : "=r" (retc)); + + return retc; +} + +static inline uint64_t getICC_IAR1(void) +{ + uint64_t retc; + + asm("mrs %0, ICC_IAR1_EL1\n" : "=r" (retc)); + + return retc; +} + +static inline void setICC_EOIR0(uint32_t interrupt) +{ + asm("msr ICC_EOIR0_EL1, %0\n; isb" :: "r" ((uint64_t)interrupt)); +} + +static inline void setICC_EOIR1(uint32_t interrupt) +{ + asm("msr ICC_EOIR1_EL1, %0\n; isb" :: "r" ((uint64_t)interrupt)); +} + +static inline void setICC_DIR(uint32_t interrupt) +{ + asm("msr ICC_DIR_EL1, %0\n; isb" :: "r" ((uint64_t)interrupt)); +} + +static inline void setICC_PMR(uint32_t priority) +{ + asm("msr ICC_PMR_EL1, %0\n; isb" :: "r" ((uint64_t)priority)); +} + +static inline void setICC_BPR0(uint32_t binarypoint) +{ + asm("msr ICC_BPR0_EL1, %0\n; isb" :: "r" ((uint64_t)binarypoint)); +} + +static inline void setICC_BPR1(uint32_t binarypoint) +{ + asm("msr ICC_BPR1_EL1, %0\n; isb" :: "r" ((uint64_t)binarypoint)); +} + +static inline uint64_t getICC_BPR0(void) +{ + uint64_t retc; + + asm("mrs %0, ICC_BPR0_EL1\n" : "=r" (retc)); + + return retc; +} + +static inline uint64_t getICC_BPR1(void) +{ + uint64_t retc; + + asm("mrs %0, ICC_BPR1_EL1\n" : "=r" (retc)); + + return retc; +} + +static inline uint64_t getICC_RPR(void) +{ + uint64_t retc; + + asm("mrs %0, ICC_RPR_EL1\n" : "=r" (retc)); + + return retc; +} + +/**********************************************************************/ + +typedef enum +{ + sgirIRMTarget = 0, + sgirIRMAll = (1ull << 40) +} ICC_SGIRBits_t; + +static inline void setICC_SGI0R(uint8_t aff3, uint8_t aff2, + uint8_t aff1, ICC_SGIRBits_t irm, + uint16_t targetlist, uint8_t intid) +{ + uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \ + ((uint64_t)aff1 << 16) | irm | targetlist | \ + ((uint64_t)(intid & 0x0f) << 24)); + + asm("msr ICC_SGI0R_EL1, %0\n; isb" :: "r" (packedbits)); +} + +static inline void setICC_SGI1R(uint8_t aff3, uint8_t aff2, + uint8_t aff1, ICC_SGIRBits_t irm, + uint16_t targetlist, uint8_t intid) +{ + uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \ + ((uint64_t)aff1 << 16) | irm | targetlist | \ + ((uint64_t)(intid & 0x0f) << 24)); + + asm("msr ICC_SGI1R_EL1, %0\n; isb" :: "r" (packedbits)); +} + +static inline void setICC_ASGI1R(uint8_t aff3, uint8_t aff2, + uint8_t aff1, ICC_SGIRBits_t irm, + uint16_t targetlist, uint8_t intid) +{ + uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \ + ((uint64_t)aff1 << 16) | irm | targetlist | \ + ((uint64_t)(intid & 0x0f) << 24)); + + asm("msr ICC_ASGI1R_EL1, %0\n; isb" :: "r" (packedbits)); +} + +#endif /* ndef GICV3_gicc_h */ diff --git a/ports/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicd.c b/ports/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicd.c new file mode 100644 index 00000000..3bfb4a93 --- /dev/null +++ b/ports/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicd.c @@ -0,0 +1,339 @@ +/* + * GICv3_gicd.c - generic driver code for GICv3 distributor + * + * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. + * Use, modification and redistribution of this file is subject to your possession of a + * valid End User License Agreement for the Arm Product of which these examples are part of + * and your compliance with all applicable terms and conditions of such licence agreement. + */ +#include + +#include "GICv3.h" + +typedef struct +{ + volatile uint32_t GICD_CTLR; // +0x0000 + const volatile uint32_t GICD_TYPER; // +0x0004 + const volatile uint32_t GICD_IIDR; // +0x0008 + + const volatile uint32_t padding0; // +0x000c + + volatile uint32_t GICD_STATUSR; // +0x0010 + + const volatile uint32_t padding1[3]; // +0x0014 + + volatile uint32_t IMP_DEF[8]; // +0x0020 + + volatile uint32_t GICD_SETSPI_NSR; // +0x0040 + const volatile uint32_t padding2; // +0x0044 + volatile uint32_t GICD_CLRSPI_NSR; // +0x0048 + const volatile uint32_t padding3; // +0x004c + volatile uint32_t GICD_SETSPI_SR; // +0x0050 + const volatile uint32_t padding4; // +0x0054 + volatile uint32_t GICD_CLRSPI_SR; // +0x0058 + + const volatile uint32_t padding5[3]; // +0x005c + + volatile uint32_t GICD_SEIR; // +0x0068 + + const volatile uint32_t padding6[5]; // +0x006c + + volatile uint32_t GICD_IGROUPR[32]; // +0x0080 + + volatile uint32_t GICD_ISENABLER[32]; // +0x0100 + volatile uint32_t GICD_ICENABLER[32]; // +0x0180 + volatile uint32_t GICD_ISPENDR[32]; // +0x0200 + volatile uint32_t GICD_ICPENDR[32]; // +0x0280 + volatile uint32_t GICD_ISACTIVER[32]; // +0x0300 + volatile uint32_t GICD_ICACTIVER[32]; // +0x0380 + + volatile uint8_t GICD_IPRIORITYR[1024]; // +0x0400 + volatile uint8_t GICD_ITARGETSR[1024]; // +0x0800 + volatile uint32_t GICD_ICFGR[64]; // +0x0c00 + volatile uint32_t GICD_IGRPMODR[32]; // +0x0d00 + const volatile uint32_t padding7[32]; // +0x0d80 + volatile uint32_t GICD_NSACR[64]; // +0x0e00 + + volatile uint32_t GICD_SGIR; // +0x0f00 + + const volatile uint32_t padding8[3]; // +0x0f04 + + volatile uint32_t GICD_CPENDSGIR[4]; // +0x0f10 + volatile uint32_t GICD_SPENDSGIR[4]; // +0x0f20 + + const volatile uint32_t padding9[52]; // +0x0f30 + const volatile uint32_t padding10[5120]; // +0x1000 + + volatile uint64_t GICD_IROUTER[1024]; // +0x6000 +} GICv3_distributor; + +/* + * use the scatter file to place GICD + */ +static GICv3_distributor __attribute__((section(".bss.distributor"))) gicd; + +void ConfigGICD(GICDCTLRFlags_t flags) +{ + gicd.GICD_CTLR = flags; +} + +void EnableGICD(GICDCTLRFlags_t flags) +{ + gicd.GICD_CTLR |= flags; +} + +void DisableGICD(GICDCTLRFlags_t flags) +{ + gicd.GICD_CTLR &= ~flags; +} + +void SyncAREinGICD(GICDCTLRFlags_t flags, uint32_t dosync) +{ + if (dosync) + { + const uint32_t tmask = gicdctlr_ARE_S | gicdctlr_ARE_NS; + const uint32_t tval = flags & tmask; + + while ((gicd.GICD_CTLR & tmask) != tval) + continue; + } + else + gicd.GICD_CTLR = flags; +} + +void EnableSPI(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_ISENABLER has 32 interrupts per register + */ + bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); + id &= 32 - 1; + + gicd.GICD_ISENABLER[bank] = 1 << id; + + return; +} + +void DisableSPI(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_ISENABLER has 32 interrupts per register + */ + bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); + id &= 32 - 1; + + gicd.GICD_ICENABLER[bank] = 1 << id; + + return; +} + +void SetSPIPriority(uint32_t id, uint32_t priority) +{ + uint32_t bank; + + /* + * GICD_IPRIORITYR has one byte-wide entry per interrupt + */ + bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR); + + gicd.GICD_IPRIORITYR[bank] = priority; +} + +uint32_t GetSPIPriority(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_IPRIORITYR has one byte-wide entry per interrupt + */ + bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR); + + return (uint32_t)(gicd.GICD_IPRIORITYR[bank]); +} + +void SetSPIRoute(uint32_t id, uint64_t affinity, GICDIROUTERBits_t mode) +{ + uint32_t bank; + + /* + * GICD_IROUTER has one doubleword-wide entry per interrupt + */ + bank = id & RANGE_LIMIT(gicd.GICD_IROUTER); + + gicd.GICD_IROUTER[bank] = affinity | (uint64_t)mode; +} + +uint64_t GetSPIRoute(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_IROUTER has one doubleword-wide entry per interrupt + */ + bank = id & RANGE_LIMIT(gicd.GICD_IROUTER); + + return gicd.GICD_IROUTER[bank]; +} + +void SetSPITarget(uint32_t id, uint32_t target) +{ + uint32_t bank; + + /* + * GICD_ITARGETSR has one byte-wide entry per interrupt + */ + bank = id & RANGE_LIMIT(gicd.GICD_ITARGETSR); + + gicd.GICD_ITARGETSR[bank] = target; +} + +uint32_t GetSPITarget(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_ITARGETSR has one byte-wide entry per interrupt + */ + /* + * GICD_ITARGETSR has 4 interrupts per register, i.e. 8-bits of + * target bitmap per register + */ + bank = id & RANGE_LIMIT(gicd.GICD_ITARGETSR); + + return (uint32_t)(gicd.GICD_ITARGETSR[bank]); +} + +void ConfigureSPI(uint32_t id, GICDICFGRBits_t config) +{ + uint32_t bank, tmp; + + /* + * GICD_ICFGR has 16 interrupts per register, i.e. 2-bits of + * configuration per register + */ + bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); + config &= 3; + + id = (id & 0xf) << 1; + + tmp = gicd.GICD_ICFGR[bank]; + tmp &= ~(3 << id); + tmp |= config << id; + gicd.GICD_ICFGR[bank] = tmp; +} + +void SetSPIPending(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_ISPENDR has 32 interrupts per register + */ + bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISPENDR); + id &= 0x1f; + + gicd.GICD_ISPENDR[bank] = 1 << id; +} + +void ClearSPIPending(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_ICPENDR has 32 interrupts per register + */ + bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICPENDR); + id &= 0x1f; + + gicd.GICD_ICPENDR[bank] = 1 << id; +} + +uint32_t GetSPIPending(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_ICPENDR has 32 interrupts per register + */ + bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICPENDR); + id &= 0x1f; + + return (gicd.GICD_ICPENDR[bank] >> id) & 1; +} + +void SetSPISecurity(uint32_t id, GICIGROUPRBits_t group) +{ + uint32_t bank, groupmod; + + /* + * GICD_IGROUPR has 32 interrupts per register + */ + bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_IGROUPR); + id &= 0x1f; + + /* + * the single group argument is split into two separate + * registers, so filter out and remove the (new to gicv3) + * group modifier bit + */ + groupmod = (group >> 1) & 1; + group &= 1; + + /* + * either set or clear the Group bit for the interrupt as appropriate + */ + if (group) + gicd.GICD_IGROUPR[bank] |= 1 << id; + else + gicd.GICD_IGROUPR[bank] &= ~(1 << id); + + /* + * now deal with groupmod + */ + if (groupmod) + gicd.GICD_IGRPMODR[bank] |= 1 << id; + else + gicd.GICD_IGRPMODR[bank] &= ~(1 << id); +} + +void SetSPISecurityBlock(uint32_t block, GICIGROUPRBits_t group) +{ + uint32_t groupmod; + const uint32_t nbits = (sizeof group * 8) - 1; + + /* + * GICD_IGROUPR has 32 interrupts per register + */ + block &= RANGE_LIMIT(gicd.GICD_IGROUPR); + + /* + * get each bit of group config duplicated over all 32-bits in a word + */ + groupmod = (uint32_t)(((int32_t)group << (nbits - 1)) >> 31); + group = (uint32_t)(((int32_t)group << nbits) >> 31); + + /* + * set the security state for this block of SPIs + */ + gicd.GICD_IGROUPR[block] = group; + gicd.GICD_IGRPMODR[block] = groupmod; +} + +void SetSPISecurityAll(GICIGROUPRBits_t group) +{ + uint32_t block; + + /* + * GICD_TYPER.ITLinesNumber gives (No. SPIS / 32) - 1, and we + * want to iterate over all blocks excluding 0 (which are the + * SGI/PPI interrupts, and not relevant here) + */ + for (block = (gicd.GICD_TYPER & ((1 << 5) - 1)); block > 0; --block) + SetSPISecurityBlock(block, group); +} + +/* EOF GICv3_gicd.c */ diff --git a/ports/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicr.c b/ports/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicr.c new file mode 100644 index 00000000..7b437b18 --- /dev/null +++ b/ports/cortex_a35/ac6/example_build/sample_threadx/GICv3_gicr.c @@ -0,0 +1,308 @@ +/* + * GICv3_gicr.c - generic driver code for GICv3 redistributor + * + * Copyright (c) 2014-2019 Arm Limited (or its affiliates). All rights reserved. + * Use, modification and redistribution of this file is subject to your possession of a + * valid End User License Agreement for the Arm Product of which these examples are part of + * and your compliance with all applicable terms and conditions of such licence agreement. + */ +#include "GICv3.h" + +/* + * physical LPI Redistributor register map + */ +typedef struct +{ + volatile uint32_t GICR_CTLR; // +0x0000 - RW - Redistributor Control Register + const volatile uint32_t GICR_IIDR; // +0x0004 - RO - Implementer Identification Register + const volatile uint32_t GICR_TYPER[2]; // +0x0008 - RO - Redistributor Type Register + volatile uint32_t GICR_STATUSR; // +0x0010 - RW - Error Reporting Status Register, optional + volatile uint32_t GICR_WAKER; // +0x0014 - RW - Redistributor Wake Register + const volatile uint32_t padding1[2]; // +0x0018 - RESERVED +#ifndef USE_GIC600 + volatile uint32_t IMPDEF1[8]; // +0x0020 - ?? - IMPLEMENTATION DEFINED +#else + volatile uint32_t GICR_FCTLR; // +0x0020 - RW - Function Control Register + volatile uint32_t GICR_PWRR; // +0x0024 - RW - Power Management Control Register + volatile uint32_t GICR_CLASS; // +0x0028 - RW - Class Register + const volatile uint32_t padding2[5]; // +0x002C - RESERVED +#endif + volatile uint64_t GICR_SETLPIR; // +0x0040 - WO - Set LPI Pending Register + volatile uint64_t GICR_CLRLPIR; // +0x0048 - WO - Clear LPI Pending Register + const volatile uint32_t padding3[8]; // +0x0050 - RESERVED + volatile uint64_t GICR_PROPBASER; // +0x0070 - RW - Redistributor Properties Base Address Register + volatile uint64_t GICR_PENDBASER; // +0x0078 - RW - Redistributor LPI Pending Table Base Address Register + const volatile uint32_t padding4[8]; // +0x0080 - RESERVED + volatile uint64_t GICR_INVLPIR; // +0x00A0 - WO - Redistributor Invalidate LPI Register + const volatile uint32_t padding5[2]; // +0x00A8 - RESERVED + volatile uint64_t GICR_INVALLR; // +0x00B0 - WO - Redistributor Invalidate All Register + const volatile uint32_t padding6[2]; // +0x00B8 - RESERVED + volatile uint64_t GICR_SYNCR; // +0x00C0 - RO - Redistributor Synchronize Register + const volatile uint32_t padding7[2]; // +0x00C8 - RESERVED + const volatile uint32_t padding8[12]; // +0x00D0 - RESERVED + volatile uint64_t IMPDEF2; // +0x0100 - WO - IMPLEMENTATION DEFINED + const volatile uint32_t padding9[2]; // +0x0108 - RESERVED + volatile uint64_t IMPDEF3; // +0x0110 - WO - IMPLEMENTATION DEFINED + const volatile uint32_t padding10[2]; // +0x0118 - RESERVED +} GICv3_redistributor_RD; + +/* + * SGI and PPI Redistributor register map + */ +typedef struct +{ + const volatile uint32_t padding1[32]; // +0x0000 - RESERVED + volatile uint32_t GICR_IGROUPR0; // +0x0080 - RW - Interrupt Group Registers (Security Registers in GICv1) + const volatile uint32_t padding2[31]; // +0x0084 - RESERVED + volatile uint32_t GICR_ISENABLER; // +0x0100 - RW - Interrupt Set-Enable Registers + const volatile uint32_t padding3[31]; // +0x0104 - RESERVED + volatile uint32_t GICR_ICENABLER; // +0x0180 - RW - Interrupt Clear-Enable Registers + const volatile uint32_t padding4[31]; // +0x0184 - RESERVED + volatile uint32_t GICR_ISPENDR; // +0x0200 - RW - Interrupt Set-Pending Registers + const volatile uint32_t padding5[31]; // +0x0204 - RESERVED + volatile uint32_t GICR_ICPENDR; // +0x0280 - RW - Interrupt Clear-Pending Registers + const volatile uint32_t padding6[31]; // +0x0284 - RESERVED + volatile uint32_t GICR_ISACTIVER; // +0x0300 - RW - Interrupt Set-Active Register + const volatile uint32_t padding7[31]; // +0x0304 - RESERVED + volatile uint32_t GICR_ICACTIVER; // +0x0380 - RW - Interrupt Clear-Active Register + const volatile uint32_t padding8[31]; // +0x0184 - RESERVED + volatile uint8_t GICR_IPRIORITYR[32]; // +0x0400 - RW - Interrupt Priority Registers + const volatile uint32_t padding9[504]; // +0x0420 - RESERVED + volatile uint32_t GICR_ICnoFGR[2]; // +0x0C00 - RW - Interrupt Configuration Registers + const volatile uint32_t padding10[62]; // +0x0C08 - RESERVED + volatile uint32_t GICR_IGRPMODR0; // +0x0D00 - RW - ???? + const volatile uint32_t padding11[63]; // +0x0D04 - RESERVED + volatile uint32_t GICR_NSACR; // +0x0E00 - RW - Non-Secure Access Control Register +} GICv3_redistributor_SGI; + +/* + * We have a multiplicity of GIC Redistributors; on the GIC-AEM and + * GIC-500 they are arranged as one 128KB region per redistributor: one + * 64KB page of GICR LPI registers, and one 64KB page of GICR Private + * Int registers + */ +typedef struct +{ + union + { + GICv3_redistributor_RD RD_base; + uint8_t padding[64 * 1024]; + } RDblock; + + union + { + GICv3_redistributor_SGI SGI_base; + uint8_t padding[64 * 1024]; + } SGIblock; +} GICv3_GICR; + +/* + * use the scatter file to place GIC Redistributor base address + * + * although this code doesn't know how many Redistributor banks + * a particular system will have, we declare gicrbase as an array + * to avoid unwanted compiler optimisations when calculating the + * base of a particular Redistributor bank + */ +static const GICv3_GICR gicrbase[2] __attribute__((section (".bss.redistributor"))); + +/**********************************************************************/ + +/* + * utility functions to calculate base of a particular + * Redistributor bank + */ + +static inline GICv3_redistributor_RD *const getgicrRD(uint32_t gicr) +{ + GICv3_GICR *const arraybase = (GICv3_GICR *const)&gicrbase; + + return &((arraybase + gicr)->RDblock.RD_base); +} + +static inline GICv3_redistributor_SGI *const getgicrSGI(uint32_t gicr) +{ + GICv3_GICR *arraybase = (GICv3_GICR *)(&gicrbase); + + return &(arraybase[gicr].SGIblock.SGI_base); +} + +/**********************************************************************/ + +// This function walks a block of RDs to find one with the matching affinity +uint32_t GetGICR(uint32_t affinity) +{ + GICv3_redistributor_RD* gicr; + uint32_t index = 0; + + do + { + gicr = getgicrRD(index); + if (gicr->GICR_TYPER[1] == affinity) + return index; + + index++; + } + while((gicr->GICR_TYPER[0] & (1<<4)) == 0); // Keep looking until GICR_TYPER.Last reports no more RDs in block + + return 0xFFFFFFFF; // return -1 to signal not RD found +} + +void WakeupGICR(uint32_t gicr) +{ + GICv3_redistributor_RD *const gicrRD = getgicrRD(gicr); +#ifdef USE_GIC600 + //Power up Re-distributor for GIC-600 + gicrRD->GICR_PWRR = 0x2; +#endif + + /* + * step 1 - ensure GICR_WAKER.ProcessorSleep is off + */ + gicrRD->GICR_WAKER &= ~gicrwaker_ProcessorSleep; + + /* + * step 2 - wait for children asleep to be cleared + */ + while ((gicrRD->GICR_WAKER & gicrwaker_ChildrenAsleep) != 0) + continue; + + /* + * OK, GICR is go + */ + return; +} + +void EnablePrivateInt(uint32_t gicr, uint32_t id) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + id &= 0x1f; + + gicrSGI->GICR_ISENABLER = 1 << id; +} + +void DisablePrivateInt(uint32_t gicr, uint32_t id) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + id &= 0x1f; + + gicrSGI->GICR_ICENABLER = 1 << id; +} + +void SetPrivateIntPriority(uint32_t gicr, uint32_t id, uint32_t priority) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + /* + * GICD_IPRIORITYR has one byte-wide entry per interrupt + */ + id &= RANGE_LIMIT(gicrSGI->GICR_IPRIORITYR); + + gicrSGI->GICR_IPRIORITYR[id] = priority; +} + +uint32_t GetPrivateIntPriority(uint32_t gicr, uint32_t id) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + /* + * GICD_IPRIORITYR has one byte-wide entry per interrupt + */ + id &= RANGE_LIMIT(gicrSGI->GICR_IPRIORITYR); + + return (uint32_t)(gicrSGI->GICR_IPRIORITYR[id]); +} + +void SetPrivateIntPending(uint32_t gicr, uint32_t id) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + /* + * GICR_ISPENDR is one 32-bit register + */ + id &= 0x1f; + + gicrSGI->GICR_ISPENDR = 1 << id; +} + +void ClearPrivateIntPending(uint32_t gicr, uint32_t id) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + /* + * GICR_ICPENDR is one 32-bit register + */ + id &= 0x1f; + + gicrSGI->GICR_ICPENDR = 1 << id; +} + +uint32_t GetPrivateIntPending(uint32_t gicr, uint32_t id) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + /* + * GICR_ISPENDR is one 32-bit register + */ + id &= 0x1f; + + return (gicrSGI->GICR_ISPENDR >> id) & 0x01; +} + +void SetPrivateIntSecurity(uint32_t gicr, uint32_t id, GICIGROUPRBits_t group) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + uint32_t groupmod; + + /* + * GICR_IGROUPR0 is one 32-bit register + */ + id &= 0x1f; + + /* + * the single group argument is split into two separate + * registers, so filter out and remove the (new to gicv3) + * group modifier bit + */ + groupmod = (group >> 1) & 1; + group &= 1; + + /* + * either set or clear the Group bit for the interrupt as appropriate + */ + if (group) + gicrSGI->GICR_IGROUPR0 |= 1 << id; + else + gicrSGI->GICR_IGROUPR0 &= ~(1 << id); + + /* + * now deal with groupmod + */ + if (groupmod) + gicrSGI->GICR_IGRPMODR0 |= 1 << id; + else + gicrSGI->GICR_IGRPMODR0 &= ~(1 << id); +} + +void SetPrivateIntSecurityBlock(uint32_t gicr, GICIGROUPRBits_t group) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + const uint32_t nbits = (sizeof group * 8) - 1; + uint32_t groupmod; + + /* + * get each bit of group config duplicated over all 32 bits + */ + groupmod = (uint32_t)(((int32_t)group << (nbits - 1)) >> 31); + group = (uint32_t)(((int32_t)group << nbits) >> 31); + + /* + * set the security state for this block of SPIs + */ + gicrSGI->GICR_IGROUPR0 = group; + gicrSGI->GICR_IGRPMODR0 = groupmod; +} + +/* EOF GICv3_gicr.c */ diff --git a/ports/cortex_a35/ac6/example_build/sample_threadx/MP_Mutexes.S b/ports/cortex_a35/ac6/example_build/sample_threadx/MP_Mutexes.S new file mode 100644 index 00000000..e7f95aa7 --- /dev/null +++ b/ports/cortex_a35/ac6/example_build/sample_threadx/MP_Mutexes.S @@ -0,0 +1,133 @@ +// +// Armv8-A AArch64 - Basic Mutex Example +// Includes the option (USE_LSE_ATOMIC) to use Large System Extension (LSE) atomics introduced in Armv8.1-A +// +// Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// + + + .text + .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + + + .global _mutex_initialize + .global _mutex_acquire + .global _mutex_release + +// +// These routines implement the mutex management functions required for running +// the Arm C library in a multi-threaded environment. +// +// They use a value of 0 to represent an unlocked mutex, and 1 for a locked mutex +// +// ********************************************************************** +// + + .type _mutex_initialize, "function" + .cfi_startproc +_mutex_initialize: + + // + // mark the mutex as unlocked + // + mov w1, #0 + str w1, [x0] + + // + // we are running multi-threaded, so set a non-zero return + // value (function prototype says use 1) + // + mov w0, #1 + ret + .cfi_endproc + +#if !defined(USE_LSE_ATOMIC) + + .type _mutex_acquire, "function" + .cfi_startproc +_mutex_acquire: + + // + // send ourselves an event, so we don't stick on the wfe at the + // top of the loop + // + sevl + + // + // wait until the mutex is available + // +loop: + wfe + ldaxr w1, [x0] + cbnz w1, loop + + // + // mutex is (at least, it was) available - try to claim it + // + mov w1, #1 + stxr w2, w1, [x0] + cbnz w2, loop + + // + // OK, we have the mutex, our work is done here + // + ret + .cfi_endproc + + + .type _mutex_release, "function" + .cfi_startproc +_mutex_release: + + mov w1, #0 + stlr w1, [x0] + ret + .cfi_endproc + +#else // LSE version + + .type _mutex_acquire, "function" + .cfi_startproc +_mutex_acquire: + // This uses a "ticket lock". The lock is stored as a 32-bit value: + // - the upper 16-bits record the thread's ticket number ("take a ticket") + // - the lower 16-bits record the ticket being served ("now serving") + + // atomically load then increment the thread's ticket number ("take a ticket") + mov w3, #(1 << 16) + ldadda w3, w1, [x0] + + // is the ticket now being served? + eor w2, w1, w1, ror #16 + cbz w2, loop_exit + + // no, so wait for the ticket to be served + + // send a local event to avoid missing an unlock before the exclusive load + sevl + +loop: + wfe + ldaxrh w3, [x0] + eor w2, w3, w1, lsr #16 + cbnz w2, loop + + // + // OK, we have the mutex, our work is done here + // +loop_exit: + ret + .cfi_endproc + + + .type _mutex_release, "function" + .cfi_startproc +_mutex_release: + mov w1, #1 + staddlh w1, [x0] + ret + .cfi_endproc +#endif diff --git a/ports/cortex_a35/ac6/example_build/sample_threadx/MP_Mutexes.h b/ports/cortex_a35/ac6/example_build/sample_threadx/MP_Mutexes.h new file mode 100644 index 00000000..ec1a1d28 --- /dev/null +++ b/ports/cortex_a35/ac6/example_build/sample_threadx/MP_Mutexes.h @@ -0,0 +1,66 @@ +/* + * Armv8-A AArch64 - Basic Mutex Example + * + * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. + * Use, modification and redistribution of this file is subject to your possession of a + * valid End User License Agreement for the Arm Product of which these examples are part of + * and your compliance with all applicable terms and conditions of such licence agreement. + */ +#ifndef MP_MUTEX_H +#define MP_MUTEX_H + +/* + * The Arm C library calls-out to these functions to manage multithreading. + * They can also be called by user application code. + * + * Mutex type is specified by the Arm C library + * + * Declare function prototypes for libc mutex routines + */ +typedef signed int *mutex; + +/* + * int _mutex_initialize(mutex *m) + * + * Inputs + * mutex *m - pointer to the 32-bit word associated with the mutex + * + * Returns + * 0 - application is non-threaded + * 1 - application is threaded + * The C library uses the return result to indicate whether it is being used in a multithreaded environment. + */ +int _mutex_initialize(mutex *m); + +/* + * void _mutex_acquire(mutex *m) + * + * Inputs + * mutex *m - pointer to the 32-bit word associated with the mutex + * + * Returns + * + * + * Side Effects + * Routine does not return until the mutex has been claimed. A load-acquire + * is used to guarantee that the mutex claim is properly ordered with + * respect to any accesses to the resource protected by the mutex + */ +void _mutex_acquire(mutex *m); + +/* + * void _mutex_release(mutex *m) + * + * Inputs + * mutex *m - pointer to the 32-bit word associated with the mutex + * + * Returns + * + * + * Side Effects + * A store-release is used to guarantee that the mutex release is properly + * ordered with respect any accesses to the resource protected by the mutex + */ +void _mutex_release(mutex *m); + +#endif diff --git a/ports/cortex_a35/ac6/example_build/sample_threadx/PPM_AEM.h b/ports/cortex_a35/ac6/example_build/sample_threadx/PPM_AEM.h new file mode 100644 index 00000000..52c9a0fe --- /dev/null +++ b/ports/cortex_a35/ac6/example_build/sample_threadx/PPM_AEM.h @@ -0,0 +1,66 @@ +// +// Private Peripheral Map for the v8 Architecture Envelope Model +// +// Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// + +#ifndef PPM_AEM_H +#define PPM_AEM_H + +// +// Distributor layout +// +#define GICD_CTLR 0x0000 +#define GICD_TYPER 0x0004 +#define GICD_IIDR 0x0008 +#define GICD_IGROUP 0x0080 +#define GICD_ISENABLE 0x0100 +#define GICD_ICENABLE 0x0180 +#define GICD_ISPEND 0x0200 +#define GICD_ICPEND 0x0280 +#define GICD_ISACTIVE 0x0300 +#define GICD_ICACTIVE 0x0380 +#define GICD_IPRIORITY 0x0400 +#define GICD_ITARGETS 0x0800 +#define GICD_ICFG 0x0c00 +#define GICD_PPISR 0x0d00 +#define GICD_SPISR 0x0d04 +#define GICD_SGIR 0x0f00 +#define GICD_CPENDSGI 0x0f10 +#define GICD_SPENDSGI 0x0f20 +#define GICD_PIDR4 0x0fd0 +#define GICD_PIDR5 0x0fd4 +#define GICD_PIDR6 0x0fd8 +#define GICD_PIDR7 0x0fdc +#define GICD_PIDR0 0x0fe0 +#define GICD_PIDR1 0x0fe4 +#define GICD_PIDR2 0x0fe8 +#define GICD_PIDR3 0x0fec +#define GICD_CIDR0 0x0ff0 +#define GICD_CIDR1 0x0ff4 +#define GICD_CIDR2 0x0ff8 +#define GICD_CIDR3 0x0ffc + +// +// CPU Interface layout +// +#define GICC_CTLR 0x0000 +#define GICC_PMR 0x0004 +#define GICC_BPR 0x0008 +#define GICC_IAR 0x000c +#define GICC_EOIR 0x0010 +#define GICC_RPR 0x0014 +#define GICC_HPPIR 0x0018 +#define GICC_ABPR 0x001c +#define GICC_AIAR 0x0020 +#define GICC_AEOIR 0x0024 +#define GICC_AHPPIR 0x0028 +#define GICC_APR0 0x00d0 +#define GICC_NSAPR0 0x00e0 +#define GICC_IIDR 0x00fc +#define GICC_DIR 0x1000 + +#endif // PPM_AEM_H diff --git a/ports/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.c new file mode 100644 index 00000000..8898ff39 --- /dev/null +++ b/ports/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.c @@ -0,0 +1,377 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" +#include + +#define DEMO_STACK_SIZE 2048 +#define DEMO_BYTE_POOL_SIZE 64000 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +UCHAR memory_pool[DEMO_BYTE_POOL_SIZE]; + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + +void init_timer(); + +/* Define main entry point. */ + +int main() +{ + + /* Initialize timer for ThreadX. */ + init_timer(); + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +UCHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_pool, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.launch b/ports/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.launch new file mode 100644 index 00000000..f0856def --- /dev/null +++ b/ports/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.launch @@ -0,0 +1,317 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.scat b/ports/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.scat new file mode 100644 index 00000000..e5783c7c --- /dev/null +++ b/ports/cortex_a35/ac6/example_build/sample_threadx/sample_threadx.scat @@ -0,0 +1,103 @@ +;******************************************************** +; Scatter file for Armv8-A Startup code on FVP Base model +; Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. +; Use, modification and redistribution of this file is subject to your possession of a +; valid End User License Agreement for the Arm Product of which these examples are part of +; and your compliance with all applicable terms and conditions of such licence agreement. +;******************************************************** + +LOAD 0x80000000 +{ + EXEC +0 + { + startup.o (StartUp, +FIRST) + * (+RO, +RW, +ZI) + } + + ; + ; App stacks for all CPUs + ; All stacks and heap are aligned to a cache-line boundary + ; + ARM_LIB_STACK +0 ALIGN 64 EMPTY 8 * 0x4000 {} + + ; + ; Separate heap - import symbol __use_two_region_memory + ; in source code for this to work correctly + ; + ARM_LIB_HEAP +0 ALIGN 64 EMPTY 0xA0000 {} + + ; + ; Handler stacks for all CPUs + ; All stacks and heap are aligned to a cache-line boundary + ; + HANDLER_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} + + ; + ; Stacks for EL3 + ; + EL3_STACKS +0 ALIGN 64 EMPTY 8 * 0x1000 {} + ; + ; Strictly speaking, the L1 tables do not need to + ; be so strongly aligned, but no matter + ; + TTB0_L1 +0 ALIGN 4096 EMPTY 0x1000 {} + + ; + ; Various sets of L2 tables + ; + ; Alignment is 4KB, since the code uses a 4K page + ; granularity - larger granularities would require + ; correspondingly stricter alignment + ; + TTB0_L2_RAM +0 ALIGN 4096 EMPTY 0x1000 {} + + TTB0_L2_PRIVATE +0 ALIGN 4096 EMPTY 0x1000 {} + + TTB0_L2_PERIPH +0 ALIGN 4096 EMPTY 0x1000 {} + + ; + ; The startup code uses the end of this region to calculate + ; the top of memory - do not place any RAM regions after it + ; + TOP_OF_RAM +0 EMPTY 4 {} + + ; + ; CS3 Peripherals is a 64MB region from 0x1c000000 + ; that includes the following: + ; System Registers at 0x1C010000 + ; UART0 (PL011) at 0x1C090000 + ; Color LCD Controller (PL111) at 0x1C1F0000 + ; plus a number of others. + ; CS3_PERIPHERALS is used by the startup code for page-table generation + ; This region is not truly empty, but we have no + ; predefined objects that live within it + ; + CS3_PERIPHERALS 0x1c000000 EMPTY 0x90000 {} + + ; + ; Place the UART peripheral registers data structure + ; This is only really needed if USE_SERIAL_PORT is defined, but + ; the linker will remove unused sections if not needed +; PL011 0x1c090000 UNINIT 0x1000 +; { +; uart.o (+ZI) +; } + ; Note that some other CS3_PERIPHERALS follow this + + ; + ; GICv3 distributor + ; + GICD 0x2f000000 UNINIT 0x8000 + { + GICv3_gicd.o (.bss.distributor) + } + + ; + ; GICv3 redistributors + ; 128KB for each redistributor in the system + ; + GICR 0x2f100000 UNINIT 0x80000 + { + GICv3_gicr.o (.bss.redistributor) + } +} diff --git a/ports/cortex_a35/ac6/example_build/sample_threadx/sp804_timer.c b/ports/cortex_a35/ac6/example_build/sample_threadx/sp804_timer.c new file mode 100644 index 00000000..4dc009b2 --- /dev/null +++ b/ports/cortex_a35/ac6/example_build/sample_threadx/sp804_timer.c @@ -0,0 +1,122 @@ +// ------------------------------------------------------------ +// SP804 Dual Timer +// +// Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#include "sp804_timer.h" + +#define TIMER_SP804_CTRL_TIMEREN (1 << 7) +#define TIMER_SP804_CTRL_TIMERMODE (1 << 6) // Bit 6: +#define TIMER_SP804_CTRL_INTENABLE (1 << 5) +#define TIMER_SP804_CTRL_TIMERSIZE (1 << 1) // Bit 1: 0=16-bit, 1=32-bit +#define TIMER_SP804_CTRL_ONESHOT (1 << 0) // Bit 0: 0=wrapping, 1=one-shot + +#define TIMER_SP804_CTRL_PRESCALE_1 (0 << 2) // clk/1 +#define TIMER_SP804_CTRL_PRESCALE_4 (1 << 2) // clk/4 +#define TIMER_SP804_CTRL_PRESCALE_8 (2 << 2) // clk/8 + +struct sp804_timer +{ + volatile uint32_t Time1Load; // +0x00 + const volatile uint32_t Time1Value; // +0x04 - RO + volatile uint32_t Timer1Control; // +0x08 + volatile uint32_t Timer1IntClr; // +0x0C - WO + const volatile uint32_t Timer1RIS; // +0x10 - RO + const volatile uint32_t Timer1MIS; // +0x14 - RO + volatile uint32_t Timer1BGLoad; // +0x18 + + volatile uint32_t Time2Load; // +0x20 + volatile uint32_t Time2Value; // +0x24 + volatile uint8_t Timer2Control; // +0x28 + volatile uint32_t Timer2IntClr; // +0x2C - WO + const volatile uint32_t Timer2RIS; // +0x30 - RO + const volatile uint32_t Timer2MIS; // +0x34 - RO + volatile uint32_t Timer2BGLoad; // +0x38 + + // Not including ID registers + +}; + +// Instance of the dual timer, will be placed using the scatter file +struct sp804_timer* dual_timer; + + +// Set base address of timer +// address - virtual address of SP804 timer +void setTimerBaseAddress(uint64_t address) +{ + dual_timer = (struct sp804_timer*)address; + return; +} + + +// Sets up the private timer +// load_value - Initial value of timer +// auto_reload - Periodic (SP804_AUTORELOAD) or one shot (SP804_SINGLESHOT) +// interrupt - Whether to generate an interrupt +void initTimer(uint32_t load_value, uint32_t auto_reload, uint32_t interrupt) +{ + uint32_t tmp = 0; + + dual_timer->Time1Load = load_value; + + // Fixed setting: 32-bit, no prescaling + tmp = TIMER_SP804_CTRL_TIMERSIZE | TIMER_SP804_CTRL_PRESCALE_1 | TIMER_SP804_CTRL_TIMERMODE; + + // Settings from parameters: interrupt generation & reload + tmp = tmp | interrupt | auto_reload; + + // Write control register + dual_timer->Timer1Control = tmp; + + return; +} + + +// Starts the timer +void startTimer(void) +{ + uint32_t tmp; + + tmp = dual_timer->Timer1Control; + tmp = tmp | TIMER_SP804_CTRL_TIMEREN; // Set TimerEn (bit 7) + dual_timer->Timer1Control = tmp; + + return; +} + + +// Stops the timer +void stopTimer(void) +{ + uint32_t tmp; + + tmp = dual_timer->Timer1Control; + tmp = tmp & ~TIMER_SP804_CTRL_TIMEREN; // Clear TimerEn (bit 7) + dual_timer->Timer1Control = tmp; + + return; +} + + +// Returns the current timer count +uint32_t getTimerCount(void) +{ + return dual_timer->Time1Value; +} + + +void clearTimerIrq(void) +{ + // A write to this register, of any value, clears the interrupt + dual_timer->Timer1IntClr = 1; +} + + +// ------------------------------------------------------------ +// End of sp804_timer.c +// ------------------------------------------------------------ diff --git a/ports/cortex_a35/ac6/example_build/sample_threadx/sp804_timer.h b/ports/cortex_a35/ac6/example_build/sample_threadx/sp804_timer.h new file mode 100644 index 00000000..777062cc --- /dev/null +++ b/ports/cortex_a35/ac6/example_build/sample_threadx/sp804_timer.h @@ -0,0 +1,53 @@ +// ------------------------------------------------------------ +// SP804 Dual Timer +// Header Filer +// +// Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#ifndef _SP804_TIMER_ +#define _SP804_TIMER_ + +#include + +// Set base address of timer +// address - virtual address of SP804 timer +void setTimerBaseAddress(uint64_t address); + + +// Sets up the private timer +// load_value - Initial value of timer +// auto_reload - Periodic (SP804_AUTORELOAD) or one shot (SP804_SINGLESHOT) +// interrupt - Whether to generate an interrupt + +#define SP804_AUTORELOAD (0) +#define SP804_SINGLESHOT (1) +#define SP804_GENERATE_IRQ (1 << 5) +#define SP804_NO_IRQ (0) + +void initTimer(uint32_t load_value, uint32_t auto_reload, uint32_t interrupt); + + +// Starts the timer +void startTimer(void); + + +// Stops the timer +void stopTimer(void); + + +// Returns the current timer count +uint32_t getTimerCount(void); + + +// Clears the timer interrupt +void clearTimerIrq(void); + +#endif + +// ------------------------------------------------------------ +// End of sp804_timer.h +// ------------------------------------------------------------ diff --git a/ports/cortex_a35/ac6/example_build/sample_threadx/startup.S b/ports/cortex_a35/ac6/example_build/sample_threadx/startup.S new file mode 100644 index 00000000..de100e56 --- /dev/null +++ b/ports/cortex_a35/ac6/example_build/sample_threadx/startup.S @@ -0,0 +1,779 @@ +// ------------------------------------------------------------ +// Armv8-A MPCore EL3 AArch64 Startup Code +// +// Basic Vectors, MMU, caches and GICv3 initialization +// +// Exits in EL1 AArch64 +// +// Copyright (c) 2014-2019 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#include "v8_mmu.h" +#include "v8_system.h" + + + .section StartUp, "ax" + .balign 4 + .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + + .global el1_vectors + .global el2_vectors + .global el3_vectors + + .global InvalidateUDCaches + .global ZeroBlock + + .global SetPrivateIntSecurityBlock + .global SetSPISecurityAll + .global SetPrivateIntPriority + + .global GetGICR + .global WakeupGICR + .global SyncAREinGICD + .global EnableGICD + .global EnablePrivateInt + .global GetPrivateIntPending + .global ClearPrivateIntPending + + .global __main + //.global MainApp + + .global Image$$EXEC$$RO$$Base + .global Image$$TTB0_L1$$ZI$$Base + .global Image$$TTB0_L2_RAM$$ZI$$Base + .global Image$$TTB0_L2_PERIPH$$ZI$$Base + .global Image$$TOP_OF_RAM$$ZI$$Base + .global Image$$GICD$$ZI$$Base + .global Image$$ARM_LIB_STACK$$ZI$$Limit + .global Image$$EL3_STACKS$$ZI$$Limit + .global Image$$CS3_PERIPHERALS$$ZI$$Base + // use separate stack and heap, as anticipated by scatter.scat + .global __use_two_region_memory + + +// ------------------------------------------------------------ + + .global start64 + .type start64, "function" +start64: + + // + // program the VBARs + // + ldr x1, =el1_vectors + msr VBAR_EL1, x1 + + ldr x1, =el2_vectors + msr VBAR_EL2, x1 + + ldr x1, =el3_vectors + msr VBAR_EL3, x1 + + + // GIC-500 comes out of reset in GICv2 compatibility mode - first set + // system register enables for all relevant exception levels, and + // select GICv3 operating mode + // + msr SCR_EL3, xzr // Ensure NS bit is initially clear, so secure copy of ICC_SRE_EL1 can be configured + isb + + mov x0, #15 + msr ICC_SRE_EL3, x0 + isb + msr ICC_SRE_EL1, x0 // Secure copy of ICC_SRE_EL1 + + // + // set lower exception levels as non-secure, with no access + // back to EL2 or EL3, and are AArch64 capable + // + mov x3, #(SCR_EL3_RW | \ + SCR_EL3_SMD | \ + SCR_EL3_NS) // Set NS bit, to access Non-secure registers + msr SCR_EL3, x3 + isb + + mov x0, #15 + msr ICC_SRE_EL2, x0 + isb + msr ICC_SRE_EL1, x0 // Non-secure copy of ICC_SRE_EL1 + + + // + // no traps or VM modifications from the Hypervisor, EL1 is AArch64 + // + mov x2, #HCR_EL2_RW + msr HCR_EL2, x2 + + // + // VMID is still significant, even when virtualisation is not + // being used, so ensure VTTBR_EL2 is properly initialised + // + msr VTTBR_EL2, xzr + + // + // VMPIDR_EL2 holds the value of the Virtualization Multiprocessor ID. This is the value returned by Non-secure EL1 reads of MPIDR_EL1. + // VPIDR_EL2 holds the value of the Virtualization Processor ID. This is the value returned by Non-secure EL1 reads of MIDR_EL1. + // Both of these registers are architecturally UNKNOWN at reset, and so they must be set to the correct value + // (even if EL2/virtualization is not being used), otherwise non-secure EL1 reads of MPIDR_EL1/MIDR_EL1 will return garbage values. + // This guarantees that any future reads of MPIDR_EL1 and MIDR_EL1 from Non-secure EL1 will return the correct value. + // + mrs x0, MPIDR_EL1 + msr VMPIDR_EL2, x0 + mrs x0, MIDR_EL1 + msr VPIDR_EL2, x0 + + // extract the core number from MPIDR_EL1 and store it in + // x19 (defined by the AAPCS as callee-saved), so we can re-use + // the number later + // + bl GetCPUID + mov x19, x0 + + // + // neither EL3 nor EL2 trap floating point or accesses to CPACR + // + msr CPTR_EL3, xzr + msr CPTR_EL2, xzr + + // + // SCTLR_ELx may come out of reset with UNKNOWN values so we will + // set the fields to 0 except, possibly, the endianess field(s). + // Note that setting SCTLR_EL2 or the EL0 related fields of SCTLR_EL1 + // is not strictly needed, since we're never in EL2 or EL0 + // +#ifdef __ARM_BIG_ENDIAN + mov x0, #(SCTLR_ELx_EE | SCTLR_EL1_E0E) +#else + mov x0, #0 +#endif + msr SCTLR_EL3, x0 + msr SCTLR_EL2, x0 + msr SCTLR_EL1, x0 + +#ifdef CORTEXA + // + // Configure ACTLR_EL[23] + // ---------------------- + // + // These bits are IMPLEMENTATION DEFINED, so are different for + // different processors + // + // For Cortex-A57, the controls we set are: + // + // Enable lower level access to CPUACTLR_EL1 + // Enable lower level access to CPUECTLR_EL1 + // Enable lower level access to L2CTLR_EL1 + // Enable lower level access to L2ECTLR_EL1 + // Enable lower level access to L2ACTLR_EL1 + // + mov x0, #((1 << 0) | \ + (1 << 1) | \ + (1 << 4) | \ + (1 << 5) | \ + (1 << 6)) + + msr ACTLR_EL3, x0 + msr ACTLR_EL2, x0 + + // + // configure CPUECTLR_EL1 + // + // These bits are IMP DEF, so need to different for different + // processors + // + // SMPEN - bit 6 - Enables the processor to receive cache + // and TLB maintenance operations + // + // Note: For Cortex-A57/53 SMPEN should be set before enabling + // the caches and MMU, or performing any cache and TLB + // maintenance operations. + // + // This register has a defined reset value, so we use a + // read-modify-write sequence to set SMPEN + // + mrs x0, S3_1_c15_c2_1 // Read EL1 CPU Extended Control Register + orr x0, x0, #(1 << 6) // Set the SMPEN bit + msr S3_1_c15_c2_1, x0 // Write EL1 CPU Extended Control Register + + isb +#endif + + // + // That's the last of the control settings for now + // + // Note: no ISB after all these changes, as registers won't be + // accessed until after an exception return, which is itself a + // context synchronisation event + // + + // + // Setup some EL3 stack space, ready for calling some subroutines, below. + // + // Stack space allocation is CPU-specific, so use CPU + // number already held in x19 + // + // 2^12 bytes per CPU for the EL3 stacks + // + ldr x0, =Image$$EL3_STACKS$$ZI$$Limit + sub x0, x0, x19, lsl #12 + mov sp, x0 + + // + // we need to configure the GIC while still in secure mode, specifically + // all PPIs and SPIs have to be programmed as Group1 interrupts + // + + // + // Before the GIC can be reliably programmed, we need to + // enable Affinity Routing, as this affects where the configuration + // registers are (with Affinity Routing enabled, some registers are + // in the Redistributor, whereas those same registers are in the + // Distributor with Affinity Routing disabled (i.e. when in GICv2 + // compatibility mode). + // + mov x0, #(1 << 4) | (1 << 5) // gicdctlr_ARE_S | gicdctlr_ARE_NS + mov x1, x19 + bl SyncAREinGICD + + // + // The Redistributor comes out of reset assuming the processor is + // asleep - correct that assumption + // + bl GetAffinity + bl GetGICR + mov w20, w0 // Keep a copy for later + bl WakeupGICR + + // + // Now we're ready to set security and other initialisations + // + // This is a per-CPU configuration for these interrupts + // + // for the first cluster, CPU number is the redistributor index + // + mov w0, w20 + mov w1, #1 // gicigroupr_G1NS + bl SetPrivateIntSecurityBlock + + // + // While we're in the Secure World, set the priority mask low enough + // for it to be writable in the Non-Secure World + // + //mov x0, #16 << 3 // 5 bits of priority in the Secure world + mov x0, #0xFF // for Non-Secure interrupts + msr ICC_PMR_EL1, x0 + + // + // there's more GIC setup to do, but only for the primary CPU + // + cbnz x19, drop_to_el1 + + // + // There's more to do to the GIC - call the utility routine to set + // all SPIs to Group1 + // + mov w0, #1 // gicigroupr_G1NS + bl SetSPISecurityAll + + // + // Set up EL1 entry point and "dummy" exception return information, + // then perform exception return to enter EL1 + // + .global drop_to_el1 +drop_to_el1: + adr x1, el1_entry_aarch64 + msr ELR_EL3, x1 + mov x1, #(AARCH64_SPSR_EL1h | \ + AARCH64_SPSR_F | \ + AARCH64_SPSR_I | \ + AARCH64_SPSR_A) + msr SPSR_EL3, x1 + eret + + + +// ------------------------------------------------------------ +// EL1 - Common start-up code +// ------------------------------------------------------------ + + .global el1_entry_aarch64 + .type el1_entry_aarch64, "function" +el1_entry_aarch64: + + // + // Now we're in EL1, setup the application stack + // the scatter file allocates 2^14 bytes per app stack + // + ldr x0, =Image$$HANDLER_STACK$$ZI$$Limit + sub x0, x0, x19, lsl #14 + mov sp, x0 + MSR SPSel, #0 + ISB + ldr x0, =Image$$ARM_LIB_STACK$$ZI$$Limit + sub x0, x0, x19, lsl #14 + mov sp, x0 + + // + // Enable floating point + // + mov x0, #CPACR_EL1_FPEN + msr CPACR_EL1, x0 + + // + // Invalidate caches and TLBs for all stage 1 + // translations used at EL1 + // + // Cortex-A processors automatically invalidate their caches on reset + // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins). + // It is therefore not necessary for software to invalidate the caches + // on startup, however, this is done here in case of a warm reset. + bl InvalidateUDCaches + tlbi VMALLE1 + + + // + // Set TTBR0 Base address + // + // The CPUs share one set of translation tables that are + // generated by CPU0 at run-time + // + // TTBR1_EL1 is not used in this example + // + ldr x1, =Image$$TTB0_L1$$ZI$$Base + msr TTBR0_EL1, x1 + + + // + // Set up memory attributes + // + // These equate to: + // + // 0 -> 0b01000100 = 0x00000044 = Normal, Inner/Outer Non-Cacheable + // 1 -> 0b11111111 = 0x0000ff00 = Normal, Inner/Outer WriteBack Read/Write Allocate + // 2 -> 0b00000100 = 0x00040000 = Device-nGnRE + // + mov x1, #0xff44 + movk x1, #4, LSL #16 // equiv to: movk x1, #0x0000000000040000 + msr MAIR_EL1, x1 + + + // + // Set up TCR_EL1 + // + // We're using only TTBR0 (EPD1 = 1), and the page table entries: + // - are using an 8-bit ASID from TTBR0 + // - have a 4K granularity (TG0 = 0b00) + // - are outer-shareable (SH0 = 0b10) + // - are using Inner & Outer WBWA Normal memory ([IO]RGN0 = 0b01) + // - map + // + 32 bits of VA space (T0SZ = 0x20) + // + into a 32-bit PA space (IPS = 0b000) + // + // 36 32 28 24 20 16 12 8 4 0 + // -----+----+----+----+----+----+----+----+----+----+ + // | | |OOII| | | |OOII| | | + // TT | | |RRRR|E T | T| |RRRR|E T | T| + // BB | I I|TTSS|GGGG|P 1 | 1|TTSS|GGGG|P 0 | 0| + // IIA| P P|GGHH|NNNN|DAS | S|GGHH|NNNN|D S | S| + // 10S| S-S|1111|1111|11Z-|---Z|0000|0000|0 Z-|---Z| + // + // 000 0000 0000 0000 1000 0000 0010 0101 0010 0000 + // + // 0x 8 0 2 5 2 0 + // + // Note: the ISB is needed to ensure the changes to system + // context are before the write of SCTLR_EL1.M to enable + // the MMU. It is likely on a "real" implementation that + // this setup would work without an ISB, due to the + // amount of code that gets executed before enabling the + // MMU, but that would not be architecturally correct. + // + ldr x1, =0x0000000000802520 + msr TCR_EL1, x1 + isb + + // + // x19 already contains the CPU number, so branch to secondary + // code if we're not on CPU0 + // + cbnz x19, el1_secondary + + // + // Fall through to primary code + // + + +// +// ------------------------------------------------------------ +// +// EL1 - primary CPU init code +// +// This code is run on CPU0, while the other CPUs are in the +// holding pen +// + + .global el1_primary + .type el1_primary, "function" +el1_primary: + + // + // Turn on the banked GIC distributor enable, + // ready for individual CPU enables later + // + mov w0, #(1 << 1) // gicdctlr_EnableGrp1A + bl EnableGICD + + // + // Generate TTBR0 L1 + // + // at 4KB granularity, 32-bit VA space, table lookup starts at + // L1, with 1GB regions + // + // we are going to create entries pointing to L2 tables for a + // couple of these 1GB regions, the first of which is the + // RAM on the VE board model - get the table addresses and + // start by emptying out the L1 page tables (4 entries at L1 + // for a 4K granularity) + // + // x21 = address of L1 tables + // + ldr x21, =Image$$TTB0_L1$$ZI$$Base + mov x0, x21 + mov x1, #(4 << 3) + bl ZeroBlock + + // + // time to start mapping the RAM regions - clear out the + // L2 tables and point to them from the L1 tables + // + // x22 = address of L2 tables, needs to be remembered in case + // we want to re-use the tables for mapping peripherals + // + ldr x22, =Image$$TTB0_L2_RAM$$ZI$$Base + mov x1, #(512 << 3) + mov x0, x22 + bl ZeroBlock + + // + // Get the start address of RAM (the EXEC region) into x4 + // and calculate the offset into the L1 table (1GB per region, + // max 4GB) + // + // x23 = L1 table offset, saved for later comparison against + // peripheral offset + // + ldr x4, =Image$$EXEC$$RO$$Base + ubfx x23, x4, #30, #2 + + orr x1, x22, #TT_S1_ATTR_PAGE + str x1, [x21, x23, lsl #3] + + // + // we've already used the RAM start address in x4 - we now need + // to get this in terms of an offset into the L2 page tables, + // where each entry covers 2MB + // + ubfx x2, x4, #21, #9 + + // + // TOP_OF_RAM in the scatter file marks the end of the + // Execute region in RAM: convert the end of this region to an + // offset too, being careful to round up, then calculate the + // number of entries to write + // + ldr x5, =Image$$TOP_OF_RAM$$ZI$$Base + sub x3, x5, #1 + ubfx x3, x3, #21, #9 + add x3, x3, #1 + sub x3, x3, x2 + + // + // set x1 to the required page table attributes, then orr + // in the start address (modulo 2MB) + // + // L2 tables in our configuration cover 2MB per entry - map + // memory as Shared, Normal WBWA (MAIR[1]) with a flat + // VA->PA translation + // + bic x4, x4, #((1 << 21) - 1) + ldr x1, =(TT_S1_ATTR_BLOCK | \ + (1 << TT_S1_ATTR_MATTR_LSB) | \ + TT_S1_ATTR_NS | \ + TT_S1_ATTR_AP_RW_PL1 | \ + TT_S1_ATTR_SH_INNER | \ + TT_S1_ATTR_AF | \ + TT_S1_ATTR_nG) + orr x1, x1, x4 + + // + // factor the offset into the page table address and then write + // the entries + // + add x0, x22, x2, lsl #3 + +loop1: + subs x3, x3, #1 + str x1, [x0], #8 + add x1, x1, #0x200, LSL #12 // equiv to add x1, x1, #(1 << 21) // 2MB per entry + bne loop1 + + + // + // now mapping the Peripheral regions - clear out the + // L2 tables and point to them from the L1 tables + // + // The assumption here is that all peripherals live within + // a common 1GB region (i.e. that there's a single set of + // L2 pages for all the peripherals). We only use a UART + // and the GIC in this example, so the assumption is sound + // + // x24 = address of L2 peripheral tables + // + ldr x24, =Image$$TTB0_L2_PERIPH$$ZI$$Base + + // + // get the GICD address into x4 and calculate + // the offset into the L1 table + // + // x25 = L1 table offset + // + ldr x4, =Image$$GICD$$ZI$$Base + ubfx x25, x4, #30, #2 + + // + // here's the tricky bit: it's possible that the peripherals are + // in the same 1GB region as the RAM, in which case we don't need + // to prime a separate set of L2 page tables, nor add them to the + // L1 tables + // + // if we're going to re-use the TTB0_L2_RAM tables, get their + // address into x24, which is used later on to write the PTEs + // + cmp x25, x23 + csel x24, x22, x24, EQ + b.eq nol2setup + + // + // Peripherals are in a separate 1GB region, and so have their own + // set of L2 tables - clean out the tables and add them to the L1 + // table + // + mov x0, x24 + mov x1, #512 << 3 + bl ZeroBlock + + orr x1, x24, #TT_S1_ATTR_PAGE + str x1, [x21, x25, lsl #3] + + // + // there's only going to be a single 2MB region for GICD (in + // x4) - get this in terms of an offset into the L2 page tables + // + // with larger systems, it is possible that the GIC redistributor + // registers require extra 2MB pages, in which case extra code + // would be required here + // +nol2setup: + ubfx x2, x4, #21, #9 + + // + // set x1 to the required page table attributes, then orr + // in the start address (modulo 2MB) + // + // L2 tables in our configuration cover 2MB per entry - map + // memory as NS Device-nGnRE (MAIR[2]) with a flat VA->PA + // translation + // + bic x4, x4, #((1 << 21) - 1) // start address mod 2MB + ldr x1, =(TT_S1_ATTR_BLOCK | \ + (2 << TT_S1_ATTR_MATTR_LSB) | \ + TT_S1_ATTR_NS | \ + TT_S1_ATTR_AP_RW_PL1 | \ + TT_S1_ATTR_AF | \ + TT_S1_ATTR_nG) + orr x1, x1, x4 + + // + // only a single L2 entry for this, so no loop as we have for RAM, above + // + str x1, [x24, x2, lsl #3] + + // + // we have CS3_PERIPHERALS that include the UART controller + // + // Again, the code is making assumptions - this time that the CS3_PERIPHERALS + // region uses the same 1GB portion of the address space as the GICD, + // and thus shares the same set of L2 page tables + // + // Get CS3_PERIPHERALS address into x4 and calculate the offset into the + // L2 tables + // + ldr x4, =Image$$CS3_PERIPHERALS$$ZI$$Base + ubfx x2, x4, #21, #9 + + // + // set x1 to the required page table attributes, then orr + // in the start address (modulo 2MB) + // + // L2 tables in our configuration cover 2MB per entry - map + // memory as NS Device-nGnRE (MAIR[2]) with a flat VA->PA + // translation + // + bic x4, x4, #((1 << 21) - 1) // start address mod 2MB + ldr x1, =(TT_S1_ATTR_BLOCK | \ + (2 << TT_S1_ATTR_MATTR_LSB) | \ + TT_S1_ATTR_NS | \ + TT_S1_ATTR_AP_RW_PL1 | \ + TT_S1_ATTR_AF | \ + TT_S1_ATTR_nG) + orr x1, x1, x4 + + // + // only a single L2 entry again - write it + // + str x1, [x24, x2, lsl #3] + + // + // issue a barrier to ensure all table entry writes are complete + // + dsb ish + + // + // Enable the MMU. Caches will be enabled later, after scatterloading. + // + mrs x1, SCTLR_EL1 + orr x1, x1, #SCTLR_ELx_M + bic x1, x1, #SCTLR_ELx_A // Disable alignment fault checking. To enable, change bic to orr + msr SCTLR_EL1, x1 + isb + + // + // Branch to C library init code + // + b __main + + +// ------------------------------------------------------------ + +// AArch64 Arm C library startup add-in: + +// The Arm Architecture Reference Manual for Armv8-A states: +// +// Instruction accesses to Non-cacheable Normal memory can be held in instruction caches. +// Correspondingly, the sequence for ensuring that modifications to instructions are available +// for execution must include invalidation of the modified locations from the instruction cache, +// even if the instructions are held in Normal Non-cacheable memory. +// This includes cases where the instruction cache is disabled. +// +// To invalidate the AArch64 instruction cache after scatter-loading and before initialization of the stack and heap, +// it is necessary for the user to: +// +// * Implement instruction cache invalidation code in _platform_pre_stackheap_init. +// * Ensure all code on the path from the program entry up to and including _platform_pre_stackheap_init is located in a root region. +// +// In this example, this function is only called once, by the primary core + + .global _platform_pre_stackheap_init + .type _platform_pre_stackheap_init, "function" + .cfi_startproc +_platform_pre_stackheap_init: + dsb ish // ensure all previous stores have completed before invalidating + ic ialluis // I cache invalidate all inner shareable to PoU (which includes secondary cores) + dsb ish // ensure completion on inner shareable domain (which includes secondary cores) + isb + + // Scatter-loading is complete, so enable the caches here, so that the C-library's mutex initialization later will work + mrs x1, SCTLR_EL1 + orr x1, x1, #SCTLR_ELx_C + orr x1, x1, #SCTLR_ELx_I + msr SCTLR_EL1, x1 + isb + + ret + .cfi_endproc + + +// ------------------------------------------------------------ +// EL1 - secondary CPU init code +// +// This code is run on CPUs 1, 2, 3 etc.... +// ------------------------------------------------------------ + + .global el1_secondary + .type el1_secondary, "function" +el1_secondary: + + // + // the primary CPU is going to use SGI 15 as a wakeup event + // to let us know when it is OK to proceed, so prepare for + // receiving that interrupt + // + // NS interrupt priorities run from 0 to 15, with 15 being + // too low a priority to ever raise an interrupt, so let's + // use 14 + // + mov w0, w20 + mov w1, #15 + mov w2, #14 << 4 // we're in NS world, so 4 bits of priority, + // 8-bit field, - 4 = 4-bit shift + bl SetPrivateIntPriority + + mov w0, w20 + mov w1, #15 + bl EnablePrivateInt + + // + // set priority mask as low as possible; although,being in the + // NS World, we can't set bit[7] of the priority, we still + // write all 8-bits of priority to an ICC register + // + mov x0, #31 << 3 + msr ICC_PMR_EL1, x0 + + // + // set global enable and wait for our interrupt to arrive + // + mov x0, #1 + msr ICC_IGRPEN1_EL1, x0 + isb + +loop_wfi: + dsb SY // Clear all pending data accesses + wfi // Go to sleep + + // + // something woke us from our wait, was it the required interrupt? + // + mov w0, w20 + mov w1, #15 + bl GetPrivateIntPending + cbz w0, loop_wfi + + // + // it was - there's no need to actually take the interrupt, + // so just clear it + // + mov w0, w20 + mov w1, #15 + bl ClearPrivateIntPending + + // + // Enable the MMU and caches + // + mrs x1, SCTLR_EL1 + orr x1, x1, #SCTLR_ELx_M + orr x1, x1, #SCTLR_ELx_C + orr x1, x1, #SCTLR_ELx_I + bic x1, x1, #SCTLR_ELx_A // Disable alignment fault checking. To enable, change bic to orr + msr SCTLR_EL1, x1 + isb + + // + // Branch to thread start + // + //B MainApp + b __main + diff --git a/ports/cortex_a35/ac6/example_build/sample_threadx/timer_interrupts.c b/ports/cortex_a35/ac6/example_build/sample_threadx/timer_interrupts.c new file mode 100644 index 00000000..8f522217 --- /dev/null +++ b/ports/cortex_a35/ac6/example_build/sample_threadx/timer_interrupts.c @@ -0,0 +1,152 @@ +/* Bare-metal example for Armv8-A FVP Base model */ + +/* Timer and interrupts */ + +/* Copyright (c) 2016-2018 Arm Limited (or its affiliates). All rights reserved. */ +/* Use, modification and redistribution of this file is subject to your possession of a */ +/* valid End User License Agreement for the Arm Product of which these examples are part of */ +/* and your compliance with all applicable terms and conditions of such licence agreement. */ + +#include + +#include "GICv3.h" +#include "GICv3_gicc.h" +#include "sp804_timer.h" + +void _tx_timer_interrupt(void); + +// LED Base address +#define LED_BASE (volatile unsigned int *)0x1C010008 + + +void nudge_leds(void) // Move LEDs along +{ + static int state = 1; + static int value = 1; + + if (state) + { + int max = (1 << 7); + value <<= 1; + if (value == max) + state = 0; + } + else + { + value >>= 1; + if (value == 1) + state = 1; + } + + *LED_BASE = value; // Update LEDs hardware +} + + +// Initialize Timer 0 and Interrupt Controller +void init_timer(void) +{ + // Enable interrupts + __asm("MSR DAIFClr, #0xF"); + setICC_IGRPEN1_EL1(igrpEnable); + + // Configure the SP804 timer to generate an interrupt + setTimerBaseAddress(0x1C110000); + initTimer(0x200, SP804_AUTORELOAD, SP804_GENERATE_IRQ); + startTimer(); + + // The SP804 timer generates SPI INTID 34. Enable + // this ID, and route it to core 0.0.0.0 (this one!) + SetSPIRoute(34, 0, gicdirouter_ModeSpecific); // Route INTID 34 to 0.0.0.0 (this core) + SetSPIPriority(34, 0); // Set INTID 34 to priority to 0 + ConfigureSPI(34, gicdicfgr_Level); // Set INTID 34 as level-sensitive + EnableSPI(34); // Enable INTID 34 +} + + +// -------------------------------------------------------- + +void irqHandler(void) +{ + unsigned int ID; + + ID = getICC_IAR1(); // readIntAck(); + + // Check for reserved IDs + if ((1020 <= ID) && (ID <= 1023)) + { + //printf("irqHandler() - Reserved INTID %d\n\n", ID); + return; + } + + switch(ID) + { + case 34: + // Dual-Timer 0 (SP804) + //printf("irqHandler() - External timer interrupt\n\n"); + nudge_leds(); + clearTimerIrq(); + + /* Call ThreadX timer interrupt processing. */ + _tx_timer_interrupt(); + + break; + + default: + // Unexpected ID value + //printf("irqHandler() - Unexpected INTID %d\n\n", ID); + break; + } + + // Write the End of Interrupt register to tell the GIC + // we've finished handling the interrupt + setICC_EOIR1(ID); // writeAliasedEOI(ID); +} + +// -------------------------------------------------------- + +// Not actually used in this example, but provided for completeness + +void fiqHandler(void) +{ + unsigned int ID; + unsigned int aliased = 0; + + ID = getICC_IAR0(); // readIntAck(); + //printf("fiqHandler() - Read %d from IAR0\n", ID); + + // Check for reserved IDs + if ((1020 <= ID) && (ID <= 1023)) + { + //printf("fiqHandler() - Reserved INTID %d\n\n", ID); + ID = getICC_IAR1(); // readAliasedIntAck(); + //printf("fiqHandler() - Read %d from AIAR\n", ID); + aliased = 1; + + // If still spurious then simply return + if ((1020 <= ID) && (ID <= 1023)) + return; + } + + switch(ID) + { + case 34: + // Dual-Timer 0 (SP804) + //printf("fiqHandler() - External timer interrupt\n\n"); + clearTimerIrq(); + break; + + default: + // Unexpected ID value + //printf("fiqHandler() - Unexpected INTID %d\n\n", ID); + break; + } + + // Write the End of Interrupt register to tell the GIC + // we've finished handling the interrupt + // NOTE: If the ID was read from the Aliased IAR, then + // the aliased EOI register must be used + if (aliased == 0) + setICC_EOIR0(ID); // writeEOI(ID); + else + setICC_EOIR1(ID); // writeAliasedEOI(ID); +} diff --git a/ports/cortex_a35/ac6/example_build/sample_threadx/use_model_semihosting.ds b/ports/cortex_a35/ac6/example_build/sample_threadx/use_model_semihosting.ds new file mode 100644 index 00000000..6fde52b2 --- /dev/null +++ b/ports/cortex_a35/ac6/example_build/sample_threadx/use_model_semihosting.ds @@ -0,0 +1 @@ +set semihosting enabled off diff --git a/ports/cortex_a35/ac6/example_build/sample_threadx/v8_aarch64.S b/ports/cortex_a35/ac6/example_build/sample_threadx/v8_aarch64.S new file mode 100644 index 00000000..f8db3bfe --- /dev/null +++ b/ports/cortex_a35/ac6/example_build/sample_threadx/v8_aarch64.S @@ -0,0 +1,179 @@ +// ------------------------------------------------------------ +// Armv8-A AArch64 - Common helper functions +// +// Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#include "v8_system.h" + + .text + .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + + .global EnableCachesEL1 + .global DisableCachesEL1 + .global InvalidateUDCaches + .global GetMIDR + .global GetMPIDR + .global GetAffinity + .global GetCPUID + +// ------------------------------------------------------------ + +// +// void EnableCachesEL1(void) +// +// enable Instruction and Data caches +// + .type EnableCachesEL1, "function" + .cfi_startproc +EnableCachesEL1: + + mrs x0, SCTLR_EL1 + orr x0, x0, #SCTLR_ELx_I + orr x0, x0, #SCTLR_ELx_C + msr SCTLR_EL1, x0 + + isb + ret + .cfi_endproc + + +// ------------------------------------------------------------ + + .type DisableCachesEL1, "function" + .cfi_startproc +DisableCachesEL1: + + mrs x0, SCTLR_EL1 + bic x0, x0, #SCTLR_ELx_I + bic x0, x0, #SCTLR_ELx_C + msr SCTLR_EL1, x0 + + isb + ret + .cfi_endproc + + +// ------------------------------------------------------------ + +// +// void InvalidateUDCaches(void) +// +// Invalidate data and unified caches +// + .type InvalidateUDCaches, "function" + .cfi_startproc +InvalidateUDCaches: + // From the Armv8-A Architecture Reference Manual + + dmb ish // ensure all prior inner-shareable accesses have been observed + + mrs x0, CLIDR_EL1 + and w3, w0, #0x07000000 // get 2 x level of coherence + lsr w3, w3, #23 + cbz w3, finished + mov w10, #0 // w10 = 2 x cache level + mov w8, #1 // w8 = constant 0b1 +loop_level: + add w2, w10, w10, lsr #1 // calculate 3 x cache level + lsr w1, w0, w2 // extract 3-bit cache type for this level + and w1, w1, #0x7 + cmp w1, #2 + b.lt next_level // no data or unified cache at this level + msr CSSELR_EL1, x10 // select this cache level + isb // synchronize change of csselr + mrs x1, CCSIDR_EL1 // read ccsidr + and w2, w1, #7 // w2 = log2(linelen)-4 + add w2, w2, #4 // w2 = log2(linelen) + ubfx w4, w1, #3, #10 // w4 = max way number, right aligned + clz w5, w4 // w5 = 32-log2(ways), bit position of way in dc operand + lsl w9, w4, w5 // w9 = max way number, aligned to position in dc operand + lsl w16, w8, w5 // w16 = amount to decrement way number per iteration +loop_way: + ubfx w7, w1, #13, #15 // w7 = max set number, right aligned + lsl w7, w7, w2 // w7 = max set number, aligned to position in dc operand + lsl w17, w8, w2 // w17 = amount to decrement set number per iteration +loop_set: + orr w11, w10, w9 // w11 = combine way number and cache number ... + orr w11, w11, w7 // ... and set number for dc operand + dc isw, x11 // do data cache invalidate by set and way + subs w7, w7, w17 // decrement set number + b.ge loop_set + subs x9, x9, x16 // decrement way number + b.ge loop_way +next_level: + add w10, w10, #2 // increment 2 x cache level + cmp w3, w10 + b.gt loop_level + dsb sy // ensure completion of previous cache maintenance operation + isb +finished: + ret + .cfi_endproc + + +// ------------------------------------------------------------ + +// +// ID Register functions +// + + .type GetMIDR, "function" + .cfi_startproc +GetMIDR: + + mrs x0, MIDR_EL1 + ret + .cfi_endproc + + + .type GetMPIDR, "function" + .cfi_startproc +GetMPIDR: + + mrs x0, MPIDR_EL1 + ret + .cfi_endproc + + + .type GetAffinity, "function" + .cfi_startproc +GetAffinity: + + mrs x0, MPIDR_EL1 + ubfx x1, x0, #32, #8 + bfi w0, w1, #24, #8 + ret + .cfi_endproc + + + .type GetCPUID, "function" + .cfi_startproc +GetCPUID: + + mrs x0, MIDR_EL1 + ubfx x0, x0, #4, #12 // extract PartNum + cmp x0, #0xD0D // Cortex-A77 + b.eq DynamIQ + cmp x0, #0xD0B // Cortex-A76 + b.eq DynamIQ + cmp x0, #0xD0A // Cortex-A75 + b.eq DynamIQ + cmp x0, #0xD05 // Cortex-A55 + b.eq DynamIQ + b Others +DynamIQ: + mrs x0, MPIDR_EL1 + ubfx x0, x0, #MPIDR_EL1_AFF1_LSB, #MPIDR_EL1_AFF_WIDTH + ret + +Others: + mrs x0, MPIDR_EL1 + ubfx x1, x0, #MPIDR_EL1_AFF0_LSB, #MPIDR_EL1_AFF_WIDTH + ubfx x2, x0, #MPIDR_EL1_AFF1_LSB, #MPIDR_EL1_AFF_WIDTH + add x0, x1, x2, LSL #2 + ret + .cfi_endproc diff --git a/ports/cortex_a35/ac6/example_build/sample_threadx/v8_aarch64.h b/ports/cortex_a35/ac6/example_build/sample_threadx/v8_aarch64.h new file mode 100644 index 00000000..b09079a4 --- /dev/null +++ b/ports/cortex_a35/ac6/example_build/sample_threadx/v8_aarch64.h @@ -0,0 +1,103 @@ +/* + * + * Armv8-A AArch64 common helper functions + * + * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. + * Use, modification and redistribution of this file is subject to your possession of a + * valid End User License Agreement for the Arm Product of which these examples are part of + * and your compliance with all applicable terms and conditions of such licence agreement. + */ + +#ifndef V8_AARCH64_H +#define V8_AARCH64_H + +/* + * Parameters for data barriers + */ +#define OSHLD 1 +#define OSHST 2 +#define OSH 3 +#define NSHLD 5 +#define NSHST 6 +#define NSH 7 +#define ISHLD 9 +#define ISHST 10 +#define ISH 11 +#define LD 13 +#define ST 14 +#define SY 15 + +/**********************************************************************/ + +/* + * function prototypes + */ + +/* + * void InvalidateUDCaches(void) + * invalidates all Unified and Data Caches + * + * Inputs + * + * + * Returns + * + * + * Side Effects + * guarantees that all levels of cache will be invalidated before + * returning to caller + */ +void InvalidateUDCaches(void); + +/* + * unsigned long long EnableCachesEL1(void) + * enables I- and D- caches at EL1 + * + * Inputs + * + * + * Returns + * New value of SCTLR_EL1 + * + * Side Effects + * context will be synchronised before returning to caller + */ +unsigned long long EnableCachesEL1(void); + +/* + * unsigned long long GetMIDR(void) + * returns the contents of MIDR_EL0 + * + * Inputs + * + * + * Returns + * MIDR_EL0 + */ +unsigned long long GetMIDR(void); + +/* + * unsigned long long GetMPIDR(void) + * returns the contents of MPIDR_EL0 + * + * Inputs + * + * + * Returns + * MPIDR_EL0 + */ +unsigned long long GetMPIDR(void); + +/* + * unsigned int GetCPUID(void) + * returns the Aff0 field of MPIDR_EL0 + * + * Inputs + * + * + * Returns + * MPIDR_EL0[7:0] + */ +unsigned int GetCPUID(void); + +#endif diff --git a/ports/cortex_a35/ac6/example_build/sample_threadx/v8_mmu.h b/ports/cortex_a35/ac6/example_build/sample_threadx/v8_mmu.h new file mode 100644 index 00000000..ee8834fa --- /dev/null +++ b/ports/cortex_a35/ac6/example_build/sample_threadx/v8_mmu.h @@ -0,0 +1,128 @@ +// +// Defines for v8 Memory Model +// +// Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// + +#ifndef V8_MMU_H +#define V8_MMU_H + +// +// Translation Control Register fields +// +// RGN field encodings +// +#define TCR_RGN_NC 0b00 +#define TCR_RGN_WBWA 0b01 +#define TCR_RGN_WT 0b10 +#define TCR_RGN_WBRA 0b11 + +// +// Shareability encodings +// +#define TCR_SHARE_NONE 0b00 +#define TCR_SHARE_OUTER 0b10 +#define TCR_SHARE_INNER 0b11 + +// +// Granule size encodings +// +#define TCR_GRANULE_4K 0b00 +#define TCR_GRANULE_64K 0b01 +#define TCR_GRANULE_16K 0b10 + +// +// Physical Address sizes +// +#define TCR_SIZE_4G 0b000 +#define TCR_SIZE_64G 0b001 +#define TCR_SIZE_1T 0b010 +#define TCR_SIZE_4T 0b011 +#define TCR_SIZE_16T 0b100 +#define TCR_SIZE_256T 0b101 + +// +// Translation Control Register fields +// +#define TCR_EL1_T0SZ_SHIFT 0 +#define TCR_EL1_EPD0 (1 << 7) +#define TCR_EL1_IRGN0_SHIFT 8 +#define TCR_EL1_ORGN0_SHIFT 10 +#define TCR_EL1_SH0_SHIFT 12 +#define TCR_EL1_TG0_SHIFT 14 + +#define TCR_EL1_T1SZ_SHIFT 16 +#define TCR_EL1_A1 (1 << 22) +#define TCR_EL1_EPD1 (1 << 23) +#define TCR_EL1_IRGN1_SHIFT 24 +#define TCR_EL1_ORGN1_SHIFT 26 +#define TCR_EL1_SH1_SHIFT 28 +#define TCR_EL1_TG1_SHIFT 30 +#define TCR_EL1_IPS_SHIFT 32 +#define TCR_EL1_AS (1 << 36) +#define TCR_EL1_TBI0 (1 << 37) +#define TCR_EL1_TBI1 (1 << 38) + +// +// Stage 1 Translation Table descriptor fields +// +#define TT_S1_ATTR_FAULT (0b00 << 0) +#define TT_S1_ATTR_BLOCK (0b01 << 0) // Level 1/2 +#define TT_S1_ATTR_TABLE (0b11 << 0) // Level 0/1/2 +#define TT_S1_ATTR_PAGE (0b11 << 0) // Level 3 + +#define TT_S1_ATTR_MATTR_LSB 2 + +#define TT_S1_ATTR_NS (1 << 5) + +#define TT_S1_ATTR_AP_RW_PL1 (0b00 << 6) +#define TT_S1_ATTR_AP_RW_ANY (0b01 << 6) +#define TT_S1_ATTR_AP_RO_PL1 (0b10 << 6) +#define TT_S1_ATTR_AP_RO_ANY (0b11 << 6) + +#define TT_S1_ATTR_SH_NONE (0b00 << 8) +#define TT_S1_ATTR_SH_OUTER (0b10 << 8) +#define TT_S1_ATTR_SH_INNER (0b11 << 8) + +#define TT_S1_ATTR_AF (1 << 10) +#define TT_S1_ATTR_nG (1 << 11) + +// OA bits [15:12] - If Armv8.2-LPA is implemented, bits[15:12] are bits[51:48] +// and bits[47:16] are bits[47:16] of the output address for a page of memory + +#define TT_S1_ATTR_nT (1 << 16) // Present if Armv8.4-TTRem is implemented, otherwise RES0 + +#define TT_S1_ATTR_DBM (1 << 51) // Present if Armv8.1-TTHM is implemented, otherwise RES0 + +#define TT_S1_ATTR_CONTIG (1 << 52) +#define TT_S1_ATTR_PXN (1 << 53) +#define TT_S1_ATTR_UXN (1 << 54) + +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED + +#define TT_S1_MAIR_DEV_nGnRnE 0b00000000 +#define TT_S1_MAIR_DEV_nGnRE 0b00000100 +#define TT_S1_MAIR_DEV_nGRE 0b00001000 +#define TT_S1_MAIR_DEV_GRE 0b00001100 + +// +// Inner and Outer Normal memory attributes use the same bit patterns +// Outer attributes just need to be shifted up +// +#define TT_S1_MAIR_OUTER_SHIFT 4 + +#define TT_S1_MAIR_WT_TRANS_RA 0b0010 + +#define TT_S1_MAIR_WB_TRANS_RA 0b0110 +#define TT_S1_MAIR_WB_TRANS_RWA 0b0111 + +#define TT_S1_MAIR_WT_RA 0b1010 + +#define TT_S1_MAIR_WB_RA 0b1110 +#define TT_S1_MAIR_WB_RWA 0b1111 + +#endif // V8_MMU_H diff --git a/ports/cortex_a35/ac6/example_build/sample_threadx/v8_system.h b/ports/cortex_a35/ac6/example_build/sample_threadx/v8_system.h new file mode 100644 index 00000000..ff96deff --- /dev/null +++ b/ports/cortex_a35/ac6/example_build/sample_threadx/v8_system.h @@ -0,0 +1,115 @@ +// +// Defines for v8 System Registers +// +// Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// + +#ifndef V8_SYSTEM_H +#define V8_SYSTEM_H + +// +// AArch64 SPSR +// +#define AARCH64_SPSR_EL3h 0b1101 +#define AARCH64_SPSR_EL3t 0b1100 +#define AARCH64_SPSR_EL2h 0b1001 +#define AARCH64_SPSR_EL2t 0b1000 +#define AARCH64_SPSR_EL1h 0b0101 +#define AARCH64_SPSR_EL1t 0b0100 +#define AARCH64_SPSR_EL0t 0b0000 +#define AARCH64_SPSR_RW (1 << 4) +#define AARCH64_SPSR_F (1 << 6) +#define AARCH64_SPSR_I (1 << 7) +#define AARCH64_SPSR_A (1 << 8) +#define AARCH64_SPSR_D (1 << 9) +#define AARCH64_SPSR_IL (1 << 20) +#define AARCH64_SPSR_SS (1 << 21) +#define AARCH64_SPSR_V (1 << 28) +#define AARCH64_SPSR_C (1 << 29) +#define AARCH64_SPSR_Z (1 << 30) +#define AARCH64_SPSR_N (1 << 31) + +// +// Multiprocessor Affinity Register +// +#define MPIDR_EL1_AFF3_LSB 32 +#define MPIDR_EL1_U (1 << 30) +#define MPIDR_EL1_MT (1 << 24) +#define MPIDR_EL1_AFF2_LSB 16 +#define MPIDR_EL1_AFF1_LSB 8 +#define MPIDR_EL1_AFF0_LSB 0 +#define MPIDR_EL1_AFF_WIDTH 8 + +// +// Data Cache Zero ID Register +// +#define DCZID_EL0_BS_LSB 0 +#define DCZID_EL0_BS_WIDTH 4 +#define DCZID_EL0_DZP_LSB 5 +#define DCZID_EL0_DZP (1 << 5) + +// +// System Control Register +// +#define SCTLR_EL1_UCI (1 << 26) +#define SCTLR_ELx_EE (1 << 25) +#define SCTLR_EL1_E0E (1 << 24) +#define SCTLR_ELx_WXN (1 << 19) +#define SCTLR_EL1_nTWE (1 << 18) +#define SCTLR_EL1_nTWI (1 << 16) +#define SCTLR_EL1_UCT (1 << 15) +#define SCTLR_EL1_DZE (1 << 14) +#define SCTLR_ELx_I (1 << 12) +#define SCTLR_EL1_UMA (1 << 9) +#define SCTLR_EL1_SED (1 << 8) +#define SCTLR_EL1_ITD (1 << 7) +#define SCTLR_EL1_THEE (1 << 6) +#define SCTLR_EL1_CP15BEN (1 << 5) +#define SCTLR_EL1_SA0 (1 << 4) +#define SCTLR_ELx_SA (1 << 3) +#define SCTLR_ELx_C (1 << 2) +#define SCTLR_ELx_A (1 << 1) +#define SCTLR_ELx_M (1 << 0) + +// +// Architectural Feature Access Control Register +// +#define CPACR_EL1_TTA (1 << 28) +#define CPACR_EL1_FPEN (3 << 20) + +// +// Architectural Feature Trap Register +// +#define CPTR_ELx_TCPAC (1 << 31) +#define CPTR_ELx_TTA (1 << 20) +#define CPTR_ELx_TFP (1 << 10) + +// +// Secure Configuration Register +// +#define SCR_EL3_TWE (1 << 13) +#define SCR_EL3_TWI (1 << 12) +#define SCR_EL3_ST (1 << 11) +#define SCR_EL3_RW (1 << 10) +#define SCR_EL3_SIF (1 << 9) +#define SCR_EL3_HCE (1 << 8) +#define SCR_EL3_SMD (1 << 7) +#define SCR_EL3_EA (1 << 3) +#define SCR_EL3_FIQ (1 << 2) +#define SCR_EL3_IRQ (1 << 1) +#define SCR_EL3_NS (1 << 0) + +// +// Hypervisor Configuration Register +// +#define HCR_EL2_ID (1 << 33) +#define HCR_EL2_CD (1 << 32) +#define HCR_EL2_RW (1 << 31) +#define HCR_EL2_TRVM (1 << 30) +#define HCR_EL2_HVC (1 << 29) +#define HCR_EL2_TDZ (1 << 28) + +#endif // V8_SYSTEM_H diff --git a/ports/cortex_a35/ac6/example_build/sample_threadx/v8_utils.S b/ports/cortex_a35/ac6/example_build/sample_threadx/v8_utils.S new file mode 100644 index 00000000..f0fcef26 --- /dev/null +++ b/ports/cortex_a35/ac6/example_build/sample_threadx/v8_utils.S @@ -0,0 +1,69 @@ +// +// Simple utility routines for baremetal v8 code +// +// Copyright (c) 2013-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// + +#include "v8_system.h" + + .text + .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + +// +// void *ZeroBlock(void *blockPtr, unsigned int nBytes) +// +// Zero fill a block of memory +// Fill memory pages or similar structures with zeros. +// The byte count must be a multiple of the block fill size (16 bytes) +// +// Inputs: +// blockPtr - base address of block to fill +// nBytes - block size, in bytes +// +// Returns: +// pointer to just filled block, NULL if nBytes is +// incompatible with block fill size +// + .global ZeroBlock + .type ZeroBlock, "function" + .cfi_startproc +ZeroBlock: + + // + // we fill data by steam, 16 bytes at a time: check that + // blocksize is a multiple of that + // + ubfx x2, x1, #0, #4 + cbnz x2, incompatible + + // + // we already have one register full of zeros, get another + // + mov x3, x2 + + // + // OK, set temporary pointer and away we go + // + add x0, x0, x1 + +loop0: + subs x1, x1, #16 + stp x2, x3, [x0, #-16]! + b.ne loop0 + + // + // that's all - x0 will be back to its start value + // + ret + + // + // parameters are incompatible with block size - return + // an indication that this is so + // +incompatible: + mov x0,#0 + ret + .cfi_endproc diff --git a/ports/cortex_a35/ac6/example_build/sample_threadx/vectors.S b/ports/cortex_a35/ac6/example_build/sample_threadx/vectors.S new file mode 100644 index 00000000..9e60e001 --- /dev/null +++ b/ports/cortex_a35/ac6/example_build/sample_threadx/vectors.S @@ -0,0 +1,252 @@ +// ------------------------------------------------------------ +// Armv8-A Vector tables +// +// Copyright (c) 2014-2016 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + + + .global el1_vectors + .global el2_vectors + .global el3_vectors + .global c0sync1 + .global irqHandler + .global fiqHandler + .global irqFirstLevelHandler + .global fiqFirstLevelHandler + + .section EL1VECTORS, "ax" + .align 11 + +// +// Current EL with SP0 +// +el1_vectors: +c0sync1: B c0sync1 + + .balign 0x80 +c0irq1: B irqFirstLevelHandler + + .balign 0x80 +c0fiq1: B fiqFirstLevelHandler + + .balign 0x80 +c0serr1: B c0serr1 + +// +// Current EL with SPx +// + .balign 0x80 +cxsync1: B cxsync1 + + .balign 0x80 +cxirq1: B irqFirstLevelHandler + + .balign 0x80 +cxfiq1: B fiqFirstLevelHandler + + .balign 0x80 +cxserr1: B cxserr1 + +// +// Lower EL using AArch64 +// + .balign 0x80 +l64sync1: B l64sync1 + + .balign 0x80 +l64irq1: B irqFirstLevelHandler + + .balign 0x80 +l64fiq1: B fiqFirstLevelHandler + + .balign 0x80 +l64serr1: B l64serr1 + +// +// Lower EL using AArch32 +// + .balign 0x80 +l32sync1: B l32sync1 + + .balign 0x80 +l32irq1: B irqFirstLevelHandler + + .balign 0x80 +l32fiq1: B fiqFirstLevelHandler + + .balign 0x80 +l32serr1: B l32serr1 + +//---------------------------------------------------------------- + + .section EL2VECTORS, "ax" + .align 11 + +// +// Current EL with SP0 +// +el2_vectors: +c0sync2: B c0sync2 + + .balign 0x80 +c0irq2: B irqFirstLevelHandler + + .balign 0x80 +c0fiq2: B fiqFirstLevelHandler + + .balign 0x80 +c0serr2: B c0serr2 + +// +// Current EL with SPx +// + .balign 0x80 +cxsync2: B cxsync2 + + .balign 0x80 +cxirq2: B irqFirstLevelHandler + + .balign 0x80 +cxfiq2: B fiqFirstLevelHandler + + .balign 0x80 +cxserr2: B cxserr2 + +// +// Lower EL using AArch64 +// + .balign 0x80 +l64sync2: B l64sync2 + + .balign 0x80 +l64irq2: B irqFirstLevelHandler + + .balign 0x80 +l64fiq2: B fiqFirstLevelHandler + + .balign 0x80 +l64serr2: B l64serr2 + +// +// Lower EL using AArch32 +// + .balign 0x80 +l32sync2: B l32sync2 + + .balign 0x80 +l32irq2: B irqFirstLevelHandler + + .balign 0x80 +l32fiq2: B fiqFirstLevelHandler + + .balign 0x80 +l32serr2: B l32serr2 + +//---------------------------------------------------------------- + + .section EL3VECTORS, "ax" + .align 11 + +// +// Current EL with SP0 +// +el3_vectors: +c0sync3: B c0sync3 + + .balign 0x80 +c0irq3: B irqFirstLevelHandler + + .balign 0x80 +c0fiq3: B fiqFirstLevelHandler + + .balign 0x80 +c0serr3: B c0serr3 + +// +// Current EL with SPx +// + .balign 0x80 +cxsync3: B cxsync3 + + .balign 0x80 +cxirq3: B irqFirstLevelHandler + + .balign 0x80 +cxfiq3: B fiqFirstLevelHandler + + .balign 0x80 +cxserr3: B cxserr3 + +// +// Lower EL using AArch64 +// + .balign 0x80 +l64sync3: B l64sync3 + + .balign 0x80 +l64irq3: B irqFirstLevelHandler + + .balign 0x80 +l64fiq3: B fiqFirstLevelHandler + + .balign 0x80 +l64serr3: B l64serr3 + +// +// Lower EL using AArch32 +// + .balign 0x80 +l32sync3: B l32sync3 + + .balign 0x80 +l32irq3: B irqFirstLevelHandler + + .balign 0x80 +l32fiq3: B fiqFirstLevelHandler + + .balign 0x80 +l32serr3: B l32serr3 + + + .section InterruptHandlers, "ax" + .balign 4 + + .type irqFirstLevelHandler, "function" +irqFirstLevelHandler: + MSR SPSel, 0 + STP x29, x30, [sp, #-16]! + BL _tx_thread_context_save + BL irqHandler + B _tx_thread_context_restore + + .type fiqFirstLevelHandler, "function" +fiqFirstLevelHandler: + STP x29, x30, [sp, #-16]! + STP x18, x19, [sp, #-16]! + STP x16, x17, [sp, #-16]! + STP x14, x15, [sp, #-16]! + STP x12, x13, [sp, #-16]! + STP x10, x11, [sp, #-16]! + STP x8, x9, [sp, #-16]! + STP x6, x7, [sp, #-16]! + STP x4, x5, [sp, #-16]! + STP x2, x3, [sp, #-16]! + STP x0, x1, [sp, #-16]! + + BL fiqHandler + + LDP x0, x1, [sp], #16 + LDP x2, x3, [sp], #16 + LDP x4, x5, [sp], #16 + LDP x6, x7, [sp], #16 + LDP x8, x9, [sp], #16 + LDP x10, x11, [sp], #16 + LDP x12, x13, [sp], #16 + LDP x14, x15, [sp], #16 + LDP x16, x17, [sp], #16 + LDP x18, x19, [sp], #16 + LDP x29, x30, [sp], #16 + ERET diff --git a/ports/cortex_a35/ac6/example_build/tx/.cproject b/ports/cortex_a35/ac6/example_build/tx/.cproject new file mode 100644 index 00000000..3df7aaf7 --- /dev/null +++ b/ports/cortex_a35/ac6/example_build/tx/.cproject @@ -0,0 +1,220 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_a35/ac6/example_build/tx/.project b/ports/cortex_a35/ac6/example_build/tx/.project new file mode 100644 index 00000000..863ca5cb --- /dev/null +++ b/ports/cortex_a35/ac6/example_build/tx/.project @@ -0,0 +1,48 @@ + + + tx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + inc_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/inc + + + inc_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/inc + + + src_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/src + + + src_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/src + + + diff --git a/ports/cortex_a35/ac6/example_build/tx/.settings/language.settings.xml b/ports/cortex_a35/ac6/example_build/tx/.settings/language.settings.xml new file mode 100644 index 00000000..830dd5dd --- /dev/null +++ b/ports/cortex_a35/ac6/example_build/tx/.settings/language.settings.xml @@ -0,0 +1,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_a35/ac6/inc/tx_port.h b/ports/cortex_a35/ac6/inc/tx_port.h new file mode 100644 index 00000000..41192cd5 --- /dev/null +++ b/ports/cortex_a35/ac6/inc/tx_port.h @@ -0,0 +1,367 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A35/AC6 */ +/* 6.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef int LONG; +typedef unsigned int ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Override the alignment type to use 64-bit alignment and storage for pointers. */ + +#define ALIGN_TYPE_DEFINED +typedef unsigned long long ALIGN_TYPE; + + +/* Override the free block marker for byte pools to be a 64-bit constant. */ + +#define TX_BYTE_BLOCK_FREE ((ALIGN_TYPE) 0xFFFFEEEEFFFFEEEE) + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 4096 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#define TX_INT_ENABLE 0x00 /* Enable IRQ & FIQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_fp_enable; +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) b = (UINT) __builtin_ctz((unsigned int) m); + +#endif + + +/* Define the internal timer extension to also hold the thread pointer such that _tx_thread_timeout + can figure out what thread timeout to process. */ + +#define TX_TIMER_INTERNAL_EXTENSION VOID *tx_timer_internal_thread_timeout_ptr; + + +/* Define the thread timeout setup logic in _tx_thread_create. */ + +#define TX_THREAD_CREATE_TIMEOUT_SETUP(t) (t) -> tx_thread_timer.tx_timer_internal_timeout_function = &(_tx_thread_timeout); \ + (t) -> tx_thread_timer.tx_timer_internal_timeout_param = 0; \ + (t) -> tx_thread_timer.tx_timer_internal_thread_timeout_ptr = (VOID *) (t); + + +/* Define the thread timeout pointer setup in _tx_thread_timeout. */ + +#define TX_THREAD_TIMEOUT_POINTER_SETUP(t) (t) = (TX_THREAD *) _tx_timer_expired_timer_ptr -> tx_timer_internal_thread_timeout_ptr; + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifndef TX_DISABLE_INLINE + +/* Define macros, with in-line assembly for performance. */ + +__attribute__( ( always_inline ) ) static inline unsigned int __disable_interrupts(void) +{ + +unsigned long long daif_value; + + __asm__ volatile (" MRS %0, DAIF ": "=r" (daif_value) ); + __asm__ volatile (" MSR DAIFSet, 0x3" : : : "memory" ); + return((unsigned int) daif_value); +} + +__attribute__( ( always_inline ) ) static inline void __restore_interrupts(unsigned int daif_value) +{ + +unsigned long long temp; + + temp = (unsigned long long) daif_value; + __asm__ volatile (" MSR DAIF,%0": : "r" (temp): "memory" ); +} + + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_DISABLE interrupt_save = __disable_interrupts(); +#define TX_RESTORE __restore_interrupts(interrupt_save); + +#else + +unsigned int _tx_thread_interrupt_disable(void); +unsigned int _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); +#endif + + +/* Define FP extension for the Cortex-A5x. Each is assumed to be called in the context of the executing + thread. */ + +#ifndef TX_SOURCE_CODE +#define tx_thread_fp_enable _tx_thread_fp_enable +#define tx_thread_fp_disable _tx_thread_fp_disable +#endif + +VOID tx_thread_fp_enable(VOID); +VOID tx_thread_fp_disable(VOID); + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A35/AC6 Version 6.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + + + + diff --git a/ports/cortex_a35/ac6/readme_threadx.txt b/ports/cortex_a35/ac6/readme_threadx.txt new file mode 100644 index 00000000..6dd1a997 --- /dev/null +++ b/ports/cortex_a35/ac6/readme_threadx.txt @@ -0,0 +1,253 @@ + Microsoft's Azure RTOS ThreadX for Cortex-A35 + + Using the ARM Compiler 6 & DS + +1. Import the ThreadX Projects + +In order to build the ThreadX library and the ThreadX SMP demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +into your DS workspace. + + +2. Building the ThreadX run-time Library + +Building the ThreadX library is easy; simply select the Eclipse project file +"tx" and then select the build button. You should now observe the compilation +and assembly of the ThreadX library. This project build produces the ThreadX +library file tx.a. + + +3. Demonstration System + +The ThreadX demonstration is designed to execute under the DS debugger on the +Base_A35x1 Bare Metal simulator. + +Building the demonstration is easy; simply select the sample_threadx project, and +select the build button. Next, in the sample_threadx project, right-click on the +sample_threadx.launch file and select 'Debug As -> sample_threadx'. The debugger is +setup for the Cortex-A35 FVP, so selecting "Debug" will launch the FVP, load +the sample_threadx.axf ELF file and run to the entry point. You are now ready to execute +the ThreadX SMP demonstration. + + +4. System Initialization + +The entry point in ThreadX for the Cortex-A35 using AC6 tools is at label +start64. This is defined within the AC6 compiler's startup code. In addition, +this is where all static and global pre-set C variable initialization processing +takes place. + +The ThreadX tx_initialize_low_level.s file is responsible for determining the +first available RAM address for use by the application, which is supplied as the +sole input parameter to your application definition function, tx_application_define. + + +5. Register Usage and Stack Frames + +The 64-bit AC6 compiler assumes that registers x0-x18 are scratch registers +for each function. All other registers used by a C function must be preserved +by the function. ThreadX takes advantage of this in situations where a context +switch happens as a result of making a ThreadX service call (which is itself a +C function). In such cases, the saved context of a thread is only the +non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + +FP not enabled and TX_THREAD.tx_thread_fp_enable == 0: + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x000 SPSR DAIF + 0x008 ELR 0 + 0x010 x28 x27 + 0x018 reserved x28 + 0x020 x26 x25 + 0x028 x27 x26 + 0x030 x24 x23 + 0x038 x25 x24 + 0x040 x22 x21 + 0x048 x23 x22 + 0x050 x20 x19 + 0x058 x21 x20 + 0x060 x18 x29 + 0x068 x19 x30 + 0x070 x16 + 0x078 x17 + 0x080 x14 + 0x088 x15 + 0x090 x12 + 0x098 x13 + 0x0A0 x10 + 0x0A8 x11 + 0x0B0 x8 + 0x0B8 x9 + 0x0C0 x6 + 0x0C8 x7 + 0x0D0 x4 + 0x0D8 x5 + 0x0E0 x2 + 0x0E8 x3 + 0x0F0 x0 + 0x0F8 x1 + 0x100 x29 + 0x108 x30 + + +FP enabled and TX_THREAD.tx_thread_fp_enable == 1: + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x000 SPSR DAIF + 0x008 ELR 0 + 0x010 FPSR FPSR + 0x018 FPCR FPCR + 0x020 q30 q14 + 0x030 q31 q15 + 0x040 q28 q12 + 0x050 q29 q13 + 0x060 q26 q10 + 0x070 q27 q11 + 0x080 q24 q8 + 0x090 q25 q9 + 0x0A0 q22 x27 + 0x0A8 x28 + 0x0B0 q23 x25 + 0x0B8 x26 + 0x0C0 q20 x23 + 0x0C8 x24 + 0x0D0 q21 x21 + 0x0D8 x22 + 0x0E0 q18 x19 + 0x0E8 x20 + 0x0F0 q19 x29 + 0x0F8 x30 + 0x100 q16 + 0x110 q17 + 0x120 q14 + 0x130 q15 + 0x140 q12 + 0x150 q13 + 0x160 q10 + 0x170 q11 + 0x180 q8 + 0x190 q9 + 0x1A0 q6 + 0x1B0 q7 + 0x1C0 q4 + 0x1D0 q5 + 0x1E0 q2 + 0x1F0 q3 + 0x200 q0 + 0x210 q1 + 0x220 x28 + 0x228 reserved + 0x230 x26 + 0x238 x27 + 0x240 x24 + 0x248 x25 + 0x250 x22 + 0x258 x23 + 0x260 x20 + 0x268 x21 + 0x270 x18 + 0x278 x19 + 0x280 x16 + 0x288 x17 + 0x290 x14 + 0x298 x15 + 0x2A0 x12 + 0x2A8 x13 + 0x2B0 x10 + 0x2B8 x11 + 0x2C0 x8 + 0x2C8 x9 + 0x2D0 x6 + 0x2D8 x7 + 0x2E0 x4 + 0x2E8 x5 + 0x2F0 x2 + 0x2F8 x3 + 0x300 x0 + 0x308 x1 + 0x310 x29 + 0x318 x30 + + + +6. Improving Performance + +The distribution version of ThreadX is built without any compiler optimizations. +This makes it easy to debug because you can trace or set breakpoints inside of +ThreadX itself. Of course, this costs some performance. To make it run faster, +you can change the project settings to the desired compiler optimization level. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-A35 +targets. Interrupts handlers for the 64-bit mode of the Cortex-A35 have the following +format: + + .global irq_handler +irq_handler: + MSR SPSel, 0 + STP x29, x30, [sp, #-16]! + BL _tx_thread_context_save + + /* Your ISR call goes here! */ + BL application_isr_handler + + B _tx_thread_context_restore + +By default, ThreadX assumes EL3 level of execution. Running and taking exceptions in EL1 +and EL2 can be done by simply building the ThreadX library with either EL1 or EL2 defined. + + +8. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, thread sleeps, +timeouts, and application timers. Without such a timer interrupt source, these services +are not functional. However, all other ThreadX services are operational without a +periodic timer source. + + +9. ARM FP Support + +By default, FP support is disabled for each thread. If saving the context of the FP registers +is needed, the following API call must be made from the context of the application thread - before +the FP usage: + +void tx_thread_fp_enable(void); + +After this API is called in the application, FP registers will be saved/restored for this thread if it +is preempted via an interrupt. All other suspension of the this thread will not require the FP registers +to be saved/restored. + +To disable FP register context saving, simply call the following API: + +void tx_thread_fp_disable(void); + + +10. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +09-30-2020 Initial ThreadX 6.1 version for Cortex-A35 using AC6 tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_a35/ac6/src/tx_initialize_low_level.S b/ports/cortex_a35/ac6/src/tx_initialize_low_level.S new file mode 100644 index 00000000..f7843ed3 --- /dev/null +++ b/ports/cortex_a35/ac6/src/tx_initialize_low_level.S @@ -0,0 +1,112 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-A35/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_initialize_low_level(VOID) +{ */ + .global _tx_initialize_low_level + .type _tx_initialize_low_level, @function +_tx_initialize_low_level: + + MSR DAIFSet, 0x3 // Lockout interrupts + + + /* Save the system stack pointer. */ + /* _tx_thread_system_stack_ptr = (VOID_PTR) (sp); */ + + LDR x0, =_tx_thread_system_stack_ptr // Pickup address of system stack ptr + MOV x1, sp // Pickup SP + BIC x1, x1, #0xF // Get 16-bit alignment + STR x1, [x0] // Store system stack + + /* Save the first available memory address. */ + /* _tx_initialize_unused_memory = (VOID_PTR) Image$$ZI$$Limit; */ + + LDR x0, =_tx_initialize_unused_memory // Pickup address of unused memory ptr + LDR x1, =zi_limit // Pickup unused memory address + LDR x1, [x1] // + STR x1, [x0] // Store unused memory address + + /* Done, return to caller. */ + + RET // Return to caller +/* } */ + + +zi_limit: + .quad (Image$$TOP_OF_RAM$$Base) + diff --git a/ports/cortex_a35/ac6/src/tx_thread_context_restore.S b/ports/cortex_a35/ac6/src/tx_thread_context_restore.S new file mode 100644 index 00000000..7dac69b2 --- /dev/null +++ b/ports/cortex_a35/ac6/src/tx_thread_context_restore.S @@ -0,0 +1,302 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + +/* .set ENABLE_ARM_FP,1 */ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore Cortex-A35/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores the interrupt context if it is processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_restore(VOID) +{ */ + .global _tx_thread_context_restore + .type _tx_thread_context_restore, @function +_tx_thread_context_restore: + + /* Lockout interrupts. */ + + MSR DAIFSet, 0x3 // Lockout interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR exit function to indicate an ISR is complete. */ + + BL _tx_execution_isr_exit // Call the ISR exit function +#endif + + /* Determine if interrupts are nested. */ + /* if (--_tx_thread_system_state) + { */ + + LDR x3, =_tx_thread_system_state // Pickup address of system state var + LDR w2, [x3, #0] // Pickup system state + SUB w2, w2, #1 // Decrement the counter + STR w2, [x3, #0] // Store the counter + CMP w2, #0 // Was this the first interrupt? + BEQ __tx_thread_not_nested_restore // If so, not a nested restore + + /* Interrupts are nested. */ + + /* Just recover the saved registers and return to the point of + interrupt. */ + + LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL +#ifdef EL1 + MSR SPSR_EL1, x4 // Setup SPSR for return + MSR ELR_EL1, x5 // Setup point of interrupt +#else +#ifdef EL2 + MSR SPSR_EL2, x4 // Setup SPSR for return + MSR ELR_EL2, x5 // Setup point of interrupt +#else + MSR SPSR_EL3, x4 // Setup SPSR for return + MSR ELR_EL3, x5 // Setup point of interrupt +#endif +#endif + LDP x18, x19, [sp], #16 // Recover x18, x19 + LDP x16, x17, [sp], #16 // Recover x16, x17 + LDP x14, x15, [sp], #16 // Recover x14, x15 + LDP x12, x13, [sp], #16 // Recover x12, x13 + LDP x10, x11, [sp], #16 // Recover x10, x11 + LDP x8, x9, [sp], #16 // Recover x8, x9 + LDP x6, x7, [sp], #16 // Recover x6, x7 + LDP x4, x5, [sp], #16 // Recover x4, x5 + LDP x2, x3, [sp], #16 // Recover x2, x3 + LDP x0, x1, [sp], #16 // Recover x0, x1 + LDP x29, x30, [sp], #16 // Recover x29, x30 + ERET // Return to point of interrupt + + /* } */ +__tx_thread_not_nested_restore: + + /* Determine if a thread was interrupted and no preemption is required. */ + /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) + || (_tx_thread_preempt_disable)) + { */ + + LDR x1, =_tx_thread_current_ptr // Pickup address of current thread ptr + LDR x0, [x1, #0] // Pickup actual current thread pointer + CMP x0, #0 // Is it NULL? + BEQ __tx_thread_idle_system_restore // Yes, idle system was interrupted + + LDR x3, =_tx_thread_preempt_disable // Pickup preempt disable address + LDR w2, [x3, #0] // Pickup actual preempt disable flag + CMP w2, #0 // Is it set? + BNE __tx_thread_no_preempt_restore // Yes, don't preempt this thread + LDR x3, =_tx_thread_execute_ptr // Pickup address of execute thread ptr + LDR x2, [x3, #0] // Pickup actual execute thread pointer + CMP x0, x2 // Is the same thread highest priority? + BNE __tx_thread_preempt_restore // No, preemption needs to happen + + +__tx_thread_no_preempt_restore: + + /* Restore interrupted thread or ISR. */ + + /* Pickup the saved stack pointer. */ + /* sp = _tx_thread_current_ptr -> tx_thread_stack_ptr; */ + + LDR x4, [x0, #8] // Switch to thread stack pointer + MOV sp, x4 // + + /* Recover the saved context and return to the point of interrupt. */ + + LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL1 +#ifdef EL1 + MSR SPSR_EL1, x4 // Setup SPSR for return + MSR ELR_EL1, x5 // Setup point of interrupt +#else +#ifdef EL2 + MSR SPSR_EL2, x4 // Setup SPSR for return + MSR ELR_EL2, x5 // Setup point of interrupt +#else + MSR SPSR_EL3, x4 // Setup SPSR for return + MSR ELR_EL3, x5 // Setup point of interrupt +#endif +#endif + LDP x18, x19, [sp], #16 // Recover x18, x19 + LDP x16, x17, [sp], #16 // Recover x16, x17 + LDP x14, x15, [sp], #16 // Recover x14, x15 + LDP x12, x13, [sp], #16 // Recover x12, x13 + LDP x10, x11, [sp], #16 // Recover x10, x11 + LDP x8, x9, [sp], #16 // Recover x8, x9 + LDP x6, x7, [sp], #16 // Recover x6, x7 + LDP x4, x5, [sp], #16 // Recover x4, x5 + LDP x2, x3, [sp], #16 // Recover x2, x3 + LDP x0, x1, [sp], #16 // Recover x0, x1 + LDP x29, x30, [sp], #16 // Recover x29, x30 + ERET // Return to point of interrupt + + /* } + else + { */ +__tx_thread_preempt_restore: + + LDR x4, [x0, #8] // Switch to thread stack pointer + MOV sp, x4 // + + LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL1 + STP x20, x21, [sp, #-16]! // Save x20, x21 + STP x22, x23, [sp, #-16]! // Save x22, x23 + STP x24, x25, [sp, #-16]! // Save x24, x25 + STP x26, x27, [sp, #-16]! // Save x26, x27 + STP x28, x29, [sp, #-16]! // Save x28, x29 +#ifdef ENABLE_ARM_FP + LDR w3, [x0, #248] // Pickup FP enable flag + CMP w3, #0 // Is FP enabled? + BEQ _skip_fp_save // No, skip FP save + STP q0, q1, [sp, #-32]! // Save q0, q1 + STP q2, q3, [sp, #-32]! // Save q2, q3 + STP q4, q5, [sp, #-32]! // Save q4, q5 + STP q6, q7, [sp, #-32]! // Save q6, q7 + STP q8, q9, [sp, #-32]! // Save q8, q9 + STP q10, q11, [sp, #-32]! // Save q10, q11 + STP q12, q13, [sp, #-32]! // Save q12, q13 + STP q14, q15, [sp, #-32]! // Save q14, q15 + STP q16, q17, [sp, #-32]! // Save q16, q17 + STP q18, q19, [sp, #-32]! // Save q18, q19 + STP q20, q21, [sp, #-32]! // Save q20, q21 + STP q22, q23, [sp, #-32]! // Save q22, q23 + STP q24, q25, [sp, #-32]! // Save q24, q25 + STP q26, q27, [sp, #-32]! // Save q26, q27 + STP q28, q29, [sp, #-32]! // Save q28, q29 + STP q30, q31, [sp, #-32]! // Save q30, q31 + MRS x2, FPSR // Pickup FPSR + MRS x3, FPCR // Pickup FPCR + STP x2, x3, [sp, #-16]! // Save FPSR, FPCR +_skip_fp_save: +#endif + STP x4, x5, [sp, #-16]! // Save x4 (SPSR_EL3), x5 (ELR_E3) + + MOV x3, sp // Move sp into x3 + STR x3, [x0, #8] // Save stack pointer in thread control + // block + LDR x3, =_tx_thread_system_stack_ptr // Pickup address of system stack + LDR x4, [x3, #0] // Pickup system stack pointer + MOV sp, x4 // Setup system stack pointer + + + /* Save the remaining time-slice and disable it. */ + /* if (_tx_timer_time_slice) + { */ + + LDR x3, =_tx_timer_time_slice // Pickup time-slice variable address + LDR w2, [x3, #0] // Pickup time-slice + CMP w2, #0 // Is it active? + BEQ __tx_thread_dont_save_ts // No, don't save it + + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + STR w2, [x0, #36] // Save thread's time-slice + MOV w2, #0 // Clear value + STR w2, [x3, #0] // Disable global time-slice flag + + /* } */ +__tx_thread_dont_save_ts: + + + /* Clear the current task pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + MOV x0, #0 // NULL value + STR x0, [x1, #0] // Clear current thread pointer + + /* Return to the scheduler. */ + /* _tx_thread_schedule(); */ + + /* } */ + +__tx_thread_idle_system_restore: + + /* Just return back to the scheduler! */ + + LDR x1, =_tx_thread_schedule // Build address for _tx_thread_schedule +#ifdef EL1 + MSR ELR_EL1, x1 // Setup point of interrupt +// MOV x1, #0x4 // Setup EL1 return +// MSR spsr_el1, x1 // Move into SPSR +#else +#ifdef EL2 + MSR ELR_EL2, x1 // Setup point of interrupt +// MOV x1, #0x8 // Setup EL2 return +// MSR spsr_el2, x1 // Move into SPSR +#else + MSR ELR_EL3, x1 // Setup point of interrupt +// MOV x1, #0xC // Setup EL3 return +// MSR spsr_el3, x1 // Move into SPSR +#endif +#endif + ERET // Return to scheduler +/* } */ + + diff --git a/ports/cortex_a35/ac6/src/tx_thread_context_save.S b/ports/cortex_a35/ac6/src/tx_thread_context_save.S new file mode 100644 index 00000000..7f1ed3a6 --- /dev/null +++ b/ports/cortex_a35/ac6/src/tx_thread_context_save.S @@ -0,0 +1,228 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save Cortex-A35/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_save(VOID) +{ */ + .global _tx_thread_context_save + .type _tx_thread_context_save, @function +_tx_thread_context_save: + + /* Upon entry to this routine, it is assumed that IRQ/FIQ interrupts are locked + out, x29 (frame pointer), x30 (link register) are saved, we are in EL1, + and all other registers are intact. */ + + /* Check for a nested interrupt condition. */ + /* if (_tx_thread_system_state++) + { */ + + STP x0, x1, [sp, #-16]! // Save x0, x1 + STP x2, x3, [sp, #-16]! // Save x2, x3 + LDR x3, =_tx_thread_system_state // Pickup address of system state var + LDR w2, [x3, #0] // Pickup system state + CMP w2, #0 // Is this the first interrupt? + BEQ __tx_thread_not_nested_save // Yes, not a nested context save + + /* Nested interrupt condition. */ + + ADD w2, w2, #1 // Increment the nested interrupt counter + STR w2, [x3, #0] // Store it back in the variable + + /* Save the rest of the scratch registers on the stack and return to the + calling ISR. */ + + STP x4, x5, [sp, #-16]! // Save x4, x5 + STP x6, x7, [sp, #-16]! // Save x6, x7 + STP x8, x9, [sp, #-16]! // Save x8, x9 + STP x10, x11, [sp, #-16]! // Save x10, x11 + STP x12, x13, [sp, #-16]! // Save x12, x13 + STP x14, x15, [sp, #-16]! // Save x14, x15 + STP x16, x17, [sp, #-16]! // Save x16, x17 + STP x18, x19, [sp, #-16]! // Save x18, x19 +#ifdef EL1 + MRS x0, SPSR_EL1 // Pickup SPSR + MRS x1, ELR_EL1 // Pickup ELR (point of interrupt) +#else +#ifdef EL2 + MRS x0, SPSR_EL2 // Pickup SPSR + MRS x1, ELR_EL2 // Pickup ELR (point of interrupt) +#else + MRS x0, SPSR_EL3 // Pickup SPSR + MRS x1, ELR_EL3 // Pickup ELR (point of interrupt) +#endif +#endif + STP x0, x1, [sp, #-16]! // Save SPSR, ELR + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + STP x29, x30, [sp, #-16]! // Save x29, x30 + BL _tx_execution_isr_enter // Call the ISR enter function + LDP x29, x30, [sp], #16 // Recover x29, x30 +#endif + + /* Return to the ISR. */ + + RET // Return to ISR + +__tx_thread_not_nested_save: + /* } */ + + /* Otherwise, not nested, check to see if a thread was running. */ + /* else if (_tx_thread_current_ptr) + { */ + + ADD w2, w2, #1 // Increment the interrupt counter + STR w2, [x3, #0] // Store it back in the variable + LDR x1, =_tx_thread_current_ptr // Pickup address of current thread ptr + LDR x0, [x1, #0] // Pickup current thread pointer + CMP x0, #0 // Is it NULL? + BEQ __tx_thread_idle_system_save // If so, interrupt occurred in + // scheduling loop - nothing needs saving! + + /* Save minimal context of interrupted thread. */ + + STP x4, x5, [sp, #-16]! // Save x4, x5 + STP x6, x7, [sp, #-16]! // Save x6, x7 + STP x8, x9, [sp, #-16]! // Save x8, x9 + STP x10, x11, [sp, #-16]! // Save x10, x11 + STP x12, x13, [sp, #-16]! // Save x12, x13 + STP x14, x15, [sp, #-16]! // Save x14, x15 + STP x16, x17, [sp, #-16]! // Save x16, x17 + STP x18, x19, [sp, #-16]! // Save x18, x19 +#ifdef EL1 + MRS x4, SPSR_EL1 // Pickup SPSR + MRS x5, ELR_EL1 // Pickup ELR (point of interrupt) +#else +#ifdef EL2 + MRS x4, SPSR_EL2 // Pickup SPSR + MRS x5, ELR_EL2 // Pickup ELR (point of interrupt) +#else + MRS x4, SPSR_EL3 // Pickup SPSR + MRS x5, ELR_EL3 // Pickup ELR (point of interrupt) +#endif +#endif + STP x4, x5, [sp, #-16]! // Save SPSR, ELR + + /* Save the current stack pointer in the thread's control block. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ + + MOV x4, sp // + STR x4, [x0, #8] // Save thread stack pointer + + /* Switch to the system stack. */ + /* sp = _tx_thread_system_stack_ptr; */ + + LDR x3, =_tx_thread_system_stack_ptr // Pickup address of system stack + LDR x4, [x3, #0] // Pickup system stack pointer + MOV sp, x4 // Setup system stack pointer + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + STP x29, x30, [sp, #-16]! // Save x29, x30 + BL _tx_execution_isr_enter // Call the ISR enter function + LDP x29, x30, [sp], #16 // Recover x29, x30 +#endif + + RET // Return to caller + + /* } + else + { */ + +__tx_thread_idle_system_save: + + /* Interrupt occurred in the scheduling loop. */ + + /* Not much to do here, just adjust the stack pointer, and return to IRQ + processing. */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + STP x29, x30, [sp, #-16]! // Save x29, x30 + BL _tx_execution_isr_enter // Call the ISR enter function + LDP x29, x30, [sp], #16 // Recover x29, x30 +#endif + + ADD sp, sp, #48 // Recover saved registers + RET // Continue IRQ processing + + /* } +} */ + + diff --git a/ports/cortex_a35/ac6/src/tx_thread_fp_disable.c b/ports/cortex_a35/ac6/src/tx_thread_fp_disable.c new file mode 100644 index 00000000..2b7a0aac --- /dev/null +++ b/ports/cortex_a35/ac6/src/tx_thread_fp_disable.c @@ -0,0 +1,95 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fp_disable Cortex-A35/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function disables the FP for the currently executing thread. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_fp_disable(VOID) +{ + +TX_THREAD *thread_ptr; +ULONG system_state; + + + /* Pickup the current thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr); + + /* Get the system state. */ + system_state = TX_THREAD_GET_SYSTEM_STATE(); + + /* Make sure it is not NULL. */ + if (thread_ptr != TX_NULL) + { + + /* Thread is running... make sure the call is from the thread context. */ + if (system_state == 0) + { + + /* Yes, now set the FP enable flag to false in the TX_THREAD structure. */ + thread_ptr -> tx_thread_fp_enable = TX_FALSE; + } + } +} + diff --git a/ports/cortex_a35/ac6/src/tx_thread_fp_enable.c b/ports/cortex_a35/ac6/src/tx_thread_fp_enable.c new file mode 100644 index 00000000..431d5598 --- /dev/null +++ b/ports/cortex_a35/ac6/src/tx_thread_fp_enable.c @@ -0,0 +1,95 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fp_enable Cortex-A35/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function enabled the FP for the currently executing thread. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_fp_enable(VOID) +{ + +TX_THREAD *thread_ptr; +ULONG system_state; + + + /* Pickup the current thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr); + + /* Get the system state. */ + system_state = TX_THREAD_GET_SYSTEM_STATE(); + + /* Make sure it is not NULL. */ + if (thread_ptr != TX_NULL) + { + + /* Thread is running... make sure the call is from the thread context. */ + if (system_state == 0) + { + + /* Yes, now setup the FP enable flag in the TX_THREAD structure. */ + thread_ptr -> tx_thread_fp_enable = TX_TRUE; + } + } +} + diff --git a/ports/cortex_a35/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a35/ac6/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..b177e05b --- /dev/null +++ b/ports/cortex_a35/ac6/src/tx_thread_interrupt_control.S @@ -0,0 +1,89 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/*#define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control Cortex-A35/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_control(UINT new_posture) +{ */ + .global _tx_thread_interrupt_control + .type _tx_thread_interrupt_control, @function +_tx_thread_interrupt_control: + + /* Pickup current interrupt lockout posture. */ + + MRS x1, DAIF // Pickup current interrupt posture + + /* Apply the new interrupt posture. */ + + MSR DAIF, x0 // Set new interrupt posture + MOV x0, x1 // Setup return value + RET // Return to caller +/* } */ + diff --git a/ports/cortex_a35/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a35/ac6/src/tx_thread_interrupt_disable.S new file mode 100644 index 00000000..11846ef0 --- /dev/null +++ b/ports/cortex_a35/ac6/src/tx_thread_interrupt_disable.S @@ -0,0 +1,87 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_disable Cortex-A35/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for disabling interrupts */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_disable(void) +{ */ + .global _tx_thread_interrupt_disable + .type _tx_thread_interrupt_disable, @function +_tx_thread_interrupt_disable: + + /* Pickup current interrupt lockout posture. */ + + MRS x0, DAIF // Pickup current interrupt lockout posture + + /* Mask interrupts. */ + + MSR DAIFSet, 0x3 // Lockout interrupts + RET // Return to caller +/* } */ + diff --git a/ports/cortex_a35/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a35/ac6/src/tx_thread_interrupt_restore.S new file mode 100644 index 00000000..8c8bb1b7 --- /dev/null +++ b/ports/cortex_a35/ac6/src/tx_thread_interrupt_restore.S @@ -0,0 +1,85 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_restore Cortex-A35/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for restoring interrupts to the state */ +/* returned by a previous _tx_thread_interrupt_disable call. */ +/* */ +/* INPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_restore(UINT old_posture) +{ */ + .global _tx_thread_interrupt_restore + .type _tx_thread_interrupt_restore, @function +_tx_thread_interrupt_restore: + + /* Restore the old interrupt posture. */ + + MSR DAIF, x0 // Setup the old posture + RET // Return to caller + +/* } */ + diff --git a/ports/cortex_a35/ac6/src/tx_thread_schedule.S b/ports/cortex_a35/ac6/src/tx_thread_schedule.S new file mode 100644 index 00000000..1e8738cb --- /dev/null +++ b/ports/cortex_a35/ac6/src/tx_thread_schedule.S @@ -0,0 +1,240 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + +/* .set ENABLE_ARM_FP,1 */ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule Cortex-A35/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* _tx_thread_context_restore Restore thread's context */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_schedule(VOID) +{ */ + .global _tx_thread_schedule + .type _tx_thread_schedule, @function +_tx_thread_schedule: + + /* Enable interrupts. */ + + MSR DAIFClr, 0x3 // Enable interrupts + + /* Wait for a thread to execute. */ + /* do + { */ + + LDR x1, =_tx_thread_execute_ptr // Address of thread execute ptr + +#ifdef TX_ENABLE_WFI +__tx_thread_schedule_loop: + LDR x0, [x1, #0] // Pickup next thread to execute + CMP x0, #0 // Is it NULL? + BNE _tx_thread_schedule_thread // + WFI // + B __tx_thread_schedule_loop // Keep looking for a thread +_tx_thread_schedule_thread: +#else +__tx_thread_schedule_loop: + LDR x0, [x1, #0] // Pickup next thread to execute + CMP x0, #0 // Is it NULL? + BEQ __tx_thread_schedule_loop // If so, keep looking for a thread +#endif + + /* } + while(_tx_thread_execute_ptr == TX_NULL); */ + + /* Yes! We have a thread to execute. Lockout interrupts and + transfer control to it. */ + + MSR DAIFSet, 0x3 // Lockout interrupts + + /* Setup the current thread pointer. */ + /* _tx_thread_current_ptr = _tx_thread_execute_ptr; */ + + LDR x1, =_tx_thread_current_ptr // Pickup address of current thread + STR x0, [x1, #0] // Setup current thread pointer + + /* Increment the run count for this thread. */ + /* _tx_thread_current_ptr -> tx_thread_run_count++; */ + + LDR w2, [x0, #4] // Pickup run counter + LDR w3, [x0, #36] // Pickup time-slice for this thread + ADD w2, w2, #1 // Increment thread run-counter + STR w2, [x0, #4] // Store the new run counter + + /* Setup time-slice, if present. */ + /* _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; */ + + LDR x2, =_tx_timer_time_slice // Pickup address of time slice + // variable + LDR x4, [x0, #8] // Switch stack pointers + MOV sp, x4 // + STR w3, [x2, #0] // Setup time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread entry function to indicate the thread is executing. */ + + MOV x19, x0 // Save x0 + BL _tx_execution_thread_enter // Call the thread execution enter function + MOV x0, x19 // Restore x0 +#endif + + /* Switch to the thread's stack. */ + /* sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; */ + + /* Determine if an interrupt frame or a synchronous task suspension frame + is present. */ + + LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL1 + CMP x5, #0 // Check for synchronous context switch (ELR_EL1 = NULL) + BEQ _tx_solicited_return +#ifdef EL1 + MSR SPSR_EL1, x4 // Setup SPSR for return + MSR ELR_EL1, x5 // Setup point of interrupt +#else +#ifdef EL2 + MSR SPSR_EL2, x4 // Setup SPSR for return + MSR ELR_EL2, x5 // Setup point of interrupt +#else + MSR SPSR_EL3, x4 // Setup SPSR for return + MSR ELR_EL3, x5 // Setup point of interrupt +#endif +#endif +#ifdef ENABLE_ARM_FP + LDR w1, [x0, #248] // Pickup FP enable flag + CMP w1, #0 // Is FP enabled? + BEQ _skip_interrupt_fp_restore // No, skip FP restore + LDP x0, x1, [sp], #16 // Pickup FPSR, FPCR + MSR FPSR, x0 // Recover FPSR + MSR FPCR, x1 // Recover FPCR + LDP q30, q31, [sp], #32 // Recover q30, q31 + LDP q28, q29, [sp], #32 // Recover q28, q29 + LDP q26, q27, [sp], #32 // Recover q26, q27 + LDP q24, q25, [sp], #32 // Recover q24, q25 + LDP q22, q23, [sp], #32 // Recover q22, q23 + LDP q20, q21, [sp], #32 // Recover q20, q21 + LDP q18, q19, [sp], #32 // Recover q18, q19 + LDP q16, q17, [sp], #32 // Recover q16, q17 + LDP q14, q15, [sp], #32 // Recover q14, q15 + LDP q12, q13, [sp], #32 // Recover q12, q13 + LDP q10, q11, [sp], #32 // Recover q10, q11 + LDP q8, q9, [sp], #32 // Recover q8, q9 + LDP q6, q7, [sp], #32 // Recover q6, q7 + LDP q4, q5, [sp], #32 // Recover q4, q5 + LDP q2, q3, [sp], #32 // Recover q2, q3 + LDP q0, q1, [sp], #32 // Recover q0, q1 +_skip_interrupt_fp_restore: +#endif + LDP x28, x29, [sp], #16 // Recover x28 + LDP x26, x27, [sp], #16 // Recover x26, x27 + LDP x24, x25, [sp], #16 // Recover x24, x25 + LDP x22, x23, [sp], #16 // Recover x22, x23 + LDP x20, x21, [sp], #16 // Recover x20, x21 + LDP x18, x19, [sp], #16 // Recover x18, x19 + LDP x16, x17, [sp], #16 // Recover x16, x17 + LDP x14, x15, [sp], #16 // Recover x14, x15 + LDP x12, x13, [sp], #16 // Recover x12, x13 + LDP x10, x11, [sp], #16 // Recover x10, x11 + LDP x8, x9, [sp], #16 // Recover x8, x9 + LDP x6, x7, [sp], #16 // Recover x6, x7 + LDP x4, x5, [sp], #16 // Recover x4, x5 + LDP x2, x3, [sp], #16 // Recover x2, x3 + LDP x0, x1, [sp], #16 // Recover x0, x1 + LDP x29, x30, [sp], #16 // Recover x29, x30 + ERET // Return to point of interrupt + +_tx_solicited_return: + +#ifdef ENABLE_ARM_FP + LDR w1, [x0, #248] // Pickup FP enable flag + CMP w1, #0 // Is FP enabled? + BEQ _skip_solicited_fp_restore // No, skip FP restore + LDP x0, x1, [sp], #16 // Pickup FPSR, FPCR + MSR FPSR, x0 // Recover FPSR + MSR FPCR, x1 // Recover FPCR + LDP q14, q15, [sp], #32 // Recover q14, q15 + LDP q12, q13, [sp], #32 // Recover q12, q13 + LDP q10, q11, [sp], #32 // Recover q10, q11 + LDP q8, q9, [sp], #32 // Recover q8, q9 +_skip_solicited_fp_restore: +#endif + LDP x27, x28, [sp], #16 // Recover x27, x28 + LDP x25, x26, [sp], #16 // Recover x25, x26 + LDP x23, x24, [sp], #16 // Recover x23, x24 + LDP x21, x22, [sp], #16 // Recover x21, x22 + LDP x19, x20, [sp], #16 // Recover x19, x20 + LDP x29, x30, [sp], #16 // Recover x29, x30 + MSR DAIF, x4 // Recover DAIF + RET // Return to caller +/* } */ + + diff --git a/ports/cortex_a35/ac6/src/tx_thread_stack_build.S b/ports/cortex_a35/ac6/src/tx_thread_stack_build.S new file mode 100644 index 00000000..06007fca --- /dev/null +++ b/ports/cortex_a35/ac6/src/tx_thread_stack_build.S @@ -0,0 +1,170 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build Cortex-A35/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +{ */ + .global _tx_thread_stack_build + .type _tx_thread_stack_build, @function +_tx_thread_stack_build: + + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-A5x should look like the following after it is built: + + Stack Top: SSPR Initial SSPR + ELR Point of interrupt + x28 Initial value for x28 + not used Not used + x26 Initial value for x26 + x27 Initial value for x27 + x24 Initial value for x24 + x25 Initial value for x25 + x22 Initial value for x22 + x23 Initial value for x23 + x20 Initial value for x20 + x21 Initial value for x21 + x18 Initial value for x18 + x19 Initial value for x19 + x16 Initial value for x16 + x17 Initial value for x17 + x14 Initial value for x14 + x15 Initial value for x15 + x12 Initial value for x12 + x13 Initial value for x13 + x10 Initial value for x10 + x11 Initial value for x11 + x8 Initial value for x8 + x9 Initial value for x9 + x6 Initial value for x6 + x7 Initial value for x7 + x4 Initial value for x4 + x5 Initial value for x5 + x2 Initial value for x2 + x3 Initial value for x3 + x0 Initial value for x0 + x1 Initial value for x1 + x29 Initial value for x29 (frame pointer) + x30 Initial value for x30 (link register) + 0 For stack backtracing + + Stack Bottom: (higher memory address) */ + + LDR x4, [x0, #24] // Pickup end of stack area + BIC x4, x4, #0xF // Ensure 16-byte alignment + + /* Actually build the stack frame. */ + + MOV x2, #0 // Build clear value + MOV x3, #0 // + + STP x2, x3, [x4, #-16]! // Set backtrace to 0 + STP x2, x3, [x4, #-16]! // Set initial x29, x30 + STP x2, x3, [x4, #-16]! // Set initial x0, x1 + STP x2, x3, [x4, #-16]! // Set initial x2, x3 + STP x2, x3, [x4, #-16]! // Set initial x4, x5 + STP x2, x3, [x4, #-16]! // Set initial x6, x7 + STP x2, x3, [x4, #-16]! // Set initial x8, x9 + STP x2, x3, [x4, #-16]! // Set initial x10, x11 + STP x2, x3, [x4, #-16]! // Set initial x12, x13 + STP x2, x3, [x4, #-16]! // Set initial x14, x15 + STP x2, x3, [x4, #-16]! // Set initial x16, x17 + STP x2, x3, [x4, #-16]! // Set initial x18, x19 + STP x2, x3, [x4, #-16]! // Set initial x20, x21 + STP x2, x3, [x4, #-16]! // Set initial x22, x23 + STP x2, x3, [x4, #-16]! // Set initial x24, x25 + STP x2, x3, [x4, #-16]! // Set initial x26, x27 + STP x2, x3, [x4, #-16]! // Set initial x28 +#ifdef EL1 + MOV x2, #0x4 // Build initial SPSR (EL1) +#else +#ifdef EL2 + MOV x2, #0x8 // Build initial SPSR (EL2) +#else + MOV x2, #0xC // Build initial SPSR (EL3) +#endif +#endif + MOV x3, x1 // Build initial ELR + STP x2, x3, [x4, #-16]! // Set initial SPSR & ELR + + /* Setup stack pointer. */ + /* thread_ptr -> tx_thread_stack_ptr = x2; */ + + STR x4, [x0, #8] // Save stack pointer in thread's + RET // Return to caller + +/* } */ + + diff --git a/ports/cortex_a35/ac6/src/tx_thread_system_return.S b/ports/cortex_a35/ac6/src/tx_thread_system_return.S new file mode 100644 index 00000000..dedc2e54 --- /dev/null +++ b/ports/cortex_a35/ac6/src/tx_thread_system_return.S @@ -0,0 +1,165 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + +/* .set ENABLE_ARM_FP,1 */ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return Cortex-A35/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the ThreadX system. Only a */ +/* minimal context is saved since the compiler assumes temp registers */ +/* are going to get slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_system_return(VOID) +{ */ + .global _tx_thread_system_return + .type _tx_thread_system_return, @function +_tx_thread_system_return: +; +; /* Save minimal context on the stack. */ +; + MRS x0, DAIF // Pickup DAIF + MSR DAIFSet, 0x3 // Lockout interrupts + STP x29, x30, [sp, #-16]! // Save x29 (frame pointer), x30 (link register) + STP x19, x20, [sp, #-16]! // Save x19, x20 + STP x21, x22, [sp, #-16]! // Save x21, x22 + STP x23, x24, [sp, #-16]! // Save x23, x24 + STP x25, x26, [sp, #-16]! // Save x25, x26 + STP x27, x28, [sp, #-16]! // Save x27, x28 + LDR x5, =_tx_thread_current_ptr // Pickup address of current ptr + LDR x6, [x5, #0] // Pickup current thread pointer + +#ifdef ENABLE_ARM_FP + LDR w7, [x6, #248] // Pickup FP enable flag + CMP w7, #0 // Is FP enabled? + BEQ _skip_fp_save // No, skip FP save + STP q8, q9, [sp, #-32]! // Save q8, q9 + STP q10, q11, [sp, #-32]! // Save q10, q11 + STP q12, q13, [sp, #-32]! // Save q12, q13 + STP q14, q15, [sp, #-32]! // Save q14, q15 + MRS x2, FPSR // Pickup FPSR + MRS x3, FPCR // Pickup FPCR + STP x2, x3, [sp, #-16]! // Save FPSR, FPCR +_skip_fp_save: +#endif + + MOV x1, #0 // Clear x1 + STP x0, x1, [sp, #-16]! // Save DAIF and clear value for ELR_EK1 + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread exit function to indicate the thread is no longer executing. */ + + MOV x19, x5 // Save x5 + MOV x20, x6 // Save x6 + BL _tx_execution_thread_exit // Call the thread exit function + MOV x5, x19 // Restore x5 + MOV x6, x20 // Restore x6 +#endif + + LDR x2, =_tx_timer_time_slice // Pickup address of time slice + LDR w1, [x2, #0] // Pickup current time slice + + /* Save current stack and switch to system stack. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ + /* sp = _tx_thread_system_stack_ptr; */ + + MOV x4, sp // + STR x4, [x6, #8] // Save thread stack pointer + LDR x3, =_tx_thread_system_stack_ptr // Pickup address of system stack + LDR x4, [x3, #0] // Pickup system stack pointer + MOV sp, x4 // Setup system stack pointer + + /* Determine if the time-slice is active. */ + /* if (_tx_timer_time_slice) + { */ + + MOV x4, #0 // Build clear value + CMP w1, #0 // Is a time-slice active? + BEQ __tx_thread_dont_save_ts // No, don't save the time-slice + + /* Save the current remaining time-slice. */ + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + STR w4, [x2, #0] // Clear time-slice + STR w1, [x6, #36] // Store current time-slice + + /* } */ +__tx_thread_dont_save_ts: + + /* Clear the current thread pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + STR x4, [x5, #0] // Clear current thread pointer + + B _tx_thread_schedule // Jump to scheduler! + +/* } */ + + diff --git a/ports/cortex_a35/ac6/src/tx_timer_interrupt.S b/ports/cortex_a35/ac6/src/tx_timer_interrupt.S new file mode 100644 index 00000000..a81edb23 --- /dev/null +++ b/ports/cortex_a35/ac6/src/tx_timer_interrupt.S @@ -0,0 +1,240 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_timer.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt Cortex-A35/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_timer_interrupt(VOID) +{ */ + .global _tx_timer_interrupt + .type _tx_timer_interrupt, @function +_tx_timer_interrupt: + + /* Upon entry to this routine, it is assumed that context save has already + been called, and therefore the compiler scratch registers are available + for use. */ + + /* Increment the system clock. */ + /* _tx_timer_system_clock++; */ + + LDR x1, =_tx_timer_system_clock // Pickup address of system clock + LDR w0, [x1, #0] // Pickup system clock + ADD w0, w0, #1 // Increment system clock + STR w0, [x1, #0] // Store new system clock + + /* Test for time-slice expiration. */ + /* if (_tx_timer_time_slice) + { */ + + LDR x3, =_tx_timer_time_slice // Pickup address of time-slice + LDR w2, [x3, #0] // Pickup time-slice + CMP w2, #0 // Is it non-active? + BEQ __tx_timer_no_time_slice // Yes, skip time-slice processing + + /* Decrement the time_slice. */ + /* _tx_timer_time_slice--; */ + + SUB w2, w2, #1 // Decrement the time-slice + STR w2, [x3, #0] // Store new time-slice value + + /* Check for expiration. */ + /* if (__tx_timer_time_slice == 0) */ + + CMP w2, #0 // Has it expired? + BNE __tx_timer_no_time_slice // No, skip expiration processing + + /* Set the time-slice expired flag. */ + /* _tx_timer_expired_time_slice = TX_TRUE; */ + + LDR x3, =_tx_timer_expired_time_slice // Pickup address of expired flag + MOV w0, #1 // Build expired value + STR w0, [x3, #0] // Set time-slice expiration flag + + /* } */ + +__tx_timer_no_time_slice: + + /* Test for timer expiration. */ + /* if (*_tx_timer_current_ptr) + { */ + + LDR x1, =_tx_timer_current_ptr // Pickup current timer pointer addr + LDR x0, [x1, #0] // Pickup current timer + LDR x2, [x0, #0] // Pickup timer list entry + CMP x2, #0 // Is there anything in the list? + BEQ __tx_timer_no_timer // No, just increment the timer + + /* Set expiration flag. */ + /* _tx_timer_expired = TX_TRUE; */ + + LDR x3, =_tx_timer_expired // Pickup expiration flag address + MOV w2, #1 // Build expired value + STR w2, [x3, #0] // Set expired flag + B __tx_timer_done // Finished timer processing + + /* } + else + { */ +__tx_timer_no_timer: + + /* No timer expired, increment the timer pointer. */ + /* _tx_timer_current_ptr++; */ + + ADD x0, x0, #8 // Move to next timer + + /* Check for wrap-around. */ + /* if (_tx_timer_current_ptr == _tx_timer_list_end) */ + + LDR x3, =_tx_timer_list_end // Pickup addr of timer list end + LDR x2, [x3, #0] // Pickup list end + CMP x0, x2 // Are we at list end? + BNE __tx_timer_skip_wrap // No, skip wrap-around logic + + /* Wrap to beginning of list. */ + /* _tx_timer_current_ptr = _tx_timer_list_start; */ + + LDR x3, =_tx_timer_list_start // Pickup addr of timer list start + LDR x0, [x3, #0] // Set current pointer to list start + +__tx_timer_skip_wrap: + + STR x0, [x1, #0] // Store new current timer pointer + /* } */ + +__tx_timer_done: + + + /* See if anything has expired. */ + /* if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) + { */ + + LDR x3, =_tx_timer_expired_time_slice // Pickup addr of expired flag + LDR w2, [x3, #0] // Pickup time-slice expired flag + CMP w2, #0 // Did a time-slice expire? + BNE __tx_something_expired // If non-zero, time-slice expired + LDR x1, =_tx_timer_expired // Pickup addr of other expired flag + LDR w0, [x1, #0] // Pickup timer expired flag + CMP w0, #0 // Did a timer expire? + BEQ __tx_timer_nothing_expired // No, nothing expired + +__tx_something_expired: + + + STP x29, x30, [sp, #-16]! // Save x29 (frame pointer), x30 (link register) + + /* Did a timer expire? */ + /* if (_tx_timer_expired) + { */ + + LDR x1, =_tx_timer_expired // Pickup addr of expired flag + LDR w0, [x1, #0] // Pickup timer expired flag + CMP w0, #0 // Check for timer expiration + BEQ __tx_timer_dont_activate // If not set, skip timer activation + + /* Process timer expiration. */ + /* _tx_timer_expiration_process(); */ + + BL _tx_timer_expiration_process // Call the timer expiration handling routine + + /* } */ +__tx_timer_dont_activate: + + /* Did time slice expire? */ + /* if (_tx_timer_expired_time_slice) + { */ + + LDR x3, =_tx_timer_expired_time_slice // Pickup addr of time-slice expired + LDR w2, [x3, #0] // Pickup the actual flag + CMP w2, #0 // See if the flag is set + BEQ __tx_timer_not_ts_expiration // No, skip time-slice processing + + /* Time slice interrupted thread. */ + /* _tx_thread_time_slice(); */ + + BL _tx_thread_time_slice // Call time-slice processing + + /* } */ + +__tx_timer_not_ts_expiration: + + LDP x29, x30, [sp], #16 // Recover x29, x30 + /* } */ + +__tx_timer_nothing_expired: + + RET // Return to caller + +/* } */ + + diff --git a/ports/cortex_a35/gnu/example_build/sample_threadx/.cproject b/ports/cortex_a35/gnu/example_build/sample_threadx/.cproject new file mode 100644 index 00000000..8a0cf9ac --- /dev/null +++ b/ports/cortex_a35/gnu/example_build/sample_threadx/.cproject @@ -0,0 +1,242 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_a35/gnu/example_build/sample_threadx/.project b/ports/cortex_a35/gnu/example_build/sample_threadx/.project new file mode 100644 index 00000000..a1b15572 --- /dev/null +++ b/ports/cortex_a35/gnu/example_build/sample_threadx/.project @@ -0,0 +1,26 @@ + + + sample_threadx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/ports/cortex_a35/gnu/example_build/sample_threadx/.settings/language.settings.xml b/ports/cortex_a35/gnu/example_build/sample_threadx/.settings/language.settings.xml new file mode 100644 index 00000000..48bda599 --- /dev/null +++ b/ports/cortex_a35/gnu/example_build/sample_threadx/.settings/language.settings.xml @@ -0,0 +1,4616 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_a35/gnu/example_build/sample_threadx/GICv3.h b/ports/cortex_a35/gnu/example_build/sample_threadx/GICv3.h new file mode 100644 index 00000000..23bc7fd8 --- /dev/null +++ b/ports/cortex_a35/gnu/example_build/sample_threadx/GICv3.h @@ -0,0 +1,561 @@ +/* + * GICv3.h - data types and function prototypes for GICv3 utility routines + * + * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. + * Use, modification and redistribution of this file is subject to your possession of a + * valid End User License Agreement for the Arm Product of which these examples are part of + * and your compliance with all applicable terms and conditions of such licence agreement. + */ +#ifndef GICV3_h +#define GICV3_h + +#include + +/* + * extra flags for GICD enable + */ +typedef enum +{ + gicdctlr_EnableGrp0 = (1 << 0), + gicdctlr_EnableGrp1NS = (1 << 1), + gicdctlr_EnableGrp1A = (1 << 1), + gicdctlr_EnableGrp1S = (1 << 2), + gicdctlr_EnableAll = (1 << 2) | (1 << 1) | (1 << 0), + gicdctlr_ARE_S = (1 << 4), /* Enable Secure state affinity routing */ + gicdctlr_ARE_NS = (1 << 5), /* Enable Non-Secure state affinity routing */ + gicdctlr_DS = (1 << 6), /* Disable Security support */ + gicdctlr_E1NWF = (1 << 7) /* Enable "1-of-N" wakeup model */ +} GICDCTLRFlags_t; + +/* + * modes for SPI routing + */ +typedef enum +{ + gicdirouter_ModeSpecific = 0, + gicdirouter_ModeAny = (1 << 31) +} GICDIROUTERBits_t; + +typedef enum +{ + gicdicfgr_Level = 0, + gicdicfgr_Edge = (1 << 1) +} GICDICFGRBits_t; + +typedef enum +{ + gicigroupr_G0S = 0, + gicigroupr_G1NS = (1 << 0), + gicigroupr_G1S = (1 << 2) +} GICIGROUPRBits_t; + +typedef enum +{ + gicrwaker_ProcessorSleep = (1 << 1), + gicrwaker_ChildrenAsleep = (1 << 2) +} GICRWAKERBits_t; + +/**********************************************************************/ + +/* + * Utility macros & functions + */ +#define RANGE_LIMIT(x) ((sizeof(x) / sizeof((x)[0])) - 1) + +static inline uint64_t gicv3PackAffinity(uint32_t aff3, uint32_t aff2, + uint32_t aff1, uint32_t aff0) +{ + /* + * only need to cast aff3 to get type promotion for all affinities + */ + return ((((uint64_t)aff3 & 0xff) << 32) | + ((aff2 & 0xff) << 16) | + ((aff1 & 0xff) << 8) | aff0); +} + +/**********************************************************************/ + +/* + * GIC Distributor Function Prototypes + */ + +/* + * ConfigGICD - configure GIC Distributor prior to enabling it + * + * Inputs: + * + * control - control flags + * + * Returns: + * + * + * + * NOTE: + * + * ConfigGICD() will set an absolute flags value, whereas + * {En,Dis}ableGICD() will only {set,clear} the flag bits + * passed as a parameter + */ +void ConfigGICD(GICDCTLRFlags_t flags); + +/* + * EnableGICD - top-level enable for GIC Distributor + * + * Inputs: + * + * flags - new control flags to set + * + * Returns: + * + * + * + * NOTE: + * + * ConfigGICD() will set an absolute flags value, whereas + * {En,Dis}ableGICD() will only {set,clear} the flag bits + * passed as a parameter + */ +void EnableGICD(GICDCTLRFlags_t flags); + +/* + * DisableGICD - top-level disable for GIC Distributor + * + * Inputs + * + * flags - control flags to clear + * + * Returns + * + * + * + * NOTE: + * + * ConfigGICD() will set an absolute flags value, whereas + * {En,Dis}ableGICD() will only {set,clear} the flag bits + * passed as a parameter + */ +void DisableGICD(GICDCTLRFlags_t flags); + +/* + * SyncAREinGICD - synchronise GICD Address Routing Enable bits + * + * Inputs + * + * flags - absolute flag bits to set in GIC Distributor + * + * dosync - flag whether to wait for ARE bits to match passed + * flag field (dosync = true), or whether to set absolute + * flag bits (dosync = false) + * + * Returns + * + * + * + * NOTE: + * + * This function is used to resolve a race in an MP system whereby secondary + * CPUs cannot reliably program all Redistributor registers until the + * primary CPU has enabled Address Routing. The primary CPU will call this + * function with dosync = false, while the secondaries will call it with + * dosync = true. + */ +void SyncAREinGICD(GICDCTLRFlags_t flags, uint32_t dosync); + +/* + * EnableSPI - enable a specific shared peripheral interrupt + * + * Inputs: + * + * id - which interrupt to enable + * + * Returns: + * + * + */ +void EnableSPI(uint32_t id); + +/* + * DisableSPI - disable a specific shared peripheral interrupt + * + * Inputs: + * + * id - which interrupt to disable + * + * Returns: + * + * + */ +void DisableSPI(uint32_t id); + +/* + * SetSPIPriority - configure the priority for a shared peripheral interrupt + * + * Inputs: + * + * id - interrupt identifier + * + * priority - 8-bit priority to program (see note below) + * + * Returns: + * + * + * + * Note: + * + * The GICv3 architecture makes this function sensitive to the Security + * context in terms of what effect it has on the programmed priority: no + * attempt is made to adjust for the reduced priority range available + * when making Non-Secure accesses to the GIC + */ +void SetSPIPriority(uint32_t id, uint32_t priority); + +/* + * GetSPIPriority - determine the priority for a shared peripheral interrupt + * + * Inputs: + * + * id - interrupt identifier + * + * Returns: + * + * interrupt priority in the range 0 - 0xff + */ +uint32_t GetSPIPriority(uint32_t id); + +/* + * SetSPIRoute - specify interrupt routing when gicdctlr_ARE is enabled + * + * Inputs: + * + * id - interrupt identifier + * + * affinity - prepacked "dotted quad" affinity routing. NOTE: use the + * gicv3PackAffinity() helper routine to generate this input + * + * mode - select routing mode (specific affinity, or any recipient) + * + * Returns: + * + * + */ +void SetSPIRoute(uint32_t id, uint64_t affinity, GICDIROUTERBits_t mode); + +/* + * GetSPIRoute - read ARE-enabled interrupt routing information + * + * Inputs: + * + * id - interrupt identifier + * + * Returns: + * + * routing configuration + */ +uint64_t GetSPIRoute(uint32_t id); + +/* + * SetSPITarget - configure the set of processor targets for an interrupt + * + * Inputs + * + * id - interrupt identifier + * + * target - 8-bit target bitmap + * + * Returns + * + * + */ +void SetSPITarget(uint32_t id, uint32_t target); + +/* + * GetSPITarget - read the set of processor targets for an interrupt + * + * Inputs + * + * id - interrupt identifier + * + * Returns + * + * 8-bit target bitmap + */ +uint32_t GetSPITarget(uint32_t id); + +/* + * ConfigureSPI - setup an interrupt as edge- or level-triggered + * + * Inputs + * + * id - interrupt identifier + * + * config - desired configuration + * + * Returns + * + * + */ +void ConfigureSPI(uint32_t id, GICDICFGRBits_t config); + +/* + * SetSPIPending - mark an interrupt as pending + * + * Inputs + * + * id - interrupt identifier + * + * Returns + * + * + */ +void SetSPIPending(uint32_t id); + +/* + * ClearSPIPending - mark an interrupt as not pending + * + * Inputs + * + * id - interrupt identifier + * + * Returns + * + * + */ +void ClearSPIPending(uint32_t id); + +/* + * GetSPIPending - query whether an interrupt is pending + * + * Inputs + * + * id - interrupt identifier + * + * Returns + * + * pending status + */ +uint32_t GetSPIPending(uint32_t id); + +/* + * SetSPISecurity - mark a shared peripheral interrupt as + * security + * + * Inputs + * + * id - which interrupt to mark + * + * group - the group for the interrupt + * + * Returns + * + * + */ +void SetSPISecurity(uint32_t id, GICIGROUPRBits_t group); + +/* + * SetSPISecurityBlock - mark a block of 32 shared peripheral + * interrupts as security + * + * Inputs: + * + * block - which block to mark (e.g. 1 = Ints 32-63) + * + * group - the group for the interrupts + * + * Returns: + * + * + */ +void SetSPISecurityBlock(uint32_t block, GICIGROUPRBits_t group); + +/* + * SetSPISecurityAll - mark all shared peripheral interrupts + * as security + * + * Inputs: + * + * group - the group for the interrupts + * + * Returns: + * + * + */ +void SetSPISecurityAll(GICIGROUPRBits_t group); + +/**********************************************************************/ + +/* + * GIC Re-Distributor Function Prototypes + * + * The model for calling Redistributor functions is that, rather than + * identifying the target redistributor with every function call, the + * SelectRedistributor() function is used to identify which redistributor + * is to be used for all functions until a different redistributor is + * explicitly selected + */ + +/* + * WakeupGICR - wake up a Redistributor + * + * Inputs: + * + * gicr - which Redistributor to wakeup + * + * Returns: + * + * + */ +void WakeupGICR(uint32_t gicr); + +/* + * EnablePrivateInt - enable a private (SGI/PPI) interrupt + * + * Inputs: + * + * gicr - which Redistributor to program + * + * id - which interrupt to enable + * + * Returns: + * + * + */ +void EnablePrivateInt(uint32_t gicr, uint32_t id); + +/* + * DisablePrivateInt - disable a private (SGI/PPI) interrupt + * + * Inputs: + * + * gicr - which Redistributor to program + * + * id - which interrupt to disable + * + * Returns: + * + * + */ +void DisablePrivateInt(uint32_t gicr, uint32_t id); + +/* + * SetPrivateIntPriority - configure the priority for a private + * (SGI/PPI) interrupt + * + * Inputs: + * + * gicr - which Redistributor to program + * + * id - interrupt identifier + * + * priority - 8-bit priority to program (see note below) + * + * Returns: + * + * + * + * Note: + * + * The GICv3 architecture makes this function sensitive to the Security + * context in terms of what effect it has on the programmed priority: no + * attempt is made to adjust for the reduced priority range available + * when making Non-Secure accesses to the GIC + */ +void SetPrivateIntPriority(uint32_t gicr, uint32_t id, uint32_t priority); + +/* + * GetPrivateIntPriority - configure the priority for a private + * (SGI/PPI) interrupt + * + * Inputs: + * + * gicr - which Redistributor to program + * + * id - interrupt identifier + * + * Returns: + * + * Int priority + */ +uint32_t GetPrivateIntPriority(uint32_t gicr, uint32_t id); + +/* + * SetPrivateIntPending - mark a private (SGI/PPI) interrupt as pending + * + * Inputs + * + * gicr - which Redistributor to program + * + * id - interrupt identifier + * + * Returns + * + * + */ +void SetPrivateIntPending(uint32_t gicr, uint32_t id); + +/* + * ClearPrivateIntPending - mark a private (SGI/PPI) interrupt as not pending + * + * Inputs + * + * gicr - which Redistributor to program + * + * id - interrupt identifier + * + * Returns + * + * + */ +void ClearPrivateIntPending(uint32_t gicr, uint32_t id); + +/* + * GetPrivateIntPending - query whether a private (SGI/PPI) interrupt is pending + * + * Inputs + * + * gicr - which Redistributor to program + * + * id - interrupt identifier + * + * Returns + * + * pending status + */ +uint32_t GetPrivateIntPending(uint32_t gicr, uint32_t id); + +/* + * SetPrivateIntSecurity - mark a private (SGI/PPI) interrupt as + * security + * + * Inputs + * + * gicr - which Redistributor to program + * + * id - which interrupt to mark + * + * group - the group for the interrupt + * + * Returns + * + * + */ +void SetPrivateIntSecurity(uint32_t gicr, uint32_t id, GICIGROUPRBits_t group); + +/* + * SetPrivateIntSecurityBlock - mark all 32 private (SGI/PPI) + * interrupts as security + * + * Inputs: + * + * gicr - which Redistributor to program + * + * group - the group for the interrupt + * + * Returns: + * + * + */ +void SetPrivateIntSecurityBlock(uint32_t gicr, GICIGROUPRBits_t group); + +#endif /* ndef GICV3_h */ + +/* EOF GICv3.h */ diff --git a/ports/cortex_a35/gnu/example_build/sample_threadx/GICv3_aliases.h b/ports/cortex_a35/gnu/example_build/sample_threadx/GICv3_aliases.h new file mode 100644 index 00000000..0928d14c --- /dev/null +++ b/ports/cortex_a35/gnu/example_build/sample_threadx/GICv3_aliases.h @@ -0,0 +1,113 @@ +// +// Aliases for GICv3 registers +// +// Copyright (c) 2016-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// + +#ifndef GICV3_ALIASES_H +#define GICV3_ALIASES_H + +#ifndef __clang__ + +/* + * Mapping of MSR and MRS to physical and virtual CPU interface registers + * + * Arm Generic Interrupt Controller Architecture Specification + * GIC architecture version 3.0 and version 4.0 + * Table 8-5 + */ +#define ICC_AP0R0_EL1 S3_0_C12_C8_4 +#define ICC_AP0R1_EL1 S3_0_C12_C8_5 +#define ICC_AP0R2_EL1 S3_0_C12_C8_6 +#define ICC_AP0R3_EL1 S3_0_C12_C8_7 + +#define ICC_AP1R0_EL1 S3_0_C12_C9_0 +#define ICC_AP1R1_EL1 S3_0_C12_C9_1 +#define ICC_AP1R2_EL1 S3_0_C12_C9_2 +#define ICC_AP1R3_EL1 S3_0_C12_C9_3 + +#define ICC_ASGI1R_EL1 S3_0_C12_C11_6 + +#define ICC_BPR0_EL1 S3_0_C12_C8_3 +#define ICC_BPR1_EL1 S3_0_C12_C12_3 + +#define ICC_CTLR_EL1 S3_0_C12_C12_4 +#define ICC_CTLR_EL3 S3_6_C12_C12_4 + +#define ICC_DIR_EL1 S3_0_C12_C11_1 + +#define ICC_EOIR0_EL1 S3_0_C12_C8_1 +#define ICC_EOIR1_EL1 S3_0_C12_C12_1 + +#define ICC_HPPIR0_EL1 S3_0_C12_C8_2 +#define ICC_HPPIR1_EL1 S3_0_C12_C12_2 + +#define ICC_IAR0_EL1 S3_0_C12_C8_0 +#define ICC_IAR1_EL1 S3_0_C12_C12_0 + +#define ICC_IGRPEN0_EL1 S3_0_C12_C12_6 +#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 +#define ICC_IGRPEN1_EL3 S3_6_C12_C12_7 + +#define ICC_PMR_EL1 S3_0_C4_C6_0 +#define ICC_RPR_EL1 S3_0_C12_C11_3 + +#define ICC_SGI0R_EL1 S3_0_C12_C11_7 +#define ICC_SGI1R_EL1 S3_0_C12_C11_5 + +#define ICC_SRE_EL1 S3_0_C12_C12_5 +#define ICC_SRE_EL2 S3_4_C12_C9_5 +#define ICC_SRE_EL3 S3_6_C12_C12_5 + +/* + * Mapping of MSR and MRS to virtual interface control registers + * + * Arm Generic Interrupt Controller Architecture Specification + * GIC architecture version 3.0 and version 4.0 + * Table 8-6 + */ +#define ICH_AP0R0_EL2 S3_4_C12_C8_0 +#define ICH_AP0R1_EL2 S3_4_C12_C8_1 +#define ICH_AP0R2_EL2 S3_4_C12_C8_2 +#define ICH_AP0R3_EL2 S3_4_C12_C8_3 + +#define ICH_AP1R0_EL2 S3_4_C12_C9_0 +#define ICH_AP1R1_EL2 S3_4_C12_C9_1 +#define ICH_AP1R2_EL2 S3_4_C12_C9_2 +#define ICH_AP1R3_EL2 S3_4_C12_C9_3 + +#define ICH_HCR_EL2 S3_4_C12_C11_0 + +#define ICH_VTR_EL2 S3_4_C12_C11_1 + +#define ICH_MISR_EL2 S3_4_C12_C11_2 + +#define ICH_EISR_EL2 S3_4_C12_C11_3 + +#define ICH_ELRSR_EL2 S3_4_C12_C11_5 + +#define ICH_VMCR_EL2 S3_4_C12_C11_7 + +#define ICH_LR0_EL2 S3_4_C12_C12_0 +#define ICH_LR1_EL2 S3_4_C12_C12_1 +#define ICH_LR2_EL2 S3_4_C12_C12_2 +#define ICH_LR3_EL2 S3_4_C12_C12_3 +#define ICH_LR4_EL2 S3_4_C12_C12_4 +#define ICH_LR5_EL2 S3_4_C12_C12_5 +#define ICH_LR6_EL2 S3_4_C12_C12_6 +#define ICH_LR7_EL2 S3_4_C12_C12_7 +#define ICH_LR8_EL2 S3_4_C12_C13_0 +#define ICH_LR9_EL2 S3_4_C12_C13_1 +#define ICH_LR10_EL2 S3_4_C12_C13_2 +#define ICH_LR11_EL2 S3_4_C12_C13_3 +#define ICH_LR12_EL2 S3_4_C12_C13_4 +#define ICH_LR13_EL2 S3_4_C12_C13_5 +#define ICH_LR14_EL2 S3_4_C12_C13_6 +#define ICH_LR15_EL2 S3_4_C12_C13_7 + +#endif /* not __clang__ */ + +#endif /* GICV3_ALIASES */ diff --git a/ports/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicc.h b/ports/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicc.h new file mode 100644 index 00000000..2b8a2d3e --- /dev/null +++ b/ports/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicc.h @@ -0,0 +1,254 @@ +/* + * GICv3_gicc.h - prototypes and inline functions for GICC system register operations + * + * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. + * Use, modification and redistribution of this file is subject to your possession of a + * valid End User License Agreement for the Arm Product of which these examples are part of + * and your compliance with all applicable terms and conditions of such licence agreement. + */ +#ifndef GICV3_gicc_h +#define GICV3_gicc_h + +#include "GICv3_aliases.h" + +#define stringify_no_expansion(x) #x +#define stringify(x) stringify_no_expansion(x) + +/**********************************************************************/ + +typedef enum +{ + sreSRE = (1 << 0), + sreDFB = (1 << 1), + sreDIB = (1 << 2), + sreEnable = (1 << 3) +} ICC_SREBits_t; + +static inline void setICC_SRE_EL1(ICC_SREBits_t mode) +{ + asm("msr "stringify(ICC_SRE_EL1)", %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline uint64_t getICC_SRE_EL1(void) +{ + uint64_t retc; + + asm("mrs %0, "stringify(ICC_SRE_EL1)"\n" : "=r" (retc)); + + return retc; +} + +static inline void setICC_SRE_EL2(ICC_SREBits_t mode) +{ + asm("msr "stringify(ICC_SRE_EL2)", %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline uint64_t getICC_SRE_EL2(void) +{ + uint64_t retc; + + asm("mrs %0, "stringify(ICC_SRE_EL2)"\n" : "=r" (retc)); + + return retc; +} + +static inline void setICC_SRE_EL3(ICC_SREBits_t mode) +{ + asm("msr "stringify(ICC_SRE_EL3)", %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline uint64_t getICC_SRE_EL3(void) +{ + uint64_t retc; + + asm("mrs %0, "stringify(ICC_SRE_EL3)"\n" : "=r" (retc)); + + return retc; +} + +/**********************************************************************/ + +typedef enum +{ + igrpEnable = (1 << 0), + igrpEnableGrp1NS = (1 << 0), + igrpEnableGrp1S = (1 << 2) +} ICC_IGRPBits_t; + +static inline void setICC_IGRPEN0_EL1(ICC_IGRPBits_t mode) +{ + asm("msr "stringify(ICC_IGRPEN0_EL1)", %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline void setICC_IGRPEN1_EL1(ICC_IGRPBits_t mode) +{ + asm("msr "stringify(ICC_IGRPEN1_EL1)", %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline void setICC_IGRPEN1_EL3(ICC_IGRPBits_t mode) +{ + asm("msr "stringify(ICC_IGRPEN1_EL3)", %0\n; isb" :: "r" ((uint64_t)mode)); +} + +/**********************************************************************/ + +typedef enum +{ + ctlrCBPR = (1 << 0), + ctlrCBPR_EL1S = (1 << 0), + ctlrEOImode = (1 << 1), + ctlrCBPR_EL1NS = (1 << 1), + ctlrEOImode_EL3 = (1 << 2), + ctlrEOImode_EL1S = (1 << 3), + ctlrEOImode_EL1NS = (1 << 4), + ctlrRM = (1 << 5), + ctlrPMHE = (1 << 6) +} ICC_CTLRBits_t; + +static inline void setICC_CTLR_EL1(ICC_CTLRBits_t mode) +{ + asm("msr "stringify(ICC_CTLR_EL1)", %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline uint64_t getICC_CTLR_EL1(void) +{ + uint64_t retc; + + asm("mrs %0, "stringify(ICC_CTLR_EL1)"\n" : "=r" (retc)); + + return retc; +} + +static inline void setICC_CTLR_EL3(ICC_CTLRBits_t mode) +{ + asm("msr "stringify(ICC_CTLR_EL3)", %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline uint64_t getICC_CTLR_EL3(void) +{ + uint64_t retc; + + asm("mrs %0, "stringify(ICC_CTLR_EL3)"\n" : "=r" (retc)); + + return retc; +} + +/**********************************************************************/ + +static inline uint64_t getICC_IAR0(void) +{ + uint64_t retc; + + asm("mrs %0, "stringify(ICC_IAR0_EL1)"\n" : "=r" (retc)); + + return retc; +} + +static inline uint64_t getICC_IAR1(void) +{ + uint64_t retc; + + asm("mrs %0, "stringify(ICC_IAR1_EL1)"\n" : "=r" (retc)); + + return retc; +} + +static inline void setICC_EOIR0(uint32_t interrupt) +{ + asm("msr "stringify(ICC_EOIR0_EL1)", %0\n; isb" :: "r" ((uint64_t)interrupt)); +} + +static inline void setICC_EOIR1(uint32_t interrupt) +{ + asm("msr "stringify(ICC_EOIR1_EL1)", %0\n; isb" :: "r" ((uint64_t)interrupt)); +} + +static inline void setICC_DIR(uint32_t interrupt) +{ + asm("msr "stringify(ICC_DIR_EL1)", %0\n; isb" :: "r" ((uint64_t)interrupt)); +} + +static inline void setICC_PMR(uint32_t priority) +{ + asm("msr "stringify(ICC_PMR_EL1)", %0\n; isb" :: "r" ((uint64_t)priority)); +} + +static inline void setICC_BPR0(uint32_t binarypoint) +{ + asm("msr "stringify(ICC_BPR0_EL1)", %0\n; isb" :: "r" ((uint64_t)binarypoint)); +} + +static inline void setICC_BPR1(uint32_t binarypoint) +{ + asm("msr "stringify(ICC_BPR1_EL1)", %0\n; isb" :: "r" ((uint64_t)binarypoint)); +} + +static inline uint64_t getICC_BPR0(void) +{ + uint64_t retc; + + asm("mrs %0, "stringify(ICC_BPR0_EL1)"\n" : "=r" (retc)); + + return retc; +} + +static inline uint64_t getICC_BPR1(void) +{ + uint64_t retc; + + asm("mrs %0, "stringify(ICC_BPR1_EL1)"\n" : "=r" (retc)); + + return retc; +} + +static inline uint64_t getICC_RPR(void) +{ + uint64_t retc; + + asm("mrs %0, "stringify(ICC_RPR_EL1)"\n" : "=r" (retc)); + + return retc; +} + +/**********************************************************************/ + +typedef enum +{ + sgirIRMTarget = 0, + sgirIRMAll = (1ull << 40) +} ICC_SGIRBits_t; + +static inline void setICC_SGI0R(uint8_t aff3, uint8_t aff2, + uint8_t aff1, ICC_SGIRBits_t irm, + uint16_t targetlist, uint8_t intid) +{ + uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \ + ((uint64_t)aff1 << 16) | irm | targetlist | \ + ((uint64_t)(intid & 0x0f) << 24)); + + asm("msr "stringify(ICC_SGI0R_EL1)", %0\n; isb" :: "r" (packedbits)); +} + +static inline void setICC_SGI1R(uint8_t aff3, uint8_t aff2, + uint8_t aff1, ICC_SGIRBits_t irm, + uint16_t targetlist, uint8_t intid) +{ + uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \ + ((uint64_t)aff1 << 16) | irm | targetlist | \ + ((uint64_t)(intid & 0x0f) << 24)); + + asm("msr "stringify(ICC_SGI1R_EL1)", %0\n; isb" :: "r" (packedbits)); +} + +static inline void setICC_ASGI1R(uint8_t aff3, uint8_t aff2, + uint8_t aff1, ICC_SGIRBits_t irm, + uint16_t targetlist, uint8_t intid) +{ + uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \ + ((uint64_t)aff1 << 16) | irm | targetlist | \ + ((uint64_t)(intid & 0x0f) << 24)); + + asm("msr "stringify(ICC_ASGI1R_EL1)", %0\n; isb" :: "r" (packedbits)); +} + +#endif /* ndef GICV3_gicc_h */ diff --git a/ports/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicd.c b/ports/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicd.c new file mode 100644 index 00000000..2cf9e843 --- /dev/null +++ b/ports/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicd.c @@ -0,0 +1,339 @@ +/* + * GICv3_gicd.c - generic driver code for GICv3 distributor + * + * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. + * Use, modification and redistribution of this file is subject to your possession of a + * valid End User License Agreement for the Arm Product of which these examples are part of + * and your compliance with all applicable terms and conditions of such licence agreement. + */ +#include + +#include "GICv3.h" + +typedef struct +{ + volatile uint32_t GICD_CTLR; // +0x0000 + const volatile uint32_t GICD_TYPER; // +0x0004 + const volatile uint32_t GICD_IIDR; // +0x0008 + + const volatile uint32_t padding0; // +0x000c + + volatile uint32_t GICD_STATUSR; // +0x0010 + + const volatile uint32_t padding1[3]; // +0x0014 + + volatile uint32_t IMP_DEF[8]; // +0x0020 + + volatile uint32_t GICD_SETSPI_NSR; // +0x0040 + const volatile uint32_t padding2; // +0x0044 + volatile uint32_t GICD_CLRSPI_NSR; // +0x0048 + const volatile uint32_t padding3; // +0x004c + volatile uint32_t GICD_SETSPI_SR; // +0x0050 + const volatile uint32_t padding4; // +0x0054 + volatile uint32_t GICD_CLRSPI_SR; // +0x0058 + + const volatile uint32_t padding5[3]; // +0x005c + + volatile uint32_t GICD_SEIR; // +0x0068 + + const volatile uint32_t padding6[5]; // +0x006c + + volatile uint32_t GICD_IGROUPR[32]; // +0x0080 + + volatile uint32_t GICD_ISENABLER[32]; // +0x0100 + volatile uint32_t GICD_ICENABLER[32]; // +0x0180 + volatile uint32_t GICD_ISPENDR[32]; // +0x0200 + volatile uint32_t GICD_ICPENDR[32]; // +0x0280 + volatile uint32_t GICD_ISACTIVER[32]; // +0x0300 + volatile uint32_t GICD_ICACTIVER[32]; // +0x0380 + + volatile uint8_t GICD_IPRIORITYR[1024]; // +0x0400 + volatile uint8_t GICD_ITARGETSR[1024]; // +0x0800 + volatile uint32_t GICD_ICFGR[64]; // +0x0c00 + volatile uint32_t GICD_IGRPMODR[32]; // +0x0d00 + const volatile uint32_t padding7[32]; // +0x0d80 + volatile uint32_t GICD_NSACR[64]; // +0x0e00 + + volatile uint32_t GICD_SGIR; // +0x0f00 + + const volatile uint32_t padding8[3]; // +0x0f04 + + volatile uint32_t GICD_CPENDSGIR[4]; // +0x0f10 + volatile uint32_t GICD_SPENDSGIR[4]; // +0x0f20 + + const volatile uint32_t padding9[52]; // +0x0f30 + const volatile uint32_t padding10[5120]; // +0x1000 + + volatile uint64_t GICD_IROUTER[1024]; // +0x6000 +} GICv3_distributor; + +/* + * use the scatter file to place GICD + */ +GICv3_distributor __attribute__((section(".gicd"))) gicd; + +void ConfigGICD(GICDCTLRFlags_t flags) +{ + gicd.GICD_CTLR = flags; +} + +void EnableGICD(GICDCTLRFlags_t flags) +{ + gicd.GICD_CTLR |= flags; +} + +void DisableGICD(GICDCTLRFlags_t flags) +{ + gicd.GICD_CTLR &= ~flags; +} + +void SyncAREinGICD(GICDCTLRFlags_t flags, uint32_t dosync) +{ + if (dosync) + { + const uint32_t tmask = gicdctlr_ARE_S | gicdctlr_ARE_NS; + const uint32_t tval = flags & tmask; + + while ((gicd.GICD_CTLR & tmask) != tval) + continue; + } + else + gicd.GICD_CTLR = flags; +} + +void EnableSPI(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_ISENABLER has 32 interrupts per register + */ + bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); + id &= 32 - 1; + + gicd.GICD_ISENABLER[bank] = 1 << id; + + return; +} + +void DisableSPI(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_ISENABLER has 32 interrupts per register + */ + bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); + id &= 32 - 1; + + gicd.GICD_ICENABLER[bank] = 1 << id; + + return; +} + +void SetSPIPriority(uint32_t id, uint32_t priority) +{ + uint32_t bank; + + /* + * GICD_IPRIORITYR has one byte-wide entry per interrupt + */ + bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR); + + gicd.GICD_IPRIORITYR[bank] = priority; +} + +uint32_t GetSPIPriority(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_IPRIORITYR has one byte-wide entry per interrupt + */ + bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR); + + return (uint32_t)(gicd.GICD_IPRIORITYR[bank]); +} + +void SetSPIRoute(uint32_t id, uint64_t affinity, GICDIROUTERBits_t mode) +{ + uint32_t bank; + + /* + * GICD_IROUTER has one doubleword-wide entry per interrupt + */ + bank = id & RANGE_LIMIT(gicd.GICD_IROUTER); + + gicd.GICD_IROUTER[bank] = affinity | (uint64_t)mode; +} + +uint64_t GetSPIRoute(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_IROUTER has one doubleword-wide entry per interrupt + */ + bank = id & RANGE_LIMIT(gicd.GICD_IROUTER); + + return gicd.GICD_IROUTER[bank]; +} + +void SetSPITarget(uint32_t id, uint32_t target) +{ + uint32_t bank; + + /* + * GICD_ITARGETSR has one byte-wide entry per interrupt + */ + bank = id & RANGE_LIMIT(gicd.GICD_ITARGETSR); + + gicd.GICD_ITARGETSR[bank] = target; +} + +uint32_t GetSPITarget(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_ITARGETSR has one byte-wide entry per interrupt + */ + /* + * GICD_ITARGETSR has 4 interrupts per register, i.e. 8-bits of + * target bitmap per register + */ + bank = id & RANGE_LIMIT(gicd.GICD_ITARGETSR); + + return (uint32_t)(gicd.GICD_ITARGETSR[bank]); +} + +void ConfigureSPI(uint32_t id, GICDICFGRBits_t config) +{ + uint32_t bank, tmp; + + /* + * GICD_ICFGR has 16 interrupts per register, i.e. 2-bits of + * configuration per register + */ + bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); + config &= 3; + + id = (id & 0xf) << 1; + + tmp = gicd.GICD_ICFGR[bank]; + tmp &= ~(3 << id); + tmp |= config << id; + gicd.GICD_ICFGR[bank] = tmp; +} + +void SetSPIPending(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_ISPENDR has 32 interrupts per register + */ + bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISPENDR); + id &= 0x1f; + + gicd.GICD_ISPENDR[bank] = 1 << id; +} + +void ClearSPIPending(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_ICPENDR has 32 interrupts per register + */ + bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICPENDR); + id &= 0x1f; + + gicd.GICD_ICPENDR[bank] = 1 << id; +} + +uint32_t GetSPIPending(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_ICPENDR has 32 interrupts per register + */ + bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICPENDR); + id &= 0x1f; + + return (gicd.GICD_ICPENDR[bank] >> id) & 1; +} + +void SetSPISecurity(uint32_t id, GICIGROUPRBits_t group) +{ + uint32_t bank, groupmod; + + /* + * GICD_IGROUPR has 32 interrupts per register + */ + bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_IGROUPR); + id &= 0x1f; + + /* + * the single group argument is split into two separate + * registers, so filter out and remove the (new to gicv3) + * group modifier bit + */ + groupmod = (group >> 1) & 1; + group &= 1; + + /* + * either set or clear the Group bit for the interrupt as appropriate + */ + if (group) + gicd.GICD_IGROUPR[bank] |= 1 << id; + else + gicd.GICD_IGROUPR[bank] &= ~(1 << id); + + /* + * now deal with groupmod + */ + if (groupmod) + gicd.GICD_IGRPMODR[bank] |= 1 << id; + else + gicd.GICD_IGRPMODR[bank] &= ~(1 << id); +} + +void SetSPISecurityBlock(uint32_t block, GICIGROUPRBits_t group) +{ + uint32_t groupmod; + const uint32_t nbits = (sizeof group * 8) - 1; + + /* + * GICD_IGROUPR has 32 interrupts per register + */ + block &= RANGE_LIMIT(gicd.GICD_IGROUPR); + + /* + * get each bit of group config duplicated over all 32-bits in a word + */ + groupmod = (uint32_t)(((int32_t)group << (nbits - 1)) >> 31); + group = (uint32_t)(((int32_t)group << nbits) >> 31); + + /* + * set the security state for this block of SPIs + */ + gicd.GICD_IGROUPR[block] = group; + gicd.GICD_IGRPMODR[block] = groupmod; +} + +void SetSPISecurityAll(GICIGROUPRBits_t group) +{ + uint32_t block; + + /* + * GICD_TYPER.ITLinesNumber gives (No. SPIS / 32) - 1, and we + * want to iterate over all blocks excluding 0 (which are the + * SGI/PPI interrupts, and not relevant here) + */ + for (block = (gicd.GICD_TYPER & ((1 << 5) - 1)); block > 0; --block) + SetSPISecurityBlock(block, group); +} + +/* EOF GICv3_gicd.c */ diff --git a/ports/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicr.c b/ports/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicr.c new file mode 100644 index 00000000..b0d22c40 --- /dev/null +++ b/ports/cortex_a35/gnu/example_build/sample_threadx/GICv3_gicr.c @@ -0,0 +1,308 @@ +/* + * GICv3_gicr.c - generic driver code for GICv3 redistributor + * + * Copyright (c) 2014-2019 Arm Limited (or its affiliates). All rights reserved. + * Use, modification and redistribution of this file is subject to your possession of a + * valid End User License Agreement for the Arm Product of which these examples are part of + * and your compliance with all applicable terms and conditions of such licence agreement. + */ +#include "GICv3.h" + +/* + * physical LPI Redistributor register map + */ +typedef struct +{ + volatile uint32_t GICR_CTLR; // +0x0000 - RW - Redistributor Control Register + const volatile uint32_t GICR_IIDR; // +0x0004 - RO - Implementer Identification Register + const volatile uint32_t GICR_TYPER[2]; // +0x0008 - RO - Redistributor Type Register + volatile uint32_t GICR_STATUSR; // +0x0010 - RW - Error Reporting Status Register, optional + volatile uint32_t GICR_WAKER; // +0x0014 - RW - Redistributor Wake Register + const volatile uint32_t padding1[2]; // +0x0018 - RESERVED +#ifndef USE_GIC600 + volatile uint32_t IMPDEF1[8]; // +0x0020 - ?? - IMPLEMENTATION DEFINED +#else + volatile uint32_t GICR_FCTLR; // +0x0020 - RW - Function Control Register + volatile uint32_t GICR_PWRR; // +0x0024 - RW - Power Management Control Register + volatile uint32_t GICR_CLASS; // +0x0028 - RW - Class Register + const volatile uint32_t padding2[5]; // +0x002C - RESERVED +#endif + volatile uint64_t GICR_SETLPIR; // +0x0040 - WO - Set LPI Pending Register + volatile uint64_t GICR_CLRLPIR; // +0x0048 - WO - Clear LPI Pending Register + const volatile uint32_t padding3[8]; // +0x0050 - RESERVED + volatile uint64_t GICR_PROPBASER; // +0x0070 - RW - Redistributor Properties Base Address Register + volatile uint64_t GICR_PENDBASER; // +0x0078 - RW - Redistributor LPI Pending Table Base Address Register + const volatile uint32_t padding4[8]; // +0x0080 - RESERVED + volatile uint64_t GICR_INVLPIR; // +0x00A0 - WO - Redistributor Invalidate LPI Register + const volatile uint32_t padding5[2]; // +0x00A8 - RESERVED + volatile uint64_t GICR_INVALLR; // +0x00B0 - WO - Redistributor Invalidate All Register + const volatile uint32_t padding6[2]; // +0x00B8 - RESERVED + volatile uint64_t GICR_SYNCR; // +0x00C0 - RO - Redistributor Synchronize Register + const volatile uint32_t padding7[2]; // +0x00C8 - RESERVED + const volatile uint32_t padding8[12]; // +0x00D0 - RESERVED + volatile uint64_t IMPDEF2; // +0x0100 - WO - IMPLEMENTATION DEFINED + const volatile uint32_t padding9[2]; // +0x0108 - RESERVED + volatile uint64_t IMPDEF3; // +0x0110 - WO - IMPLEMENTATION DEFINED + const volatile uint32_t padding10[2]; // +0x0118 - RESERVED +} GICv3_redistributor_RD; + +/* + * SGI and PPI Redistributor register map + */ +typedef struct +{ + const volatile uint32_t padding1[32]; // +0x0000 - RESERVED + volatile uint32_t GICR_IGROUPR0; // +0x0080 - RW - Interrupt Group Registers (Security Registers in GICv1) + const volatile uint32_t padding2[31]; // +0x0084 - RESERVED + volatile uint32_t GICR_ISENABLER; // +0x0100 - RW - Interrupt Set-Enable Registers + const volatile uint32_t padding3[31]; // +0x0104 - RESERVED + volatile uint32_t GICR_ICENABLER; // +0x0180 - RW - Interrupt Clear-Enable Registers + const volatile uint32_t padding4[31]; // +0x0184 - RESERVED + volatile uint32_t GICR_ISPENDR; // +0x0200 - RW - Interrupt Set-Pending Registers + const volatile uint32_t padding5[31]; // +0x0204 - RESERVED + volatile uint32_t GICR_ICPENDR; // +0x0280 - RW - Interrupt Clear-Pending Registers + const volatile uint32_t padding6[31]; // +0x0284 - RESERVED + volatile uint32_t GICR_ISACTIVER; // +0x0300 - RW - Interrupt Set-Active Register + const volatile uint32_t padding7[31]; // +0x0304 - RESERVED + volatile uint32_t GICR_ICACTIVER; // +0x0380 - RW - Interrupt Clear-Active Register + const volatile uint32_t padding8[31]; // +0x0184 - RESERVED + volatile uint8_t GICR_IPRIORITYR[32]; // +0x0400 - RW - Interrupt Priority Registers + const volatile uint32_t padding9[504]; // +0x0420 - RESERVED + volatile uint32_t GICR_ICnoFGR[2]; // +0x0C00 - RW - Interrupt Configuration Registers + const volatile uint32_t padding10[62]; // +0x0C08 - RESERVED + volatile uint32_t GICR_IGRPMODR0; // +0x0D00 - RW - ???? + const volatile uint32_t padding11[63]; // +0x0D04 - RESERVED + volatile uint32_t GICR_NSACR; // +0x0E00 - RW - Non-Secure Access Control Register +} GICv3_redistributor_SGI; + +/* + * We have a multiplicity of GIC Redistributors; on the GIC-AEM and + * GIC-500 they are arranged as one 128KB region per redistributor: one + * 64KB page of GICR LPI registers, and one 64KB page of GICR Private + * Int registers + */ +typedef struct +{ + union + { + GICv3_redistributor_RD RD_base; + uint8_t padding[64 * 1024]; + } RDblock; + + union + { + GICv3_redistributor_SGI SGI_base; + uint8_t padding[64 * 1024]; + } SGIblock; +} GICv3_GICR; + +/* + * use the scatter file to place GIC Redistributor base address + * + * although this code doesn't know how many Redistributor banks + * a particular system will have, we declare gicrbase as an array + * to avoid unwanted compiler optimisations when calculating the + * base of a particular Redistributor bank + */ +static const GICv3_GICR gicrbase[2] __attribute__((section (".gicr"))); + +/**********************************************************************/ + +/* + * utility functions to calculate base of a particular + * Redistributor bank + */ + +static inline GICv3_redistributor_RD *const getgicrRD(uint32_t gicr) +{ + GICv3_GICR *const arraybase = (GICv3_GICR *const)&gicrbase; + + return &((arraybase + gicr)->RDblock.RD_base); +} + +static inline GICv3_redistributor_SGI *const getgicrSGI(uint32_t gicr) +{ + GICv3_GICR *arraybase = (GICv3_GICR *)(&gicrbase); + + return &(arraybase[gicr].SGIblock.SGI_base); +} + +/**********************************************************************/ + +// This function walks a block of RDs to find one with the matching affinity +uint32_t GetGICR(uint32_t affinity) +{ + GICv3_redistributor_RD* gicr; + uint32_t index = 0; + + do + { + gicr = getgicrRD(index); + if (gicr->GICR_TYPER[1] == affinity) + return index; + + index++; + } + while((gicr->GICR_TYPER[0] & (1<<4)) == 0); // Keep looking until GICR_TYPER.Last reports no more RDs in block + + return 0xFFFFFFFF; // return -1 to signal not RD found +} + +void WakeupGICR(uint32_t gicr) +{ + GICv3_redistributor_RD *const gicrRD = getgicrRD(gicr); +#ifdef USE_GIC600 + //Power up Re-distributor for GIC-600 + gicrRD->GICR_PWRR = 0x2; +#endif + + /* + * step 1 - ensure GICR_WAKER.ProcessorSleep is off + */ + gicrRD->GICR_WAKER &= ~gicrwaker_ProcessorSleep; + + /* + * step 2 - wait for children asleep to be cleared + */ + while ((gicrRD->GICR_WAKER & gicrwaker_ChildrenAsleep) != 0) + continue; + + /* + * OK, GICR is go + */ + return; +} + +void EnablePrivateInt(uint32_t gicr, uint32_t id) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + id &= 0x1f; + + gicrSGI->GICR_ISENABLER = 1 << id; +} + +void DisablePrivateInt(uint32_t gicr, uint32_t id) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + id &= 0x1f; + + gicrSGI->GICR_ICENABLER = 1 << id; +} + +void SetPrivateIntPriority(uint32_t gicr, uint32_t id, uint32_t priority) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + /* + * GICD_IPRIORITYR has one byte-wide entry per interrupt + */ + id &= RANGE_LIMIT(gicrSGI->GICR_IPRIORITYR); + + gicrSGI->GICR_IPRIORITYR[id] = priority; +} + +uint32_t GetPrivateIntPriority(uint32_t gicr, uint32_t id) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + /* + * GICD_IPRIORITYR has one byte-wide entry per interrupt + */ + id &= RANGE_LIMIT(gicrSGI->GICR_IPRIORITYR); + + return (uint32_t)(gicrSGI->GICR_IPRIORITYR[id]); +} + +void SetPrivateIntPending(uint32_t gicr, uint32_t id) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + /* + * GICR_ISPENDR is one 32-bit register + */ + id &= 0x1f; + + gicrSGI->GICR_ISPENDR = 1 << id; +} + +void ClearPrivateIntPending(uint32_t gicr, uint32_t id) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + /* + * GICR_ICPENDR is one 32-bit register + */ + id &= 0x1f; + + gicrSGI->GICR_ICPENDR = 1 << id; +} + +uint32_t GetPrivateIntPending(uint32_t gicr, uint32_t id) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + /* + * GICR_ISPENDR is one 32-bit register + */ + id &= 0x1f; + + return (gicrSGI->GICR_ISPENDR >> id) & 0x01; +} + +void SetPrivateIntSecurity(uint32_t gicr, uint32_t id, GICIGROUPRBits_t group) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + uint32_t groupmod; + + /* + * GICR_IGROUPR0 is one 32-bit register + */ + id &= 0x1f; + + /* + * the single group argument is split into two separate + * registers, so filter out and remove the (new to gicv3) + * group modifier bit + */ + groupmod = (group >> 1) & 1; + group &= 1; + + /* + * either set or clear the Group bit for the interrupt as appropriate + */ + if (group) + gicrSGI->GICR_IGROUPR0 |= 1 << id; + else + gicrSGI->GICR_IGROUPR0 &= ~(1 << id); + + /* + * now deal with groupmod + */ + if (groupmod) + gicrSGI->GICR_IGRPMODR0 |= 1 << id; + else + gicrSGI->GICR_IGRPMODR0 &= ~(1 << id); +} + +void SetPrivateIntSecurityBlock(uint32_t gicr, GICIGROUPRBits_t group) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + const uint32_t nbits = (sizeof group * 8) - 1; + uint32_t groupmod; + + /* + * get each bit of group config duplicated over all 32 bits + */ + groupmod = (uint32_t)(((int32_t)group << (nbits - 1)) >> 31); + group = (uint32_t)(((int32_t)group << nbits) >> 31); + + /* + * set the security state for this block of SPIs + */ + gicrSGI->GICR_IGROUPR0 = group; + gicrSGI->GICR_IGRPMODR0 = groupmod; +} + +/* EOF GICv3_gicr.c */ diff --git a/ports/cortex_a35/gnu/example_build/sample_threadx/MP_Mutexes.S b/ports/cortex_a35/gnu/example_build/sample_threadx/MP_Mutexes.S new file mode 100644 index 00000000..e7f95aa7 --- /dev/null +++ b/ports/cortex_a35/gnu/example_build/sample_threadx/MP_Mutexes.S @@ -0,0 +1,133 @@ +// +// Armv8-A AArch64 - Basic Mutex Example +// Includes the option (USE_LSE_ATOMIC) to use Large System Extension (LSE) atomics introduced in Armv8.1-A +// +// Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// + + + .text + .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + + + .global _mutex_initialize + .global _mutex_acquire + .global _mutex_release + +// +// These routines implement the mutex management functions required for running +// the Arm C library in a multi-threaded environment. +// +// They use a value of 0 to represent an unlocked mutex, and 1 for a locked mutex +// +// ********************************************************************** +// + + .type _mutex_initialize, "function" + .cfi_startproc +_mutex_initialize: + + // + // mark the mutex as unlocked + // + mov w1, #0 + str w1, [x0] + + // + // we are running multi-threaded, so set a non-zero return + // value (function prototype says use 1) + // + mov w0, #1 + ret + .cfi_endproc + +#if !defined(USE_LSE_ATOMIC) + + .type _mutex_acquire, "function" + .cfi_startproc +_mutex_acquire: + + // + // send ourselves an event, so we don't stick on the wfe at the + // top of the loop + // + sevl + + // + // wait until the mutex is available + // +loop: + wfe + ldaxr w1, [x0] + cbnz w1, loop + + // + // mutex is (at least, it was) available - try to claim it + // + mov w1, #1 + stxr w2, w1, [x0] + cbnz w2, loop + + // + // OK, we have the mutex, our work is done here + // + ret + .cfi_endproc + + + .type _mutex_release, "function" + .cfi_startproc +_mutex_release: + + mov w1, #0 + stlr w1, [x0] + ret + .cfi_endproc + +#else // LSE version + + .type _mutex_acquire, "function" + .cfi_startproc +_mutex_acquire: + // This uses a "ticket lock". The lock is stored as a 32-bit value: + // - the upper 16-bits record the thread's ticket number ("take a ticket") + // - the lower 16-bits record the ticket being served ("now serving") + + // atomically load then increment the thread's ticket number ("take a ticket") + mov w3, #(1 << 16) + ldadda w3, w1, [x0] + + // is the ticket now being served? + eor w2, w1, w1, ror #16 + cbz w2, loop_exit + + // no, so wait for the ticket to be served + + // send a local event to avoid missing an unlock before the exclusive load + sevl + +loop: + wfe + ldaxrh w3, [x0] + eor w2, w3, w1, lsr #16 + cbnz w2, loop + + // + // OK, we have the mutex, our work is done here + // +loop_exit: + ret + .cfi_endproc + + + .type _mutex_release, "function" + .cfi_startproc +_mutex_release: + mov w1, #1 + staddlh w1, [x0] + ret + .cfi_endproc +#endif diff --git a/ports/cortex_a35/gnu/example_build/sample_threadx/MP_Mutexes.h b/ports/cortex_a35/gnu/example_build/sample_threadx/MP_Mutexes.h new file mode 100644 index 00000000..ec1a1d28 --- /dev/null +++ b/ports/cortex_a35/gnu/example_build/sample_threadx/MP_Mutexes.h @@ -0,0 +1,66 @@ +/* + * Armv8-A AArch64 - Basic Mutex Example + * + * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. + * Use, modification and redistribution of this file is subject to your possession of a + * valid End User License Agreement for the Arm Product of which these examples are part of + * and your compliance with all applicable terms and conditions of such licence agreement. + */ +#ifndef MP_MUTEX_H +#define MP_MUTEX_H + +/* + * The Arm C library calls-out to these functions to manage multithreading. + * They can also be called by user application code. + * + * Mutex type is specified by the Arm C library + * + * Declare function prototypes for libc mutex routines + */ +typedef signed int *mutex; + +/* + * int _mutex_initialize(mutex *m) + * + * Inputs + * mutex *m - pointer to the 32-bit word associated with the mutex + * + * Returns + * 0 - application is non-threaded + * 1 - application is threaded + * The C library uses the return result to indicate whether it is being used in a multithreaded environment. + */ +int _mutex_initialize(mutex *m); + +/* + * void _mutex_acquire(mutex *m) + * + * Inputs + * mutex *m - pointer to the 32-bit word associated with the mutex + * + * Returns + * + * + * Side Effects + * Routine does not return until the mutex has been claimed. A load-acquire + * is used to guarantee that the mutex claim is properly ordered with + * respect to any accesses to the resource protected by the mutex + */ +void _mutex_acquire(mutex *m); + +/* + * void _mutex_release(mutex *m) + * + * Inputs + * mutex *m - pointer to the 32-bit word associated with the mutex + * + * Returns + * + * + * Side Effects + * A store-release is used to guarantee that the mutex release is properly + * ordered with respect any accesses to the resource protected by the mutex + */ +void _mutex_release(mutex *m); + +#endif diff --git a/ports/cortex_a35/gnu/example_build/sample_threadx/PPM_AEM.h b/ports/cortex_a35/gnu/example_build/sample_threadx/PPM_AEM.h new file mode 100644 index 00000000..52c9a0fe --- /dev/null +++ b/ports/cortex_a35/gnu/example_build/sample_threadx/PPM_AEM.h @@ -0,0 +1,66 @@ +// +// Private Peripheral Map for the v8 Architecture Envelope Model +// +// Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// + +#ifndef PPM_AEM_H +#define PPM_AEM_H + +// +// Distributor layout +// +#define GICD_CTLR 0x0000 +#define GICD_TYPER 0x0004 +#define GICD_IIDR 0x0008 +#define GICD_IGROUP 0x0080 +#define GICD_ISENABLE 0x0100 +#define GICD_ICENABLE 0x0180 +#define GICD_ISPEND 0x0200 +#define GICD_ICPEND 0x0280 +#define GICD_ISACTIVE 0x0300 +#define GICD_ICACTIVE 0x0380 +#define GICD_IPRIORITY 0x0400 +#define GICD_ITARGETS 0x0800 +#define GICD_ICFG 0x0c00 +#define GICD_PPISR 0x0d00 +#define GICD_SPISR 0x0d04 +#define GICD_SGIR 0x0f00 +#define GICD_CPENDSGI 0x0f10 +#define GICD_SPENDSGI 0x0f20 +#define GICD_PIDR4 0x0fd0 +#define GICD_PIDR5 0x0fd4 +#define GICD_PIDR6 0x0fd8 +#define GICD_PIDR7 0x0fdc +#define GICD_PIDR0 0x0fe0 +#define GICD_PIDR1 0x0fe4 +#define GICD_PIDR2 0x0fe8 +#define GICD_PIDR3 0x0fec +#define GICD_CIDR0 0x0ff0 +#define GICD_CIDR1 0x0ff4 +#define GICD_CIDR2 0x0ff8 +#define GICD_CIDR3 0x0ffc + +// +// CPU Interface layout +// +#define GICC_CTLR 0x0000 +#define GICC_PMR 0x0004 +#define GICC_BPR 0x0008 +#define GICC_IAR 0x000c +#define GICC_EOIR 0x0010 +#define GICC_RPR 0x0014 +#define GICC_HPPIR 0x0018 +#define GICC_ABPR 0x001c +#define GICC_AIAR 0x0020 +#define GICC_AEOIR 0x0024 +#define GICC_AHPPIR 0x0028 +#define GICC_APR0 0x00d0 +#define GICC_NSAPR0 0x00e0 +#define GICC_IIDR 0x00fc +#define GICC_DIR 0x1000 + +#endif // PPM_AEM_H diff --git a/ports/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.c new file mode 100644 index 00000000..8898ff39 --- /dev/null +++ b/ports/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.c @@ -0,0 +1,377 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" +#include + +#define DEMO_STACK_SIZE 2048 +#define DEMO_BYTE_POOL_SIZE 64000 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +UCHAR memory_pool[DEMO_BYTE_POOL_SIZE]; + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + +void init_timer(); + +/* Define main entry point. */ + +int main() +{ + + /* Initialize timer for ThreadX. */ + init_timer(); + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +UCHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_pool, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.launch b/ports/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.launch new file mode 100644 index 00000000..12938fd1 --- /dev/null +++ b/ports/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.launch @@ -0,0 +1,328 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.ld b/ports/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.ld new file mode 100644 index 00000000..eec8f12b --- /dev/null +++ b/ports/cortex_a35/gnu/example_build/sample_threadx/sample_threadx.ld @@ -0,0 +1,245 @@ +/* Linker script to place sections and symbol values. + * It references following symbols, which must be defined in code: + * start64 : Entry point + * + * It defines following symbols, which code can use without definition: + * __cs3_peripherals + * __code_start + * __exidx_start + * __exidx_end + * __data_start + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __bss_start__ + * __bss_end__ + * __end__ + * __stack + * __el3_stack + * __ttb0_l1 + * __ttb0_l2_ram + * __ttb0_l2_private + * __ttb0_l2_periph + * __top_of_ram + */ + +ENTRY(start64) + +SECTIONS +{ + /* + * CS3 Peripherals is a 64MB region from 0x1c000000 + * that includes the following: + * System Registers at 0x1C010000 + * UART0 (PL011) at 0x1C090000 + * Color LCD Controller (PL111) at 0x1C1F0000 + * plus a number of others. + * CS3_PERIPHERALS is used by the startup code for page-table generation + * This region is not truly empty, but we have no + * predefined objects that live within it + */ + __cs3_peripherals = 0x1c000000; + + /* + * GICv3 distributor + */ + .gicd 0x2f000000 (NOLOAD): + { + *(.gicd) + } + + /* + * GICv3 redistributors + * 128KB for each redistributor in the system + */ + .gicr 0x2f100000 (NOLOAD): + { + *(.gicr) + } + + .vectors 0x80000000: + { + __code_start = .; + KEEP(*(StartUp)) + KEEP(*(EL1VECTORS EL2VECTORS EL3VECTORS)) + } + + .init : + { + KEEP (*(SORT_NONE(.init))) + } + + .text : + { + *(.text*) + } + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } + + .rodata : + { + *(.rodata .rodata.* .gnu.linkonce.r.*) + } + + .eh_frame : + { + KEEP (*(.eh_frame)) + } + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } + + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array )) + PROVIDE_HIDDEN (__init_array_end = .); + } + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array )) + PROVIDE_HIDDEN (__fini_array_end = .); + } + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } + + .jcr : + { + KEEP (*(.jcr)) + } + + .data : + { + __data_start = . ; + *(.data .data.* .gnu.linkonce.d.*) + SORT(CONSTRUCTORS) + } + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } + + .heap (NOLOAD): + { + . = ALIGN(64); + __end__ = .; + PROVIDE(end = .); + . = . + 0x1000; + } + + .stack (NOLOAD): + { + . = ALIGN(64); + . = . + 8 * 0x4000; + __handler_stack = .; + } + + .stack (NOLOAD): + { + . = ALIGN(64); + . = . + 8 * 0x4000; + __stack = .; + } + + .el3_stack (NOLOAD): + { + . = ALIGN(64); + . = . + 8 * 0x1000; + __el3_stack = .; + } + + .ttb0_l1 (NOLOAD): + { + . = ALIGN(4096); + __ttb0_l1 = .; + . = . + 0x1000; + } + + .ttb0_l2_ram (NOLOAD): + { + . = ALIGN(4096); + __ttb0_l2_ram = .; + . = . + 0x1000; + } + + .ttb0_l2_private (NOLOAD): + { + . = ALIGN(4096); + __ttb0_l2_private = .; + . = . + 0x1000; + } + + .ttb0_l2_periph (NOLOAD): + { + . = ALIGN(4096); + __ttb0_l2_periph = .; + . = . + 0x1000; + } + + /* + * The startup code uses the end of this region to calculate + * the top of memory - don't place any RAM regions after it + */ + __top_of_ram = .; +} diff --git a/ports/cortex_a35/gnu/example_build/sample_threadx/sp804_timer.c b/ports/cortex_a35/gnu/example_build/sample_threadx/sp804_timer.c new file mode 100644 index 00000000..4dc009b2 --- /dev/null +++ b/ports/cortex_a35/gnu/example_build/sample_threadx/sp804_timer.c @@ -0,0 +1,122 @@ +// ------------------------------------------------------------ +// SP804 Dual Timer +// +// Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#include "sp804_timer.h" + +#define TIMER_SP804_CTRL_TIMEREN (1 << 7) +#define TIMER_SP804_CTRL_TIMERMODE (1 << 6) // Bit 6: +#define TIMER_SP804_CTRL_INTENABLE (1 << 5) +#define TIMER_SP804_CTRL_TIMERSIZE (1 << 1) // Bit 1: 0=16-bit, 1=32-bit +#define TIMER_SP804_CTRL_ONESHOT (1 << 0) // Bit 0: 0=wrapping, 1=one-shot + +#define TIMER_SP804_CTRL_PRESCALE_1 (0 << 2) // clk/1 +#define TIMER_SP804_CTRL_PRESCALE_4 (1 << 2) // clk/4 +#define TIMER_SP804_CTRL_PRESCALE_8 (2 << 2) // clk/8 + +struct sp804_timer +{ + volatile uint32_t Time1Load; // +0x00 + const volatile uint32_t Time1Value; // +0x04 - RO + volatile uint32_t Timer1Control; // +0x08 + volatile uint32_t Timer1IntClr; // +0x0C - WO + const volatile uint32_t Timer1RIS; // +0x10 - RO + const volatile uint32_t Timer1MIS; // +0x14 - RO + volatile uint32_t Timer1BGLoad; // +0x18 + + volatile uint32_t Time2Load; // +0x20 + volatile uint32_t Time2Value; // +0x24 + volatile uint8_t Timer2Control; // +0x28 + volatile uint32_t Timer2IntClr; // +0x2C - WO + const volatile uint32_t Timer2RIS; // +0x30 - RO + const volatile uint32_t Timer2MIS; // +0x34 - RO + volatile uint32_t Timer2BGLoad; // +0x38 + + // Not including ID registers + +}; + +// Instance of the dual timer, will be placed using the scatter file +struct sp804_timer* dual_timer; + + +// Set base address of timer +// address - virtual address of SP804 timer +void setTimerBaseAddress(uint64_t address) +{ + dual_timer = (struct sp804_timer*)address; + return; +} + + +// Sets up the private timer +// load_value - Initial value of timer +// auto_reload - Periodic (SP804_AUTORELOAD) or one shot (SP804_SINGLESHOT) +// interrupt - Whether to generate an interrupt +void initTimer(uint32_t load_value, uint32_t auto_reload, uint32_t interrupt) +{ + uint32_t tmp = 0; + + dual_timer->Time1Load = load_value; + + // Fixed setting: 32-bit, no prescaling + tmp = TIMER_SP804_CTRL_TIMERSIZE | TIMER_SP804_CTRL_PRESCALE_1 | TIMER_SP804_CTRL_TIMERMODE; + + // Settings from parameters: interrupt generation & reload + tmp = tmp | interrupt | auto_reload; + + // Write control register + dual_timer->Timer1Control = tmp; + + return; +} + + +// Starts the timer +void startTimer(void) +{ + uint32_t tmp; + + tmp = dual_timer->Timer1Control; + tmp = tmp | TIMER_SP804_CTRL_TIMEREN; // Set TimerEn (bit 7) + dual_timer->Timer1Control = tmp; + + return; +} + + +// Stops the timer +void stopTimer(void) +{ + uint32_t tmp; + + tmp = dual_timer->Timer1Control; + tmp = tmp & ~TIMER_SP804_CTRL_TIMEREN; // Clear TimerEn (bit 7) + dual_timer->Timer1Control = tmp; + + return; +} + + +// Returns the current timer count +uint32_t getTimerCount(void) +{ + return dual_timer->Time1Value; +} + + +void clearTimerIrq(void) +{ + // A write to this register, of any value, clears the interrupt + dual_timer->Timer1IntClr = 1; +} + + +// ------------------------------------------------------------ +// End of sp804_timer.c +// ------------------------------------------------------------ diff --git a/ports/cortex_a35/gnu/example_build/sample_threadx/sp804_timer.h b/ports/cortex_a35/gnu/example_build/sample_threadx/sp804_timer.h new file mode 100644 index 00000000..777062cc --- /dev/null +++ b/ports/cortex_a35/gnu/example_build/sample_threadx/sp804_timer.h @@ -0,0 +1,53 @@ +// ------------------------------------------------------------ +// SP804 Dual Timer +// Header Filer +// +// Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#ifndef _SP804_TIMER_ +#define _SP804_TIMER_ + +#include + +// Set base address of timer +// address - virtual address of SP804 timer +void setTimerBaseAddress(uint64_t address); + + +// Sets up the private timer +// load_value - Initial value of timer +// auto_reload - Periodic (SP804_AUTORELOAD) or one shot (SP804_SINGLESHOT) +// interrupt - Whether to generate an interrupt + +#define SP804_AUTORELOAD (0) +#define SP804_SINGLESHOT (1) +#define SP804_GENERATE_IRQ (1 << 5) +#define SP804_NO_IRQ (0) + +void initTimer(uint32_t load_value, uint32_t auto_reload, uint32_t interrupt); + + +// Starts the timer +void startTimer(void); + + +// Stops the timer +void stopTimer(void); + + +// Returns the current timer count +uint32_t getTimerCount(void); + + +// Clears the timer interrupt +void clearTimerIrq(void); + +#endif + +// ------------------------------------------------------------ +// End of sp804_timer.h +// ------------------------------------------------------------ diff --git a/ports/cortex_a35/gnu/example_build/sample_threadx/startup.S b/ports/cortex_a35/gnu/example_build/sample_threadx/startup.S new file mode 100644 index 00000000..67dd8a6a --- /dev/null +++ b/ports/cortex_a35/gnu/example_build/sample_threadx/startup.S @@ -0,0 +1,787 @@ +// ------------------------------------------------------------ +// Armv8-A MPCore EL3 AArch64 Startup Code +// +// Basic Vectors, MMU, caches and GICv3 initialization +// +// Exits in EL1 AArch64 +// +// Copyright (c) 2014-2019 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#include "v8_mmu.h" +#include "v8_system.h" +#include "GICv3_aliases.h" + + .section StartUp, "ax" + .balign 4 + + + .global el1_vectors + .global el2_vectors + .global el3_vectors + + .global InvalidateUDCaches + .global ZeroBlock + + .global SetPrivateIntSecurityBlock + .global SetSPISecurityAll + .global SetPrivateIntPriority + + .global GetGICR + .global WakeupGICR + .global SyncAREinGICD + .global EnableGICD + .global EnablePrivateInt + .global GetPrivateIntPending + .global ClearPrivateIntPending + + .global _start + .global MainApp + + .global __code_start + .global __ttb0_l1 + .global __ttb0_l2_ram + .global __ttb0_l2_periph + .global __top_of_ram + .global gicd + .global __stack + .global __el3_stack + .global __cs3_peripherals + + + + +// ------------------------------------------------------------ + + .global start64 + .type start64, "function" +start64: + + // + // program the VBARs + // + ldr x1, =el1_vectors + msr VBAR_EL1, x1 + + ldr x1, =el2_vectors + msr VBAR_EL2, x1 + + ldr x1, =el3_vectors + msr VBAR_EL3, x1 + + + // GIC-500 comes out of reset in GICv2 compatibility mode - first set + // system register enables for all relevant exception levels, and + // select GICv3 operating mode + // + msr SCR_EL3, xzr // Ensure NS bit is initially clear, so secure copy of ICC_SRE_EL1 can be configured + isb + + mov x0, #15 + msr ICC_SRE_EL3, x0 + isb + msr ICC_SRE_EL1, x0 // Secure copy of ICC_SRE_EL1 + + // + // set lower exception levels as non-secure, with no access + // back to EL2 or EL3, and are AArch64 capable + // + mov x3, #(SCR_EL3_RW | \ + SCR_EL3_SMD | \ + SCR_EL3_NS) // Set NS bit, to access Non-secure registers + msr SCR_EL3, x3 + isb + + mov x0, #15 + msr ICC_SRE_EL2, x0 + isb + msr ICC_SRE_EL1, x0 // Non-secure copy of ICC_SRE_EL1 + + + // + // no traps or VM modifications from the Hypervisor, EL1 is AArch64 + // + mov x2, #HCR_EL2_RW + msr HCR_EL2, x2 + + // + // VMID is still significant, even when virtualisation is not + // being used, so ensure VTTBR_EL2 is properly initialised + // + msr VTTBR_EL2, xzr + + // + // VMPIDR_EL2 holds the value of the Virtualization Multiprocessor ID. This is the value returned by Non-secure EL1 reads of MPIDR_EL1. + // VPIDR_EL2 holds the value of the Virtualization Processor ID. This is the value returned by Non-secure EL1 reads of MIDR_EL1. + // Both of these registers are architecturally UNKNOWN at reset, and so they must be set to the correct value + // (even if EL2/virtualization is not being used), otherwise non-secure EL1 reads of MPIDR_EL1/MIDR_EL1 will return garbage values. + // This guarantees that any future reads of MPIDR_EL1 and MIDR_EL1 from Non-secure EL1 will return the correct value. + // + mrs x0, MPIDR_EL1 + msr VMPIDR_EL2, x0 + mrs x0, MIDR_EL1 + msr VPIDR_EL2, x0 + + // extract the core number from MPIDR_EL1 and store it in + // x19 (defined by the AAPCS as callee-saved), so we can re-use + // the number later + // + bl GetCPUID + mov x19, x0 + + // + // neither EL3 nor EL2 trap floating point or accesses to CPACR + // + msr CPTR_EL3, xzr + msr CPTR_EL2, xzr + + // + // SCTLR_ELx may come out of reset with UNKNOWN values so we will + // set the fields to 0 except, possibly, the endianess field(s). + // Note that setting SCTLR_EL2 or the EL0 related fields of SCTLR_EL1 + // is not strictly needed, since we're never in EL2 or EL0 + // +#ifdef __ARM_BIG_ENDIAN + mov x0, #(SCTLR_ELx_EE | SCTLR_EL1_E0E) +#else + mov x0, #0 +#endif + msr SCTLR_EL3, x0 + msr SCTLR_EL2, x0 + msr SCTLR_EL1, x0 + +#ifdef CORTEXA + // + // Configure ACTLR_EL[23] + // ---------------------- + // + // These bits are IMPLEMENTATION DEFINED, so are different for + // different processors + // + // For Cortex-A57, the controls we set are: + // + // Enable lower level access to CPUACTLR_EL1 + // Enable lower level access to CPUECTLR_EL1 + // Enable lower level access to L2CTLR_EL1 + // Enable lower level access to L2ECTLR_EL1 + // Enable lower level access to L2ACTLR_EL1 + // + mov x0, #((1 << 0) | \ + (1 << 1) | \ + (1 << 4) | \ + (1 << 5) | \ + (1 << 6)) + + msr ACTLR_EL3, x0 + msr ACTLR_EL2, x0 + + // + // configure CPUECTLR_EL1 + // + // These bits are IMP DEF, so need to different for different + // processors + // + // SMPEN - bit 6 - Enables the processor to receive cache + // and TLB maintenance operations + // + // Note: For Cortex-A57/53 SMPEN should be set before enabling + // the caches and MMU, or performing any cache and TLB + // maintenance operations. + // + // This register has a defined reset value, so we use a + // read-modify-write sequence to set SMPEN + // + mrs x0, S3_1_c15_c2_1 // Read EL1 CPU Extended Control Register + orr x0, x0, #(1 << 6) // Set the SMPEN bit + msr S3_1_c15_c2_1, x0 // Write EL1 CPU Extended Control Register + + isb +#endif + + // + // That's the last of the control settings for now + // + // Note: no ISB after all these changes, as registers won't be + // accessed until after an exception return, which is itself a + // context synchronisation event + // + + // + // Setup some EL3 stack space, ready for calling some subroutines, below. + // + // Stack space allocation is CPU-specific, so use CPU + // number already held in x19 + // + // 2^12 bytes per CPU for the EL3 stacks + // + ldr x0, =__el3_stack + sub x0, x0, x19, lsl #12 + mov sp, x0 + + // + // we need to configure the GIC while still in secure mode, specifically + // all PPIs and SPIs have to be programmed as Group1 interrupts + // + + // + // Before the GIC can be reliably programmed, we need to + // enable Affinity Routing, as this affects where the configuration + // registers are (with Affinity Routing enabled, some registers are + // in the Redistributor, whereas those same registers are in the + // Distributor with Affinity Routing disabled (i.e. when in GICv2 + // compatibility mode). + // + mov x0, #(1 << 4) | (1 << 5) // gicdctlr_ARE_S | gicdctlr_ARE_NS + mov x1, x19 + bl SyncAREinGICD + + // + // The Redistributor comes out of reset assuming the processor is + // asleep - correct that assumption + // + bl GetAffinity + bl GetGICR + mov w20, w0 // Keep a copy for later + bl WakeupGICR + + // + // Now we're ready to set security and other initialisations + // + // This is a per-CPU configuration for these interrupts + // + // for the first cluster, CPU number is the redistributor index + // + mov w0, w20 + mov w1, #1 // gicigroupr_G1NS + bl SetPrivateIntSecurityBlock + + // + // While we're in the Secure World, set the priority mask low enough + // for it to be writable in the Non-Secure World + // + //mov x0, #16 << 3 // 5 bits of priority in the Secure world + mov x0, #0xFF // for Non-Secure interrupts + msr ICC_PMR_EL1, x0 + + // + // there's more GIC setup to do, but only for the primary CPU + // + cbnz x19, drop_to_el1 + + // + // There's more to do to the GIC - call the utility routine to set + // all SPIs to Group1 + // + mov w0, #1 // gicigroupr_G1NS + bl SetSPISecurityAll + + // + // Set up EL1 entry point and "dummy" exception return information, + // then perform exception return to enter EL1 + // + .global drop_to_el1 +drop_to_el1: + adr x1, el1_entry_aarch64 + msr ELR_EL3, x1 + mov x1, #(AARCH64_SPSR_EL1h | \ + AARCH64_SPSR_F | \ + AARCH64_SPSR_I | \ + AARCH64_SPSR_A) + msr SPSR_EL3, x1 + eret + + + +// ------------------------------------------------------------ +// EL1 - Common start-up code +// ------------------------------------------------------------ + + .global el1_entry_aarch64 + .type el1_entry_aarch64, "function" +el1_entry_aarch64: + + // + // Now we're in EL1, setup the application stack + // the scatter file allocates 2^14 bytes per app stack + // + ldr x0, =__handler_stack + sub x0, x0, x19, lsl #14 + mov sp, x0 + MSR SPSel, #0 + ISB + ldr x0, =__stack + sub x0, x0, x19, lsl #14 + mov sp, x0 + + // + // Enable floating point + // + mov x0, #CPACR_EL1_FPEN + msr CPACR_EL1, x0 + + // + // Invalidate caches and TLBs for all stage 1 + // translations used at EL1 + // + // Cortex-A processors automatically invalidate their caches on reset + // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins). + // It is therefore not necessary for software to invalidate the caches + // on startup, however, this is done here in case of a warm reset. + bl InvalidateUDCaches + tlbi VMALLE1 + + + // + // Set TTBR0 Base address + // + // The CPUs share one set of translation tables that are + // generated by CPU0 at run-time + // + // TTBR1_EL1 is not used in this example + // + ldr x1, =__ttb0_l1 + msr TTBR0_EL1, x1 + + + // + // Set up memory attributes + // + // These equate to: + // + // 0 -> 0b01000100 = 0x00000044 = Normal, Inner/Outer Non-Cacheable + // 1 -> 0b11111111 = 0x0000ff00 = Normal, Inner/Outer WriteBack Read/Write Allocate + // 2 -> 0b00000100 = 0x00040000 = Device-nGnRE + // + mov x1, #0xff44 + movk x1, #4, LSL #16 // equiv to: movk x1, #0x0000000000040000 + msr MAIR_EL1, x1 + + + // + // Set up TCR_EL1 + // + // We're using only TTBR0 (EPD1 = 1), and the page table entries: + // - are using an 8-bit ASID from TTBR0 + // - have a 4K granularity (TG0 = 0b00) + // - are outer-shareable (SH0 = 0b10) + // - are using Inner & Outer WBWA Normal memory ([IO]RGN0 = 0b01) + // - map + // + 32 bits of VA space (T0SZ = 0x20) + // + into a 32-bit PA space (IPS = 0b000) + // + // 36 32 28 24 20 16 12 8 4 0 + // -----+----+----+----+----+----+----+----+----+----+ + // | | |OOII| | | |OOII| | | + // TT | | |RRRR|E T | T| |RRRR|E T | T| + // BB | I I|TTSS|GGGG|P 1 | 1|TTSS|GGGG|P 0 | 0| + // IIA| P P|GGHH|NNNN|DAS | S|GGHH|NNNN|D S | S| + // 10S| S-S|1111|1111|11Z-|---Z|0000|0000|0 Z-|---Z| + // + // 000 0000 0000 0000 1000 0000 0010 0101 0010 0000 + // + // 0x 8 0 2 5 2 0 + // + // Note: the ISB is needed to ensure the changes to system + // context are before the write of SCTLR_EL1.M to enable + // the MMU. It is likely on a "real" implementation that + // this setup would work without an ISB, due to the + // amount of code that gets executed before enabling the + // MMU, but that would not be architecturally correct. + // + ldr x1, =0x0000000000802520 + msr TCR_EL1, x1 + isb + + // + // x19 already contains the CPU number, so branch to secondary + // code if we're not on CPU0 + // + cbnz x19, el1_secondary + + // + // Fall through to primary code + // + + +// +// ------------------------------------------------------------ +// +// EL1 - primary CPU init code +// +// This code is run on CPU0, while the other CPUs are in the +// holding pen +// + + .global el1_primary + .type el1_primary, "function" +el1_primary: + + // + // Turn on the banked GIC distributor enable, + // ready for individual CPU enables later + // + mov w0, #(1 << 1) // gicdctlr_EnableGrp1A + bl EnableGICD + + // + // Generate TTBR0 L1 + // + // at 4KB granularity, 32-bit VA space, table lookup starts at + // L1, with 1GB regions + // + // we are going to create entries pointing to L2 tables for a + // couple of these 1GB regions, the first of which is the + // RAM on the VE board model - get the table addresses and + // start by emptying out the L1 page tables (4 entries at L1 + // for a 4K granularity) + // + // x21 = address of L1 tables + // + ldr x21, =__ttb0_l1 + mov x0, x21 + mov x1, #(4 << 3) + bl ZeroBlock + + // + // time to start mapping the RAM regions - clear out the + // L2 tables and point to them from the L1 tables + // + // x22 = address of L2 tables, needs to be remembered in case + // we want to re-use the tables for mapping peripherals + // + ldr x22, =__ttb0_l2_ram + mov x1, #(512 << 3) + mov x0, x22 + bl ZeroBlock + + // + // Get the start address of RAM (the EXEC region) into x4 + // and calculate the offset into the L1 table (1GB per region, + // max 4GB) + // + // x23 = L1 table offset, saved for later comparison against + // peripheral offset + // + ldr x4, =__code_start + ubfx x23, x4, #30, #2 + + orr x1, x22, #TT_S1_ATTR_PAGE + str x1, [x21, x23, lsl #3] + + // + // we've already used the RAM start address in x4 - we now need + // to get this in terms of an offset into the L2 page tables, + // where each entry covers 2MB + // + ubfx x2, x4, #21, #9 + + // + // TOP_OF_RAM in the scatter file marks the end of the + // Execute region in RAM: convert the end of this region to an + // offset too, being careful to round up, then calculate the + // number of entries to write + // + ldr x5, =__top_of_ram + sub x3, x5, #1 + ubfx x3, x3, #21, #9 + add x3, x3, #1 + sub x3, x3, x2 + + // + // set x1 to the required page table attributes, then orr + // in the start address (modulo 2MB) + // + // L2 tables in our configuration cover 2MB per entry - map + // memory as Shared, Normal WBWA (MAIR[1]) with a flat + // VA->PA translation + // + bic x4, x4, #((1 << 21) - 1) + ldr x1, =(TT_S1_ATTR_BLOCK | \ + (1 << TT_S1_ATTR_MATTR_LSB) | \ + TT_S1_ATTR_NS | \ + TT_S1_ATTR_AP_RW_PL1 | \ + TT_S1_ATTR_SH_INNER | \ + TT_S1_ATTR_AF | \ + TT_S1_ATTR_nG) + orr x1, x1, x4 + + // + // factor the offset into the page table address and then write + // the entries + // + add x0, x22, x2, lsl #3 + +loop1: + subs x3, x3, #1 + str x1, [x0], #8 + add x1, x1, #0x200, LSL #12 // equiv to add x1, x1, #(1 << 21) // 2MB per entry + bne loop1 + + + // + // now mapping the Peripheral regions - clear out the + // L2 tables and point to them from the L1 tables + // + // The assumption here is that all peripherals live within + // a common 1GB region (i.e. that there's a single set of + // L2 pages for all the peripherals). We only use a UART + // and the GIC in this example, so the assumption is sound + // + // x24 = address of L2 peripheral tables + // + ldr x24, =__ttb0_l2_periph + + // + // get the GICD address into x4 and calculate + // the offset into the L1 table + // + // x25 = L1 table offset + // + ldr x4, =gicd + ubfx x25, x4, #30, #2 + + // + // here's the tricky bit: it's possible that the peripherals are + // in the same 1GB region as the RAM, in which case we don't need + // to prime a separate set of L2 page tables, nor add them to the + // L1 tables + // + // if we're going to re-use the TTB0_L2_RAM tables, get their + // address into x24, which is used later on to write the PTEs + // + cmp x25, x23 + csel x24, x22, x24, EQ + b.eq nol2setup + + // + // Peripherals are in a separate 1GB region, and so have their own + // set of L2 tables - clean out the tables and add them to the L1 + // table + // + mov x0, x24 + mov x1, #512 << 3 + bl ZeroBlock + + orr x1, x24, #TT_S1_ATTR_PAGE + str x1, [x21, x25, lsl #3] + + // + // there's only going to be a single 2MB region for GICD (in + // x4) - get this in terms of an offset into the L2 page tables + // + // with larger systems, it is possible that the GIC redistributor + // registers require extra 2MB pages, in which case extra code + // would be required here + // +nol2setup: + ubfx x2, x4, #21, #9 + + // + // set x1 to the required page table attributes, then orr + // in the start address (modulo 2MB) + // + // L2 tables in our configuration cover 2MB per entry - map + // memory as NS Device-nGnRE (MAIR[2]) with a flat VA->PA + // translation + // + bic x4, x4, #((1 << 21) - 1) // start address mod 2MB + ldr x1, =(TT_S1_ATTR_BLOCK | \ + (2 << TT_S1_ATTR_MATTR_LSB) | \ + TT_S1_ATTR_NS | \ + TT_S1_ATTR_AP_RW_PL1 | \ + TT_S1_ATTR_AF | \ + TT_S1_ATTR_nG) + orr x1, x1, x4 + + // + // only a single L2 entry for this, so no loop as we have for RAM, above + // + str x1, [x24, x2, lsl #3] + + // + // we have CS3_PERIPHERALS that include the UART controller + // + // Again, the code is making assumptions - this time that the CS3_PERIPHERALS + // region uses the same 1GB portion of the address space as the GICD, + // and thus shares the same set of L2 page tables + // + // Get CS3_PERIPHERALS address into x4 and calculate the offset into the + // L2 tables + // + ldr x4, =__cs3_peripherals + ubfx x2, x4, #21, #9 + + // + // set x1 to the required page table attributes, then orr + // in the start address (modulo 2MB) + // + // L2 tables in our configuration cover 2MB per entry - map + // memory as NS Device-nGnRE (MAIR[2]) with a flat VA->PA + // translation + // + bic x4, x4, #((1 << 21) - 1) // start address mod 2MB + ldr x1, =(TT_S1_ATTR_BLOCK | \ + (2 << TT_S1_ATTR_MATTR_LSB) | \ + TT_S1_ATTR_NS | \ + TT_S1_ATTR_AP_RW_PL1 | \ + TT_S1_ATTR_AF | \ + TT_S1_ATTR_nG) + orr x1, x1, x4 + + // + // only a single L2 entry again - write it + // + str x1, [x24, x2, lsl #3] + + // + // issue a barrier to ensure all table entry writes are complete + // + dsb ish + + // + // Enable the MMU. Caches will be enabled later, after scatterloading. + // + mrs x1, SCTLR_EL1 + orr x1, x1, #SCTLR_ELx_M + bic x1, x1, #SCTLR_ELx_A // Disable alignment fault checking. To enable, change bic to orr + msr SCTLR_EL1, x1 + isb + + // + // The Arm Architecture Reference Manual for Armv8-A states: + // + // Instruction accesses to Non-cacheable Normal memory can be held in instruction caches. + // Correspondingly, the sequence for ensuring that modifications to instructions are available + // for execution must include invalidation of the modified locations from the instruction cache, + // even if the instructions are held in Normal Non-cacheable memory. + // This includes cases where the instruction cache is disabled. + // + + dsb ish // ensure all previous stores have completed before invalidating + ic ialluis // I cache invalidate all inner shareable to PoU (which includes secondary cores) + dsb ish // ensure completion on inner shareable domain (which includes secondary cores) + isb + + // Scatter-loading is complete, so enable the caches here, so that the C-library's mutex initialization later will work + mrs x1, SCTLR_EL1 + orr x1, x1, #SCTLR_ELx_C + orr x1, x1, #SCTLR_ELx_I + msr SCTLR_EL1, x1 + isb + + // Zero the bss + ldr x0, =__bss_start__ // Start of block + mov x1, #0 // Fill value + ldr x2, =__bss_end__ // End of block + sub x2, x2, x0 // Length of block + bl memset + + // Set up the standard file handles + bl initialise_monitor_handles + + // Set up _fini and fini_array to be called at exit + ldr x0, =__libc_fini_array + bl atexit + + // Call preinit_array, _init and init_array + bl __libc_init_array + + // Set argc = 1, argv[0] = "" and then call main + .pushsection .data + .align 3 +argv: + .dword arg0 + .dword 0 +arg0: + .byte 0 + .popsection + + mov x0, #1 + ldr x1, =argv + bl main + + b exit // Will not return + +// ------------------------------------------------------------ +// EL1 - secondary CPU init code +// +// This code is run on CPUs 1, 2, 3 etc.... +// ------------------------------------------------------------ + + .global el1_secondary + .type el1_secondary, "function" +el1_secondary: + + // + // the primary CPU is going to use SGI 15 as a wakeup event + // to let us know when it is OK to proceed, so prepare for + // receiving that interrupt + // + // NS interrupt priorities run from 0 to 15, with 15 being + // too low a priority to ever raise an interrupt, so let's + // use 14 + // + mov w0, w20 + mov w1, #15 + mov w2, #14 << 4 // we're in NS world, so 4 bits of priority, + // 8-bit field, - 4 = 4-bit shift + bl SetPrivateIntPriority + + mov w0, w20 + mov w1, #15 + bl EnablePrivateInt + + // + // set priority mask as low as possible; although,being in the + // NS World, we can't set bit[7] of the priority, we still + // write all 8-bits of priority to an ICC register + // + mov x0, #31 << 3 + msr ICC_PMR_EL1, x0 + + // + // set global enable and wait for our interrupt to arrive + // + mov x0, #1 + msr ICC_IGRPEN1_EL1, x0 + isb + +loop_wfi: + dsb SY // Clear all pending data accesses + wfi // Go to sleep + + // + // something woke us from our wait, was it the required interrupt? + // + mov w0, w20 + mov w1, #15 + bl GetPrivateIntPending + cbz w0, loop_wfi + + // + // it was - there's no need to actually take the interrupt, + // so just clear it + // + mov w0, w20 + mov w1, #15 + bl ClearPrivateIntPending + + // + // Enable the MMU and caches + // + mrs x1, SCTLR_EL1 + orr x1, x1, #SCTLR_ELx_M + orr x1, x1, #SCTLR_ELx_C + orr x1, x1, #SCTLR_ELx_I + bic x1, x1, #SCTLR_ELx_A // Disable alignment fault checking. To enable, change bic to orr + msr SCTLR_EL1, x1 + isb + + // + // Branch to thread start + // + //B MainApp + diff --git a/ports/cortex_a35/gnu/example_build/sample_threadx/timer_interrupts.c b/ports/cortex_a35/gnu/example_build/sample_threadx/timer_interrupts.c new file mode 100644 index 00000000..8f522217 --- /dev/null +++ b/ports/cortex_a35/gnu/example_build/sample_threadx/timer_interrupts.c @@ -0,0 +1,152 @@ +/* Bare-metal example for Armv8-A FVP Base model */ + +/* Timer and interrupts */ + +/* Copyright (c) 2016-2018 Arm Limited (or its affiliates). All rights reserved. */ +/* Use, modification and redistribution of this file is subject to your possession of a */ +/* valid End User License Agreement for the Arm Product of which these examples are part of */ +/* and your compliance with all applicable terms and conditions of such licence agreement. */ + +#include + +#include "GICv3.h" +#include "GICv3_gicc.h" +#include "sp804_timer.h" + +void _tx_timer_interrupt(void); + +// LED Base address +#define LED_BASE (volatile unsigned int *)0x1C010008 + + +void nudge_leds(void) // Move LEDs along +{ + static int state = 1; + static int value = 1; + + if (state) + { + int max = (1 << 7); + value <<= 1; + if (value == max) + state = 0; + } + else + { + value >>= 1; + if (value == 1) + state = 1; + } + + *LED_BASE = value; // Update LEDs hardware +} + + +// Initialize Timer 0 and Interrupt Controller +void init_timer(void) +{ + // Enable interrupts + __asm("MSR DAIFClr, #0xF"); + setICC_IGRPEN1_EL1(igrpEnable); + + // Configure the SP804 timer to generate an interrupt + setTimerBaseAddress(0x1C110000); + initTimer(0x200, SP804_AUTORELOAD, SP804_GENERATE_IRQ); + startTimer(); + + // The SP804 timer generates SPI INTID 34. Enable + // this ID, and route it to core 0.0.0.0 (this one!) + SetSPIRoute(34, 0, gicdirouter_ModeSpecific); // Route INTID 34 to 0.0.0.0 (this core) + SetSPIPriority(34, 0); // Set INTID 34 to priority to 0 + ConfigureSPI(34, gicdicfgr_Level); // Set INTID 34 as level-sensitive + EnableSPI(34); // Enable INTID 34 +} + + +// -------------------------------------------------------- + +void irqHandler(void) +{ + unsigned int ID; + + ID = getICC_IAR1(); // readIntAck(); + + // Check for reserved IDs + if ((1020 <= ID) && (ID <= 1023)) + { + //printf("irqHandler() - Reserved INTID %d\n\n", ID); + return; + } + + switch(ID) + { + case 34: + // Dual-Timer 0 (SP804) + //printf("irqHandler() - External timer interrupt\n\n"); + nudge_leds(); + clearTimerIrq(); + + /* Call ThreadX timer interrupt processing. */ + _tx_timer_interrupt(); + + break; + + default: + // Unexpected ID value + //printf("irqHandler() - Unexpected INTID %d\n\n", ID); + break; + } + + // Write the End of Interrupt register to tell the GIC + // we've finished handling the interrupt + setICC_EOIR1(ID); // writeAliasedEOI(ID); +} + +// -------------------------------------------------------- + +// Not actually used in this example, but provided for completeness + +void fiqHandler(void) +{ + unsigned int ID; + unsigned int aliased = 0; + + ID = getICC_IAR0(); // readIntAck(); + //printf("fiqHandler() - Read %d from IAR0\n", ID); + + // Check for reserved IDs + if ((1020 <= ID) && (ID <= 1023)) + { + //printf("fiqHandler() - Reserved INTID %d\n\n", ID); + ID = getICC_IAR1(); // readAliasedIntAck(); + //printf("fiqHandler() - Read %d from AIAR\n", ID); + aliased = 1; + + // If still spurious then simply return + if ((1020 <= ID) && (ID <= 1023)) + return; + } + + switch(ID) + { + case 34: + // Dual-Timer 0 (SP804) + //printf("fiqHandler() - External timer interrupt\n\n"); + clearTimerIrq(); + break; + + default: + // Unexpected ID value + //printf("fiqHandler() - Unexpected INTID %d\n\n", ID); + break; + } + + // Write the End of Interrupt register to tell the GIC + // we've finished handling the interrupt + // NOTE: If the ID was read from the Aliased IAR, then + // the aliased EOI register must be used + if (aliased == 0) + setICC_EOIR0(ID); // writeEOI(ID); + else + setICC_EOIR1(ID); // writeAliasedEOI(ID); +} diff --git a/ports/cortex_a35/gnu/example_build/sample_threadx/use_model_semihosting.ds b/ports/cortex_a35/gnu/example_build/sample_threadx/use_model_semihosting.ds new file mode 100644 index 00000000..6fde52b2 --- /dev/null +++ b/ports/cortex_a35/gnu/example_build/sample_threadx/use_model_semihosting.ds @@ -0,0 +1 @@ +set semihosting enabled off diff --git a/ports/cortex_a35/gnu/example_build/sample_threadx/v8_aarch64.S b/ports/cortex_a35/gnu/example_build/sample_threadx/v8_aarch64.S new file mode 100644 index 00000000..f8db3bfe --- /dev/null +++ b/ports/cortex_a35/gnu/example_build/sample_threadx/v8_aarch64.S @@ -0,0 +1,179 @@ +// ------------------------------------------------------------ +// Armv8-A AArch64 - Common helper functions +// +// Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#include "v8_system.h" + + .text + .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + + .global EnableCachesEL1 + .global DisableCachesEL1 + .global InvalidateUDCaches + .global GetMIDR + .global GetMPIDR + .global GetAffinity + .global GetCPUID + +// ------------------------------------------------------------ + +// +// void EnableCachesEL1(void) +// +// enable Instruction and Data caches +// + .type EnableCachesEL1, "function" + .cfi_startproc +EnableCachesEL1: + + mrs x0, SCTLR_EL1 + orr x0, x0, #SCTLR_ELx_I + orr x0, x0, #SCTLR_ELx_C + msr SCTLR_EL1, x0 + + isb + ret + .cfi_endproc + + +// ------------------------------------------------------------ + + .type DisableCachesEL1, "function" + .cfi_startproc +DisableCachesEL1: + + mrs x0, SCTLR_EL1 + bic x0, x0, #SCTLR_ELx_I + bic x0, x0, #SCTLR_ELx_C + msr SCTLR_EL1, x0 + + isb + ret + .cfi_endproc + + +// ------------------------------------------------------------ + +// +// void InvalidateUDCaches(void) +// +// Invalidate data and unified caches +// + .type InvalidateUDCaches, "function" + .cfi_startproc +InvalidateUDCaches: + // From the Armv8-A Architecture Reference Manual + + dmb ish // ensure all prior inner-shareable accesses have been observed + + mrs x0, CLIDR_EL1 + and w3, w0, #0x07000000 // get 2 x level of coherence + lsr w3, w3, #23 + cbz w3, finished + mov w10, #0 // w10 = 2 x cache level + mov w8, #1 // w8 = constant 0b1 +loop_level: + add w2, w10, w10, lsr #1 // calculate 3 x cache level + lsr w1, w0, w2 // extract 3-bit cache type for this level + and w1, w1, #0x7 + cmp w1, #2 + b.lt next_level // no data or unified cache at this level + msr CSSELR_EL1, x10 // select this cache level + isb // synchronize change of csselr + mrs x1, CCSIDR_EL1 // read ccsidr + and w2, w1, #7 // w2 = log2(linelen)-4 + add w2, w2, #4 // w2 = log2(linelen) + ubfx w4, w1, #3, #10 // w4 = max way number, right aligned + clz w5, w4 // w5 = 32-log2(ways), bit position of way in dc operand + lsl w9, w4, w5 // w9 = max way number, aligned to position in dc operand + lsl w16, w8, w5 // w16 = amount to decrement way number per iteration +loop_way: + ubfx w7, w1, #13, #15 // w7 = max set number, right aligned + lsl w7, w7, w2 // w7 = max set number, aligned to position in dc operand + lsl w17, w8, w2 // w17 = amount to decrement set number per iteration +loop_set: + orr w11, w10, w9 // w11 = combine way number and cache number ... + orr w11, w11, w7 // ... and set number for dc operand + dc isw, x11 // do data cache invalidate by set and way + subs w7, w7, w17 // decrement set number + b.ge loop_set + subs x9, x9, x16 // decrement way number + b.ge loop_way +next_level: + add w10, w10, #2 // increment 2 x cache level + cmp w3, w10 + b.gt loop_level + dsb sy // ensure completion of previous cache maintenance operation + isb +finished: + ret + .cfi_endproc + + +// ------------------------------------------------------------ + +// +// ID Register functions +// + + .type GetMIDR, "function" + .cfi_startproc +GetMIDR: + + mrs x0, MIDR_EL1 + ret + .cfi_endproc + + + .type GetMPIDR, "function" + .cfi_startproc +GetMPIDR: + + mrs x0, MPIDR_EL1 + ret + .cfi_endproc + + + .type GetAffinity, "function" + .cfi_startproc +GetAffinity: + + mrs x0, MPIDR_EL1 + ubfx x1, x0, #32, #8 + bfi w0, w1, #24, #8 + ret + .cfi_endproc + + + .type GetCPUID, "function" + .cfi_startproc +GetCPUID: + + mrs x0, MIDR_EL1 + ubfx x0, x0, #4, #12 // extract PartNum + cmp x0, #0xD0D // Cortex-A77 + b.eq DynamIQ + cmp x0, #0xD0B // Cortex-A76 + b.eq DynamIQ + cmp x0, #0xD0A // Cortex-A75 + b.eq DynamIQ + cmp x0, #0xD05 // Cortex-A55 + b.eq DynamIQ + b Others +DynamIQ: + mrs x0, MPIDR_EL1 + ubfx x0, x0, #MPIDR_EL1_AFF1_LSB, #MPIDR_EL1_AFF_WIDTH + ret + +Others: + mrs x0, MPIDR_EL1 + ubfx x1, x0, #MPIDR_EL1_AFF0_LSB, #MPIDR_EL1_AFF_WIDTH + ubfx x2, x0, #MPIDR_EL1_AFF1_LSB, #MPIDR_EL1_AFF_WIDTH + add x0, x1, x2, LSL #2 + ret + .cfi_endproc diff --git a/ports/cortex_a35/gnu/example_build/sample_threadx/v8_aarch64.h b/ports/cortex_a35/gnu/example_build/sample_threadx/v8_aarch64.h new file mode 100644 index 00000000..b09079a4 --- /dev/null +++ b/ports/cortex_a35/gnu/example_build/sample_threadx/v8_aarch64.h @@ -0,0 +1,103 @@ +/* + * + * Armv8-A AArch64 common helper functions + * + * Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved. + * Use, modification and redistribution of this file is subject to your possession of a + * valid End User License Agreement for the Arm Product of which these examples are part of + * and your compliance with all applicable terms and conditions of such licence agreement. + */ + +#ifndef V8_AARCH64_H +#define V8_AARCH64_H + +/* + * Parameters for data barriers + */ +#define OSHLD 1 +#define OSHST 2 +#define OSH 3 +#define NSHLD 5 +#define NSHST 6 +#define NSH 7 +#define ISHLD 9 +#define ISHST 10 +#define ISH 11 +#define LD 13 +#define ST 14 +#define SY 15 + +/**********************************************************************/ + +/* + * function prototypes + */ + +/* + * void InvalidateUDCaches(void) + * invalidates all Unified and Data Caches + * + * Inputs + * + * + * Returns + * + * + * Side Effects + * guarantees that all levels of cache will be invalidated before + * returning to caller + */ +void InvalidateUDCaches(void); + +/* + * unsigned long long EnableCachesEL1(void) + * enables I- and D- caches at EL1 + * + * Inputs + * + * + * Returns + * New value of SCTLR_EL1 + * + * Side Effects + * context will be synchronised before returning to caller + */ +unsigned long long EnableCachesEL1(void); + +/* + * unsigned long long GetMIDR(void) + * returns the contents of MIDR_EL0 + * + * Inputs + * + * + * Returns + * MIDR_EL0 + */ +unsigned long long GetMIDR(void); + +/* + * unsigned long long GetMPIDR(void) + * returns the contents of MPIDR_EL0 + * + * Inputs + * + * + * Returns + * MPIDR_EL0 + */ +unsigned long long GetMPIDR(void); + +/* + * unsigned int GetCPUID(void) + * returns the Aff0 field of MPIDR_EL0 + * + * Inputs + * + * + * Returns + * MPIDR_EL0[7:0] + */ +unsigned int GetCPUID(void); + +#endif diff --git a/ports/cortex_a35/gnu/example_build/sample_threadx/v8_mmu.h b/ports/cortex_a35/gnu/example_build/sample_threadx/v8_mmu.h new file mode 100644 index 00000000..ee8834fa --- /dev/null +++ b/ports/cortex_a35/gnu/example_build/sample_threadx/v8_mmu.h @@ -0,0 +1,128 @@ +// +// Defines for v8 Memory Model +// +// Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// + +#ifndef V8_MMU_H +#define V8_MMU_H + +// +// Translation Control Register fields +// +// RGN field encodings +// +#define TCR_RGN_NC 0b00 +#define TCR_RGN_WBWA 0b01 +#define TCR_RGN_WT 0b10 +#define TCR_RGN_WBRA 0b11 + +// +// Shareability encodings +// +#define TCR_SHARE_NONE 0b00 +#define TCR_SHARE_OUTER 0b10 +#define TCR_SHARE_INNER 0b11 + +// +// Granule size encodings +// +#define TCR_GRANULE_4K 0b00 +#define TCR_GRANULE_64K 0b01 +#define TCR_GRANULE_16K 0b10 + +// +// Physical Address sizes +// +#define TCR_SIZE_4G 0b000 +#define TCR_SIZE_64G 0b001 +#define TCR_SIZE_1T 0b010 +#define TCR_SIZE_4T 0b011 +#define TCR_SIZE_16T 0b100 +#define TCR_SIZE_256T 0b101 + +// +// Translation Control Register fields +// +#define TCR_EL1_T0SZ_SHIFT 0 +#define TCR_EL1_EPD0 (1 << 7) +#define TCR_EL1_IRGN0_SHIFT 8 +#define TCR_EL1_ORGN0_SHIFT 10 +#define TCR_EL1_SH0_SHIFT 12 +#define TCR_EL1_TG0_SHIFT 14 + +#define TCR_EL1_T1SZ_SHIFT 16 +#define TCR_EL1_A1 (1 << 22) +#define TCR_EL1_EPD1 (1 << 23) +#define TCR_EL1_IRGN1_SHIFT 24 +#define TCR_EL1_ORGN1_SHIFT 26 +#define TCR_EL1_SH1_SHIFT 28 +#define TCR_EL1_TG1_SHIFT 30 +#define TCR_EL1_IPS_SHIFT 32 +#define TCR_EL1_AS (1 << 36) +#define TCR_EL1_TBI0 (1 << 37) +#define TCR_EL1_TBI1 (1 << 38) + +// +// Stage 1 Translation Table descriptor fields +// +#define TT_S1_ATTR_FAULT (0b00 << 0) +#define TT_S1_ATTR_BLOCK (0b01 << 0) // Level 1/2 +#define TT_S1_ATTR_TABLE (0b11 << 0) // Level 0/1/2 +#define TT_S1_ATTR_PAGE (0b11 << 0) // Level 3 + +#define TT_S1_ATTR_MATTR_LSB 2 + +#define TT_S1_ATTR_NS (1 << 5) + +#define TT_S1_ATTR_AP_RW_PL1 (0b00 << 6) +#define TT_S1_ATTR_AP_RW_ANY (0b01 << 6) +#define TT_S1_ATTR_AP_RO_PL1 (0b10 << 6) +#define TT_S1_ATTR_AP_RO_ANY (0b11 << 6) + +#define TT_S1_ATTR_SH_NONE (0b00 << 8) +#define TT_S1_ATTR_SH_OUTER (0b10 << 8) +#define TT_S1_ATTR_SH_INNER (0b11 << 8) + +#define TT_S1_ATTR_AF (1 << 10) +#define TT_S1_ATTR_nG (1 << 11) + +// OA bits [15:12] - If Armv8.2-LPA is implemented, bits[15:12] are bits[51:48] +// and bits[47:16] are bits[47:16] of the output address for a page of memory + +#define TT_S1_ATTR_nT (1 << 16) // Present if Armv8.4-TTRem is implemented, otherwise RES0 + +#define TT_S1_ATTR_DBM (1 << 51) // Present if Armv8.1-TTHM is implemented, otherwise RES0 + +#define TT_S1_ATTR_CONTIG (1 << 52) +#define TT_S1_ATTR_PXN (1 << 53) +#define TT_S1_ATTR_UXN (1 << 54) + +// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits +// for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED + +#define TT_S1_MAIR_DEV_nGnRnE 0b00000000 +#define TT_S1_MAIR_DEV_nGnRE 0b00000100 +#define TT_S1_MAIR_DEV_nGRE 0b00001000 +#define TT_S1_MAIR_DEV_GRE 0b00001100 + +// +// Inner and Outer Normal memory attributes use the same bit patterns +// Outer attributes just need to be shifted up +// +#define TT_S1_MAIR_OUTER_SHIFT 4 + +#define TT_S1_MAIR_WT_TRANS_RA 0b0010 + +#define TT_S1_MAIR_WB_TRANS_RA 0b0110 +#define TT_S1_MAIR_WB_TRANS_RWA 0b0111 + +#define TT_S1_MAIR_WT_RA 0b1010 + +#define TT_S1_MAIR_WB_RA 0b1110 +#define TT_S1_MAIR_WB_RWA 0b1111 + +#endif // V8_MMU_H diff --git a/ports/cortex_a35/gnu/example_build/sample_threadx/v8_system.h b/ports/cortex_a35/gnu/example_build/sample_threadx/v8_system.h new file mode 100644 index 00000000..ff96deff --- /dev/null +++ b/ports/cortex_a35/gnu/example_build/sample_threadx/v8_system.h @@ -0,0 +1,115 @@ +// +// Defines for v8 System Registers +// +// Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// + +#ifndef V8_SYSTEM_H +#define V8_SYSTEM_H + +// +// AArch64 SPSR +// +#define AARCH64_SPSR_EL3h 0b1101 +#define AARCH64_SPSR_EL3t 0b1100 +#define AARCH64_SPSR_EL2h 0b1001 +#define AARCH64_SPSR_EL2t 0b1000 +#define AARCH64_SPSR_EL1h 0b0101 +#define AARCH64_SPSR_EL1t 0b0100 +#define AARCH64_SPSR_EL0t 0b0000 +#define AARCH64_SPSR_RW (1 << 4) +#define AARCH64_SPSR_F (1 << 6) +#define AARCH64_SPSR_I (1 << 7) +#define AARCH64_SPSR_A (1 << 8) +#define AARCH64_SPSR_D (1 << 9) +#define AARCH64_SPSR_IL (1 << 20) +#define AARCH64_SPSR_SS (1 << 21) +#define AARCH64_SPSR_V (1 << 28) +#define AARCH64_SPSR_C (1 << 29) +#define AARCH64_SPSR_Z (1 << 30) +#define AARCH64_SPSR_N (1 << 31) + +// +// Multiprocessor Affinity Register +// +#define MPIDR_EL1_AFF3_LSB 32 +#define MPIDR_EL1_U (1 << 30) +#define MPIDR_EL1_MT (1 << 24) +#define MPIDR_EL1_AFF2_LSB 16 +#define MPIDR_EL1_AFF1_LSB 8 +#define MPIDR_EL1_AFF0_LSB 0 +#define MPIDR_EL1_AFF_WIDTH 8 + +// +// Data Cache Zero ID Register +// +#define DCZID_EL0_BS_LSB 0 +#define DCZID_EL0_BS_WIDTH 4 +#define DCZID_EL0_DZP_LSB 5 +#define DCZID_EL0_DZP (1 << 5) + +// +// System Control Register +// +#define SCTLR_EL1_UCI (1 << 26) +#define SCTLR_ELx_EE (1 << 25) +#define SCTLR_EL1_E0E (1 << 24) +#define SCTLR_ELx_WXN (1 << 19) +#define SCTLR_EL1_nTWE (1 << 18) +#define SCTLR_EL1_nTWI (1 << 16) +#define SCTLR_EL1_UCT (1 << 15) +#define SCTLR_EL1_DZE (1 << 14) +#define SCTLR_ELx_I (1 << 12) +#define SCTLR_EL1_UMA (1 << 9) +#define SCTLR_EL1_SED (1 << 8) +#define SCTLR_EL1_ITD (1 << 7) +#define SCTLR_EL1_THEE (1 << 6) +#define SCTLR_EL1_CP15BEN (1 << 5) +#define SCTLR_EL1_SA0 (1 << 4) +#define SCTLR_ELx_SA (1 << 3) +#define SCTLR_ELx_C (1 << 2) +#define SCTLR_ELx_A (1 << 1) +#define SCTLR_ELx_M (1 << 0) + +// +// Architectural Feature Access Control Register +// +#define CPACR_EL1_TTA (1 << 28) +#define CPACR_EL1_FPEN (3 << 20) + +// +// Architectural Feature Trap Register +// +#define CPTR_ELx_TCPAC (1 << 31) +#define CPTR_ELx_TTA (1 << 20) +#define CPTR_ELx_TFP (1 << 10) + +// +// Secure Configuration Register +// +#define SCR_EL3_TWE (1 << 13) +#define SCR_EL3_TWI (1 << 12) +#define SCR_EL3_ST (1 << 11) +#define SCR_EL3_RW (1 << 10) +#define SCR_EL3_SIF (1 << 9) +#define SCR_EL3_HCE (1 << 8) +#define SCR_EL3_SMD (1 << 7) +#define SCR_EL3_EA (1 << 3) +#define SCR_EL3_FIQ (1 << 2) +#define SCR_EL3_IRQ (1 << 1) +#define SCR_EL3_NS (1 << 0) + +// +// Hypervisor Configuration Register +// +#define HCR_EL2_ID (1 << 33) +#define HCR_EL2_CD (1 << 32) +#define HCR_EL2_RW (1 << 31) +#define HCR_EL2_TRVM (1 << 30) +#define HCR_EL2_HVC (1 << 29) +#define HCR_EL2_TDZ (1 << 28) + +#endif // V8_SYSTEM_H diff --git a/ports/cortex_a35/gnu/example_build/sample_threadx/v8_utils.S b/ports/cortex_a35/gnu/example_build/sample_threadx/v8_utils.S new file mode 100644 index 00000000..f0fcef26 --- /dev/null +++ b/ports/cortex_a35/gnu/example_build/sample_threadx/v8_utils.S @@ -0,0 +1,69 @@ +// +// Simple utility routines for baremetal v8 code +// +// Copyright (c) 2013-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// + +#include "v8_system.h" + + .text + .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + +// +// void *ZeroBlock(void *blockPtr, unsigned int nBytes) +// +// Zero fill a block of memory +// Fill memory pages or similar structures with zeros. +// The byte count must be a multiple of the block fill size (16 bytes) +// +// Inputs: +// blockPtr - base address of block to fill +// nBytes - block size, in bytes +// +// Returns: +// pointer to just filled block, NULL if nBytes is +// incompatible with block fill size +// + .global ZeroBlock + .type ZeroBlock, "function" + .cfi_startproc +ZeroBlock: + + // + // we fill data by steam, 16 bytes at a time: check that + // blocksize is a multiple of that + // + ubfx x2, x1, #0, #4 + cbnz x2, incompatible + + // + // we already have one register full of zeros, get another + // + mov x3, x2 + + // + // OK, set temporary pointer and away we go + // + add x0, x0, x1 + +loop0: + subs x1, x1, #16 + stp x2, x3, [x0, #-16]! + b.ne loop0 + + // + // that's all - x0 will be back to its start value + // + ret + + // + // parameters are incompatible with block size - return + // an indication that this is so + // +incompatible: + mov x0,#0 + ret + .cfi_endproc diff --git a/ports/cortex_a35/gnu/example_build/sample_threadx/vectors.S b/ports/cortex_a35/gnu/example_build/sample_threadx/vectors.S new file mode 100644 index 00000000..9e60e001 --- /dev/null +++ b/ports/cortex_a35/gnu/example_build/sample_threadx/vectors.S @@ -0,0 +1,252 @@ +// ------------------------------------------------------------ +// Armv8-A Vector tables +// +// Copyright (c) 2014-2016 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + + + .global el1_vectors + .global el2_vectors + .global el3_vectors + .global c0sync1 + .global irqHandler + .global fiqHandler + .global irqFirstLevelHandler + .global fiqFirstLevelHandler + + .section EL1VECTORS, "ax" + .align 11 + +// +// Current EL with SP0 +// +el1_vectors: +c0sync1: B c0sync1 + + .balign 0x80 +c0irq1: B irqFirstLevelHandler + + .balign 0x80 +c0fiq1: B fiqFirstLevelHandler + + .balign 0x80 +c0serr1: B c0serr1 + +// +// Current EL with SPx +// + .balign 0x80 +cxsync1: B cxsync1 + + .balign 0x80 +cxirq1: B irqFirstLevelHandler + + .balign 0x80 +cxfiq1: B fiqFirstLevelHandler + + .balign 0x80 +cxserr1: B cxserr1 + +// +// Lower EL using AArch64 +// + .balign 0x80 +l64sync1: B l64sync1 + + .balign 0x80 +l64irq1: B irqFirstLevelHandler + + .balign 0x80 +l64fiq1: B fiqFirstLevelHandler + + .balign 0x80 +l64serr1: B l64serr1 + +// +// Lower EL using AArch32 +// + .balign 0x80 +l32sync1: B l32sync1 + + .balign 0x80 +l32irq1: B irqFirstLevelHandler + + .balign 0x80 +l32fiq1: B fiqFirstLevelHandler + + .balign 0x80 +l32serr1: B l32serr1 + +//---------------------------------------------------------------- + + .section EL2VECTORS, "ax" + .align 11 + +// +// Current EL with SP0 +// +el2_vectors: +c0sync2: B c0sync2 + + .balign 0x80 +c0irq2: B irqFirstLevelHandler + + .balign 0x80 +c0fiq2: B fiqFirstLevelHandler + + .balign 0x80 +c0serr2: B c0serr2 + +// +// Current EL with SPx +// + .balign 0x80 +cxsync2: B cxsync2 + + .balign 0x80 +cxirq2: B irqFirstLevelHandler + + .balign 0x80 +cxfiq2: B fiqFirstLevelHandler + + .balign 0x80 +cxserr2: B cxserr2 + +// +// Lower EL using AArch64 +// + .balign 0x80 +l64sync2: B l64sync2 + + .balign 0x80 +l64irq2: B irqFirstLevelHandler + + .balign 0x80 +l64fiq2: B fiqFirstLevelHandler + + .balign 0x80 +l64serr2: B l64serr2 + +// +// Lower EL using AArch32 +// + .balign 0x80 +l32sync2: B l32sync2 + + .balign 0x80 +l32irq2: B irqFirstLevelHandler + + .balign 0x80 +l32fiq2: B fiqFirstLevelHandler + + .balign 0x80 +l32serr2: B l32serr2 + +//---------------------------------------------------------------- + + .section EL3VECTORS, "ax" + .align 11 + +// +// Current EL with SP0 +// +el3_vectors: +c0sync3: B c0sync3 + + .balign 0x80 +c0irq3: B irqFirstLevelHandler + + .balign 0x80 +c0fiq3: B fiqFirstLevelHandler + + .balign 0x80 +c0serr3: B c0serr3 + +// +// Current EL with SPx +// + .balign 0x80 +cxsync3: B cxsync3 + + .balign 0x80 +cxirq3: B irqFirstLevelHandler + + .balign 0x80 +cxfiq3: B fiqFirstLevelHandler + + .balign 0x80 +cxserr3: B cxserr3 + +// +// Lower EL using AArch64 +// + .balign 0x80 +l64sync3: B l64sync3 + + .balign 0x80 +l64irq3: B irqFirstLevelHandler + + .balign 0x80 +l64fiq3: B fiqFirstLevelHandler + + .balign 0x80 +l64serr3: B l64serr3 + +// +// Lower EL using AArch32 +// + .balign 0x80 +l32sync3: B l32sync3 + + .balign 0x80 +l32irq3: B irqFirstLevelHandler + + .balign 0x80 +l32fiq3: B fiqFirstLevelHandler + + .balign 0x80 +l32serr3: B l32serr3 + + + .section InterruptHandlers, "ax" + .balign 4 + + .type irqFirstLevelHandler, "function" +irqFirstLevelHandler: + MSR SPSel, 0 + STP x29, x30, [sp, #-16]! + BL _tx_thread_context_save + BL irqHandler + B _tx_thread_context_restore + + .type fiqFirstLevelHandler, "function" +fiqFirstLevelHandler: + STP x29, x30, [sp, #-16]! + STP x18, x19, [sp, #-16]! + STP x16, x17, [sp, #-16]! + STP x14, x15, [sp, #-16]! + STP x12, x13, [sp, #-16]! + STP x10, x11, [sp, #-16]! + STP x8, x9, [sp, #-16]! + STP x6, x7, [sp, #-16]! + STP x4, x5, [sp, #-16]! + STP x2, x3, [sp, #-16]! + STP x0, x1, [sp, #-16]! + + BL fiqHandler + + LDP x0, x1, [sp], #16 + LDP x2, x3, [sp], #16 + LDP x4, x5, [sp], #16 + LDP x6, x7, [sp], #16 + LDP x8, x9, [sp], #16 + LDP x10, x11, [sp], #16 + LDP x12, x13, [sp], #16 + LDP x14, x15, [sp], #16 + LDP x16, x17, [sp], #16 + LDP x18, x19, [sp], #16 + LDP x29, x30, [sp], #16 + ERET diff --git a/ports/cortex_a35/gnu/example_build/tx/.cproject b/ports/cortex_a35/gnu/example_build/tx/.cproject new file mode 100644 index 00000000..01370489 --- /dev/null +++ b/ports/cortex_a35/gnu/example_build/tx/.cproject @@ -0,0 +1,234 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_a35/gnu/example_build/tx/.project b/ports/cortex_a35/gnu/example_build/tx/.project new file mode 100644 index 00000000..863ca5cb --- /dev/null +++ b/ports/cortex_a35/gnu/example_build/tx/.project @@ -0,0 +1,48 @@ + + + tx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + inc_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/inc + + + inc_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/inc + + + src_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/src + + + src_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/src + + + diff --git a/ports/cortex_a35/gnu/example_build/tx/.settings/language.settings.xml b/ports/cortex_a35/gnu/example_build/tx/.settings/language.settings.xml new file mode 100644 index 00000000..754cc5fb --- /dev/null +++ b/ports/cortex_a35/gnu/example_build/tx/.settings/language.settings.xml @@ -0,0 +1,4616 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_a35/gnu/inc/tx_port.h b/ports/cortex_a35/gnu/inc/tx_port.h new file mode 100644 index 00000000..ca8a1149 --- /dev/null +++ b/ports/cortex_a35/gnu/inc/tx_port.h @@ -0,0 +1,367 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A35/GNU */ +/* 6.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef int LONG; +typedef unsigned int ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Override the alignment type to use 64-bit alignment and storage for pointers. */ + +#define ALIGN_TYPE_DEFINED +typedef unsigned long long ALIGN_TYPE; + + +/* Override the free block marker for byte pools to be a 64-bit constant. */ + +#define TX_BYTE_BLOCK_FREE ((ALIGN_TYPE) 0xFFFFEEEEFFFFEEEE) + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 4096 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#define TX_INT_ENABLE 0x00 /* Enable IRQ & FIQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_fp_enable; +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) b = (UINT) __builtin_ctz((unsigned int) m); + +#endif + + +/* Define the internal timer extension to also hold the thread pointer such that _tx_thread_timeout + can figure out what thread timeout to process. */ + +#define TX_TIMER_INTERNAL_EXTENSION VOID *tx_timer_internal_thread_timeout_ptr; + + +/* Define the thread timeout setup logic in _tx_thread_create. */ + +#define TX_THREAD_CREATE_TIMEOUT_SETUP(t) (t) -> tx_thread_timer.tx_timer_internal_timeout_function = &(_tx_thread_timeout); \ + (t) -> tx_thread_timer.tx_timer_internal_timeout_param = 0; \ + (t) -> tx_thread_timer.tx_timer_internal_thread_timeout_ptr = (VOID *) (t); + + +/* Define the thread timeout pointer setup in _tx_thread_timeout. */ + +#define TX_THREAD_TIMEOUT_POINTER_SETUP(t) (t) = (TX_THREAD *) _tx_timer_expired_timer_ptr -> tx_timer_internal_thread_timeout_ptr; + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifndef TX_DISABLE_INLINE + +/* Define macros, with in-line assembly for performance. */ + +__attribute__( ( always_inline ) ) static inline unsigned int __disable_interrupts(void) +{ + +unsigned long long daif_value; + + __asm__ volatile (" MRS %0, DAIF ": "=r" (daif_value) ); + __asm__ volatile (" MSR DAIFSet, 0x3" : : : "memory" ); + return((unsigned int) daif_value); +} + +__attribute__( ( always_inline ) ) static inline void __restore_interrupts(unsigned int daif_value) +{ + +unsigned long long temp; + + temp = (unsigned long long) daif_value; + __asm__ volatile (" MSR DAIF,%0": : "r" (temp): "memory" ); +} + + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_DISABLE interrupt_save = __disable_interrupts(); +#define TX_RESTORE __restore_interrupts(interrupt_save); + +#else + +unsigned int _tx_thread_interrupt_disable(void); +unsigned int _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); +#endif + + +/* Define FP extension for the Cortex-A5x. Each is assumed to be called in the context of the executing + thread. */ + +#ifndef TX_SOURCE_CODE +#define tx_thread_fp_enable _tx_thread_fp_enable +#define tx_thread_fp_disable _tx_thread_fp_disable +#endif + +VOID tx_thread_fp_enable(VOID); +VOID tx_thread_fp_disable(VOID); + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A35/GNU Version 6.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + + + + diff --git a/ports/cortex_a35/gnu/readme_threadx.txt b/ports/cortex_a35/gnu/readme_threadx.txt new file mode 100644 index 00000000..5b2a3ef8 --- /dev/null +++ b/ports/cortex_a35/gnu/readme_threadx.txt @@ -0,0 +1,253 @@ + Microsoft's Azure RTOS ThreadX for Cortex-A35 + + Using the ARM GNU Compiler & DS + +1. Import the ThreadX Projects + +In order to build the ThreadX library and the ThreadX SMP demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +into your DS workspace. + + +2. Building the ThreadX run-time Library + +Building the ThreadX library is easy; simply select the Eclipse project file +"tx" and then select the build button. You should now observe the compilation +and assembly of the ThreadX library. This project build produces the ThreadX +library file tx.a. + + +3. Demonstration System + +The ThreadX demonstration is designed to execute under the DS debugger on the +Base_A35x1 Bare Metal simulator. + +Building the demonstration is easy; simply select the sample_threadx project, and +select the build button. Next, in the sample_threadx project, right-click on the +sample_threadx.launch file and select 'Debug As -> sample_threadx'. The debugger is +setup for the Cortex-A35 FVP, so selecting "Debug" will launch the FVP, load +the sample_threadx.axf ELF file and run to the entry point. You are now ready to execute +the ThreadX SMP demonstration. + + +4. System Initialization + +The entry point in ThreadX for the Cortex-A35 using GCC tools is at label +"start64". This is defined within the GCC compiler's startup code. In addition, +this is where all static and global pre-set C variable initialization processing +takes place. + +The ThreadX tx_initialize_low_level.s file is responsible for determining the +first available RAM address for use by the application, which is supplied as the +sole input parameter to your application definition function, tx_application_define. + + +5. Register Usage and Stack Frames + +The 64-bit GCC compiler assumes that registers x0-x18 are scratch registers +for each function. All other registers used by a C function must be preserved +by the function. ThreadX takes advantage of this in situations where a context +switch happens as a result of making a ThreadX service call (which is itself a +C function). In such cases, the saved context of a thread is only the +non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + +FP not enabled and TX_THREAD.tx_thread_fp_enable == 0: + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x000 SPSR DAIF + 0x008 ELR 0 + 0x010 x28 x27 + 0x018 reserved x28 + 0x020 x26 x25 + 0x028 x27 x26 + 0x030 x24 x23 + 0x038 x25 x24 + 0x040 x22 x21 + 0x048 x23 x22 + 0x050 x20 x19 + 0x058 x21 x20 + 0x060 x18 x29 + 0x068 x19 x30 + 0x070 x16 + 0x078 x17 + 0x080 x14 + 0x088 x15 + 0x090 x12 + 0x098 x13 + 0x0A0 x10 + 0x0A8 x11 + 0x0B0 x8 + 0x0B8 x9 + 0x0C0 x6 + 0x0C8 x7 + 0x0D0 x4 + 0x0D8 x5 + 0x0E0 x2 + 0x0E8 x3 + 0x0F0 x0 + 0x0F8 x1 + 0x100 x29 + 0x108 x30 + + +FP enabled and TX_THREAD.tx_thread_fp_enable == 1: + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x000 SPSR DAIF + 0x008 ELR 0 + 0x010 FPSR FPSR + 0x018 FPCR FPCR + 0x020 q30 q14 + 0x030 q31 q15 + 0x040 q28 q12 + 0x050 q29 q13 + 0x060 q26 q10 + 0x070 q27 q11 + 0x080 q24 q8 + 0x090 q25 q9 + 0x0A0 q22 x27 + 0x0A8 x28 + 0x0B0 q23 x25 + 0x0B8 x26 + 0x0C0 q20 x23 + 0x0C8 x24 + 0x0D0 q21 x21 + 0x0D8 x22 + 0x0E0 q18 x19 + 0x0E8 x20 + 0x0F0 q19 x29 + 0x0F8 x30 + 0x100 q16 + 0x110 q17 + 0x120 q14 + 0x130 q15 + 0x140 q12 + 0x150 q13 + 0x160 q10 + 0x170 q11 + 0x180 q8 + 0x190 q9 + 0x1A0 q6 + 0x1B0 q7 + 0x1C0 q4 + 0x1D0 q5 + 0x1E0 q2 + 0x1F0 q3 + 0x200 q0 + 0x210 q1 + 0x220 x28 + 0x228 reserved + 0x230 x26 + 0x238 x27 + 0x240 x24 + 0x248 x25 + 0x250 x22 + 0x258 x23 + 0x260 x20 + 0x268 x21 + 0x270 x18 + 0x278 x19 + 0x280 x16 + 0x288 x17 + 0x290 x14 + 0x298 x15 + 0x2A0 x12 + 0x2A8 x13 + 0x2B0 x10 + 0x2B8 x11 + 0x2C0 x8 + 0x2C8 x9 + 0x2D0 x6 + 0x2D8 x7 + 0x2E0 x4 + 0x2E8 x5 + 0x2F0 x2 + 0x2F8 x3 + 0x300 x0 + 0x308 x1 + 0x310 x29 + 0x318 x30 + + + +6. Improving Performance + +The distribution version of ThreadX is built without any compiler optimizations. +This makes it easy to debug because you can trace or set breakpoints inside of +ThreadX itself. Of course, this costs some performance. To make it run faster, +you can change the project settings to the desired compiler optimization level. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-A35 +targets. Interrupts handlers for the 64-bit mode of the Cortex-A35 have the following +format: + + .global irq_handler +irq_handler: + MSR SPSel, 0 + STP x29, x30, [sp, #-16]! + BL _tx_thread_context_save + + /* Your ISR call goes here! */ + BL application_isr_handler + + B _tx_thread_context_restore + +By default, ThreadX assumes EL3 level of execution. Running and taking exceptions in EL1 +and EL2 can be done by simply building the ThreadX library with either EL1 or EL2 defined. + + +8. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, thread sleeps, +timeouts, and application timers. Without such a timer interrupt source, these services +are not functional. However, all other ThreadX services are operational without a +periodic timer source. + + +9. ARM FP Support + +By default, FP support is disabled for each thread. If saving the context of the FP registers +is needed, the following API call must be made from the context of the application thread - before +the FP usage: + +void tx_thread_fp_enable(void); + +After this API is called in the application, FP registers will be saved/restored for this thread if it +is preempted via an interrupt. All other suspension of the this thread will not require the FP registers +to be saved/restored. + +To disable FP register context saving, simply call the following API: + +void tx_thread_fp_disable(void); + + +10. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +09-30-2020 Initial ThreadX 6.1 version for Cortex-A35 using GCC tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_a35/gnu/src/tx_initialize_low_level.S b/ports/cortex_a35/gnu/src/tx_initialize_low_level.S new file mode 100644 index 00000000..6dca4867 --- /dev/null +++ b/ports/cortex_a35/gnu/src/tx_initialize_low_level.S @@ -0,0 +1,108 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-A35/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_initialize_low_level(VOID) +{ */ + .global _tx_initialize_low_level + .type _tx_initialize_low_level, @function +_tx_initialize_low_level: + + MSR DAIFSet, 0x3 // Lockout interrupts + + + /* Save the system stack pointer. */ + /* _tx_thread_system_stack_ptr = (VOID_PTR) (sp); */ + + LDR x0, =_tx_thread_system_stack_ptr // Pickup address of system stack ptr + MOV x1, sp // Pickup SP + BIC x1, x1, #0xF // Get 16-bit alignment + STR x1, [x0] // Store system stack + + /* Save the first available memory address. */ + /* _tx_initialize_unused_memory = (VOID_PTR) Image$$ZI$$Limit; */ + + LDR x0, =_tx_initialize_unused_memory // Pickup address of unused memory ptr + LDR x1, =__top_of_ram // Pickup unused memory address + LDR x1, [x1] // + STR x1, [x0] // Store unused memory address + + /* Done, return to caller. */ + + RET // Return to caller +/* } */ + diff --git a/ports/cortex_a35/gnu/src/tx_thread_context_restore.S b/ports/cortex_a35/gnu/src/tx_thread_context_restore.S new file mode 100644 index 00000000..06ed7e41 --- /dev/null +++ b/ports/cortex_a35/gnu/src/tx_thread_context_restore.S @@ -0,0 +1,302 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + +/* .set ENABLE_ARM_FP,1 */ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore Cortex-A35/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores the interrupt context if it is processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_restore(VOID) +{ */ + .global _tx_thread_context_restore + .type _tx_thread_context_restore, @function +_tx_thread_context_restore: + + /* Lockout interrupts. */ + + MSR DAIFSet, 0x3 // Lockout interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR exit function to indicate an ISR is complete. */ + + BL _tx_execution_isr_exit // Call the ISR exit function +#endif + + /* Determine if interrupts are nested. */ + /* if (--_tx_thread_system_state) + { */ + + LDR x3, =_tx_thread_system_state // Pickup address of system state var + LDR w2, [x3, #0] // Pickup system state + SUB w2, w2, #1 // Decrement the counter + STR w2, [x3, #0] // Store the counter + CMP w2, #0 // Was this the first interrupt? + BEQ __tx_thread_not_nested_restore // If so, not a nested restore + + /* Interrupts are nested. */ + + /* Just recover the saved registers and return to the point of + interrupt. */ + + LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL +#ifdef EL1 + MSR SPSR_EL1, x4 // Setup SPSR for return + MSR ELR_EL1, x5 // Setup point of interrupt +#else +#ifdef EL2 + MSR SPSR_EL2, x4 // Setup SPSR for return + MSR ELR_EL2, x5 // Setup point of interrupt +#else + MSR SPSR_EL3, x4 // Setup SPSR for return + MSR ELR_EL3, x5 // Setup point of interrupt +#endif +#endif + LDP x18, x19, [sp], #16 // Recover x18, x19 + LDP x16, x17, [sp], #16 // Recover x16, x17 + LDP x14, x15, [sp], #16 // Recover x14, x15 + LDP x12, x13, [sp], #16 // Recover x12, x13 + LDP x10, x11, [sp], #16 // Recover x10, x11 + LDP x8, x9, [sp], #16 // Recover x8, x9 + LDP x6, x7, [sp], #16 // Recover x6, x7 + LDP x4, x5, [sp], #16 // Recover x4, x5 + LDP x2, x3, [sp], #16 // Recover x2, x3 + LDP x0, x1, [sp], #16 // Recover x0, x1 + LDP x29, x30, [sp], #16 // Recover x29, x30 + ERET // Return to point of interrupt + + /* } */ +__tx_thread_not_nested_restore: + + /* Determine if a thread was interrupted and no preemption is required. */ + /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) + || (_tx_thread_preempt_disable)) + { */ + + LDR x1, =_tx_thread_current_ptr // Pickup address of current thread ptr + LDR x0, [x1, #0] // Pickup actual current thread pointer + CMP x0, #0 // Is it NULL? + BEQ __tx_thread_idle_system_restore // Yes, idle system was interrupted + + LDR x3, =_tx_thread_preempt_disable // Pickup preempt disable address + LDR w2, [x3, #0] // Pickup actual preempt disable flag + CMP w2, #0 // Is it set? + BNE __tx_thread_no_preempt_restore // Yes, don't preempt this thread + LDR x3, =_tx_thread_execute_ptr // Pickup address of execute thread ptr + LDR x2, [x3, #0] // Pickup actual execute thread pointer + CMP x0, x2 // Is the same thread highest priority? + BNE __tx_thread_preempt_restore // No, preemption needs to happen + + +__tx_thread_no_preempt_restore: + + /* Restore interrupted thread or ISR. */ + + /* Pickup the saved stack pointer. */ + /* sp = _tx_thread_current_ptr -> tx_thread_stack_ptr; */ + + LDR x4, [x0, #8] // Switch to thread stack pointer + MOV sp, x4 // + + /* Recover the saved context and return to the point of interrupt. */ + + LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL1 +#ifdef EL1 + MSR SPSR_EL1, x4 // Setup SPSR for return + MSR ELR_EL1, x5 // Setup point of interrupt +#else +#ifdef EL2 + MSR SPSR_EL2, x4 // Setup SPSR for return + MSR ELR_EL2, x5 // Setup point of interrupt +#else + MSR SPSR_EL3, x4 // Setup SPSR for return + MSR ELR_EL3, x5 // Setup point of interrupt +#endif +#endif + LDP x18, x19, [sp], #16 // Recover x18, x19 + LDP x16, x17, [sp], #16 // Recover x16, x17 + LDP x14, x15, [sp], #16 // Recover x14, x15 + LDP x12, x13, [sp], #16 // Recover x12, x13 + LDP x10, x11, [sp], #16 // Recover x10, x11 + LDP x8, x9, [sp], #16 // Recover x8, x9 + LDP x6, x7, [sp], #16 // Recover x6, x7 + LDP x4, x5, [sp], #16 // Recover x4, x5 + LDP x2, x3, [sp], #16 // Recover x2, x3 + LDP x0, x1, [sp], #16 // Recover x0, x1 + LDP x29, x30, [sp], #16 // Recover x29, x30 + ERET // Return to point of interrupt + + /* } + else + { */ +__tx_thread_preempt_restore: + + LDR x4, [x0, #8] // Switch to thread stack pointer + MOV sp, x4 // + + LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL1 + STP x20, x21, [sp, #-16]! // Save x20, x21 + STP x22, x23, [sp, #-16]! // Save x22, x23 + STP x24, x25, [sp, #-16]! // Save x24, x25 + STP x26, x27, [sp, #-16]! // Save x26, x27 + STP x28, x29, [sp, #-16]! // Save x28, x29 +#ifdef ENABLE_ARM_FP + LDR w3, [x0, #248] // Pickup FP enable flag + CMP w3, #0 // Is FP enabled? + BEQ _skip_fp_save // No, skip FP save + STP q0, q1, [sp, #-32]! // Save q0, q1 + STP q2, q3, [sp, #-32]! // Save q2, q3 + STP q4, q5, [sp, #-32]! // Save q4, q5 + STP q6, q7, [sp, #-32]! // Save q6, q7 + STP q8, q9, [sp, #-32]! // Save q8, q9 + STP q10, q11, [sp, #-32]! // Save q10, q11 + STP q12, q13, [sp, #-32]! // Save q12, q13 + STP q14, q15, [sp, #-32]! // Save q14, q15 + STP q16, q17, [sp, #-32]! // Save q16, q17 + STP q18, q19, [sp, #-32]! // Save q18, q19 + STP q20, q21, [sp, #-32]! // Save q20, q21 + STP q22, q23, [sp, #-32]! // Save q22, q23 + STP q24, q25, [sp, #-32]! // Save q24, q25 + STP q26, q27, [sp, #-32]! // Save q26, q27 + STP q28, q29, [sp, #-32]! // Save q28, q29 + STP q30, q31, [sp, #-32]! // Save q30, q31 + MRS x2, FPSR // Pickup FPSR + MRS x3, FPCR // Pickup FPCR + STP x2, x3, [sp, #-16]! // Save FPSR, FPCR +_skip_fp_save: +#endif + STP x4, x5, [sp, #-16]! // Save x4 (SPSR_EL3), x5 (ELR_E3) + + MOV x3, sp // Move sp into x3 + STR x3, [x0, #8] // Save stack pointer in thread control + // block + LDR x3, =_tx_thread_system_stack_ptr // Pickup address of system stack + LDR x4, [x3, #0] // Pickup system stack pointer + MOV sp, x4 // Setup system stack pointer + + + /* Save the remaining time-slice and disable it. */ + /* if (_tx_timer_time_slice) + { */ + + LDR x3, =_tx_timer_time_slice // Pickup time-slice variable address + LDR w2, [x3, #0] // Pickup time-slice + CMP w2, #0 // Is it active? + BEQ __tx_thread_dont_save_ts // No, don't save it + + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + STR w2, [x0, #36] // Save thread's time-slice + MOV w2, #0 // Clear value + STR w2, [x3, #0] // Disable global time-slice flag + + /* } */ +__tx_thread_dont_save_ts: + + + /* Clear the current task pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + MOV x0, #0 // NULL value + STR x0, [x1, #0] // Clear current thread pointer + + /* Return to the scheduler. */ + /* _tx_thread_schedule(); */ + + /* } */ + +__tx_thread_idle_system_restore: + + /* Just return back to the scheduler! */ + + LDR x1, =_tx_thread_schedule // Build address for _tx_thread_schedule +#ifdef EL1 + MSR ELR_EL1, x1 // Setup point of interrupt +// MOV x1, #0x4 // Setup EL1 return +// MSR spsr_el1, x1 // Move into SPSR +#else +#ifdef EL2 + MSR ELR_EL2, x1 // Setup point of interrupt +// MOV x1, #0x8 // Setup EL2 return +// MSR spsr_el2, x1 // Move into SPSR +#else + MSR ELR_EL3, x1 // Setup point of interrupt +// MOV x1, #0xC // Setup EL3 return +// MSR spsr_el3, x1 // Move into SPSR +#endif +#endif + ERET // Return to scheduler +/* } */ + + diff --git a/ports/cortex_a35/gnu/src/tx_thread_context_save.S b/ports/cortex_a35/gnu/src/tx_thread_context_save.S new file mode 100644 index 00000000..f8749f74 --- /dev/null +++ b/ports/cortex_a35/gnu/src/tx_thread_context_save.S @@ -0,0 +1,228 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save Cortex-A35/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_save(VOID) +{ */ + .global _tx_thread_context_save + .type _tx_thread_context_save, @function +_tx_thread_context_save: + + /* Upon entry to this routine, it is assumed that IRQ/FIQ interrupts are locked + out, x29 (frame pointer), x30 (link register) are saved, we are in EL1, + and all other registers are intact. */ + + /* Check for a nested interrupt condition. */ + /* if (_tx_thread_system_state++) + { */ + + STP x0, x1, [sp, #-16]! // Save x0, x1 + STP x2, x3, [sp, #-16]! // Save x2, x3 + LDR x3, =_tx_thread_system_state // Pickup address of system state var + LDR w2, [x3, #0] // Pickup system state + CMP w2, #0 // Is this the first interrupt? + BEQ __tx_thread_not_nested_save // Yes, not a nested context save + + /* Nested interrupt condition. */ + + ADD w2, w2, #1 // Increment the nested interrupt counter + STR w2, [x3, #0] // Store it back in the variable + + /* Save the rest of the scratch registers on the stack and return to the + calling ISR. */ + + STP x4, x5, [sp, #-16]! // Save x4, x5 + STP x6, x7, [sp, #-16]! // Save x6, x7 + STP x8, x9, [sp, #-16]! // Save x8, x9 + STP x10, x11, [sp, #-16]! // Save x10, x11 + STP x12, x13, [sp, #-16]! // Save x12, x13 + STP x14, x15, [sp, #-16]! // Save x14, x15 + STP x16, x17, [sp, #-16]! // Save x16, x17 + STP x18, x19, [sp, #-16]! // Save x18, x19 +#ifdef EL1 + MRS x0, SPSR_EL1 // Pickup SPSR + MRS x1, ELR_EL1 // Pickup ELR (point of interrupt) +#else +#ifdef EL2 + MRS x0, SPSR_EL2 // Pickup SPSR + MRS x1, ELR_EL2 // Pickup ELR (point of interrupt) +#else + MRS x0, SPSR_EL3 // Pickup SPSR + MRS x1, ELR_EL3 // Pickup ELR (point of interrupt) +#endif +#endif + STP x0, x1, [sp, #-16]! // Save SPSR, ELR + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + STP x29, x30, [sp, #-16]! // Save x29, x30 + BL _tx_execution_isr_enter // Call the ISR enter function + LDP x29, x30, [sp], #16 // Recover x29, x30 +#endif + + /* Return to the ISR. */ + + RET // Return to ISR + +__tx_thread_not_nested_save: + /* } */ + + /* Otherwise, not nested, check to see if a thread was running. */ + /* else if (_tx_thread_current_ptr) + { */ + + ADD w2, w2, #1 // Increment the interrupt counter + STR w2, [x3, #0] // Store it back in the variable + LDR x1, =_tx_thread_current_ptr // Pickup address of current thread ptr + LDR x0, [x1, #0] // Pickup current thread pointer + CMP x0, #0 // Is it NULL? + BEQ __tx_thread_idle_system_save // If so, interrupt occurred in + // scheduling loop - nothing needs saving! + + /* Save minimal context of interrupted thread. */ + + STP x4, x5, [sp, #-16]! // Save x4, x5 + STP x6, x7, [sp, #-16]! // Save x6, x7 + STP x8, x9, [sp, #-16]! // Save x8, x9 + STP x10, x11, [sp, #-16]! // Save x10, x11 + STP x12, x13, [sp, #-16]! // Save x12, x13 + STP x14, x15, [sp, #-16]! // Save x14, x15 + STP x16, x17, [sp, #-16]! // Save x16, x17 + STP x18, x19, [sp, #-16]! // Save x18, x19 +#ifdef EL1 + MRS x4, SPSR_EL1 // Pickup SPSR + MRS x5, ELR_EL1 // Pickup ELR (point of interrupt) +#else +#ifdef EL2 + MRS x4, SPSR_EL2 // Pickup SPSR + MRS x5, ELR_EL2 // Pickup ELR (point of interrupt) +#else + MRS x4, SPSR_EL3 // Pickup SPSR + MRS x5, ELR_EL3 // Pickup ELR (point of interrupt) +#endif +#endif + STP x4, x5, [sp, #-16]! // Save SPSR, ELR + + /* Save the current stack pointer in the thread's control block. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ + + MOV x4, sp // + STR x4, [x0, #8] // Save thread stack pointer + + /* Switch to the system stack. */ + /* sp = _tx_thread_system_stack_ptr; */ + + LDR x3, =_tx_thread_system_stack_ptr // Pickup address of system stack + LDR x4, [x3, #0] // Pickup system stack pointer + MOV sp, x4 // Setup system stack pointer + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + STP x29, x30, [sp, #-16]! // Save x29, x30 + BL _tx_execution_isr_enter // Call the ISR enter function + LDP x29, x30, [sp], #16 // Recover x29, x30 +#endif + + RET // Return to caller + + /* } + else + { */ + +__tx_thread_idle_system_save: + + /* Interrupt occurred in the scheduling loop. */ + + /* Not much to do here, just adjust the stack pointer, and return to IRQ + processing. */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + STP x29, x30, [sp, #-16]! // Save x29, x30 + BL _tx_execution_isr_enter // Call the ISR enter function + LDP x29, x30, [sp], #16 // Recover x29, x30 +#endif + + ADD sp, sp, #48 // Recover saved registers + RET // Continue IRQ processing + + /* } +} */ + + diff --git a/ports/cortex_a35/gnu/src/tx_thread_fp_disable.c b/ports/cortex_a35/gnu/src/tx_thread_fp_disable.c new file mode 100644 index 00000000..0f59986e --- /dev/null +++ b/ports/cortex_a35/gnu/src/tx_thread_fp_disable.c @@ -0,0 +1,95 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fp_disable Cortex-A35/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function disables the FP for the currently executing thread. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_fp_disable(VOID) +{ + +TX_THREAD *thread_ptr; +ULONG system_state; + + + /* Pickup the current thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr); + + /* Get the system state. */ + system_state = TX_THREAD_GET_SYSTEM_STATE(); + + /* Make sure it is not NULL. */ + if (thread_ptr != TX_NULL) + { + + /* Thread is running... make sure the call is from the thread context. */ + if (system_state == 0) + { + + /* Yes, now set the FP enable flag to false in the TX_THREAD structure. */ + thread_ptr -> tx_thread_fp_enable = TX_FALSE; + } + } +} + diff --git a/ports/cortex_a35/gnu/src/tx_thread_fp_enable.c b/ports/cortex_a35/gnu/src/tx_thread_fp_enable.c new file mode 100644 index 00000000..4a4751ab --- /dev/null +++ b/ports/cortex_a35/gnu/src/tx_thread_fp_enable.c @@ -0,0 +1,95 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fp_enable Cortex-A35/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function enabled the FP for the currently executing thread. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_fp_enable(VOID) +{ + +TX_THREAD *thread_ptr; +ULONG system_state; + + + /* Pickup the current thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr); + + /* Get the system state. */ + system_state = TX_THREAD_GET_SYSTEM_STATE(); + + /* Make sure it is not NULL. */ + if (thread_ptr != TX_NULL) + { + + /* Thread is running... make sure the call is from the thread context. */ + if (system_state == 0) + { + + /* Yes, now setup the FP enable flag in the TX_THREAD structure. */ + thread_ptr -> tx_thread_fp_enable = TX_TRUE; + } + } +} + diff --git a/ports/cortex_a35/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a35/gnu/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..f387c449 --- /dev/null +++ b/ports/cortex_a35/gnu/src/tx_thread_interrupt_control.S @@ -0,0 +1,89 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/*#define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control Cortex-A35/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_control(UINT new_posture) +{ */ + .global _tx_thread_interrupt_control + .type _tx_thread_interrupt_control, @function +_tx_thread_interrupt_control: + + /* Pickup current interrupt lockout posture. */ + + MRS x1, DAIF // Pickup current interrupt posture + + /* Apply the new interrupt posture. */ + + MSR DAIF, x0 // Set new interrupt posture + MOV x0, x1 // Setup return value + RET // Return to caller +/* } */ + diff --git a/ports/cortex_a35/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a35/gnu/src/tx_thread_interrupt_disable.S new file mode 100644 index 00000000..0e31281c --- /dev/null +++ b/ports/cortex_a35/gnu/src/tx_thread_interrupt_disable.S @@ -0,0 +1,87 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_disable Cortex-A35/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for disabling interrupts */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_disable(void) +{ */ + .global _tx_thread_interrupt_disable + .type _tx_thread_interrupt_disable, @function +_tx_thread_interrupt_disable: + + /* Pickup current interrupt lockout posture. */ + + MRS x0, DAIF // Pickup current interrupt lockout posture + + /* Mask interrupts. */ + + MSR DAIFSet, 0x3 // Lockout interrupts + RET // Return to caller +/* } */ + diff --git a/ports/cortex_a35/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a35/gnu/src/tx_thread_interrupt_restore.S new file mode 100644 index 00000000..7edae01a --- /dev/null +++ b/ports/cortex_a35/gnu/src/tx_thread_interrupt_restore.S @@ -0,0 +1,85 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_restore Cortex-A35/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for restoring interrupts to the state */ +/* returned by a previous _tx_thread_interrupt_disable call. */ +/* */ +/* INPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_restore(UINT old_posture) +{ */ + .global _tx_thread_interrupt_restore + .type _tx_thread_interrupt_restore, @function +_tx_thread_interrupt_restore: + + /* Restore the old interrupt posture. */ + + MSR DAIF, x0 // Setup the old posture + RET // Return to caller + +/* } */ + diff --git a/ports/cortex_a35/gnu/src/tx_thread_schedule.S b/ports/cortex_a35/gnu/src/tx_thread_schedule.S new file mode 100644 index 00000000..e55a0048 --- /dev/null +++ b/ports/cortex_a35/gnu/src/tx_thread_schedule.S @@ -0,0 +1,240 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + +/* .set ENABLE_ARM_FP,1 */ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule Cortex-A35/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* _tx_thread_context_restore Restore thread's context */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_schedule(VOID) +{ */ + .global _tx_thread_schedule + .type _tx_thread_schedule, @function +_tx_thread_schedule: + + /* Enable interrupts. */ + + MSR DAIFClr, 0x3 // Enable interrupts + + /* Wait for a thread to execute. */ + /* do + { */ + + LDR x1, =_tx_thread_execute_ptr // Address of thread execute ptr + +#ifdef TX_ENABLE_WFI +__tx_thread_schedule_loop: + LDR x0, [x1, #0] // Pickup next thread to execute + CMP x0, #0 // Is it NULL? + BNE _tx_thread_schedule_thread // + WFI // + B __tx_thread_schedule_loop // Keep looking for a thread +_tx_thread_schedule_thread: +#else +__tx_thread_schedule_loop: + LDR x0, [x1, #0] // Pickup next thread to execute + CMP x0, #0 // Is it NULL? + BEQ __tx_thread_schedule_loop // If so, keep looking for a thread +#endif + + /* } + while(_tx_thread_execute_ptr == TX_NULL); */ + + /* Yes! We have a thread to execute. Lockout interrupts and + transfer control to it. */ + + MSR DAIFSet, 0x3 // Lockout interrupts + + /* Setup the current thread pointer. */ + /* _tx_thread_current_ptr = _tx_thread_execute_ptr; */ + + LDR x1, =_tx_thread_current_ptr // Pickup address of current thread + STR x0, [x1, #0] // Setup current thread pointer + + /* Increment the run count for this thread. */ + /* _tx_thread_current_ptr -> tx_thread_run_count++; */ + + LDR w2, [x0, #4] // Pickup run counter + LDR w3, [x0, #36] // Pickup time-slice for this thread + ADD w2, w2, #1 // Increment thread run-counter + STR w2, [x0, #4] // Store the new run counter + + /* Setup time-slice, if present. */ + /* _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; */ + + LDR x2, =_tx_timer_time_slice // Pickup address of time slice + // variable + LDR x4, [x0, #8] // Switch stack pointers + MOV sp, x4 // + STR w3, [x2, #0] // Setup time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread entry function to indicate the thread is executing. */ + + MOV x19, x0 // Save x0 + BL _tx_execution_thread_enter // Call the thread execution enter function + MOV x0, x19 // Restore x0 +#endif + + /* Switch to the thread's stack. */ + /* sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; */ + + /* Determine if an interrupt frame or a synchronous task suspension frame + is present. */ + + LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL1 + CMP x5, #0 // Check for synchronous context switch (ELR_EL1 = NULL) + BEQ _tx_solicited_return +#ifdef EL1 + MSR SPSR_EL1, x4 // Setup SPSR for return + MSR ELR_EL1, x5 // Setup point of interrupt +#else +#ifdef EL2 + MSR SPSR_EL2, x4 // Setup SPSR for return + MSR ELR_EL2, x5 // Setup point of interrupt +#else + MSR SPSR_EL3, x4 // Setup SPSR for return + MSR ELR_EL3, x5 // Setup point of interrupt +#endif +#endif +#ifdef ENABLE_ARM_FP + LDR w1, [x0, #248] // Pickup FP enable flag + CMP w1, #0 // Is FP enabled? + BEQ _skip_interrupt_fp_restore // No, skip FP restore + LDP x0, x1, [sp], #16 // Pickup FPSR, FPCR + MSR FPSR, x0 // Recover FPSR + MSR FPCR, x1 // Recover FPCR + LDP q30, q31, [sp], #32 // Recover q30, q31 + LDP q28, q29, [sp], #32 // Recover q28, q29 + LDP q26, q27, [sp], #32 // Recover q26, q27 + LDP q24, q25, [sp], #32 // Recover q24, q25 + LDP q22, q23, [sp], #32 // Recover q22, q23 + LDP q20, q21, [sp], #32 // Recover q20, q21 + LDP q18, q19, [sp], #32 // Recover q18, q19 + LDP q16, q17, [sp], #32 // Recover q16, q17 + LDP q14, q15, [sp], #32 // Recover q14, q15 + LDP q12, q13, [sp], #32 // Recover q12, q13 + LDP q10, q11, [sp], #32 // Recover q10, q11 + LDP q8, q9, [sp], #32 // Recover q8, q9 + LDP q6, q7, [sp], #32 // Recover q6, q7 + LDP q4, q5, [sp], #32 // Recover q4, q5 + LDP q2, q3, [sp], #32 // Recover q2, q3 + LDP q0, q1, [sp], #32 // Recover q0, q1 +_skip_interrupt_fp_restore: +#endif + LDP x28, x29, [sp], #16 // Recover x28 + LDP x26, x27, [sp], #16 // Recover x26, x27 + LDP x24, x25, [sp], #16 // Recover x24, x25 + LDP x22, x23, [sp], #16 // Recover x22, x23 + LDP x20, x21, [sp], #16 // Recover x20, x21 + LDP x18, x19, [sp], #16 // Recover x18, x19 + LDP x16, x17, [sp], #16 // Recover x16, x17 + LDP x14, x15, [sp], #16 // Recover x14, x15 + LDP x12, x13, [sp], #16 // Recover x12, x13 + LDP x10, x11, [sp], #16 // Recover x10, x11 + LDP x8, x9, [sp], #16 // Recover x8, x9 + LDP x6, x7, [sp], #16 // Recover x6, x7 + LDP x4, x5, [sp], #16 // Recover x4, x5 + LDP x2, x3, [sp], #16 // Recover x2, x3 + LDP x0, x1, [sp], #16 // Recover x0, x1 + LDP x29, x30, [sp], #16 // Recover x29, x30 + ERET // Return to point of interrupt + +_tx_solicited_return: + +#ifdef ENABLE_ARM_FP + LDR w1, [x0, #248] // Pickup FP enable flag + CMP w1, #0 // Is FP enabled? + BEQ _skip_solicited_fp_restore // No, skip FP restore + LDP x0, x1, [sp], #16 // Pickup FPSR, FPCR + MSR FPSR, x0 // Recover FPSR + MSR FPCR, x1 // Recover FPCR + LDP q14, q15, [sp], #32 // Recover q14, q15 + LDP q12, q13, [sp], #32 // Recover q12, q13 + LDP q10, q11, [sp], #32 // Recover q10, q11 + LDP q8, q9, [sp], #32 // Recover q8, q9 +_skip_solicited_fp_restore: +#endif + LDP x27, x28, [sp], #16 // Recover x27, x28 + LDP x25, x26, [sp], #16 // Recover x25, x26 + LDP x23, x24, [sp], #16 // Recover x23, x24 + LDP x21, x22, [sp], #16 // Recover x21, x22 + LDP x19, x20, [sp], #16 // Recover x19, x20 + LDP x29, x30, [sp], #16 // Recover x29, x30 + MSR DAIF, x4 // Recover DAIF + RET // Return to caller +/* } */ + + diff --git a/ports/cortex_a35/gnu/src/tx_thread_stack_build.S b/ports/cortex_a35/gnu/src/tx_thread_stack_build.S new file mode 100644 index 00000000..d052a9e0 --- /dev/null +++ b/ports/cortex_a35/gnu/src/tx_thread_stack_build.S @@ -0,0 +1,170 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build Cortex-A35/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +{ */ + .global _tx_thread_stack_build + .type _tx_thread_stack_build, @function +_tx_thread_stack_build: + + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-A5x should look like the following after it is built: + + Stack Top: SSPR Initial SSPR + ELR Point of interrupt + x28 Initial value for x28 + not used Not used + x26 Initial value for x26 + x27 Initial value for x27 + x24 Initial value for x24 + x25 Initial value for x25 + x22 Initial value for x22 + x23 Initial value for x23 + x20 Initial value for x20 + x21 Initial value for x21 + x18 Initial value for x18 + x19 Initial value for x19 + x16 Initial value for x16 + x17 Initial value for x17 + x14 Initial value for x14 + x15 Initial value for x15 + x12 Initial value for x12 + x13 Initial value for x13 + x10 Initial value for x10 + x11 Initial value for x11 + x8 Initial value for x8 + x9 Initial value for x9 + x6 Initial value for x6 + x7 Initial value for x7 + x4 Initial value for x4 + x5 Initial value for x5 + x2 Initial value for x2 + x3 Initial value for x3 + x0 Initial value for x0 + x1 Initial value for x1 + x29 Initial value for x29 (frame pointer) + x30 Initial value for x30 (link register) + 0 For stack backtracing + + Stack Bottom: (higher memory address) */ + + LDR x4, [x0, #24] // Pickup end of stack area + BIC x4, x4, #0xF // Ensure 16-byte alignment + + /* Actually build the stack frame. */ + + MOV x2, #0 // Build clear value + MOV x3, #0 // + + STP x2, x3, [x4, #-16]! // Set backtrace to 0 + STP x2, x3, [x4, #-16]! // Set initial x29, x30 + STP x2, x3, [x4, #-16]! // Set initial x0, x1 + STP x2, x3, [x4, #-16]! // Set initial x2, x3 + STP x2, x3, [x4, #-16]! // Set initial x4, x5 + STP x2, x3, [x4, #-16]! // Set initial x6, x7 + STP x2, x3, [x4, #-16]! // Set initial x8, x9 + STP x2, x3, [x4, #-16]! // Set initial x10, x11 + STP x2, x3, [x4, #-16]! // Set initial x12, x13 + STP x2, x3, [x4, #-16]! // Set initial x14, x15 + STP x2, x3, [x4, #-16]! // Set initial x16, x17 + STP x2, x3, [x4, #-16]! // Set initial x18, x19 + STP x2, x3, [x4, #-16]! // Set initial x20, x21 + STP x2, x3, [x4, #-16]! // Set initial x22, x23 + STP x2, x3, [x4, #-16]! // Set initial x24, x25 + STP x2, x3, [x4, #-16]! // Set initial x26, x27 + STP x2, x3, [x4, #-16]! // Set initial x28 +#ifdef EL1 + MOV x2, #0x4 // Build initial SPSR (EL1) +#else +#ifdef EL2 + MOV x2, #0x8 // Build initial SPSR (EL2) +#else + MOV x2, #0xC // Build initial SPSR (EL3) +#endif +#endif + MOV x3, x1 // Build initial ELR + STP x2, x3, [x4, #-16]! // Set initial SPSR & ELR + + /* Setup stack pointer. */ + /* thread_ptr -> tx_thread_stack_ptr = x2; */ + + STR x4, [x0, #8] // Save stack pointer in thread's + RET // Return to caller + +/* } */ + + diff --git a/ports/cortex_a35/gnu/src/tx_thread_system_return.S b/ports/cortex_a35/gnu/src/tx_thread_system_return.S new file mode 100644 index 00000000..eb9d5b34 --- /dev/null +++ b/ports/cortex_a35/gnu/src/tx_thread_system_return.S @@ -0,0 +1,165 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + +/* .set ENABLE_ARM_FP,1 */ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return Cortex-A35/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the ThreadX system. Only a */ +/* minimal context is saved since the compiler assumes temp registers */ +/* are going to get slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_system_return(VOID) +{ */ + .global _tx_thread_system_return + .type _tx_thread_system_return, @function +_tx_thread_system_return: +; +; /* Save minimal context on the stack. */ +; + MRS x0, DAIF // Pickup DAIF + MSR DAIFSet, 0x3 // Lockout interrupts + STP x29, x30, [sp, #-16]! // Save x29 (frame pointer), x30 (link register) + STP x19, x20, [sp, #-16]! // Save x19, x20 + STP x21, x22, [sp, #-16]! // Save x21, x22 + STP x23, x24, [sp, #-16]! // Save x23, x24 + STP x25, x26, [sp, #-16]! // Save x25, x26 + STP x27, x28, [sp, #-16]! // Save x27, x28 + LDR x5, =_tx_thread_current_ptr // Pickup address of current ptr + LDR x6, [x5, #0] // Pickup current thread pointer + +#ifdef ENABLE_ARM_FP + LDR w7, [x6, #248] // Pickup FP enable flag + CMP w7, #0 // Is FP enabled? + BEQ _skip_fp_save // No, skip FP save + STP q8, q9, [sp, #-32]! // Save q8, q9 + STP q10, q11, [sp, #-32]! // Save q10, q11 + STP q12, q13, [sp, #-32]! // Save q12, q13 + STP q14, q15, [sp, #-32]! // Save q14, q15 + MRS x2, FPSR // Pickup FPSR + MRS x3, FPCR // Pickup FPCR + STP x2, x3, [sp, #-16]! // Save FPSR, FPCR +_skip_fp_save: +#endif + + MOV x1, #0 // Clear x1 + STP x0, x1, [sp, #-16]! // Save DAIF and clear value for ELR_EK1 + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread exit function to indicate the thread is no longer executing. */ + + MOV x19, x5 // Save x5 + MOV x20, x6 // Save x6 + BL _tx_execution_thread_exit // Call the thread exit function + MOV x5, x19 // Restore x5 + MOV x6, x20 // Restore x6 +#endif + + LDR x2, =_tx_timer_time_slice // Pickup address of time slice + LDR w1, [x2, #0] // Pickup current time slice + + /* Save current stack and switch to system stack. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ + /* sp = _tx_thread_system_stack_ptr; */ + + MOV x4, sp // + STR x4, [x6, #8] // Save thread stack pointer + LDR x3, =_tx_thread_system_stack_ptr // Pickup address of system stack + LDR x4, [x3, #0] // Pickup system stack pointer + MOV sp, x4 // Setup system stack pointer + + /* Determine if the time-slice is active. */ + /* if (_tx_timer_time_slice) + { */ + + MOV x4, #0 // Build clear value + CMP w1, #0 // Is a time-slice active? + BEQ __tx_thread_dont_save_ts // No, don't save the time-slice + + /* Save the current remaining time-slice. */ + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + STR w4, [x2, #0] // Clear time-slice + STR w1, [x6, #36] // Store current time-slice + + /* } */ +__tx_thread_dont_save_ts: + + /* Clear the current thread pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + STR x4, [x5, #0] // Clear current thread pointer + + B _tx_thread_schedule // Jump to scheduler! + +/* } */ + + diff --git a/ports/cortex_a35/gnu/src/tx_timer_interrupt.S b/ports/cortex_a35/gnu/src/tx_timer_interrupt.S new file mode 100644 index 00000000..a2808e78 --- /dev/null +++ b/ports/cortex_a35/gnu/src/tx_timer_interrupt.S @@ -0,0 +1,240 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_timer.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt Cortex-A35/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_timer_interrupt(VOID) +{ */ + .global _tx_timer_interrupt + .type _tx_timer_interrupt, @function +_tx_timer_interrupt: + + /* Upon entry to this routine, it is assumed that context save has already + been called, and therefore the compiler scratch registers are available + for use. */ + + /* Increment the system clock. */ + /* _tx_timer_system_clock++; */ + + LDR x1, =_tx_timer_system_clock // Pickup address of system clock + LDR w0, [x1, #0] // Pickup system clock + ADD w0, w0, #1 // Increment system clock + STR w0, [x1, #0] // Store new system clock + + /* Test for time-slice expiration. */ + /* if (_tx_timer_time_slice) + { */ + + LDR x3, =_tx_timer_time_slice // Pickup address of time-slice + LDR w2, [x3, #0] // Pickup time-slice + CMP w2, #0 // Is it non-active? + BEQ __tx_timer_no_time_slice // Yes, skip time-slice processing + + /* Decrement the time_slice. */ + /* _tx_timer_time_slice--; */ + + SUB w2, w2, #1 // Decrement the time-slice + STR w2, [x3, #0] // Store new time-slice value + + /* Check for expiration. */ + /* if (__tx_timer_time_slice == 0) */ + + CMP w2, #0 // Has it expired? + BNE __tx_timer_no_time_slice // No, skip expiration processing + + /* Set the time-slice expired flag. */ + /* _tx_timer_expired_time_slice = TX_TRUE; */ + + LDR x3, =_tx_timer_expired_time_slice // Pickup address of expired flag + MOV w0, #1 // Build expired value + STR w0, [x3, #0] // Set time-slice expiration flag + + /* } */ + +__tx_timer_no_time_slice: + + /* Test for timer expiration. */ + /* if (*_tx_timer_current_ptr) + { */ + + LDR x1, =_tx_timer_current_ptr // Pickup current timer pointer addr + LDR x0, [x1, #0] // Pickup current timer + LDR x2, [x0, #0] // Pickup timer list entry + CMP x2, #0 // Is there anything in the list? + BEQ __tx_timer_no_timer // No, just increment the timer + + /* Set expiration flag. */ + /* _tx_timer_expired = TX_TRUE; */ + + LDR x3, =_tx_timer_expired // Pickup expiration flag address + MOV w2, #1 // Build expired value + STR w2, [x3, #0] // Set expired flag + B __tx_timer_done // Finished timer processing + + /* } + else + { */ +__tx_timer_no_timer: + + /* No timer expired, increment the timer pointer. */ + /* _tx_timer_current_ptr++; */ + + ADD x0, x0, #8 // Move to next timer + + /* Check for wrap-around. */ + /* if (_tx_timer_current_ptr == _tx_timer_list_end) */ + + LDR x3, =_tx_timer_list_end // Pickup addr of timer list end + LDR x2, [x3, #0] // Pickup list end + CMP x0, x2 // Are we at list end? + BNE __tx_timer_skip_wrap // No, skip wrap-around logic + + /* Wrap to beginning of list. */ + /* _tx_timer_current_ptr = _tx_timer_list_start; */ + + LDR x3, =_tx_timer_list_start // Pickup addr of timer list start + LDR x0, [x3, #0] // Set current pointer to list start + +__tx_timer_skip_wrap: + + STR x0, [x1, #0] // Store new current timer pointer + /* } */ + +__tx_timer_done: + + + /* See if anything has expired. */ + /* if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) + { */ + + LDR x3, =_tx_timer_expired_time_slice // Pickup addr of expired flag + LDR w2, [x3, #0] // Pickup time-slice expired flag + CMP w2, #0 // Did a time-slice expire? + BNE __tx_something_expired // If non-zero, time-slice expired + LDR x1, =_tx_timer_expired // Pickup addr of other expired flag + LDR w0, [x1, #0] // Pickup timer expired flag + CMP w0, #0 // Did a timer expire? + BEQ __tx_timer_nothing_expired // No, nothing expired + +__tx_something_expired: + + + STP x29, x30, [sp, #-16]! // Save x29 (frame pointer), x30 (link register) + + /* Did a timer expire? */ + /* if (_tx_timer_expired) + { */ + + LDR x1, =_tx_timer_expired // Pickup addr of expired flag + LDR w0, [x1, #0] // Pickup timer expired flag + CMP w0, #0 // Check for timer expiration + BEQ __tx_timer_dont_activate // If not set, skip timer activation + + /* Process timer expiration. */ + /* _tx_timer_expiration_process(); */ + + BL _tx_timer_expiration_process // Call the timer expiration handling routine + + /* } */ +__tx_timer_dont_activate: + + /* Did time slice expire? */ + /* if (_tx_timer_expired_time_slice) + { */ + + LDR x3, =_tx_timer_expired_time_slice // Pickup addr of time-slice expired + LDR w2, [x3, #0] // Pickup the actual flag + CMP w2, #0 // See if the flag is set + BEQ __tx_timer_not_ts_expiration // No, skip time-slice processing + + /* Time slice interrupted thread. */ + /* _tx_thread_time_slice(); */ + + BL _tx_thread_time_slice // Call time-slice processing + + /* } */ + +__tx_timer_not_ts_expiration: + + LDP x29, x30, [sp], #16 // Recover x29, x30 + /* } */ + +__tx_timer_nothing_expired: + + RET // Return to caller + +/* } */ + + diff --git a/ports/cortex_a5/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_a5/ac5/example_build/tx_initialize_low_level.s index 03505b66..e553657b 100644 --- a/ports/cortex_a5/ac5/example_build/tx_initialize_low_level.s +++ b/ports/cortex_a5/ac5/example_build/tx_initialize_low_level.s @@ -96,7 +96,7 @@ __vectors ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level Cortex-A5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -129,7 +129,7 @@ __vectors ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_a5/ac5/inc/tx_port.h b/ports/cortex_a5/ac5/inc/tx_port.h index d2f09195..516f3f0f 100644 --- a/ports/cortex_a5/ac5/inc/tx_port.h +++ b/ports/cortex_a5/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A5/AC5 */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -324,7 +324,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5/AC5 Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5/AC5 Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a5/ac5/readme_threadx.txt b/ports/cortex_a5/ac5/readme_threadx.txt index 4dcbf556..d6a08426 100644 --- a/ports/cortex_a5/ac5/readme_threadx.txt +++ b/ports/cortex_a5/ac5/readme_threadx.txt @@ -535,7 +535,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A5 using AC5 tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-A5 using AC5 tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_a5/ac5/src/tx_thread_context_restore.s b/ports/cortex_a5/ac5/src/tx_thread_context_restore.s index 1434cb44..d0b82fbb 100644 --- a/ports/cortex_a5/ac5/src/tx_thread_context_restore.s +++ b/ports/cortex_a5/ac5/src/tx_thread_context_restore.s @@ -60,7 +60,7 @@ SVC_MODE EQU 0x93 ; SVC mode ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore Cortex-A5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -92,7 +92,7 @@ SVC_MODE EQU 0x93 ; SVC mode ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_a5/ac5/src/tx_thread_context_save.s b/ports/cortex_a5/ac5/src/tx_thread_context_save.s index fac7c5a4..fb73006d 100644 --- a/ports/cortex_a5/ac5/src/tx_thread_context_save.s +++ b/ports/cortex_a5/ac5/src/tx_thread_context_save.s @@ -45,7 +45,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save Cortex-A5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -76,7 +76,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_a5/ac5/src/tx_thread_fiq_context_restore.s b/ports/cortex_a5/ac5/src/tx_thread_fiq_context_restore.s index 66186e5a..9a7bc396 100644 --- a/ports/cortex_a5/ac5/src/tx_thread_fiq_context_restore.s +++ b/ports/cortex_a5/ac5/src/tx_thread_fiq_context_restore.s @@ -56,7 +56,7 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_context_restore Cortex-A5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -88,7 +88,7 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_context_restore(VOID) diff --git a/ports/cortex_a5/ac5/src/tx_thread_fiq_context_save.s b/ports/cortex_a5/ac5/src/tx_thread_fiq_context_save.s index 198ea091..9cc7fa32 100644 --- a/ports/cortex_a5/ac5/src/tx_thread_fiq_context_save.s +++ b/ports/cortex_a5/ac5/src/tx_thread_fiq_context_save.s @@ -45,7 +45,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_context_save Cortex-A5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -76,7 +76,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ; VOID _tx_thread_fiq_context_save(VOID) diff --git a/ports/cortex_a5/ac5/src/tx_thread_fiq_nesting_end.s b/ports/cortex_a5/ac5/src/tx_thread_fiq_nesting_end.s index d1007354..3fecebcb 100644 --- a/ports/cortex_a5/ac5/src/tx_thread_fiq_nesting_end.s +++ b/ports/cortex_a5/ac5/src/tx_thread_fiq_nesting_end.s @@ -45,7 +45,7 @@ FIQ_MODE_BITS EQU 0x11 ; FIQ mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_nesting_end Cortex-A5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -84,7 +84,7 @@ FIQ_MODE_BITS EQU 0x11 ; FIQ mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_end(VOID) diff --git a/ports/cortex_a5/ac5/src/tx_thread_fiq_nesting_start.s b/ports/cortex_a5/ac5/src/tx_thread_fiq_nesting_start.s index aa8e30bd..2e196e04 100644 --- a/ports/cortex_a5/ac5/src/tx_thread_fiq_nesting_start.s +++ b/ports/cortex_a5/ac5/src/tx_thread_fiq_nesting_start.s @@ -41,7 +41,7 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_nesting_start Cortex-A5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/cortex_a5/ac5/src/tx_thread_interrupt_control.s b/ports/cortex_a5/ac5/src/tx_thread_interrupt_control.s index 9c48eea6..22efbaa7 100644 --- a/ports/cortex_a5/ac5/src/tx_thread_interrupt_control.s +++ b/ports/cortex_a5/ac5/src/tx_thread_interrupt_control.s @@ -42,7 +42,7 @@ INT_MASK EQU 0x80 ; Interrupt bit mask ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control Cortex-A5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ INT_MASK EQU 0x80 ; Interrupt bit mask ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a5/ac5/src/tx_thread_interrupt_disable.s b/ports/cortex_a5/ac5/src/tx_thread_interrupt_disable.s index b9996a64..96902003 100644 --- a/ports/cortex_a5/ac5/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_a5/ac5/src/tx_thread_interrupt_disable.s @@ -35,7 +35,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_disable Cortex-A5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -64,7 +64,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(void) diff --git a/ports/cortex_a5/ac5/src/tx_thread_interrupt_restore.s b/ports/cortex_a5/ac5/src/tx_thread_interrupt_restore.s index a331c9df..8736cac4 100644 --- a/ports/cortex_a5/ac5/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_a5/ac5/src/tx_thread_interrupt_restore.s @@ -35,7 +35,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-A5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -65,7 +65,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a5/ac5/src/tx_thread_irq_nesting_end.s b/ports/cortex_a5/ac5/src/tx_thread_irq_nesting_end.s index 42d3fca2..e08062ba 100644 --- a/ports/cortex_a5/ac5/src/tx_thread_irq_nesting_end.s +++ b/ports/cortex_a5/ac5/src/tx_thread_irq_nesting_end.s @@ -45,7 +45,7 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_irq_nesting_end Cortex-A5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -84,7 +84,7 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports/cortex_a5/ac5/src/tx_thread_irq_nesting_start.s b/ports/cortex_a5/ac5/src/tx_thread_irq_nesting_start.s index eb7c2952..e7d6696f 100644 --- a/ports/cortex_a5/ac5/src/tx_thread_irq_nesting_start.s +++ b/ports/cortex_a5/ac5/src/tx_thread_irq_nesting_start.s @@ -41,7 +41,7 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_irq_nesting_start Cortex-A5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_a5/ac5/src/tx_thread_schedule.s b/ports/cortex_a5/ac5/src/tx_thread_schedule.s index 6e250a23..6ccd94f7 100644 --- a/ports/cortex_a5/ac5/src/tx_thread_schedule.s +++ b/ports/cortex_a5/ac5/src/tx_thread_schedule.s @@ -46,7 +46,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-A5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -79,7 +79,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_a5/ac5/src/tx_thread_stack_build.s b/ports/cortex_a5/ac5/src/tx_thread_stack_build.s index 00764f2b..d9721b57 100644 --- a/ports/cortex_a5/ac5/src/tx_thread_stack_build.s +++ b/ports/cortex_a5/ac5/src/tx_thread_stack_build.s @@ -47,7 +47,7 @@ THUMB_BIT EQU 0x20 ; Thumb-bit ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build Cortex-A5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -79,7 +79,7 @@ THUMB_BIT EQU 0x20 ; Thumb-bit ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_a5/ac5/src/tx_thread_system_return.s b/ports/cortex_a5/ac5/src/tx_thread_system_return.s index a5e3120b..85a5a035 100644 --- a/ports/cortex_a5/ac5/src/tx_thread_system_return.s +++ b/ports/cortex_a5/ac5/src/tx_thread_system_return.s @@ -45,7 +45,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return Cortex-A5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_a5/ac5/src/tx_thread_vectored_context_save.s b/ports/cortex_a5/ac5/src/tx_thread_vectored_context_save.s index 375b9fad..a374eb7a 100644 --- a/ports/cortex_a5/ac5/src/tx_thread_vectored_context_save.s +++ b/ports/cortex_a5/ac5/src/tx_thread_vectored_context_save.s @@ -44,7 +44,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_vectored_context_save Cortex-A5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -75,7 +75,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) diff --git a/ports/cortex_a5/ac5/src/tx_timer_interrupt.s b/ports/cortex_a5/ac5/src/tx_timer_interrupt.s index 422e3576..463c73c3 100644 --- a/ports/cortex_a5/ac5/src/tx_timer_interrupt.s +++ b/ports/cortex_a5/ac5/src/tx_timer_interrupt.s @@ -50,7 +50,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt Cortex-A5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -84,7 +84,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_a5/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_a5/gnu/example_build/tx_initialize_low_level.S index e4c5b25f..1e7b0abb 100644 --- a/ports/cortex_a5/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_a5/gnu/example_build/tx_initialize_low_level.S @@ -78,7 +78,7 @@ $_tx_initialize_low_level: @/* FUNCTION RELEASE */ @/* */ @/* _tx_initialize_low_level Cortex-A5/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -111,7 +111,7 @@ $_tx_initialize_low_level: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_a5/gnu/inc/tx_port.h b/ports/cortex_a5/gnu/inc/tx_port.h index 8a389740..989d71ed 100644 --- a/ports/cortex_a5/gnu/inc/tx_port.h +++ b/ports/cortex_a5/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A5/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -313,7 +313,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5/GNU Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5/GNU Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a5/gnu/readme_threadx.txt b/ports/cortex_a5/gnu/readme_threadx.txt index 37a92981..28569eda 100644 --- a/ports/cortex_a5/gnu/readme_threadx.txt +++ b/ports/cortex_a5/gnu/readme_threadx.txt @@ -503,7 +503,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A5 using GNU tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-A5 using GNU tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_a5/gnu/src/tx_thread_context_restore.S b/ports/cortex_a5/gnu/src/tx_thread_context_restore.S index 2a3f0165..73f70895 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a5/gnu/src/tx_thread_context_restore.S @@ -60,7 +60,7 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_restore Cortex-A5/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -92,7 +92,7 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_a5/gnu/src/tx_thread_context_save.S b/ports/cortex_a5/gnu/src/tx_thread_context_save.S index d35776b6..20f372e7 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a5/gnu/src/tx_thread_context_save.S @@ -48,7 +48,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_save Cortex-A5/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -79,7 +79,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_a5/gnu/src/tx_thread_fiq_context_restore.S b/ports/cortex_a5/gnu/src/tx_thread_fiq_context_restore.S index b7a6d9cb..dccc6c18 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_a5/gnu/src/tx_thread_fiq_context_restore.S @@ -59,7 +59,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_context_restore Cortex-A5/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -91,7 +91,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_context_restore(VOID) diff --git a/ports/cortex_a5/gnu/src/tx_thread_fiq_context_save.S b/ports/cortex_a5/gnu/src/tx_thread_fiq_context_save.S index 44dbcf7d..ebb197aa 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_a5/gnu/src/tx_thread_fiq_context_save.S @@ -47,7 +47,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_context_save Cortex-A5/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -78,7 +78,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @ VOID _tx_thread_fiq_context_save(VOID) diff --git a/ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_end.S index 884f3347..5a21397a 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_end.S @@ -50,7 +50,7 @@ FIQ_MODE_BITS = 0x11 @ FIQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_nesting_end Cortex-A5/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -89,7 +89,7 @@ FIQ_MODE_BITS = 0x11 @ FIQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_end(VOID) diff --git a/ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_start.S index f80d74b6..6afdc528 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_start.S @@ -46,7 +46,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_nesting_start Cortex-A5/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/cortex_a5/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a5/gnu/src/tx_thread_interrupt_control.S index ff7db62d..a56054c4 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a5/gnu/src/tx_thread_interrupt_control.S @@ -56,7 +56,7 @@ $_tx_thread_interrupt_control: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_control Cortex-A5/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -86,7 +86,7 @@ $_tx_thread_interrupt_control: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a5/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a5/gnu/src/tx_thread_interrupt_disable.S index a65b911d..76693663 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a5/gnu/src/tx_thread_interrupt_disable.S @@ -53,7 +53,7 @@ $_tx_thread_interrupt_disable: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_disable Cortex-A5/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ $_tx_thread_interrupt_disable: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_disable(void) diff --git a/ports/cortex_a5/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a5/gnu/src/tx_thread_interrupt_restore.S index 4bea9e52..043c6fd9 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a5/gnu/src/tx_thread_interrupt_restore.S @@ -53,7 +53,7 @@ $_tx_thread_interrupt_restore: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_restore Cortex-A5/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -83,7 +83,7 @@ $_tx_thread_interrupt_restore: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a5/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_a5/gnu/src/tx_thread_irq_nesting_end.S index 35284eed..2cd4f44a 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a5/gnu/src/tx_thread_irq_nesting_end.S @@ -50,7 +50,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_irq_nesting_end Cortex-A5/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -89,7 +89,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports/cortex_a5/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_a5/gnu/src/tx_thread_irq_nesting_start.S index 6b702e93..ff5ef319 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a5/gnu/src/tx_thread_irq_nesting_start.S @@ -46,7 +46,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_irq_nesting_start Cortex-A5/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_a5/gnu/src/tx_thread_schedule.S b/ports/cortex_a5/gnu/src/tx_thread_schedule.S index df86a053..d4ddfce3 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a5/gnu/src/tx_thread_schedule.S @@ -62,7 +62,7 @@ $_tx_thread_schedule: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule Cortex-A5/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -95,7 +95,7 @@ $_tx_thread_schedule: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_a5/gnu/src/tx_thread_stack_build.S b/ports/cortex_a5/gnu/src/tx_thread_stack_build.S index 90f28e0b..8f09c7ae 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a5/gnu/src/tx_thread_stack_build.S @@ -64,7 +64,7 @@ $_tx_thread_stack_build: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_stack_build Cortex-A5/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -96,7 +96,7 @@ $_tx_thread_stack_build: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_a5/gnu/src/tx_thread_system_return.S b/ports/cortex_a5/gnu/src/tx_thread_system_return.S index 7c2878de..bb141595 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a5/gnu/src/tx_thread_system_return.S @@ -64,7 +64,7 @@ $_tx_thread_system_return: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_system_return Cortex-A5/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -96,7 +96,7 @@ $_tx_thread_system_return: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_a5/gnu/src/tx_thread_vectored_context_save.S b/ports/cortex_a5/gnu/src/tx_thread_vectored_context_save.S index de6a5a7c..e40893a5 100644 --- a/ports/cortex_a5/gnu/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_a5/gnu/src/tx_thread_vectored_context_save.S @@ -47,7 +47,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_vectored_context_save Cortex-A5/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -78,7 +78,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_vectored_context_save(VOID) diff --git a/ports/cortex_a5/gnu/src/tx_timer_interrupt.S b/ports/cortex_a5/gnu/src/tx_timer_interrupt.S index cdecf06c..2f922527 100644 --- a/ports/cortex_a5/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a5/gnu/src/tx_timer_interrupt.S @@ -71,7 +71,7 @@ $_tx_timer_interrupt: @/* FUNCTION RELEASE */ @/* */ @/* _tx_timer_interrupt Cortex-A5/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -105,7 +105,7 @@ $_tx_timer_interrupt: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_a5/green/example_build/azure_rtos_workspace.gpj b/ports/cortex_a5/green/example_build/azure_rtos_workspace.gpj new file mode 100644 index 00000000..3b56f15c --- /dev/null +++ b/ports/cortex_a5/green/example_build/azure_rtos_workspace.gpj @@ -0,0 +1,12 @@ +#!gbuild +primaryTarget=arm_standalone.tgt +[Project] + -bsp generic + -G + -cpu=cortexa5 + -littleendian +sample_threadx.gpj [Program] +sample_threadx_el.gpj [Program] +tx.gpj [Library] +txe.gpj [Library] +..\readme_threadx.txt diff --git a/ports/cortex_a5/green/example_build/reset.arm b/ports/cortex_a5/green/example_build/reset.arm new file mode 100644 index 00000000..67136f44 --- /dev/null +++ b/ports/cortex_a5/green/example_build/reset.arm @@ -0,0 +1,45 @@ +# +# +#/* Define the Cortex-A5 vector area. This should be located or copied to 0. */ +# + + .section ".reset", .text + .globl __vectors +__vectors: + B __entry # Reset goes to the entry function + LDR pc,UNDEFINED # Undefined handler + LDR pc,SWI # Software interrupt handler + LDR pc,PREFETCH # Prefetch exception handler + LDR pc,ABORT # Abort exception handler + LDR pc,RESERVED # Reserved exception handler + LDR pc,IRQ # IRQ interrupt handler + LDR pc,FIQ # FIQ interrupt handler +# +# +__entry: + LDR sp,STACK # Setup stack pointer + LDR pc,START # Jump to Green Hills startup +# +# +STACK: + .data.w __ghsend_stack +START: + .data.w _start # Reset goes to startup function +UNDEFINED: + .data.w __tx_undefined # Undefined handler +SWI: + .data.w __tx_swi_interrupt # Software interrupt handler +PREFETCH: + .data.w __tx_prefetch_handler # Prefetch exception handler +ABORT: + .data.w __tx_abort_handler # Abort exception handler +RESERVED: + .data.w __tx_reserved_handler # Reserved exception handler +IRQ: + .data.w __tx_irq_handler # IRQ interrupt handler +FIQ: + .data.w __tx_fiq_handler # FIQ interrupt handler +# +# + .type __vectors,$function + .size __vectors,.-__vectors diff --git a/ports/cortex_a5/green/example_build/sample_threadx.c b/ports/cortex_a5/green/example_build/sample_threadx.c new file mode 100644 index 00000000..418ec634 --- /dev/null +++ b/ports/cortex_a5/green/example_build/sample_threadx.c @@ -0,0 +1,369 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_a5/green/example_build/sample_threadx.con b/ports/cortex_a5/green/example_build/sample_threadx.con new file mode 100644 index 00000000..7d427f10 --- /dev/null +++ b/ports/cortex_a5/green/example_build/sample_threadx.con @@ -0,0 +1,11 @@ +target_connection.00000000.title="Simulator connection for ThreadX" +target_connection.00000000.type="Custom" +target_connection.00000000.short_type="Custom" +target_connection.00000000.args="simarm -cpu=cortexa5 -fpu -rom" +target_connection.00000000.command="simarm -cpu=cortexa5 -fpu -rom" +target_connection.00000000.logfile="" +target_connection.00000000.mode="download" +target_connection.00000000.setup_script="" +target_connection.00000000.sane="yes" +target_connection.00000000.log="no" +target_connection.00000000.timestamp="1192825758" diff --git a/ports/cortex_a5/green/example_build/sample_threadx.gpj b/ports/cortex_a5/green/example_build/sample_threadx.gpj new file mode 100644 index 00000000..b9b2c04c --- /dev/null +++ b/ports/cortex_a5/green/example_build/sample_threadx.gpj @@ -0,0 +1,11 @@ +#!gbuild +[Program] + -I../../../../common/inc + -I../../../../ports_common_green/inc + -I../inc +reset.arm +tx_initialize_low_level.arm +sample_threadx.c +tx.a +sample_threadx.ld +sample_threadx.con diff --git a/ports/cortex_a5/green/example_build/sample_threadx.ld b/ports/cortex_a5/green/example_build/sample_threadx.ld new file mode 100644 index 00000000..8d1ab4df --- /dev/null +++ b/ports/cortex_a5/green/example_build/sample_threadx.ld @@ -0,0 +1,44 @@ +# The following explains what the default Green Hills sections are for: +# +# picbase - base of the text sections, relocatable in -pic mode +# text - text section +# syscall - syscall section, for host I/O under Multi +# fixaddr/fixtype - for PIC/PID fixups +# rodata - read only data +# romdata - the ROM image of .data +# romsdata - the ROM image of .sdata +# secinfo - section information section, used by the start-up code +# pidbase - base of the data sections, relocatable in -pid mode +# sdabase - base of the small data area section pointer +# sbss - small BSS (zeroed data) section +# sdata - small data section +# data - non-zeroed writeable data section +# bss - zeroed data section +# heap - the heap, grows upward +# stack - the stack, grows downward + +-sec +{ + .reset 0x000000 : + .picbase 0x1000 : + .text : + .comment : + .intercall : + .interfunc : + .syscall : + .fixaddr : + .fixtype : + .rodata : + .romdata ROM(.data) : + .romsdata ROM(.sdata) : + .secinfo : + .pidbase align(16) : + .sdabase : + .sbss : + .sdata : + .data : + .bss : + .heap align(16) pad(0x10000) : + .stack align(16) pad(0x1000) : + .free_mem align(16) pad(0x10000) : +} diff --git a/ports/cortex_a5/green/example_build/sample_threadx_el.gpj b/ports/cortex_a5/green/example_build/sample_threadx_el.gpj new file mode 100644 index 00000000..a51049ca --- /dev/null +++ b/ports/cortex_a5/green/example_build/sample_threadx_el.gpj @@ -0,0 +1,13 @@ +#!gbuild +[Program] + -DTX_ENABLE_EVENT_LOGGING + -I../../../../common/inc + -I../../../../ports_common_green/inc + -I../inc +reset.arm +tx_initialize_low_level.arm +sample_threadx.c +txe.a +sample_threadx_el.ld +sample_threadx.con +readme_threadx.txt diff --git a/ports/cortex_a5/green/example_build/sample_threadx_el.ld b/ports/cortex_a5/green/example_build/sample_threadx_el.ld new file mode 100644 index 00000000..33c0f934 --- /dev/null +++ b/ports/cortex_a5/green/example_build/sample_threadx_el.ld @@ -0,0 +1,45 @@ +# The following explains what the default Green Hills sections are for: +# +# picbase - base of the text sections, relocatable in -pic mode +# text - text section +# syscall - syscall section, for host I/O under Multi +# fixaddr/fixtype - for PIC/PID fixups +# rodata - read only data +# romdata - the ROM image of .data +# romsdata - the ROM image of .sdata +# secinfo - section information section, used by the start-up code +# pidbase - base of the data sections, relocatable in -pid mode +# sdabase - base of the small data area section pointer +# sbss - small BSS (zeroed data) section +# sdata - small data section +# data - non-zeroed writeable data section +# bss - zeroed data section +# heap - the heap, grows upward +# stack - the stack, grows downward + +-sec +{ + .reset 0x000000 : + .picbase 0x1000 : + .text : + .comment : + .intercall : + .interfunc : + .syscall : + .fixaddr : + .fixtype : + .rodata : + .romdata ROM(.data) : + .romsdata ROM(.sdata) : + .secinfo : + .pidbase align(16) : + .sdabase : + .sbss : + .sdata : + .data : + .bss : + .heap align(16) pad(0x1000) : + .stack align(16) pad(0x1000) : + .eventlog align(16) pad(0x10000) : + .free_mem align(16) pad(0x10000) : +} diff --git a/ports/cortex_a5/green/example_build/tx.gpj b/ports/cortex_a5/green/example_build/tx.gpj new file mode 100644 index 00000000..afbd6bef --- /dev/null +++ b/ports/cortex_a5/green/example_build/tx.gpj @@ -0,0 +1,283 @@ +#!gbuild +[Library] + -I../../../../common/inc + -I../../../../ports_common_green/inc + -I../inc +..\..\..\..\common\inc\tx_api.h +..\..\..\..\common\inc\tx_block_pool.h +..\..\..\..\common\inc\tx_byte_pool.h +..\..\..\..\common\inc\tx_event_flags.h +..\..\..\..\common\inc\tx_initialize.h +..\..\..\..\common\inc\tx_mutex.h +..\..\..\..\common\inc\tx_queue.h +..\..\..\..\common\inc\tx_semaphore.h +..\..\..\..\common\inc\tx_thread.h +..\..\..\..\common\inc\tx_timer.h +..\..\..\..\common\inc\tx_trace.h +..\..\..\..\common\inc\tx_user_sample.h +..\inc\tx_port.h +..\..\..\..\ports_common_green\inc\tx_el.h +..\..\..\..\ports_common_green\inc\tx_ghs.h +..\src\tx_thread_context_restore.arm +..\src\tx_thread_context_save.arm +..\src\tx_thread_fiq_context_restore.arm +..\src\tx_thread_fiq_context_save.arm +..\src\tx_thread_fiq_nesting_end.arm +..\src\tx_thread_fiq_nesting_start.arm +..\src\tx_thread_interrupt_control.arm +..\src\tx_thread_interrupt_disable.arm +..\src\tx_thread_interrupt_restore.arm +..\src\tx_thread_irq_nesting_end.arm +..\src\tx_thread_irq_nesting_start.arm +..\src\tx_thread_schedule.arm +..\src\tx_thread_stack_build.arm +..\src\tx_thread_system_return.arm +..\src\tx_thread_vectored_context_save.arm +..\src\tx_timer_interrupt.arm +..\..\..\..\common\src\tx_block_allocate.c +..\..\..\..\common\src\tx_block_pool_cleanup.c +..\..\..\..\common\src\tx_block_pool_create.c +..\..\..\..\common\src\tx_block_pool_delete.c +..\..\..\..\common\src\tx_block_pool_info_get.c +..\..\..\..\common\src\tx_block_pool_initialize.c +..\..\..\..\common\src\tx_block_pool_performance_info_get.c +..\..\..\..\common\src\tx_block_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_block_pool_prioritize.c +..\..\..\..\common\src\tx_block_release.c +..\..\..\..\common\src\tx_byte_allocate.c +..\..\..\..\common\src\tx_byte_pool_cleanup.c +..\..\..\..\common\src\tx_byte_pool_create.c +..\..\..\..\common\src\tx_byte_pool_delete.c +..\..\..\..\common\src\tx_byte_pool_info_get.c +..\..\..\..\common\src\tx_byte_pool_initialize.c +..\..\..\..\common\src\tx_byte_pool_performance_info_get.c +..\..\..\..\common\src\tx_byte_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_byte_pool_prioritize.c +..\..\..\..\common\src\tx_byte_pool_search.c +..\..\..\..\common\src\tx_byte_release.c +..\..\..\..\common\src\tx_event_flags_cleanup.c +..\..\..\..\common\src\tx_event_flags_create.c +..\..\..\..\common\src\tx_event_flags_delete.c +..\..\..\..\common\src\tx_event_flags_get.c +..\..\..\..\common\src\tx_event_flags_info_get.c +..\..\..\..\common\src\tx_event_flags_initialize.c +..\..\..\..\common\src\tx_event_flags_performance_info_get.c +..\..\..\..\common\src\tx_event_flags_performance_system_info_get.c +..\..\..\..\common\src\tx_event_flags_set.c +..\..\..\..\common\src\tx_event_flags_set_notify.c +..\..\..\..\common\src\tx_initialize_high_level.c +..\..\..\..\common\src\tx_initialize_kernel_enter.c +..\..\..\..\common\src\tx_initialize_kernel_setup.c +..\..\..\..\common\src\tx_mutex_cleanup.c +..\..\..\..\common\src\tx_mutex_create.c +..\..\..\..\common\src\tx_mutex_delete.c +..\..\..\..\common\src\tx_mutex_get.c +..\..\..\..\common\src\tx_mutex_info_get.c +..\..\..\..\common\src\tx_mutex_initialize.c +..\..\..\..\common\src\tx_mutex_performance_info_get.c +..\..\..\..\common\src\tx_mutex_performance_system_info_get.c +..\..\..\..\common\src\tx_mutex_prioritize.c +..\..\..\..\common\src\tx_mutex_priority_change.c +..\..\..\..\common\src\tx_mutex_put.c +..\..\..\..\common\src\tx_queue_cleanup.c +..\..\..\..\common\src\tx_queue_create.c +..\..\..\..\common\src\tx_queue_delete.c +..\..\..\..\common\src\tx_queue_flush.c +..\..\..\..\common\src\tx_queue_front_send.c +..\..\..\..\common\src\tx_queue_info_get.c +..\..\..\..\common\src\tx_queue_initialize.c +..\..\..\..\common\src\tx_queue_performance_info_get.c +..\..\..\..\common\src\tx_queue_performance_system_info_get.c +..\..\..\..\common\src\tx_queue_prioritize.c +..\..\..\..\common\src\tx_queue_receive.c +..\..\..\..\common\src\tx_queue_send.c +..\..\..\..\common\src\tx_queue_send_notify.c +..\..\..\..\common\src\tx_semaphore_ceiling_put.c +..\..\..\..\common\src\tx_semaphore_cleanup.c +..\..\..\..\common\src\tx_semaphore_create.c +..\..\..\..\common\src\tx_semaphore_delete.c +..\..\..\..\common\src\tx_semaphore_get.c +..\..\..\..\common\src\tx_semaphore_info_get.c +..\..\..\..\common\src\tx_semaphore_initialize.c +..\..\..\..\common\src\tx_semaphore_performance_info_get.c +..\..\..\..\common\src\tx_semaphore_performance_system_info_get.c +..\..\..\..\common\src\tx_semaphore_prioritize.c +..\..\..\..\common\src\tx_semaphore_put.c +..\..\..\..\common\src\tx_semaphore_put_notify.c +..\..\..\..\common\src\tx_thread_create.c +..\..\..\..\common\src\tx_thread_delete.c +..\..\..\..\common\src\tx_thread_entry_exit_notify.c +..\..\..\..\common\src\tx_thread_identify.c +..\..\..\..\common\src\tx_thread_info_get.c +..\..\..\..\common\src\tx_thread_initialize.c +..\..\..\..\common\src\tx_thread_performance_info_get.c +..\..\..\..\common\src\tx_thread_performance_system_info_get.c +..\..\..\..\common\src\tx_thread_preemption_change.c +..\..\..\..\common\src\tx_thread_priority_change.c +..\..\..\..\common\src\tx_thread_relinquish.c +..\..\..\..\common\src\tx_thread_reset.c +..\..\..\..\common\src\tx_thread_resume.c +..\..\..\..\common\src\tx_thread_shell_entry.c +..\..\..\..\common\src\tx_thread_sleep.c +..\..\..\..\common\src\tx_thread_stack_analyze.c +..\..\..\..\common\src\tx_thread_stack_error_handler.c +..\..\..\..\common\src\tx_thread_stack_error_notify.c +..\..\..\..\common\src\tx_thread_suspend.c +..\..\..\..\common\src\tx_thread_system_preempt_check.c +..\..\..\..\common\src\tx_thread_system_resume.c +..\..\..\..\common\src\tx_thread_system_suspend.c +..\..\..\..\common\src\tx_thread_terminate.c +..\..\..\..\common\src\tx_thread_time_slice.c +..\..\..\..\common\src\tx_thread_time_slice_change.c +..\..\..\..\common\src\tx_thread_timeout.c +..\..\..\..\common\src\tx_thread_wait_abort.c +..\..\..\..\common\src\tx_time_get.c +..\..\..\..\common\src\tx_time_set.c +..\..\..\..\common\src\tx_timer_activate.c +..\..\..\..\common\src\tx_timer_change.c +..\..\..\..\common\src\tx_timer_create.c +..\..\..\..\common\src\tx_timer_deactivate.c +..\..\..\..\common\src\tx_timer_delete.c +..\..\..\..\common\src\tx_timer_expiration_process.c +..\..\..\..\common\src\tx_timer_info_get.c +..\..\..\..\common\src\tx_timer_initialize.c +..\..\..\..\common\src\tx_timer_performance_info_get.c +..\..\..\..\common\src\tx_timer_performance_system_info_get.c +..\..\..\..\common\src\tx_timer_system_activate.c +..\..\..\..\common\src\tx_timer_system_deactivate.c +..\..\..\..\common\src\tx_timer_thread_entry.c +..\..\..\..\common\src\tx_trace_buffer_full_notify.c +..\..\..\..\common\src\tx_trace_disable.c +..\..\..\..\common\src\tx_trace_enable.c +..\..\..\..\common\src\tx_trace_event_filter.c +..\..\..\..\common\src\tx_trace_event_unfilter.c +..\..\..\..\common\src\tx_trace_initialize.c +..\..\..\..\common\src\tx_trace_interrupt_control.c +..\..\..\..\common\src\tx_trace_isr_enter_insert.c +..\..\..\..\common\src\tx_trace_isr_exit_insert.c +..\..\..\..\common\src\tx_trace_object_register.c +..\..\..\..\common\src\tx_trace_object_unregister.c +..\..\..\..\common\src\tx_trace_user_event_insert.c +..\..\..\..\common\src\txe_block_allocate.c +..\..\..\..\common\src\txe_block_pool_create.c +..\..\..\..\common\src\txe_block_pool_delete.c +..\..\..\..\common\src\txe_block_pool_info_get.c +..\..\..\..\common\src\txe_block_pool_prioritize.c +..\..\..\..\common\src\txe_block_release.c +..\..\..\..\common\src\txe_byte_allocate.c +..\..\..\..\common\src\txe_byte_pool_create.c +..\..\..\..\common\src\txe_byte_pool_delete.c +..\..\..\..\common\src\txe_byte_pool_info_get.c +..\..\..\..\common\src\txe_byte_pool_prioritize.c +..\..\..\..\common\src\txe_byte_release.c +..\..\..\..\common\src\txe_event_flags_create.c +..\..\..\..\common\src\txe_event_flags_delete.c +..\..\..\..\common\src\txe_event_flags_get.c +..\..\..\..\common\src\txe_event_flags_info_get.c +..\..\..\..\common\src\txe_event_flags_set.c +..\..\..\..\common\src\txe_event_flags_set_notify.c +..\..\..\..\common\src\txe_mutex_create.c +..\..\..\..\common\src\txe_mutex_delete.c +..\..\..\..\common\src\txe_mutex_get.c +..\..\..\..\common\src\txe_mutex_info_get.c +..\..\..\..\common\src\txe_mutex_prioritize.c +..\..\..\..\common\src\txe_mutex_put.c +..\..\..\..\common\src\txe_queue_create.c +..\..\..\..\common\src\txe_queue_delete.c +..\..\..\..\common\src\txe_queue_flush.c +..\..\..\..\common\src\txe_queue_front_send.c +..\..\..\..\common\src\txe_queue_info_get.c +..\..\..\..\common\src\txe_queue_prioritize.c +..\..\..\..\common\src\txe_queue_receive.c +..\..\..\..\common\src\txe_queue_send.c +..\..\..\..\common\src\txe_queue_send_notify.c +..\..\..\..\common\src\txe_semaphore_ceiling_put.c +..\..\..\..\common\src\txe_semaphore_create.c +..\..\..\..\common\src\txe_semaphore_delete.c +..\..\..\..\common\src\txe_semaphore_get.c +..\..\..\..\common\src\txe_semaphore_info_get.c +..\..\..\..\common\src\txe_semaphore_prioritize.c +..\..\..\..\common\src\txe_semaphore_put.c +..\..\..\..\common\src\txe_semaphore_put_notify.c +..\..\..\..\common\src\txe_thread_create.c +..\..\..\..\common\src\txe_thread_delete.c +..\..\..\..\common\src\txe_thread_entry_exit_notify.c +..\..\..\..\common\src\txe_thread_info_get.c +..\..\..\..\common\src\txe_thread_preemption_change.c +..\..\..\..\common\src\txe_thread_priority_change.c +..\..\..\..\common\src\txe_thread_relinquish.c +..\..\..\..\common\src\txe_thread_reset.c +..\..\..\..\common\src\txe_thread_resume.c +..\..\..\..\common\src\txe_thread_suspend.c +..\..\..\..\common\src\txe_thread_terminate.c +..\..\..\..\common\src\txe_thread_time_slice_change.c +..\..\..\..\common\src\txe_thread_wait_abort.c +..\..\..\..\common\src\txe_timer_activate.c +..\..\..\..\common\src\txe_timer_change.c +..\..\..\..\common\src\txe_timer_create.c +..\..\..\..\common\src\txe_timer_deactivate.c +..\..\..\..\common\src\txe_timer_delete.c +..\..\..\..\common\src\txe_timer_info_get.c +..\..\..\..\ports_common_green\src\tx_el.c +..\..\..\..\ports_common_green\src\tx_ghs.c +..\..\..\..\ports_common_green\src\tx_ghse.c +..\..\..\..\ports_common_green\src\txr_block_allocate.c +..\..\..\..\ports_common_green\src\txr_block_pool_create.c +..\..\..\..\ports_common_green\src\txr_block_pool_delete.c +..\..\..\..\ports_common_green\src\txr_block_pool_info_get.c +..\..\..\..\ports_common_green\src\txr_block_pool_prioritize.c +..\..\..\..\ports_common_green\src\txr_block_release.c +..\..\..\..\ports_common_green\src\txr_byte_allocate.c +..\..\..\..\ports_common_green\src\txr_byte_pool_create.c +..\..\..\..\ports_common_green\src\txr_byte_pool_delete.c +..\..\..\..\ports_common_green\src\txr_byte_pool_info_get.c +..\..\..\..\ports_common_green\src\txr_byte_pool_prioritize.c +..\..\..\..\ports_common_green\src\txr_byte_release.c +..\..\..\..\ports_common_green\src\txr_event_flags_create.c +..\..\..\..\ports_common_green\src\txr_event_flags_delete.c +..\..\..\..\ports_common_green\src\txr_event_flags_get.c +..\..\..\..\ports_common_green\src\txr_event_flags_info_get.c +..\..\..\..\ports_common_green\src\txr_event_flags_set.c +..\..\..\..\ports_common_green\src\txr_event_flags_set_notify.c +..\..\..\..\ports_common_green\src\txr_ghs.c +..\..\..\..\ports_common_green\src\txr_mutex_create.c +..\..\..\..\ports_common_green\src\txr_mutex_delete.c +..\..\..\..\ports_common_green\src\txr_mutex_get.c +..\..\..\..\ports_common_green\src\txr_mutex_info_get.c +..\..\..\..\ports_common_green\src\txr_mutex_prioritize.c +..\..\..\..\ports_common_green\src\txr_mutex_put.c +..\..\..\..\ports_common_green\src\txr_queue_create.c +..\..\..\..\ports_common_green\src\txr_queue_delete.c +..\..\..\..\ports_common_green\src\txr_queue_flush.c +..\..\..\..\ports_common_green\src\txr_queue_front_send.c +..\..\..\..\ports_common_green\src\txr_queue_info_get.c +..\..\..\..\ports_common_green\src\txr_queue_prioritize.c +..\..\..\..\ports_common_green\src\txr_queue_receive.c +..\..\..\..\ports_common_green\src\txr_queue_send.c +..\..\..\..\ports_common_green\src\txr_queue_send_notify.c +..\..\..\..\ports_common_green\src\txr_semaphore_ceiling_put.c +..\..\..\..\ports_common_green\src\txr_semaphore_create.c +..\..\..\..\ports_common_green\src\txr_semaphore_delete.c +..\..\..\..\ports_common_green\src\txr_semaphore_get.c +..\..\..\..\ports_common_green\src\txr_semaphore_info_get.c +..\..\..\..\ports_common_green\src\txr_semaphore_prioritize.c +..\..\..\..\ports_common_green\src\txr_semaphore_put.c +..\..\..\..\ports_common_green\src\txr_semaphore_put_notify.c +..\..\..\..\ports_common_green\src\txr_thread_create.c +..\..\..\..\ports_common_green\src\txr_thread_delete.c +..\..\..\..\ports_common_green\src\txr_thread_entry_exit_notify.c +..\..\..\..\ports_common_green\src\txr_thread_info_get.c +..\..\..\..\ports_common_green\src\txr_thread_preemption_change.c +..\..\..\..\ports_common_green\src\txr_thread_priority_change.c +..\..\..\..\ports_common_green\src\txr_thread_reset.c +..\..\..\..\ports_common_green\src\txr_thread_resume.c +..\..\..\..\ports_common_green\src\txr_thread_suspend.c +..\..\..\..\ports_common_green\src\txr_thread_terminate.c +..\..\..\..\ports_common_green\src\txr_thread_time_slice_change.c +..\..\..\..\ports_common_green\src\txr_thread_wait_abort.c +..\..\..\..\ports_common_green\src\txr_timer_activate.c +..\..\..\..\ports_common_green\src\txr_timer_change.c +..\..\..\..\ports_common_green\src\txr_timer_create.c +..\..\..\..\ports_common_green\src\txr_timer_deactivate.c +..\..\..\..\ports_common_green\src\txr_timer_delete.c +..\..\..\..\ports_common_green\src\txr_timer_info_get.c diff --git a/ports/cortex_a5/green/example_build/tx_initialize_low_level.arm b/ports/cortex_a5/green/example_build/tx_initialize_low_level.arm new file mode 100644 index 00000000..6ff4d548 --- /dev/null +++ b/ports/cortex_a5/green/example_build/tx_initialize_low_level.arm @@ -0,0 +1,319 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_initialize.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + SVC_MODE = 0xD3 # Disable IRQ/FIQ SVC mode + IRQ_MODE = 0xD2 # Disable IRQ/FIQ IRQ mode + FIQ_MODE = 0xD1 # Disable IRQ/FIQ FIQ mode + SYS_MODE = 0xDF # Disable IRQ/FIQ SYS mode + MODE_MASK = 0x1F # Mode mask + FIQ_STACK_SIZE = 512 # FIQ stack size + IRQ_STACK_SIZE = 1024 # IRQ stack size + SYS_STACK_SIZE = 1024 # SYS stack size + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-A5/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_initialize_low_level(VOID) +{ */ + .globl _tx_initialize_low_level +_tx_initialize_low_level: + + /****** NOTE ****** We must be in SVC MODE at this point. Some monitors + enter this routine in USER mode and require a software interrupt to + change into SVC mode. */ + + /* Save the system stack pointer. */ + /* _tx_thread_system_stack_ptr = (VOID_PTR) (sp); */ + + LDR r1,=_tx_thread_system_stack_ptr # Pickup address of system stack ptr + STR sp, [r1] # Save system stack + + /* Pickup the first available memory address. */ + + LDR r0,=__ghsbegin_free_mem # Pickup free memory address + + /* Setup initial stack pointers for IRQ and FIQ modes. */ + + MRS r12, CPSR # Pickup current CPSR + MOV r1, r0 # Get first available memory +#ifdef TX_ENABLE_IRQ_NESTING + /* Setup the system mode stack for nested interrupt support */ + LDR r2, =SYS_STACK_SIZE # Pickup stack size + BIC r3, r12, MODE_MASK # Clear mode bits + ORR r3, r3, SYS_MODE # Build SYS mode CPSR + MSR CPSR_c, r3 # Enter SYS mode + ADD r1, r1, r2 # Calculate start of SYS stack + SUB r1, r1, 1 # Backup one byte + BIC r1, r1, 7 # Insure 8-byte alignment + MOV sp, r1 # Setup SYS stack pointer +#endif + LDR r2, =FIQ_STACK_SIZE # Pickup stack size + BIC r3, r12, MODE_MASK # Clear mode bits + ORR r3, r3, FIQ_MODE # Build FIQ mode CPSR + MSR CPSR_c, r3 # Enter FIQ mode + ADD r1, r1, r2 # Calculate start of FIQ stack + SUB r1, r1, 1 # Backup one byte + BIC r1, r1, 7 # Insure 8-byte alignment + MOV sp, r1 # Setup FIQ stack pointer + MOV r10, 0 # Clear sl + MOV r11, 0 # Clear fp + LDR r2, =IRQ_STACK_SIZE # Pickup IRQ (system stack size) + BIC r3, r12, MODE_MASK # Clear mode bits + ORR r3, r3, IRQ_MODE # Build IRQ mode CPSR + MSR CPSR_c, r3 # Enter IRQ mode + ADD r1, r1, r2 # Calculate start of IRQ stack + SUB r1, r1, 1 # Backup one byte + BIC r1, r1, 7 # Insure 8-byte alignment + MOV sp, r1 # Setup IRQ stack pointer + MSR CPSR_c, r12 # Restore previous mode + ADD r0, r1, 4 # Adjust the new free memory + + + /* Save the first available memory address. */ + /* _tx_initialize_unused_memory = (VOID_PTR) __ghsbegin_free_mem + [SYS_STACK] + FIQ_STACK + IRQ_STACK; */ + + LDR r2,=_tx_initialize_unused_memory # Pickup unused memory ptr address + STR r0, [r2] # Save first free memory address + + + /* Setup Timer for periodic interrupts. To generate timer interrupts with + the Green Hills simulator, enter the following command in the target + window: timer 9999 irq */ + + /* Done, return to caller. */ + + RET # Return to caller + + .type _tx_initialize_low_level,$function + .size _tx_initialize_low_level,.-_tx_initialize_low_level +/* } */ + + +/* Define shells for each of the interrupt vectors. */ + + .globl __tx_undefined +__tx_undefined: + B __tx_undefined # Undefined handler + + .type __tx_undefined,$function + .size __tx_undefined,.-__tx_undefined + + .globl __tx_swi_interrupt +__tx_swi_interrupt: + B __tx_swi_interrupt # Software interrupt handler + + .type __tx_swi_interrupt,$function + .size __tx_swi_interrupt,.-__tx_swi_interrupt + + .globl __tx_prefetch_handler +__tx_prefetch_handler: + B __tx_prefetch_handler # Prefetch exception handler + + .type __tx_prefetch_handler,$function + .size __tx_prefetch_handler,.-__tx_prefetch_handler + + .globl __tx_abort_handler +__tx_abort_handler: + B __tx_abort_handler # Abort exception handler + + .type __tx_abort_handler,$function + .size __tx_abort_handler,.-__tx_abort_handler + + .globl __tx_reserved_handler +__tx_reserved_handler: + B __tx_reserved_handler # Reserved exception handler + + .type __tx_reserved_handler,$function + .size __tx_reserved_handler,.-__tx_reserved_handler + + .globl __tx_irq_handler + .globl __tx_irq_processing_return +__tx_irq_handler: + + /* Jump to context save to save system context. */ + B _tx_thread_context_save + + .type __tx_irq_handler,$function + .size __tx_irq_handler,.-__tx_irq_handler + +__tx_irq_processing_return: + + /* At this point execution is still in the IRQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. */ + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 0 # Build interrupt code + BL _tx_el_interrupt # Call interrupt event logging +#endif + + /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start + from IRQ mode with interrupts disabled. This routine switches to the + system mode and returns with IRQ interrupts enabled. + + NOTE: It is very important to ensure all IRQ interrupts are cleared + prior to enabling nested IRQ interrupts. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_start +#endif + + + /* For debug purpose, execute the timer interrupt processing here. In + a real system, some kind of status indication would have to be checked + before the timer interrupt handler could be called. */ + BL _tx_timer_interrupt # Timer interrupt handler + + /* Application IRQ handlers can be called here! */ + + /* If interrupt nesting was started earlier, the end of interrupt nesting + service must be called before returning to _tx_thread_context_restore. + This routine returns in processing in IRQ mode with interrupts disabled. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_end +#endif + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 0 # Build interrupt code + BL _tx_el_interrupt_end # Call interrupt event logging +#endif + + /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + .type __tx_irq_processing_return,$function + .size __tx_irq_processing_return,.-__tx_irq_processing_return + +#ifdef TX_ENABLE_FIQ_SUPPORT + + .globl __tx_fiq_handler + .globl __tx_fiq_processing_return +__tx_fiq_handler: + /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save + + .type __tx_fiq_handler,$function + .size __tx_fiq_handler,.-__tx_fiq_handler + +__tx_fiq_processing_return: + + /* At this point execution is still in the FIQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. */ + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 1 # Build interrupt code + BL _tx_el_interrupt # Call interrupt event logging +#endif + + /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start + from FIQ mode with interrupts disabled. This routine switches to the + system mode and returns with FIQ interrupts enabled. + + NOTE: It is very important to ensure all FIQ interrupts are cleared + prior to enabling nested FIQ interrupts. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_start +#endif + + /* Application FIQ handlers can be called here! */ + + /* If interrupt nesting was started earlier, the end of interrupt nesting + service must be called before returning to _tx_thread_fiq_context_restore. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_end +#endif + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 1 # Build interrupt code + BL _tx_el_interrupt_end # Call interrupt event logging +#endif + + /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + .type __tx_fiq_processing_return,$function + .size __tx_fiq_processing_return,.-__tx_fiq_processing_return + +#else + .globl __tx_fiq_handler +__tx_fiq_handler: + B __tx_fiq_handler # FIQ interrupt handler + + .type __tx_fiq_handler,$function + .size __tx_fiq_handler,.-__tx_fiq_handler +#endif + + /* Reference build options and version ID to ensure they come in. */ + +BUILD_OPTIONS: + .data.w _tx_build_options +VERSION_ID: + .data.w _tx_version_id diff --git a/ports/cortex_a5/green/example_build/txe.gpj b/ports/cortex_a5/green/example_build/txe.gpj new file mode 100644 index 00000000..662bcd16 --- /dev/null +++ b/ports/cortex_a5/green/example_build/txe.gpj @@ -0,0 +1,284 @@ +#!gbuild +[Library] + -DTX_ENABLE_EVENT_LOGGING + -I../../../../common/inc + -I../../../../ports_common_green/inc + -I../inc +..\..\..\..\common\inc\tx_api.h +..\..\..\..\common\inc\tx_block_pool.h +..\..\..\..\common\inc\tx_byte_pool.h +..\..\..\..\common\inc\tx_event_flags.h +..\..\..\..\common\inc\tx_initialize.h +..\..\..\..\common\inc\tx_mutex.h +..\..\..\..\common\inc\tx_queue.h +..\..\..\..\common\inc\tx_semaphore.h +..\..\..\..\common\inc\tx_thread.h +..\..\..\..\common\inc\tx_timer.h +..\..\..\..\common\inc\tx_trace.h +..\..\..\..\common\inc\tx_user_sample.h +..\inc\tx_port.h +..\..\..\..\ports_common_green\inc\tx_el.h +..\..\..\..\ports_common_green\inc\tx_ghs.h +..\src\tx_thread_context_restore.arm +..\src\tx_thread_context_save.arm +..\src\tx_thread_fiq_context_restore.arm +..\src\tx_thread_fiq_context_save.arm +..\src\tx_thread_fiq_nesting_end.arm +..\src\tx_thread_fiq_nesting_start.arm +..\src\tx_thread_interrupt_control.arm +..\src\tx_thread_interrupt_disable.arm +..\src\tx_thread_interrupt_restore.arm +..\src\tx_thread_irq_nesting_end.arm +..\src\tx_thread_irq_nesting_start.arm +..\src\tx_thread_schedule.arm +..\src\tx_thread_stack_build.arm +..\src\tx_thread_system_return.arm +..\src\tx_thread_vectored_context_save.arm +..\src\tx_timer_interrupt.arm +..\..\..\..\common\src\tx_block_allocate.c +..\..\..\..\common\src\tx_block_pool_cleanup.c +..\..\..\..\common\src\tx_block_pool_create.c +..\..\..\..\common\src\tx_block_pool_delete.c +..\..\..\..\common\src\tx_block_pool_info_get.c +..\..\..\..\common\src\tx_block_pool_initialize.c +..\..\..\..\common\src\tx_block_pool_performance_info_get.c +..\..\..\..\common\src\tx_block_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_block_pool_prioritize.c +..\..\..\..\common\src\tx_block_release.c +..\..\..\..\common\src\tx_byte_allocate.c +..\..\..\..\common\src\tx_byte_pool_cleanup.c +..\..\..\..\common\src\tx_byte_pool_create.c +..\..\..\..\common\src\tx_byte_pool_delete.c +..\..\..\..\common\src\tx_byte_pool_info_get.c +..\..\..\..\common\src\tx_byte_pool_initialize.c +..\..\..\..\common\src\tx_byte_pool_performance_info_get.c +..\..\..\..\common\src\tx_byte_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_byte_pool_prioritize.c +..\..\..\..\common\src\tx_byte_pool_search.c +..\..\..\..\common\src\tx_byte_release.c +..\..\..\..\common\src\tx_event_flags_cleanup.c +..\..\..\..\common\src\tx_event_flags_create.c +..\..\..\..\common\src\tx_event_flags_delete.c +..\..\..\..\common\src\tx_event_flags_get.c +..\..\..\..\common\src\tx_event_flags_info_get.c +..\..\..\..\common\src\tx_event_flags_initialize.c +..\..\..\..\common\src\tx_event_flags_performance_info_get.c +..\..\..\..\common\src\tx_event_flags_performance_system_info_get.c +..\..\..\..\common\src\tx_event_flags_set.c +..\..\..\..\common\src\tx_event_flags_set_notify.c +..\..\..\..\common\src\tx_initialize_high_level.c +..\..\..\..\common\src\tx_initialize_kernel_enter.c +..\..\..\..\common\src\tx_initialize_kernel_setup.c +..\..\..\..\common\src\tx_mutex_cleanup.c +..\..\..\..\common\src\tx_mutex_create.c +..\..\..\..\common\src\tx_mutex_delete.c +..\..\..\..\common\src\tx_mutex_get.c +..\..\..\..\common\src\tx_mutex_info_get.c +..\..\..\..\common\src\tx_mutex_initialize.c +..\..\..\..\common\src\tx_mutex_performance_info_get.c +..\..\..\..\common\src\tx_mutex_performance_system_info_get.c +..\..\..\..\common\src\tx_mutex_prioritize.c +..\..\..\..\common\src\tx_mutex_priority_change.c +..\..\..\..\common\src\tx_mutex_put.c +..\..\..\..\common\src\tx_queue_cleanup.c +..\..\..\..\common\src\tx_queue_create.c +..\..\..\..\common\src\tx_queue_delete.c +..\..\..\..\common\src\tx_queue_flush.c +..\..\..\..\common\src\tx_queue_front_send.c +..\..\..\..\common\src\tx_queue_info_get.c +..\..\..\..\common\src\tx_queue_initialize.c +..\..\..\..\common\src\tx_queue_performance_info_get.c +..\..\..\..\common\src\tx_queue_performance_system_info_get.c +..\..\..\..\common\src\tx_queue_prioritize.c +..\..\..\..\common\src\tx_queue_receive.c +..\..\..\..\common\src\tx_queue_send.c +..\..\..\..\common\src\tx_queue_send_notify.c +..\..\..\..\common\src\tx_semaphore_ceiling_put.c +..\..\..\..\common\src\tx_semaphore_cleanup.c +..\..\..\..\common\src\tx_semaphore_create.c +..\..\..\..\common\src\tx_semaphore_delete.c +..\..\..\..\common\src\tx_semaphore_get.c +..\..\..\..\common\src\tx_semaphore_info_get.c +..\..\..\..\common\src\tx_semaphore_initialize.c +..\..\..\..\common\src\tx_semaphore_performance_info_get.c +..\..\..\..\common\src\tx_semaphore_performance_system_info_get.c +..\..\..\..\common\src\tx_semaphore_prioritize.c +..\..\..\..\common\src\tx_semaphore_put.c +..\..\..\..\common\src\tx_semaphore_put_notify.c +..\..\..\..\common\src\tx_thread_create.c +..\..\..\..\common\src\tx_thread_delete.c +..\..\..\..\common\src\tx_thread_entry_exit_notify.c +..\..\..\..\common\src\tx_thread_identify.c +..\..\..\..\common\src\tx_thread_info_get.c +..\..\..\..\common\src\tx_thread_initialize.c +..\..\..\..\common\src\tx_thread_performance_info_get.c +..\..\..\..\common\src\tx_thread_performance_system_info_get.c +..\..\..\..\common\src\tx_thread_preemption_change.c +..\..\..\..\common\src\tx_thread_priority_change.c +..\..\..\..\common\src\tx_thread_relinquish.c +..\..\..\..\common\src\tx_thread_reset.c +..\..\..\..\common\src\tx_thread_resume.c +..\..\..\..\common\src\tx_thread_shell_entry.c +..\..\..\..\common\src\tx_thread_sleep.c +..\..\..\..\common\src\tx_thread_stack_analyze.c +..\..\..\..\common\src\tx_thread_stack_error_handler.c +..\..\..\..\common\src\tx_thread_stack_error_notify.c +..\..\..\..\common\src\tx_thread_suspend.c +..\..\..\..\common\src\tx_thread_system_preempt_check.c +..\..\..\..\common\src\tx_thread_system_resume.c +..\..\..\..\common\src\tx_thread_system_suspend.c +..\..\..\..\common\src\tx_thread_terminate.c +..\..\..\..\common\src\tx_thread_time_slice.c +..\..\..\..\common\src\tx_thread_time_slice_change.c +..\..\..\..\common\src\tx_thread_timeout.c +..\..\..\..\common\src\tx_thread_wait_abort.c +..\..\..\..\common\src\tx_time_get.c +..\..\..\..\common\src\tx_time_set.c +..\..\..\..\common\src\tx_timer_activate.c +..\..\..\..\common\src\tx_timer_change.c +..\..\..\..\common\src\tx_timer_create.c +..\..\..\..\common\src\tx_timer_deactivate.c +..\..\..\..\common\src\tx_timer_delete.c +..\..\..\..\common\src\tx_timer_expiration_process.c +..\..\..\..\common\src\tx_timer_info_get.c +..\..\..\..\common\src\tx_timer_initialize.c +..\..\..\..\common\src\tx_timer_performance_info_get.c +..\..\..\..\common\src\tx_timer_performance_system_info_get.c +..\..\..\..\common\src\tx_timer_system_activate.c +..\..\..\..\common\src\tx_timer_system_deactivate.c +..\..\..\..\common\src\tx_timer_thread_entry.c +..\..\..\..\common\src\tx_trace_buffer_full_notify.c +..\..\..\..\common\src\tx_trace_disable.c +..\..\..\..\common\src\tx_trace_enable.c +..\..\..\..\common\src\tx_trace_event_filter.c +..\..\..\..\common\src\tx_trace_event_unfilter.c +..\..\..\..\common\src\tx_trace_initialize.c +..\..\..\..\common\src\tx_trace_interrupt_control.c +..\..\..\..\common\src\tx_trace_isr_enter_insert.c +..\..\..\..\common\src\tx_trace_isr_exit_insert.c +..\..\..\..\common\src\tx_trace_object_register.c +..\..\..\..\common\src\tx_trace_object_unregister.c +..\..\..\..\common\src\tx_trace_user_event_insert.c +..\..\..\..\common\src\txe_block_allocate.c +..\..\..\..\common\src\txe_block_pool_create.c +..\..\..\..\common\src\txe_block_pool_delete.c +..\..\..\..\common\src\txe_block_pool_info_get.c +..\..\..\..\common\src\txe_block_pool_prioritize.c +..\..\..\..\common\src\txe_block_release.c +..\..\..\..\common\src\txe_byte_allocate.c +..\..\..\..\common\src\txe_byte_pool_create.c +..\..\..\..\common\src\txe_byte_pool_delete.c +..\..\..\..\common\src\txe_byte_pool_info_get.c +..\..\..\..\common\src\txe_byte_pool_prioritize.c +..\..\..\..\common\src\txe_byte_release.c +..\..\..\..\common\src\txe_event_flags_create.c +..\..\..\..\common\src\txe_event_flags_delete.c +..\..\..\..\common\src\txe_event_flags_get.c +..\..\..\..\common\src\txe_event_flags_info_get.c +..\..\..\..\common\src\txe_event_flags_set.c +..\..\..\..\common\src\txe_event_flags_set_notify.c +..\..\..\..\common\src\txe_mutex_create.c +..\..\..\..\common\src\txe_mutex_delete.c +..\..\..\..\common\src\txe_mutex_get.c +..\..\..\..\common\src\txe_mutex_info_get.c +..\..\..\..\common\src\txe_mutex_prioritize.c +..\..\..\..\common\src\txe_mutex_put.c +..\..\..\..\common\src\txe_queue_create.c +..\..\..\..\common\src\txe_queue_delete.c +..\..\..\..\common\src\txe_queue_flush.c +..\..\..\..\common\src\txe_queue_front_send.c +..\..\..\..\common\src\txe_queue_info_get.c +..\..\..\..\common\src\txe_queue_prioritize.c +..\..\..\..\common\src\txe_queue_receive.c +..\..\..\..\common\src\txe_queue_send.c +..\..\..\..\common\src\txe_queue_send_notify.c +..\..\..\..\common\src\txe_semaphore_ceiling_put.c +..\..\..\..\common\src\txe_semaphore_create.c +..\..\..\..\common\src\txe_semaphore_delete.c +..\..\..\..\common\src\txe_semaphore_get.c +..\..\..\..\common\src\txe_semaphore_info_get.c +..\..\..\..\common\src\txe_semaphore_prioritize.c +..\..\..\..\common\src\txe_semaphore_put.c +..\..\..\..\common\src\txe_semaphore_put_notify.c +..\..\..\..\common\src\txe_thread_create.c +..\..\..\..\common\src\txe_thread_delete.c +..\..\..\..\common\src\txe_thread_entry_exit_notify.c +..\..\..\..\common\src\txe_thread_info_get.c +..\..\..\..\common\src\txe_thread_preemption_change.c +..\..\..\..\common\src\txe_thread_priority_change.c +..\..\..\..\common\src\txe_thread_relinquish.c +..\..\..\..\common\src\txe_thread_reset.c +..\..\..\..\common\src\txe_thread_resume.c +..\..\..\..\common\src\txe_thread_suspend.c +..\..\..\..\common\src\txe_thread_terminate.c +..\..\..\..\common\src\txe_thread_time_slice_change.c +..\..\..\..\common\src\txe_thread_wait_abort.c +..\..\..\..\common\src\txe_timer_activate.c +..\..\..\..\common\src\txe_timer_change.c +..\..\..\..\common\src\txe_timer_create.c +..\..\..\..\common\src\txe_timer_deactivate.c +..\..\..\..\common\src\txe_timer_delete.c +..\..\..\..\common\src\txe_timer_info_get.c +..\..\..\..\ports_common_green\src\tx_el.c +..\..\..\..\ports_common_green\src\tx_ghs.c +..\..\..\..\ports_common_green\src\tx_ghse.c +..\..\..\..\ports_common_green\src\txr_block_allocate.c +..\..\..\..\ports_common_green\src\txr_block_pool_create.c +..\..\..\..\ports_common_green\src\txr_block_pool_delete.c +..\..\..\..\ports_common_green\src\txr_block_pool_info_get.c +..\..\..\..\ports_common_green\src\txr_block_pool_prioritize.c +..\..\..\..\ports_common_green\src\txr_block_release.c +..\..\..\..\ports_common_green\src\txr_byte_allocate.c +..\..\..\..\ports_common_green\src\txr_byte_pool_create.c +..\..\..\..\ports_common_green\src\txr_byte_pool_delete.c +..\..\..\..\ports_common_green\src\txr_byte_pool_info_get.c +..\..\..\..\ports_common_green\src\txr_byte_pool_prioritize.c +..\..\..\..\ports_common_green\src\txr_byte_release.c +..\..\..\..\ports_common_green\src\txr_event_flags_create.c +..\..\..\..\ports_common_green\src\txr_event_flags_delete.c +..\..\..\..\ports_common_green\src\txr_event_flags_get.c +..\..\..\..\ports_common_green\src\txr_event_flags_info_get.c +..\..\..\..\ports_common_green\src\txr_event_flags_set.c +..\..\..\..\ports_common_green\src\txr_event_flags_set_notify.c +..\..\..\..\ports_common_green\src\txr_ghs.c +..\..\..\..\ports_common_green\src\txr_mutex_create.c +..\..\..\..\ports_common_green\src\txr_mutex_delete.c +..\..\..\..\ports_common_green\src\txr_mutex_get.c +..\..\..\..\ports_common_green\src\txr_mutex_info_get.c +..\..\..\..\ports_common_green\src\txr_mutex_prioritize.c +..\..\..\..\ports_common_green\src\txr_mutex_put.c +..\..\..\..\ports_common_green\src\txr_queue_create.c +..\..\..\..\ports_common_green\src\txr_queue_delete.c +..\..\..\..\ports_common_green\src\txr_queue_flush.c +..\..\..\..\ports_common_green\src\txr_queue_front_send.c +..\..\..\..\ports_common_green\src\txr_queue_info_get.c +..\..\..\..\ports_common_green\src\txr_queue_prioritize.c +..\..\..\..\ports_common_green\src\txr_queue_receive.c +..\..\..\..\ports_common_green\src\txr_queue_send.c +..\..\..\..\ports_common_green\src\txr_queue_send_notify.c +..\..\..\..\ports_common_green\src\txr_semaphore_ceiling_put.c +..\..\..\..\ports_common_green\src\txr_semaphore_create.c +..\..\..\..\ports_common_green\src\txr_semaphore_delete.c +..\..\..\..\ports_common_green\src\txr_semaphore_get.c +..\..\..\..\ports_common_green\src\txr_semaphore_info_get.c +..\..\..\..\ports_common_green\src\txr_semaphore_prioritize.c +..\..\..\..\ports_common_green\src\txr_semaphore_put.c +..\..\..\..\ports_common_green\src\txr_semaphore_put_notify.c +..\..\..\..\ports_common_green\src\txr_thread_create.c +..\..\..\..\ports_common_green\src\txr_thread_delete.c +..\..\..\..\ports_common_green\src\txr_thread_entry_exit_notify.c +..\..\..\..\ports_common_green\src\txr_thread_info_get.c +..\..\..\..\ports_common_green\src\txr_thread_preemption_change.c +..\..\..\..\ports_common_green\src\txr_thread_priority_change.c +..\..\..\..\ports_common_green\src\txr_thread_reset.c +..\..\..\..\ports_common_green\src\txr_thread_resume.c +..\..\..\..\ports_common_green\src\txr_thread_suspend.c +..\..\..\..\ports_common_green\src\txr_thread_terminate.c +..\..\..\..\ports_common_green\src\txr_thread_time_slice_change.c +..\..\..\..\ports_common_green\src\txr_thread_wait_abort.c +..\..\..\..\ports_common_green\src\txr_timer_activate.c +..\..\..\..\ports_common_green\src\txr_timer_change.c +..\..\..\..\ports_common_green\src\txr_timer_create.c +..\..\..\..\ports_common_green\src\txr_timer_deactivate.c +..\..\..\..\ports_common_green\src\txr_timer_delete.c +..\..\..\..\ports_common_green\src\txr_timer_info_get.c diff --git a/ports/cortex_a5/green/inc/tx_port.h b/ports/cortex_a5/green/inc/tx_port.h new file mode 100644 index 00000000..037a85f0 --- /dev/null +++ b/ports/cortex_a5/green/inc/tx_port.h @@ -0,0 +1,402 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A5/Green Hills */ +/* 6.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include +#include +#include "tx_ghs.h" + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define constants for Green Hills EventAnalyzer. */ + +/* Define the number of ticks per second. This informs the EventAnalyzer what the timestamps + represent. By default, this is set to 1,000,000 i.e., one tick every microsecond. */ + +#define TX_EL_TICKS_PER_SECOND 1000000 + +/* Define the method of how to get the upper and lower 32-bits of the time stamp. By default, simply + simulate the time-stamp source with a counter. */ + +#define read_tbu() _tx_el_time_base_upper +#define read_tbl() ++_tx_el_time_base_lower + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ + VOID * tx_thread_eh_globals; \ + int Errno; /* errno. */ \ + char * strtok_saved_pos; /* strtok() position. */ +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + +#if (__GHS_VERSION_NUMBER >= 500) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) \ + { \ + extern void __tx_cpp_exception_init(TX_THREAD *thread_ptr); \ + __tx_cpp_exception_init(thread_ptr); \ + } +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) \ + { \ + #pragma weak __cpp_exception_init \ + extern void __cpp_exception_init(void **); \ + static void (*const cpp_init_funcp)(void **) = __cpp_exception_init; \ + if (cpp_init_funcp) \ + __cpp_exception_init(&(thread_ptr -> tx_thread_eh_globals)); \ + } +#endif + +#if (__GHS_VERSION_NUMBER >= 500) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) \ + { \ + extern void __tx_cpp_exception_cleanup(TX_THREAD *thread_ptr); \ + __tx_cpp_exception_cleanup(thread_ptr); \ + } +#else +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) \ + { \ + #pragma weak __cpp_exception_cleanup \ + extern void __cpp_exception_cleanup(void **); \ + static void (*const cpp_cleanup_funcp)(void **) = \ + __cpp_exception_cleanup; \ + if (cpp_cleanup_funcp) \ + __cpp_exception_cleanup(&(thread_ptr -> tx_thread_eh_globals)); \ + } +#endif + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + b = __CLZ32(m); \ + b = 31 - b; + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#if defined(__THUMB) + +unsigned int _tx_thread_interrupt_disable(void); +void _tx_thread_interrupt_restore(unsigned int new_posture); + +#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); + +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; + +#if defined(__GHS_VERSION_NUMBER) && (__GHS_VERSION_NUMBER >= 350) + +/* Define ThreadX interrupt lockout and restore macros using + compiler built-in functions if using Green Hills ARM compiler + version 3.5 or later. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_DISABLE interrupt_save = __GETSR(); \ + __SETSR(interrupt_save | 0xC0); + +#define TX_RESTORE __SETSR(interrupt_save); +#else +#define TX_DISABLE interrupt_save = __GETSR(); \ + __SETSR(interrupt_save | 0x80); + +#define TX_RESTORE __SETSR(interrupt_save); +#endif + +#else + +/* Define ThreadX interrupt lockout and restore macros using + asm macros if using Green Hills ARM compiler earlier than + version 3.5. */ + +asm int disable_ints(void) +{ +% + MRS r0,CPSR +#ifdef TX_BEFORE_ARMV6 +#ifdef TX_ENABLE_FIQ_SUPPORT + ORR r1,r0,0xC0 +#else + ORR r1,r0,0x80 +#endif + MSR CPSR_c,r1 +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if +#else + CPSID i +#endif +#endif +%error +} + +asm void restore_ints(int a) +{ +%reg a + MSR CPSR_c,a +%mem a + LDR r0,a + MSR CPSR_c,r0 +%error +} + +#define TX_DISABLE interrupt_save = disable_ints(); + +#define TX_RESTORE restore_ints(interrupt_save); +#endif +#endif + + +/* Define VFP extension for the Cortex-A8. Each is assumed to be called in the context of the executing + thread. */ + +void tx_thread_vfp_enable(void); +void tx_thread_vfp_disable(void); + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5/Green Hills Version 6.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + diff --git a/ports/cortex_a5/green/readme_threadx.txt b/ports/cortex_a5/green/readme_threadx.txt new file mode 100644 index 00000000..58eb9de0 --- /dev/null +++ b/ports/cortex_a5/green/readme_threadx.txt @@ -0,0 +1,527 @@ + Microsoft's Azure RTOS ThreadX for Cortex-A5 + + Using the Green Hills Software Tools + +1. Open the ThreadX Project Workspace + +In order to build the ThreadX library and the ThreadX demonstration first load +the Azure RTOS Workspace azure_rtos_workspace.gpj, which is located inside the +"example_build" directory. + + +2. Building the ThreadX run-time Library + +Building the ThreadX library is easy; simply select the MULTI project file +tx.gpj and then select the build button. You should now observe the +compilation and assembly of the ThreadX library. This project build produces +the ThreadX library file tx.a. + + +3. Demonstration System + +The ThreadX demonstration is designed to execute under the MULTI environment +on the Green Hills Cortex-A5 simulator. The instructions that follow describe +how to get the ThreadX evaluation running under the MULTI Cortex-A5 simulation +environment. + +Building the demonstration is easy; simply select the MULTI project file +sample_threadx.gpj. At this point, select the "Project Build" button and observe +the compilation, assembly, and linkage of the ThreadX demonstration application. + +After the demonstration is built, invoke the MULTI ARM simulator by selecting +the simulator connection from within the sample_threadx.con connection file. +Once connected to the simulator, select the "Debug" button. You should now +observe the main function of sample_threadx.c. + +At this point, you should setup a simulated timer interrupt for ThreadX +by entering "timer 9999 irq" in the "target" window of the debugger. + +You are now ready to execute the ThreadX demonstration system. Select +breakpoints and data watches to observe the execution of the sample_threadx.c +application. + + +4. EventAnalyzer Demonstration + +To build a demonstration system that also logs events for the MULTI EventAnalyzer, +perform the same steps as the regular demo, except build the ThreadX library with +txe.gpj file and use the sample_threadx_el.gpj build file to build the demonstration. +The resulting image will log all system events, which can then be displayed by the +MULTI EventAnalyzer. + + +5. System Initialization + +The system entry point using the Green Hills tools is at the label _start. +This is defined within the crt0.arm file supplied by Green Hills. In addition, +this is where all static and global preset C variable initialization +processing is called from. + +After the Green Hills startup function returns, ThreadX initialization is +called. The main initialization function is _tx_initialize_low_level and +is located in the file tx_initialize_low_level.arm. This function is responsible +for setting up various system data structures, interrupt vectors, and the +periodic timer interrupt source of ThreadX. + +In addition, _tx_initialize_low_level determines where the first available +RAM memory address is located. This address is supplied to tx_application_define. + +By default, the first available RAM memory address is assumed to start at the +beginning of the ThreadX section .free_mem. If changes are made to the +sample_threadx.ld file, the .free_mem section should remain the last allocated +section in the main RAM area. The starting address of this section is passed +to tx_application_define. + + +6. User defines + +The following defines and their associated action are as follows: + + Define Meaning + + TX_ENABLE_IRQ_NESTING If defined, this brings in special IRQ + interrupt nesting logic into the ThreadX + library. This define should be applied + to the entire ThreadX library. + + TX_ENABLE_FIQ_NESTING If defined, this brings in special FIQ + interrupt nesting logic into the ThreadX + library. This define should be applied + to the entire ThreadX library and the + define TX_ENABLE_FIQ_SUPPORT should also + be defined. + + TX_ENABLE_FIQ_SUPPORT If defined, this brings in FIQ context + save and restore logic necessary for + applications to call ThreadX services from + FIQ interrupt handlers. This define + should be applied to the entire ThreadX + library. + + + TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, + this define causes basic ThreadX error + checking to be disabled. Please see + Chapter 4 in the "ThreadX User Guide" + for more details. + + TX_ENABLE_EVENT_LOGGING This define enables event logging for any + or all of the ThreadX source code. If this + option is used anywhere, the tx_initialize_high_level.c + file must be compiled with it as well, since this + is where the event log is initialized. + + TX_NO_EVENT_INFO This is a sub-option for event logging. + If this is enabled, only basic information + is saved in the log. + + TX_ENABLE_EVENT_FILTERS This is also a sub-option for event-logging. + If this is enabled, run-time filtering logic + is added to the event logging code. + + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By + default, this value is set to 32 priority levels. + + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found + in tx_port.h. + + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default + value is port-specific and is found in tx_port.h. + + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined + in tx_port.h. + + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. + By default, this option is not defined. + + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. + By default, this option is not defined. + + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is + not defined. + + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. + By default, this option is not defined. + + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. + By default, this option is not defined. + + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. + By default, this option is not defined. + + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size + and improves performance. + + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is + not defined. + + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is + not defined. + + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option + is not defined. + + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is + not defined. + + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is + not defined. + + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is + not defined. + + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is + not defined. + + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is + not defined. + + + +7. Register Usage and Stack Frames + +The Green Hills compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) +are scratch registers for each function. All other registers used by a C +function must be preserved by the function. ThreadX takes advantage of this +in situations where a context switch happens as a result of making a ThreadX +service call (which is itself a C function). In such cases, the saved +context of a thread is only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 CPSR CPSR + 0x08 r0 (a1) r4 (v1) + 0x0C r1 (a2) r5 (v2) + 0x10 r2 (a3) r6 (v3) + 0x14 r3 (a4) r7 (v4) + 0x18 r4 (v1) r8 (v5) + 0x1C r5 (v2) r9 (v6) + 0x20 r6 (v3) r10 (v7) + 0x24 r7 (v4) r11 (fp) + 0x28 r8 (v5) r14 (lr) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) + 0x3C r14 (lr) + 0x40 PC + + +8. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make ThreadX run faster, you can change the tx.gpj project +to disable debug information and enable the desired optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined before tx_api.h is included. + + +9. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-A5 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +9.1 Vector Area + +The Cortex-A5 vectors start at address zero. The demonstration system reset.arm +file contains the reset section (which contains all the ARM vectors) and is +typically loaded at address zero. On actual hardware platforms, this section +might have to be copied to address 0. + +9.2 IRQ ISRs + +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested +IRQ interrupts. The following sub-sections define the IRQ capabilities. + + +9.2.1 Standard IRQ ISRs + +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +is the default IRQ handler defined in tx_initialize_low_level.arm: + + + .globl __tx_irq_handler + .globl __tx_irq_processing_return +__tx_irq_handler: + + /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return: + + /* At this point execution is still in the IRQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. Note + that IRQ interrupts are still disabled upon return from the context + save function. */ + + /* Application ISR call(s) go here! */ + + /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +9.2.2 Vectored IRQ ISRs + +The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified +by the particular implementation. The following is an example IRQ handler defined in +tx_initialize_low_level.arm: + + .globl __tx_irq_example_handler +__tx_irq_example_handler: + + /* Call context save to save system context. */ + + STMDB sp!, {r0-r3} # Save some scratch registers + MRS r0, SPSR # Pickup saved SPSR + SUB lr, lr, #4 # Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} # Store other scratch registers + BL _tx_thread_vectored_context_save # Call the vectored IRQ context save + + /* At this point execution is still in the IRQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. Note + that IRQ interrupts are still disabled upon return from the context + save function. */ + + /* Application ISR call goes here! */ + + /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +9.2.3 Nested IRQ Support + +By default, nested IRQ interrupt support is not enabled. To enable nested +IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING +defined. With this defined, two new IRQ interrupt management services are +available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. +These function should be called between the IRQ context save and restore +calls. + +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +by switching from IRQ mode to SYS mode and enabling IRQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.arm. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables nesting +by disabling IRQ interrupts and switching back to IRQ mode in preparation for +the IRQ context restore service. + +The following is an example of enabling IRQ nested interrupts in the +typical IRQ handler: + + .globl __tx_irq_handler + .globl __tx_irq_processing_return +__tx_irq_handler: + + /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return: + + /* Enable nested IRQ interrupts. NOTE: Since this service returns + with IRQ interrupts enabled, all IRQ interrupt sources must be + cleared prior to calling this service. */ + BL _tx_thread_irq_nesting_start + + /* Application ISR call(s) go here! */ + + /* Disable nested IRQ interrupts. The mode is switched back to + IRQ mode and IRQ interrupts are disable upon return. */ + BL _tx_thread_irq_nesting_end + + /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +9.3 FIQ Interrupts + +By default, Cortex-A5 FIQ interrupts are left completely enabled by ThreadX. +Of course, this means that the application is fully responsible for +saving/restoring any registers used in the FIQ ISR processing. In addition, +no ThreadX service calls are allowed from the default FIQ ISRs. The default +FIQ interrupt shell is located in tx_initialize_low_level.arm. + +9.3.1 Managed FIQ Interrupts + +Full ThreadX management of FIQ interrupts is provided if the ThreadX sources +are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built +this way, the FIQ interrupt handlers are very similar to the IRQ interrupt +handlers defined previously. The following is default FIQ handler +defined in tx_initialize_low_level.arm: + + + .globl __tx_fiq_handler + .globl __tx_fiq_processing_return +__tx_fiq_handler: + + /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: + + /* At this point execution is still in the FIQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. */ + + /* Application FIQ handlers can be called here! */ + + /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +9.3.1.1 Nested FIQ Support + +By default, nested FIQ interrupt support is not enabled. To enable nested +FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING +defined. With this defined, two new FIQ interrupt management services are +available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. +These function should be called between the FIQ context save and restore +calls. + +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +by switching from FIQ mode to SYS mode and enabling FIQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.arm. When nested FIQ interrupts are no longer +required, calling the _tx_thread_fiq_nesting_end service disables nesting by +disabling FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +context restore service. + +The following is an example of enabling FIQ nested interrupts in the +typical FIQ handler: + + + .globl __tx_fiq_handler + .globl __tx_fiq_processing_return +__tx_fiq_handler: + + /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: + + /* At this point execution is still in the FIQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. */ + + /* Enable nested FIQ interrupts. NOTE: Since this service returns + with FIQ interrupts enabled, all FIQ interrupt sources must be + cleared prior to calling this service. */ + BL _tx_thread_fiq_nesting_start + + /* Application FIQ handlers can be called here! */ + + /* Disable nested FIQ interrupts. The mode is switched back to + FIQ mode and FIQ interrupts are disable upon return. */ + BL _tx_thread_fiq_nesting_end + + /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + + +10. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional. However, all other +ThreadX services are operational without a periodic timer source. + +To add the timer interrupt processing, simply make a call to +_tx_timer_interrupt in the IRQ processing. An example of this can be +found in the file tx_initialize_low_level.arm. + + +11. Thumb/Cortex-A5 Mixed Mode + +By default, ThreadX is setup for running in Cortex-A5 32-bit mode. This is +also true for the demonstration system. It is possible to build any +ThreadX file and/or the application in Thumb mode. The only exception +to this is the file tx_thread_shell_entry.c. This file must always be +built in 32-bit mode. + + +12. VFP Support + +By default, VFP support is disabled for each thread. If saving the context of the VFP registers +is needed, the following API call must be made from the context of the application thread - before +the VFP usage: + +void tx_thread_vfp_enable(void); + +After this API is called in the application, VFP registers will be saved/restored for this thread if it +is preempted via an interrupt. All other suspension of the this thread will not require the VFP registers +to be saved/restored. + +To disable VFP register context saving, simply call the following API: + +void tx_thread_vfp_disable(void); + + +13. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +05/19/2020 Initial ThreadX version of Cortex-A5/Green Hills port. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_a5/green/src/tx_thread_context_restore.arm b/ports/cortex_a5/green/src/tx_thread_context_restore.arm new file mode 100644 index 00000000..03afd6fe --- /dev/null +++ b/ports/cortex_a5/green/src/tx_thread_context_restore.arm @@ -0,0 +1,259 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # Disable IRQ and FIQ interrupts +#else + DISABLE_INTS = 0x80 # Disable IRQ interrupts +#endif + SVC_MODE = (0x13 | DISABLE_INTS) # SVC mode + IRQ_MODE = (0x12 | DISABLE_INTS) # IRQ mode + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore Cortex-A5/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores the interrupt context if it is processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_restore(VOID) +{ */ + .globl _tx_thread_context_restore +_tx_thread_context_restore: + + /* Lockout interrupts. */ + +#ifdef TX_BEFORE_ARMV6 + MRS r3, CPSR # Pickup current CPSR + ORR r0, r3, DISABLE_INTS # Build interrupt disable value + MSR CPSR_c, r0 # Lockout interrupts +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if # Disable IRQ and FIQ interrupts +#else + CPSID i # Disable IRQ interrupts +#endif +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR exit function to indicate an ISR is complete. */ + + BL _tx_execution_isr_exit # Call the ISR exit function +#endif + + /* Determine if interrupts are nested. */ + /* if (--_tx_thread_system_state) + { */ + + LDR r3, =_tx_thread_system_state # Pickup address of system state var + LDR r2, [r3] # Pickup system state + SUB r2, r2, 1 # Decrement the counter + STR r2, [r3] # Store the counter + CMP r2, 0 # Was this the first interrupt? + BEQ __tx_thread_not_nested_restore # If so, not a nested restore + + /* Interrupts are nested. */ + + /* Just recover the saved registers and return to the point of + interrupt. */ + + LDMIA sp!, {r0, r10, r12, lr} # Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 # Put SPSR back + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOVS pc, lr # Return to point of interrupt + + /* } */ +__tx_thread_not_nested_restore: + + /* Determine if a thread was interrupted and no preemption is required. */ + /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) + || (_tx_thread_preempt_disable)) + { */ + + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup actual current thread pointer + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_idle_system_restore # Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable # Pickup preempt disable address + LDR r2, [r3] # Pickup actual preempt disable flag + CMP r2, 0 # Is it set? + BNE __tx_thread_no_preempt_restore # Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr # Pickup address of execute thread ptr + LDR r2, [r3] # Pickup actual execute thread pointer + CMP r0, r2 # Is the same thread highest priority? + BNE __tx_thread_preempt_restore # No, preemption needs to happen + + +__tx_thread_no_preempt_restore: + + /* Restore interrupted thread or ISR. */ + + /* Pickup the saved stack pointer. */ + /* tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; */ + + /* Recover the saved context and return to the point of interrupt. */ + + LDMIA sp!, {r0, r10, r12, lr} # Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 # Put SPSR back + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOVS pc, lr # Return to point of interrupt + + /* } + else + { */ +__tx_thread_preempt_restore: + + LDMIA sp!, {r3, r10, r12, lr} # Recover temporarily saved registers + MOV r1, lr # Save lr (point of interrupt) + MOV r2, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r2 # Enter SVC mode + STR r1, [sp, -4]! # Save point of interrupt + STMDB sp!, {r4-r12, lr} # Save upper half of registers + MOV r4, r3 # Save SPSR in r4 + MOV r2, IRQ_MODE # Build IRQ mode CPSR + MSR CPSR_c, r2 # Re-enter IRQ mode + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOV r5, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r5 # Enter SVC mode + STMDB sp!, {r0-r3} # Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup current thread pointer + +#ifdef __VFP__ + LDR r2, [r0, 144] # Pickup the VFP enabled flag + CMP r2, 0 # Is the VFP enabled? + BEQ _tx_skip_irq_vfp_save # No, skip VFP IRQ save + VMRS r2, FPSCR # Pickup the FPSCR + STR r2, [sp, -4]! # Save FPSCR + VSTMDB sp!, {D16-D31} # Save D16-D31 + VSTMDB sp!, {D0-D15} # Save D0-D15 +_tx_skip_irq_vfp_save: +#endif + + MOV r3, 1 # Build interrupt stack type + STMDB sp!, {r3, r4} # Save interrupt stack type and SPSR + STR sp, [r0, 8] # Save stack pointer in thread control + /* # block */ + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r4, r0 # Save r0 + MOV r5, r1 # Save r1 + BL _tx_el_thread_preempted # Call thread preempted routine + MOV r0, r4 # Restore r0 + MOV r1, r5 # Restore r1 +#endif + + /* Save the remaining time-slice and disable it. */ + /* if (_tx_timer_time_slice) + { */ + + LDR r3, =_tx_timer_time_slice # Pickup time-slice variable address + LDR r2, [r3] # Pickup time-slice + CMP r2, 0 # Is it active? + BEQ __tx_thread_dont_save_ts # No, don't save it + + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + STR r2, [r0, 24] # Save thread's time-slice + MOV r2, 0 # Clear value + STR r2, [r3] # Disable global time-slice flag + + /* } */ +__tx_thread_dont_save_ts: + + + /* Clear the current task pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + MOV r0, 0 # NULL value + STR r0, [r1] # Clear current thread pointer + + /* Return to the scheduler. */ + /* _tx_thread_schedule(); */ + + B _tx_thread_schedule # Return to scheduler + /* } */ + +__tx_thread_idle_system_restore: + + /* Just return back to the scheduler! */ + + + MOV r3, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r3 # Lockout interrupts + B _tx_thread_schedule # Return to scheduler + + .type _tx_thread_context_restore,$function + .size _tx_thread_context_restore,.-_tx_thread_context_restore + +/* } */ + diff --git a/ports/cortex_a5/green/src/tx_thread_context_save.arm b/ports/cortex_a5/green/src/tx_thread_context_save.arm new file mode 100644 index 00000000..8ad6b339 --- /dev/null +++ b/ports/cortex_a5/green/src/tx_thread_context_save.arm @@ -0,0 +1,207 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # IRQ & FIQ interrupts disabled +#else + DISABLE_INTS = 0x80 # IRQ interrupts disabled +#endif + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save Cortex-A5/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_save(VOID) +{ */ + .globl _tx_thread_context_save +_tx_thread_context_save: + + /* Upon entry to this routine, it is assumed that IRQ interrupts are locked + out, we are in IRQ mode, and all registers are intact. */ + + /* Check for a nested interrupt condition. */ + /* if (_tx_thread_system_state++) + { */ + + STMDB sp!, {r0-r3} # Save some working registers + +#ifdef TX_ENABLE_FIQ_SUPPORT +#ifdef TX_BEFORE_ARMV6 + MRS r0, CPSR # Pickup the CPSR + ORR r0, r0, DISABLE_INTS # Build disable interrupt CPSR + MSR CPSR_c, r0 # Disable interrupts +#else + CPSID if # Disable FIQ interrupts +#endif +#endif + + LDR r3, =_tx_thread_system_state # Pickup address of system state var + LDR r2, [r3] # Pickup system state + CMP r2, 0 # Is this the first interrupt? + BEQ __tx_thread_not_nested_save # Yes, not a nested context save + + /* Nested interrupt condition. */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + + /* Save the rest of the scratch registers on the stack and return to the + calling ISR. */ + + MRS r0, SPSR # Pickup saved SPSR + SUB lr, lr, 4 # Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} # Store other registers + + /* Return to the ISR. */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + B __tx_irq_processing_return # Continue IRQ processing + +__tx_thread_not_nested_save: + /* } */ + + /* Otherwise, not nested, check to see if a thread was running. */ + /* else if (_tx_thread_current_ptr) + { */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup current thread pointer + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_idle_system_save # If so, interrupt occurred in + /* # scheduling loop - nothing needs saving! */ + + /* Save minimal context of interrupted thread. */ + + MRS r2, SPSR # Pickup saved SPSR + SUB lr, lr, 4 # Adjust point of interrupt + STMDB sp!, {r2, r10, r12, lr} # Store other registers + + /* Save the current stack pointer in the thread's control block. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ + + /* Switch to the system stack. */ + /* sp = _tx_thread_system_stack_ptr; */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + B __tx_irq_processing_return # Continue IRQ processing + + /* } + else + { */ + +__tx_thread_idle_system_save: + + /* Interrupt occurred in the scheduling loop. */ + + /* Not much to do here, just adjust the stack pointer, and return to IRQ + processing. */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + ADD sp, sp, 16 # Recover saved registers + B __tx_irq_processing_return # Continue IRQ processing + + .type _tx_thread_context_save,$function + .size _tx_thread_context_save,.-_tx_thread_context_save + + /* } +} */ + diff --git a/ports/cortex_a5/green/src/tx_thread_fiq_context_restore.arm b/ports/cortex_a5/green/src/tx_thread_fiq_context_restore.arm new file mode 100644 index 00000000..b6886b0e --- /dev/null +++ b/ports/cortex_a5/green/src/tx_thread_fiq_context_restore.arm @@ -0,0 +1,264 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + SVC_MODE = 0xD3 # SVC mode + FIQ_MODE = 0xD1 # FIQ mode +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # Disable IRQ and FIQ interrupts +#else + DISABLE_INTS = 0x80 # Disable IRQ interrupts +#endif + MODE_MASK = 0x1F # Mode mask + IRQ_MODE_BITS = 0x12 # IRQ mode bits + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_context_restore Cortex-A5/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores the fiq interrupt context when processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* FIQ ISR Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_fiq_context_restore(VOID) +{ */ + .globl _tx_thread_fiq_context_restore +_tx_thread_fiq_context_restore: + + /* Lockout interrupts. */ + +#ifdef TX_BEFORE_ARMV6 + MRS r3, CPSR # Pickup current CPSR + ORR r0, r3, DISABLE_INTS # Build interrupt disable value + MSR CPSR_c, r0 # Lockout interrupts +#else + CPSID if # Disable IRQ and FIQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR exit function to indicate an ISR is complete. */ + + BL _tx_execution_isr_exit # Call the ISR exit function +#endif + + /* Determine if interrupts are nested. */ + /* if (--_tx_thread_system_state) + { */ + + LDR r3, =_tx_thread_system_state # Pickup address of system state var + LDR r2, [r3] # Pickup system state + SUB r2, r2, 1 # Decrement the counter + STR r2, [r3] # Store the counter + CMP r2, 0 # Was this the first interrupt? + BEQ __tx_thread_fiq_not_nested_restore # If so, not a nested restore + + /* Interrupts are nested. */ + + /* Just recover the saved registers and return to the point of + interrupt. */ + + LDMIA sp!, {r0, r10, r12, lr} # Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 # Put SPSR back + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOVS pc, lr # Return to point of interrupt + + /* } */ +__tx_thread_fiq_not_nested_restore: + + /* Determine if a thread was interrupted and no preemption is required. */ + /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) + || (_tx_thread_preempt_disable)) + { */ + + LDR r1, [sp] # Pickup the saved SPSR + MOV r2, MODE_MASK # Build mask to isolate the interrupted mode + AND r1, r1, r2 # Isolate mode bits + CMP r1, IRQ_MODE_BITS # Was an interrupt taken in IRQ mode before we + /* # got to context save? */ + BEQ __tx_thread_fiq_no_preempt_restore # Yes, just go back to point of interrupt + + + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup actual current thread pointer + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_fiq_idle_system_restore # Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable # Pickup preempt disable address + LDR r2, [r3] # Pickup actual preempt disable flag + CMP r2, 0 # Is it set? + BNE __tx_thread_fiq_no_preempt_restore # Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr # Pickup address of execute thread ptr + LDR r2, [r3] # Pickup actual execute thread pointer + CMP r0, r2 # Is the same thread highest priority? + BNE __tx_thread_fiq_preempt_restore # No, preemption needs to happen + + +__tx_thread_fiq_no_preempt_restore: + + /* Restore interrupted thread or ISR. */ + + /* Pickup the saved stack pointer. */ + /* tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; */ + + /* Recover the saved context and return to the point of interrupt. */ + + LDMIA sp!, {r0, lr} # Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 # Put SPSR back + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOVS pc, lr # Return to point of interrupt + + /* } + else + { */ +__tx_thread_fiq_preempt_restore: + + LDMIA sp!, {r3, lr} # Recover temporarily saved registers + MOV r1, lr # Save lr (point of interrupt) + MOV r2, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r2 # Enter SVC mode + STR r1, [sp, -4]! # Save point of interrupt + STMDB sp!, {r4-r12, lr} # Save upper half of registers + MOV r4, r3 # Save SPSR in r4 + MOV r2, FIQ_MODE # Build FIQ mode CPSR + MSR CPSR_c, r2 # Re-enter FIQ mode + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOV r5, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r5 # Enter SVC mode + STMDB sp!, {r0-r3} # Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup current thread pointer + +#ifdef __VFP__ + LDR r2, [r0, 144] # Pickup the VFP enabled flag + CMP r2, 0 # Is the VFP enabled? + BEQ _tx_skip_fiq_vfp_save # No, skip VFP IRQ save + VMRS r2, FPSCR # Pickup the FPSCR + STR r2, [sp, -4]! # Save FPSCR + VSTMDB sp!, {D16-D31} # Save D16-D31 + VSTMDB sp!, {D0-D15} # Save D0-D15 +_tx_skip_fiq_vfp_save: +#endif + + MOV r3, 1 # Build interrupt stack type + STMDB sp!, {r3, r4} # Save interrupt stack type and SPSR + STR sp, [r0, 8] # Save stack pointer in thread control + /* # block */ + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r4, r0 # Save r0 + MOV r5, r1 # Save r1 + BL _tx_el_thread_preempted # Call thread preempted routine + MOV r0, r4 # Restore r0 + MOV r1, r5 # Restore r1 +#endif + + /* Save the remaining time-slice and disable it. */ + /* if (_tx_timer_time_slice) + { */ + + LDR r3, =_tx_timer_time_slice # Pickup time-slice variable address + LDR r2, [r3] # Pickup time-slice + CMP r2, 0 # Is it active? + BEQ __tx_thread_fiq_dont_save_ts # No, don't save it + + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + STR r2, [r0, 24] # Save thread's time-slice + MOV r2, 0 # Clear value + STR r2, [r3] # Disable global time-slice flag + + /* } */ +__tx_thread_fiq_dont_save_ts: + + + /* Clear the current task pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + MOV r0, 0 # NULL value + STR r0, [r1] # Clear current thread pointer + + /* Return to the scheduler. */ + /* _tx_thread_schedule(); */ + + B _tx_thread_schedule # Return to scheduler + /* } */ + +__tx_thread_fiq_idle_system_restore: + + /* Just return back to the scheduler! */ + + ADD sp, sp, 24 # Recover FIQ stack space + MOV r3, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r3 # Lockout interrupts + B _tx_thread_schedule # Return to scheduler + + .type _tx_thread_fiq_context_restore,$function + .size _tx_thread_fiq_context_restore,.-_tx_thread_fiq_context_restore + +/* } */ + diff --git a/ports/cortex_a5/green/src/tx_thread_fiq_context_save.arm b/ports/cortex_a5/green/src/tx_thread_fiq_context_save.arm new file mode 100644 index 00000000..d6df9a63 --- /dev/null +++ b/ports/cortex_a5/green/src/tx_thread_fiq_context_save.arm @@ -0,0 +1,197 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_context_save Cortex-A5/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_fiq_context_save(VOID) +{ */ + .globl _tx_thread_fiq_context_save +_tx_thread_fiq_context_save: + + /* Upon entry to this routine, it is assumed that IRQ interrupts are locked + out, we are in IRQ mode, and all registers are intact. */ + + /* Check for a nested interrupt condition. */ + /* if (_tx_thread_system_state++) + { */ + + STMDB sp!, {r0-r3} # Save some working registers + LDR r3, =_tx_thread_system_state # Pickup address of system state var + LDR r2, [r3] # Pickup system state + CMP r2, 0 # Is this the first interrupt? + BEQ __tx_thread_fiq_not_nested_save # Yes, not a nested context save + + /* Nested interrupt condition. */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + + /* Save the rest of the scratch registers on the stack and return to the + calling ISR. */ + + MRS r0, SPSR # Pickup saved SPSR + SUB lr, lr, 4 # Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} # Store other registers + + /* Return to the ISR. */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + B __tx_fiq_processing_return # Continue FIQ processing + +__tx_thread_fiq_not_nested_save: + /* } */ + + /* Otherwise, not nested, check to see if a thread was running. */ + /* else if (_tx_thread_current_ptr) + { */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup current thread pointer + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_fiq_idle_system_save # If so, interrupt occurred in + /* # scheduling loop - nothing needs saving! */ + + /* Save minimal context of interrupted thread. */ + + MRS r2, SPSR # Pickup saved SPSR + SUB lr, lr, 4 # Adjust point of interrupt + STMDB sp!, {r2, lr} # Store other registers, Note that we don't + /* # need to save sl and ip since FIQ has + # copies of these registers. Nested + # interrupt processing does need to save + # these registers. */ + + /* Save the current stack pointer in the thread's control block. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ + + /* Switch to the system stack. */ + /* sp = _tx_thread_system_stack_ptr; */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + B __tx_fiq_processing_return # Continue FIQ processing + + /* } + else + { */ + +__tx_thread_fiq_idle_system_save: + + /* Interrupt occurred in the scheduling loop. */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + /* Not much to do here, save the current SPSR and LR for possible + use in IRQ interrupted in idle system conditions, and return to + FIQ interrupt processing. */ + + MRS r0, SPSR # Pickup saved SPSR + SUB lr, lr, 4 # Adjust point of interrupt + STMDB sp!, {r0, lr} # Store other registers that will get used + /* # or stripped off the stack in context + # restore */ + B __tx_fiq_processing_return # Continue FIQ processing + + .type _tx_thread_fiq_context_save,$function + .size _tx_thread_fiq_context_save,.-_tx_thread_fiq_context_save + + /* } +} */ + diff --git a/ports/cortex_a5/green/src/tx_thread_fiq_nesting_end.arm b/ports/cortex_a5/green/src/tx_thread_fiq_nesting_end.arm new file mode 100644 index 00000000..156bf31c --- /dev/null +++ b/ports/cortex_a5/green/src/tx_thread_fiq_nesting_end.arm @@ -0,0 +1,109 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # Disable IRQ and FIQ interrupts +#else + DISABLE_INTS = 0x80 # Disable IRQ interrupts +#endif + MODE_MASK = 0x1F # Mode mask + FIQ_MODE_BITS = 0x11 # FIQ mode bits + SVC_MODE_BITS = 0x13 # SVC mode value */ + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_nesting_end Cortex-A5/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from FIQ mode after */ +/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +/* processing from system mode back to FIQ mode prior to the ISR */ +/* calling _tx_thread_fiq_context_restore. Note that this function */ +/* assumes the system stack pointer is in the same position after */ +/* nesting start function was called. */ +/* */ +/* This function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.arm). */ +/* */ +/* This function returns with FIQ interrupts disabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_fiq_nesting_end(VOID) +{ */ + .globl _tx_thread_fiq_nesting_end +_tx_thread_fiq_nesting_end: + MOV r3,lr # Save ISR return address + MRS r0, CPSR # Pickup the CPSR + ORR r0, r0, DISABLE_INTS # Build disable interrupt value + MSR CPSR_c, r0 # Disable interrupts + LDR lr, [sp] # Pickup saved lr + ADD sp, sp, 4 # Adjust stack pointer + BIC r0, r0, MODE_MASK # Clear mode bits + ORR r0, r0, FIQ_MODE_BITS # Build IRQ mode CPSR + MSR CPSR_c, r0 # Re-enter IRQ mode + MOV pc, r3 # Return to ISR + + .type _tx_thread_fiq_nesting_end,$function + .size _tx_thread_fiq_nesting_end,.-_tx_thread_fiq_nesting_end +/* } */ + diff --git a/ports/cortex_a5/green/src/tx_thread_fiq_nesting_start.arm b/ports/cortex_a5/green/src/tx_thread_fiq_nesting_start.arm new file mode 100644 index 00000000..e085b508 --- /dev/null +++ b/ports/cortex_a5/green/src/tx_thread_fiq_nesting_start.arm @@ -0,0 +1,103 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + + FIQ_DISABLE = 0x40 # FIQ disable bit + MODE_MASK = 0x1F # Mode mask + SYS_MODE_BITS = 0x1F # System mode bits + + + .text + .align 4 + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_nesting_start Cortex-A5/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from FIQ mode after */ +/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +/* processing to the system mode so nested FIQ interrupt processing */ +/* is possible (system mode has its own "lr" register). Note that */ +/* this function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.arm). */ +/* */ +/* This function returns with FIQ interrupts enabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_fiq_nesting_start(VOID) +{ */ + .globl _tx_thread_fiq_nesting_start +_tx_thread_fiq_nesting_start: + MOV r3,lr # Save ISR return address + MRS r0, CPSR # Pickup the CPSR + BIC r0, r0, MODE_MASK # Clear the mode bits + ORR r0, r0, SYS_MODE_BITS # Build system mode CPSR + MSR CPSR_c, r0 # Enter system mode + STR lr, [sp, -4]! # Push the system mode lr on the system mode stack + BIC r0, r0, FIQ_DISABLE # Build enable FIQ CPSR + MSR CPSR_c, r0 # Enter system mode + MOV pc, r3 # Return to ISR + + .type _tx_thread_fiq_nesting_start,$function + .size _tx_thread_fiq_nesting_start,.-_tx_thread_fiq_nesting_start +/* } */ + diff --git a/ports/cortex_a5/green/src/tx_thread_interrupt_control.arm b/ports/cortex_a5/green/src/tx_thread_interrupt_control.arm new file mode 100644 index 00000000..d10afac0 --- /dev/null +++ b/ports/cortex_a5/green/src/tx_thread_interrupt_control.arm @@ -0,0 +1,101 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" */ + + +#ifdef TX_ENABLE_FIQ_SUPPORT + INT_MASK = 0xC0 # Interrupt bit mask +#else + INT_MASK = 0x80 # Interrupt bit mask +#endif + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control Cortex-A5/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_control(UINT new_posture) +{ */ + .globl _tx_thread_interrupt_control +_tx_thread_interrupt_control: + + /* Pickup current interrupt lockout posture. */ + + MRS r3, CPSR # Pickup current CPSR + BIC r1, r3, INT_MASK # Clear interrupt lockout bits + ORR r1, r1, r0 # Or-in new interrupt lockout bits + + /* Apply the new interrupt posture. */ + + MSR CPSR_c, r1 # Setup new CPSR + AND r0, r3, INT_MASK # Return previous interrupt mask + RET # Return to caller + + .type _tx_thread_interrupt_control,$function + .size _tx_thread_interrupt_control,.-_tx_thread_interrupt_control +/* } */ + + + diff --git a/ports/cortex_a5/green/src/tx_thread_interrupt_disable.arm b/ports/cortex_a5/green/src/tx_thread_interrupt_disable.arm new file mode 100644 index 00000000..a67b3135 --- /dev/null +++ b/ports/cortex_a5/green/src/tx_thread_interrupt_disable.arm @@ -0,0 +1,105 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" */ + + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # IRQ & FIQ interrupts disabled +#else + DISABLE_INTS = 0x80 # IRQ interrupts disabled +#endif + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_disable Cortex-A5/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for disabling interrupts */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_disable(void) +{ */ + .globl _tx_thread_interrupt_disable +_tx_thread_interrupt_disable: + + /* Pickup current interrupt lockout posture. */ + + MRS r0, CPSR # Pickup current CPSR + + /* Mask interrupts. */ + +#ifdef TX_BEFORE_ARMV6 + ORR r1, r0, DISABLE_INTS # Mask interrupts + MSR CPSR_c, r1 # Setup new CPSR +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if # Disable IRQ and FIQ +#else + CPSID i # Disable IRQ +#endif +#endif + + RET # Return previous CPSR value + + .type _tx_thread_interrupt_disable,$function + .size _tx_thread_interrupt_disable,.-_tx_thread_interrupt_disable +/* } */ + diff --git a/ports/cortex_a5/green/src/tx_thread_interrupt_restore.arm b/ports/cortex_a5/green/src/tx_thread_interrupt_restore.arm new file mode 100644 index 00000000..37a1fc67 --- /dev/null +++ b/ports/cortex_a5/green/src/tx_thread_interrupt_restore.arm @@ -0,0 +1,85 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" */ + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_restore Cortex-A5/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for restoring interrupts to the state */ +/* returned by a previous _tx_thread_interrupt_disable call. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_interrupt_restore(UINT new_posture) +{ */ + .globl _tx_thread_interrupt_restore +_tx_thread_interrupt_restore: + + /* Apply the new interrupt posture. */ + + MSR CPSR_c, r0 # Setup new CPSR + RET + + .type _tx_thread_interrupt_restore,$function + .size _tx_thread_interrupt_restore,.-_tx_thread_interrupt_restore +/* } */ + diff --git a/ports/cortex_a5/green/src/tx_thread_irq_nesting_end.arm b/ports/cortex_a5/green/src/tx_thread_irq_nesting_end.arm new file mode 100644 index 00000000..f58cbdce --- /dev/null +++ b/ports/cortex_a5/green/src/tx_thread_irq_nesting_end.arm @@ -0,0 +1,109 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # Disable IRQ and FIQ interrupts +#else + DISABLE_INTS = 0x80 # Disable IRQ interrupts +#endif + MODE_MASK = 0x1F # Mode mask + IRQ_MODE_BITS = 0x12 # IRQ mode bits + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_irq_nesting_end Cortex-A5/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from IRQ mode after */ +/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +/* processing from system mode back to IRQ mode prior to the ISR */ +/* calling _tx_thread_context_restore. Note that this function */ +/* assumes the system stack pointer is in the same position after */ +/* nesting start function was called. */ +/* */ +/* This function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.arm). */ +/* */ +/* This function returns with IRQ interrupts disabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_irq_nesting_end(VOID) +{ */ + .globl _tx_thread_irq_nesting_end +_tx_thread_irq_nesting_end: + MOV r3,lr # Save ISR return address + MRS r0, CPSR # Pickup the CPSR + ORR r0, r0, DISABLE_INTS # Build disable interrupt value + MSR CPSR_c, r0 # Disable interrupts + LDR lr, [sp] # Pickup saved lr + ADD sp, sp, 4 # Adjust stack pointer + BIC r0, r0, MODE_MASK # Clear mode bits + ORR r0, r0, IRQ_MODE_BITS # Build IRQ mode CPSR + MSR CPSR_c, r0 # Re-enter IRQ mode + MOV pc, r3 # Return to ISR + + .type _tx_thread_irq_nesting_end,$function + .size _tx_thread_irq_nesting_end,.-_tx_thread_irq_nesting_end + +/* } */ + diff --git a/ports/cortex_a5/green/src/tx_thread_irq_nesting_start.arm b/ports/cortex_a5/green/src/tx_thread_irq_nesting_start.arm new file mode 100644 index 00000000..6a1c0671 --- /dev/null +++ b/ports/cortex_a5/green/src/tx_thread_irq_nesting_start.arm @@ -0,0 +1,102 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + + IRQ_DISABLE = 0x80 # IRQ disable bit + MODE_MASK = 0x1F # Mode mask + SYS_MODE_BITS = 0x1F # System mode bits + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_irq_nesting_start Cortex-A5/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from IRQ mode after */ +/* _tx_thread_context_save has been called and switches the IRQ */ +/* processing to the system mode so nested IRQ interrupt processing */ +/* is possible (system mode has its own "lr" register). Note that */ +/* this function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.arm). */ +/* */ +/* This function returns with IRQ interrupts enabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_irq_nesting_start(VOID) +{ */ + .globl _tx_thread_irq_nesting_start +_tx_thread_irq_nesting_start: + MOV r3,lr # Save ISR return address + MRS r0, CPSR # Pickup the CPSR + BIC r0, r0, MODE_MASK # Clear the mode bits + ORR r0, r0, SYS_MODE_BITS # Build system mode CPSR + MSR CPSR_c, r0 # Enter system mode + STR lr, [sp, -4]! # Push the system mode lr on the system mode stack + BIC r0, r0, IRQ_DISABLE # Build enable IRQ CPSR + MSR CPSR_c, r0 # Enter system mode + MOV pc, r3 # Return to ISR + + .type _tx_thread_irq_nesting_start,$function + .size _tx_thread_irq_nesting_start,.-_tx_thread_irq_nesting_start +/* } */ + diff --git a/ports/cortex_a5/green/src/tx_thread_schedule.arm b/ports/cortex_a5/green/src/tx_thread_schedule.arm new file mode 100644 index 00000000..00f21742 --- /dev/null +++ b/ports/cortex_a5/green/src/tx_thread_schedule.arm @@ -0,0 +1,253 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + ENABLE_INTS = 0xC0 # IRQ & FIQ Interrupts enabled mask +#else + ENABLE_INTS = 0x80 # IRQ Interrupts enabled mask +#endif + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule Cortex-A5/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* _tx_thread_context_restore Restore thread's context */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_schedule(VOID) +{ */ + .globl _tx_thread_schedule +_tx_thread_schedule: + + /* Enable interrupts. */ + +#ifdef TX_BEFORE_ARMV6 + MRS r2, CPSR # Pickup CPSR + BIC r0, r2, ENABLE_INTS # Clear the disable bit(s) + MSR CPSR_c, r0 # Enable interrupts +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSIE if # Enable IRQ and FIQ interrupts +#else + CPSIE i # Enable IRQ interrupts +#endif +#endif + + /* Wait for a thread to execute. */ + /* do + { */ + LDR r1, =_tx_thread_execute_ptr # Address of thread execute ptr + +__tx_thread_schedule_loop: + + LDR r0, [r1] # Pickup next thread to execute + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_schedule_loop # If so, keep looking for a thread + + /* } + while(_tx_thread_execute_ptr == TX_NULL); */ + + /* Yes! We have a thread to execute. Lockout interrupts and + transfer control to it. */ + +#ifdef TX_BEFORE_ARMV6 + MSR CPSR_c, r2 # Disable interrupts +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if # Disable IRQ and FIQ interrupts +#else + CPSID i # Disable IRQ interrupts +#endif +#endif + + /* Setup the current thread pointer. */ + /* _tx_thread_current_ptr = _tx_thread_execute_ptr; */ + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV v1, r0 # Save temp register in non-volatile register + BL _tx_el_thread_running # Call event logging routine + MOV r0, v1 # Restore temp register +#endif + + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread + STR r0, [r1] # Setup current thread pointer + + /* Increment the run count for this thread. */ + /* _tx_thread_current_ptr -> tx_thread_run_count++; */ + + LDR r2, [r0, 4] # Pickup run counter + LDR r3, [r0, 24] # Pickup time-slice for this thread + ADD r2, r2, 1 # Increment thread run-counter + STR r2, [r0, 4] # Store the new run counter + + /* Setup time-slice, if present. */ + /* _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; */ + + LDR r2, =_tx_timer_time_slice # Pickup address of time slice + /* # variable */ + LDR sp, [r0, 8] # Switch stack pointers + STR r3, [r2] # Setup time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread entry function to indicate the thread is executing. */ + + MOV r5, r0 # Save r0 + BL _tx_execution_thread_enter # Call the thread execution enter function + MOV r0, r5 # Restore r0 +#endif + + /* Switch to the thread's stack. */ + /* sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; */ + + /* Determine if an interrupt frame or a synchronous task suspension frame + is present. */ + + LDMIA sp!, {r4, r5} # Pickup the stack type and saved CPSR + CMP r4, 0 # Check for synchronous context switch + BEQ _tx_solicited_return + MSR SPSR_cxsf, r5 # Setup SPSR for return +#ifdef __VFP__ + LDR r1, [r0, 144] # Pickup the VFP enabled flag + CMP r1, 0 # Is the VFP enabled? + BEQ _tx_skip_interrupt_vfp_restore # No, skip VFP interrupt restore + VLDMIA sp!, {D0-D15} # Recover D0-D15 + VLDMIA sp!, {D16-D31} # Recover D16-D31 + LDR r4, [sp], 4 # Pickup FPSCR + VMSR FPSCR, r4 # Restore FPSCR +_tx_skip_interrupt_vfp_restore: +#endif + LDMIA sp!, {r0-r12, lr, pc}^ # Return to point of thread interrupt + +_tx_solicited_return: +#ifdef __VFP__ + LDR r1, [r0, 144] # Pickup the VFP enabled flag + CMP r1, 0 # Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_restore # No, skip VFP solicited restore + VLDMIA sp!, {D8-D15} # Recover D8-D15 + VLDMIA sp!, {D16-D31} # Recover D16-D31 + LDR r4, [sp], 4 # Pickup FPSCR + VMSR FPSCR, r4 # Restore FPSCR +_tx_skip_solicited_vfp_restore: +#endif + MSR CPSR_cxsf, r5 # Recover CPSR + LDMIA sp!, {r4-r11, lr} # Return to thread synchronously + RET # Return to caller (Thumb safe) + + .type _tx_thread_schedule,$function + .size _tx_thread_schedule,.-_tx_thread_schedule + +#ifdef __VFP__ + .globl tx_thread_vfp_enable +tx_thread_vfp_enable: + MRS r2, CPSR # Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSIE if # Enable IRQ and FIQ interrupts +#else + CPSIE i # Enable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr # Build current thread pointer address + LDR r1, [r0] # Pickup current thread pointer + CMP r1, 0 # Check for NULL thread pointer + BEQ __tx_no_thread_to_enable # If NULL, skip VFP enable + MOV r0, 1 # Build enable value + STR r0, [r1, 144] # Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_enable: + MSR CPSR_cxsf, r2 # Recover CPSR + RET # Return to caller (Thumb safe) + + .type tx_thread_vfp_enable,$function + .size tx_thread_vfp_enable,.-tx_thread_vfp_enable + + + .globl tx_thread_vfp_disable +tx_thread_vfp_disable: + MRS r2, CPSR # Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSIE if # Enable IRQ and FIQ interrupts +#else + CPSIE i # Enable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr # Build current thread pointer address + LDR r1, [r0] # Pickup current thread pointer + CMP r1, 0 # Check for NULL thread pointer + BEQ __tx_no_thread_to_disable # If NULL, skip VFP disable + MOV r0, 0 # Build disable value + STR r0, [r1, 144] # Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_disable: + MSR CPSR_cxsf, r2 # Recover CPSR + RET # Return to caller (Thumb safe) + + .type tx_thread_vfp_disable,$function + .size tx_thread_vfp_disable,.-tx_thread_vfp_disable + +#endif + +/* } */ + + diff --git a/ports/cortex_a5/green/src/tx_thread_stack_build.arm b/ports/cortex_a5/green/src/tx_thread_stack_build.arm new file mode 100644 index 00000000..9775e47c --- /dev/null +++ b/ports/cortex_a5/green/src/tx_thread_stack_build.arm @@ -0,0 +1,161 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" */ + + SVC_MODE = 0x13 # SVC mode +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSR_MASK = 0xDF # Mask initial CPSR, IRQ & FIQ ints enabled +#else + CPSR_MASK = 0x9F # Mask initial CPSR, IRQ ints enabled +#endif + + THUMB_BIT = 0x20 # Thumb-bit + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build Cortex-A5/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +{ */ + .globl _tx_thread_stack_build +_tx_thread_stack_build: + + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-A5 should look like the following after it is built: + + Stack Top: 1 Interrupt stack frame type + CPSR Initial value for CPSR + r0 (a1) Initial value for r0 + r1 (a2) Initial value for r1 + r2 (a3) Initial value for r2 + r3 (a4) Initial value for r3 + r4 (v1) Initial value for r4 + r5 (v2) Initial value for r5 + r6 (v3) Initial value for r6 + r7 (v4) Initial value for r7 + r8 (v5) Initial value for r8 + r9 (sb) Initial value for r9 + r10 (sl) Initial value for r10 + r11 (fp) Initial value for r11 + r12 (ip) Initial value for r12 + lr Initial value for lr + pc Initial value for pc + 0 For stack backtracing + + Stack Bottom: (higher memory address) */ + + LDR r2, [r0, 16] # Pickup end of stack area + BIC r2, r2, 7 # Ensure 8-byte alignment + SUB r2, r2, 76 # Allocate space for the stack frame + + /* Actually build the stack frame. */ + + MOV r3, 1 # Build interrupt stack type + STR r3, [r2] # Store stack type + MOV r3, 0 # Build initial register value + STR r3, [r2, 8] # Store initial r0 + STR r3, [r2, 12] # Store initial r1 + STR r3, [r2, 16] # Store initial r2 + STR r3, [r2, 20] # Store initial r3 + STR r3, [r2, 24] # Store initial r4 + STR r3, [r2, 28] # Store initial r5 + STR r3, [r2, 32] # Store initial r6 + STR r3, [r2, 36] # Store initial r7 + STR r3, [r2, 40] # Store initial r8 + STR r3, [r2, 44] # Store initial r9 + LDR r3, [r0, 12] # Pickup stack starting address + STR r3, [r2, 48] # Store initial r10 + MOV r3, 0 # Build initial register value + STR r3, [r2, 52] # Store initial r11 + STR r3, [r2, 56] # Store initial r12 + STR r3, [r2, 60] # Store initial lr + STR r1, [r2, 64] # Store initial pc + STR r3, [r2, 68] # 0 for back-trace + + MRS r3, CPSR # Pickup CPSR + BIC r3, r3, CPSR_MASK # Mask mode bits of CPSR + ORR r3, r3, SVC_MODE # Build CPSR, SVC mode, interrupts enabled + BIC r3, r3, #THUMB_BIT # Clear Thumb-bit by default + AND r1, r1, #1 # Determine if the entry function is in Thumb mode + CMP r1, 1 # Is the Thumb-bit set? + ORREQ r3, r3, #THUMB_BIT # Yes, set the Thumb-bit + STR r3, [r2, 4] # Store initial CPSR + + /* Setup stack pointer. */ + /* thread_ptr -> tx_thread_stack_ptr = r2; */ + + STR r2, [r0, 8] # Save stack pointer in thread's + /* # control block */ + RET # Return to caller + + .type _tx_thread_stack_build,$function + .size _tx_thread_stack_build,.-_tx_thread_stack_build +/* } */ + diff --git a/ports/cortex_a5/green/src/tx_thread_system_return.arm b/ports/cortex_a5/green/src/tx_thread_system_return.arm new file mode 100644 index 00000000..0d86c095 --- /dev/null +++ b/ports/cortex_a5/green/src/tx_thread_system_return.arm @@ -0,0 +1,167 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # IRQ & FIQ interrupts disabled +#else + DISABLE_INTS = 0x80 # IRQ interrupts disabled +#endif + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return Cortex-A5/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the ThreadX system. Only a */ +/* minimal context is saved since the compiler assumes temp registers */ +/* are going to get slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_system_return(VOID) +{ */ + .globl _tx_thread_system_return +_tx_thread_system_return: + + /* Save minimal context on the stack. */ + + MOV r0, 0 # Build a solicited stack type + MRS r1, CPSR # Pickup the CPSR + STMDB sp!, {r4-r11, lr} # Save minimal context + + LDR r4, =_tx_thread_current_ptr # Pickup address of current ptr + LDR r5, [r4] # Pickup current thread pointer + +#ifdef __VFP__ + LDR r1, [r5, 144] # Pickup the VFP enabled flag + CMP r1, 0 # Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_save # No, skip VFP solicited save + VMRS r1, FPSCR # Pickup the FPSCR + STR r1, [sp, -4]! # Save FPSCR + VSTMDB sp!, {D16-D31} # Save D16-D31 + VSTMDB sp!, {D8-D15} # Save D8-D15 +_tx_skip_solicited_vfp_save: +#endif + + MOV r0, #0 # Build a solicited stack type + MRS r1, CPSR # Pickup the CPSR + STMDB sp!, {r0-r1} # Save type and CPSR + + /* Lockout interrupts. */ + +#ifdef TX_BEFORE_ARMV6 + ORR r2, r1, DISABLE_INTS # Build disable interrupt CPSR + MSR CPSR_c, r2 # Disable interrupts +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if # Disable IRQ and FIQ interrupts +#else + CPSID i # Disable IRQ interrutps +#endif +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread exit function to indicate the thread is no longer executing. */ + + BL _tx_execution_thread_exit # Call the thread exit function +#endif + + MOV r3, r4 # Pickup address of current ptr + MOV r0, r5 # Pickup current thread pointer + LDR r2, =_tx_timer_time_slice # Pickup address of time slice + LDR r1, [r2] # Pickup current time slice + + /* Save current stack and switch to system stack. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; + sp = _tx_thread_system_stack_ptr; */ + + STR sp, [r0, 8] # Save thread stack pointer + + /* Determine if the time-slice is active. */ + /* if (_tx_timer_time_slice) + { */ + + MOV r4, 0 # Build clear value + CMP r1, 0 # Is a time-slice active? + BEQ __tx_thread_dont_save_ts # No, don't save the current time-slice + + /* Save time-slice for the thread and clear the current time-slice. */ + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + STR r4, [r2, 0] # Clear time-slice + STR r1, [r0, 24] # Save current time-slice + + /* } */ +__tx_thread_dont_save_ts: + + /* Clear the current thread pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + STR r4, [r3] # Clear current thread pointer + B _tx_thread_schedule # Jump to scheduler! + + .type _tx_thread_system_return,$function + .size _tx_thread_system_return,.-_tx_thread_system_return +/* } */ + diff --git a/ports/cortex_a5/green/src/tx_thread_vectored_context_save.arm b/ports/cortex_a5/green/src/tx_thread_vectored_context_save.arm new file mode 100644 index 00000000..df7ab16a --- /dev/null +++ b/ports/cortex_a5/green/src/tx_thread_vectored_context_save.arm @@ -0,0 +1,196 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # IRQ & FIQ interrupts disabled +#else + DISABLE_INTS = 0x80 # IRQ interrupts disabled +#endif + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_vectored_context_save Cortex-A5/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_vectored_context_save(VOID) +{ */ + .globl _tx_thread_vectored_context_save +_tx_thread_vectored_context_save: + + /* Upon entry to this routine, it is assumed that IRQ interrupts are locked + out, we are in IRQ mode, the minimal context is already saved, and the + lr register contains the return ISR address. */ + + /* Check for a nested interrupt condition. */ + /* if (_tx_thread_system_state++) + { */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#ifdef TX_BEFORE_ARMV6 + MRS r0, CPSR # Pickup the CPSR + ORR r0, r0, DISABLE_INTS # Build disable interrupt CPSR + MSR CPSR_c, r0 # Disable interrupts +#else + CPSID if # Disable IRQ and FIQ interrupts +#endif +#endif + LDR r3, =_tx_thread_system_state # Pickup address of system state var + LDR r2, [r3] # Pickup system state + CMP r2, 0 # Is this the first interrupt? + BEQ __tx_thread_not_nested_save # Yes, not a nested context save + + /* Nested interrupt condition. */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + + /* Note: Minimal context of interrupted thread is already saved. */ + + /* Return to the ISR. */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + MOV pc, lr # Return to caller + +__tx_thread_not_nested_save: + /* } */ + + /* Otherwise, not nested, check to see if a thread was running. */ + /* else if (_tx_thread_current_ptr) + { */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup current thread pointer + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_idle_system_save # If so, interrupt occurred in + /* # scheduling loop - nothing needs saving! */ + + /* Note: Minimal context of interrupted thread is already saved. */ + + /* Save the current stack pointer in the thread's control block. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ + + /* Switch to the system stack. */ + /* sp = _tx_thread_system_stack_ptr; */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + MOV pc, lr # Return to caller + + /* } + else + { */ + +__tx_thread_idle_system_save: + + /* Interrupt occurred in the scheduling loop. */ + + /* Not much to do here, just adjust the stack pointer, and return to IRQ + processing. */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + ADD sp, sp, 32 # Recover saved registers + MOV pc, lr # Return to caller + + .type _tx_thread_vectored_context_save,$function + .size _tx_thread_vectored_context_save,.-_tx_thread_vectored_context_save + + /* } +} */ + diff --git a/ports/cortex_a5/green/src/tx_timer_interrupt.arm b/ports/cortex_a5/green/src/tx_timer_interrupt.arm new file mode 100644 index 00000000..336b0176 --- /dev/null +++ b/ports/cortex_a5/green/src/tx_timer_interrupt.arm @@ -0,0 +1,241 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_timer.h" + #include "tx_thread.h" */ + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt Cortex-A5/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Process timer expiration */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_timer_interrupt(VOID) +{ */ + .globl _tx_timer_interrupt +_tx_timer_interrupt: + + /* Upon entry to this routine, it is assumed that context save has already + been called, and therefore the compiler scratch registers are available + for use. */ + + /* Increment the system clock. */ + /* _tx_timer_system_clock++; */ + + LDR r1, =_tx_timer_system_clock # Pickup address of system clock + LDR r0, [r1] # Pickup system clock + ADD r0, r0, 1 # Increment system clock + STR r0, [r1] # Store new system clock + + /* Test for time-slice expiration. */ + /* if (_tx_timer_time_slice) + { */ + + LDR r3, =_tx_timer_time_slice # Pickup address of time-slice + LDR r2, [r3] # Pickup time-slice + CMP r2, 0 # Is it non-active? + BEQ __tx_timer_no_time_slice # Yes, skip time-slice processing + + /* Decrement the time_slice. */ + /* _tx_timer_time_slice--; */ + + SUB r2, r2, 1 # Decrement the time-slice + STR r2, [r3] # Store new time-slice value + + /* Check for expiration. */ + /* if (__tx_timer_time_slice == 0) */ + + CMP r2, 0 # Has it expired? + BNE __tx_timer_no_time_slice # No, skip expiration processing + + /* Set the time-slice expired flag. */ + /* _tx_timer_expired_time_slice = TX_TRUE; */ + + LDR r3,=_tx_timer_expired_time_slice # Pickup address of expired flag + MOV r0, 1 # Build expired value + STR r0, [r3] # Set time-slice expiration flag + + /* } */ + +__tx_timer_no_time_slice: + + /* Test for timer expiration. */ + /* if (*_tx_timer_current_ptr) + { */ + + LDR r1, =_tx_timer_current_ptr # Pickup current timer pointer addr + LDR r0, [r1] # Pickup current timer + LDR r2, [r0] # Pickup timer list entry + CMP r2, 0 # Is there anything in the list? + BEQ __tx_timer_no_timer # No, just increment the timer + + /* Set expiration flag. */ + /* _tx_timer_expired = TX_TRUE; */ + + LDR r3, =_tx_timer_expired # Pickup expiration flag address + MOV r2, 1 # Build expired value + STR r2, [r3] # Set expired flag + B __tx_timer_done # Finished timer processing + + /* } + else + { */ +__tx_timer_no_timer: + + /* No timer expired, increment the timer pointer. */ + /* _tx_timer_current_ptr++; */ + + ADD r0, r0, 4 # Move to next timer + + /* Check for wrap-around. */ + /* if (_tx_timer_current_ptr == _tx_timer_list_end) */ + + LDR r3, =_tx_timer_list_end # Pickup addr of timer list end + LDR r2, [r3] # Pickup list end + CMP r0, r2 # Are we at list end? + BNE __tx_timer_skip_wrap # No, skip wrap-around logic + + /* Wrap to beginning of list. */ + /* _tx_timer_current_ptr = _tx_timer_list_start; */ + + LDR r3, =_tx_timer_list_start # Pickup addr of timer list start + LDR r0, [r3] # Set current pointer to list start + +__tx_timer_skip_wrap: + + STR r0, [r1] # Store new current timer pointer + /* } */ + +__tx_timer_done: + + + /* See if anything has expired. */ + /* if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) + { */ + + LDR r3, =_tx_timer_expired_time_slice # Pickup addr of expired flag + LDR r2, [r3] # Pickup time-slice expired flag + CMP r2, 0 # Did a time-slice expire? + BNE __tx_something_expired # If non-zero, time-slice expired + LDR r1, =_tx_timer_expired # Pickup addr of other expired flag + LDR r0, [r1] # Pickup timer expired flag + CMP r0, 0 # Did a timer expire? + BEQ __tx_timer_nothing_expired # No, nothing expired + +__tx_something_expired: + + + STMDB sp!, {r0, lr} # Save the lr register on the stack + /* # and save r0 just to keep 8-byte alignment */ + + /* Did a timer expire? */ + /* if (_tx_timer_expired) + { */ + + LDR r1, =_tx_timer_expired # Pickup addr of expired flag + LDR r0, [r1] # Pickup timer expired flag + CMP r0, 0 # Check for timer expiration + BEQ __tx_timer_dont_activate # If not set, skip timer activation + + /* Process the timer expiration. */ + /* _tx_timer_expiration_process(); */ + BL _tx_timer_expiration_process # Call the timer expiration handling routine + + /* } */ +__tx_timer_dont_activate: + + /* Did time slice expire? */ + /* if (_tx_timer_expired_time_slice) + { */ + + LDR r3, =_tx_timer_expired_time_slice # Pickup addr of time-slice expired + LDR r2, [r3] # Pickup the actual flag + CMP r2, 0 # See if the flag is set + BEQ __tx_timer_not_ts_expiration # No, skip time-slice processing + + /* Time slice interrupted thread. */ + /* _tx_thread_time_slice(); */ + + BL _tx_thread_time_slice # Call time-slice processing + + /* } */ +__tx_timer_not_ts_expiration: + + + LDMIA sp!, {r0, lr} # Recover lr register (r0 is just there for + /* # the 8-byte stack alignment */ + + /* } */ + +__tx_timer_nothing_expired: + + RET # Return to caller + + .type _tx_timer_interrupt,$function + .size _tx_timer_interrupt,.-_tx_timer_interrupt +/* } */ + diff --git a/ports/cortex_a5/iar/example_build/tx_initialize_low_level.s b/ports/cortex_a5/iar/example_build/tx_initialize_low_level.s index 5369491b..8aaee8f0 100644 --- a/ports/cortex_a5/iar/example_build/tx_initialize_low_level.s +++ b/ports/cortex_a5/iar/example_build/tx_initialize_low_level.s @@ -81,7 +81,7 @@ __tx_free_memory_start ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level Cortex-A5/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -114,7 +114,7 @@ __tx_free_memory_start ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_a5/iar/inc/tx_port.h b/ports/cortex_a5/iar/inc/tx_port.h index 7c107cdf..7d02f22a 100644 --- a/ports/cortex_a5/iar/inc/tx_port.h +++ b/ports/cortex_a5/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A5/IAR */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -380,7 +380,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5/IAR Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5/IAR Version 6.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_a5/iar/readme_threadx.txt b/ports/cortex_a5/iar/readme_threadx.txt index b3b9f85c..fc4d73d2 100644 --- a/ports/cortex_a5/iar/readme_threadx.txt +++ b/ports/cortex_a5/iar/readme_threadx.txt @@ -534,7 +534,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX version 6.0.1 for Cortex-A5 using IAR's ARM tools. +09-30-2020 Initial ThreadX version 6.1 for Cortex-A5 using IAR's ARM tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_a5/iar/src/tx_thread_context_restore.s b/ports/cortex_a5/iar/src/tx_thread_context_restore.s index b212254e..2e432067 100644 --- a/ports/cortex_a5/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_a5/iar/src/tx_thread_context_restore.s @@ -57,7 +57,7 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore Cortex-A5/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -89,7 +89,7 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_a5/iar/src/tx_thread_context_save.s b/ports/cortex_a5/iar/src/tx_thread_context_save.s index 63733553..7f4decd2 100644 --- a/ports/cortex_a5/iar/src/tx_thread_context_save.s +++ b/ports/cortex_a5/iar/src/tx_thread_context_save.s @@ -49,7 +49,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save Cortex-A5/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -80,7 +80,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_a5/iar/src/tx_thread_fiq_context_restore.s b/ports/cortex_a5/iar/src/tx_thread_fiq_context_restore.s index 64a1a9eb..465f9c3d 100644 --- a/ports/cortex_a5/iar/src/tx_thread_fiq_context_restore.s +++ b/ports/cortex_a5/iar/src/tx_thread_fiq_context_restore.s @@ -58,7 +58,7 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_context_restore Cortex-A5/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -90,7 +90,7 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_context_restore(VOID) diff --git a/ports/cortex_a5/iar/src/tx_thread_fiq_context_save.s b/ports/cortex_a5/iar/src/tx_thread_fiq_context_save.s index 22e2d0c7..74beabf7 100644 --- a/ports/cortex_a5/iar/src/tx_thread_fiq_context_save.s +++ b/ports/cortex_a5/iar/src/tx_thread_fiq_context_save.s @@ -42,7 +42,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_context_save Cortex-A5/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -73,7 +73,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ; VOID _tx_thread_fiq_context_save(VOID) diff --git a/ports/cortex_a5/iar/src/tx_thread_fiq_nesting_end.s b/ports/cortex_a5/iar/src/tx_thread_fiq_nesting_end.s index 368cec31..c8e555a3 100644 --- a/ports/cortex_a5/iar/src/tx_thread_fiq_nesting_end.s +++ b/ports/cortex_a5/iar/src/tx_thread_fiq_nesting_end.s @@ -44,7 +44,7 @@ FIQ_MODE_BITS DEFINE 0x11 ; FIQ mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_nesting_end Cortex-A5/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -83,7 +83,7 @@ FIQ_MODE_BITS DEFINE 0x11 ; FIQ mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_end(VOID) diff --git a/ports/cortex_a5/iar/src/tx_thread_fiq_nesting_start.s b/ports/cortex_a5/iar/src/tx_thread_fiq_nesting_start.s index 00f81c4e..551e295c 100644 --- a/ports/cortex_a5/iar/src/tx_thread_fiq_nesting_start.s +++ b/ports/cortex_a5/iar/src/tx_thread_fiq_nesting_start.s @@ -41,7 +41,7 @@ SYS_MODE_BITS DEFINE 0x1F ; System mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_nesting_start Cortex-A5/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ SYS_MODE_BITS DEFINE 0x1F ; System mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/cortex_a5/iar/src/tx_thread_interrupt_control.s b/ports/cortex_a5/iar/src/tx_thread_interrupt_control.s index 76b0d89c..850db901 100644 --- a/ports/cortex_a5/iar/src/tx_thread_interrupt_control.s +++ b/ports/cortex_a5/iar/src/tx_thread_interrupt_control.s @@ -41,7 +41,7 @@ INT_MASK DEFINE 0x80 ; Interrupt bit mask ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control Cortex-A5/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ INT_MASK DEFINE 0x80 ; Interrupt bit mask ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a5/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_a5/iar/src/tx_thread_interrupt_disable.s index b892e436..87c29ff2 100644 --- a/ports/cortex_a5/iar/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_a5/iar/src/tx_thread_interrupt_disable.s @@ -42,7 +42,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_disable Cortex-A5/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports/cortex_a5/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_a5/iar/src/tx_thread_interrupt_restore.s index 84827bbd..a761948c 100644 --- a/ports/cortex_a5/iar/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_a5/iar/src/tx_thread_interrupt_restore.s @@ -34,7 +34,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-A5/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -64,7 +64,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;void _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a5/iar/src/tx_thread_irq_nesting_end.s b/ports/cortex_a5/iar/src/tx_thread_irq_nesting_end.s index 755d2280..87ee0d55 100644 --- a/ports/cortex_a5/iar/src/tx_thread_irq_nesting_end.s +++ b/ports/cortex_a5/iar/src/tx_thread_irq_nesting_end.s @@ -45,7 +45,7 @@ IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_irq_nesting_end Cortex-A5/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -84,7 +84,7 @@ IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports/cortex_a5/iar/src/tx_thread_irq_nesting_start.s b/ports/cortex_a5/iar/src/tx_thread_irq_nesting_start.s index 66ff64dd..b8d05127 100644 --- a/ports/cortex_a5/iar/src/tx_thread_irq_nesting_start.s +++ b/ports/cortex_a5/iar/src/tx_thread_irq_nesting_start.s @@ -41,7 +41,7 @@ SYS_MODE_BITS DEFINE 0x1F ; System mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_irq_nesting_start Cortex-A5/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ SYS_MODE_BITS DEFINE 0x1F ; System mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_a5/iar/src/tx_thread_schedule.s b/ports/cortex_a5/iar/src/tx_thread_schedule.s index 6c07f922..b9cfdfd5 100644 --- a/ports/cortex_a5/iar/src/tx_thread_schedule.s +++ b/ports/cortex_a5/iar/src/tx_thread_schedule.s @@ -49,7 +49,7 @@ ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-A5/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_a5/iar/src/tx_thread_stack_build.s b/ports/cortex_a5/iar/src/tx_thread_stack_build.s index efa63ed9..135c20a8 100644 --- a/ports/cortex_a5/iar/src/tx_thread_stack_build.s +++ b/ports/cortex_a5/iar/src/tx_thread_stack_build.s @@ -43,7 +43,7 @@ CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints en ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build Cortex-A5/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -75,7 +75,7 @@ CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints en ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_a5/iar/src/tx_thread_system_return.s b/ports/cortex_a5/iar/src/tx_thread_system_return.s index 457af6d0..3ecb2b2e 100644 --- a/ports/cortex_a5/iar/src/tx_thread_system_return.s +++ b/ports/cortex_a5/iar/src/tx_thread_system_return.s @@ -48,7 +48,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return Cortex-A5/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -80,7 +80,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_a5/iar/src/tx_thread_vectored_context_save.s b/ports/cortex_a5/iar/src/tx_thread_vectored_context_save.s index 1f363c90..57f03a98 100644 --- a/ports/cortex_a5/iar/src/tx_thread_vectored_context_save.s +++ b/ports/cortex_a5/iar/src/tx_thread_vectored_context_save.s @@ -47,7 +47,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_vectored_context_save Cortex-A5/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -78,7 +78,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) diff --git a/ports/cortex_a5/iar/src/tx_timer_interrupt.s b/ports/cortex_a5/iar/src/tx_timer_interrupt.s index d4b8b35f..7b45d57c 100644 --- a/ports/cortex_a5/iar/src/tx_timer_interrupt.s +++ b/ports/cortex_a5/iar/src/tx_timer_interrupt.s @@ -49,7 +49,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt Cortex-A5/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -83,7 +83,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_a5x/ac6/inc/tx_port.h b/ports/cortex_a5x/ac6/inc/tx_port.h index 33a029ff..82de074d 100644 --- a/ports/cortex_a5x/ac6/inc/tx_port.h +++ b/ports/cortex_a5x/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A5x/ARM */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -354,7 +354,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5x/ARM Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5x/ARM Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a5x/ac6/readme_threadx.txt b/ports/cortex_a5x/ac6/readme_threadx.txt index 6907bd0f..0e3a645a 100644 --- a/ports/cortex_a5x/ac6/readme_threadx.txt +++ b/ports/cortex_a5x/ac6/readme_threadx.txt @@ -245,7 +245,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A5x using ARM tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-A5x using ARM tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_a5x/ac6/src/tx_initialize_low_level.S b/ports/cortex_a5x/ac6/src/tx_initialize_low_level.S index 699a819a..e442a7cc 100644 --- a/ports/cortex_a5x/ac6/src/tx_initialize_low_level.S +++ b/ports/cortex_a5x/ac6/src/tx_initialize_low_level.S @@ -40,7 +40,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_initialize_low_level Cortex-A5x/ARM */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -73,7 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_a5x/ac6/src/tx_thread_context_restore.S b/ports/cortex_a5x/ac6/src/tx_thread_context_restore.S index b8de07ac..c3dbf1e8 100644 --- a/ports/cortex_a5x/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_a5x/ac6/src/tx_thread_context_restore.S @@ -41,7 +41,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore Cortex-A5x/ARM */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -73,7 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_a5x/ac6/src/tx_thread_context_save.S b/ports/cortex_a5x/ac6/src/tx_thread_context_save.S index 88774af3..6d211842 100644 --- a/ports/cortex_a5x/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_a5x/ac6/src/tx_thread_context_save.S @@ -38,7 +38,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save Cortex-A5x/ARM */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,7 +69,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_a5x/ac6/src/tx_thread_fp_disable.c b/ports/cortex_a5x/ac6/src/tx_thread_fp_disable.c index 8a921e86..386cc72e 100644 --- a/ports/cortex_a5x/ac6/src/tx_thread_fp_disable.c +++ b/ports/cortex_a5x/ac6/src/tx_thread_fp_disable.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_fp_disable Cortex-A5x/ARM */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -63,7 +63,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) diff --git a/ports/cortex_a5x/ac6/src/tx_thread_fp_enable.c b/ports/cortex_a5x/ac6/src/tx_thread_fp_enable.c index 818b3e8a..75905772 100644 --- a/ports/cortex_a5x/ac6/src/tx_thread_fp_enable.c +++ b/ports/cortex_a5x/ac6/src/tx_thread_fp_enable.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_fp_enable Cortex-A5x/ARM */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -63,7 +63,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) diff --git a/ports/cortex_a5x/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a5x/ac6/src/tx_thread_interrupt_control.S index 1096b0b8..6e28dd44 100644 --- a/ports/cortex_a5x/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a5x/ac6/src/tx_thread_interrupt_control.S @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control Cortex-A5x/ARM */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,7 +67,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a5x/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a5x/ac6/src/tx_thread_interrupt_disable.S index fb865d66..75d9c799 100644 --- a/ports/cortex_a5x/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a5x/ac6/src/tx_thread_interrupt_disable.S @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable Cortex-A5x/ARM */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -66,7 +66,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* UINT _tx_thread_interrupt_disable(void) diff --git a/ports/cortex_a5x/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a5x/ac6/src/tx_thread_interrupt_restore.S index 336f54f8..9cb6d20e 100644 --- a/ports/cortex_a5x/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a5x/ac6/src/tx_thread_interrupt_restore.S @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore Cortex-A5x/ARM */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,7 +67,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a5x/ac6/src/tx_thread_schedule.S b/ports/cortex_a5x/ac6/src/tx_thread_schedule.S index 7b4e7ff4..97578ee2 100644 --- a/ports/cortex_a5x/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a5x/ac6/src/tx_thread_schedule.S @@ -41,7 +41,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-A5x/ARM */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -74,7 +74,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_a5x/ac6/src/tx_thread_stack_build.S b/ports/cortex_a5x/ac6/src/tx_thread_stack_build.S index cd8609f2..e196df38 100644 --- a/ports/cortex_a5x/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_a5x/ac6/src/tx_thread_stack_build.S @@ -39,7 +39,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build Cortex-A5x/ARM */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_a5x/ac6/src/tx_thread_system_return.S b/ports/cortex_a5x/ac6/src/tx_thread_system_return.S index 5106a801..f220b93b 100644 --- a/ports/cortex_a5x/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a5x/ac6/src/tx_thread_system_return.S @@ -40,7 +40,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return Cortex-A5x/ARM */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_a5x/ac6/src/tx_timer_interrupt.S b/ports/cortex_a5x/ac6/src/tx_timer_interrupt.S index 1559352e..0bb67e5f 100644 --- a/ports/cortex_a5x/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_a5x/ac6/src/tx_timer_interrupt.S @@ -38,7 +38,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt Cortex-A5x/ARM */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_a7/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_a7/ac5/example_build/tx_initialize_low_level.s index f137555a..7020d418 100644 --- a/ports/cortex_a7/ac5/example_build/tx_initialize_low_level.s +++ b/ports/cortex_a7/ac5/example_build/tx_initialize_low_level.s @@ -116,7 +116,7 @@ Reset_Vector ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level Cortex-A7/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -149,7 +149,7 @@ Reset_Vector ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_a7/ac5/inc/tx_port.h b/ports/cortex_a7/ac5/inc/tx_port.h index 9ba22c77..7f3f43bc 100644 --- a/ports/cortex_a7/ac5/inc/tx_port.h +++ b/ports/cortex_a7/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A7/AC5 */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -324,7 +324,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/AC5 Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/AC5 Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a7/ac5/readme_threadx.txt b/ports/cortex_a7/ac5/readme_threadx.txt index 4423047b..48b5a904 100644 --- a/ports/cortex_a7/ac5/readme_threadx.txt +++ b/ports/cortex_a7/ac5/readme_threadx.txt @@ -534,7 +534,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A7 using AC5 tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-A7 using AC5 tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_a7/ac5/src/tx_thread_context_restore.s b/ports/cortex_a7/ac5/src/tx_thread_context_restore.s index 0d03b49c..39a45530 100644 --- a/ports/cortex_a7/ac5/src/tx_thread_context_restore.s +++ b/ports/cortex_a7/ac5/src/tx_thread_context_restore.s @@ -60,7 +60,7 @@ SVC_MODE EQU 0x93 ; SVC mode ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore Cortex-A7/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -92,7 +92,7 @@ SVC_MODE EQU 0x93 ; SVC mode ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_a7/ac5/src/tx_thread_context_save.s b/ports/cortex_a7/ac5/src/tx_thread_context_save.s index 93f1fc52..086437a3 100644 --- a/ports/cortex_a7/ac5/src/tx_thread_context_save.s +++ b/ports/cortex_a7/ac5/src/tx_thread_context_save.s @@ -45,7 +45,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save Cortex-A7/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -76,7 +76,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_a7/ac5/src/tx_thread_fiq_context_restore.s b/ports/cortex_a7/ac5/src/tx_thread_fiq_context_restore.s index fc1c0dfc..9fba762b 100644 --- a/ports/cortex_a7/ac5/src/tx_thread_fiq_context_restore.s +++ b/ports/cortex_a7/ac5/src/tx_thread_fiq_context_restore.s @@ -56,7 +56,7 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_context_restore Cortex-A7/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -88,7 +88,7 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_context_restore(VOID) diff --git a/ports/cortex_a7/ac5/src/tx_thread_fiq_context_save.s b/ports/cortex_a7/ac5/src/tx_thread_fiq_context_save.s index 45b0d4cb..0ac665b1 100644 --- a/ports/cortex_a7/ac5/src/tx_thread_fiq_context_save.s +++ b/ports/cortex_a7/ac5/src/tx_thread_fiq_context_save.s @@ -45,7 +45,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_context_save Cortex-A7/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -76,7 +76,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ; VOID _tx_thread_fiq_context_save(VOID) diff --git a/ports/cortex_a7/ac5/src/tx_thread_fiq_nesting_end.s b/ports/cortex_a7/ac5/src/tx_thread_fiq_nesting_end.s index ce1d8ae2..f36c3d0f 100644 --- a/ports/cortex_a7/ac5/src/tx_thread_fiq_nesting_end.s +++ b/ports/cortex_a7/ac5/src/tx_thread_fiq_nesting_end.s @@ -45,7 +45,7 @@ FIQ_MODE_BITS EQU 0x11 ; FIQ mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_nesting_end Cortex-A7/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -84,7 +84,7 @@ FIQ_MODE_BITS EQU 0x11 ; FIQ mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_end(VOID) diff --git a/ports/cortex_a7/ac5/src/tx_thread_fiq_nesting_start.s b/ports/cortex_a7/ac5/src/tx_thread_fiq_nesting_start.s index 84c344a7..005e8bc2 100644 --- a/ports/cortex_a7/ac5/src/tx_thread_fiq_nesting_start.s +++ b/ports/cortex_a7/ac5/src/tx_thread_fiq_nesting_start.s @@ -41,7 +41,7 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_nesting_start Cortex-A7/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/cortex_a7/ac5/src/tx_thread_interrupt_control.s b/ports/cortex_a7/ac5/src/tx_thread_interrupt_control.s index 717606de..f219c40b 100644 --- a/ports/cortex_a7/ac5/src/tx_thread_interrupt_control.s +++ b/ports/cortex_a7/ac5/src/tx_thread_interrupt_control.s @@ -42,7 +42,7 @@ INT_MASK EQU 0x80 ; Interrupt bit mask ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control Cortex-A7/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ INT_MASK EQU 0x80 ; Interrupt bit mask ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a7/ac5/src/tx_thread_interrupt_disable.s b/ports/cortex_a7/ac5/src/tx_thread_interrupt_disable.s index 70c49171..51f14717 100644 --- a/ports/cortex_a7/ac5/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_a7/ac5/src/tx_thread_interrupt_disable.s @@ -35,7 +35,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_disable Cortex-A7/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -64,7 +64,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(void) diff --git a/ports/cortex_a7/ac5/src/tx_thread_interrupt_restore.s b/ports/cortex_a7/ac5/src/tx_thread_interrupt_restore.s index 5dcb28e6..b18323a3 100644 --- a/ports/cortex_a7/ac5/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_a7/ac5/src/tx_thread_interrupt_restore.s @@ -35,7 +35,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-A7/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -65,7 +65,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a7/ac5/src/tx_thread_irq_nesting_end.s b/ports/cortex_a7/ac5/src/tx_thread_irq_nesting_end.s index 3af929a5..2c090601 100644 --- a/ports/cortex_a7/ac5/src/tx_thread_irq_nesting_end.s +++ b/ports/cortex_a7/ac5/src/tx_thread_irq_nesting_end.s @@ -45,7 +45,7 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_irq_nesting_end Cortex-A7/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -84,7 +84,7 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports/cortex_a7/ac5/src/tx_thread_irq_nesting_start.s b/ports/cortex_a7/ac5/src/tx_thread_irq_nesting_start.s index c1083df4..5f28f0b3 100644 --- a/ports/cortex_a7/ac5/src/tx_thread_irq_nesting_start.s +++ b/ports/cortex_a7/ac5/src/tx_thread_irq_nesting_start.s @@ -41,7 +41,7 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_irq_nesting_start Cortex-A7/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_a7/ac5/src/tx_thread_schedule.s b/ports/cortex_a7/ac5/src/tx_thread_schedule.s index 76ea630f..faf47512 100644 --- a/ports/cortex_a7/ac5/src/tx_thread_schedule.s +++ b/ports/cortex_a7/ac5/src/tx_thread_schedule.s @@ -46,7 +46,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-A7/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -79,7 +79,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_a7/ac5/src/tx_thread_stack_build.s b/ports/cortex_a7/ac5/src/tx_thread_stack_build.s index 965582ab..27a9d929 100644 --- a/ports/cortex_a7/ac5/src/tx_thread_stack_build.s +++ b/ports/cortex_a7/ac5/src/tx_thread_stack_build.s @@ -47,7 +47,7 @@ THUMB_BIT EQU 0x20 ; Thumb-bit ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build Cortex-A7/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -79,7 +79,7 @@ THUMB_BIT EQU 0x20 ; Thumb-bit ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_a7/ac5/src/tx_thread_system_return.s b/ports/cortex_a7/ac5/src/tx_thread_system_return.s index 95eed654..e3029a13 100644 --- a/ports/cortex_a7/ac5/src/tx_thread_system_return.s +++ b/ports/cortex_a7/ac5/src/tx_thread_system_return.s @@ -45,7 +45,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return Cortex-A7/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_a7/ac5/src/tx_thread_vectored_context_save.s b/ports/cortex_a7/ac5/src/tx_thread_vectored_context_save.s index 6237775e..9bae0304 100644 --- a/ports/cortex_a7/ac5/src/tx_thread_vectored_context_save.s +++ b/ports/cortex_a7/ac5/src/tx_thread_vectored_context_save.s @@ -44,7 +44,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_vectored_context_save Cortex-A7/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -75,7 +75,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) diff --git a/ports/cortex_a7/ac5/src/tx_timer_interrupt.s b/ports/cortex_a7/ac5/src/tx_timer_interrupt.s index eb23279f..c0c10196 100644 --- a/ports/cortex_a7/ac5/src/tx_timer_interrupt.s +++ b/ports/cortex_a7/ac5/src/tx_timer_interrupt.s @@ -50,7 +50,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt Cortex-A7/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -84,7 +84,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_a7/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_a7/ac6/example_build/sample_threadx/tx_initialize_low_level.S index c290d1c4..304e84f1 100644 --- a/ports/cortex_a7/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports/cortex_a7/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -75,7 +75,7 @@ $_tx_initialize_low_level: @/* FUNCTION RELEASE */ @/* */ @/* _tx_initialize_low_level Cortex-A7/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -108,7 +108,7 @@ $_tx_initialize_low_level: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_a7/ac6/inc/tx_port.h b/ports/cortex_a7/ac6/inc/tx_port.h index 282c5ed0..b418ea3b 100644 --- a/ports/cortex_a7/ac6/inc/tx_port.h +++ b/ports/cortex_a7/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A7/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -313,7 +313,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/AC6 Version 6.0.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/AC6 Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a7/ac6/readme_threadx.txt b/ports/cortex_a7/ac6/readme_threadx.txt index 26861000..82503ec4 100644 --- a/ports/cortex_a7/ac6/readme_threadx.txt +++ b/ports/cortex_a7/ac6/readme_threadx.txt @@ -332,7 +332,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A7 using AC6 tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-A7 using AC6 tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_a7/ac6/src/tx_thread_context_restore.S b/ports/cortex_a7/ac6/src/tx_thread_context_restore.S index 8611279e..5b33d05d 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_a7/ac6/src/tx_thread_context_restore.S @@ -59,7 +59,7 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_restore Cortex-A7/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -91,7 +91,7 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_a7/ac6/src/tx_thread_context_save.S b/ports/cortex_a7/ac6/src/tx_thread_context_save.S index 126f5417..6b4805cb 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_a7/ac6/src/tx_thread_context_save.S @@ -47,7 +47,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_save Cortex-A7/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -78,7 +78,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_a7/ac6/src/tx_thread_fiq_context_restore.S b/ports/cortex_a7/ac6/src/tx_thread_fiq_context_restore.S index 3130be5a..4e301b41 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_a7/ac6/src/tx_thread_fiq_context_restore.S @@ -58,7 +58,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_context_restore Cortex-A7/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -90,7 +90,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_context_restore(VOID) diff --git a/ports/cortex_a7/ac6/src/tx_thread_fiq_context_save.S b/ports/cortex_a7/ac6/src/tx_thread_fiq_context_save.S index 7ffdb84d..c1972325 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_a7/ac6/src/tx_thread_fiq_context_save.S @@ -46,7 +46,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_context_save Cortex-A7/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @ VOID _tx_thread_fiq_context_save(VOID) diff --git a/ports/cortex_a7/ac6/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a7/ac6/src/tx_thread_fiq_nesting_end.S index 9965a19b..505a4878 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a7/ac6/src/tx_thread_fiq_nesting_end.S @@ -50,7 +50,7 @@ FIQ_MODE_BITS = 0x11 @ FIQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_nesting_end Cortex-A7/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -89,7 +89,7 @@ FIQ_MODE_BITS = 0x11 @ FIQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_end(VOID) diff --git a/ports/cortex_a7/ac6/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a7/ac6/src/tx_thread_fiq_nesting_start.S index 83082588..43754d60 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a7/ac6/src/tx_thread_fiq_nesting_start.S @@ -46,7 +46,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_nesting_start Cortex-A7/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/cortex_a7/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a7/ac6/src/tx_thread_interrupt_control.S index cabd14cc..94d09fcd 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a7/ac6/src/tx_thread_interrupt_control.S @@ -56,7 +56,7 @@ $_tx_thread_interrupt_control: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_control Cortex-A7/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -86,7 +86,7 @@ $_tx_thread_interrupt_control: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a7/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a7/ac6/src/tx_thread_interrupt_disable.S index 3774e330..bf82e314 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a7/ac6/src/tx_thread_interrupt_disable.S @@ -53,7 +53,7 @@ $_tx_thread_interrupt_disable: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_disable Cortex-A7/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ $_tx_thread_interrupt_disable: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_disable(void) diff --git a/ports/cortex_a7/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a7/ac6/src/tx_thread_interrupt_restore.S index ca9f64c1..2f402e34 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a7/ac6/src/tx_thread_interrupt_restore.S @@ -53,7 +53,7 @@ $_tx_thread_interrupt_restore: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_restore Cortex-A7/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -83,7 +83,7 @@ $_tx_thread_interrupt_restore: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a7/ac6/src/tx_thread_irq_nesting_end.S b/ports/cortex_a7/ac6/src/tx_thread_irq_nesting_end.S index 14a4ce8c..0081073b 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a7/ac6/src/tx_thread_irq_nesting_end.S @@ -50,7 +50,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_irq_nesting_end Cortex-A7/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -89,7 +89,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports/cortex_a7/ac6/src/tx_thread_irq_nesting_start.S b/ports/cortex_a7/ac6/src/tx_thread_irq_nesting_start.S index 9126b19c..ef976b80 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a7/ac6/src/tx_thread_irq_nesting_start.S @@ -46,7 +46,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_irq_nesting_start Cortex-A7/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_a7/ac6/src/tx_thread_schedule.S b/ports/cortex_a7/ac6/src/tx_thread_schedule.S index e2bdd523..cdb0a24f 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a7/ac6/src/tx_thread_schedule.S @@ -61,7 +61,7 @@ $_tx_thread_schedule: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule Cortex-A7/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -94,7 +94,7 @@ $_tx_thread_schedule: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_a7/ac6/src/tx_thread_stack_build.S b/ports/cortex_a7/ac6/src/tx_thread_stack_build.S index 1c5f597f..8598428e 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_a7/ac6/src/tx_thread_stack_build.S @@ -64,7 +64,7 @@ $_tx_thread_stack_build: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_stack_build Cortex-A7/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -96,7 +96,7 @@ $_tx_thread_stack_build: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_a7/ac6/src/tx_thread_system_return.S b/ports/cortex_a7/ac6/src/tx_thread_system_return.S index 4aca258c..a1ca92b9 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a7/ac6/src/tx_thread_system_return.S @@ -63,7 +63,7 @@ $_tx_thread_system_return: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_system_return Cortex-A7/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -95,7 +95,7 @@ $_tx_thread_system_return: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_a7/ac6/src/tx_thread_vectored_context_save.S b/ports/cortex_a7/ac6/src/tx_thread_vectored_context_save.S index 140807c1..ef7c07d2 100644 --- a/ports/cortex_a7/ac6/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_a7/ac6/src/tx_thread_vectored_context_save.S @@ -46,7 +46,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_vectored_context_save Cortex-A7/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_vectored_context_save(VOID) diff --git a/ports/cortex_a7/ac6/src/tx_timer_interrupt.S b/ports/cortex_a7/ac6/src/tx_timer_interrupt.S index b057387c..907de9f8 100644 --- a/ports/cortex_a7/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_a7/ac6/src/tx_timer_interrupt.S @@ -71,7 +71,7 @@ $_tx_timer_interrupt: @/* FUNCTION RELEASE */ @/* */ @/* _tx_timer_interrupt Cortex-A7/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -105,7 +105,7 @@ $_tx_timer_interrupt: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_a7/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_a7/gnu/example_build/tx_initialize_low_level.S index 6138b610..7d2ac9b7 100644 --- a/ports/cortex_a7/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_a7/gnu/example_build/tx_initialize_low_level.S @@ -78,7 +78,7 @@ $_tx_initialize_low_level: @/* FUNCTION RELEASE */ @/* */ @/* _tx_initialize_low_level Cortex-A7/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -111,7 +111,7 @@ $_tx_initialize_low_level: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_a7/gnu/inc/tx_port.h b/ports/cortex_a7/gnu/inc/tx_port.h index 07221bb7..997dd446 100644 --- a/ports/cortex_a7/gnu/inc/tx_port.h +++ b/ports/cortex_a7/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A7/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -313,7 +313,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/GNU Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/GNU Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a7/gnu/readme_threadx.txt b/ports/cortex_a7/gnu/readme_threadx.txt index f56a131e..b7186b39 100644 --- a/ports/cortex_a7/gnu/readme_threadx.txt +++ b/ports/cortex_a7/gnu/readme_threadx.txt @@ -503,7 +503,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A7 using GNU tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-A7 using GNU tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_a7/gnu/src/tx_thread_context_restore.S b/ports/cortex_a7/gnu/src/tx_thread_context_restore.S index 1a90baaf..9021e57c 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a7/gnu/src/tx_thread_context_restore.S @@ -60,7 +60,7 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_restore Cortex-A7/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -92,7 +92,7 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_a7/gnu/src/tx_thread_context_save.S b/ports/cortex_a7/gnu/src/tx_thread_context_save.S index 0535151c..ddb7698e 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a7/gnu/src/tx_thread_context_save.S @@ -48,7 +48,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_save Cortex-A7/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -79,7 +79,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_a7/gnu/src/tx_thread_fiq_context_restore.S b/ports/cortex_a7/gnu/src/tx_thread_fiq_context_restore.S index b7ce5f4e..c0b14e8f 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_a7/gnu/src/tx_thread_fiq_context_restore.S @@ -59,7 +59,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_context_restore Cortex-A7/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -91,7 +91,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_context_restore(VOID) diff --git a/ports/cortex_a7/gnu/src/tx_thread_fiq_context_save.S b/ports/cortex_a7/gnu/src/tx_thread_fiq_context_save.S index 16ff6eb6..172d361f 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_a7/gnu/src/tx_thread_fiq_context_save.S @@ -47,7 +47,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_context_save Cortex-A7/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -78,7 +78,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @ VOID _tx_thread_fiq_context_save(VOID) diff --git a/ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_end.S index f4dbedda..2df342b3 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_end.S @@ -50,7 +50,7 @@ FIQ_MODE_BITS = 0x11 @ FIQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_nesting_end Cortex-A7/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -89,7 +89,7 @@ FIQ_MODE_BITS = 0x11 @ FIQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_end(VOID) diff --git a/ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_start.S index ac18c99a..1028d4cf 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_start.S @@ -46,7 +46,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_nesting_start Cortex-A7/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/cortex_a7/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a7/gnu/src/tx_thread_interrupt_control.S index 453a6b43..e3825784 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a7/gnu/src/tx_thread_interrupt_control.S @@ -56,7 +56,7 @@ $_tx_thread_interrupt_control: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_control Cortex-A7/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -86,7 +86,7 @@ $_tx_thread_interrupt_control: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a7/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a7/gnu/src/tx_thread_interrupt_disable.S index 64721b51..bb62310b 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a7/gnu/src/tx_thread_interrupt_disable.S @@ -53,7 +53,7 @@ $_tx_thread_interrupt_disable: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_disable Cortex-A7/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ $_tx_thread_interrupt_disable: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_disable(void) diff --git a/ports/cortex_a7/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a7/gnu/src/tx_thread_interrupt_restore.S index 8bae905a..f914fc31 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a7/gnu/src/tx_thread_interrupt_restore.S @@ -53,7 +53,7 @@ $_tx_thread_interrupt_restore: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_restore Cortex-A7/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -83,7 +83,7 @@ $_tx_thread_interrupt_restore: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a7/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_a7/gnu/src/tx_thread_irq_nesting_end.S index c62e38e1..61414de8 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a7/gnu/src/tx_thread_irq_nesting_end.S @@ -50,7 +50,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_irq_nesting_end Cortex-A7/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -89,7 +89,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports/cortex_a7/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_a7/gnu/src/tx_thread_irq_nesting_start.S index 4e2fd962..4d606250 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a7/gnu/src/tx_thread_irq_nesting_start.S @@ -46,7 +46,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_irq_nesting_start Cortex-A7/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_a7/gnu/src/tx_thread_schedule.S b/ports/cortex_a7/gnu/src/tx_thread_schedule.S index f0e20b7e..7bcff023 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a7/gnu/src/tx_thread_schedule.S @@ -62,7 +62,7 @@ $_tx_thread_schedule: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule Cortex-A7/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -95,7 +95,7 @@ $_tx_thread_schedule: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_a7/gnu/src/tx_thread_stack_build.S b/ports/cortex_a7/gnu/src/tx_thread_stack_build.S index 6c89ae45..b4809307 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a7/gnu/src/tx_thread_stack_build.S @@ -64,7 +64,7 @@ $_tx_thread_stack_build: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_stack_build Cortex-A7/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -96,7 +96,7 @@ $_tx_thread_stack_build: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_a7/gnu/src/tx_thread_system_return.S b/ports/cortex_a7/gnu/src/tx_thread_system_return.S index 5c2047b4..386b2c06 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a7/gnu/src/tx_thread_system_return.S @@ -64,7 +64,7 @@ $_tx_thread_system_return: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_system_return Cortex-A7/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -96,7 +96,7 @@ $_tx_thread_system_return: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_a7/gnu/src/tx_thread_vectored_context_save.S b/ports/cortex_a7/gnu/src/tx_thread_vectored_context_save.S index b01f9190..7713d339 100644 --- a/ports/cortex_a7/gnu/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_a7/gnu/src/tx_thread_vectored_context_save.S @@ -47,7 +47,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_vectored_context_save Cortex-A7/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -78,7 +78,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_vectored_context_save(VOID) diff --git a/ports/cortex_a7/gnu/src/tx_timer_interrupt.S b/ports/cortex_a7/gnu/src/tx_timer_interrupt.S index bf58c2ee..1b8f37df 100644 --- a/ports/cortex_a7/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a7/gnu/src/tx_timer_interrupt.S @@ -71,7 +71,7 @@ $_tx_timer_interrupt: @/* FUNCTION RELEASE */ @/* */ @/* _tx_timer_interrupt Cortex-A7/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -105,7 +105,7 @@ $_tx_timer_interrupt: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_a7/green/example_build/azure_rtos_workspace.gpj b/ports/cortex_a7/green/example_build/azure_rtos_workspace.gpj new file mode 100644 index 00000000..dfeae879 --- /dev/null +++ b/ports/cortex_a7/green/example_build/azure_rtos_workspace.gpj @@ -0,0 +1,12 @@ +#!gbuild +primaryTarget=arm_standalone.tgt +[Project] + -bsp generic + -G + -cpu=cortexa7 + -littleendian +sample_threadx.gpj [Program] +sample_threadx_el.gpj [Program] +tx.gpj [Library] +txe.gpj [Library] +..\readme_threadx.txt diff --git a/ports/cortex_a7/green/example_build/reset.arm b/ports/cortex_a7/green/example_build/reset.arm new file mode 100644 index 00000000..8bb5bff6 --- /dev/null +++ b/ports/cortex_a7/green/example_build/reset.arm @@ -0,0 +1,45 @@ +# +# +#/* Define the Cortex-A7 vector area. This should be located or copied to 0. */ +# + + .section ".reset", .text + .globl __vectors +__vectors: + B __entry # Reset goes to the entry function + LDR pc,UNDEFINED # Undefined handler + LDR pc,SWI # Software interrupt handler + LDR pc,PREFETCH # Prefetch exception handler + LDR pc,ABORT # Abort exception handler + LDR pc,RESERVED # Reserved exception handler + LDR pc,IRQ # IRQ interrupt handler + LDR pc,FIQ # FIQ interrupt handler +# +# +__entry: + LDR sp,STACK # Setup stack pointer + LDR pc,START # Jump to Green Hills startup +# +# +STACK: + .data.w __ghsend_stack +START: + .data.w _start # Reset goes to startup function +UNDEFINED: + .data.w __tx_undefined # Undefined handler +SWI: + .data.w __tx_swi_interrupt # Software interrupt handler +PREFETCH: + .data.w __tx_prefetch_handler # Prefetch exception handler +ABORT: + .data.w __tx_abort_handler # Abort exception handler +RESERVED: + .data.w __tx_reserved_handler # Reserved exception handler +IRQ: + .data.w __tx_irq_handler # IRQ interrupt handler +FIQ: + .data.w __tx_fiq_handler # FIQ interrupt handler +# +# + .type __vectors,$function + .size __vectors,.-__vectors diff --git a/ports/cortex_a7/green/example_build/sample_threadx.c b/ports/cortex_a7/green/example_build/sample_threadx.c new file mode 100644 index 00000000..418ec634 --- /dev/null +++ b/ports/cortex_a7/green/example_build/sample_threadx.c @@ -0,0 +1,369 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_a7/green/example_build/sample_threadx.con b/ports/cortex_a7/green/example_build/sample_threadx.con new file mode 100644 index 00000000..70f51196 --- /dev/null +++ b/ports/cortex_a7/green/example_build/sample_threadx.con @@ -0,0 +1,11 @@ +target_connection.00000000.title="Simulator connection for ThreadX" +target_connection.00000000.type="Custom" +target_connection.00000000.short_type="Custom" +target_connection.00000000.args="simarm -cpu=cortexa7 -fpu -rom" +target_connection.00000000.command="simarm -cpu=cortexa7 -fpu -rom" +target_connection.00000000.logfile="" +target_connection.00000000.mode="download" +target_connection.00000000.setup_script="" +target_connection.00000000.sane="yes" +target_connection.00000000.log="no" +target_connection.00000000.timestamp="1192825758" diff --git a/ports/cortex_a7/green/example_build/sample_threadx.gpj b/ports/cortex_a7/green/example_build/sample_threadx.gpj new file mode 100644 index 00000000..b9b2c04c --- /dev/null +++ b/ports/cortex_a7/green/example_build/sample_threadx.gpj @@ -0,0 +1,11 @@ +#!gbuild +[Program] + -I../../../../common/inc + -I../../../../ports_common_green/inc + -I../inc +reset.arm +tx_initialize_low_level.arm +sample_threadx.c +tx.a +sample_threadx.ld +sample_threadx.con diff --git a/ports/cortex_a7/green/example_build/sample_threadx.ld b/ports/cortex_a7/green/example_build/sample_threadx.ld new file mode 100644 index 00000000..8d1ab4df --- /dev/null +++ b/ports/cortex_a7/green/example_build/sample_threadx.ld @@ -0,0 +1,44 @@ +# The following explains what the default Green Hills sections are for: +# +# picbase - base of the text sections, relocatable in -pic mode +# text - text section +# syscall - syscall section, for host I/O under Multi +# fixaddr/fixtype - for PIC/PID fixups +# rodata - read only data +# romdata - the ROM image of .data +# romsdata - the ROM image of .sdata +# secinfo - section information section, used by the start-up code +# pidbase - base of the data sections, relocatable in -pid mode +# sdabase - base of the small data area section pointer +# sbss - small BSS (zeroed data) section +# sdata - small data section +# data - non-zeroed writeable data section +# bss - zeroed data section +# heap - the heap, grows upward +# stack - the stack, grows downward + +-sec +{ + .reset 0x000000 : + .picbase 0x1000 : + .text : + .comment : + .intercall : + .interfunc : + .syscall : + .fixaddr : + .fixtype : + .rodata : + .romdata ROM(.data) : + .romsdata ROM(.sdata) : + .secinfo : + .pidbase align(16) : + .sdabase : + .sbss : + .sdata : + .data : + .bss : + .heap align(16) pad(0x10000) : + .stack align(16) pad(0x1000) : + .free_mem align(16) pad(0x10000) : +} diff --git a/ports/cortex_a7/green/example_build/sample_threadx_el.gpj b/ports/cortex_a7/green/example_build/sample_threadx_el.gpj new file mode 100644 index 00000000..a51049ca --- /dev/null +++ b/ports/cortex_a7/green/example_build/sample_threadx_el.gpj @@ -0,0 +1,13 @@ +#!gbuild +[Program] + -DTX_ENABLE_EVENT_LOGGING + -I../../../../common/inc + -I../../../../ports_common_green/inc + -I../inc +reset.arm +tx_initialize_low_level.arm +sample_threadx.c +txe.a +sample_threadx_el.ld +sample_threadx.con +readme_threadx.txt diff --git a/ports/cortex_a7/green/example_build/sample_threadx_el.ld b/ports/cortex_a7/green/example_build/sample_threadx_el.ld new file mode 100644 index 00000000..33c0f934 --- /dev/null +++ b/ports/cortex_a7/green/example_build/sample_threadx_el.ld @@ -0,0 +1,45 @@ +# The following explains what the default Green Hills sections are for: +# +# picbase - base of the text sections, relocatable in -pic mode +# text - text section +# syscall - syscall section, for host I/O under Multi +# fixaddr/fixtype - for PIC/PID fixups +# rodata - read only data +# romdata - the ROM image of .data +# romsdata - the ROM image of .sdata +# secinfo - section information section, used by the start-up code +# pidbase - base of the data sections, relocatable in -pid mode +# sdabase - base of the small data area section pointer +# sbss - small BSS (zeroed data) section +# sdata - small data section +# data - non-zeroed writeable data section +# bss - zeroed data section +# heap - the heap, grows upward +# stack - the stack, grows downward + +-sec +{ + .reset 0x000000 : + .picbase 0x1000 : + .text : + .comment : + .intercall : + .interfunc : + .syscall : + .fixaddr : + .fixtype : + .rodata : + .romdata ROM(.data) : + .romsdata ROM(.sdata) : + .secinfo : + .pidbase align(16) : + .sdabase : + .sbss : + .sdata : + .data : + .bss : + .heap align(16) pad(0x1000) : + .stack align(16) pad(0x1000) : + .eventlog align(16) pad(0x10000) : + .free_mem align(16) pad(0x10000) : +} diff --git a/ports/cortex_a7/green/example_build/tx.gpj b/ports/cortex_a7/green/example_build/tx.gpj new file mode 100644 index 00000000..afbd6bef --- /dev/null +++ b/ports/cortex_a7/green/example_build/tx.gpj @@ -0,0 +1,283 @@ +#!gbuild +[Library] + -I../../../../common/inc + -I../../../../ports_common_green/inc + -I../inc +..\..\..\..\common\inc\tx_api.h +..\..\..\..\common\inc\tx_block_pool.h +..\..\..\..\common\inc\tx_byte_pool.h +..\..\..\..\common\inc\tx_event_flags.h +..\..\..\..\common\inc\tx_initialize.h +..\..\..\..\common\inc\tx_mutex.h +..\..\..\..\common\inc\tx_queue.h +..\..\..\..\common\inc\tx_semaphore.h +..\..\..\..\common\inc\tx_thread.h +..\..\..\..\common\inc\tx_timer.h +..\..\..\..\common\inc\tx_trace.h +..\..\..\..\common\inc\tx_user_sample.h +..\inc\tx_port.h +..\..\..\..\ports_common_green\inc\tx_el.h +..\..\..\..\ports_common_green\inc\tx_ghs.h +..\src\tx_thread_context_restore.arm +..\src\tx_thread_context_save.arm +..\src\tx_thread_fiq_context_restore.arm +..\src\tx_thread_fiq_context_save.arm +..\src\tx_thread_fiq_nesting_end.arm +..\src\tx_thread_fiq_nesting_start.arm +..\src\tx_thread_interrupt_control.arm +..\src\tx_thread_interrupt_disable.arm +..\src\tx_thread_interrupt_restore.arm +..\src\tx_thread_irq_nesting_end.arm +..\src\tx_thread_irq_nesting_start.arm +..\src\tx_thread_schedule.arm +..\src\tx_thread_stack_build.arm +..\src\tx_thread_system_return.arm +..\src\tx_thread_vectored_context_save.arm +..\src\tx_timer_interrupt.arm +..\..\..\..\common\src\tx_block_allocate.c +..\..\..\..\common\src\tx_block_pool_cleanup.c +..\..\..\..\common\src\tx_block_pool_create.c +..\..\..\..\common\src\tx_block_pool_delete.c +..\..\..\..\common\src\tx_block_pool_info_get.c +..\..\..\..\common\src\tx_block_pool_initialize.c +..\..\..\..\common\src\tx_block_pool_performance_info_get.c +..\..\..\..\common\src\tx_block_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_block_pool_prioritize.c +..\..\..\..\common\src\tx_block_release.c +..\..\..\..\common\src\tx_byte_allocate.c +..\..\..\..\common\src\tx_byte_pool_cleanup.c +..\..\..\..\common\src\tx_byte_pool_create.c +..\..\..\..\common\src\tx_byte_pool_delete.c +..\..\..\..\common\src\tx_byte_pool_info_get.c +..\..\..\..\common\src\tx_byte_pool_initialize.c +..\..\..\..\common\src\tx_byte_pool_performance_info_get.c +..\..\..\..\common\src\tx_byte_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_byte_pool_prioritize.c +..\..\..\..\common\src\tx_byte_pool_search.c +..\..\..\..\common\src\tx_byte_release.c +..\..\..\..\common\src\tx_event_flags_cleanup.c +..\..\..\..\common\src\tx_event_flags_create.c +..\..\..\..\common\src\tx_event_flags_delete.c +..\..\..\..\common\src\tx_event_flags_get.c +..\..\..\..\common\src\tx_event_flags_info_get.c +..\..\..\..\common\src\tx_event_flags_initialize.c +..\..\..\..\common\src\tx_event_flags_performance_info_get.c +..\..\..\..\common\src\tx_event_flags_performance_system_info_get.c +..\..\..\..\common\src\tx_event_flags_set.c +..\..\..\..\common\src\tx_event_flags_set_notify.c +..\..\..\..\common\src\tx_initialize_high_level.c +..\..\..\..\common\src\tx_initialize_kernel_enter.c +..\..\..\..\common\src\tx_initialize_kernel_setup.c +..\..\..\..\common\src\tx_mutex_cleanup.c +..\..\..\..\common\src\tx_mutex_create.c +..\..\..\..\common\src\tx_mutex_delete.c +..\..\..\..\common\src\tx_mutex_get.c +..\..\..\..\common\src\tx_mutex_info_get.c +..\..\..\..\common\src\tx_mutex_initialize.c +..\..\..\..\common\src\tx_mutex_performance_info_get.c +..\..\..\..\common\src\tx_mutex_performance_system_info_get.c +..\..\..\..\common\src\tx_mutex_prioritize.c +..\..\..\..\common\src\tx_mutex_priority_change.c +..\..\..\..\common\src\tx_mutex_put.c +..\..\..\..\common\src\tx_queue_cleanup.c +..\..\..\..\common\src\tx_queue_create.c +..\..\..\..\common\src\tx_queue_delete.c +..\..\..\..\common\src\tx_queue_flush.c +..\..\..\..\common\src\tx_queue_front_send.c +..\..\..\..\common\src\tx_queue_info_get.c +..\..\..\..\common\src\tx_queue_initialize.c +..\..\..\..\common\src\tx_queue_performance_info_get.c +..\..\..\..\common\src\tx_queue_performance_system_info_get.c +..\..\..\..\common\src\tx_queue_prioritize.c +..\..\..\..\common\src\tx_queue_receive.c +..\..\..\..\common\src\tx_queue_send.c +..\..\..\..\common\src\tx_queue_send_notify.c +..\..\..\..\common\src\tx_semaphore_ceiling_put.c +..\..\..\..\common\src\tx_semaphore_cleanup.c +..\..\..\..\common\src\tx_semaphore_create.c +..\..\..\..\common\src\tx_semaphore_delete.c +..\..\..\..\common\src\tx_semaphore_get.c +..\..\..\..\common\src\tx_semaphore_info_get.c +..\..\..\..\common\src\tx_semaphore_initialize.c +..\..\..\..\common\src\tx_semaphore_performance_info_get.c +..\..\..\..\common\src\tx_semaphore_performance_system_info_get.c +..\..\..\..\common\src\tx_semaphore_prioritize.c +..\..\..\..\common\src\tx_semaphore_put.c +..\..\..\..\common\src\tx_semaphore_put_notify.c +..\..\..\..\common\src\tx_thread_create.c +..\..\..\..\common\src\tx_thread_delete.c +..\..\..\..\common\src\tx_thread_entry_exit_notify.c +..\..\..\..\common\src\tx_thread_identify.c +..\..\..\..\common\src\tx_thread_info_get.c +..\..\..\..\common\src\tx_thread_initialize.c +..\..\..\..\common\src\tx_thread_performance_info_get.c +..\..\..\..\common\src\tx_thread_performance_system_info_get.c +..\..\..\..\common\src\tx_thread_preemption_change.c +..\..\..\..\common\src\tx_thread_priority_change.c +..\..\..\..\common\src\tx_thread_relinquish.c +..\..\..\..\common\src\tx_thread_reset.c +..\..\..\..\common\src\tx_thread_resume.c +..\..\..\..\common\src\tx_thread_shell_entry.c +..\..\..\..\common\src\tx_thread_sleep.c +..\..\..\..\common\src\tx_thread_stack_analyze.c +..\..\..\..\common\src\tx_thread_stack_error_handler.c +..\..\..\..\common\src\tx_thread_stack_error_notify.c +..\..\..\..\common\src\tx_thread_suspend.c +..\..\..\..\common\src\tx_thread_system_preempt_check.c +..\..\..\..\common\src\tx_thread_system_resume.c +..\..\..\..\common\src\tx_thread_system_suspend.c +..\..\..\..\common\src\tx_thread_terminate.c +..\..\..\..\common\src\tx_thread_time_slice.c +..\..\..\..\common\src\tx_thread_time_slice_change.c +..\..\..\..\common\src\tx_thread_timeout.c +..\..\..\..\common\src\tx_thread_wait_abort.c +..\..\..\..\common\src\tx_time_get.c +..\..\..\..\common\src\tx_time_set.c +..\..\..\..\common\src\tx_timer_activate.c +..\..\..\..\common\src\tx_timer_change.c +..\..\..\..\common\src\tx_timer_create.c +..\..\..\..\common\src\tx_timer_deactivate.c +..\..\..\..\common\src\tx_timer_delete.c +..\..\..\..\common\src\tx_timer_expiration_process.c +..\..\..\..\common\src\tx_timer_info_get.c +..\..\..\..\common\src\tx_timer_initialize.c +..\..\..\..\common\src\tx_timer_performance_info_get.c +..\..\..\..\common\src\tx_timer_performance_system_info_get.c +..\..\..\..\common\src\tx_timer_system_activate.c +..\..\..\..\common\src\tx_timer_system_deactivate.c +..\..\..\..\common\src\tx_timer_thread_entry.c +..\..\..\..\common\src\tx_trace_buffer_full_notify.c +..\..\..\..\common\src\tx_trace_disable.c +..\..\..\..\common\src\tx_trace_enable.c +..\..\..\..\common\src\tx_trace_event_filter.c +..\..\..\..\common\src\tx_trace_event_unfilter.c +..\..\..\..\common\src\tx_trace_initialize.c +..\..\..\..\common\src\tx_trace_interrupt_control.c +..\..\..\..\common\src\tx_trace_isr_enter_insert.c +..\..\..\..\common\src\tx_trace_isr_exit_insert.c +..\..\..\..\common\src\tx_trace_object_register.c +..\..\..\..\common\src\tx_trace_object_unregister.c +..\..\..\..\common\src\tx_trace_user_event_insert.c +..\..\..\..\common\src\txe_block_allocate.c +..\..\..\..\common\src\txe_block_pool_create.c +..\..\..\..\common\src\txe_block_pool_delete.c +..\..\..\..\common\src\txe_block_pool_info_get.c +..\..\..\..\common\src\txe_block_pool_prioritize.c +..\..\..\..\common\src\txe_block_release.c +..\..\..\..\common\src\txe_byte_allocate.c +..\..\..\..\common\src\txe_byte_pool_create.c +..\..\..\..\common\src\txe_byte_pool_delete.c +..\..\..\..\common\src\txe_byte_pool_info_get.c +..\..\..\..\common\src\txe_byte_pool_prioritize.c +..\..\..\..\common\src\txe_byte_release.c +..\..\..\..\common\src\txe_event_flags_create.c +..\..\..\..\common\src\txe_event_flags_delete.c +..\..\..\..\common\src\txe_event_flags_get.c +..\..\..\..\common\src\txe_event_flags_info_get.c +..\..\..\..\common\src\txe_event_flags_set.c +..\..\..\..\common\src\txe_event_flags_set_notify.c +..\..\..\..\common\src\txe_mutex_create.c +..\..\..\..\common\src\txe_mutex_delete.c +..\..\..\..\common\src\txe_mutex_get.c +..\..\..\..\common\src\txe_mutex_info_get.c +..\..\..\..\common\src\txe_mutex_prioritize.c +..\..\..\..\common\src\txe_mutex_put.c +..\..\..\..\common\src\txe_queue_create.c +..\..\..\..\common\src\txe_queue_delete.c +..\..\..\..\common\src\txe_queue_flush.c +..\..\..\..\common\src\txe_queue_front_send.c +..\..\..\..\common\src\txe_queue_info_get.c +..\..\..\..\common\src\txe_queue_prioritize.c +..\..\..\..\common\src\txe_queue_receive.c +..\..\..\..\common\src\txe_queue_send.c +..\..\..\..\common\src\txe_queue_send_notify.c +..\..\..\..\common\src\txe_semaphore_ceiling_put.c +..\..\..\..\common\src\txe_semaphore_create.c +..\..\..\..\common\src\txe_semaphore_delete.c +..\..\..\..\common\src\txe_semaphore_get.c +..\..\..\..\common\src\txe_semaphore_info_get.c +..\..\..\..\common\src\txe_semaphore_prioritize.c +..\..\..\..\common\src\txe_semaphore_put.c +..\..\..\..\common\src\txe_semaphore_put_notify.c +..\..\..\..\common\src\txe_thread_create.c +..\..\..\..\common\src\txe_thread_delete.c +..\..\..\..\common\src\txe_thread_entry_exit_notify.c +..\..\..\..\common\src\txe_thread_info_get.c +..\..\..\..\common\src\txe_thread_preemption_change.c +..\..\..\..\common\src\txe_thread_priority_change.c +..\..\..\..\common\src\txe_thread_relinquish.c +..\..\..\..\common\src\txe_thread_reset.c +..\..\..\..\common\src\txe_thread_resume.c +..\..\..\..\common\src\txe_thread_suspend.c +..\..\..\..\common\src\txe_thread_terminate.c +..\..\..\..\common\src\txe_thread_time_slice_change.c +..\..\..\..\common\src\txe_thread_wait_abort.c +..\..\..\..\common\src\txe_timer_activate.c +..\..\..\..\common\src\txe_timer_change.c +..\..\..\..\common\src\txe_timer_create.c +..\..\..\..\common\src\txe_timer_deactivate.c +..\..\..\..\common\src\txe_timer_delete.c +..\..\..\..\common\src\txe_timer_info_get.c +..\..\..\..\ports_common_green\src\tx_el.c +..\..\..\..\ports_common_green\src\tx_ghs.c +..\..\..\..\ports_common_green\src\tx_ghse.c +..\..\..\..\ports_common_green\src\txr_block_allocate.c +..\..\..\..\ports_common_green\src\txr_block_pool_create.c +..\..\..\..\ports_common_green\src\txr_block_pool_delete.c +..\..\..\..\ports_common_green\src\txr_block_pool_info_get.c +..\..\..\..\ports_common_green\src\txr_block_pool_prioritize.c +..\..\..\..\ports_common_green\src\txr_block_release.c +..\..\..\..\ports_common_green\src\txr_byte_allocate.c +..\..\..\..\ports_common_green\src\txr_byte_pool_create.c +..\..\..\..\ports_common_green\src\txr_byte_pool_delete.c +..\..\..\..\ports_common_green\src\txr_byte_pool_info_get.c +..\..\..\..\ports_common_green\src\txr_byte_pool_prioritize.c +..\..\..\..\ports_common_green\src\txr_byte_release.c +..\..\..\..\ports_common_green\src\txr_event_flags_create.c +..\..\..\..\ports_common_green\src\txr_event_flags_delete.c +..\..\..\..\ports_common_green\src\txr_event_flags_get.c +..\..\..\..\ports_common_green\src\txr_event_flags_info_get.c +..\..\..\..\ports_common_green\src\txr_event_flags_set.c +..\..\..\..\ports_common_green\src\txr_event_flags_set_notify.c +..\..\..\..\ports_common_green\src\txr_ghs.c +..\..\..\..\ports_common_green\src\txr_mutex_create.c +..\..\..\..\ports_common_green\src\txr_mutex_delete.c +..\..\..\..\ports_common_green\src\txr_mutex_get.c +..\..\..\..\ports_common_green\src\txr_mutex_info_get.c +..\..\..\..\ports_common_green\src\txr_mutex_prioritize.c +..\..\..\..\ports_common_green\src\txr_mutex_put.c +..\..\..\..\ports_common_green\src\txr_queue_create.c +..\..\..\..\ports_common_green\src\txr_queue_delete.c +..\..\..\..\ports_common_green\src\txr_queue_flush.c +..\..\..\..\ports_common_green\src\txr_queue_front_send.c +..\..\..\..\ports_common_green\src\txr_queue_info_get.c +..\..\..\..\ports_common_green\src\txr_queue_prioritize.c +..\..\..\..\ports_common_green\src\txr_queue_receive.c +..\..\..\..\ports_common_green\src\txr_queue_send.c +..\..\..\..\ports_common_green\src\txr_queue_send_notify.c +..\..\..\..\ports_common_green\src\txr_semaphore_ceiling_put.c +..\..\..\..\ports_common_green\src\txr_semaphore_create.c +..\..\..\..\ports_common_green\src\txr_semaphore_delete.c +..\..\..\..\ports_common_green\src\txr_semaphore_get.c +..\..\..\..\ports_common_green\src\txr_semaphore_info_get.c +..\..\..\..\ports_common_green\src\txr_semaphore_prioritize.c +..\..\..\..\ports_common_green\src\txr_semaphore_put.c +..\..\..\..\ports_common_green\src\txr_semaphore_put_notify.c +..\..\..\..\ports_common_green\src\txr_thread_create.c +..\..\..\..\ports_common_green\src\txr_thread_delete.c +..\..\..\..\ports_common_green\src\txr_thread_entry_exit_notify.c +..\..\..\..\ports_common_green\src\txr_thread_info_get.c +..\..\..\..\ports_common_green\src\txr_thread_preemption_change.c +..\..\..\..\ports_common_green\src\txr_thread_priority_change.c +..\..\..\..\ports_common_green\src\txr_thread_reset.c +..\..\..\..\ports_common_green\src\txr_thread_resume.c +..\..\..\..\ports_common_green\src\txr_thread_suspend.c +..\..\..\..\ports_common_green\src\txr_thread_terminate.c +..\..\..\..\ports_common_green\src\txr_thread_time_slice_change.c +..\..\..\..\ports_common_green\src\txr_thread_wait_abort.c +..\..\..\..\ports_common_green\src\txr_timer_activate.c +..\..\..\..\ports_common_green\src\txr_timer_change.c +..\..\..\..\ports_common_green\src\txr_timer_create.c +..\..\..\..\ports_common_green\src\txr_timer_deactivate.c +..\..\..\..\ports_common_green\src\txr_timer_delete.c +..\..\..\..\ports_common_green\src\txr_timer_info_get.c diff --git a/ports/cortex_a7/green/example_build/tx_initialize_low_level.arm b/ports/cortex_a7/green/example_build/tx_initialize_low_level.arm new file mode 100644 index 00000000..e01e1206 --- /dev/null +++ b/ports/cortex_a7/green/example_build/tx_initialize_low_level.arm @@ -0,0 +1,319 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_initialize.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + SVC_MODE = 0xD3 # Disable IRQ/FIQ SVC mode + IRQ_MODE = 0xD2 # Disable IRQ/FIQ IRQ mode + FIQ_MODE = 0xD1 # Disable IRQ/FIQ FIQ mode + SYS_MODE = 0xDF # Disable IRQ/FIQ SYS mode + MODE_MASK = 0x1F # Mode mask + FIQ_STACK_SIZE = 512 # FIQ stack size + IRQ_STACK_SIZE = 1024 # IRQ stack size + SYS_STACK_SIZE = 1024 # SYS stack size + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-A7/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_initialize_low_level(VOID) +{ */ + .globl _tx_initialize_low_level +_tx_initialize_low_level: + + /****** NOTE ****** We must be in SVC MODE at this point. Some monitors + enter this routine in USER mode and require a software interrupt to + change into SVC mode. */ + + /* Save the system stack pointer. */ + /* _tx_thread_system_stack_ptr = (VOID_PTR) (sp); */ + + LDR r1,=_tx_thread_system_stack_ptr # Pickup address of system stack ptr + STR sp, [r1] # Save system stack + + /* Pickup the first available memory address. */ + + LDR r0,=__ghsbegin_free_mem # Pickup free memory address + + /* Setup initial stack pointers for IRQ and FIQ modes. */ + + MRS r12, CPSR # Pickup current CPSR + MOV r1, r0 # Get first available memory +#ifdef TX_ENABLE_IRQ_NESTING + /* Setup the system mode stack for nested interrupt support */ + LDR r2, =SYS_STACK_SIZE # Pickup stack size + BIC r3, r12, MODE_MASK # Clear mode bits + ORR r3, r3, SYS_MODE # Build SYS mode CPSR + MSR CPSR_c, r3 # Enter SYS mode + ADD r1, r1, r2 # Calculate start of SYS stack + SUB r1, r1, 1 # Backup one byte + BIC r1, r1, 7 # Insure 8-byte alignment + MOV sp, r1 # Setup SYS stack pointer +#endif + LDR r2, =FIQ_STACK_SIZE # Pickup stack size + BIC r3, r12, MODE_MASK # Clear mode bits + ORR r3, r3, FIQ_MODE # Build FIQ mode CPSR + MSR CPSR_c, r3 # Enter FIQ mode + ADD r1, r1, r2 # Calculate start of FIQ stack + SUB r1, r1, 1 # Backup one byte + BIC r1, r1, 7 # Insure 8-byte alignment + MOV sp, r1 # Setup FIQ stack pointer + MOV r10, 0 # Clear sl + MOV r11, 0 # Clear fp + LDR r2, =IRQ_STACK_SIZE # Pickup IRQ (system stack size) + BIC r3, r12, MODE_MASK # Clear mode bits + ORR r3, r3, IRQ_MODE # Build IRQ mode CPSR + MSR CPSR_c, r3 # Enter IRQ mode + ADD r1, r1, r2 # Calculate start of IRQ stack + SUB r1, r1, 1 # Backup one byte + BIC r1, r1, 7 # Insure 8-byte alignment + MOV sp, r1 # Setup IRQ stack pointer + MSR CPSR_c, r12 # Restore previous mode + ADD r0, r1, 4 # Adjust the new free memory + + + /* Save the first available memory address. */ + /* _tx_initialize_unused_memory = (VOID_PTR) __ghsbegin_free_mem + [SYS_STACK] + FIQ_STACK + IRQ_STACK; */ + + LDR r2,=_tx_initialize_unused_memory # Pickup unused memory ptr address + STR r0, [r2] # Save first free memory address + + + /* Setup Timer for periodic interrupts. To generate timer interrupts with + the Green Hills simulator, enter the following command in the target + window: timer 9999 irq */ + + /* Done, return to caller. */ + + RET # Return to caller + + .type _tx_initialize_low_level,$function + .size _tx_initialize_low_level,.-_tx_initialize_low_level +/* } */ + + +/* Define shells for each of the interrupt vectors. */ + + .globl __tx_undefined +__tx_undefined: + B __tx_undefined # Undefined handler + + .type __tx_undefined,$function + .size __tx_undefined,.-__tx_undefined + + .globl __tx_swi_interrupt +__tx_swi_interrupt: + B __tx_swi_interrupt # Software interrupt handler + + .type __tx_swi_interrupt,$function + .size __tx_swi_interrupt,.-__tx_swi_interrupt + + .globl __tx_prefetch_handler +__tx_prefetch_handler: + B __tx_prefetch_handler # Prefetch exception handler + + .type __tx_prefetch_handler,$function + .size __tx_prefetch_handler,.-__tx_prefetch_handler + + .globl __tx_abort_handler +__tx_abort_handler: + B __tx_abort_handler # Abort exception handler + + .type __tx_abort_handler,$function + .size __tx_abort_handler,.-__tx_abort_handler + + .globl __tx_reserved_handler +__tx_reserved_handler: + B __tx_reserved_handler # Reserved exception handler + + .type __tx_reserved_handler,$function + .size __tx_reserved_handler,.-__tx_reserved_handler + + .globl __tx_irq_handler + .globl __tx_irq_processing_return +__tx_irq_handler: + + /* Jump to context save to save system context. */ + B _tx_thread_context_save + + .type __tx_irq_handler,$function + .size __tx_irq_handler,.-__tx_irq_handler + +__tx_irq_processing_return: + + /* At this point execution is still in the IRQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. */ + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 0 # Build interrupt code + BL _tx_el_interrupt # Call interrupt event logging +#endif + + /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start + from IRQ mode with interrupts disabled. This routine switches to the + system mode and returns with IRQ interrupts enabled. + + NOTE: It is very important to ensure all IRQ interrupts are cleared + prior to enabling nested IRQ interrupts. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_start +#endif + + + /* For debug purpose, execute the timer interrupt processing here. In + a real system, some kind of status indication would have to be checked + before the timer interrupt handler could be called. */ + BL _tx_timer_interrupt # Timer interrupt handler + + /* Application IRQ handlers can be called here! */ + + /* If interrupt nesting was started earlier, the end of interrupt nesting + service must be called before returning to _tx_thread_context_restore. + This routine returns in processing in IRQ mode with interrupts disabled. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_end +#endif + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 0 # Build interrupt code + BL _tx_el_interrupt_end # Call interrupt event logging +#endif + + /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + .type __tx_irq_processing_return,$function + .size __tx_irq_processing_return,.-__tx_irq_processing_return + +#ifdef TX_ENABLE_FIQ_SUPPORT + + .globl __tx_fiq_handler + .globl __tx_fiq_processing_return +__tx_fiq_handler: + /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save + + .type __tx_fiq_handler,$function + .size __tx_fiq_handler,.-__tx_fiq_handler + +__tx_fiq_processing_return: + + /* At this point execution is still in the FIQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. */ + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 1 # Build interrupt code + BL _tx_el_interrupt # Call interrupt event logging +#endif + + /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start + from FIQ mode with interrupts disabled. This routine switches to the + system mode and returns with FIQ interrupts enabled. + + NOTE: It is very important to ensure all FIQ interrupts are cleared + prior to enabling nested FIQ interrupts. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_start +#endif + + /* Application FIQ handlers can be called here! */ + + /* If interrupt nesting was started earlier, the end of interrupt nesting + service must be called before returning to _tx_thread_fiq_context_restore. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_end +#endif + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 1 # Build interrupt code + BL _tx_el_interrupt_end # Call interrupt event logging +#endif + + /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + .type __tx_fiq_processing_return,$function + .size __tx_fiq_processing_return,.-__tx_fiq_processing_return + +#else + .globl __tx_fiq_handler +__tx_fiq_handler: + B __tx_fiq_handler # FIQ interrupt handler + + .type __tx_fiq_handler,$function + .size __tx_fiq_handler,.-__tx_fiq_handler +#endif + + /* Reference build options and version ID to ensure they come in. */ + +BUILD_OPTIONS: + .data.w _tx_build_options +VERSION_ID: + .data.w _tx_version_id diff --git a/ports/cortex_a7/green/example_build/txe.gpj b/ports/cortex_a7/green/example_build/txe.gpj new file mode 100644 index 00000000..662bcd16 --- /dev/null +++ b/ports/cortex_a7/green/example_build/txe.gpj @@ -0,0 +1,284 @@ +#!gbuild +[Library] + -DTX_ENABLE_EVENT_LOGGING + -I../../../../common/inc + -I../../../../ports_common_green/inc + -I../inc +..\..\..\..\common\inc\tx_api.h +..\..\..\..\common\inc\tx_block_pool.h +..\..\..\..\common\inc\tx_byte_pool.h +..\..\..\..\common\inc\tx_event_flags.h +..\..\..\..\common\inc\tx_initialize.h +..\..\..\..\common\inc\tx_mutex.h +..\..\..\..\common\inc\tx_queue.h +..\..\..\..\common\inc\tx_semaphore.h +..\..\..\..\common\inc\tx_thread.h +..\..\..\..\common\inc\tx_timer.h +..\..\..\..\common\inc\tx_trace.h +..\..\..\..\common\inc\tx_user_sample.h +..\inc\tx_port.h +..\..\..\..\ports_common_green\inc\tx_el.h +..\..\..\..\ports_common_green\inc\tx_ghs.h +..\src\tx_thread_context_restore.arm +..\src\tx_thread_context_save.arm +..\src\tx_thread_fiq_context_restore.arm +..\src\tx_thread_fiq_context_save.arm +..\src\tx_thread_fiq_nesting_end.arm +..\src\tx_thread_fiq_nesting_start.arm +..\src\tx_thread_interrupt_control.arm +..\src\tx_thread_interrupt_disable.arm +..\src\tx_thread_interrupt_restore.arm +..\src\tx_thread_irq_nesting_end.arm +..\src\tx_thread_irq_nesting_start.arm +..\src\tx_thread_schedule.arm +..\src\tx_thread_stack_build.arm +..\src\tx_thread_system_return.arm +..\src\tx_thread_vectored_context_save.arm +..\src\tx_timer_interrupt.arm +..\..\..\..\common\src\tx_block_allocate.c +..\..\..\..\common\src\tx_block_pool_cleanup.c +..\..\..\..\common\src\tx_block_pool_create.c +..\..\..\..\common\src\tx_block_pool_delete.c +..\..\..\..\common\src\tx_block_pool_info_get.c +..\..\..\..\common\src\tx_block_pool_initialize.c +..\..\..\..\common\src\tx_block_pool_performance_info_get.c +..\..\..\..\common\src\tx_block_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_block_pool_prioritize.c +..\..\..\..\common\src\tx_block_release.c +..\..\..\..\common\src\tx_byte_allocate.c +..\..\..\..\common\src\tx_byte_pool_cleanup.c +..\..\..\..\common\src\tx_byte_pool_create.c +..\..\..\..\common\src\tx_byte_pool_delete.c +..\..\..\..\common\src\tx_byte_pool_info_get.c +..\..\..\..\common\src\tx_byte_pool_initialize.c +..\..\..\..\common\src\tx_byte_pool_performance_info_get.c +..\..\..\..\common\src\tx_byte_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_byte_pool_prioritize.c +..\..\..\..\common\src\tx_byte_pool_search.c +..\..\..\..\common\src\tx_byte_release.c +..\..\..\..\common\src\tx_event_flags_cleanup.c +..\..\..\..\common\src\tx_event_flags_create.c +..\..\..\..\common\src\tx_event_flags_delete.c +..\..\..\..\common\src\tx_event_flags_get.c +..\..\..\..\common\src\tx_event_flags_info_get.c +..\..\..\..\common\src\tx_event_flags_initialize.c +..\..\..\..\common\src\tx_event_flags_performance_info_get.c +..\..\..\..\common\src\tx_event_flags_performance_system_info_get.c +..\..\..\..\common\src\tx_event_flags_set.c +..\..\..\..\common\src\tx_event_flags_set_notify.c +..\..\..\..\common\src\tx_initialize_high_level.c +..\..\..\..\common\src\tx_initialize_kernel_enter.c +..\..\..\..\common\src\tx_initialize_kernel_setup.c +..\..\..\..\common\src\tx_mutex_cleanup.c +..\..\..\..\common\src\tx_mutex_create.c +..\..\..\..\common\src\tx_mutex_delete.c +..\..\..\..\common\src\tx_mutex_get.c +..\..\..\..\common\src\tx_mutex_info_get.c +..\..\..\..\common\src\tx_mutex_initialize.c +..\..\..\..\common\src\tx_mutex_performance_info_get.c +..\..\..\..\common\src\tx_mutex_performance_system_info_get.c +..\..\..\..\common\src\tx_mutex_prioritize.c +..\..\..\..\common\src\tx_mutex_priority_change.c +..\..\..\..\common\src\tx_mutex_put.c +..\..\..\..\common\src\tx_queue_cleanup.c +..\..\..\..\common\src\tx_queue_create.c +..\..\..\..\common\src\tx_queue_delete.c +..\..\..\..\common\src\tx_queue_flush.c +..\..\..\..\common\src\tx_queue_front_send.c +..\..\..\..\common\src\tx_queue_info_get.c +..\..\..\..\common\src\tx_queue_initialize.c +..\..\..\..\common\src\tx_queue_performance_info_get.c +..\..\..\..\common\src\tx_queue_performance_system_info_get.c +..\..\..\..\common\src\tx_queue_prioritize.c +..\..\..\..\common\src\tx_queue_receive.c +..\..\..\..\common\src\tx_queue_send.c +..\..\..\..\common\src\tx_queue_send_notify.c +..\..\..\..\common\src\tx_semaphore_ceiling_put.c +..\..\..\..\common\src\tx_semaphore_cleanup.c +..\..\..\..\common\src\tx_semaphore_create.c +..\..\..\..\common\src\tx_semaphore_delete.c +..\..\..\..\common\src\tx_semaphore_get.c +..\..\..\..\common\src\tx_semaphore_info_get.c +..\..\..\..\common\src\tx_semaphore_initialize.c +..\..\..\..\common\src\tx_semaphore_performance_info_get.c +..\..\..\..\common\src\tx_semaphore_performance_system_info_get.c +..\..\..\..\common\src\tx_semaphore_prioritize.c +..\..\..\..\common\src\tx_semaphore_put.c +..\..\..\..\common\src\tx_semaphore_put_notify.c +..\..\..\..\common\src\tx_thread_create.c +..\..\..\..\common\src\tx_thread_delete.c +..\..\..\..\common\src\tx_thread_entry_exit_notify.c +..\..\..\..\common\src\tx_thread_identify.c +..\..\..\..\common\src\tx_thread_info_get.c +..\..\..\..\common\src\tx_thread_initialize.c +..\..\..\..\common\src\tx_thread_performance_info_get.c +..\..\..\..\common\src\tx_thread_performance_system_info_get.c +..\..\..\..\common\src\tx_thread_preemption_change.c +..\..\..\..\common\src\tx_thread_priority_change.c +..\..\..\..\common\src\tx_thread_relinquish.c +..\..\..\..\common\src\tx_thread_reset.c +..\..\..\..\common\src\tx_thread_resume.c +..\..\..\..\common\src\tx_thread_shell_entry.c +..\..\..\..\common\src\tx_thread_sleep.c +..\..\..\..\common\src\tx_thread_stack_analyze.c +..\..\..\..\common\src\tx_thread_stack_error_handler.c +..\..\..\..\common\src\tx_thread_stack_error_notify.c +..\..\..\..\common\src\tx_thread_suspend.c +..\..\..\..\common\src\tx_thread_system_preempt_check.c +..\..\..\..\common\src\tx_thread_system_resume.c +..\..\..\..\common\src\tx_thread_system_suspend.c +..\..\..\..\common\src\tx_thread_terminate.c +..\..\..\..\common\src\tx_thread_time_slice.c +..\..\..\..\common\src\tx_thread_time_slice_change.c +..\..\..\..\common\src\tx_thread_timeout.c +..\..\..\..\common\src\tx_thread_wait_abort.c +..\..\..\..\common\src\tx_time_get.c +..\..\..\..\common\src\tx_time_set.c +..\..\..\..\common\src\tx_timer_activate.c +..\..\..\..\common\src\tx_timer_change.c +..\..\..\..\common\src\tx_timer_create.c +..\..\..\..\common\src\tx_timer_deactivate.c +..\..\..\..\common\src\tx_timer_delete.c +..\..\..\..\common\src\tx_timer_expiration_process.c +..\..\..\..\common\src\tx_timer_info_get.c +..\..\..\..\common\src\tx_timer_initialize.c +..\..\..\..\common\src\tx_timer_performance_info_get.c +..\..\..\..\common\src\tx_timer_performance_system_info_get.c +..\..\..\..\common\src\tx_timer_system_activate.c +..\..\..\..\common\src\tx_timer_system_deactivate.c +..\..\..\..\common\src\tx_timer_thread_entry.c +..\..\..\..\common\src\tx_trace_buffer_full_notify.c +..\..\..\..\common\src\tx_trace_disable.c +..\..\..\..\common\src\tx_trace_enable.c +..\..\..\..\common\src\tx_trace_event_filter.c +..\..\..\..\common\src\tx_trace_event_unfilter.c +..\..\..\..\common\src\tx_trace_initialize.c +..\..\..\..\common\src\tx_trace_interrupt_control.c +..\..\..\..\common\src\tx_trace_isr_enter_insert.c +..\..\..\..\common\src\tx_trace_isr_exit_insert.c +..\..\..\..\common\src\tx_trace_object_register.c +..\..\..\..\common\src\tx_trace_object_unregister.c +..\..\..\..\common\src\tx_trace_user_event_insert.c +..\..\..\..\common\src\txe_block_allocate.c +..\..\..\..\common\src\txe_block_pool_create.c +..\..\..\..\common\src\txe_block_pool_delete.c +..\..\..\..\common\src\txe_block_pool_info_get.c +..\..\..\..\common\src\txe_block_pool_prioritize.c +..\..\..\..\common\src\txe_block_release.c +..\..\..\..\common\src\txe_byte_allocate.c +..\..\..\..\common\src\txe_byte_pool_create.c +..\..\..\..\common\src\txe_byte_pool_delete.c +..\..\..\..\common\src\txe_byte_pool_info_get.c +..\..\..\..\common\src\txe_byte_pool_prioritize.c +..\..\..\..\common\src\txe_byte_release.c +..\..\..\..\common\src\txe_event_flags_create.c +..\..\..\..\common\src\txe_event_flags_delete.c +..\..\..\..\common\src\txe_event_flags_get.c +..\..\..\..\common\src\txe_event_flags_info_get.c +..\..\..\..\common\src\txe_event_flags_set.c +..\..\..\..\common\src\txe_event_flags_set_notify.c +..\..\..\..\common\src\txe_mutex_create.c +..\..\..\..\common\src\txe_mutex_delete.c +..\..\..\..\common\src\txe_mutex_get.c +..\..\..\..\common\src\txe_mutex_info_get.c +..\..\..\..\common\src\txe_mutex_prioritize.c +..\..\..\..\common\src\txe_mutex_put.c +..\..\..\..\common\src\txe_queue_create.c +..\..\..\..\common\src\txe_queue_delete.c +..\..\..\..\common\src\txe_queue_flush.c +..\..\..\..\common\src\txe_queue_front_send.c +..\..\..\..\common\src\txe_queue_info_get.c +..\..\..\..\common\src\txe_queue_prioritize.c +..\..\..\..\common\src\txe_queue_receive.c +..\..\..\..\common\src\txe_queue_send.c +..\..\..\..\common\src\txe_queue_send_notify.c +..\..\..\..\common\src\txe_semaphore_ceiling_put.c +..\..\..\..\common\src\txe_semaphore_create.c +..\..\..\..\common\src\txe_semaphore_delete.c +..\..\..\..\common\src\txe_semaphore_get.c +..\..\..\..\common\src\txe_semaphore_info_get.c +..\..\..\..\common\src\txe_semaphore_prioritize.c +..\..\..\..\common\src\txe_semaphore_put.c +..\..\..\..\common\src\txe_semaphore_put_notify.c +..\..\..\..\common\src\txe_thread_create.c +..\..\..\..\common\src\txe_thread_delete.c +..\..\..\..\common\src\txe_thread_entry_exit_notify.c +..\..\..\..\common\src\txe_thread_info_get.c +..\..\..\..\common\src\txe_thread_preemption_change.c +..\..\..\..\common\src\txe_thread_priority_change.c +..\..\..\..\common\src\txe_thread_relinquish.c +..\..\..\..\common\src\txe_thread_reset.c +..\..\..\..\common\src\txe_thread_resume.c +..\..\..\..\common\src\txe_thread_suspend.c +..\..\..\..\common\src\txe_thread_terminate.c +..\..\..\..\common\src\txe_thread_time_slice_change.c +..\..\..\..\common\src\txe_thread_wait_abort.c +..\..\..\..\common\src\txe_timer_activate.c +..\..\..\..\common\src\txe_timer_change.c +..\..\..\..\common\src\txe_timer_create.c +..\..\..\..\common\src\txe_timer_deactivate.c +..\..\..\..\common\src\txe_timer_delete.c +..\..\..\..\common\src\txe_timer_info_get.c +..\..\..\..\ports_common_green\src\tx_el.c +..\..\..\..\ports_common_green\src\tx_ghs.c +..\..\..\..\ports_common_green\src\tx_ghse.c +..\..\..\..\ports_common_green\src\txr_block_allocate.c +..\..\..\..\ports_common_green\src\txr_block_pool_create.c +..\..\..\..\ports_common_green\src\txr_block_pool_delete.c +..\..\..\..\ports_common_green\src\txr_block_pool_info_get.c +..\..\..\..\ports_common_green\src\txr_block_pool_prioritize.c +..\..\..\..\ports_common_green\src\txr_block_release.c +..\..\..\..\ports_common_green\src\txr_byte_allocate.c +..\..\..\..\ports_common_green\src\txr_byte_pool_create.c +..\..\..\..\ports_common_green\src\txr_byte_pool_delete.c +..\..\..\..\ports_common_green\src\txr_byte_pool_info_get.c +..\..\..\..\ports_common_green\src\txr_byte_pool_prioritize.c +..\..\..\..\ports_common_green\src\txr_byte_release.c +..\..\..\..\ports_common_green\src\txr_event_flags_create.c +..\..\..\..\ports_common_green\src\txr_event_flags_delete.c +..\..\..\..\ports_common_green\src\txr_event_flags_get.c +..\..\..\..\ports_common_green\src\txr_event_flags_info_get.c +..\..\..\..\ports_common_green\src\txr_event_flags_set.c +..\..\..\..\ports_common_green\src\txr_event_flags_set_notify.c +..\..\..\..\ports_common_green\src\txr_ghs.c +..\..\..\..\ports_common_green\src\txr_mutex_create.c +..\..\..\..\ports_common_green\src\txr_mutex_delete.c +..\..\..\..\ports_common_green\src\txr_mutex_get.c +..\..\..\..\ports_common_green\src\txr_mutex_info_get.c +..\..\..\..\ports_common_green\src\txr_mutex_prioritize.c +..\..\..\..\ports_common_green\src\txr_mutex_put.c +..\..\..\..\ports_common_green\src\txr_queue_create.c +..\..\..\..\ports_common_green\src\txr_queue_delete.c +..\..\..\..\ports_common_green\src\txr_queue_flush.c +..\..\..\..\ports_common_green\src\txr_queue_front_send.c +..\..\..\..\ports_common_green\src\txr_queue_info_get.c +..\..\..\..\ports_common_green\src\txr_queue_prioritize.c +..\..\..\..\ports_common_green\src\txr_queue_receive.c +..\..\..\..\ports_common_green\src\txr_queue_send.c +..\..\..\..\ports_common_green\src\txr_queue_send_notify.c +..\..\..\..\ports_common_green\src\txr_semaphore_ceiling_put.c +..\..\..\..\ports_common_green\src\txr_semaphore_create.c +..\..\..\..\ports_common_green\src\txr_semaphore_delete.c +..\..\..\..\ports_common_green\src\txr_semaphore_get.c +..\..\..\..\ports_common_green\src\txr_semaphore_info_get.c +..\..\..\..\ports_common_green\src\txr_semaphore_prioritize.c +..\..\..\..\ports_common_green\src\txr_semaphore_put.c +..\..\..\..\ports_common_green\src\txr_semaphore_put_notify.c +..\..\..\..\ports_common_green\src\txr_thread_create.c +..\..\..\..\ports_common_green\src\txr_thread_delete.c +..\..\..\..\ports_common_green\src\txr_thread_entry_exit_notify.c +..\..\..\..\ports_common_green\src\txr_thread_info_get.c +..\..\..\..\ports_common_green\src\txr_thread_preemption_change.c +..\..\..\..\ports_common_green\src\txr_thread_priority_change.c +..\..\..\..\ports_common_green\src\txr_thread_reset.c +..\..\..\..\ports_common_green\src\txr_thread_resume.c +..\..\..\..\ports_common_green\src\txr_thread_suspend.c +..\..\..\..\ports_common_green\src\txr_thread_terminate.c +..\..\..\..\ports_common_green\src\txr_thread_time_slice_change.c +..\..\..\..\ports_common_green\src\txr_thread_wait_abort.c +..\..\..\..\ports_common_green\src\txr_timer_activate.c +..\..\..\..\ports_common_green\src\txr_timer_change.c +..\..\..\..\ports_common_green\src\txr_timer_create.c +..\..\..\..\ports_common_green\src\txr_timer_deactivate.c +..\..\..\..\ports_common_green\src\txr_timer_delete.c +..\..\..\..\ports_common_green\src\txr_timer_info_get.c diff --git a/ports/cortex_a7/green/inc/tx_port.h b/ports/cortex_a7/green/inc/tx_port.h new file mode 100644 index 00000000..76e55d62 --- /dev/null +++ b/ports/cortex_a7/green/inc/tx_port.h @@ -0,0 +1,402 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A7/Green Hills */ +/* 6.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include +#include +#include "tx_ghs.h" + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define constants for Green Hills EventAnalyzer. */ + +/* Define the number of ticks per second. This informs the EventAnalyzer what the timestamps + represent. By default, this is set to 1,000,000 i.e., one tick every microsecond. */ + +#define TX_EL_TICKS_PER_SECOND 1000000 + +/* Define the method of how to get the upper and lower 32-bits of the time stamp. By default, simply + simulate the time-stamp source with a counter. */ + +#define read_tbu() _tx_el_time_base_upper +#define read_tbl() ++_tx_el_time_base_lower + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ + VOID * tx_thread_eh_globals; \ + int Errno; /* errno. */ \ + char * strtok_saved_pos; /* strtok() position. */ +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + +#if (__GHS_VERSION_NUMBER >= 500) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) \ + { \ + extern void __tx_cpp_exception_init(TX_THREAD *thread_ptr); \ + __tx_cpp_exception_init(thread_ptr); \ + } +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) \ + { \ + #pragma weak __cpp_exception_init \ + extern void __cpp_exception_init(void **); \ + static void (*const cpp_init_funcp)(void **) = __cpp_exception_init; \ + if (cpp_init_funcp) \ + __cpp_exception_init(&(thread_ptr -> tx_thread_eh_globals)); \ + } +#endif + +#if (__GHS_VERSION_NUMBER >= 500) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) \ + { \ + extern void __tx_cpp_exception_cleanup(TX_THREAD *thread_ptr); \ + __tx_cpp_exception_cleanup(thread_ptr); \ + } +#else +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) \ + { \ + #pragma weak __cpp_exception_cleanup \ + extern void __cpp_exception_cleanup(void **); \ + static void (*const cpp_cleanup_funcp)(void **) = \ + __cpp_exception_cleanup; \ + if (cpp_cleanup_funcp) \ + __cpp_exception_cleanup(&(thread_ptr -> tx_thread_eh_globals)); \ + } +#endif + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + b = __CLZ32(m); \ + b = 31 - b; + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#if defined(__THUMB) + +unsigned int _tx_thread_interrupt_disable(void); +void _tx_thread_interrupt_restore(unsigned int new_posture); + +#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); + +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; + +#if defined(__GHS_VERSION_NUMBER) && (__GHS_VERSION_NUMBER >= 350) + +/* Define ThreadX interrupt lockout and restore macros using + compiler built-in functions if using Green Hills ARM compiler + version 3.5 or later. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_DISABLE interrupt_save = __GETSR(); \ + __SETSR(interrupt_save | 0xC0); + +#define TX_RESTORE __SETSR(interrupt_save); +#else +#define TX_DISABLE interrupt_save = __GETSR(); \ + __SETSR(interrupt_save | 0x80); + +#define TX_RESTORE __SETSR(interrupt_save); +#endif + +#else + +/* Define ThreadX interrupt lockout and restore macros using + asm macros if using Green Hills ARM compiler earlier than + version 3.5. */ + +asm int disable_ints(void) +{ +% + MRS r0,CPSR +#ifdef TX_BEFORE_ARMV6 +#ifdef TX_ENABLE_FIQ_SUPPORT + ORR r1,r0,0xC0 +#else + ORR r1,r0,0x80 +#endif + MSR CPSR_c,r1 +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if +#else + CPSID i +#endif +#endif +%error +} + +asm void restore_ints(int a) +{ +%reg a + MSR CPSR_c,a +%mem a + LDR r0,a + MSR CPSR_c,r0 +%error +} + +#define TX_DISABLE interrupt_save = disable_ints(); + +#define TX_RESTORE restore_ints(interrupt_save); +#endif +#endif + + +/* Define VFP extension for the Cortex-A8. Each is assumed to be called in the context of the executing + thread. */ + +void tx_thread_vfp_enable(void); +void tx_thread_vfp_disable(void); + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/Green Hills Version 6.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + diff --git a/ports/cortex_a7/green/readme_threadx.txt b/ports/cortex_a7/green/readme_threadx.txt new file mode 100644 index 00000000..6ed148a0 --- /dev/null +++ b/ports/cortex_a7/green/readme_threadx.txt @@ -0,0 +1,527 @@ + Microsoft's Azure RTOS ThreadX for Cortex-A7 + + Using the Green Hills Software Tools + +1. Open the ThreadX Project Workspace + +In order to build the ThreadX library and the ThreadX demonstration first load +the Azure RTOS Workspace azure_rtos_workspace.gpj, which is located inside the +"example_build" directory. + + +2. Building the ThreadX run-time Library + +Building the ThreadX library is easy; simply select the MULTI project file +tx.gpj and then select the build button. You should now observe the +compilation and assembly of the ThreadX library. This project build produces +the ThreadX library file tx.a. + + +3. Demonstration System + +The ThreadX demonstration is designed to execute under the MULTI environment +on the Green Hills Cortex-A7 simulator. The instructions that follow describe +how to get the ThreadX evaluation running under the MULTI Cortex-A7 simulation +environment. + +Building the demonstration is easy; simply select the MULTI project file +sample_threadx.gpj. At this point, select the "Project Build" button and observe +the compilation, assembly, and linkage of the ThreadX demonstration application. + +After the demonstration is built, invoke the MULTI ARM simulator by selecting +the simulator connection from within the sample_threadx.con connection file. +Once connected to the simulator, select the "Debug" button. You should now +observe the main function of sample_threadx.c. + +At this point, you should setup a simulated timer interrupt for ThreadX +by entering "timer 9999 irq" in the "target" window of the debugger. + +You are now ready to execute the ThreadX demonstration system. Select +breakpoints and data watches to observe the execution of the sample_threadx.c +application. + + +4. EventAnalyzer Demonstration + +To build a demonstration system that also logs events for the MULTI EventAnalyzer, +perform the same steps as the regular demo, except build the ThreadX library with +txe.gpj file and use the sample_threadx_el.gpj build file to build the demonstration. +The resulting image will log all system events, which can then be displayed by the +MULTI EventAnalyzer. + + +5. System Initialization + +The system entry point using the Green Hills tools is at the label _start. +This is defined within the crt0.arm file supplied by Green Hills. In addition, +this is where all static and global preset C variable initialization +processing is called from. + +After the Green Hills startup function returns, ThreadX initialization is +called. The main initialization function is _tx_initialize_low_level and +is located in the file tx_initialize_low_level.arm. This function is responsible +for setting up various system data structures, interrupt vectors, and the +periodic timer interrupt source of ThreadX. + +In addition, _tx_initialize_low_level determines where the first available +RAM memory address is located. This address is supplied to tx_application_define. + +By default, the first available RAM memory address is assumed to start at the +beginning of the ThreadX section .free_mem. If changes are made to the +sample_threadx.ld file, the .free_mem section should remain the last allocated +section in the main RAM area. The starting address of this section is passed +to tx_application_define. + + +6. User defines + +The following defines and their associated action are as follows: + + Define Meaning + + TX_ENABLE_IRQ_NESTING If defined, this brings in special IRQ + interrupt nesting logic into the ThreadX + library. This define should be applied + to the entire ThreadX library. + + TX_ENABLE_FIQ_NESTING If defined, this brings in special FIQ + interrupt nesting logic into the ThreadX + library. This define should be applied + to the entire ThreadX library and the + define TX_ENABLE_FIQ_SUPPORT should also + be defined. + + TX_ENABLE_FIQ_SUPPORT If defined, this brings in FIQ context + save and restore logic necessary for + applications to call ThreadX services from + FIQ interrupt handlers. This define + should be applied to the entire ThreadX + library. + + + TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, + this define causes basic ThreadX error + checking to be disabled. Please see + Chapter 4 in the "ThreadX User Guide" + for more details. + + TX_ENABLE_EVENT_LOGGING This define enables event logging for any + or all of the ThreadX source code. If this + option is used anywhere, the tx_initialize_high_level.c + file must be compiled with it as well, since this + is where the event log is initialized. + + TX_NO_EVENT_INFO This is a sub-option for event logging. + If this is enabled, only basic information + is saved in the log. + + TX_ENABLE_EVENT_FILTERS This is also a sub-option for event-logging. + If this is enabled, run-time filtering logic + is added to the event logging code. + + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By + default, this value is set to 32 priority levels. + + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found + in tx_port.h. + + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default + value is port-specific and is found in tx_port.h. + + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined + in tx_port.h. + + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. + By default, this option is not defined. + + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. + By default, this option is not defined. + + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is + not defined. + + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. + By default, this option is not defined. + + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. + By default, this option is not defined. + + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. + By default, this option is not defined. + + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size + and improves performance. + + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is + not defined. + + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is + not defined. + + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option + is not defined. + + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is + not defined. + + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is + not defined. + + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is + not defined. + + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is + not defined. + + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is + not defined. + + + +7. Register Usage and Stack Frames + +The Green Hills compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) +are scratch registers for each function. All other registers used by a C +function must be preserved by the function. ThreadX takes advantage of this +in situations where a context switch happens as a result of making a ThreadX +service call (which is itself a C function). In such cases, the saved +context of a thread is only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 CPSR CPSR + 0x08 r0 (a1) r4 (v1) + 0x0C r1 (a2) r5 (v2) + 0x10 r2 (a3) r6 (v3) + 0x14 r3 (a4) r7 (v4) + 0x18 r4 (v1) r8 (v5) + 0x1C r5 (v2) r9 (v6) + 0x20 r6 (v3) r10 (v7) + 0x24 r7 (v4) r11 (fp) + 0x28 r8 (v5) r14 (lr) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) + 0x3C r14 (lr) + 0x40 PC + + +8. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make ThreadX run faster, you can change the tx.gpj project +to disable debug information and enable the desired optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined before tx_api.h is included. + + +9. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-A7 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +9.1 Vector Area + +The Cortex-A7 vectors start at address zero. The demonstration system reset.arm +file contains the reset section (which contains all the ARM vectors) and is +typically loaded at address zero. On actual hardware platforms, this section +might have to be copied to address 0. + +9.2 IRQ ISRs + +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested +IRQ interrupts. The following sub-sections define the IRQ capabilities. + + +9.2.1 Standard IRQ ISRs + +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +is the default IRQ handler defined in tx_initialize_low_level.arm: + + + .globl __tx_irq_handler + .globl __tx_irq_processing_return +__tx_irq_handler: + + /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return: + + /* At this point execution is still in the IRQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. Note + that IRQ interrupts are still disabled upon return from the context + save function. */ + + /* Application ISR call(s) go here! */ + + /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +9.2.2 Vectored IRQ ISRs + +The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified +by the particular implementation. The following is an example IRQ handler defined in +tx_initialize_low_level.arm: + + .globl __tx_irq_example_handler +__tx_irq_example_handler: + + /* Call context save to save system context. */ + + STMDB sp!, {r0-r3} # Save some scratch registers + MRS r0, SPSR # Pickup saved SPSR + SUB lr, lr, #4 # Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} # Store other scratch registers + BL _tx_thread_vectored_context_save # Call the vectored IRQ context save + + /* At this point execution is still in the IRQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. Note + that IRQ interrupts are still disabled upon return from the context + save function. */ + + /* Application ISR call goes here! */ + + /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +9.2.3 Nested IRQ Support + +By default, nested IRQ interrupt support is not enabled. To enable nested +IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING +defined. With this defined, two new IRQ interrupt management services are +available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. +These function should be called between the IRQ context save and restore +calls. + +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +by switching from IRQ mode to SYS mode and enabling IRQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.arm. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables nesting +by disabling IRQ interrupts and switching back to IRQ mode in preparation for +the IRQ context restore service. + +The following is an example of enabling IRQ nested interrupts in the +typical IRQ handler: + + .globl __tx_irq_handler + .globl __tx_irq_processing_return +__tx_irq_handler: + + /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return: + + /* Enable nested IRQ interrupts. NOTE: Since this service returns + with IRQ interrupts enabled, all IRQ interrupt sources must be + cleared prior to calling this service. */ + BL _tx_thread_irq_nesting_start + + /* Application ISR call(s) go here! */ + + /* Disable nested IRQ interrupts. The mode is switched back to + IRQ mode and IRQ interrupts are disable upon return. */ + BL _tx_thread_irq_nesting_end + + /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +9.3 FIQ Interrupts + +By default, Cortex-A7 FIQ interrupts are left completely enabled by ThreadX. +Of course, this means that the application is fully responsible for +saving/restoring any registers used in the FIQ ISR processing. In addition, +no ThreadX service calls are allowed from the default FIQ ISRs. The default +FIQ interrupt shell is located in tx_initialize_low_level.arm. + +9.3.1 Managed FIQ Interrupts + +Full ThreadX management of FIQ interrupts is provided if the ThreadX sources +are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built +this way, the FIQ interrupt handlers are very similar to the IRQ interrupt +handlers defined previously. The following is default FIQ handler +defined in tx_initialize_low_level.arm: + + + .globl __tx_fiq_handler + .globl __tx_fiq_processing_return +__tx_fiq_handler: + + /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: + + /* At this point execution is still in the FIQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. */ + + /* Application FIQ handlers can be called here! */ + + /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +9.3.1.1 Nested FIQ Support + +By default, nested FIQ interrupt support is not enabled. To enable nested +FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING +defined. With this defined, two new FIQ interrupt management services are +available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. +These function should be called between the FIQ context save and restore +calls. + +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +by switching from FIQ mode to SYS mode and enabling FIQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.arm. When nested FIQ interrupts are no longer +required, calling the _tx_thread_fiq_nesting_end service disables nesting by +disabling FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +context restore service. + +The following is an example of enabling FIQ nested interrupts in the +typical FIQ handler: + + + .globl __tx_fiq_handler + .globl __tx_fiq_processing_return +__tx_fiq_handler: + + /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: + + /* At this point execution is still in the FIQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. */ + + /* Enable nested FIQ interrupts. NOTE: Since this service returns + with FIQ interrupts enabled, all FIQ interrupt sources must be + cleared prior to calling this service. */ + BL _tx_thread_fiq_nesting_start + + /* Application FIQ handlers can be called here! */ + + /* Disable nested FIQ interrupts. The mode is switched back to + FIQ mode and FIQ interrupts are disable upon return. */ + BL _tx_thread_fiq_nesting_end + + /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + + +10. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional. However, all other +ThreadX services are operational without a periodic timer source. + +To add the timer interrupt processing, simply make a call to +_tx_timer_interrupt in the IRQ processing. An example of this can be +found in the file tx_initialize_low_level.arm. + + +11. Thumb/Cortex-A7 Mixed Mode + +By default, ThreadX is setup for running in Cortex-A7 32-bit mode. This is +also true for the demonstration system. It is possible to build any +ThreadX file and/or the application in Thumb mode. The only exception +to this is the file tx_thread_shell_entry.c. This file must always be +built in 32-bit mode. + + +12. VFP Support + +By default, VFP support is disabled for each thread. If saving the context of the VFP registers +is needed, the following API call must be made from the context of the application thread - before +the VFP usage: + +void tx_thread_vfp_enable(void); + +After this API is called in the application, VFP registers will be saved/restored for this thread if it +is preempted via an interrupt. All other suspension of the this thread will not require the VFP registers +to be saved/restored. + +To disable VFP register context saving, simply call the following API: + +void tx_thread_vfp_disable(void); + + +13. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +05/19/2020 Initial ThreadX version of Cortex-A7/Green Hills port. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_a7/green/src/tx_thread_context_restore.arm b/ports/cortex_a7/green/src/tx_thread_context_restore.arm new file mode 100644 index 00000000..664c560d --- /dev/null +++ b/ports/cortex_a7/green/src/tx_thread_context_restore.arm @@ -0,0 +1,259 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # Disable IRQ and FIQ interrupts +#else + DISABLE_INTS = 0x80 # Disable IRQ interrupts +#endif + SVC_MODE = (0x13 | DISABLE_INTS) # SVC mode + IRQ_MODE = (0x12 | DISABLE_INTS) # IRQ mode + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore Cortex-A7/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores the interrupt context if it is processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_restore(VOID) +{ */ + .globl _tx_thread_context_restore +_tx_thread_context_restore: + + /* Lockout interrupts. */ + +#ifdef TX_BEFORE_ARMV6 + MRS r3, CPSR # Pickup current CPSR + ORR r0, r3, DISABLE_INTS # Build interrupt disable value + MSR CPSR_c, r0 # Lockout interrupts +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if # Disable IRQ and FIQ interrupts +#else + CPSID i # Disable IRQ interrupts +#endif +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR exit function to indicate an ISR is complete. */ + + BL _tx_execution_isr_exit # Call the ISR exit function +#endif + + /* Determine if interrupts are nested. */ + /* if (--_tx_thread_system_state) + { */ + + LDR r3, =_tx_thread_system_state # Pickup address of system state var + LDR r2, [r3] # Pickup system state + SUB r2, r2, 1 # Decrement the counter + STR r2, [r3] # Store the counter + CMP r2, 0 # Was this the first interrupt? + BEQ __tx_thread_not_nested_restore # If so, not a nested restore + + /* Interrupts are nested. */ + + /* Just recover the saved registers and return to the point of + interrupt. */ + + LDMIA sp!, {r0, r10, r12, lr} # Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 # Put SPSR back + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOVS pc, lr # Return to point of interrupt + + /* } */ +__tx_thread_not_nested_restore: + + /* Determine if a thread was interrupted and no preemption is required. */ + /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) + || (_tx_thread_preempt_disable)) + { */ + + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup actual current thread pointer + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_idle_system_restore # Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable # Pickup preempt disable address + LDR r2, [r3] # Pickup actual preempt disable flag + CMP r2, 0 # Is it set? + BNE __tx_thread_no_preempt_restore # Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr # Pickup address of execute thread ptr + LDR r2, [r3] # Pickup actual execute thread pointer + CMP r0, r2 # Is the same thread highest priority? + BNE __tx_thread_preempt_restore # No, preemption needs to happen + + +__tx_thread_no_preempt_restore: + + /* Restore interrupted thread or ISR. */ + + /* Pickup the saved stack pointer. */ + /* tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; */ + + /* Recover the saved context and return to the point of interrupt. */ + + LDMIA sp!, {r0, r10, r12, lr} # Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 # Put SPSR back + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOVS pc, lr # Return to point of interrupt + + /* } + else + { */ +__tx_thread_preempt_restore: + + LDMIA sp!, {r3, r10, r12, lr} # Recover temporarily saved registers + MOV r1, lr # Save lr (point of interrupt) + MOV r2, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r2 # Enter SVC mode + STR r1, [sp, -4]! # Save point of interrupt + STMDB sp!, {r4-r12, lr} # Save upper half of registers + MOV r4, r3 # Save SPSR in r4 + MOV r2, IRQ_MODE # Build IRQ mode CPSR + MSR CPSR_c, r2 # Re-enter IRQ mode + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOV r5, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r5 # Enter SVC mode + STMDB sp!, {r0-r3} # Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup current thread pointer + +#ifdef __VFP__ + LDR r2, [r0, 144] # Pickup the VFP enabled flag + CMP r2, 0 # Is the VFP enabled? + BEQ _tx_skip_irq_vfp_save # No, skip VFP IRQ save + VMRS r2, FPSCR # Pickup the FPSCR + STR r2, [sp, -4]! # Save FPSCR + VSTMDB sp!, {D16-D31} # Save D16-D31 + VSTMDB sp!, {D0-D15} # Save D0-D15 +_tx_skip_irq_vfp_save: +#endif + + MOV r3, 1 # Build interrupt stack type + STMDB sp!, {r3, r4} # Save interrupt stack type and SPSR + STR sp, [r0, 8] # Save stack pointer in thread control + /* # block */ + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r4, r0 # Save r0 + MOV r5, r1 # Save r1 + BL _tx_el_thread_preempted # Call thread preempted routine + MOV r0, r4 # Restore r0 + MOV r1, r5 # Restore r1 +#endif + + /* Save the remaining time-slice and disable it. */ + /* if (_tx_timer_time_slice) + { */ + + LDR r3, =_tx_timer_time_slice # Pickup time-slice variable address + LDR r2, [r3] # Pickup time-slice + CMP r2, 0 # Is it active? + BEQ __tx_thread_dont_save_ts # No, don't save it + + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + STR r2, [r0, 24] # Save thread's time-slice + MOV r2, 0 # Clear value + STR r2, [r3] # Disable global time-slice flag + + /* } */ +__tx_thread_dont_save_ts: + + + /* Clear the current task pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + MOV r0, 0 # NULL value + STR r0, [r1] # Clear current thread pointer + + /* Return to the scheduler. */ + /* _tx_thread_schedule(); */ + + B _tx_thread_schedule # Return to scheduler + /* } */ + +__tx_thread_idle_system_restore: + + /* Just return back to the scheduler! */ + + + MOV r3, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r3 # Lockout interrupts + B _tx_thread_schedule # Return to scheduler + + .type _tx_thread_context_restore,$function + .size _tx_thread_context_restore,.-_tx_thread_context_restore + +/* } */ + diff --git a/ports/cortex_a7/green/src/tx_thread_context_save.arm b/ports/cortex_a7/green/src/tx_thread_context_save.arm new file mode 100644 index 00000000..d0f4be62 --- /dev/null +++ b/ports/cortex_a7/green/src/tx_thread_context_save.arm @@ -0,0 +1,207 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # IRQ & FIQ interrupts disabled +#else + DISABLE_INTS = 0x80 # IRQ interrupts disabled +#endif + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save Cortex-A7/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_save(VOID) +{ */ + .globl _tx_thread_context_save +_tx_thread_context_save: + + /* Upon entry to this routine, it is assumed that IRQ interrupts are locked + out, we are in IRQ mode, and all registers are intact. */ + + /* Check for a nested interrupt condition. */ + /* if (_tx_thread_system_state++) + { */ + + STMDB sp!, {r0-r3} # Save some working registers + +#ifdef TX_ENABLE_FIQ_SUPPORT +#ifdef TX_BEFORE_ARMV6 + MRS r0, CPSR # Pickup the CPSR + ORR r0, r0, DISABLE_INTS # Build disable interrupt CPSR + MSR CPSR_c, r0 # Disable interrupts +#else + CPSID if # Disable FIQ interrupts +#endif +#endif + + LDR r3, =_tx_thread_system_state # Pickup address of system state var + LDR r2, [r3] # Pickup system state + CMP r2, 0 # Is this the first interrupt? + BEQ __tx_thread_not_nested_save # Yes, not a nested context save + + /* Nested interrupt condition. */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + + /* Save the rest of the scratch registers on the stack and return to the + calling ISR. */ + + MRS r0, SPSR # Pickup saved SPSR + SUB lr, lr, 4 # Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} # Store other registers + + /* Return to the ISR. */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + B __tx_irq_processing_return # Continue IRQ processing + +__tx_thread_not_nested_save: + /* } */ + + /* Otherwise, not nested, check to see if a thread was running. */ + /* else if (_tx_thread_current_ptr) + { */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup current thread pointer + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_idle_system_save # If so, interrupt occurred in + /* # scheduling loop - nothing needs saving! */ + + /* Save minimal context of interrupted thread. */ + + MRS r2, SPSR # Pickup saved SPSR + SUB lr, lr, 4 # Adjust point of interrupt + STMDB sp!, {r2, r10, r12, lr} # Store other registers + + /* Save the current stack pointer in the thread's control block. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ + + /* Switch to the system stack. */ + /* sp = _tx_thread_system_stack_ptr; */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + B __tx_irq_processing_return # Continue IRQ processing + + /* } + else + { */ + +__tx_thread_idle_system_save: + + /* Interrupt occurred in the scheduling loop. */ + + /* Not much to do here, just adjust the stack pointer, and return to IRQ + processing. */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + ADD sp, sp, 16 # Recover saved registers + B __tx_irq_processing_return # Continue IRQ processing + + .type _tx_thread_context_save,$function + .size _tx_thread_context_save,.-_tx_thread_context_save + + /* } +} */ + diff --git a/ports/cortex_a7/green/src/tx_thread_fiq_context_restore.arm b/ports/cortex_a7/green/src/tx_thread_fiq_context_restore.arm new file mode 100644 index 00000000..8be49f3c --- /dev/null +++ b/ports/cortex_a7/green/src/tx_thread_fiq_context_restore.arm @@ -0,0 +1,264 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + SVC_MODE = 0xD3 # SVC mode + FIQ_MODE = 0xD1 # FIQ mode +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # Disable IRQ and FIQ interrupts +#else + DISABLE_INTS = 0x80 # Disable IRQ interrupts +#endif + MODE_MASK = 0x1F # Mode mask + IRQ_MODE_BITS = 0x12 # IRQ mode bits + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_context_restore Cortex-A7/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores the fiq interrupt context when processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* FIQ ISR Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_fiq_context_restore(VOID) +{ */ + .globl _tx_thread_fiq_context_restore +_tx_thread_fiq_context_restore: + + /* Lockout interrupts. */ + +#ifdef TX_BEFORE_ARMV6 + MRS r3, CPSR # Pickup current CPSR + ORR r0, r3, DISABLE_INTS # Build interrupt disable value + MSR CPSR_c, r0 # Lockout interrupts +#else + CPSID if # Disable IRQ and FIQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR exit function to indicate an ISR is complete. */ + + BL _tx_execution_isr_exit # Call the ISR exit function +#endif + + /* Determine if interrupts are nested. */ + /* if (--_tx_thread_system_state) + { */ + + LDR r3, =_tx_thread_system_state # Pickup address of system state var + LDR r2, [r3] # Pickup system state + SUB r2, r2, 1 # Decrement the counter + STR r2, [r3] # Store the counter + CMP r2, 0 # Was this the first interrupt? + BEQ __tx_thread_fiq_not_nested_restore # If so, not a nested restore + + /* Interrupts are nested. */ + + /* Just recover the saved registers and return to the point of + interrupt. */ + + LDMIA sp!, {r0, r10, r12, lr} # Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 # Put SPSR back + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOVS pc, lr # Return to point of interrupt + + /* } */ +__tx_thread_fiq_not_nested_restore: + + /* Determine if a thread was interrupted and no preemption is required. */ + /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) + || (_tx_thread_preempt_disable)) + { */ + + LDR r1, [sp] # Pickup the saved SPSR + MOV r2, MODE_MASK # Build mask to isolate the interrupted mode + AND r1, r1, r2 # Isolate mode bits + CMP r1, IRQ_MODE_BITS # Was an interrupt taken in IRQ mode before we + /* # got to context save? */ + BEQ __tx_thread_fiq_no_preempt_restore # Yes, just go back to point of interrupt + + + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup actual current thread pointer + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_fiq_idle_system_restore # Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable # Pickup preempt disable address + LDR r2, [r3] # Pickup actual preempt disable flag + CMP r2, 0 # Is it set? + BNE __tx_thread_fiq_no_preempt_restore # Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr # Pickup address of execute thread ptr + LDR r2, [r3] # Pickup actual execute thread pointer + CMP r0, r2 # Is the same thread highest priority? + BNE __tx_thread_fiq_preempt_restore # No, preemption needs to happen + + +__tx_thread_fiq_no_preempt_restore: + + /* Restore interrupted thread or ISR. */ + + /* Pickup the saved stack pointer. */ + /* tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; */ + + /* Recover the saved context and return to the point of interrupt. */ + + LDMIA sp!, {r0, lr} # Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 # Put SPSR back + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOVS pc, lr # Return to point of interrupt + + /* } + else + { */ +__tx_thread_fiq_preempt_restore: + + LDMIA sp!, {r3, lr} # Recover temporarily saved registers + MOV r1, lr # Save lr (point of interrupt) + MOV r2, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r2 # Enter SVC mode + STR r1, [sp, -4]! # Save point of interrupt + STMDB sp!, {r4-r12, lr} # Save upper half of registers + MOV r4, r3 # Save SPSR in r4 + MOV r2, FIQ_MODE # Build FIQ mode CPSR + MSR CPSR_c, r2 # Re-enter FIQ mode + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOV r5, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r5 # Enter SVC mode + STMDB sp!, {r0-r3} # Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup current thread pointer + +#ifdef __VFP__ + LDR r2, [r0, 144] # Pickup the VFP enabled flag + CMP r2, 0 # Is the VFP enabled? + BEQ _tx_skip_fiq_vfp_save # No, skip VFP IRQ save + VMRS r2, FPSCR # Pickup the FPSCR + STR r2, [sp, -4]! # Save FPSCR + VSTMDB sp!, {D16-D31} # Save D16-D31 + VSTMDB sp!, {D0-D15} # Save D0-D15 +_tx_skip_fiq_vfp_save: +#endif + + MOV r3, 1 # Build interrupt stack type + STMDB sp!, {r3, r4} # Save interrupt stack type and SPSR + STR sp, [r0, 8] # Save stack pointer in thread control + /* # block */ + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r4, r0 # Save r0 + MOV r5, r1 # Save r1 + BL _tx_el_thread_preempted # Call thread preempted routine + MOV r0, r4 # Restore r0 + MOV r1, r5 # Restore r1 +#endif + + /* Save the remaining time-slice and disable it. */ + /* if (_tx_timer_time_slice) + { */ + + LDR r3, =_tx_timer_time_slice # Pickup time-slice variable address + LDR r2, [r3] # Pickup time-slice + CMP r2, 0 # Is it active? + BEQ __tx_thread_fiq_dont_save_ts # No, don't save it + + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + STR r2, [r0, 24] # Save thread's time-slice + MOV r2, 0 # Clear value + STR r2, [r3] # Disable global time-slice flag + + /* } */ +__tx_thread_fiq_dont_save_ts: + + + /* Clear the current task pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + MOV r0, 0 # NULL value + STR r0, [r1] # Clear current thread pointer + + /* Return to the scheduler. */ + /* _tx_thread_schedule(); */ + + B _tx_thread_schedule # Return to scheduler + /* } */ + +__tx_thread_fiq_idle_system_restore: + + /* Just return back to the scheduler! */ + + ADD sp, sp, 24 # Recover FIQ stack space + MOV r3, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r3 # Lockout interrupts + B _tx_thread_schedule # Return to scheduler + + .type _tx_thread_fiq_context_restore,$function + .size _tx_thread_fiq_context_restore,.-_tx_thread_fiq_context_restore + +/* } */ + diff --git a/ports/cortex_a7/green/src/tx_thread_fiq_context_save.arm b/ports/cortex_a7/green/src/tx_thread_fiq_context_save.arm new file mode 100644 index 00000000..31d75d6b --- /dev/null +++ b/ports/cortex_a7/green/src/tx_thread_fiq_context_save.arm @@ -0,0 +1,197 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_context_save Cortex-A7/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_fiq_context_save(VOID) +{ */ + .globl _tx_thread_fiq_context_save +_tx_thread_fiq_context_save: + + /* Upon entry to this routine, it is assumed that IRQ interrupts are locked + out, we are in IRQ mode, and all registers are intact. */ + + /* Check for a nested interrupt condition. */ + /* if (_tx_thread_system_state++) + { */ + + STMDB sp!, {r0-r3} # Save some working registers + LDR r3, =_tx_thread_system_state # Pickup address of system state var + LDR r2, [r3] # Pickup system state + CMP r2, 0 # Is this the first interrupt? + BEQ __tx_thread_fiq_not_nested_save # Yes, not a nested context save + + /* Nested interrupt condition. */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + + /* Save the rest of the scratch registers on the stack and return to the + calling ISR. */ + + MRS r0, SPSR # Pickup saved SPSR + SUB lr, lr, 4 # Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} # Store other registers + + /* Return to the ISR. */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + B __tx_fiq_processing_return # Continue FIQ processing + +__tx_thread_fiq_not_nested_save: + /* } */ + + /* Otherwise, not nested, check to see if a thread was running. */ + /* else if (_tx_thread_current_ptr) + { */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup current thread pointer + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_fiq_idle_system_save # If so, interrupt occurred in + /* # scheduling loop - nothing needs saving! */ + + /* Save minimal context of interrupted thread. */ + + MRS r2, SPSR # Pickup saved SPSR + SUB lr, lr, 4 # Adjust point of interrupt + STMDB sp!, {r2, lr} # Store other registers, Note that we don't + /* # need to save sl and ip since FIQ has + # copies of these registers. Nested + # interrupt processing does need to save + # these registers. */ + + /* Save the current stack pointer in the thread's control block. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ + + /* Switch to the system stack. */ + /* sp = _tx_thread_system_stack_ptr; */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + B __tx_fiq_processing_return # Continue FIQ processing + + /* } + else + { */ + +__tx_thread_fiq_idle_system_save: + + /* Interrupt occurred in the scheduling loop. */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + /* Not much to do here, save the current SPSR and LR for possible + use in IRQ interrupted in idle system conditions, and return to + FIQ interrupt processing. */ + + MRS r0, SPSR # Pickup saved SPSR + SUB lr, lr, 4 # Adjust point of interrupt + STMDB sp!, {r0, lr} # Store other registers that will get used + /* # or stripped off the stack in context + # restore */ + B __tx_fiq_processing_return # Continue FIQ processing + + .type _tx_thread_fiq_context_save,$function + .size _tx_thread_fiq_context_save,.-_tx_thread_fiq_context_save + + /* } +} */ + diff --git a/ports/cortex_a7/green/src/tx_thread_fiq_nesting_end.arm b/ports/cortex_a7/green/src/tx_thread_fiq_nesting_end.arm new file mode 100644 index 00000000..4e9c058d --- /dev/null +++ b/ports/cortex_a7/green/src/tx_thread_fiq_nesting_end.arm @@ -0,0 +1,109 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # Disable IRQ and FIQ interrupts +#else + DISABLE_INTS = 0x80 # Disable IRQ interrupts +#endif + MODE_MASK = 0x1F # Mode mask + FIQ_MODE_BITS = 0x11 # FIQ mode bits + SVC_MODE_BITS = 0x13 # SVC mode value */ + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_nesting_end Cortex-A7/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from FIQ mode after */ +/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +/* processing from system mode back to FIQ mode prior to the ISR */ +/* calling _tx_thread_fiq_context_restore. Note that this function */ +/* assumes the system stack pointer is in the same position after */ +/* nesting start function was called. */ +/* */ +/* This function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.arm). */ +/* */ +/* This function returns with FIQ interrupts disabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_fiq_nesting_end(VOID) +{ */ + .globl _tx_thread_fiq_nesting_end +_tx_thread_fiq_nesting_end: + MOV r3,lr # Save ISR return address + MRS r0, CPSR # Pickup the CPSR + ORR r0, r0, DISABLE_INTS # Build disable interrupt value + MSR CPSR_c, r0 # Disable interrupts + LDR lr, [sp] # Pickup saved lr + ADD sp, sp, 4 # Adjust stack pointer + BIC r0, r0, MODE_MASK # Clear mode bits + ORR r0, r0, FIQ_MODE_BITS # Build IRQ mode CPSR + MSR CPSR_c, r0 # Re-enter IRQ mode + MOV pc, r3 # Return to ISR + + .type _tx_thread_fiq_nesting_end,$function + .size _tx_thread_fiq_nesting_end,.-_tx_thread_fiq_nesting_end +/* } */ + diff --git a/ports/cortex_a7/green/src/tx_thread_fiq_nesting_start.arm b/ports/cortex_a7/green/src/tx_thread_fiq_nesting_start.arm new file mode 100644 index 00000000..7ebf3e47 --- /dev/null +++ b/ports/cortex_a7/green/src/tx_thread_fiq_nesting_start.arm @@ -0,0 +1,103 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + + FIQ_DISABLE = 0x40 # FIQ disable bit + MODE_MASK = 0x1F # Mode mask + SYS_MODE_BITS = 0x1F # System mode bits + + + .text + .align 4 + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_nesting_start Cortex-A7/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from FIQ mode after */ +/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +/* processing to the system mode so nested FIQ interrupt processing */ +/* is possible (system mode has its own "lr" register). Note that */ +/* this function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.arm). */ +/* */ +/* This function returns with FIQ interrupts enabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_fiq_nesting_start(VOID) +{ */ + .globl _tx_thread_fiq_nesting_start +_tx_thread_fiq_nesting_start: + MOV r3,lr # Save ISR return address + MRS r0, CPSR # Pickup the CPSR + BIC r0, r0, MODE_MASK # Clear the mode bits + ORR r0, r0, SYS_MODE_BITS # Build system mode CPSR + MSR CPSR_c, r0 # Enter system mode + STR lr, [sp, -4]! # Push the system mode lr on the system mode stack + BIC r0, r0, FIQ_DISABLE # Build enable FIQ CPSR + MSR CPSR_c, r0 # Enter system mode + MOV pc, r3 # Return to ISR + + .type _tx_thread_fiq_nesting_start,$function + .size _tx_thread_fiq_nesting_start,.-_tx_thread_fiq_nesting_start +/* } */ + diff --git a/ports/cortex_a7/green/src/tx_thread_interrupt_control.arm b/ports/cortex_a7/green/src/tx_thread_interrupt_control.arm new file mode 100644 index 00000000..c3bf37a0 --- /dev/null +++ b/ports/cortex_a7/green/src/tx_thread_interrupt_control.arm @@ -0,0 +1,101 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" */ + + +#ifdef TX_ENABLE_FIQ_SUPPORT + INT_MASK = 0xC0 # Interrupt bit mask +#else + INT_MASK = 0x80 # Interrupt bit mask +#endif + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control Cortex-A7/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_control(UINT new_posture) +{ */ + .globl _tx_thread_interrupt_control +_tx_thread_interrupt_control: + + /* Pickup current interrupt lockout posture. */ + + MRS r3, CPSR # Pickup current CPSR + BIC r1, r3, INT_MASK # Clear interrupt lockout bits + ORR r1, r1, r0 # Or-in new interrupt lockout bits + + /* Apply the new interrupt posture. */ + + MSR CPSR_c, r1 # Setup new CPSR + AND r0, r3, INT_MASK # Return previous interrupt mask + RET # Return to caller + + .type _tx_thread_interrupt_control,$function + .size _tx_thread_interrupt_control,.-_tx_thread_interrupt_control +/* } */ + + + diff --git a/ports/cortex_a7/green/src/tx_thread_interrupt_disable.arm b/ports/cortex_a7/green/src/tx_thread_interrupt_disable.arm new file mode 100644 index 00000000..cecddc22 --- /dev/null +++ b/ports/cortex_a7/green/src/tx_thread_interrupt_disable.arm @@ -0,0 +1,105 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" */ + + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # IRQ & FIQ interrupts disabled +#else + DISABLE_INTS = 0x80 # IRQ interrupts disabled +#endif + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_disable Cortex-A7/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for disabling interrupts */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_disable(void) +{ */ + .globl _tx_thread_interrupt_disable +_tx_thread_interrupt_disable: + + /* Pickup current interrupt lockout posture. */ + + MRS r0, CPSR # Pickup current CPSR + + /* Mask interrupts. */ + +#ifdef TX_BEFORE_ARMV6 + ORR r1, r0, DISABLE_INTS # Mask interrupts + MSR CPSR_c, r1 # Setup new CPSR +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if # Disable IRQ and FIQ +#else + CPSID i # Disable IRQ +#endif +#endif + + RET # Return previous CPSR value + + .type _tx_thread_interrupt_disable,$function + .size _tx_thread_interrupt_disable,.-_tx_thread_interrupt_disable +/* } */ + diff --git a/ports/cortex_a7/green/src/tx_thread_interrupt_restore.arm b/ports/cortex_a7/green/src/tx_thread_interrupt_restore.arm new file mode 100644 index 00000000..930d889e --- /dev/null +++ b/ports/cortex_a7/green/src/tx_thread_interrupt_restore.arm @@ -0,0 +1,85 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" */ + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_restore Cortex-A7/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for restoring interrupts to the state */ +/* returned by a previous _tx_thread_interrupt_disable call. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_interrupt_restore(UINT new_posture) +{ */ + .globl _tx_thread_interrupt_restore +_tx_thread_interrupt_restore: + + /* Apply the new interrupt posture. */ + + MSR CPSR_c, r0 # Setup new CPSR + RET + + .type _tx_thread_interrupt_restore,$function + .size _tx_thread_interrupt_restore,.-_tx_thread_interrupt_restore +/* } */ + diff --git a/ports/cortex_a7/green/src/tx_thread_irq_nesting_end.arm b/ports/cortex_a7/green/src/tx_thread_irq_nesting_end.arm new file mode 100644 index 00000000..27e85ace --- /dev/null +++ b/ports/cortex_a7/green/src/tx_thread_irq_nesting_end.arm @@ -0,0 +1,109 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # Disable IRQ and FIQ interrupts +#else + DISABLE_INTS = 0x80 # Disable IRQ interrupts +#endif + MODE_MASK = 0x1F # Mode mask + IRQ_MODE_BITS = 0x12 # IRQ mode bits + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_irq_nesting_end Cortex-A7/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from IRQ mode after */ +/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +/* processing from system mode back to IRQ mode prior to the ISR */ +/* calling _tx_thread_context_restore. Note that this function */ +/* assumes the system stack pointer is in the same position after */ +/* nesting start function was called. */ +/* */ +/* This function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.arm). */ +/* */ +/* This function returns with IRQ interrupts disabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_irq_nesting_end(VOID) +{ */ + .globl _tx_thread_irq_nesting_end +_tx_thread_irq_nesting_end: + MOV r3,lr # Save ISR return address + MRS r0, CPSR # Pickup the CPSR + ORR r0, r0, DISABLE_INTS # Build disable interrupt value + MSR CPSR_c, r0 # Disable interrupts + LDR lr, [sp] # Pickup saved lr + ADD sp, sp, 4 # Adjust stack pointer + BIC r0, r0, MODE_MASK # Clear mode bits + ORR r0, r0, IRQ_MODE_BITS # Build IRQ mode CPSR + MSR CPSR_c, r0 # Re-enter IRQ mode + MOV pc, r3 # Return to ISR + + .type _tx_thread_irq_nesting_end,$function + .size _tx_thread_irq_nesting_end,.-_tx_thread_irq_nesting_end + +/* } */ + diff --git a/ports/cortex_a7/green/src/tx_thread_irq_nesting_start.arm b/ports/cortex_a7/green/src/tx_thread_irq_nesting_start.arm new file mode 100644 index 00000000..e9473ee3 --- /dev/null +++ b/ports/cortex_a7/green/src/tx_thread_irq_nesting_start.arm @@ -0,0 +1,102 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + + IRQ_DISABLE = 0x80 # IRQ disable bit + MODE_MASK = 0x1F # Mode mask + SYS_MODE_BITS = 0x1F # System mode bits + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_irq_nesting_start Cortex-A7/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from IRQ mode after */ +/* _tx_thread_context_save has been called and switches the IRQ */ +/* processing to the system mode so nested IRQ interrupt processing */ +/* is possible (system mode has its own "lr" register). Note that */ +/* this function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.arm). */ +/* */ +/* This function returns with IRQ interrupts enabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_irq_nesting_start(VOID) +{ */ + .globl _tx_thread_irq_nesting_start +_tx_thread_irq_nesting_start: + MOV r3,lr # Save ISR return address + MRS r0, CPSR # Pickup the CPSR + BIC r0, r0, MODE_MASK # Clear the mode bits + ORR r0, r0, SYS_MODE_BITS # Build system mode CPSR + MSR CPSR_c, r0 # Enter system mode + STR lr, [sp, -4]! # Push the system mode lr on the system mode stack + BIC r0, r0, IRQ_DISABLE # Build enable IRQ CPSR + MSR CPSR_c, r0 # Enter system mode + MOV pc, r3 # Return to ISR + + .type _tx_thread_irq_nesting_start,$function + .size _tx_thread_irq_nesting_start,.-_tx_thread_irq_nesting_start +/* } */ + diff --git a/ports/cortex_a7/green/src/tx_thread_schedule.arm b/ports/cortex_a7/green/src/tx_thread_schedule.arm new file mode 100644 index 00000000..1e3d7206 --- /dev/null +++ b/ports/cortex_a7/green/src/tx_thread_schedule.arm @@ -0,0 +1,253 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + ENABLE_INTS = 0xC0 # IRQ & FIQ Interrupts enabled mask +#else + ENABLE_INTS = 0x80 # IRQ Interrupts enabled mask +#endif + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule Cortex-A7/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* _tx_thread_context_restore Restore thread's context */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_schedule(VOID) +{ */ + .globl _tx_thread_schedule +_tx_thread_schedule: + + /* Enable interrupts. */ + +#ifdef TX_BEFORE_ARMV6 + MRS r2, CPSR # Pickup CPSR + BIC r0, r2, ENABLE_INTS # Clear the disable bit(s) + MSR CPSR_c, r0 # Enable interrupts +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSIE if # Enable IRQ and FIQ interrupts +#else + CPSIE i # Enable IRQ interrupts +#endif +#endif + + /* Wait for a thread to execute. */ + /* do + { */ + LDR r1, =_tx_thread_execute_ptr # Address of thread execute ptr + +__tx_thread_schedule_loop: + + LDR r0, [r1] # Pickup next thread to execute + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_schedule_loop # If so, keep looking for a thread + + /* } + while(_tx_thread_execute_ptr == TX_NULL); */ + + /* Yes! We have a thread to execute. Lockout interrupts and + transfer control to it. */ + +#ifdef TX_BEFORE_ARMV6 + MSR CPSR_c, r2 # Disable interrupts +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if # Disable IRQ and FIQ interrupts +#else + CPSID i # Disable IRQ interrupts +#endif +#endif + + /* Setup the current thread pointer. */ + /* _tx_thread_current_ptr = _tx_thread_execute_ptr; */ + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV v1, r0 # Save temp register in non-volatile register + BL _tx_el_thread_running # Call event logging routine + MOV r0, v1 # Restore temp register +#endif + + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread + STR r0, [r1] # Setup current thread pointer + + /* Increment the run count for this thread. */ + /* _tx_thread_current_ptr -> tx_thread_run_count++; */ + + LDR r2, [r0, 4] # Pickup run counter + LDR r3, [r0, 24] # Pickup time-slice for this thread + ADD r2, r2, 1 # Increment thread run-counter + STR r2, [r0, 4] # Store the new run counter + + /* Setup time-slice, if present. */ + /* _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; */ + + LDR r2, =_tx_timer_time_slice # Pickup address of time slice + /* # variable */ + LDR sp, [r0, 8] # Switch stack pointers + STR r3, [r2] # Setup time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread entry function to indicate the thread is executing. */ + + MOV r5, r0 # Save r0 + BL _tx_execution_thread_enter # Call the thread execution enter function + MOV r0, r5 # Restore r0 +#endif + + /* Switch to the thread's stack. */ + /* sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; */ + + /* Determine if an interrupt frame or a synchronous task suspension frame + is present. */ + + LDMIA sp!, {r4, r5} # Pickup the stack type and saved CPSR + CMP r4, 0 # Check for synchronous context switch + BEQ _tx_solicited_return + MSR SPSR_cxsf, r5 # Setup SPSR for return +#ifdef __VFP__ + LDR r1, [r0, 144] # Pickup the VFP enabled flag + CMP r1, 0 # Is the VFP enabled? + BEQ _tx_skip_interrupt_vfp_restore # No, skip VFP interrupt restore + VLDMIA sp!, {D0-D15} # Recover D0-D15 + VLDMIA sp!, {D16-D31} # Recover D16-D31 + LDR r4, [sp], 4 # Pickup FPSCR + VMSR FPSCR, r4 # Restore FPSCR +_tx_skip_interrupt_vfp_restore: +#endif + LDMIA sp!, {r0-r12, lr, pc}^ # Return to point of thread interrupt + +_tx_solicited_return: +#ifdef __VFP__ + LDR r1, [r0, 144] # Pickup the VFP enabled flag + CMP r1, 0 # Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_restore # No, skip VFP solicited restore + VLDMIA sp!, {D8-D15} # Recover D8-D15 + VLDMIA sp!, {D16-D31} # Recover D16-D31 + LDR r4, [sp], 4 # Pickup FPSCR + VMSR FPSCR, r4 # Restore FPSCR +_tx_skip_solicited_vfp_restore: +#endif + MSR CPSR_cxsf, r5 # Recover CPSR + LDMIA sp!, {r4-r11, lr} # Return to thread synchronously + RET # Return to caller (Thumb safe) + + .type _tx_thread_schedule,$function + .size _tx_thread_schedule,.-_tx_thread_schedule + +#ifdef __VFP__ + .globl tx_thread_vfp_enable +tx_thread_vfp_enable: + MRS r2, CPSR # Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSIE if # Enable IRQ and FIQ interrupts +#else + CPSIE i # Enable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr # Build current thread pointer address + LDR r1, [r0] # Pickup current thread pointer + CMP r1, 0 # Check for NULL thread pointer + BEQ __tx_no_thread_to_enable # If NULL, skip VFP enable + MOV r0, 1 # Build enable value + STR r0, [r1, 144] # Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_enable: + MSR CPSR_cxsf, r2 # Recover CPSR + RET # Return to caller (Thumb safe) + + .type tx_thread_vfp_enable,$function + .size tx_thread_vfp_enable,.-tx_thread_vfp_enable + + + .globl tx_thread_vfp_disable +tx_thread_vfp_disable: + MRS r2, CPSR # Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSIE if # Enable IRQ and FIQ interrupts +#else + CPSIE i # Enable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr # Build current thread pointer address + LDR r1, [r0] # Pickup current thread pointer + CMP r1, 0 # Check for NULL thread pointer + BEQ __tx_no_thread_to_disable # If NULL, skip VFP disable + MOV r0, 0 # Build disable value + STR r0, [r1, 144] # Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_disable: + MSR CPSR_cxsf, r2 # Recover CPSR + RET # Return to caller (Thumb safe) + + .type tx_thread_vfp_disable,$function + .size tx_thread_vfp_disable,.-tx_thread_vfp_disable + +#endif + +/* } */ + + diff --git a/ports/cortex_a7/green/src/tx_thread_stack_build.arm b/ports/cortex_a7/green/src/tx_thread_stack_build.arm new file mode 100644 index 00000000..d9450813 --- /dev/null +++ b/ports/cortex_a7/green/src/tx_thread_stack_build.arm @@ -0,0 +1,161 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" */ + + SVC_MODE = 0x13 # SVC mode +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSR_MASK = 0xDF # Mask initial CPSR, IRQ & FIQ ints enabled +#else + CPSR_MASK = 0x9F # Mask initial CPSR, IRQ ints enabled +#endif + + THUMB_BIT = 0x20 # Thumb-bit + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build Cortex-A7/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +{ */ + .globl _tx_thread_stack_build +_tx_thread_stack_build: + + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-A7 should look like the following after it is built: + + Stack Top: 1 Interrupt stack frame type + CPSR Initial value for CPSR + r0 (a1) Initial value for r0 + r1 (a2) Initial value for r1 + r2 (a3) Initial value for r2 + r3 (a4) Initial value for r3 + r4 (v1) Initial value for r4 + r5 (v2) Initial value for r5 + r6 (v3) Initial value for r6 + r7 (v4) Initial value for r7 + r8 (v5) Initial value for r8 + r9 (sb) Initial value for r9 + r10 (sl) Initial value for r10 + r11 (fp) Initial value for r11 + r12 (ip) Initial value for r12 + lr Initial value for lr + pc Initial value for pc + 0 For stack backtracing + + Stack Bottom: (higher memory address) */ + + LDR r2, [r0, 16] # Pickup end of stack area + BIC r2, r2, 7 # Ensure 8-byte alignment + SUB r2, r2, 76 # Allocate space for the stack frame + + /* Actually build the stack frame. */ + + MOV r3, 1 # Build interrupt stack type + STR r3, [r2] # Store stack type + MOV r3, 0 # Build initial register value + STR r3, [r2, 8] # Store initial r0 + STR r3, [r2, 12] # Store initial r1 + STR r3, [r2, 16] # Store initial r2 + STR r3, [r2, 20] # Store initial r3 + STR r3, [r2, 24] # Store initial r4 + STR r3, [r2, 28] # Store initial r5 + STR r3, [r2, 32] # Store initial r6 + STR r3, [r2, 36] # Store initial r7 + STR r3, [r2, 40] # Store initial r8 + STR r3, [r2, 44] # Store initial r9 + LDR r3, [r0, 12] # Pickup stack starting address + STR r3, [r2, 48] # Store initial r10 + MOV r3, 0 # Build initial register value + STR r3, [r2, 52] # Store initial r11 + STR r3, [r2, 56] # Store initial r12 + STR r3, [r2, 60] # Store initial lr + STR r1, [r2, 64] # Store initial pc + STR r3, [r2, 68] # 0 for back-trace + + MRS r3, CPSR # Pickup CPSR + BIC r3, r3, CPSR_MASK # Mask mode bits of CPSR + ORR r3, r3, SVC_MODE # Build CPSR, SVC mode, interrupts enabled + BIC r3, r3, #THUMB_BIT # Clear Thumb-bit by default + AND r1, r1, #1 # Determine if the entry function is in Thumb mode + CMP r1, 1 # Is the Thumb-bit set? + ORREQ r3, r3, #THUMB_BIT # Yes, set the Thumb-bit + STR r3, [r2, 4] # Store initial CPSR + + /* Setup stack pointer. */ + /* thread_ptr -> tx_thread_stack_ptr = r2; */ + + STR r2, [r0, 8] # Save stack pointer in thread's + /* # control block */ + RET # Return to caller + + .type _tx_thread_stack_build,$function + .size _tx_thread_stack_build,.-_tx_thread_stack_build +/* } */ + diff --git a/ports/cortex_a7/green/src/tx_thread_system_return.arm b/ports/cortex_a7/green/src/tx_thread_system_return.arm new file mode 100644 index 00000000..58b5a013 --- /dev/null +++ b/ports/cortex_a7/green/src/tx_thread_system_return.arm @@ -0,0 +1,167 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # IRQ & FIQ interrupts disabled +#else + DISABLE_INTS = 0x80 # IRQ interrupts disabled +#endif + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return Cortex-A7/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the ThreadX system. Only a */ +/* minimal context is saved since the compiler assumes temp registers */ +/* are going to get slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_system_return(VOID) +{ */ + .globl _tx_thread_system_return +_tx_thread_system_return: + + /* Save minimal context on the stack. */ + + MOV r0, 0 # Build a solicited stack type + MRS r1, CPSR # Pickup the CPSR + STMDB sp!, {r4-r11, lr} # Save minimal context + + LDR r4, =_tx_thread_current_ptr # Pickup address of current ptr + LDR r5, [r4] # Pickup current thread pointer + +#ifdef __VFP__ + LDR r1, [r5, 144] # Pickup the VFP enabled flag + CMP r1, 0 # Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_save # No, skip VFP solicited save + VMRS r1, FPSCR # Pickup the FPSCR + STR r1, [sp, -4]! # Save FPSCR + VSTMDB sp!, {D16-D31} # Save D16-D31 + VSTMDB sp!, {D8-D15} # Save D8-D15 +_tx_skip_solicited_vfp_save: +#endif + + MOV r0, #0 # Build a solicited stack type + MRS r1, CPSR # Pickup the CPSR + STMDB sp!, {r0-r1} # Save type and CPSR + + /* Lockout interrupts. */ + +#ifdef TX_BEFORE_ARMV6 + ORR r2, r1, DISABLE_INTS # Build disable interrupt CPSR + MSR CPSR_c, r2 # Disable interrupts +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if # Disable IRQ and FIQ interrupts +#else + CPSID i # Disable IRQ interrutps +#endif +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread exit function to indicate the thread is no longer executing. */ + + BL _tx_execution_thread_exit # Call the thread exit function +#endif + + MOV r3, r4 # Pickup address of current ptr + MOV r0, r5 # Pickup current thread pointer + LDR r2, =_tx_timer_time_slice # Pickup address of time slice + LDR r1, [r2] # Pickup current time slice + + /* Save current stack and switch to system stack. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; + sp = _tx_thread_system_stack_ptr; */ + + STR sp, [r0, 8] # Save thread stack pointer + + /* Determine if the time-slice is active. */ + /* if (_tx_timer_time_slice) + { */ + + MOV r4, 0 # Build clear value + CMP r1, 0 # Is a time-slice active? + BEQ __tx_thread_dont_save_ts # No, don't save the current time-slice + + /* Save time-slice for the thread and clear the current time-slice. */ + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + STR r4, [r2, 0] # Clear time-slice + STR r1, [r0, 24] # Save current time-slice + + /* } */ +__tx_thread_dont_save_ts: + + /* Clear the current thread pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + STR r4, [r3] # Clear current thread pointer + B _tx_thread_schedule # Jump to scheduler! + + .type _tx_thread_system_return,$function + .size _tx_thread_system_return,.-_tx_thread_system_return +/* } */ + diff --git a/ports/cortex_a7/green/src/tx_thread_vectored_context_save.arm b/ports/cortex_a7/green/src/tx_thread_vectored_context_save.arm new file mode 100644 index 00000000..534d4642 --- /dev/null +++ b/ports/cortex_a7/green/src/tx_thread_vectored_context_save.arm @@ -0,0 +1,196 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # IRQ & FIQ interrupts disabled +#else + DISABLE_INTS = 0x80 # IRQ interrupts disabled +#endif + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_vectored_context_save Cortex-A7/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_vectored_context_save(VOID) +{ */ + .globl _tx_thread_vectored_context_save +_tx_thread_vectored_context_save: + + /* Upon entry to this routine, it is assumed that IRQ interrupts are locked + out, we are in IRQ mode, the minimal context is already saved, and the + lr register contains the return ISR address. */ + + /* Check for a nested interrupt condition. */ + /* if (_tx_thread_system_state++) + { */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#ifdef TX_BEFORE_ARMV6 + MRS r0, CPSR # Pickup the CPSR + ORR r0, r0, DISABLE_INTS # Build disable interrupt CPSR + MSR CPSR_c, r0 # Disable interrupts +#else + CPSID if # Disable IRQ and FIQ interrupts +#endif +#endif + LDR r3, =_tx_thread_system_state # Pickup address of system state var + LDR r2, [r3] # Pickup system state + CMP r2, 0 # Is this the first interrupt? + BEQ __tx_thread_not_nested_save # Yes, not a nested context save + + /* Nested interrupt condition. */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + + /* Note: Minimal context of interrupted thread is already saved. */ + + /* Return to the ISR. */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + MOV pc, lr # Return to caller + +__tx_thread_not_nested_save: + /* } */ + + /* Otherwise, not nested, check to see if a thread was running. */ + /* else if (_tx_thread_current_ptr) + { */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup current thread pointer + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_idle_system_save # If so, interrupt occurred in + /* # scheduling loop - nothing needs saving! */ + + /* Note: Minimal context of interrupted thread is already saved. */ + + /* Save the current stack pointer in the thread's control block. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ + + /* Switch to the system stack. */ + /* sp = _tx_thread_system_stack_ptr; */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + MOV pc, lr # Return to caller + + /* } + else + { */ + +__tx_thread_idle_system_save: + + /* Interrupt occurred in the scheduling loop. */ + + /* Not much to do here, just adjust the stack pointer, and return to IRQ + processing. */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + ADD sp, sp, 32 # Recover saved registers + MOV pc, lr # Return to caller + + .type _tx_thread_vectored_context_save,$function + .size _tx_thread_vectored_context_save,.-_tx_thread_vectored_context_save + + /* } +} */ + diff --git a/ports/cortex_a7/green/src/tx_timer_interrupt.arm b/ports/cortex_a7/green/src/tx_timer_interrupt.arm new file mode 100644 index 00000000..71c5357b --- /dev/null +++ b/ports/cortex_a7/green/src/tx_timer_interrupt.arm @@ -0,0 +1,241 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_timer.h" + #include "tx_thread.h" */ + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt Cortex-A7/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Process timer expiration */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_timer_interrupt(VOID) +{ */ + .globl _tx_timer_interrupt +_tx_timer_interrupt: + + /* Upon entry to this routine, it is assumed that context save has already + been called, and therefore the compiler scratch registers are available + for use. */ + + /* Increment the system clock. */ + /* _tx_timer_system_clock++; */ + + LDR r1, =_tx_timer_system_clock # Pickup address of system clock + LDR r0, [r1] # Pickup system clock + ADD r0, r0, 1 # Increment system clock + STR r0, [r1] # Store new system clock + + /* Test for time-slice expiration. */ + /* if (_tx_timer_time_slice) + { */ + + LDR r3, =_tx_timer_time_slice # Pickup address of time-slice + LDR r2, [r3] # Pickup time-slice + CMP r2, 0 # Is it non-active? + BEQ __tx_timer_no_time_slice # Yes, skip time-slice processing + + /* Decrement the time_slice. */ + /* _tx_timer_time_slice--; */ + + SUB r2, r2, 1 # Decrement the time-slice + STR r2, [r3] # Store new time-slice value + + /* Check for expiration. */ + /* if (__tx_timer_time_slice == 0) */ + + CMP r2, 0 # Has it expired? + BNE __tx_timer_no_time_slice # No, skip expiration processing + + /* Set the time-slice expired flag. */ + /* _tx_timer_expired_time_slice = TX_TRUE; */ + + LDR r3,=_tx_timer_expired_time_slice # Pickup address of expired flag + MOV r0, 1 # Build expired value + STR r0, [r3] # Set time-slice expiration flag + + /* } */ + +__tx_timer_no_time_slice: + + /* Test for timer expiration. */ + /* if (*_tx_timer_current_ptr) + { */ + + LDR r1, =_tx_timer_current_ptr # Pickup current timer pointer addr + LDR r0, [r1] # Pickup current timer + LDR r2, [r0] # Pickup timer list entry + CMP r2, 0 # Is there anything in the list? + BEQ __tx_timer_no_timer # No, just increment the timer + + /* Set expiration flag. */ + /* _tx_timer_expired = TX_TRUE; */ + + LDR r3, =_tx_timer_expired # Pickup expiration flag address + MOV r2, 1 # Build expired value + STR r2, [r3] # Set expired flag + B __tx_timer_done # Finished timer processing + + /* } + else + { */ +__tx_timer_no_timer: + + /* No timer expired, increment the timer pointer. */ + /* _tx_timer_current_ptr++; */ + + ADD r0, r0, 4 # Move to next timer + + /* Check for wrap-around. */ + /* if (_tx_timer_current_ptr == _tx_timer_list_end) */ + + LDR r3, =_tx_timer_list_end # Pickup addr of timer list end + LDR r2, [r3] # Pickup list end + CMP r0, r2 # Are we at list end? + BNE __tx_timer_skip_wrap # No, skip wrap-around logic + + /* Wrap to beginning of list. */ + /* _tx_timer_current_ptr = _tx_timer_list_start; */ + + LDR r3, =_tx_timer_list_start # Pickup addr of timer list start + LDR r0, [r3] # Set current pointer to list start + +__tx_timer_skip_wrap: + + STR r0, [r1] # Store new current timer pointer + /* } */ + +__tx_timer_done: + + + /* See if anything has expired. */ + /* if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) + { */ + + LDR r3, =_tx_timer_expired_time_slice # Pickup addr of expired flag + LDR r2, [r3] # Pickup time-slice expired flag + CMP r2, 0 # Did a time-slice expire? + BNE __tx_something_expired # If non-zero, time-slice expired + LDR r1, =_tx_timer_expired # Pickup addr of other expired flag + LDR r0, [r1] # Pickup timer expired flag + CMP r0, 0 # Did a timer expire? + BEQ __tx_timer_nothing_expired # No, nothing expired + +__tx_something_expired: + + + STMDB sp!, {r0, lr} # Save the lr register on the stack + /* # and save r0 just to keep 8-byte alignment */ + + /* Did a timer expire? */ + /* if (_tx_timer_expired) + { */ + + LDR r1, =_tx_timer_expired # Pickup addr of expired flag + LDR r0, [r1] # Pickup timer expired flag + CMP r0, 0 # Check for timer expiration + BEQ __tx_timer_dont_activate # If not set, skip timer activation + + /* Process the timer expiration. */ + /* _tx_timer_expiration_process(); */ + BL _tx_timer_expiration_process # Call the timer expiration handling routine + + /* } */ +__tx_timer_dont_activate: + + /* Did time slice expire? */ + /* if (_tx_timer_expired_time_slice) + { */ + + LDR r3, =_tx_timer_expired_time_slice # Pickup addr of time-slice expired + LDR r2, [r3] # Pickup the actual flag + CMP r2, 0 # See if the flag is set + BEQ __tx_timer_not_ts_expiration # No, skip time-slice processing + + /* Time slice interrupted thread. */ + /* _tx_thread_time_slice(); */ + + BL _tx_thread_time_slice # Call time-slice processing + + /* } */ +__tx_timer_not_ts_expiration: + + + LDMIA sp!, {r0, lr} # Recover lr register (r0 is just there for + /* # the 8-byte stack alignment */ + + /* } */ + +__tx_timer_nothing_expired: + + RET # Return to caller + + .type _tx_timer_interrupt,$function + .size _tx_timer_interrupt,.-_tx_timer_interrupt +/* } */ + diff --git a/ports/cortex_a7/iar/example_build/tx_initialize_low_level.s b/ports/cortex_a7/iar/example_build/tx_initialize_low_level.s index c8eabf0c..fcc2598c 100644 --- a/ports/cortex_a7/iar/example_build/tx_initialize_low_level.s +++ b/ports/cortex_a7/iar/example_build/tx_initialize_low_level.s @@ -81,7 +81,7 @@ __tx_free_memory_start ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level Cortex-A7/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -114,7 +114,7 @@ __tx_free_memory_start ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_a7/iar/inc/tx_port.h b/ports/cortex_a7/iar/inc/tx_port.h index 73ea8e18..d339d526 100644 --- a/ports/cortex_a7/iar/inc/tx_port.h +++ b/ports/cortex_a7/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A7/IAR */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -380,7 +380,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/IAR Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/IAR Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a7/iar/readme_threadx.txt b/ports/cortex_a7/iar/readme_threadx.txt index 0b12c22c..534f8465 100644 --- a/ports/cortex_a7/iar/readme_threadx.txt +++ b/ports/cortex_a7/iar/readme_threadx.txt @@ -534,7 +534,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX version 6.0.1 for Cortex-A7 using IAR's ARM tools. +09-30-2020 Initial ThreadX version 6.1 for Cortex-A7 using IAR's ARM tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_a7/iar/src/tx_thread_context_restore.s b/ports/cortex_a7/iar/src/tx_thread_context_restore.s index 559c05bf..977f9f65 100644 --- a/ports/cortex_a7/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_a7/iar/src/tx_thread_context_restore.s @@ -57,7 +57,7 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore Cortex-A7/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -89,7 +89,7 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_a7/iar/src/tx_thread_context_save.s b/ports/cortex_a7/iar/src/tx_thread_context_save.s index 0751e98a..d84c5d67 100644 --- a/ports/cortex_a7/iar/src/tx_thread_context_save.s +++ b/ports/cortex_a7/iar/src/tx_thread_context_save.s @@ -49,7 +49,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save Cortex-A7/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -80,7 +80,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_a7/iar/src/tx_thread_fiq_context_restore.s b/ports/cortex_a7/iar/src/tx_thread_fiq_context_restore.s index 03fb04b5..5b8fc22e 100644 --- a/ports/cortex_a7/iar/src/tx_thread_fiq_context_restore.s +++ b/ports/cortex_a7/iar/src/tx_thread_fiq_context_restore.s @@ -58,7 +58,7 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_context_restore Cortex-A7/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -90,7 +90,7 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_context_restore(VOID) diff --git a/ports/cortex_a7/iar/src/tx_thread_fiq_context_save.s b/ports/cortex_a7/iar/src/tx_thread_fiq_context_save.s index 339e227b..a07e97ad 100644 --- a/ports/cortex_a7/iar/src/tx_thread_fiq_context_save.s +++ b/ports/cortex_a7/iar/src/tx_thread_fiq_context_save.s @@ -42,7 +42,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_context_save Cortex-A7/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -73,7 +73,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ; VOID _tx_thread_fiq_context_save(VOID) diff --git a/ports/cortex_a7/iar/src/tx_thread_fiq_nesting_end.s b/ports/cortex_a7/iar/src/tx_thread_fiq_nesting_end.s index 87088021..836a17ef 100644 --- a/ports/cortex_a7/iar/src/tx_thread_fiq_nesting_end.s +++ b/ports/cortex_a7/iar/src/tx_thread_fiq_nesting_end.s @@ -44,7 +44,7 @@ FIQ_MODE_BITS DEFINE 0x11 ; FIQ mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_nesting_end Cortex-A7/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -83,7 +83,7 @@ FIQ_MODE_BITS DEFINE 0x11 ; FIQ mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_end(VOID) diff --git a/ports/cortex_a7/iar/src/tx_thread_fiq_nesting_start.s b/ports/cortex_a7/iar/src/tx_thread_fiq_nesting_start.s index 671cb6f9..603b7c2c 100644 --- a/ports/cortex_a7/iar/src/tx_thread_fiq_nesting_start.s +++ b/ports/cortex_a7/iar/src/tx_thread_fiq_nesting_start.s @@ -41,7 +41,7 @@ SYS_MODE_BITS DEFINE 0x1F ; System mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_nesting_start Cortex-A7/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ SYS_MODE_BITS DEFINE 0x1F ; System mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/cortex_a7/iar/src/tx_thread_interrupt_control.s b/ports/cortex_a7/iar/src/tx_thread_interrupt_control.s index 61d091d0..6d699d2f 100644 --- a/ports/cortex_a7/iar/src/tx_thread_interrupt_control.s +++ b/ports/cortex_a7/iar/src/tx_thread_interrupt_control.s @@ -41,7 +41,7 @@ INT_MASK DEFINE 0x80 ; Interrupt bit mask ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control Cortex-A7/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ INT_MASK DEFINE 0x80 ; Interrupt bit mask ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a7/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_a7/iar/src/tx_thread_interrupt_disable.s index 27911f58..ec40503d 100644 --- a/ports/cortex_a7/iar/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_a7/iar/src/tx_thread_interrupt_disable.s @@ -42,7 +42,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_disable Cortex-A7/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports/cortex_a7/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_a7/iar/src/tx_thread_interrupt_restore.s index 80028df8..29f57554 100644 --- a/ports/cortex_a7/iar/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_a7/iar/src/tx_thread_interrupt_restore.s @@ -34,7 +34,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-A7/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -64,7 +64,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;void _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a7/iar/src/tx_thread_irq_nesting_end.s b/ports/cortex_a7/iar/src/tx_thread_irq_nesting_end.s index 72b794b6..3dc0d18c 100644 --- a/ports/cortex_a7/iar/src/tx_thread_irq_nesting_end.s +++ b/ports/cortex_a7/iar/src/tx_thread_irq_nesting_end.s @@ -45,7 +45,7 @@ IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_irq_nesting_end Cortex-A7/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -84,7 +84,7 @@ IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports/cortex_a7/iar/src/tx_thread_irq_nesting_start.s b/ports/cortex_a7/iar/src/tx_thread_irq_nesting_start.s index ceed092b..3a61d74c 100644 --- a/ports/cortex_a7/iar/src/tx_thread_irq_nesting_start.s +++ b/ports/cortex_a7/iar/src/tx_thread_irq_nesting_start.s @@ -41,7 +41,7 @@ SYS_MODE_BITS DEFINE 0x1F ; System mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_irq_nesting_start Cortex-A7/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ SYS_MODE_BITS DEFINE 0x1F ; System mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_a7/iar/src/tx_thread_schedule.s b/ports/cortex_a7/iar/src/tx_thread_schedule.s index fb11bd10..10d721db 100644 --- a/ports/cortex_a7/iar/src/tx_thread_schedule.s +++ b/ports/cortex_a7/iar/src/tx_thread_schedule.s @@ -49,7 +49,7 @@ ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-A7/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_a7/iar/src/tx_thread_stack_build.s b/ports/cortex_a7/iar/src/tx_thread_stack_build.s index 2ed9f538..9a23d523 100644 --- a/ports/cortex_a7/iar/src/tx_thread_stack_build.s +++ b/ports/cortex_a7/iar/src/tx_thread_stack_build.s @@ -43,7 +43,7 @@ CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints en ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build Cortex-A7/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -75,7 +75,7 @@ CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints en ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_a7/iar/src/tx_thread_system_return.s b/ports/cortex_a7/iar/src/tx_thread_system_return.s index 09d927db..a78c59dd 100644 --- a/ports/cortex_a7/iar/src/tx_thread_system_return.s +++ b/ports/cortex_a7/iar/src/tx_thread_system_return.s @@ -48,7 +48,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return Cortex-A7/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -80,7 +80,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_a7/iar/src/tx_thread_vectored_context_save.s b/ports/cortex_a7/iar/src/tx_thread_vectored_context_save.s index e73b7385..1d55c979 100644 --- a/ports/cortex_a7/iar/src/tx_thread_vectored_context_save.s +++ b/ports/cortex_a7/iar/src/tx_thread_vectored_context_save.s @@ -47,7 +47,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_vectored_context_save Cortex-A7/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -78,7 +78,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) diff --git a/ports/cortex_a7/iar/src/tx_timer_interrupt.s b/ports/cortex_a7/iar/src/tx_timer_interrupt.s index 1603243f..4103cbdd 100644 --- a/ports/cortex_a7/iar/src/tx_timer_interrupt.s +++ b/ports/cortex_a7/iar/src/tx_timer_interrupt.s @@ -49,7 +49,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt Cortex-A7/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -83,7 +83,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_a8/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_a8/ac5/example_build/tx_initialize_low_level.s index 580d5042..d7a6cb57 100644 --- a/ports/cortex_a8/ac5/example_build/tx_initialize_low_level.s +++ b/ports/cortex_a8/ac5/example_build/tx_initialize_low_level.s @@ -96,7 +96,7 @@ __vectors ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level Cortex-A8/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -129,7 +129,7 @@ __vectors ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_a8/ac5/inc/tx_port.h b/ports/cortex_a8/ac5/inc/tx_port.h index 4fb4e180..3f3889d9 100644 --- a/ports/cortex_a8/ac5/inc/tx_port.h +++ b/ports/cortex_a8/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A8/AC5 */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -324,7 +324,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A8/AC5 Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A8/AC5 Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a8/ac5/readme_threadx.txt b/ports/cortex_a8/ac5/readme_threadx.txt index ac883521..05355c12 100644 --- a/ports/cortex_a8/ac5/readme_threadx.txt +++ b/ports/cortex_a8/ac5/readme_threadx.txt @@ -537,7 +537,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A8 using AC5 tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-A8 using AC5 tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_a8/ac5/src/tx_thread_context_restore.s b/ports/cortex_a8/ac5/src/tx_thread_context_restore.s index 905651b4..c4ad07ba 100644 --- a/ports/cortex_a8/ac5/src/tx_thread_context_restore.s +++ b/ports/cortex_a8/ac5/src/tx_thread_context_restore.s @@ -60,7 +60,7 @@ SVC_MODE EQU 0x93 ; SVC mode ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore Cortex-A8/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -92,7 +92,7 @@ SVC_MODE EQU 0x93 ; SVC mode ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_a8/ac5/src/tx_thread_context_save.s b/ports/cortex_a8/ac5/src/tx_thread_context_save.s index ff1d228f..2b6ffca5 100644 --- a/ports/cortex_a8/ac5/src/tx_thread_context_save.s +++ b/ports/cortex_a8/ac5/src/tx_thread_context_save.s @@ -45,7 +45,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save Cortex-A8/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -76,7 +76,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_a8/ac5/src/tx_thread_fiq_context_restore.s b/ports/cortex_a8/ac5/src/tx_thread_fiq_context_restore.s index f41ee539..9efb6142 100644 --- a/ports/cortex_a8/ac5/src/tx_thread_fiq_context_restore.s +++ b/ports/cortex_a8/ac5/src/tx_thread_fiq_context_restore.s @@ -56,7 +56,7 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_context_restore Cortex-A8/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -88,7 +88,7 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_context_restore(VOID) diff --git a/ports/cortex_a8/ac5/src/tx_thread_fiq_context_save.s b/ports/cortex_a8/ac5/src/tx_thread_fiq_context_save.s index e31b7ef3..54d282e8 100644 --- a/ports/cortex_a8/ac5/src/tx_thread_fiq_context_save.s +++ b/ports/cortex_a8/ac5/src/tx_thread_fiq_context_save.s @@ -45,7 +45,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_context_save Cortex-A8/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -76,7 +76,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ; VOID _tx_thread_fiq_context_save(VOID) diff --git a/ports/cortex_a8/ac5/src/tx_thread_fiq_nesting_end.s b/ports/cortex_a8/ac5/src/tx_thread_fiq_nesting_end.s index a1204696..24608a33 100644 --- a/ports/cortex_a8/ac5/src/tx_thread_fiq_nesting_end.s +++ b/ports/cortex_a8/ac5/src/tx_thread_fiq_nesting_end.s @@ -45,7 +45,7 @@ FIQ_MODE_BITS EQU 0x11 ; FIQ mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_nesting_end Cortex-A8/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -84,7 +84,7 @@ FIQ_MODE_BITS EQU 0x11 ; FIQ mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_end(VOID) diff --git a/ports/cortex_a8/ac5/src/tx_thread_fiq_nesting_start.s b/ports/cortex_a8/ac5/src/tx_thread_fiq_nesting_start.s index f2fbf4f9..d693c217 100644 --- a/ports/cortex_a8/ac5/src/tx_thread_fiq_nesting_start.s +++ b/ports/cortex_a8/ac5/src/tx_thread_fiq_nesting_start.s @@ -41,7 +41,7 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_nesting_start Cortex-A8/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/cortex_a8/ac5/src/tx_thread_interrupt_control.s b/ports/cortex_a8/ac5/src/tx_thread_interrupt_control.s index c743a36d..78fa6c06 100644 --- a/ports/cortex_a8/ac5/src/tx_thread_interrupt_control.s +++ b/ports/cortex_a8/ac5/src/tx_thread_interrupt_control.s @@ -42,7 +42,7 @@ INT_MASK EQU 0x80 ; Interrupt bit mask ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control Cortex-A8/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ INT_MASK EQU 0x80 ; Interrupt bit mask ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a8/ac5/src/tx_thread_interrupt_disable.s b/ports/cortex_a8/ac5/src/tx_thread_interrupt_disable.s index 02439931..9872cf03 100644 --- a/ports/cortex_a8/ac5/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_a8/ac5/src/tx_thread_interrupt_disable.s @@ -35,7 +35,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_disable Cortex-A8/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -64,7 +64,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(void) diff --git a/ports/cortex_a8/ac5/src/tx_thread_interrupt_restore.s b/ports/cortex_a8/ac5/src/tx_thread_interrupt_restore.s index 9d328f1c..ea84dfba 100644 --- a/ports/cortex_a8/ac5/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_a8/ac5/src/tx_thread_interrupt_restore.s @@ -35,7 +35,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-A8/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -65,7 +65,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a8/ac5/src/tx_thread_irq_nesting_end.s b/ports/cortex_a8/ac5/src/tx_thread_irq_nesting_end.s index 1999adc1..91a7b564 100644 --- a/ports/cortex_a8/ac5/src/tx_thread_irq_nesting_end.s +++ b/ports/cortex_a8/ac5/src/tx_thread_irq_nesting_end.s @@ -45,7 +45,7 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_irq_nesting_end Cortex-A8/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -84,7 +84,7 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports/cortex_a8/ac5/src/tx_thread_irq_nesting_start.s b/ports/cortex_a8/ac5/src/tx_thread_irq_nesting_start.s index 5e1071aa..ce87e123 100644 --- a/ports/cortex_a8/ac5/src/tx_thread_irq_nesting_start.s +++ b/ports/cortex_a8/ac5/src/tx_thread_irq_nesting_start.s @@ -41,7 +41,7 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_irq_nesting_start Cortex-A8/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_a8/ac5/src/tx_thread_schedule.s b/ports/cortex_a8/ac5/src/tx_thread_schedule.s index 0e888c7e..3557a34c 100644 --- a/ports/cortex_a8/ac5/src/tx_thread_schedule.s +++ b/ports/cortex_a8/ac5/src/tx_thread_schedule.s @@ -46,7 +46,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-A8/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -79,7 +79,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_a8/ac5/src/tx_thread_stack_build.s b/ports/cortex_a8/ac5/src/tx_thread_stack_build.s index 7f7975f2..0d6673e6 100644 --- a/ports/cortex_a8/ac5/src/tx_thread_stack_build.s +++ b/ports/cortex_a8/ac5/src/tx_thread_stack_build.s @@ -47,7 +47,7 @@ THUMB_BIT EQU 0x20 ; Thumb-bit ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build Cortex-A8/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -79,7 +79,7 @@ THUMB_BIT EQU 0x20 ; Thumb-bit ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_a8/ac5/src/tx_thread_system_return.s b/ports/cortex_a8/ac5/src/tx_thread_system_return.s index 3812aa90..0e977e9b 100644 --- a/ports/cortex_a8/ac5/src/tx_thread_system_return.s +++ b/ports/cortex_a8/ac5/src/tx_thread_system_return.s @@ -45,7 +45,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return Cortex-A8/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_a8/ac5/src/tx_thread_vectored_context_save.s b/ports/cortex_a8/ac5/src/tx_thread_vectored_context_save.s index 342e8ba7..8896d073 100644 --- a/ports/cortex_a8/ac5/src/tx_thread_vectored_context_save.s +++ b/ports/cortex_a8/ac5/src/tx_thread_vectored_context_save.s @@ -44,7 +44,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_vectored_context_save Cortex-A8/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -75,7 +75,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) diff --git a/ports/cortex_a8/ac5/src/tx_timer_interrupt.s b/ports/cortex_a8/ac5/src/tx_timer_interrupt.s index b71d49b7..669f34d1 100644 --- a/ports/cortex_a8/ac5/src/tx_timer_interrupt.s +++ b/ports/cortex_a8/ac5/src/tx_timer_interrupt.s @@ -50,7 +50,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt Cortex-A8/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -84,7 +84,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_a8/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_a8/ac6/example_build/sample_threadx/tx_initialize_low_level.S index 9dfb7a25..aa4bee84 100644 --- a/ports/cortex_a8/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports/cortex_a8/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -75,7 +75,7 @@ $_tx_initialize_low_level: @/* FUNCTION RELEASE */ @/* */ @/* _tx_initialize_low_level Cortex-A8/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -108,7 +108,7 @@ $_tx_initialize_low_level: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_a8/ac6/inc/tx_port.h b/ports/cortex_a8/ac6/inc/tx_port.h index cdd68ecd..0dcdf194 100644 --- a/ports/cortex_a8/ac6/inc/tx_port.h +++ b/ports/cortex_a8/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A8/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -313,7 +313,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A8/AC6 Version 6.0.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A8/AC6 Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a8/ac6/readme_threadx.txt b/ports/cortex_a8/ac6/readme_threadx.txt index a3f367ab..fc0697bb 100644 --- a/ports/cortex_a8/ac6/readme_threadx.txt +++ b/ports/cortex_a8/ac6/readme_threadx.txt @@ -329,7 +329,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A8 using AC6 tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-A8 using AC6 tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_a8/ac6/src/tx_thread_context_restore.S b/ports/cortex_a8/ac6/src/tx_thread_context_restore.S index 6c32d0b8..2c4aa9d6 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_a8/ac6/src/tx_thread_context_restore.S @@ -59,7 +59,7 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_restore Cortex-A8/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -91,7 +91,7 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_a8/ac6/src/tx_thread_context_save.S b/ports/cortex_a8/ac6/src/tx_thread_context_save.S index fd4c9199..59de16f1 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_a8/ac6/src/tx_thread_context_save.S @@ -47,7 +47,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_save Cortex-A8/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -78,7 +78,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_a8/ac6/src/tx_thread_fiq_context_restore.S b/ports/cortex_a8/ac6/src/tx_thread_fiq_context_restore.S index 6d94d5cb..ae06b73d 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_a8/ac6/src/tx_thread_fiq_context_restore.S @@ -58,7 +58,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_context_restore Cortex-A8/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -90,7 +90,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_context_restore(VOID) diff --git a/ports/cortex_a8/ac6/src/tx_thread_fiq_context_save.S b/ports/cortex_a8/ac6/src/tx_thread_fiq_context_save.S index 521128a7..7ac4d8c5 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_a8/ac6/src/tx_thread_fiq_context_save.S @@ -46,7 +46,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_context_save Cortex-A8/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @ VOID _tx_thread_fiq_context_save(VOID) diff --git a/ports/cortex_a8/ac6/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a8/ac6/src/tx_thread_fiq_nesting_end.S index 3bfb4134..18375623 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a8/ac6/src/tx_thread_fiq_nesting_end.S @@ -50,7 +50,7 @@ FIQ_MODE_BITS = 0x11 @ FIQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_nesting_end Cortex-A8/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -89,7 +89,7 @@ FIQ_MODE_BITS = 0x11 @ FIQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_end(VOID) diff --git a/ports/cortex_a8/ac6/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a8/ac6/src/tx_thread_fiq_nesting_start.S index 632be482..54bc9312 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a8/ac6/src/tx_thread_fiq_nesting_start.S @@ -46,7 +46,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_nesting_start Cortex-A8/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/cortex_a8/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a8/ac6/src/tx_thread_interrupt_control.S index d7c0071e..d6a6c3e3 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a8/ac6/src/tx_thread_interrupt_control.S @@ -56,7 +56,7 @@ $_tx_thread_interrupt_control: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_control Cortex-A8/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -86,7 +86,7 @@ $_tx_thread_interrupt_control: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a8/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a8/ac6/src/tx_thread_interrupt_disable.S index fd002635..984ea3c5 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a8/ac6/src/tx_thread_interrupt_disable.S @@ -53,7 +53,7 @@ $_tx_thread_interrupt_disable: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_disable Cortex-A8/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ $_tx_thread_interrupt_disable: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_disable(void) diff --git a/ports/cortex_a8/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a8/ac6/src/tx_thread_interrupt_restore.S index 8ee63b2c..563eaa2d 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a8/ac6/src/tx_thread_interrupt_restore.S @@ -53,7 +53,7 @@ $_tx_thread_interrupt_restore: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_restore Cortex-A8/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -83,7 +83,7 @@ $_tx_thread_interrupt_restore: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a8/ac6/src/tx_thread_irq_nesting_end.S b/ports/cortex_a8/ac6/src/tx_thread_irq_nesting_end.S index aeac7b99..5e152c09 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a8/ac6/src/tx_thread_irq_nesting_end.S @@ -50,7 +50,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_irq_nesting_end Cortex-A8/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -89,7 +89,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports/cortex_a8/ac6/src/tx_thread_irq_nesting_start.S b/ports/cortex_a8/ac6/src/tx_thread_irq_nesting_start.S index e1eb663d..27836bec 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a8/ac6/src/tx_thread_irq_nesting_start.S @@ -46,7 +46,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_irq_nesting_start Cortex-A8/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_a8/ac6/src/tx_thread_schedule.S b/ports/cortex_a8/ac6/src/tx_thread_schedule.S index c6c4a8be..44760f1a 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a8/ac6/src/tx_thread_schedule.S @@ -61,7 +61,7 @@ $_tx_thread_schedule: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule Cortex-A8/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -94,7 +94,7 @@ $_tx_thread_schedule: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_a8/ac6/src/tx_thread_stack_build.S b/ports/cortex_a8/ac6/src/tx_thread_stack_build.S index 51d783ff..506a0e3d 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_a8/ac6/src/tx_thread_stack_build.S @@ -64,7 +64,7 @@ $_tx_thread_stack_build: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_stack_build Cortex-A8/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -96,7 +96,7 @@ $_tx_thread_stack_build: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_a8/ac6/src/tx_thread_system_return.S b/ports/cortex_a8/ac6/src/tx_thread_system_return.S index 07044996..8361ea44 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a8/ac6/src/tx_thread_system_return.S @@ -63,7 +63,7 @@ $_tx_thread_system_return: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_system_return Cortex-A8/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -95,7 +95,7 @@ $_tx_thread_system_return: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_a8/ac6/src/tx_thread_vectored_context_save.S b/ports/cortex_a8/ac6/src/tx_thread_vectored_context_save.S index 97ab8427..910ba3c1 100644 --- a/ports/cortex_a8/ac6/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_a8/ac6/src/tx_thread_vectored_context_save.S @@ -46,7 +46,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_vectored_context_save Cortex-A8/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_vectored_context_save(VOID) diff --git a/ports/cortex_a8/ac6/src/tx_timer_interrupt.S b/ports/cortex_a8/ac6/src/tx_timer_interrupt.S index 84e057a0..9529953d 100644 --- a/ports/cortex_a8/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_a8/ac6/src/tx_timer_interrupt.S @@ -71,7 +71,7 @@ $_tx_timer_interrupt: @/* FUNCTION RELEASE */ @/* */ @/* _tx_timer_interrupt Cortex-A8/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -105,7 +105,7 @@ $_tx_timer_interrupt: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_a8/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_a8/gnu/example_build/tx_initialize_low_level.S index 2cd32c9e..82bf7825 100644 --- a/ports/cortex_a8/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_a8/gnu/example_build/tx_initialize_low_level.S @@ -78,7 +78,7 @@ $_tx_initialize_low_level: @/* FUNCTION RELEASE */ @/* */ @/* _tx_initialize_low_level Cortex-A8/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -111,7 +111,7 @@ $_tx_initialize_low_level: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_a8/gnu/inc/tx_port.h b/ports/cortex_a8/gnu/inc/tx_port.h index bb5781f1..dac79ee2 100644 --- a/ports/cortex_a8/gnu/inc/tx_port.h +++ b/ports/cortex_a8/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A8/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -313,7 +313,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A8/GNU Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A8/GNU Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a8/gnu/readme_threadx.txt b/ports/cortex_a8/gnu/readme_threadx.txt index bc4d709a..e06f0dc0 100644 --- a/ports/cortex_a8/gnu/readme_threadx.txt +++ b/ports/cortex_a8/gnu/readme_threadx.txt @@ -503,7 +503,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A8 using GNU tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-A8 using GNU tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_a8/gnu/src/tx_thread_context_restore.S b/ports/cortex_a8/gnu/src/tx_thread_context_restore.S index 91b1c150..0c3062af 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a8/gnu/src/tx_thread_context_restore.S @@ -60,7 +60,7 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_restore Cortex-A8/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -92,7 +92,7 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_a8/gnu/src/tx_thread_context_save.S b/ports/cortex_a8/gnu/src/tx_thread_context_save.S index 8c55a18b..e4e4977b 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a8/gnu/src/tx_thread_context_save.S @@ -48,7 +48,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_save Cortex-A8/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -79,7 +79,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_a8/gnu/src/tx_thread_fiq_context_restore.S b/ports/cortex_a8/gnu/src/tx_thread_fiq_context_restore.S index ee677edf..b9dcd6b5 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_a8/gnu/src/tx_thread_fiq_context_restore.S @@ -59,7 +59,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_context_restore Cortex-A8/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -91,7 +91,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_context_restore(VOID) diff --git a/ports/cortex_a8/gnu/src/tx_thread_fiq_context_save.S b/ports/cortex_a8/gnu/src/tx_thread_fiq_context_save.S index 3a3eda70..afa0baa8 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_a8/gnu/src/tx_thread_fiq_context_save.S @@ -47,7 +47,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_context_save Cortex-A8/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -78,7 +78,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @ VOID _tx_thread_fiq_context_save(VOID) diff --git a/ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_end.S index 71ac82b3..5667d51c 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_end.S @@ -50,7 +50,7 @@ FIQ_MODE_BITS = 0x11 @ FIQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_nesting_end Cortex-A8/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -89,7 +89,7 @@ FIQ_MODE_BITS = 0x11 @ FIQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_end(VOID) diff --git a/ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_start.S index f4ae9a78..ddda6089 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_start.S @@ -46,7 +46,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_nesting_start Cortex-A8/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/cortex_a8/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a8/gnu/src/tx_thread_interrupt_control.S index ce0949ec..7f3c0f78 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a8/gnu/src/tx_thread_interrupt_control.S @@ -56,7 +56,7 @@ $_tx_thread_interrupt_control: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_control Cortex-A8/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -86,7 +86,7 @@ $_tx_thread_interrupt_control: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a8/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a8/gnu/src/tx_thread_interrupt_disable.S index ea6f1193..3bce811f 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a8/gnu/src/tx_thread_interrupt_disable.S @@ -53,7 +53,7 @@ $_tx_thread_interrupt_disable: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_disable Cortex-A8/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ $_tx_thread_interrupt_disable: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_disable(void) diff --git a/ports/cortex_a8/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a8/gnu/src/tx_thread_interrupt_restore.S index 63ca62d9..4efdfb75 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a8/gnu/src/tx_thread_interrupt_restore.S @@ -53,7 +53,7 @@ $_tx_thread_interrupt_restore: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_restore Cortex-A8/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -83,7 +83,7 @@ $_tx_thread_interrupt_restore: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a8/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_a8/gnu/src/tx_thread_irq_nesting_end.S index b892370b..473348d7 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a8/gnu/src/tx_thread_irq_nesting_end.S @@ -50,7 +50,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_irq_nesting_end Cortex-A8/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -89,7 +89,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports/cortex_a8/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_a8/gnu/src/tx_thread_irq_nesting_start.S index f8cd2efd..766e83d3 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a8/gnu/src/tx_thread_irq_nesting_start.S @@ -46,7 +46,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_irq_nesting_start Cortex-A8/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_a8/gnu/src/tx_thread_schedule.S b/ports/cortex_a8/gnu/src/tx_thread_schedule.S index a6e0293f..d7dc5e11 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a8/gnu/src/tx_thread_schedule.S @@ -62,7 +62,7 @@ $_tx_thread_schedule: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule Cortex-A8/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -95,7 +95,7 @@ $_tx_thread_schedule: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_a8/gnu/src/tx_thread_stack_build.S b/ports/cortex_a8/gnu/src/tx_thread_stack_build.S index 4de92045..3946d652 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a8/gnu/src/tx_thread_stack_build.S @@ -64,7 +64,7 @@ $_tx_thread_stack_build: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_stack_build Cortex-A8/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -96,7 +96,7 @@ $_tx_thread_stack_build: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_a8/gnu/src/tx_thread_system_return.S b/ports/cortex_a8/gnu/src/tx_thread_system_return.S index 28c756e5..15453144 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a8/gnu/src/tx_thread_system_return.S @@ -64,7 +64,7 @@ $_tx_thread_system_return: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_system_return Cortex-A8/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -96,7 +96,7 @@ $_tx_thread_system_return: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_a8/gnu/src/tx_thread_vectored_context_save.S b/ports/cortex_a8/gnu/src/tx_thread_vectored_context_save.S index 96f8d0eb..2716bba3 100644 --- a/ports/cortex_a8/gnu/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_a8/gnu/src/tx_thread_vectored_context_save.S @@ -47,7 +47,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_vectored_context_save Cortex-A8/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -78,7 +78,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_vectored_context_save(VOID) diff --git a/ports/cortex_a8/gnu/src/tx_timer_interrupt.S b/ports/cortex_a8/gnu/src/tx_timer_interrupt.S index 501b2771..2f8ffccf 100644 --- a/ports/cortex_a8/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a8/gnu/src/tx_timer_interrupt.S @@ -71,7 +71,7 @@ $_tx_timer_interrupt: @/* FUNCTION RELEASE */ @/* */ @/* _tx_timer_interrupt Cortex-A8/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -105,7 +105,7 @@ $_tx_timer_interrupt: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_a8/green/example_build/azure_rtos_workspace.gpj b/ports/cortex_a8/green/example_build/azure_rtos_workspace.gpj new file mode 100644 index 00000000..df5b91c0 --- /dev/null +++ b/ports/cortex_a8/green/example_build/azure_rtos_workspace.gpj @@ -0,0 +1,12 @@ +#!gbuild +primaryTarget=arm_standalone.tgt +[Project] + -bsp generic + -G + -cpu=cortexa8 + -littleendian +sample_threadx.gpj [Program] +sample_threadx_el.gpj [Program] +tx.gpj [Library] +txe.gpj [Library] +..\readme_threadx.txt diff --git a/ports/cortex_a8/green/example_build/reset.arm b/ports/cortex_a8/green/example_build/reset.arm new file mode 100644 index 00000000..26881396 --- /dev/null +++ b/ports/cortex_a8/green/example_build/reset.arm @@ -0,0 +1,45 @@ +# +# +#/* Define the Cortex-A8 vector area. This should be located or copied to 0. */ +# + + .section ".reset", .text + .globl __vectors +__vectors: + B __entry # Reset goes to the entry function + LDR pc,UNDEFINED # Undefined handler + LDR pc,SWI # Software interrupt handler + LDR pc,PREFETCH # Prefetch exception handler + LDR pc,ABORT # Abort exception handler + LDR pc,RESERVED # Reserved exception handler + LDR pc,IRQ # IRQ interrupt handler + LDR pc,FIQ # FIQ interrupt handler +# +# +__entry: + LDR sp,STACK # Setup stack pointer + LDR pc,START # Jump to Green Hills startup +# +# +STACK: + .data.w __ghsend_stack +START: + .data.w _start # Reset goes to startup function +UNDEFINED: + .data.w __tx_undefined # Undefined handler +SWI: + .data.w __tx_swi_interrupt # Software interrupt handler +PREFETCH: + .data.w __tx_prefetch_handler # Prefetch exception handler +ABORT: + .data.w __tx_abort_handler # Abort exception handler +RESERVED: + .data.w __tx_reserved_handler # Reserved exception handler +IRQ: + .data.w __tx_irq_handler # IRQ interrupt handler +FIQ: + .data.w __tx_fiq_handler # FIQ interrupt handler +# +# + .type __vectors,$function + .size __vectors,.-__vectors diff --git a/ports/cortex_a8/green/example_build/sample_threadx.c b/ports/cortex_a8/green/example_build/sample_threadx.c new file mode 100644 index 00000000..418ec634 --- /dev/null +++ b/ports/cortex_a8/green/example_build/sample_threadx.c @@ -0,0 +1,369 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_a8/green/example_build/sample_threadx.con b/ports/cortex_a8/green/example_build/sample_threadx.con new file mode 100644 index 00000000..7a34994c --- /dev/null +++ b/ports/cortex_a8/green/example_build/sample_threadx.con @@ -0,0 +1,11 @@ +target_connection.00000000.title="Simulator connection for ThreadX" +target_connection.00000000.type="Custom" +target_connection.00000000.short_type="Custom" +target_connection.00000000.args="simarm -cpu=cortexa8 -fpu -rom" +target_connection.00000000.command="simarm -cpu=cortexa8 -fpu -rom" +target_connection.00000000.logfile="" +target_connection.00000000.mode="download" +target_connection.00000000.setup_script="" +target_connection.00000000.sane="yes" +target_connection.00000000.log="no" +target_connection.00000000.timestamp="1192825758" diff --git a/ports/cortex_a8/green/example_build/sample_threadx.gpj b/ports/cortex_a8/green/example_build/sample_threadx.gpj new file mode 100644 index 00000000..b9b2c04c --- /dev/null +++ b/ports/cortex_a8/green/example_build/sample_threadx.gpj @@ -0,0 +1,11 @@ +#!gbuild +[Program] + -I../../../../common/inc + -I../../../../ports_common_green/inc + -I../inc +reset.arm +tx_initialize_low_level.arm +sample_threadx.c +tx.a +sample_threadx.ld +sample_threadx.con diff --git a/ports/cortex_a8/green/example_build/sample_threadx.ld b/ports/cortex_a8/green/example_build/sample_threadx.ld new file mode 100644 index 00000000..8d1ab4df --- /dev/null +++ b/ports/cortex_a8/green/example_build/sample_threadx.ld @@ -0,0 +1,44 @@ +# The following explains what the default Green Hills sections are for: +# +# picbase - base of the text sections, relocatable in -pic mode +# text - text section +# syscall - syscall section, for host I/O under Multi +# fixaddr/fixtype - for PIC/PID fixups +# rodata - read only data +# romdata - the ROM image of .data +# romsdata - the ROM image of .sdata +# secinfo - section information section, used by the start-up code +# pidbase - base of the data sections, relocatable in -pid mode +# sdabase - base of the small data area section pointer +# sbss - small BSS (zeroed data) section +# sdata - small data section +# data - non-zeroed writeable data section +# bss - zeroed data section +# heap - the heap, grows upward +# stack - the stack, grows downward + +-sec +{ + .reset 0x000000 : + .picbase 0x1000 : + .text : + .comment : + .intercall : + .interfunc : + .syscall : + .fixaddr : + .fixtype : + .rodata : + .romdata ROM(.data) : + .romsdata ROM(.sdata) : + .secinfo : + .pidbase align(16) : + .sdabase : + .sbss : + .sdata : + .data : + .bss : + .heap align(16) pad(0x10000) : + .stack align(16) pad(0x1000) : + .free_mem align(16) pad(0x10000) : +} diff --git a/ports/cortex_a8/green/example_build/sample_threadx_el.gpj b/ports/cortex_a8/green/example_build/sample_threadx_el.gpj new file mode 100644 index 00000000..a51049ca --- /dev/null +++ b/ports/cortex_a8/green/example_build/sample_threadx_el.gpj @@ -0,0 +1,13 @@ +#!gbuild +[Program] + -DTX_ENABLE_EVENT_LOGGING + -I../../../../common/inc + -I../../../../ports_common_green/inc + -I../inc +reset.arm +tx_initialize_low_level.arm +sample_threadx.c +txe.a +sample_threadx_el.ld +sample_threadx.con +readme_threadx.txt diff --git a/ports/cortex_a8/green/example_build/sample_threadx_el.ld b/ports/cortex_a8/green/example_build/sample_threadx_el.ld new file mode 100644 index 00000000..33c0f934 --- /dev/null +++ b/ports/cortex_a8/green/example_build/sample_threadx_el.ld @@ -0,0 +1,45 @@ +# The following explains what the default Green Hills sections are for: +# +# picbase - base of the text sections, relocatable in -pic mode +# text - text section +# syscall - syscall section, for host I/O under Multi +# fixaddr/fixtype - for PIC/PID fixups +# rodata - read only data +# romdata - the ROM image of .data +# romsdata - the ROM image of .sdata +# secinfo - section information section, used by the start-up code +# pidbase - base of the data sections, relocatable in -pid mode +# sdabase - base of the small data area section pointer +# sbss - small BSS (zeroed data) section +# sdata - small data section +# data - non-zeroed writeable data section +# bss - zeroed data section +# heap - the heap, grows upward +# stack - the stack, grows downward + +-sec +{ + .reset 0x000000 : + .picbase 0x1000 : + .text : + .comment : + .intercall : + .interfunc : + .syscall : + .fixaddr : + .fixtype : + .rodata : + .romdata ROM(.data) : + .romsdata ROM(.sdata) : + .secinfo : + .pidbase align(16) : + .sdabase : + .sbss : + .sdata : + .data : + .bss : + .heap align(16) pad(0x1000) : + .stack align(16) pad(0x1000) : + .eventlog align(16) pad(0x10000) : + .free_mem align(16) pad(0x10000) : +} diff --git a/ports/cortex_a8/green/example_build/tx.gpj b/ports/cortex_a8/green/example_build/tx.gpj new file mode 100644 index 00000000..afbd6bef --- /dev/null +++ b/ports/cortex_a8/green/example_build/tx.gpj @@ -0,0 +1,283 @@ +#!gbuild +[Library] + -I../../../../common/inc + -I../../../../ports_common_green/inc + -I../inc +..\..\..\..\common\inc\tx_api.h +..\..\..\..\common\inc\tx_block_pool.h +..\..\..\..\common\inc\tx_byte_pool.h +..\..\..\..\common\inc\tx_event_flags.h +..\..\..\..\common\inc\tx_initialize.h +..\..\..\..\common\inc\tx_mutex.h +..\..\..\..\common\inc\tx_queue.h +..\..\..\..\common\inc\tx_semaphore.h +..\..\..\..\common\inc\tx_thread.h +..\..\..\..\common\inc\tx_timer.h +..\..\..\..\common\inc\tx_trace.h +..\..\..\..\common\inc\tx_user_sample.h +..\inc\tx_port.h +..\..\..\..\ports_common_green\inc\tx_el.h +..\..\..\..\ports_common_green\inc\tx_ghs.h +..\src\tx_thread_context_restore.arm +..\src\tx_thread_context_save.arm +..\src\tx_thread_fiq_context_restore.arm +..\src\tx_thread_fiq_context_save.arm +..\src\tx_thread_fiq_nesting_end.arm +..\src\tx_thread_fiq_nesting_start.arm +..\src\tx_thread_interrupt_control.arm +..\src\tx_thread_interrupt_disable.arm +..\src\tx_thread_interrupt_restore.arm +..\src\tx_thread_irq_nesting_end.arm +..\src\tx_thread_irq_nesting_start.arm +..\src\tx_thread_schedule.arm +..\src\tx_thread_stack_build.arm +..\src\tx_thread_system_return.arm +..\src\tx_thread_vectored_context_save.arm +..\src\tx_timer_interrupt.arm +..\..\..\..\common\src\tx_block_allocate.c +..\..\..\..\common\src\tx_block_pool_cleanup.c +..\..\..\..\common\src\tx_block_pool_create.c +..\..\..\..\common\src\tx_block_pool_delete.c +..\..\..\..\common\src\tx_block_pool_info_get.c +..\..\..\..\common\src\tx_block_pool_initialize.c +..\..\..\..\common\src\tx_block_pool_performance_info_get.c +..\..\..\..\common\src\tx_block_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_block_pool_prioritize.c +..\..\..\..\common\src\tx_block_release.c +..\..\..\..\common\src\tx_byte_allocate.c +..\..\..\..\common\src\tx_byte_pool_cleanup.c +..\..\..\..\common\src\tx_byte_pool_create.c +..\..\..\..\common\src\tx_byte_pool_delete.c +..\..\..\..\common\src\tx_byte_pool_info_get.c +..\..\..\..\common\src\tx_byte_pool_initialize.c +..\..\..\..\common\src\tx_byte_pool_performance_info_get.c +..\..\..\..\common\src\tx_byte_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_byte_pool_prioritize.c +..\..\..\..\common\src\tx_byte_pool_search.c +..\..\..\..\common\src\tx_byte_release.c +..\..\..\..\common\src\tx_event_flags_cleanup.c +..\..\..\..\common\src\tx_event_flags_create.c +..\..\..\..\common\src\tx_event_flags_delete.c +..\..\..\..\common\src\tx_event_flags_get.c +..\..\..\..\common\src\tx_event_flags_info_get.c +..\..\..\..\common\src\tx_event_flags_initialize.c +..\..\..\..\common\src\tx_event_flags_performance_info_get.c +..\..\..\..\common\src\tx_event_flags_performance_system_info_get.c +..\..\..\..\common\src\tx_event_flags_set.c +..\..\..\..\common\src\tx_event_flags_set_notify.c +..\..\..\..\common\src\tx_initialize_high_level.c +..\..\..\..\common\src\tx_initialize_kernel_enter.c +..\..\..\..\common\src\tx_initialize_kernel_setup.c +..\..\..\..\common\src\tx_mutex_cleanup.c +..\..\..\..\common\src\tx_mutex_create.c +..\..\..\..\common\src\tx_mutex_delete.c +..\..\..\..\common\src\tx_mutex_get.c +..\..\..\..\common\src\tx_mutex_info_get.c +..\..\..\..\common\src\tx_mutex_initialize.c +..\..\..\..\common\src\tx_mutex_performance_info_get.c +..\..\..\..\common\src\tx_mutex_performance_system_info_get.c +..\..\..\..\common\src\tx_mutex_prioritize.c +..\..\..\..\common\src\tx_mutex_priority_change.c +..\..\..\..\common\src\tx_mutex_put.c +..\..\..\..\common\src\tx_queue_cleanup.c +..\..\..\..\common\src\tx_queue_create.c +..\..\..\..\common\src\tx_queue_delete.c +..\..\..\..\common\src\tx_queue_flush.c +..\..\..\..\common\src\tx_queue_front_send.c +..\..\..\..\common\src\tx_queue_info_get.c +..\..\..\..\common\src\tx_queue_initialize.c +..\..\..\..\common\src\tx_queue_performance_info_get.c +..\..\..\..\common\src\tx_queue_performance_system_info_get.c +..\..\..\..\common\src\tx_queue_prioritize.c +..\..\..\..\common\src\tx_queue_receive.c +..\..\..\..\common\src\tx_queue_send.c +..\..\..\..\common\src\tx_queue_send_notify.c +..\..\..\..\common\src\tx_semaphore_ceiling_put.c +..\..\..\..\common\src\tx_semaphore_cleanup.c +..\..\..\..\common\src\tx_semaphore_create.c +..\..\..\..\common\src\tx_semaphore_delete.c +..\..\..\..\common\src\tx_semaphore_get.c +..\..\..\..\common\src\tx_semaphore_info_get.c +..\..\..\..\common\src\tx_semaphore_initialize.c +..\..\..\..\common\src\tx_semaphore_performance_info_get.c +..\..\..\..\common\src\tx_semaphore_performance_system_info_get.c +..\..\..\..\common\src\tx_semaphore_prioritize.c +..\..\..\..\common\src\tx_semaphore_put.c +..\..\..\..\common\src\tx_semaphore_put_notify.c +..\..\..\..\common\src\tx_thread_create.c +..\..\..\..\common\src\tx_thread_delete.c +..\..\..\..\common\src\tx_thread_entry_exit_notify.c +..\..\..\..\common\src\tx_thread_identify.c +..\..\..\..\common\src\tx_thread_info_get.c +..\..\..\..\common\src\tx_thread_initialize.c +..\..\..\..\common\src\tx_thread_performance_info_get.c +..\..\..\..\common\src\tx_thread_performance_system_info_get.c +..\..\..\..\common\src\tx_thread_preemption_change.c +..\..\..\..\common\src\tx_thread_priority_change.c +..\..\..\..\common\src\tx_thread_relinquish.c +..\..\..\..\common\src\tx_thread_reset.c +..\..\..\..\common\src\tx_thread_resume.c +..\..\..\..\common\src\tx_thread_shell_entry.c +..\..\..\..\common\src\tx_thread_sleep.c +..\..\..\..\common\src\tx_thread_stack_analyze.c +..\..\..\..\common\src\tx_thread_stack_error_handler.c +..\..\..\..\common\src\tx_thread_stack_error_notify.c +..\..\..\..\common\src\tx_thread_suspend.c +..\..\..\..\common\src\tx_thread_system_preempt_check.c +..\..\..\..\common\src\tx_thread_system_resume.c +..\..\..\..\common\src\tx_thread_system_suspend.c +..\..\..\..\common\src\tx_thread_terminate.c +..\..\..\..\common\src\tx_thread_time_slice.c +..\..\..\..\common\src\tx_thread_time_slice_change.c +..\..\..\..\common\src\tx_thread_timeout.c +..\..\..\..\common\src\tx_thread_wait_abort.c +..\..\..\..\common\src\tx_time_get.c +..\..\..\..\common\src\tx_time_set.c +..\..\..\..\common\src\tx_timer_activate.c +..\..\..\..\common\src\tx_timer_change.c +..\..\..\..\common\src\tx_timer_create.c +..\..\..\..\common\src\tx_timer_deactivate.c +..\..\..\..\common\src\tx_timer_delete.c +..\..\..\..\common\src\tx_timer_expiration_process.c +..\..\..\..\common\src\tx_timer_info_get.c +..\..\..\..\common\src\tx_timer_initialize.c +..\..\..\..\common\src\tx_timer_performance_info_get.c +..\..\..\..\common\src\tx_timer_performance_system_info_get.c +..\..\..\..\common\src\tx_timer_system_activate.c +..\..\..\..\common\src\tx_timer_system_deactivate.c +..\..\..\..\common\src\tx_timer_thread_entry.c +..\..\..\..\common\src\tx_trace_buffer_full_notify.c +..\..\..\..\common\src\tx_trace_disable.c +..\..\..\..\common\src\tx_trace_enable.c +..\..\..\..\common\src\tx_trace_event_filter.c +..\..\..\..\common\src\tx_trace_event_unfilter.c +..\..\..\..\common\src\tx_trace_initialize.c +..\..\..\..\common\src\tx_trace_interrupt_control.c +..\..\..\..\common\src\tx_trace_isr_enter_insert.c +..\..\..\..\common\src\tx_trace_isr_exit_insert.c +..\..\..\..\common\src\tx_trace_object_register.c +..\..\..\..\common\src\tx_trace_object_unregister.c +..\..\..\..\common\src\tx_trace_user_event_insert.c +..\..\..\..\common\src\txe_block_allocate.c +..\..\..\..\common\src\txe_block_pool_create.c +..\..\..\..\common\src\txe_block_pool_delete.c +..\..\..\..\common\src\txe_block_pool_info_get.c +..\..\..\..\common\src\txe_block_pool_prioritize.c +..\..\..\..\common\src\txe_block_release.c +..\..\..\..\common\src\txe_byte_allocate.c +..\..\..\..\common\src\txe_byte_pool_create.c +..\..\..\..\common\src\txe_byte_pool_delete.c +..\..\..\..\common\src\txe_byte_pool_info_get.c +..\..\..\..\common\src\txe_byte_pool_prioritize.c +..\..\..\..\common\src\txe_byte_release.c +..\..\..\..\common\src\txe_event_flags_create.c +..\..\..\..\common\src\txe_event_flags_delete.c +..\..\..\..\common\src\txe_event_flags_get.c +..\..\..\..\common\src\txe_event_flags_info_get.c +..\..\..\..\common\src\txe_event_flags_set.c +..\..\..\..\common\src\txe_event_flags_set_notify.c +..\..\..\..\common\src\txe_mutex_create.c +..\..\..\..\common\src\txe_mutex_delete.c +..\..\..\..\common\src\txe_mutex_get.c +..\..\..\..\common\src\txe_mutex_info_get.c +..\..\..\..\common\src\txe_mutex_prioritize.c +..\..\..\..\common\src\txe_mutex_put.c +..\..\..\..\common\src\txe_queue_create.c +..\..\..\..\common\src\txe_queue_delete.c +..\..\..\..\common\src\txe_queue_flush.c +..\..\..\..\common\src\txe_queue_front_send.c +..\..\..\..\common\src\txe_queue_info_get.c +..\..\..\..\common\src\txe_queue_prioritize.c +..\..\..\..\common\src\txe_queue_receive.c +..\..\..\..\common\src\txe_queue_send.c +..\..\..\..\common\src\txe_queue_send_notify.c +..\..\..\..\common\src\txe_semaphore_ceiling_put.c +..\..\..\..\common\src\txe_semaphore_create.c +..\..\..\..\common\src\txe_semaphore_delete.c +..\..\..\..\common\src\txe_semaphore_get.c +..\..\..\..\common\src\txe_semaphore_info_get.c +..\..\..\..\common\src\txe_semaphore_prioritize.c +..\..\..\..\common\src\txe_semaphore_put.c +..\..\..\..\common\src\txe_semaphore_put_notify.c +..\..\..\..\common\src\txe_thread_create.c +..\..\..\..\common\src\txe_thread_delete.c +..\..\..\..\common\src\txe_thread_entry_exit_notify.c +..\..\..\..\common\src\txe_thread_info_get.c +..\..\..\..\common\src\txe_thread_preemption_change.c +..\..\..\..\common\src\txe_thread_priority_change.c +..\..\..\..\common\src\txe_thread_relinquish.c +..\..\..\..\common\src\txe_thread_reset.c +..\..\..\..\common\src\txe_thread_resume.c +..\..\..\..\common\src\txe_thread_suspend.c +..\..\..\..\common\src\txe_thread_terminate.c +..\..\..\..\common\src\txe_thread_time_slice_change.c +..\..\..\..\common\src\txe_thread_wait_abort.c +..\..\..\..\common\src\txe_timer_activate.c +..\..\..\..\common\src\txe_timer_change.c +..\..\..\..\common\src\txe_timer_create.c +..\..\..\..\common\src\txe_timer_deactivate.c +..\..\..\..\common\src\txe_timer_delete.c +..\..\..\..\common\src\txe_timer_info_get.c +..\..\..\..\ports_common_green\src\tx_el.c +..\..\..\..\ports_common_green\src\tx_ghs.c +..\..\..\..\ports_common_green\src\tx_ghse.c +..\..\..\..\ports_common_green\src\txr_block_allocate.c +..\..\..\..\ports_common_green\src\txr_block_pool_create.c +..\..\..\..\ports_common_green\src\txr_block_pool_delete.c +..\..\..\..\ports_common_green\src\txr_block_pool_info_get.c +..\..\..\..\ports_common_green\src\txr_block_pool_prioritize.c +..\..\..\..\ports_common_green\src\txr_block_release.c +..\..\..\..\ports_common_green\src\txr_byte_allocate.c +..\..\..\..\ports_common_green\src\txr_byte_pool_create.c +..\..\..\..\ports_common_green\src\txr_byte_pool_delete.c +..\..\..\..\ports_common_green\src\txr_byte_pool_info_get.c +..\..\..\..\ports_common_green\src\txr_byte_pool_prioritize.c +..\..\..\..\ports_common_green\src\txr_byte_release.c +..\..\..\..\ports_common_green\src\txr_event_flags_create.c +..\..\..\..\ports_common_green\src\txr_event_flags_delete.c +..\..\..\..\ports_common_green\src\txr_event_flags_get.c +..\..\..\..\ports_common_green\src\txr_event_flags_info_get.c +..\..\..\..\ports_common_green\src\txr_event_flags_set.c +..\..\..\..\ports_common_green\src\txr_event_flags_set_notify.c +..\..\..\..\ports_common_green\src\txr_ghs.c +..\..\..\..\ports_common_green\src\txr_mutex_create.c +..\..\..\..\ports_common_green\src\txr_mutex_delete.c +..\..\..\..\ports_common_green\src\txr_mutex_get.c +..\..\..\..\ports_common_green\src\txr_mutex_info_get.c +..\..\..\..\ports_common_green\src\txr_mutex_prioritize.c +..\..\..\..\ports_common_green\src\txr_mutex_put.c +..\..\..\..\ports_common_green\src\txr_queue_create.c +..\..\..\..\ports_common_green\src\txr_queue_delete.c +..\..\..\..\ports_common_green\src\txr_queue_flush.c +..\..\..\..\ports_common_green\src\txr_queue_front_send.c +..\..\..\..\ports_common_green\src\txr_queue_info_get.c +..\..\..\..\ports_common_green\src\txr_queue_prioritize.c +..\..\..\..\ports_common_green\src\txr_queue_receive.c +..\..\..\..\ports_common_green\src\txr_queue_send.c +..\..\..\..\ports_common_green\src\txr_queue_send_notify.c +..\..\..\..\ports_common_green\src\txr_semaphore_ceiling_put.c +..\..\..\..\ports_common_green\src\txr_semaphore_create.c +..\..\..\..\ports_common_green\src\txr_semaphore_delete.c +..\..\..\..\ports_common_green\src\txr_semaphore_get.c +..\..\..\..\ports_common_green\src\txr_semaphore_info_get.c +..\..\..\..\ports_common_green\src\txr_semaphore_prioritize.c +..\..\..\..\ports_common_green\src\txr_semaphore_put.c +..\..\..\..\ports_common_green\src\txr_semaphore_put_notify.c +..\..\..\..\ports_common_green\src\txr_thread_create.c +..\..\..\..\ports_common_green\src\txr_thread_delete.c +..\..\..\..\ports_common_green\src\txr_thread_entry_exit_notify.c +..\..\..\..\ports_common_green\src\txr_thread_info_get.c +..\..\..\..\ports_common_green\src\txr_thread_preemption_change.c +..\..\..\..\ports_common_green\src\txr_thread_priority_change.c +..\..\..\..\ports_common_green\src\txr_thread_reset.c +..\..\..\..\ports_common_green\src\txr_thread_resume.c +..\..\..\..\ports_common_green\src\txr_thread_suspend.c +..\..\..\..\ports_common_green\src\txr_thread_terminate.c +..\..\..\..\ports_common_green\src\txr_thread_time_slice_change.c +..\..\..\..\ports_common_green\src\txr_thread_wait_abort.c +..\..\..\..\ports_common_green\src\txr_timer_activate.c +..\..\..\..\ports_common_green\src\txr_timer_change.c +..\..\..\..\ports_common_green\src\txr_timer_create.c +..\..\..\..\ports_common_green\src\txr_timer_deactivate.c +..\..\..\..\ports_common_green\src\txr_timer_delete.c +..\..\..\..\ports_common_green\src\txr_timer_info_get.c diff --git a/ports/cortex_a8/green/example_build/tx_initialize_low_level.arm b/ports/cortex_a8/green/example_build/tx_initialize_low_level.arm new file mode 100644 index 00000000..ab71ab46 --- /dev/null +++ b/ports/cortex_a8/green/example_build/tx_initialize_low_level.arm @@ -0,0 +1,319 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_initialize.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + SVC_MODE = 0xD3 # Disable IRQ/FIQ SVC mode + IRQ_MODE = 0xD2 # Disable IRQ/FIQ IRQ mode + FIQ_MODE = 0xD1 # Disable IRQ/FIQ FIQ mode + SYS_MODE = 0xDF # Disable IRQ/FIQ SYS mode + MODE_MASK = 0x1F # Mode mask + FIQ_STACK_SIZE = 512 # FIQ stack size + IRQ_STACK_SIZE = 1024 # IRQ stack size + SYS_STACK_SIZE = 1024 # SYS stack size + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-A8/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_initialize_low_level(VOID) +{ */ + .globl _tx_initialize_low_level +_tx_initialize_low_level: + + /****** NOTE ****** We must be in SVC MODE at this point. Some monitors + enter this routine in USER mode and require a software interrupt to + change into SVC mode. */ + + /* Save the system stack pointer. */ + /* _tx_thread_system_stack_ptr = (VOID_PTR) (sp); */ + + LDR r1,=_tx_thread_system_stack_ptr # Pickup address of system stack ptr + STR sp, [r1] # Save system stack + + /* Pickup the first available memory address. */ + + LDR r0,=__ghsbegin_free_mem # Pickup free memory address + + /* Setup initial stack pointers for IRQ and FIQ modes. */ + + MRS r12, CPSR # Pickup current CPSR + MOV r1, r0 # Get first available memory +#ifdef TX_ENABLE_IRQ_NESTING + /* Setup the system mode stack for nested interrupt support */ + LDR r2, =SYS_STACK_SIZE # Pickup stack size + BIC r3, r12, MODE_MASK # Clear mode bits + ORR r3, r3, SYS_MODE # Build SYS mode CPSR + MSR CPSR_c, r3 # Enter SYS mode + ADD r1, r1, r2 # Calculate start of SYS stack + SUB r1, r1, 1 # Backup one byte + BIC r1, r1, 7 # Insure 8-byte alignment + MOV sp, r1 # Setup SYS stack pointer +#endif + LDR r2, =FIQ_STACK_SIZE # Pickup stack size + BIC r3, r12, MODE_MASK # Clear mode bits + ORR r3, r3, FIQ_MODE # Build FIQ mode CPSR + MSR CPSR_c, r3 # Enter FIQ mode + ADD r1, r1, r2 # Calculate start of FIQ stack + SUB r1, r1, 1 # Backup one byte + BIC r1, r1, 7 # Insure 8-byte alignment + MOV sp, r1 # Setup FIQ stack pointer + MOV r10, 0 # Clear sl + MOV r11, 0 # Clear fp + LDR r2, =IRQ_STACK_SIZE # Pickup IRQ (system stack size) + BIC r3, r12, MODE_MASK # Clear mode bits + ORR r3, r3, IRQ_MODE # Build IRQ mode CPSR + MSR CPSR_c, r3 # Enter IRQ mode + ADD r1, r1, r2 # Calculate start of IRQ stack + SUB r1, r1, 1 # Backup one byte + BIC r1, r1, 7 # Insure 8-byte alignment + MOV sp, r1 # Setup IRQ stack pointer + MSR CPSR_c, r12 # Restore previous mode + ADD r0, r1, 4 # Adjust the new free memory + + + /* Save the first available memory address. */ + /* _tx_initialize_unused_memory = (VOID_PTR) __ghsbegin_free_mem + [SYS_STACK] + FIQ_STACK + IRQ_STACK; */ + + LDR r2,=_tx_initialize_unused_memory # Pickup unused memory ptr address + STR r0, [r2] # Save first free memory address + + + /* Setup Timer for periodic interrupts. To generate timer interrupts with + the Green Hills simulator, enter the following command in the target + window: timer 9999 irq */ + + /* Done, return to caller. */ + + RET # Return to caller + + .type _tx_initialize_low_level,$function + .size _tx_initialize_low_level,.-_tx_initialize_low_level +/* } */ + + +/* Define shells for each of the interrupt vectors. */ + + .globl __tx_undefined +__tx_undefined: + B __tx_undefined # Undefined handler + + .type __tx_undefined,$function + .size __tx_undefined,.-__tx_undefined + + .globl __tx_swi_interrupt +__tx_swi_interrupt: + B __tx_swi_interrupt # Software interrupt handler + + .type __tx_swi_interrupt,$function + .size __tx_swi_interrupt,.-__tx_swi_interrupt + + .globl __tx_prefetch_handler +__tx_prefetch_handler: + B __tx_prefetch_handler # Prefetch exception handler + + .type __tx_prefetch_handler,$function + .size __tx_prefetch_handler,.-__tx_prefetch_handler + + .globl __tx_abort_handler +__tx_abort_handler: + B __tx_abort_handler # Abort exception handler + + .type __tx_abort_handler,$function + .size __tx_abort_handler,.-__tx_abort_handler + + .globl __tx_reserved_handler +__tx_reserved_handler: + B __tx_reserved_handler # Reserved exception handler + + .type __tx_reserved_handler,$function + .size __tx_reserved_handler,.-__tx_reserved_handler + + .globl __tx_irq_handler + .globl __tx_irq_processing_return +__tx_irq_handler: + + /* Jump to context save to save system context. */ + B _tx_thread_context_save + + .type __tx_irq_handler,$function + .size __tx_irq_handler,.-__tx_irq_handler + +__tx_irq_processing_return: + + /* At this point execution is still in the IRQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. */ + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 0 # Build interrupt code + BL _tx_el_interrupt # Call interrupt event logging +#endif + + /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start + from IRQ mode with interrupts disabled. This routine switches to the + system mode and returns with IRQ interrupts enabled. + + NOTE: It is very important to ensure all IRQ interrupts are cleared + prior to enabling nested IRQ interrupts. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_start +#endif + + + /* For debug purpose, execute the timer interrupt processing here. In + a real system, some kind of status indication would have to be checked + before the timer interrupt handler could be called. */ + BL _tx_timer_interrupt # Timer interrupt handler + + /* Application IRQ handlers can be called here! */ + + /* If interrupt nesting was started earlier, the end of interrupt nesting + service must be called before returning to _tx_thread_context_restore. + This routine returns in processing in IRQ mode with interrupts disabled. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_end +#endif + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 0 # Build interrupt code + BL _tx_el_interrupt_end # Call interrupt event logging +#endif + + /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + .type __tx_irq_processing_return,$function + .size __tx_irq_processing_return,.-__tx_irq_processing_return + +#ifdef TX_ENABLE_FIQ_SUPPORT + + .globl __tx_fiq_handler + .globl __tx_fiq_processing_return +__tx_fiq_handler: + /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save + + .type __tx_fiq_handler,$function + .size __tx_fiq_handler,.-__tx_fiq_handler + +__tx_fiq_processing_return: + + /* At this point execution is still in the FIQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. */ + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 1 # Build interrupt code + BL _tx_el_interrupt # Call interrupt event logging +#endif + + /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start + from FIQ mode with interrupts disabled. This routine switches to the + system mode and returns with FIQ interrupts enabled. + + NOTE: It is very important to ensure all FIQ interrupts are cleared + prior to enabling nested FIQ interrupts. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_start +#endif + + /* Application FIQ handlers can be called here! */ + + /* If interrupt nesting was started earlier, the end of interrupt nesting + service must be called before returning to _tx_thread_fiq_context_restore. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_end +#endif + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 1 # Build interrupt code + BL _tx_el_interrupt_end # Call interrupt event logging +#endif + + /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + .type __tx_fiq_processing_return,$function + .size __tx_fiq_processing_return,.-__tx_fiq_processing_return + +#else + .globl __tx_fiq_handler +__tx_fiq_handler: + B __tx_fiq_handler # FIQ interrupt handler + + .type __tx_fiq_handler,$function + .size __tx_fiq_handler,.-__tx_fiq_handler +#endif + + /* Reference build options and version ID to ensure they come in. */ + +BUILD_OPTIONS: + .data.w _tx_build_options +VERSION_ID: + .data.w _tx_version_id diff --git a/ports/cortex_a8/green/example_build/txe.gpj b/ports/cortex_a8/green/example_build/txe.gpj new file mode 100644 index 00000000..662bcd16 --- /dev/null +++ b/ports/cortex_a8/green/example_build/txe.gpj @@ -0,0 +1,284 @@ +#!gbuild +[Library] + -DTX_ENABLE_EVENT_LOGGING + -I../../../../common/inc + -I../../../../ports_common_green/inc + -I../inc +..\..\..\..\common\inc\tx_api.h +..\..\..\..\common\inc\tx_block_pool.h +..\..\..\..\common\inc\tx_byte_pool.h +..\..\..\..\common\inc\tx_event_flags.h +..\..\..\..\common\inc\tx_initialize.h +..\..\..\..\common\inc\tx_mutex.h +..\..\..\..\common\inc\tx_queue.h +..\..\..\..\common\inc\tx_semaphore.h +..\..\..\..\common\inc\tx_thread.h +..\..\..\..\common\inc\tx_timer.h +..\..\..\..\common\inc\tx_trace.h +..\..\..\..\common\inc\tx_user_sample.h +..\inc\tx_port.h +..\..\..\..\ports_common_green\inc\tx_el.h +..\..\..\..\ports_common_green\inc\tx_ghs.h +..\src\tx_thread_context_restore.arm +..\src\tx_thread_context_save.arm +..\src\tx_thread_fiq_context_restore.arm +..\src\tx_thread_fiq_context_save.arm +..\src\tx_thread_fiq_nesting_end.arm +..\src\tx_thread_fiq_nesting_start.arm +..\src\tx_thread_interrupt_control.arm +..\src\tx_thread_interrupt_disable.arm +..\src\tx_thread_interrupt_restore.arm +..\src\tx_thread_irq_nesting_end.arm +..\src\tx_thread_irq_nesting_start.arm +..\src\tx_thread_schedule.arm +..\src\tx_thread_stack_build.arm +..\src\tx_thread_system_return.arm +..\src\tx_thread_vectored_context_save.arm +..\src\tx_timer_interrupt.arm +..\..\..\..\common\src\tx_block_allocate.c +..\..\..\..\common\src\tx_block_pool_cleanup.c +..\..\..\..\common\src\tx_block_pool_create.c +..\..\..\..\common\src\tx_block_pool_delete.c +..\..\..\..\common\src\tx_block_pool_info_get.c +..\..\..\..\common\src\tx_block_pool_initialize.c +..\..\..\..\common\src\tx_block_pool_performance_info_get.c +..\..\..\..\common\src\tx_block_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_block_pool_prioritize.c +..\..\..\..\common\src\tx_block_release.c +..\..\..\..\common\src\tx_byte_allocate.c +..\..\..\..\common\src\tx_byte_pool_cleanup.c +..\..\..\..\common\src\tx_byte_pool_create.c +..\..\..\..\common\src\tx_byte_pool_delete.c +..\..\..\..\common\src\tx_byte_pool_info_get.c +..\..\..\..\common\src\tx_byte_pool_initialize.c +..\..\..\..\common\src\tx_byte_pool_performance_info_get.c +..\..\..\..\common\src\tx_byte_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_byte_pool_prioritize.c +..\..\..\..\common\src\tx_byte_pool_search.c +..\..\..\..\common\src\tx_byte_release.c +..\..\..\..\common\src\tx_event_flags_cleanup.c +..\..\..\..\common\src\tx_event_flags_create.c +..\..\..\..\common\src\tx_event_flags_delete.c +..\..\..\..\common\src\tx_event_flags_get.c +..\..\..\..\common\src\tx_event_flags_info_get.c +..\..\..\..\common\src\tx_event_flags_initialize.c +..\..\..\..\common\src\tx_event_flags_performance_info_get.c +..\..\..\..\common\src\tx_event_flags_performance_system_info_get.c +..\..\..\..\common\src\tx_event_flags_set.c +..\..\..\..\common\src\tx_event_flags_set_notify.c +..\..\..\..\common\src\tx_initialize_high_level.c +..\..\..\..\common\src\tx_initialize_kernel_enter.c +..\..\..\..\common\src\tx_initialize_kernel_setup.c +..\..\..\..\common\src\tx_mutex_cleanup.c +..\..\..\..\common\src\tx_mutex_create.c +..\..\..\..\common\src\tx_mutex_delete.c +..\..\..\..\common\src\tx_mutex_get.c +..\..\..\..\common\src\tx_mutex_info_get.c +..\..\..\..\common\src\tx_mutex_initialize.c +..\..\..\..\common\src\tx_mutex_performance_info_get.c +..\..\..\..\common\src\tx_mutex_performance_system_info_get.c +..\..\..\..\common\src\tx_mutex_prioritize.c +..\..\..\..\common\src\tx_mutex_priority_change.c +..\..\..\..\common\src\tx_mutex_put.c +..\..\..\..\common\src\tx_queue_cleanup.c +..\..\..\..\common\src\tx_queue_create.c +..\..\..\..\common\src\tx_queue_delete.c +..\..\..\..\common\src\tx_queue_flush.c +..\..\..\..\common\src\tx_queue_front_send.c +..\..\..\..\common\src\tx_queue_info_get.c +..\..\..\..\common\src\tx_queue_initialize.c +..\..\..\..\common\src\tx_queue_performance_info_get.c +..\..\..\..\common\src\tx_queue_performance_system_info_get.c +..\..\..\..\common\src\tx_queue_prioritize.c +..\..\..\..\common\src\tx_queue_receive.c +..\..\..\..\common\src\tx_queue_send.c +..\..\..\..\common\src\tx_queue_send_notify.c +..\..\..\..\common\src\tx_semaphore_ceiling_put.c +..\..\..\..\common\src\tx_semaphore_cleanup.c +..\..\..\..\common\src\tx_semaphore_create.c +..\..\..\..\common\src\tx_semaphore_delete.c +..\..\..\..\common\src\tx_semaphore_get.c +..\..\..\..\common\src\tx_semaphore_info_get.c +..\..\..\..\common\src\tx_semaphore_initialize.c +..\..\..\..\common\src\tx_semaphore_performance_info_get.c +..\..\..\..\common\src\tx_semaphore_performance_system_info_get.c +..\..\..\..\common\src\tx_semaphore_prioritize.c +..\..\..\..\common\src\tx_semaphore_put.c +..\..\..\..\common\src\tx_semaphore_put_notify.c +..\..\..\..\common\src\tx_thread_create.c +..\..\..\..\common\src\tx_thread_delete.c +..\..\..\..\common\src\tx_thread_entry_exit_notify.c +..\..\..\..\common\src\tx_thread_identify.c +..\..\..\..\common\src\tx_thread_info_get.c +..\..\..\..\common\src\tx_thread_initialize.c +..\..\..\..\common\src\tx_thread_performance_info_get.c +..\..\..\..\common\src\tx_thread_performance_system_info_get.c +..\..\..\..\common\src\tx_thread_preemption_change.c +..\..\..\..\common\src\tx_thread_priority_change.c +..\..\..\..\common\src\tx_thread_relinquish.c +..\..\..\..\common\src\tx_thread_reset.c +..\..\..\..\common\src\tx_thread_resume.c +..\..\..\..\common\src\tx_thread_shell_entry.c +..\..\..\..\common\src\tx_thread_sleep.c +..\..\..\..\common\src\tx_thread_stack_analyze.c +..\..\..\..\common\src\tx_thread_stack_error_handler.c +..\..\..\..\common\src\tx_thread_stack_error_notify.c +..\..\..\..\common\src\tx_thread_suspend.c +..\..\..\..\common\src\tx_thread_system_preempt_check.c +..\..\..\..\common\src\tx_thread_system_resume.c +..\..\..\..\common\src\tx_thread_system_suspend.c +..\..\..\..\common\src\tx_thread_terminate.c +..\..\..\..\common\src\tx_thread_time_slice.c +..\..\..\..\common\src\tx_thread_time_slice_change.c +..\..\..\..\common\src\tx_thread_timeout.c +..\..\..\..\common\src\tx_thread_wait_abort.c +..\..\..\..\common\src\tx_time_get.c +..\..\..\..\common\src\tx_time_set.c +..\..\..\..\common\src\tx_timer_activate.c +..\..\..\..\common\src\tx_timer_change.c +..\..\..\..\common\src\tx_timer_create.c +..\..\..\..\common\src\tx_timer_deactivate.c +..\..\..\..\common\src\tx_timer_delete.c +..\..\..\..\common\src\tx_timer_expiration_process.c +..\..\..\..\common\src\tx_timer_info_get.c +..\..\..\..\common\src\tx_timer_initialize.c +..\..\..\..\common\src\tx_timer_performance_info_get.c +..\..\..\..\common\src\tx_timer_performance_system_info_get.c +..\..\..\..\common\src\tx_timer_system_activate.c +..\..\..\..\common\src\tx_timer_system_deactivate.c +..\..\..\..\common\src\tx_timer_thread_entry.c +..\..\..\..\common\src\tx_trace_buffer_full_notify.c +..\..\..\..\common\src\tx_trace_disable.c +..\..\..\..\common\src\tx_trace_enable.c +..\..\..\..\common\src\tx_trace_event_filter.c +..\..\..\..\common\src\tx_trace_event_unfilter.c +..\..\..\..\common\src\tx_trace_initialize.c +..\..\..\..\common\src\tx_trace_interrupt_control.c +..\..\..\..\common\src\tx_trace_isr_enter_insert.c +..\..\..\..\common\src\tx_trace_isr_exit_insert.c +..\..\..\..\common\src\tx_trace_object_register.c +..\..\..\..\common\src\tx_trace_object_unregister.c +..\..\..\..\common\src\tx_trace_user_event_insert.c +..\..\..\..\common\src\txe_block_allocate.c +..\..\..\..\common\src\txe_block_pool_create.c +..\..\..\..\common\src\txe_block_pool_delete.c +..\..\..\..\common\src\txe_block_pool_info_get.c +..\..\..\..\common\src\txe_block_pool_prioritize.c +..\..\..\..\common\src\txe_block_release.c +..\..\..\..\common\src\txe_byte_allocate.c +..\..\..\..\common\src\txe_byte_pool_create.c +..\..\..\..\common\src\txe_byte_pool_delete.c +..\..\..\..\common\src\txe_byte_pool_info_get.c +..\..\..\..\common\src\txe_byte_pool_prioritize.c +..\..\..\..\common\src\txe_byte_release.c +..\..\..\..\common\src\txe_event_flags_create.c +..\..\..\..\common\src\txe_event_flags_delete.c +..\..\..\..\common\src\txe_event_flags_get.c +..\..\..\..\common\src\txe_event_flags_info_get.c +..\..\..\..\common\src\txe_event_flags_set.c +..\..\..\..\common\src\txe_event_flags_set_notify.c +..\..\..\..\common\src\txe_mutex_create.c +..\..\..\..\common\src\txe_mutex_delete.c +..\..\..\..\common\src\txe_mutex_get.c +..\..\..\..\common\src\txe_mutex_info_get.c +..\..\..\..\common\src\txe_mutex_prioritize.c +..\..\..\..\common\src\txe_mutex_put.c +..\..\..\..\common\src\txe_queue_create.c +..\..\..\..\common\src\txe_queue_delete.c +..\..\..\..\common\src\txe_queue_flush.c +..\..\..\..\common\src\txe_queue_front_send.c +..\..\..\..\common\src\txe_queue_info_get.c +..\..\..\..\common\src\txe_queue_prioritize.c +..\..\..\..\common\src\txe_queue_receive.c +..\..\..\..\common\src\txe_queue_send.c +..\..\..\..\common\src\txe_queue_send_notify.c +..\..\..\..\common\src\txe_semaphore_ceiling_put.c +..\..\..\..\common\src\txe_semaphore_create.c +..\..\..\..\common\src\txe_semaphore_delete.c +..\..\..\..\common\src\txe_semaphore_get.c +..\..\..\..\common\src\txe_semaphore_info_get.c +..\..\..\..\common\src\txe_semaphore_prioritize.c +..\..\..\..\common\src\txe_semaphore_put.c +..\..\..\..\common\src\txe_semaphore_put_notify.c +..\..\..\..\common\src\txe_thread_create.c +..\..\..\..\common\src\txe_thread_delete.c +..\..\..\..\common\src\txe_thread_entry_exit_notify.c +..\..\..\..\common\src\txe_thread_info_get.c +..\..\..\..\common\src\txe_thread_preemption_change.c +..\..\..\..\common\src\txe_thread_priority_change.c +..\..\..\..\common\src\txe_thread_relinquish.c +..\..\..\..\common\src\txe_thread_reset.c +..\..\..\..\common\src\txe_thread_resume.c +..\..\..\..\common\src\txe_thread_suspend.c +..\..\..\..\common\src\txe_thread_terminate.c +..\..\..\..\common\src\txe_thread_time_slice_change.c +..\..\..\..\common\src\txe_thread_wait_abort.c +..\..\..\..\common\src\txe_timer_activate.c +..\..\..\..\common\src\txe_timer_change.c +..\..\..\..\common\src\txe_timer_create.c +..\..\..\..\common\src\txe_timer_deactivate.c +..\..\..\..\common\src\txe_timer_delete.c +..\..\..\..\common\src\txe_timer_info_get.c +..\..\..\..\ports_common_green\src\tx_el.c +..\..\..\..\ports_common_green\src\tx_ghs.c +..\..\..\..\ports_common_green\src\tx_ghse.c +..\..\..\..\ports_common_green\src\txr_block_allocate.c +..\..\..\..\ports_common_green\src\txr_block_pool_create.c +..\..\..\..\ports_common_green\src\txr_block_pool_delete.c +..\..\..\..\ports_common_green\src\txr_block_pool_info_get.c +..\..\..\..\ports_common_green\src\txr_block_pool_prioritize.c +..\..\..\..\ports_common_green\src\txr_block_release.c +..\..\..\..\ports_common_green\src\txr_byte_allocate.c +..\..\..\..\ports_common_green\src\txr_byte_pool_create.c +..\..\..\..\ports_common_green\src\txr_byte_pool_delete.c +..\..\..\..\ports_common_green\src\txr_byte_pool_info_get.c +..\..\..\..\ports_common_green\src\txr_byte_pool_prioritize.c +..\..\..\..\ports_common_green\src\txr_byte_release.c +..\..\..\..\ports_common_green\src\txr_event_flags_create.c +..\..\..\..\ports_common_green\src\txr_event_flags_delete.c +..\..\..\..\ports_common_green\src\txr_event_flags_get.c +..\..\..\..\ports_common_green\src\txr_event_flags_info_get.c +..\..\..\..\ports_common_green\src\txr_event_flags_set.c +..\..\..\..\ports_common_green\src\txr_event_flags_set_notify.c +..\..\..\..\ports_common_green\src\txr_ghs.c +..\..\..\..\ports_common_green\src\txr_mutex_create.c +..\..\..\..\ports_common_green\src\txr_mutex_delete.c +..\..\..\..\ports_common_green\src\txr_mutex_get.c +..\..\..\..\ports_common_green\src\txr_mutex_info_get.c +..\..\..\..\ports_common_green\src\txr_mutex_prioritize.c +..\..\..\..\ports_common_green\src\txr_mutex_put.c +..\..\..\..\ports_common_green\src\txr_queue_create.c +..\..\..\..\ports_common_green\src\txr_queue_delete.c +..\..\..\..\ports_common_green\src\txr_queue_flush.c +..\..\..\..\ports_common_green\src\txr_queue_front_send.c +..\..\..\..\ports_common_green\src\txr_queue_info_get.c +..\..\..\..\ports_common_green\src\txr_queue_prioritize.c +..\..\..\..\ports_common_green\src\txr_queue_receive.c +..\..\..\..\ports_common_green\src\txr_queue_send.c +..\..\..\..\ports_common_green\src\txr_queue_send_notify.c +..\..\..\..\ports_common_green\src\txr_semaphore_ceiling_put.c +..\..\..\..\ports_common_green\src\txr_semaphore_create.c +..\..\..\..\ports_common_green\src\txr_semaphore_delete.c +..\..\..\..\ports_common_green\src\txr_semaphore_get.c +..\..\..\..\ports_common_green\src\txr_semaphore_info_get.c +..\..\..\..\ports_common_green\src\txr_semaphore_prioritize.c +..\..\..\..\ports_common_green\src\txr_semaphore_put.c +..\..\..\..\ports_common_green\src\txr_semaphore_put_notify.c +..\..\..\..\ports_common_green\src\txr_thread_create.c +..\..\..\..\ports_common_green\src\txr_thread_delete.c +..\..\..\..\ports_common_green\src\txr_thread_entry_exit_notify.c +..\..\..\..\ports_common_green\src\txr_thread_info_get.c +..\..\..\..\ports_common_green\src\txr_thread_preemption_change.c +..\..\..\..\ports_common_green\src\txr_thread_priority_change.c +..\..\..\..\ports_common_green\src\txr_thread_reset.c +..\..\..\..\ports_common_green\src\txr_thread_resume.c +..\..\..\..\ports_common_green\src\txr_thread_suspend.c +..\..\..\..\ports_common_green\src\txr_thread_terminate.c +..\..\..\..\ports_common_green\src\txr_thread_time_slice_change.c +..\..\..\..\ports_common_green\src\txr_thread_wait_abort.c +..\..\..\..\ports_common_green\src\txr_timer_activate.c +..\..\..\..\ports_common_green\src\txr_timer_change.c +..\..\..\..\ports_common_green\src\txr_timer_create.c +..\..\..\..\ports_common_green\src\txr_timer_deactivate.c +..\..\..\..\ports_common_green\src\txr_timer_delete.c +..\..\..\..\ports_common_green\src\txr_timer_info_get.c diff --git a/ports/cortex_a8/green/inc/tx_port.h b/ports/cortex_a8/green/inc/tx_port.h new file mode 100644 index 00000000..61b3db87 --- /dev/null +++ b/ports/cortex_a8/green/inc/tx_port.h @@ -0,0 +1,402 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A8/Green Hills */ +/* 6.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include +#include +#include "tx_ghs.h" + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define constants for Green Hills EventAnalyzer. */ + +/* Define the number of ticks per second. This informs the EventAnalyzer what the timestamps + represent. By default, this is set to 1,000,000 i.e., one tick every microsecond. */ + +#define TX_EL_TICKS_PER_SECOND 1000000 + +/* Define the method of how to get the upper and lower 32-bits of the time stamp. By default, simply + simulate the time-stamp source with a counter. */ + +#define read_tbu() _tx_el_time_base_upper +#define read_tbl() ++_tx_el_time_base_lower + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ + VOID * tx_thread_eh_globals; \ + int Errno; /* errno. */ \ + char * strtok_saved_pos; /* strtok() position. */ +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + +#if (__GHS_VERSION_NUMBER >= 500) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) \ + { \ + extern void __tx_cpp_exception_init(TX_THREAD *thread_ptr); \ + __tx_cpp_exception_init(thread_ptr); \ + } +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) \ + { \ + #pragma weak __cpp_exception_init \ + extern void __cpp_exception_init(void **); \ + static void (*const cpp_init_funcp)(void **) = __cpp_exception_init; \ + if (cpp_init_funcp) \ + __cpp_exception_init(&(thread_ptr -> tx_thread_eh_globals)); \ + } +#endif + +#if (__GHS_VERSION_NUMBER >= 500) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) \ + { \ + extern void __tx_cpp_exception_cleanup(TX_THREAD *thread_ptr); \ + __tx_cpp_exception_cleanup(thread_ptr); \ + } +#else +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) \ + { \ + #pragma weak __cpp_exception_cleanup \ + extern void __cpp_exception_cleanup(void **); \ + static void (*const cpp_cleanup_funcp)(void **) = \ + __cpp_exception_cleanup; \ + if (cpp_cleanup_funcp) \ + __cpp_exception_cleanup(&(thread_ptr -> tx_thread_eh_globals)); \ + } +#endif + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + b = __CLZ32(m); \ + b = 31 - b; + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#if defined(__THUMB) + +unsigned int _tx_thread_interrupt_disable(void); +void _tx_thread_interrupt_restore(unsigned int new_posture); + +#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); + +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; + +#if defined(__GHS_VERSION_NUMBER) && (__GHS_VERSION_NUMBER >= 350) + +/* Define ThreadX interrupt lockout and restore macros using + compiler built-in functions if using Green Hills ARM compiler + version 3.5 or later. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_DISABLE interrupt_save = __GETSR(); \ + __SETSR(interrupt_save | 0xC0); + +#define TX_RESTORE __SETSR(interrupt_save); +#else +#define TX_DISABLE interrupt_save = __GETSR(); \ + __SETSR(interrupt_save | 0x80); + +#define TX_RESTORE __SETSR(interrupt_save); +#endif + +#else + +/* Define ThreadX interrupt lockout and restore macros using + asm macros if using Green Hills ARM compiler earlier than + version 3.5. */ + +asm int disable_ints(void) +{ +% + MRS r0,CPSR +#ifdef TX_BEFORE_ARMV6 +#ifdef TX_ENABLE_FIQ_SUPPORT + ORR r1,r0,0xC0 +#else + ORR r1,r0,0x80 +#endif + MSR CPSR_c,r1 +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if +#else + CPSID i +#endif +#endif +%error +} + +asm void restore_ints(int a) +{ +%reg a + MSR CPSR_c,a +%mem a + LDR r0,a + MSR CPSR_c,r0 +%error +} + +#define TX_DISABLE interrupt_save = disable_ints(); + +#define TX_RESTORE restore_ints(interrupt_save); +#endif +#endif + + +/* Define VFP extension for the Cortex-A8. Each is assumed to be called in the context of the executing + thread. */ + +void tx_thread_vfp_enable(void); +void tx_thread_vfp_disable(void); + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A8/Green Hills Version 6.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + diff --git a/ports/cortex_a8/green/readme_threadx.txt b/ports/cortex_a8/green/readme_threadx.txt new file mode 100644 index 00000000..330d21e2 --- /dev/null +++ b/ports/cortex_a8/green/readme_threadx.txt @@ -0,0 +1,528 @@ + Microsoft's Azure RTOS ThreadX for Cortex-A8 + + Using the Green Hills Software Tools + +1. Open the ThreadX Project Workspace + +In order to build the ThreadX library and the ThreadX demonstration first load +the Azure RTOS Workspace azure_rtos_workspace.gpj, which is located inside the +"example_build" directory. + + +2. Building the ThreadX run-time Library + +Building the ThreadX library is easy; simply select the MULTI project file +tx.gpj and then select the build button. You should now observe the +compilation and assembly of the ThreadX library. This project build produces +the ThreadX library file tx.a. + + +3. Demonstration System + +The ThreadX demonstration is designed to execute under the MULTI environment +on the Green Hills Cortex-A8 simulator. The instructions that follow describe +how to get the ThreadX evaluation running under the MULTI Cortex-A8 simulation +environment. + +Building the demonstration is easy; simply select the MULTI project file +sample_threadx.gpj. At this point, select the "Project Build" button and observe +the compilation, assembly, and linkage of the ThreadX demonstration application. + +After the demonstration is built, invoke the MULTI ARM simulator by selecting +the simulator connection from within the sample_threadx.con connection file. +Once connected to the simulator, select the "Debug" button. You should now +observe the main function of sample_threadx.c. + +At this point, you should setup a simulated timer interrupt for ThreadX +by entering "timer 9999 irq" in the "target" window of the debugger. + +You are now ready to execute the ThreadX demonstration system. Select +breakpoints and data watches to observe the execution of the sample_threadx.c +application. + + +4. EventAnalyzer Demonstration + +To build a demonstration system that also logs events for the MULTI EventAnalyzer, +perform the same steps as the regular demo, except build the ThreadX library with +txe.gpj file and use the sample_threadx_el.gpj build file to build the demonstration. +The resulting image will log all system events, which can then be displayed by the +MULTI EventAnalyzer. + + +5. System Initialization + +The system entry point using the Green Hills tools is at the label _start. +This is defined within the crt0.arm file supplied by Green Hills. In addition, +this is where all static and global preset C variable initialization +processing is called from. + +After the Green Hills startup function returns, ThreadX initialization is +called. The main initialization function is _tx_initialize_low_level and +is located in the file tx_initialize_low_level.arm. This function is responsible +for setting up various system data structures, interrupt vectors, and the +periodic timer interrupt source of ThreadX. + +In addition, _tx_initialize_low_level determines where the first available +RAM memory address is located. This address is supplied to tx_application_define. + +By default, the first available RAM memory address is assumed to start at the +beginning of the ThreadX section .free_mem. If changes are made to the +sample_threadx.ld file, the .free_mem section should remain the last allocated +section in the main RAM area. The starting address of this section is passed +to tx_application_define. + + +6. User defines + +The following defines and their associated action are as follows: + + Define Meaning + + TX_ENABLE_IRQ_NESTING If defined, this brings in special IRQ + interrupt nesting logic into the ThreadX + library. This define should be applied + to the entire ThreadX library. + + TX_ENABLE_FIQ_NESTING If defined, this brings in special FIQ + interrupt nesting logic into the ThreadX + library. This define should be applied + to the entire ThreadX library and the + define TX_ENABLE_FIQ_SUPPORT should also + be defined. + + TX_ENABLE_FIQ_SUPPORT If defined, this brings in FIQ context + save and restore logic necessary for + applications to call ThreadX services from + FIQ interrupt handlers. This define + should be applied to the entire ThreadX + library. + + + TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, + this define causes basic ThreadX error + checking to be disabled. Please see + Chapter 4 in the "ThreadX User Guide" + for more details. + + TX_ENABLE_EVENT_LOGGING This define enables event logging for any + or all of the ThreadX source code. If this + option is used anywhere, the tx_initialize_high_level.c + file must be compiled with it as well, since this + is where the event log is initialized. + + TX_NO_EVENT_INFO This is a sub-option for event logging. + If this is enabled, only basic information + is saved in the log. + + TX_ENABLE_EVENT_FILTERS This is also a sub-option for event-logging. + If this is enabled, run-time filtering logic + is added to the event logging code. + + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By + default, this value is set to 32 priority levels. + + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found + in tx_port.h. + + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default + value is port-specific and is found in tx_port.h. + + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined + in tx_port.h. + + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. + By default, this option is not defined. + + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. + By default, this option is not defined. + + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is + not defined. + + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. + By default, this option is not defined. + + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. + By default, this option is not defined. + + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. + By default, this option is not defined. + + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size + and improves performance. + + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is + not defined. + + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is + not defined. + + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option + is not defined. + + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is + not defined. + + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is + not defined. + + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is + not defined. + + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is + not defined. + + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is + not defined. + + + +7. Register Usage and Stack Frames + +The Green Hills compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) +are scratch registers for each function. All other registers used by a C +function must be preserved by the function. ThreadX takes advantage of this +in situations where a context switch happens as a result of making a ThreadX +service call (which is itself a C function). In such cases, the saved +context of a thread is only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 CPSR CPSR + 0x08 r0 (a1) r4 (v1) + 0x0C r1 (a2) r5 (v2) + 0x10 r2 (a3) r6 (v3) + 0x14 r3 (a4) r7 (v4) + 0x18 r4 (v1) r8 (v5) + 0x1C r5 (v2) r9 (v6) + 0x20 r6 (v3) r10 (v7) + 0x24 r7 (v4) r11 (fp) + 0x28 r8 (v5) r14 (lr) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) + 0x3C r14 (lr) + 0x40 PC + + +8. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make ThreadX run faster, you can change the tx.gpj project +to disable debug information and enable the desired optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined before tx_api.h is included. + + +9. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-A8 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +9.1 Vector Area + +The Cortex-A8 vectors start at address zero. The demonstration system reset.arm +file contains the reset section (which contains all the ARM vectors) and is +typically loaded at address zero. On actual hardware platforms, this section +might have to be copied to address 0. + +9.2 IRQ ISRs + +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested +IRQ interrupts. The following sub-sections define the IRQ capabilities. + + +9.2.1 Standard IRQ ISRs + +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +is the default IRQ handler defined in tx_initialize_low_level.arm: + + + .globl __tx_irq_handler + .globl __tx_irq_processing_return +__tx_irq_handler: + + /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return: + + /* At this point execution is still in the IRQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. Note + that IRQ interrupts are still disabled upon return from the context + save function. */ + + /* Application ISR call(s) go here! */ + + /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +9.2.2 Vectored IRQ ISRs + +The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified +by the particular implementation. The following is an example IRQ handler defined in +tx_initialize_low_level.arm: + + .globl __tx_irq_example_handler +__tx_irq_example_handler: + + /* Call context save to save system context. */ + + STMDB sp!, {r0-r3} # Save some scratch registers + MRS r0, SPSR # Pickup saved SPSR + SUB lr, lr, #4 # Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} # Store other scratch registers + BL _tx_thread_vectored_context_save # Call the vectored IRQ context save + + /* At this point execution is still in the IRQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. Note + that IRQ interrupts are still disabled upon return from the context + save function. */ + + /* Application ISR call goes here! */ + + /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +9.2.3 Nested IRQ Support + +By default, nested IRQ interrupt support is not enabled. To enable nested +IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING +defined. With this defined, two new IRQ interrupt management services are +available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. +These function should be called between the IRQ context save and restore +calls. + +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +by switching from IRQ mode to SYS mode and enabling IRQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.arm. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables nesting +by disabling IRQ interrupts and switching back to IRQ mode in preparation for +the IRQ context restore service. + +The following is an example of enabling IRQ nested interrupts in the +typical IRQ handler: + + .globl __tx_irq_handler + .globl __tx_irq_processing_return +__tx_irq_handler: + + /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return: + + /* Enable nested IRQ interrupts. NOTE: Since this service returns + with IRQ interrupts enabled, all IRQ interrupt sources must be + cleared prior to calling this service. */ + BL _tx_thread_irq_nesting_start + + /* Application ISR call(s) go here! */ + + /* Disable nested IRQ interrupts. The mode is switched back to + IRQ mode and IRQ interrupts are disable upon return. */ + BL _tx_thread_irq_nesting_end + + /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +9.3 FIQ Interrupts + +By default, Cortex-A8 FIQ interrupts are left completely enabled by ThreadX. +Of course, this means that the application is fully responsible for +saving/restoring any registers used in the FIQ ISR processing. In addition, +no ThreadX service calls are allowed from the default FIQ ISRs. The default +FIQ interrupt shell is located in tx_initialize_low_level.arm. + +9.3.1 Managed FIQ Interrupts + +Full ThreadX management of FIQ interrupts is provided if the ThreadX sources +are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built +this way, the FIQ interrupt handlers are very similar to the IRQ interrupt +handlers defined previously. The following is default FIQ handler +defined in tx_initialize_low_level.arm: + + + .globl __tx_fiq_handler + .globl __tx_fiq_processing_return +__tx_fiq_handler: + + /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: + + /* At this point execution is still in the FIQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. */ + + /* Application FIQ handlers can be called here! */ + + /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +9.3.1.1 Nested FIQ Support + +By default, nested FIQ interrupt support is not enabled. To enable nested +FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING +defined. With this defined, two new FIQ interrupt management services are +available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. +These function should be called between the FIQ context save and restore +calls. + +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +by switching from FIQ mode to SYS mode and enabling FIQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.arm. When nested FIQ interrupts are no longer +required, calling the _tx_thread_fiq_nesting_end service disables nesting by +disabling FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +context restore service. + +The following is an example of enabling FIQ nested interrupts in the +typical FIQ handler: + + + .globl __tx_fiq_handler + .globl __tx_fiq_processing_return +__tx_fiq_handler: + + /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: + + /* At this point execution is still in the FIQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. */ + + /* Enable nested FIQ interrupts. NOTE: Since this service returns + with FIQ interrupts enabled, all FIQ interrupt sources must be + cleared prior to calling this service. */ + BL _tx_thread_fiq_nesting_start + + /* Application FIQ handlers can be called here! */ + + /* Disable nested FIQ interrupts. The mode is switched back to + FIQ mode and FIQ interrupts are disable upon return. */ + BL _tx_thread_fiq_nesting_end + + /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + + +10. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional. However, all other +ThreadX services are operational without a periodic timer source. + +To add the timer interrupt processing, simply make a call to +_tx_timer_interrupt in the IRQ processing. An example of this can be +found in the file tx_initialize_low_level.arm. + + +11. Thumb/Cortex-A8 Mixed Mode + +By default, ThreadX is setup for running in Cortex-A8 32-bit mode. This is +also true for the demonstration system. It is possible to build any +ThreadX file and/or the application in Thumb mode. The only exception +to this is the file tx_thread_shell_entry.c. This file must always be +built in 32-bit mode. + + +12. VFP Support + +By default, VFP support is disabled for each thread. If saving the context of the VFP registers +is needed, the following API call must be made from the context of the application thread - before +the VFP usage: + +void tx_thread_vfp_enable(void); + +After this API is called in the application, VFP registers will be saved/restored for this thread if it +is preempted via an interrupt. All other suspension of the this thread will not require the VFP registers +to be saved/restored. + +To disable VFP register context saving, simply call the following API: + +void tx_thread_vfp_disable(void); + + + +13. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +05/19/2020 Initial ThreadX version of Cortex-A8/Green Hills port. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_a8/green/src/tx_thread_context_restore.arm b/ports/cortex_a8/green/src/tx_thread_context_restore.arm new file mode 100644 index 00000000..d64adde7 --- /dev/null +++ b/ports/cortex_a8/green/src/tx_thread_context_restore.arm @@ -0,0 +1,259 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # Disable IRQ and FIQ interrupts +#else + DISABLE_INTS = 0x80 # Disable IRQ interrupts +#endif + SVC_MODE = (0x13 | DISABLE_INTS) # SVC mode + IRQ_MODE = (0x12 | DISABLE_INTS) # IRQ mode + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore Cortex-A8/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores the interrupt context if it is processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_restore(VOID) +{ */ + .globl _tx_thread_context_restore +_tx_thread_context_restore: + + /* Lockout interrupts. */ + +#ifdef TX_BEFORE_ARMV6 + MRS r3, CPSR # Pickup current CPSR + ORR r0, r3, DISABLE_INTS # Build interrupt disable value + MSR CPSR_c, r0 # Lockout interrupts +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if # Disable IRQ and FIQ interrupts +#else + CPSID i # Disable IRQ interrupts +#endif +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR exit function to indicate an ISR is complete. */ + + BL _tx_execution_isr_exit # Call the ISR exit function +#endif + + /* Determine if interrupts are nested. */ + /* if (--_tx_thread_system_state) + { */ + + LDR r3, =_tx_thread_system_state # Pickup address of system state var + LDR r2, [r3] # Pickup system state + SUB r2, r2, 1 # Decrement the counter + STR r2, [r3] # Store the counter + CMP r2, 0 # Was this the first interrupt? + BEQ __tx_thread_not_nested_restore # If so, not a nested restore + + /* Interrupts are nested. */ + + /* Just recover the saved registers and return to the point of + interrupt. */ + + LDMIA sp!, {r0, r10, r12, lr} # Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 # Put SPSR back + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOVS pc, lr # Return to point of interrupt + + /* } */ +__tx_thread_not_nested_restore: + + /* Determine if a thread was interrupted and no preemption is required. */ + /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) + || (_tx_thread_preempt_disable)) + { */ + + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup actual current thread pointer + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_idle_system_restore # Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable # Pickup preempt disable address + LDR r2, [r3] # Pickup actual preempt disable flag + CMP r2, 0 # Is it set? + BNE __tx_thread_no_preempt_restore # Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr # Pickup address of execute thread ptr + LDR r2, [r3] # Pickup actual execute thread pointer + CMP r0, r2 # Is the same thread highest priority? + BNE __tx_thread_preempt_restore # No, preemption needs to happen + + +__tx_thread_no_preempt_restore: + + /* Restore interrupted thread or ISR. */ + + /* Pickup the saved stack pointer. */ + /* tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; */ + + /* Recover the saved context and return to the point of interrupt. */ + + LDMIA sp!, {r0, r10, r12, lr} # Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 # Put SPSR back + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOVS pc, lr # Return to point of interrupt + + /* } + else + { */ +__tx_thread_preempt_restore: + + LDMIA sp!, {r3, r10, r12, lr} # Recover temporarily saved registers + MOV r1, lr # Save lr (point of interrupt) + MOV r2, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r2 # Enter SVC mode + STR r1, [sp, -4]! # Save point of interrupt + STMDB sp!, {r4-r12, lr} # Save upper half of registers + MOV r4, r3 # Save SPSR in r4 + MOV r2, IRQ_MODE # Build IRQ mode CPSR + MSR CPSR_c, r2 # Re-enter IRQ mode + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOV r5, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r5 # Enter SVC mode + STMDB sp!, {r0-r3} # Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup current thread pointer + +#ifdef __VFP__ + LDR r2, [r0, 144] # Pickup the VFP enabled flag + CMP r2, 0 # Is the VFP enabled? + BEQ _tx_skip_irq_vfp_save # No, skip VFP IRQ save + VMRS r2, FPSCR # Pickup the FPSCR + STR r2, [sp, -4]! # Save FPSCR + VSTMDB sp!, {D16-D31} # Save D16-D31 + VSTMDB sp!, {D0-D15} # Save D0-D15 +_tx_skip_irq_vfp_save: +#endif + + MOV r3, 1 # Build interrupt stack type + STMDB sp!, {r3, r4} # Save interrupt stack type and SPSR + STR sp, [r0, 8] # Save stack pointer in thread control + /* # block */ + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r4, r0 # Save r0 + MOV r5, r1 # Save r1 + BL _tx_el_thread_preempted # Call thread preempted routine + MOV r0, r4 # Restore r0 + MOV r1, r5 # Restore r1 +#endif + + /* Save the remaining time-slice and disable it. */ + /* if (_tx_timer_time_slice) + { */ + + LDR r3, =_tx_timer_time_slice # Pickup time-slice variable address + LDR r2, [r3] # Pickup time-slice + CMP r2, 0 # Is it active? + BEQ __tx_thread_dont_save_ts # No, don't save it + + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + STR r2, [r0, 24] # Save thread's time-slice + MOV r2, 0 # Clear value + STR r2, [r3] # Disable global time-slice flag + + /* } */ +__tx_thread_dont_save_ts: + + + /* Clear the current task pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + MOV r0, 0 # NULL value + STR r0, [r1] # Clear current thread pointer + + /* Return to the scheduler. */ + /* _tx_thread_schedule(); */ + + B _tx_thread_schedule # Return to scheduler + /* } */ + +__tx_thread_idle_system_restore: + + /* Just return back to the scheduler! */ + + + MOV r3, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r3 # Lockout interrupts + B _tx_thread_schedule # Return to scheduler + + .type _tx_thread_context_restore,$function + .size _tx_thread_context_restore,.-_tx_thread_context_restore + +/* } */ + diff --git a/ports/cortex_a8/green/src/tx_thread_context_save.arm b/ports/cortex_a8/green/src/tx_thread_context_save.arm new file mode 100644 index 00000000..8e868cf0 --- /dev/null +++ b/ports/cortex_a8/green/src/tx_thread_context_save.arm @@ -0,0 +1,207 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # IRQ & FIQ interrupts disabled +#else + DISABLE_INTS = 0x80 # IRQ interrupts disabled +#endif + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save Cortex-A8/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_save(VOID) +{ */ + .globl _tx_thread_context_save +_tx_thread_context_save: + + /* Upon entry to this routine, it is assumed that IRQ interrupts are locked + out, we are in IRQ mode, and all registers are intact. */ + + /* Check for a nested interrupt condition. */ + /* if (_tx_thread_system_state++) + { */ + + STMDB sp!, {r0-r3} # Save some working registers + +#ifdef TX_ENABLE_FIQ_SUPPORT +#ifdef TX_BEFORE_ARMV6 + MRS r0, CPSR # Pickup the CPSR + ORR r0, r0, DISABLE_INTS # Build disable interrupt CPSR + MSR CPSR_c, r0 # Disable interrupts +#else + CPSID if # Disable FIQ interrupts +#endif +#endif + + LDR r3, =_tx_thread_system_state # Pickup address of system state var + LDR r2, [r3] # Pickup system state + CMP r2, 0 # Is this the first interrupt? + BEQ __tx_thread_not_nested_save # Yes, not a nested context save + + /* Nested interrupt condition. */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + + /* Save the rest of the scratch registers on the stack and return to the + calling ISR. */ + + MRS r0, SPSR # Pickup saved SPSR + SUB lr, lr, 4 # Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} # Store other registers + + /* Return to the ISR. */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + B __tx_irq_processing_return # Continue IRQ processing + +__tx_thread_not_nested_save: + /* } */ + + /* Otherwise, not nested, check to see if a thread was running. */ + /* else if (_tx_thread_current_ptr) + { */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup current thread pointer + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_idle_system_save # If so, interrupt occurred in + /* # scheduling loop - nothing needs saving! */ + + /* Save minimal context of interrupted thread. */ + + MRS r2, SPSR # Pickup saved SPSR + SUB lr, lr, 4 # Adjust point of interrupt + STMDB sp!, {r2, r10, r12, lr} # Store other registers + + /* Save the current stack pointer in the thread's control block. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ + + /* Switch to the system stack. */ + /* sp = _tx_thread_system_stack_ptr; */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + B __tx_irq_processing_return # Continue IRQ processing + + /* } + else + { */ + +__tx_thread_idle_system_save: + + /* Interrupt occurred in the scheduling loop. */ + + /* Not much to do here, just adjust the stack pointer, and return to IRQ + processing. */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + ADD sp, sp, 16 # Recover saved registers + B __tx_irq_processing_return # Continue IRQ processing + + .type _tx_thread_context_save,$function + .size _tx_thread_context_save,.-_tx_thread_context_save + + /* } +} */ + diff --git a/ports/cortex_a8/green/src/tx_thread_fiq_context_restore.arm b/ports/cortex_a8/green/src/tx_thread_fiq_context_restore.arm new file mode 100644 index 00000000..9a943616 --- /dev/null +++ b/ports/cortex_a8/green/src/tx_thread_fiq_context_restore.arm @@ -0,0 +1,264 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + SVC_MODE = 0xD3 # SVC mode + FIQ_MODE = 0xD1 # FIQ mode +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # Disable IRQ and FIQ interrupts +#else + DISABLE_INTS = 0x80 # Disable IRQ interrupts +#endif + MODE_MASK = 0x1F # Mode mask + IRQ_MODE_BITS = 0x12 # IRQ mode bits + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_context_restore Cortex-A8/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores the fiq interrupt context when processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* FIQ ISR Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_fiq_context_restore(VOID) +{ */ + .globl _tx_thread_fiq_context_restore +_tx_thread_fiq_context_restore: + + /* Lockout interrupts. */ + +#ifdef TX_BEFORE_ARMV6 + MRS r3, CPSR # Pickup current CPSR + ORR r0, r3, DISABLE_INTS # Build interrupt disable value + MSR CPSR_c, r0 # Lockout interrupts +#else + CPSID if # Disable IRQ and FIQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR exit function to indicate an ISR is complete. */ + + BL _tx_execution_isr_exit # Call the ISR exit function +#endif + + /* Determine if interrupts are nested. */ + /* if (--_tx_thread_system_state) + { */ + + LDR r3, =_tx_thread_system_state # Pickup address of system state var + LDR r2, [r3] # Pickup system state + SUB r2, r2, 1 # Decrement the counter + STR r2, [r3] # Store the counter + CMP r2, 0 # Was this the first interrupt? + BEQ __tx_thread_fiq_not_nested_restore # If so, not a nested restore + + /* Interrupts are nested. */ + + /* Just recover the saved registers and return to the point of + interrupt. */ + + LDMIA sp!, {r0, r10, r12, lr} # Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 # Put SPSR back + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOVS pc, lr # Return to point of interrupt + + /* } */ +__tx_thread_fiq_not_nested_restore: + + /* Determine if a thread was interrupted and no preemption is required. */ + /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) + || (_tx_thread_preempt_disable)) + { */ + + LDR r1, [sp] # Pickup the saved SPSR + MOV r2, MODE_MASK # Build mask to isolate the interrupted mode + AND r1, r1, r2 # Isolate mode bits + CMP r1, IRQ_MODE_BITS # Was an interrupt taken in IRQ mode before we + /* # got to context save? */ + BEQ __tx_thread_fiq_no_preempt_restore # Yes, just go back to point of interrupt + + + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup actual current thread pointer + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_fiq_idle_system_restore # Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable # Pickup preempt disable address + LDR r2, [r3] # Pickup actual preempt disable flag + CMP r2, 0 # Is it set? + BNE __tx_thread_fiq_no_preempt_restore # Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr # Pickup address of execute thread ptr + LDR r2, [r3] # Pickup actual execute thread pointer + CMP r0, r2 # Is the same thread highest priority? + BNE __tx_thread_fiq_preempt_restore # No, preemption needs to happen + + +__tx_thread_fiq_no_preempt_restore: + + /* Restore interrupted thread or ISR. */ + + /* Pickup the saved stack pointer. */ + /* tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; */ + + /* Recover the saved context and return to the point of interrupt. */ + + LDMIA sp!, {r0, lr} # Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 # Put SPSR back + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOVS pc, lr # Return to point of interrupt + + /* } + else + { */ +__tx_thread_fiq_preempt_restore: + + LDMIA sp!, {r3, lr} # Recover temporarily saved registers + MOV r1, lr # Save lr (point of interrupt) + MOV r2, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r2 # Enter SVC mode + STR r1, [sp, -4]! # Save point of interrupt + STMDB sp!, {r4-r12, lr} # Save upper half of registers + MOV r4, r3 # Save SPSR in r4 + MOV r2, FIQ_MODE # Build FIQ mode CPSR + MSR CPSR_c, r2 # Re-enter FIQ mode + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOV r5, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r5 # Enter SVC mode + STMDB sp!, {r0-r3} # Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup current thread pointer + +#ifdef __VFP__ + LDR r2, [r0, 144] # Pickup the VFP enabled flag + CMP r2, 0 # Is the VFP enabled? + BEQ _tx_skip_fiq_vfp_save # No, skip VFP IRQ save + VMRS r2, FPSCR # Pickup the FPSCR + STR r2, [sp, -4]! # Save FPSCR + VSTMDB sp!, {D16-D31} # Save D16-D31 + VSTMDB sp!, {D0-D15} # Save D0-D15 +_tx_skip_fiq_vfp_save: +#endif + + MOV r3, 1 # Build interrupt stack type + STMDB sp!, {r3, r4} # Save interrupt stack type and SPSR + STR sp, [r0, 8] # Save stack pointer in thread control + /* # block */ + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r4, r0 # Save r0 + MOV r5, r1 # Save r1 + BL _tx_el_thread_preempted # Call thread preempted routine + MOV r0, r4 # Restore r0 + MOV r1, r5 # Restore r1 +#endif + + /* Save the remaining time-slice and disable it. */ + /* if (_tx_timer_time_slice) + { */ + + LDR r3, =_tx_timer_time_slice # Pickup time-slice variable address + LDR r2, [r3] # Pickup time-slice + CMP r2, 0 # Is it active? + BEQ __tx_thread_fiq_dont_save_ts # No, don't save it + + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + STR r2, [r0, 24] # Save thread's time-slice + MOV r2, 0 # Clear value + STR r2, [r3] # Disable global time-slice flag + + /* } */ +__tx_thread_fiq_dont_save_ts: + + + /* Clear the current task pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + MOV r0, 0 # NULL value + STR r0, [r1] # Clear current thread pointer + + /* Return to the scheduler. */ + /* _tx_thread_schedule(); */ + + B _tx_thread_schedule # Return to scheduler + /* } */ + +__tx_thread_fiq_idle_system_restore: + + /* Just return back to the scheduler! */ + + ADD sp, sp, 24 # Recover FIQ stack space + MOV r3, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r3 # Lockout interrupts + B _tx_thread_schedule # Return to scheduler + + .type _tx_thread_fiq_context_restore,$function + .size _tx_thread_fiq_context_restore,.-_tx_thread_fiq_context_restore + +/* } */ + diff --git a/ports/cortex_a8/green/src/tx_thread_fiq_context_save.arm b/ports/cortex_a8/green/src/tx_thread_fiq_context_save.arm new file mode 100644 index 00000000..70c04156 --- /dev/null +++ b/ports/cortex_a8/green/src/tx_thread_fiq_context_save.arm @@ -0,0 +1,197 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_context_save Cortex-A8/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_fiq_context_save(VOID) +{ */ + .globl _tx_thread_fiq_context_save +_tx_thread_fiq_context_save: + + /* Upon entry to this routine, it is assumed that IRQ interrupts are locked + out, we are in IRQ mode, and all registers are intact. */ + + /* Check for a nested interrupt condition. */ + /* if (_tx_thread_system_state++) + { */ + + STMDB sp!, {r0-r3} # Save some working registers + LDR r3, =_tx_thread_system_state # Pickup address of system state var + LDR r2, [r3] # Pickup system state + CMP r2, 0 # Is this the first interrupt? + BEQ __tx_thread_fiq_not_nested_save # Yes, not a nested context save + + /* Nested interrupt condition. */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + + /* Save the rest of the scratch registers on the stack and return to the + calling ISR. */ + + MRS r0, SPSR # Pickup saved SPSR + SUB lr, lr, 4 # Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} # Store other registers + + /* Return to the ISR. */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + B __tx_fiq_processing_return # Continue FIQ processing + +__tx_thread_fiq_not_nested_save: + /* } */ + + /* Otherwise, not nested, check to see if a thread was running. */ + /* else if (_tx_thread_current_ptr) + { */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup current thread pointer + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_fiq_idle_system_save # If so, interrupt occurred in + /* # scheduling loop - nothing needs saving! */ + + /* Save minimal context of interrupted thread. */ + + MRS r2, SPSR # Pickup saved SPSR + SUB lr, lr, 4 # Adjust point of interrupt + STMDB sp!, {r2, lr} # Store other registers, Note that we don't + /* # need to save sl and ip since FIQ has + # copies of these registers. Nested + # interrupt processing does need to save + # these registers. */ + + /* Save the current stack pointer in the thread's control block. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ + + /* Switch to the system stack. */ + /* sp = _tx_thread_system_stack_ptr; */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + B __tx_fiq_processing_return # Continue FIQ processing + + /* } + else + { */ + +__tx_thread_fiq_idle_system_save: + + /* Interrupt occurred in the scheduling loop. */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + /* Not much to do here, save the current SPSR and LR for possible + use in IRQ interrupted in idle system conditions, and return to + FIQ interrupt processing. */ + + MRS r0, SPSR # Pickup saved SPSR + SUB lr, lr, 4 # Adjust point of interrupt + STMDB sp!, {r0, lr} # Store other registers that will get used + /* # or stripped off the stack in context + # restore */ + B __tx_fiq_processing_return # Continue FIQ processing + + .type _tx_thread_fiq_context_save,$function + .size _tx_thread_fiq_context_save,.-_tx_thread_fiq_context_save + + /* } +} */ + diff --git a/ports/cortex_a8/green/src/tx_thread_fiq_nesting_end.arm b/ports/cortex_a8/green/src/tx_thread_fiq_nesting_end.arm new file mode 100644 index 00000000..176af18b --- /dev/null +++ b/ports/cortex_a8/green/src/tx_thread_fiq_nesting_end.arm @@ -0,0 +1,109 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # Disable IRQ and FIQ interrupts +#else + DISABLE_INTS = 0x80 # Disable IRQ interrupts +#endif + MODE_MASK = 0x1F # Mode mask + FIQ_MODE_BITS = 0x11 # FIQ mode bits + SVC_MODE_BITS = 0x13 # SVC mode value */ + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_nesting_end Cortex-A8/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from FIQ mode after */ +/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +/* processing from system mode back to FIQ mode prior to the ISR */ +/* calling _tx_thread_fiq_context_restore. Note that this function */ +/* assumes the system stack pointer is in the same position after */ +/* nesting start function was called. */ +/* */ +/* This function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.arm). */ +/* */ +/* This function returns with FIQ interrupts disabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_fiq_nesting_end(VOID) +{ */ + .globl _tx_thread_fiq_nesting_end +_tx_thread_fiq_nesting_end: + MOV r3,lr # Save ISR return address + MRS r0, CPSR # Pickup the CPSR + ORR r0, r0, DISABLE_INTS # Build disable interrupt value + MSR CPSR_c, r0 # Disable interrupts + LDR lr, [sp] # Pickup saved lr + ADD sp, sp, 4 # Adjust stack pointer + BIC r0, r0, MODE_MASK # Clear mode bits + ORR r0, r0, FIQ_MODE_BITS # Build IRQ mode CPSR + MSR CPSR_c, r0 # Re-enter IRQ mode + MOV pc, r3 # Return to ISR + + .type _tx_thread_fiq_nesting_end,$function + .size _tx_thread_fiq_nesting_end,.-_tx_thread_fiq_nesting_end +/* } */ + diff --git a/ports/cortex_a8/green/src/tx_thread_fiq_nesting_start.arm b/ports/cortex_a8/green/src/tx_thread_fiq_nesting_start.arm new file mode 100644 index 00000000..93d45a8e --- /dev/null +++ b/ports/cortex_a8/green/src/tx_thread_fiq_nesting_start.arm @@ -0,0 +1,103 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + + FIQ_DISABLE = 0x40 # FIQ disable bit + MODE_MASK = 0x1F # Mode mask + SYS_MODE_BITS = 0x1F # System mode bits + + + .text + .align 4 + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_nesting_start Cortex-A8/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from FIQ mode after */ +/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +/* processing to the system mode so nested FIQ interrupt processing */ +/* is possible (system mode has its own "lr" register). Note that */ +/* this function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.arm). */ +/* */ +/* This function returns with FIQ interrupts enabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_fiq_nesting_start(VOID) +{ */ + .globl _tx_thread_fiq_nesting_start +_tx_thread_fiq_nesting_start: + MOV r3,lr # Save ISR return address + MRS r0, CPSR # Pickup the CPSR + BIC r0, r0, MODE_MASK # Clear the mode bits + ORR r0, r0, SYS_MODE_BITS # Build system mode CPSR + MSR CPSR_c, r0 # Enter system mode + STR lr, [sp, -4]! # Push the system mode lr on the system mode stack + BIC r0, r0, FIQ_DISABLE # Build enable FIQ CPSR + MSR CPSR_c, r0 # Enter system mode + MOV pc, r3 # Return to ISR + + .type _tx_thread_fiq_nesting_start,$function + .size _tx_thread_fiq_nesting_start,.-_tx_thread_fiq_nesting_start +/* } */ + diff --git a/ports/cortex_a8/green/src/tx_thread_interrupt_control.arm b/ports/cortex_a8/green/src/tx_thread_interrupt_control.arm new file mode 100644 index 00000000..3df58bdd --- /dev/null +++ b/ports/cortex_a8/green/src/tx_thread_interrupt_control.arm @@ -0,0 +1,101 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" */ + + +#ifdef TX_ENABLE_FIQ_SUPPORT + INT_MASK = 0xC0 # Interrupt bit mask +#else + INT_MASK = 0x80 # Interrupt bit mask +#endif + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control Cortex-A8/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_control(UINT new_posture) +{ */ + .globl _tx_thread_interrupt_control +_tx_thread_interrupt_control: + + /* Pickup current interrupt lockout posture. */ + + MRS r3, CPSR # Pickup current CPSR + BIC r1, r3, INT_MASK # Clear interrupt lockout bits + ORR r1, r1, r0 # Or-in new interrupt lockout bits + + /* Apply the new interrupt posture. */ + + MSR CPSR_c, r1 # Setup new CPSR + AND r0, r3, INT_MASK # Return previous interrupt mask + RET # Return to caller + + .type _tx_thread_interrupt_control,$function + .size _tx_thread_interrupt_control,.-_tx_thread_interrupt_control +/* } */ + + + diff --git a/ports/cortex_a8/green/src/tx_thread_interrupt_disable.arm b/ports/cortex_a8/green/src/tx_thread_interrupt_disable.arm new file mode 100644 index 00000000..6f82915d --- /dev/null +++ b/ports/cortex_a8/green/src/tx_thread_interrupt_disable.arm @@ -0,0 +1,105 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" */ + + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # IRQ & FIQ interrupts disabled +#else + DISABLE_INTS = 0x80 # IRQ interrupts disabled +#endif + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_disable Cortex-A8/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for disabling interrupts */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_disable(void) +{ */ + .globl _tx_thread_interrupt_disable +_tx_thread_interrupt_disable: + + /* Pickup current interrupt lockout posture. */ + + MRS r0, CPSR # Pickup current CPSR + + /* Mask interrupts. */ + +#ifdef TX_BEFORE_ARMV6 + ORR r1, r0, DISABLE_INTS # Mask interrupts + MSR CPSR_c, r1 # Setup new CPSR +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if # Disable IRQ and FIQ +#else + CPSID i # Disable IRQ +#endif +#endif + + RET # Return previous CPSR value + + .type _tx_thread_interrupt_disable,$function + .size _tx_thread_interrupt_disable,.-_tx_thread_interrupt_disable +/* } */ + diff --git a/ports/cortex_a8/green/src/tx_thread_interrupt_restore.arm b/ports/cortex_a8/green/src/tx_thread_interrupt_restore.arm new file mode 100644 index 00000000..b15a4575 --- /dev/null +++ b/ports/cortex_a8/green/src/tx_thread_interrupt_restore.arm @@ -0,0 +1,85 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" */ + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_restore Cortex-A8/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for restoring interrupts to the state */ +/* returned by a previous _tx_thread_interrupt_disable call. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_interrupt_restore(UINT new_posture) +{ */ + .globl _tx_thread_interrupt_restore +_tx_thread_interrupt_restore: + + /* Apply the new interrupt posture. */ + + MSR CPSR_c, r0 # Setup new CPSR + RET + + .type _tx_thread_interrupt_restore,$function + .size _tx_thread_interrupt_restore,.-_tx_thread_interrupt_restore +/* } */ + diff --git a/ports/cortex_a8/green/src/tx_thread_irq_nesting_end.arm b/ports/cortex_a8/green/src/tx_thread_irq_nesting_end.arm new file mode 100644 index 00000000..03b9e389 --- /dev/null +++ b/ports/cortex_a8/green/src/tx_thread_irq_nesting_end.arm @@ -0,0 +1,109 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # Disable IRQ and FIQ interrupts +#else + DISABLE_INTS = 0x80 # Disable IRQ interrupts +#endif + MODE_MASK = 0x1F # Mode mask + IRQ_MODE_BITS = 0x12 # IRQ mode bits + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_irq_nesting_end Cortex-A8/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from IRQ mode after */ +/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +/* processing from system mode back to IRQ mode prior to the ISR */ +/* calling _tx_thread_context_restore. Note that this function */ +/* assumes the system stack pointer is in the same position after */ +/* nesting start function was called. */ +/* */ +/* This function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.arm). */ +/* */ +/* This function returns with IRQ interrupts disabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_irq_nesting_end(VOID) +{ */ + .globl _tx_thread_irq_nesting_end +_tx_thread_irq_nesting_end: + MOV r3,lr # Save ISR return address + MRS r0, CPSR # Pickup the CPSR + ORR r0, r0, DISABLE_INTS # Build disable interrupt value + MSR CPSR_c, r0 # Disable interrupts + LDR lr, [sp] # Pickup saved lr + ADD sp, sp, 4 # Adjust stack pointer + BIC r0, r0, MODE_MASK # Clear mode bits + ORR r0, r0, IRQ_MODE_BITS # Build IRQ mode CPSR + MSR CPSR_c, r0 # Re-enter IRQ mode + MOV pc, r3 # Return to ISR + + .type _tx_thread_irq_nesting_end,$function + .size _tx_thread_irq_nesting_end,.-_tx_thread_irq_nesting_end + +/* } */ + diff --git a/ports/cortex_a8/green/src/tx_thread_irq_nesting_start.arm b/ports/cortex_a8/green/src/tx_thread_irq_nesting_start.arm new file mode 100644 index 00000000..0843df24 --- /dev/null +++ b/ports/cortex_a8/green/src/tx_thread_irq_nesting_start.arm @@ -0,0 +1,102 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + + IRQ_DISABLE = 0x80 # IRQ disable bit + MODE_MASK = 0x1F # Mode mask + SYS_MODE_BITS = 0x1F # System mode bits + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_irq_nesting_start Cortex-A8/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from IRQ mode after */ +/* _tx_thread_context_save has been called and switches the IRQ */ +/* processing to the system mode so nested IRQ interrupt processing */ +/* is possible (system mode has its own "lr" register). Note that */ +/* this function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.arm). */ +/* */ +/* This function returns with IRQ interrupts enabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_irq_nesting_start(VOID) +{ */ + .globl _tx_thread_irq_nesting_start +_tx_thread_irq_nesting_start: + MOV r3,lr # Save ISR return address + MRS r0, CPSR # Pickup the CPSR + BIC r0, r0, MODE_MASK # Clear the mode bits + ORR r0, r0, SYS_MODE_BITS # Build system mode CPSR + MSR CPSR_c, r0 # Enter system mode + STR lr, [sp, -4]! # Push the system mode lr on the system mode stack + BIC r0, r0, IRQ_DISABLE # Build enable IRQ CPSR + MSR CPSR_c, r0 # Enter system mode + MOV pc, r3 # Return to ISR + + .type _tx_thread_irq_nesting_start,$function + .size _tx_thread_irq_nesting_start,.-_tx_thread_irq_nesting_start +/* } */ + diff --git a/ports/cortex_a8/green/src/tx_thread_schedule.arm b/ports/cortex_a8/green/src/tx_thread_schedule.arm new file mode 100644 index 00000000..b3525bb0 --- /dev/null +++ b/ports/cortex_a8/green/src/tx_thread_schedule.arm @@ -0,0 +1,251 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + ENABLE_INTS = 0xC0 # IRQ & FIQ Interrupts enabled mask +#else + ENABLE_INTS = 0x80 # IRQ Interrupts enabled mask +#endif + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule Cortex-A8/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* _tx_thread_context_restore Restore thread's context */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_schedule(VOID) +{ */ + .globl _tx_thread_schedule +_tx_thread_schedule: + + /* Enable interrupts. */ + +#ifdef TX_BEFORE_ARMV6 + MRS r2, CPSR # Pickup CPSR + BIC r0, r2, ENABLE_INTS # Clear the disable bit(s) + MSR CPSR_c, r0 # Enable interrupts +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSIE if # Enable IRQ and FIQ interrupts +#else + CPSIE i # Enable IRQ interrupts +#endif +#endif + + /* Wait for a thread to execute. */ + /* do + { */ + LDR r1, =_tx_thread_execute_ptr # Address of thread execute ptr + +__tx_thread_schedule_loop: + + LDR r0, [r1] # Pickup next thread to execute + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_schedule_loop # If so, keep looking for a thread + + /* } + while(_tx_thread_execute_ptr == TX_NULL); */ + + /* Yes! We have a thread to execute. Lockout interrupts and + transfer control to it. */ + +#ifdef TX_BEFORE_ARMV6 + MSR CPSR_c, r2 # Disable interrupts +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if # Disable IRQ and FIQ interrupts +#else + CPSID i # Disable IRQ interrupts +#endif +#endif + + /* Setup the current thread pointer. */ + /* _tx_thread_current_ptr = _tx_thread_execute_ptr; */ + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV v1, r0 # Save temp register in non-volatile register + BL _tx_el_thread_running # Call event logging routine + MOV r0, v1 # Restore temp register +#endif + + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread + STR r0, [r1] # Setup current thread pointer + + /* Increment the run count for this thread. */ + /* _tx_thread_current_ptr -> tx_thread_run_count++; */ + + LDR r2, [r0, 4] # Pickup run counter + LDR r3, [r0, 24] # Pickup time-slice for this thread + ADD r2, r2, 1 # Increment thread run-counter + STR r2, [r0, 4] # Store the new run counter + + /* Setup time-slice, if present. */ + /* _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; */ + + LDR r2, =_tx_timer_time_slice # Pickup address of time slice + /* # variable */ + LDR sp, [r0, 8] # Switch stack pointers + STR r3, [r2] # Setup time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread entry function to indicate the thread is executing. */ + MOV r5, r0 # Save r0 + BL _tx_execution_thread_enter # Call the thread execution enter function + MOV r0, r5 # Restore r0 +#endif + + /* Switch to the thread's stack. */ + /* sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; */ + + /* Determine if an interrupt frame or a synchronous task suspension frame + is present. */ + + LDMIA sp!, {r4, r5} # Pickup the stack type and saved CPSR + CMP r4, 0 # Check for synchronous context switch + BEQ _tx_solicited_return + MSR SPSR_cxsf, r5 # Setup SPSR for return +#ifdef __VFP__ + LDR r1, [r0, 144] # Pickup the VFP enabled flag + CMP r1, 0 # Is the VFP enabled? + BEQ _tx_skip_interrupt_vfp_restore # No, skip VFP interrupt restore + VLDMIA sp!, {D0-D15} # Recover D0-D15 + VLDMIA sp!, {D16-D31} # Recover D16-D31 + LDR r4, [sp], 4 # Pickup FPSCR + VMSR FPSCR, r4 # Restore FPSCR +_tx_skip_interrupt_vfp_restore: +#endif + LDMIA sp!, {r0-r12, lr, pc}^ # Return to point of thread interrupt + +_tx_solicited_return: +#ifdef __VFP__ + LDR r1, [r0, 144] # Pickup the VFP enabled flag + CMP r1, 0 # Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_restore # No, skip VFP solicited restore + VLDMIA sp!, {D8-D15} # Recover D8-D15 + VLDMIA sp!, {D16-D31} # Recover D16-D31 + LDR r4, [sp], 4 # Pickup FPSCR + VMSR FPSCR, r4 # Restore FPSCR +_tx_skip_solicited_vfp_restore: +#endif + MSR CPSR_cxsf, r5 # Recover CPSR + LDMIA sp!, {r4-r11, lr} # Return to thread synchronously + RET # Return to caller (Thumb safe) + + .type _tx_thread_schedule,$function + .size _tx_thread_schedule,.-_tx_thread_schedule + +#ifdef __VFP__ + .globl tx_thread_vfp_enable +tx_thread_vfp_enable: + MRS r2, CPSR # Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSIE if # Enable IRQ and FIQ interrupts +#else + CPSIE i # Enable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr # Build current thread pointer address + LDR r1, [r0] # Pickup current thread pointer + CMP r1, 0 # Check for NULL thread pointer + BEQ __tx_no_thread_to_enable # If NULL, skip VFP enable + MOV r0, 1 # Build enable value + STR r0, [r1, 144] # Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_enable: + MSR CPSR_cxsf, r2 # Recover CPSR + RET # Return to caller (Thumb safe) + + .type tx_thread_vfp_enable,$function + .size tx_thread_vfp_enable,.-tx_thread_vfp_enable + + + .globl tx_thread_vfp_disable +tx_thread_vfp_disable: + MRS r2, CPSR # Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSIE if # Enable IRQ and FIQ interrupts +#else + CPSIE i # Enable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr # Build current thread pointer address + LDR r1, [r0] # Pickup current thread pointer + CMP r1, 0 # Check for NULL thread pointer + BEQ __tx_no_thread_to_disable # If NULL, skip VFP disable + MOV r0, 0 # Build disable value + STR r0, [r1, 144] # Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_disable: + MSR CPSR_cxsf, r2 # Recover CPSR + RET # Return to caller (Thumb safe) + + .type tx_thread_vfp_disable,$function + .size tx_thread_vfp_disable,.-tx_thread_vfp_disable + +#endif + +/* } */ + diff --git a/ports/cortex_a8/green/src/tx_thread_stack_build.arm b/ports/cortex_a8/green/src/tx_thread_stack_build.arm new file mode 100644 index 00000000..9059e14a --- /dev/null +++ b/ports/cortex_a8/green/src/tx_thread_stack_build.arm @@ -0,0 +1,161 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" */ + + SVC_MODE = 0x13 # SVC mode +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSR_MASK = 0xDF # Mask initial CPSR, IRQ & FIQ ints enabled +#else + CPSR_MASK = 0x9F # Mask initial CPSR, IRQ ints enabled +#endif + + THUMB_BIT = 0x20 # Thumb-bit + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build Cortex-A8/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +{ */ + .globl _tx_thread_stack_build +_tx_thread_stack_build: + + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-A8 should look like the following after it is built: + + Stack Top: 1 Interrupt stack frame type + CPSR Initial value for CPSR + r0 (a1) Initial value for r0 + r1 (a2) Initial value for r1 + r2 (a3) Initial value for r2 + r3 (a4) Initial value for r3 + r4 (v1) Initial value for r4 + r5 (v2) Initial value for r5 + r6 (v3) Initial value for r6 + r7 (v4) Initial value for r7 + r8 (v5) Initial value for r8 + r9 (sb) Initial value for r9 + r10 (sl) Initial value for r10 + r11 (fp) Initial value for r11 + r12 (ip) Initial value for r12 + lr Initial value for lr + pc Initial value for pc + 0 For stack backtracing + + Stack Bottom: (higher memory address) */ + + LDR r2, [r0, 16] # Pickup end of stack area + BIC r2, r2, 7 # Ensure 8-byte alignment + SUB r2, r2, 76 # Allocate space for the stack frame + + /* Actually build the stack frame. */ + + MOV r3, 1 # Build interrupt stack type + STR r3, [r2] # Store stack type + MOV r3, 0 # Build initial register value + STR r3, [r2, 8] # Store initial r0 + STR r3, [r2, 12] # Store initial r1 + STR r3, [r2, 16] # Store initial r2 + STR r3, [r2, 20] # Store initial r3 + STR r3, [r2, 24] # Store initial r4 + STR r3, [r2, 28] # Store initial r5 + STR r3, [r2, 32] # Store initial r6 + STR r3, [r2, 36] # Store initial r7 + STR r3, [r2, 40] # Store initial r8 + STR r3, [r2, 44] # Store initial r9 + LDR r3, [r0, 12] # Pickup stack starting address + STR r3, [r2, 48] # Store initial r10 + MOV r3, 0 # Build initial register value + STR r3, [r2, 52] # Store initial r11 + STR r3, [r2, 56] # Store initial r12 + STR r3, [r2, 60] # Store initial lr + STR r1, [r2, 64] # Store initial pc + STR r3, [r2, 68] # 0 for back-trace + + MRS r3, CPSR # Pickup CPSR + BIC r3, r3, CPSR_MASK # Mask mode bits of CPSR + ORR r3, r3, SVC_MODE # Build CPSR, SVC mode, interrupts enabled + BIC r3, r3, #THUMB_BIT # Clear Thumb-bit by default + AND r1, r1, #1 # Determine if the entry function is in Thumb mode + CMP r1, 1 # Is the Thumb-bit set? + ORREQ r3, r3, #THUMB_BIT # Yes, set the Thumb-bit + STR r3, [r2, 4] # Store initial CPSR + + /* Setup stack pointer. */ + /* thread_ptr -> tx_thread_stack_ptr = r2; */ + + STR r2, [r0, 8] # Save stack pointer in thread's + /* # control block */ + RET # Return to caller + + .type _tx_thread_stack_build,$function + .size _tx_thread_stack_build,.-_tx_thread_stack_build +/* } */ + diff --git a/ports/cortex_a8/green/src/tx_thread_system_return.arm b/ports/cortex_a8/green/src/tx_thread_system_return.arm new file mode 100644 index 00000000..31c10d3f --- /dev/null +++ b/ports/cortex_a8/green/src/tx_thread_system_return.arm @@ -0,0 +1,167 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # IRQ & FIQ interrupts disabled +#else + DISABLE_INTS = 0x80 # IRQ interrupts disabled +#endif + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return Cortex-A8/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the ThreadX system. Only a */ +/* minimal context is saved since the compiler assumes temp registers */ +/* are going to get slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_system_return(VOID) +{ */ + .globl _tx_thread_system_return +_tx_thread_system_return: + + /* Save minimal context on the stack. */ + + MOV r0, 0 # Build a solicited stack type + MRS r1, CPSR # Pickup the CPSR + STMDB sp!, {r4-r11, lr} # Save minimal context + + LDR r4, =_tx_thread_current_ptr # Pickup address of current ptr + LDR r5, [r4] # Pickup current thread pointer + +#ifdef __VFP__ + LDR r1, [r5, 144] # Pickup the VFP enabled flag + CMP r1, 0 # Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_save # No, skip VFP solicited save + VMRS r1, FPSCR # Pickup the FPSCR + STR r1, [sp, -4]! # Save FPSCR + VSTMDB sp!, {D16-D31} # Save D16-D31 + VSTMDB sp!, {D8-D15} # Save D8-D15 +_tx_skip_solicited_vfp_save: +#endif + + MOV r0, #0 # Build a solicited stack type + MRS r1, CPSR # Pickup the CPSR + STMDB sp!, {r0-r1} # Save type and CPSR + + /* Lockout interrupts. */ + +#ifdef TX_BEFORE_ARMV6 + ORR r2, r1, DISABLE_INTS # Build disable interrupt CPSR + MSR CPSR_c, r2 # Disable interrupts +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if # Disable IRQ and FIQ interrupts +#else + CPSID i # Disable IRQ interrutps +#endif +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread exit function to indicate the thread is no longer executing. */ + + BL _tx_execution_thread_exit # Call the thread exit function +#endif + + MOV r3, r4 # Pickup address of current ptr + MOV r0, r5 # Pickup current thread pointer + LDR r2, =_tx_timer_time_slice # Pickup address of time slice + LDR r1, [r2] # Pickup current time slice + + /* Save current stack and switch to system stack. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; + sp = _tx_thread_system_stack_ptr; */ + + STR sp, [r0, 8] # Save thread stack pointer + + /* Determine if the time-slice is active. */ + /* if (_tx_timer_time_slice) + { */ + + MOV r4, 0 # Build clear value + CMP r1, 0 # Is a time-slice active? + BEQ __tx_thread_dont_save_ts # No, don't save the current time-slice + + /* Save time-slice for the thread and clear the current time-slice. */ + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + STR r4, [r2, 0] # Clear time-slice + STR r1, [r0, 24] # Save current time-slice + + /* } */ +__tx_thread_dont_save_ts: + + /* Clear the current thread pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + STR r4, [r3] # Clear current thread pointer + B _tx_thread_schedule # Jump to scheduler! + + .type _tx_thread_system_return,$function + .size _tx_thread_system_return,.-_tx_thread_system_return +/* } */ + diff --git a/ports/cortex_a8/green/src/tx_thread_vectored_context_save.arm b/ports/cortex_a8/green/src/tx_thread_vectored_context_save.arm new file mode 100644 index 00000000..767a238b --- /dev/null +++ b/ports/cortex_a8/green/src/tx_thread_vectored_context_save.arm @@ -0,0 +1,196 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # IRQ & FIQ interrupts disabled +#else + DISABLE_INTS = 0x80 # IRQ interrupts disabled +#endif + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_vectored_context_save Cortex-A8/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_vectored_context_save(VOID) +{ */ + .globl _tx_thread_vectored_context_save +_tx_thread_vectored_context_save: + + /* Upon entry to this routine, it is assumed that IRQ interrupts are locked + out, we are in IRQ mode, the minimal context is already saved, and the + lr register contains the return ISR address. */ + + /* Check for a nested interrupt condition. */ + /* if (_tx_thread_system_state++) + { */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#ifdef TX_BEFORE_ARMV6 + MRS r0, CPSR # Pickup the CPSR + ORR r0, r0, DISABLE_INTS # Build disable interrupt CPSR + MSR CPSR_c, r0 # Disable interrupts +#else + CPSID if # Disable IRQ and FIQ interrupts +#endif +#endif + LDR r3, =_tx_thread_system_state # Pickup address of system state var + LDR r2, [r3] # Pickup system state + CMP r2, 0 # Is this the first interrupt? + BEQ __tx_thread_not_nested_save # Yes, not a nested context save + + /* Nested interrupt condition. */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + + /* Note: Minimal context of interrupted thread is already saved. */ + + /* Return to the ISR. */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + MOV pc, lr # Return to caller + +__tx_thread_not_nested_save: + /* } */ + + /* Otherwise, not nested, check to see if a thread was running. */ + /* else if (_tx_thread_current_ptr) + { */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup current thread pointer + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_idle_system_save # If so, interrupt occurred in + /* # scheduling loop - nothing needs saving! */ + + /* Note: Minimal context of interrupted thread is already saved. */ + + /* Save the current stack pointer in the thread's control block. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ + + /* Switch to the system stack. */ + /* sp = _tx_thread_system_stack_ptr; */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + MOV pc, lr # Return to caller + + /* } + else + { */ + +__tx_thread_idle_system_save: + + /* Interrupt occurred in the scheduling loop. */ + + /* Not much to do here, just adjust the stack pointer, and return to IRQ + processing. */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + ADD sp, sp, 32 # Recover saved registers + MOV pc, lr # Return to caller + + .type _tx_thread_vectored_context_save,$function + .size _tx_thread_vectored_context_save,.-_tx_thread_vectored_context_save + + /* } +} */ + diff --git a/ports/cortex_a8/green/src/tx_timer_interrupt.arm b/ports/cortex_a8/green/src/tx_timer_interrupt.arm new file mode 100644 index 00000000..7021f16b --- /dev/null +++ b/ports/cortex_a8/green/src/tx_timer_interrupt.arm @@ -0,0 +1,241 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_timer.h" + #include "tx_thread.h" */ + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt Cortex-A8/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Process timer expiration */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_timer_interrupt(VOID) +{ */ + .globl _tx_timer_interrupt +_tx_timer_interrupt: + + /* Upon entry to this routine, it is assumed that context save has already + been called, and therefore the compiler scratch registers are available + for use. */ + + /* Increment the system clock. */ + /* _tx_timer_system_clock++; */ + + LDR r1, =_tx_timer_system_clock # Pickup address of system clock + LDR r0, [r1] # Pickup system clock + ADD r0, r0, 1 # Increment system clock + STR r0, [r1] # Store new system clock + + /* Test for time-slice expiration. */ + /* if (_tx_timer_time_slice) + { */ + + LDR r3, =_tx_timer_time_slice # Pickup address of time-slice + LDR r2, [r3] # Pickup time-slice + CMP r2, 0 # Is it non-active? + BEQ __tx_timer_no_time_slice # Yes, skip time-slice processing + + /* Decrement the time_slice. */ + /* _tx_timer_time_slice--; */ + + SUB r2, r2, 1 # Decrement the time-slice + STR r2, [r3] # Store new time-slice value + + /* Check for expiration. */ + /* if (__tx_timer_time_slice == 0) */ + + CMP r2, 0 # Has it expired? + BNE __tx_timer_no_time_slice # No, skip expiration processing + + /* Set the time-slice expired flag. */ + /* _tx_timer_expired_time_slice = TX_TRUE; */ + + LDR r3,=_tx_timer_expired_time_slice # Pickup address of expired flag + MOV r0, 1 # Build expired value + STR r0, [r3] # Set time-slice expiration flag + + /* } */ + +__tx_timer_no_time_slice: + + /* Test for timer expiration. */ + /* if (*_tx_timer_current_ptr) + { */ + + LDR r1, =_tx_timer_current_ptr # Pickup current timer pointer addr + LDR r0, [r1] # Pickup current timer + LDR r2, [r0] # Pickup timer list entry + CMP r2, 0 # Is there anything in the list? + BEQ __tx_timer_no_timer # No, just increment the timer + + /* Set expiration flag. */ + /* _tx_timer_expired = TX_TRUE; */ + + LDR r3, =_tx_timer_expired # Pickup expiration flag address + MOV r2, 1 # Build expired value + STR r2, [r3] # Set expired flag + B __tx_timer_done # Finished timer processing + + /* } + else + { */ +__tx_timer_no_timer: + + /* No timer expired, increment the timer pointer. */ + /* _tx_timer_current_ptr++; */ + + ADD r0, r0, 4 # Move to next timer + + /* Check for wrap-around. */ + /* if (_tx_timer_current_ptr == _tx_timer_list_end) */ + + LDR r3, =_tx_timer_list_end # Pickup addr of timer list end + LDR r2, [r3] # Pickup list end + CMP r0, r2 # Are we at list end? + BNE __tx_timer_skip_wrap # No, skip wrap-around logic + + /* Wrap to beginning of list. */ + /* _tx_timer_current_ptr = _tx_timer_list_start; */ + + LDR r3, =_tx_timer_list_start # Pickup addr of timer list start + LDR r0, [r3] # Set current pointer to list start + +__tx_timer_skip_wrap: + + STR r0, [r1] # Store new current timer pointer + /* } */ + +__tx_timer_done: + + + /* See if anything has expired. */ + /* if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) + { */ + + LDR r3, =_tx_timer_expired_time_slice # Pickup addr of expired flag + LDR r2, [r3] # Pickup time-slice expired flag + CMP r2, 0 # Did a time-slice expire? + BNE __tx_something_expired # If non-zero, time-slice expired + LDR r1, =_tx_timer_expired # Pickup addr of other expired flag + LDR r0, [r1] # Pickup timer expired flag + CMP r0, 0 # Did a timer expire? + BEQ __tx_timer_nothing_expired # No, nothing expired + +__tx_something_expired: + + + STMDB sp!, {r0, lr} # Save the lr register on the stack + /* # and save r0 just to keep 8-byte alignment */ + + /* Did a timer expire? */ + /* if (_tx_timer_expired) + { */ + + LDR r1, =_tx_timer_expired # Pickup addr of expired flag + LDR r0, [r1] # Pickup timer expired flag + CMP r0, 0 # Check for timer expiration + BEQ __tx_timer_dont_activate # If not set, skip timer activation + + /* Process the timer expiration. */ + /* _tx_timer_expiration_process(); */ + BL _tx_timer_expiration_process # Call the timer expiration handling routine + + /* } */ +__tx_timer_dont_activate: + + /* Did time slice expire? */ + /* if (_tx_timer_expired_time_slice) + { */ + + LDR r3, =_tx_timer_expired_time_slice # Pickup addr of time-slice expired + LDR r2, [r3] # Pickup the actual flag + CMP r2, 0 # See if the flag is set + BEQ __tx_timer_not_ts_expiration # No, skip time-slice processing + + /* Time slice interrupted thread. */ + /* _tx_thread_time_slice(); */ + + BL _tx_thread_time_slice # Call time-slice processing + + /* } */ +__tx_timer_not_ts_expiration: + + + LDMIA sp!, {r0, lr} # Recover lr register (r0 is just there for + /* # the 8-byte stack alignment */ + + /* } */ + +__tx_timer_nothing_expired: + + RET # Return to caller + + .type _tx_timer_interrupt,$function + .size _tx_timer_interrupt,.-_tx_timer_interrupt +/* } */ + diff --git a/ports/cortex_a8/iar/example_build/tx_initialize_low_level.s b/ports/cortex_a8/iar/example_build/tx_initialize_low_level.s index 5dce3ab5..9699610a 100644 --- a/ports/cortex_a8/iar/example_build/tx_initialize_low_level.s +++ b/ports/cortex_a8/iar/example_build/tx_initialize_low_level.s @@ -81,7 +81,7 @@ __tx_free_memory_start ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level Cortex-A8/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -114,7 +114,7 @@ __tx_free_memory_start ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_a8/iar/inc/tx_port.h b/ports/cortex_a8/iar/inc/tx_port.h index 3ff8ef9b..58c88d26 100644 --- a/ports/cortex_a8/iar/inc/tx_port.h +++ b/ports/cortex_a8/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A8/IAR */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -381,7 +381,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A8/IAR Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A8/IAR Version 6.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_a8/iar/readme_threadx.txt b/ports/cortex_a8/iar/readme_threadx.txt index e46fdee8..3f380c85 100644 --- a/ports/cortex_a8/iar/readme_threadx.txt +++ b/ports/cortex_a8/iar/readme_threadx.txt @@ -534,7 +534,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX version 6.0.1 for Cortex-A8 using IAR's ARM tools. +09-30-2020 Initial ThreadX version 6.1 for Cortex-A8 using IAR's ARM tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_a8/iar/src/tx_thread_context_restore.s b/ports/cortex_a8/iar/src/tx_thread_context_restore.s index 4a66c503..80ef5a89 100644 --- a/ports/cortex_a8/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_a8/iar/src/tx_thread_context_restore.s @@ -57,7 +57,7 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore Cortex-A8/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -89,7 +89,7 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_a8/iar/src/tx_thread_context_save.s b/ports/cortex_a8/iar/src/tx_thread_context_save.s index 0d4256ea..78f09a95 100644 --- a/ports/cortex_a8/iar/src/tx_thread_context_save.s +++ b/ports/cortex_a8/iar/src/tx_thread_context_save.s @@ -49,7 +49,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save Cortex-A8/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -80,7 +80,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_a8/iar/src/tx_thread_fiq_context_restore.s b/ports/cortex_a8/iar/src/tx_thread_fiq_context_restore.s index 3036be83..6c806079 100644 --- a/ports/cortex_a8/iar/src/tx_thread_fiq_context_restore.s +++ b/ports/cortex_a8/iar/src/tx_thread_fiq_context_restore.s @@ -58,7 +58,7 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_context_restore Cortex-A8/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -90,7 +90,7 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_context_restore(VOID) diff --git a/ports/cortex_a8/iar/src/tx_thread_fiq_context_save.s b/ports/cortex_a8/iar/src/tx_thread_fiq_context_save.s index fb54ea4c..4a61a974 100644 --- a/ports/cortex_a8/iar/src/tx_thread_fiq_context_save.s +++ b/ports/cortex_a8/iar/src/tx_thread_fiq_context_save.s @@ -42,7 +42,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_context_save Cortex-A8/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -73,7 +73,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ; VOID _tx_thread_fiq_context_save(VOID) diff --git a/ports/cortex_a8/iar/src/tx_thread_fiq_nesting_end.s b/ports/cortex_a8/iar/src/tx_thread_fiq_nesting_end.s index cc8bb560..33c793cc 100644 --- a/ports/cortex_a8/iar/src/tx_thread_fiq_nesting_end.s +++ b/ports/cortex_a8/iar/src/tx_thread_fiq_nesting_end.s @@ -44,7 +44,7 @@ FIQ_MODE_BITS DEFINE 0x11 ; FIQ mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_nesting_end Cortex-A8/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -83,7 +83,7 @@ FIQ_MODE_BITS DEFINE 0x11 ; FIQ mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_end(VOID) diff --git a/ports/cortex_a8/iar/src/tx_thread_fiq_nesting_start.s b/ports/cortex_a8/iar/src/tx_thread_fiq_nesting_start.s index 7d1ef512..5e3915cd 100644 --- a/ports/cortex_a8/iar/src/tx_thread_fiq_nesting_start.s +++ b/ports/cortex_a8/iar/src/tx_thread_fiq_nesting_start.s @@ -41,7 +41,7 @@ SYS_MODE_BITS DEFINE 0x1F ; System mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_nesting_start Cortex-A8/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ SYS_MODE_BITS DEFINE 0x1F ; System mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/cortex_a8/iar/src/tx_thread_interrupt_control.s b/ports/cortex_a8/iar/src/tx_thread_interrupt_control.s index 4a409e4b..45a31830 100644 --- a/ports/cortex_a8/iar/src/tx_thread_interrupt_control.s +++ b/ports/cortex_a8/iar/src/tx_thread_interrupt_control.s @@ -41,7 +41,7 @@ INT_MASK DEFINE 0x80 ; Interrupt bit mask ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control Cortex-A8/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ INT_MASK DEFINE 0x80 ; Interrupt bit mask ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a8/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_a8/iar/src/tx_thread_interrupt_disable.s index 552ebed1..146c34b9 100644 --- a/ports/cortex_a8/iar/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_a8/iar/src/tx_thread_interrupt_disable.s @@ -42,7 +42,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_disable Cortex-A8/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports/cortex_a8/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_a8/iar/src/tx_thread_interrupt_restore.s index 7d0750c1..28f6226d 100644 --- a/ports/cortex_a8/iar/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_a8/iar/src/tx_thread_interrupt_restore.s @@ -34,7 +34,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-A8/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -64,7 +64,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;void _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a8/iar/src/tx_thread_irq_nesting_end.s b/ports/cortex_a8/iar/src/tx_thread_irq_nesting_end.s index 6da2fdcb..a207f14e 100644 --- a/ports/cortex_a8/iar/src/tx_thread_irq_nesting_end.s +++ b/ports/cortex_a8/iar/src/tx_thread_irq_nesting_end.s @@ -45,7 +45,7 @@ IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_irq_nesting_end Cortex-A8/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -84,7 +84,7 @@ IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports/cortex_a8/iar/src/tx_thread_irq_nesting_start.s b/ports/cortex_a8/iar/src/tx_thread_irq_nesting_start.s index 8d9efeff..b4bff315 100644 --- a/ports/cortex_a8/iar/src/tx_thread_irq_nesting_start.s +++ b/ports/cortex_a8/iar/src/tx_thread_irq_nesting_start.s @@ -41,7 +41,7 @@ SYS_MODE_BITS DEFINE 0x1F ; System mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_irq_nesting_start Cortex-A8/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ SYS_MODE_BITS DEFINE 0x1F ; System mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_a8/iar/src/tx_thread_schedule.s b/ports/cortex_a8/iar/src/tx_thread_schedule.s index 865fb9dd..5da963c5 100644 --- a/ports/cortex_a8/iar/src/tx_thread_schedule.s +++ b/ports/cortex_a8/iar/src/tx_thread_schedule.s @@ -49,7 +49,7 @@ ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-A8/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_a8/iar/src/tx_thread_stack_build.s b/ports/cortex_a8/iar/src/tx_thread_stack_build.s index f5f4da77..2d7c66e7 100644 --- a/ports/cortex_a8/iar/src/tx_thread_stack_build.s +++ b/ports/cortex_a8/iar/src/tx_thread_stack_build.s @@ -43,7 +43,7 @@ CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints en ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build Cortex-A8/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -75,7 +75,7 @@ CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints en ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_a8/iar/src/tx_thread_system_return.s b/ports/cortex_a8/iar/src/tx_thread_system_return.s index 814bc727..474b778f 100644 --- a/ports/cortex_a8/iar/src/tx_thread_system_return.s +++ b/ports/cortex_a8/iar/src/tx_thread_system_return.s @@ -48,7 +48,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return Cortex-A8/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -80,7 +80,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_a8/iar/src/tx_thread_vectored_context_save.s b/ports/cortex_a8/iar/src/tx_thread_vectored_context_save.s index efd958c2..2cc6ab17 100644 --- a/ports/cortex_a8/iar/src/tx_thread_vectored_context_save.s +++ b/ports/cortex_a8/iar/src/tx_thread_vectored_context_save.s @@ -47,7 +47,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_vectored_context_save Cortex-A8/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -78,7 +78,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) diff --git a/ports/cortex_a8/iar/src/tx_timer_interrupt.s b/ports/cortex_a8/iar/src/tx_timer_interrupt.s index d7a98738..4d2caab1 100644 --- a/ports/cortex_a8/iar/src/tx_timer_interrupt.s +++ b/ports/cortex_a8/iar/src/tx_timer_interrupt.s @@ -49,7 +49,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt Cortex-A8/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -83,7 +83,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_a9/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_a9/ac5/example_build/tx_initialize_low_level.s index 4bec5bf9..37a8dd2a 100644 --- a/ports/cortex_a9/ac5/example_build/tx_initialize_low_level.s +++ b/ports/cortex_a9/ac5/example_build/tx_initialize_low_level.s @@ -116,7 +116,7 @@ Reset_Vector ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level Cortex-A9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -149,7 +149,7 @@ Reset_Vector ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_a9/ac5/inc/tx_port.h b/ports/cortex_a9/ac5/inc/tx_port.h index bc92b621..b14def8c 100644 --- a/ports/cortex_a9/ac5/inc/tx_port.h +++ b/ports/cortex_a9/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A9/AC5 */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -324,7 +324,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A9/AC5 Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A9/AC5 Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a9/ac5/readme_threadx.txt b/ports/cortex_a9/ac5/readme_threadx.txt index b05b8f73..68fdde1c 100644 --- a/ports/cortex_a9/ac5/readme_threadx.txt +++ b/ports/cortex_a9/ac5/readme_threadx.txt @@ -535,7 +535,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A9 using AC5 tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-A9 using AC5 tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_a9/ac5/src/tx_thread_context_restore.s b/ports/cortex_a9/ac5/src/tx_thread_context_restore.s index 5c5259a7..da09cb49 100644 --- a/ports/cortex_a9/ac5/src/tx_thread_context_restore.s +++ b/ports/cortex_a9/ac5/src/tx_thread_context_restore.s @@ -60,7 +60,7 @@ SVC_MODE EQU 0x93 ; SVC mode ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore Cortex-A9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -92,7 +92,7 @@ SVC_MODE EQU 0x93 ; SVC mode ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_a9/ac5/src/tx_thread_context_save.s b/ports/cortex_a9/ac5/src/tx_thread_context_save.s index ec7710aa..6714df37 100644 --- a/ports/cortex_a9/ac5/src/tx_thread_context_save.s +++ b/ports/cortex_a9/ac5/src/tx_thread_context_save.s @@ -45,7 +45,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save Cortex-A9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -76,7 +76,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_a9/ac5/src/tx_thread_fiq_context_restore.s b/ports/cortex_a9/ac5/src/tx_thread_fiq_context_restore.s index a5484af5..3826b296 100644 --- a/ports/cortex_a9/ac5/src/tx_thread_fiq_context_restore.s +++ b/ports/cortex_a9/ac5/src/tx_thread_fiq_context_restore.s @@ -56,7 +56,7 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_context_restore Cortex-A9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -88,7 +88,7 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_context_restore(VOID) diff --git a/ports/cortex_a9/ac5/src/tx_thread_fiq_context_save.s b/ports/cortex_a9/ac5/src/tx_thread_fiq_context_save.s index 371ac248..1d614bce 100644 --- a/ports/cortex_a9/ac5/src/tx_thread_fiq_context_save.s +++ b/ports/cortex_a9/ac5/src/tx_thread_fiq_context_save.s @@ -45,7 +45,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_context_save Cortex-A9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -76,7 +76,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ; VOID _tx_thread_fiq_context_save(VOID) diff --git a/ports/cortex_a9/ac5/src/tx_thread_fiq_nesting_end.s b/ports/cortex_a9/ac5/src/tx_thread_fiq_nesting_end.s index a3b20759..643e089f 100644 --- a/ports/cortex_a9/ac5/src/tx_thread_fiq_nesting_end.s +++ b/ports/cortex_a9/ac5/src/tx_thread_fiq_nesting_end.s @@ -45,7 +45,7 @@ FIQ_MODE_BITS EQU 0x11 ; FIQ mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_nesting_end Cortex-A9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -84,7 +84,7 @@ FIQ_MODE_BITS EQU 0x11 ; FIQ mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_end(VOID) diff --git a/ports/cortex_a9/ac5/src/tx_thread_fiq_nesting_start.s b/ports/cortex_a9/ac5/src/tx_thread_fiq_nesting_start.s index 221258d5..5a9d5791 100644 --- a/ports/cortex_a9/ac5/src/tx_thread_fiq_nesting_start.s +++ b/ports/cortex_a9/ac5/src/tx_thread_fiq_nesting_start.s @@ -41,7 +41,7 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_nesting_start Cortex-A9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/cortex_a9/ac5/src/tx_thread_interrupt_control.s b/ports/cortex_a9/ac5/src/tx_thread_interrupt_control.s index 4c4a7c38..69bb538a 100644 --- a/ports/cortex_a9/ac5/src/tx_thread_interrupt_control.s +++ b/ports/cortex_a9/ac5/src/tx_thread_interrupt_control.s @@ -42,7 +42,7 @@ INT_MASK EQU 0x80 ; Interrupt bit mask ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control Cortex-A9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ INT_MASK EQU 0x80 ; Interrupt bit mask ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a9/ac5/src/tx_thread_interrupt_disable.s b/ports/cortex_a9/ac5/src/tx_thread_interrupt_disable.s index c15f0bdf..56c0163e 100644 --- a/ports/cortex_a9/ac5/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_a9/ac5/src/tx_thread_interrupt_disable.s @@ -35,7 +35,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_disable Cortex-A9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -64,7 +64,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(void) diff --git a/ports/cortex_a9/ac5/src/tx_thread_interrupt_restore.s b/ports/cortex_a9/ac5/src/tx_thread_interrupt_restore.s index 955544e7..259979c7 100644 --- a/ports/cortex_a9/ac5/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_a9/ac5/src/tx_thread_interrupt_restore.s @@ -35,7 +35,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-A9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -65,7 +65,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a9/ac5/src/tx_thread_irq_nesting_end.s b/ports/cortex_a9/ac5/src/tx_thread_irq_nesting_end.s index 7b91c316..e740ac6c 100644 --- a/ports/cortex_a9/ac5/src/tx_thread_irq_nesting_end.s +++ b/ports/cortex_a9/ac5/src/tx_thread_irq_nesting_end.s @@ -45,7 +45,7 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_irq_nesting_end Cortex-A9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -84,7 +84,7 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports/cortex_a9/ac5/src/tx_thread_irq_nesting_start.s b/ports/cortex_a9/ac5/src/tx_thread_irq_nesting_start.s index d1a25514..4279a4c4 100644 --- a/ports/cortex_a9/ac5/src/tx_thread_irq_nesting_start.s +++ b/ports/cortex_a9/ac5/src/tx_thread_irq_nesting_start.s @@ -41,7 +41,7 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_irq_nesting_start Cortex-A9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_a9/ac5/src/tx_thread_schedule.s b/ports/cortex_a9/ac5/src/tx_thread_schedule.s index 10bbe36a..ace85a3d 100644 --- a/ports/cortex_a9/ac5/src/tx_thread_schedule.s +++ b/ports/cortex_a9/ac5/src/tx_thread_schedule.s @@ -46,7 +46,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-A9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -79,7 +79,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_a9/ac5/src/tx_thread_stack_build.s b/ports/cortex_a9/ac5/src/tx_thread_stack_build.s index 0364ba18..02055ea6 100644 --- a/ports/cortex_a9/ac5/src/tx_thread_stack_build.s +++ b/ports/cortex_a9/ac5/src/tx_thread_stack_build.s @@ -47,7 +47,7 @@ THUMB_BIT EQU 0x20 ; Thumb-bit ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build Cortex-A9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -79,7 +79,7 @@ THUMB_BIT EQU 0x20 ; Thumb-bit ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_a9/ac5/src/tx_thread_system_return.s b/ports/cortex_a9/ac5/src/tx_thread_system_return.s index c4ae7a15..3b228404 100644 --- a/ports/cortex_a9/ac5/src/tx_thread_system_return.s +++ b/ports/cortex_a9/ac5/src/tx_thread_system_return.s @@ -45,7 +45,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return Cortex-A9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_a9/ac5/src/tx_thread_vectored_context_save.s b/ports/cortex_a9/ac5/src/tx_thread_vectored_context_save.s index c74480a5..d49dbd07 100644 --- a/ports/cortex_a9/ac5/src/tx_thread_vectored_context_save.s +++ b/ports/cortex_a9/ac5/src/tx_thread_vectored_context_save.s @@ -44,7 +44,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_vectored_context_save Cortex-A9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -75,7 +75,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) diff --git a/ports/cortex_a9/ac5/src/tx_timer_interrupt.s b/ports/cortex_a9/ac5/src/tx_timer_interrupt.s index 1fdec243..1900335f 100644 --- a/ports/cortex_a9/ac5/src/tx_timer_interrupt.s +++ b/ports/cortex_a9/ac5/src/tx_timer_interrupt.s @@ -50,7 +50,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt Cortex-A9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -84,7 +84,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_a9/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_a9/ac6/example_build/sample_threadx/tx_initialize_low_level.S index b7a3ef98..e3907d1e 100644 --- a/ports/cortex_a9/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports/cortex_a9/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -75,7 +75,7 @@ $_tx_initialize_low_level: @/* FUNCTION RELEASE */ @/* */ @/* _tx_initialize_low_level Cortex-A9/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -108,7 +108,7 @@ $_tx_initialize_low_level: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_a9/ac6/inc/tx_port.h b/ports/cortex_a9/ac6/inc/tx_port.h index 94990c28..bc54c159 100644 --- a/ports/cortex_a9/ac6/inc/tx_port.h +++ b/ports/cortex_a9/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A9/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -313,7 +313,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A9/AC6 Version 6.0.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A9/AC6 Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a9/ac6/readme_threadx.txt b/ports/cortex_a9/ac6/readme_threadx.txt index 1360697d..ab150408 100644 --- a/ports/cortex_a9/ac6/readme_threadx.txt +++ b/ports/cortex_a9/ac6/readme_threadx.txt @@ -332,7 +332,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A9 using AC6 tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-A9 using AC6 tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_a9/ac6/src/tx_thread_context_restore.S b/ports/cortex_a9/ac6/src/tx_thread_context_restore.S index b710b81c..d1406509 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_a9/ac6/src/tx_thread_context_restore.S @@ -59,7 +59,7 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_restore Cortex-A9/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -91,7 +91,7 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_a9/ac6/src/tx_thread_context_save.S b/ports/cortex_a9/ac6/src/tx_thread_context_save.S index 112b0961..5d49dae8 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_a9/ac6/src/tx_thread_context_save.S @@ -47,7 +47,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_save Cortex-A9/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -78,7 +78,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_a9/ac6/src/tx_thread_fiq_context_restore.S b/ports/cortex_a9/ac6/src/tx_thread_fiq_context_restore.S index 36d0e349..371e3c88 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_a9/ac6/src/tx_thread_fiq_context_restore.S @@ -58,7 +58,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_context_restore Cortex-A9/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -90,7 +90,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_context_restore(VOID) diff --git a/ports/cortex_a9/ac6/src/tx_thread_fiq_context_save.S b/ports/cortex_a9/ac6/src/tx_thread_fiq_context_save.S index 0798ff9b..819a35c0 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_a9/ac6/src/tx_thread_fiq_context_save.S @@ -46,7 +46,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_context_save Cortex-A9/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @ VOID _tx_thread_fiq_context_save(VOID) diff --git a/ports/cortex_a9/ac6/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a9/ac6/src/tx_thread_fiq_nesting_end.S index c5f1913d..ecf2db8e 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a9/ac6/src/tx_thread_fiq_nesting_end.S @@ -50,7 +50,7 @@ FIQ_MODE_BITS = 0x11 @ FIQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_nesting_end Cortex-A9/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -89,7 +89,7 @@ FIQ_MODE_BITS = 0x11 @ FIQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_end(VOID) diff --git a/ports/cortex_a9/ac6/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a9/ac6/src/tx_thread_fiq_nesting_start.S index 51153ce4..f042af5d 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a9/ac6/src/tx_thread_fiq_nesting_start.S @@ -46,7 +46,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_nesting_start Cortex-A9/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/cortex_a9/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a9/ac6/src/tx_thread_interrupt_control.S index 95eab866..a6ac989c 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a9/ac6/src/tx_thread_interrupt_control.S @@ -56,7 +56,7 @@ $_tx_thread_interrupt_control: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_control Cortex-A9/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -86,7 +86,7 @@ $_tx_thread_interrupt_control: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a9/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a9/ac6/src/tx_thread_interrupt_disable.S index 2e2e6268..2b0f0840 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a9/ac6/src/tx_thread_interrupt_disable.S @@ -53,7 +53,7 @@ $_tx_thread_interrupt_disable: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_disable Cortex-A9/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ $_tx_thread_interrupt_disable: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_disable(void) diff --git a/ports/cortex_a9/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a9/ac6/src/tx_thread_interrupt_restore.S index dcc6ccfd..3793925d 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a9/ac6/src/tx_thread_interrupt_restore.S @@ -53,7 +53,7 @@ $_tx_thread_interrupt_restore: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_restore Cortex-A9/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -83,7 +83,7 @@ $_tx_thread_interrupt_restore: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a9/ac6/src/tx_thread_irq_nesting_end.S b/ports/cortex_a9/ac6/src/tx_thread_irq_nesting_end.S index 5c9a6fea..b66fa3ca 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a9/ac6/src/tx_thread_irq_nesting_end.S @@ -50,7 +50,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_irq_nesting_end Cortex-A9/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -89,7 +89,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports/cortex_a9/ac6/src/tx_thread_irq_nesting_start.S b/ports/cortex_a9/ac6/src/tx_thread_irq_nesting_start.S index 19b76019..e864d867 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a9/ac6/src/tx_thread_irq_nesting_start.S @@ -46,7 +46,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_irq_nesting_start Cortex-A9/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_a9/ac6/src/tx_thread_schedule.S b/ports/cortex_a9/ac6/src/tx_thread_schedule.S index c3f6e260..b8ad6c0d 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_a9/ac6/src/tx_thread_schedule.S @@ -61,7 +61,7 @@ $_tx_thread_schedule: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule Cortex-A9/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -94,7 +94,7 @@ $_tx_thread_schedule: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_a9/ac6/src/tx_thread_stack_build.S b/ports/cortex_a9/ac6/src/tx_thread_stack_build.S index 226a6586..3adf5080 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_a9/ac6/src/tx_thread_stack_build.S @@ -64,7 +64,7 @@ $_tx_thread_stack_build: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_stack_build Cortex-A9/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -96,7 +96,7 @@ $_tx_thread_stack_build: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_a9/ac6/src/tx_thread_system_return.S b/ports/cortex_a9/ac6/src/tx_thread_system_return.S index 1b7bb949..818fe348 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_a9/ac6/src/tx_thread_system_return.S @@ -63,7 +63,7 @@ $_tx_thread_system_return: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_system_return Cortex-A9/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -95,7 +95,7 @@ $_tx_thread_system_return: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_a9/ac6/src/tx_thread_vectored_context_save.S b/ports/cortex_a9/ac6/src/tx_thread_vectored_context_save.S index bc52d3ff..f3d01d9b 100644 --- a/ports/cortex_a9/ac6/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_a9/ac6/src/tx_thread_vectored_context_save.S @@ -46,7 +46,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_vectored_context_save Cortex-A9/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_vectored_context_save(VOID) diff --git a/ports/cortex_a9/ac6/src/tx_timer_interrupt.S b/ports/cortex_a9/ac6/src/tx_timer_interrupt.S index 06659120..fa28e728 100644 --- a/ports/cortex_a9/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_a9/ac6/src/tx_timer_interrupt.S @@ -71,7 +71,7 @@ $_tx_timer_interrupt: @/* FUNCTION RELEASE */ @/* */ @/* _tx_timer_interrupt Cortex-A9/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -105,7 +105,7 @@ $_tx_timer_interrupt: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_a9/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_a9/gnu/example_build/tx_initialize_low_level.S index 4f77c8ad..2e274666 100644 --- a/ports/cortex_a9/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_a9/gnu/example_build/tx_initialize_low_level.S @@ -78,7 +78,7 @@ $_tx_initialize_low_level: @/* FUNCTION RELEASE */ @/* */ @/* _tx_initialize_low_level Cortex-A9/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -111,7 +111,7 @@ $_tx_initialize_low_level: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_a9/gnu/inc/tx_port.h b/ports/cortex_a9/gnu/inc/tx_port.h index 9e519bbc..a9652aad 100644 --- a/ports/cortex_a9/gnu/inc/tx_port.h +++ b/ports/cortex_a9/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A9/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -313,7 +313,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A9/GNU Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A9/GNU Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a9/gnu/readme_threadx.txt b/ports/cortex_a9/gnu/readme_threadx.txt index 684e996f..c1b02ff8 100644 --- a/ports/cortex_a9/gnu/readme_threadx.txt +++ b/ports/cortex_a9/gnu/readme_threadx.txt @@ -503,7 +503,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A9 using GNU tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-A9 using GNU tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_a9/gnu/src/tx_thread_context_restore.S b/ports/cortex_a9/gnu/src/tx_thread_context_restore.S index 3e85f010..0fd00e50 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_a9/gnu/src/tx_thread_context_restore.S @@ -60,7 +60,7 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_restore Cortex-A9/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -92,7 +92,7 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_a9/gnu/src/tx_thread_context_save.S b/ports/cortex_a9/gnu/src/tx_thread_context_save.S index 59370609..35b2febc 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_a9/gnu/src/tx_thread_context_save.S @@ -48,7 +48,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_save Cortex-A9/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -79,7 +79,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_a9/gnu/src/tx_thread_fiq_context_restore.S b/ports/cortex_a9/gnu/src/tx_thread_fiq_context_restore.S index 2aa3606b..8c1cbadc 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_a9/gnu/src/tx_thread_fiq_context_restore.S @@ -59,7 +59,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_context_restore Cortex-A9/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -91,7 +91,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_context_restore(VOID) diff --git a/ports/cortex_a9/gnu/src/tx_thread_fiq_context_save.S b/ports/cortex_a9/gnu/src/tx_thread_fiq_context_save.S index 970ddfd0..a82d6945 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_a9/gnu/src/tx_thread_fiq_context_save.S @@ -47,7 +47,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_context_save Cortex-A9/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -78,7 +78,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @ VOID _tx_thread_fiq_context_save(VOID) diff --git a/ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_end.S index a9e545bc..db32cf5b 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_end.S @@ -50,7 +50,7 @@ FIQ_MODE_BITS = 0x11 @ FIQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_nesting_end Cortex-A9/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -89,7 +89,7 @@ FIQ_MODE_BITS = 0x11 @ FIQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_end(VOID) diff --git a/ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_start.S index 85bbbb41..6cb88686 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_start.S @@ -46,7 +46,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_nesting_start Cortex-A9/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/cortex_a9/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a9/gnu/src/tx_thread_interrupt_control.S index 54557d55..ac645d47 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_a9/gnu/src/tx_thread_interrupt_control.S @@ -56,7 +56,7 @@ $_tx_thread_interrupt_control: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_control Cortex-A9/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -86,7 +86,7 @@ $_tx_thread_interrupt_control: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a9/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a9/gnu/src/tx_thread_interrupt_disable.S index 3f6b5de5..b7fa0185 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_a9/gnu/src/tx_thread_interrupt_disable.S @@ -53,7 +53,7 @@ $_tx_thread_interrupt_disable: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_disable Cortex-A9/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ $_tx_thread_interrupt_disable: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_disable(void) diff --git a/ports/cortex_a9/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a9/gnu/src/tx_thread_interrupt_restore.S index b4469688..e88e6090 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_a9/gnu/src/tx_thread_interrupt_restore.S @@ -53,7 +53,7 @@ $_tx_thread_interrupt_restore: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_restore Cortex-A9/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -83,7 +83,7 @@ $_tx_thread_interrupt_restore: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a9/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_a9/gnu/src/tx_thread_irq_nesting_end.S index 955667ca..30e601cb 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_a9/gnu/src/tx_thread_irq_nesting_end.S @@ -50,7 +50,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_irq_nesting_end Cortex-A9/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -89,7 +89,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports/cortex_a9/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_a9/gnu/src/tx_thread_irq_nesting_start.S index 65a24d7f..a13f73cb 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_a9/gnu/src/tx_thread_irq_nesting_start.S @@ -46,7 +46,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_irq_nesting_start Cortex-A9/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_a9/gnu/src/tx_thread_schedule.S b/ports/cortex_a9/gnu/src/tx_thread_schedule.S index 78d18a2e..2daa8004 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_a9/gnu/src/tx_thread_schedule.S @@ -62,7 +62,7 @@ $_tx_thread_schedule: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule Cortex-A9/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -95,7 +95,7 @@ $_tx_thread_schedule: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_a9/gnu/src/tx_thread_stack_build.S b/ports/cortex_a9/gnu/src/tx_thread_stack_build.S index e4724f6e..5bb2c09f 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_a9/gnu/src/tx_thread_stack_build.S @@ -64,7 +64,7 @@ $_tx_thread_stack_build: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_stack_build Cortex-A9/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -96,7 +96,7 @@ $_tx_thread_stack_build: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_a9/gnu/src/tx_thread_system_return.S b/ports/cortex_a9/gnu/src/tx_thread_system_return.S index c7123974..65831549 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_a9/gnu/src/tx_thread_system_return.S @@ -64,7 +64,7 @@ $_tx_thread_system_return: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_system_return Cortex-A9/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -96,7 +96,7 @@ $_tx_thread_system_return: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_a9/gnu/src/tx_thread_vectored_context_save.S b/ports/cortex_a9/gnu/src/tx_thread_vectored_context_save.S index 7c588776..41a1a8b4 100644 --- a/ports/cortex_a9/gnu/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_a9/gnu/src/tx_thread_vectored_context_save.S @@ -47,7 +47,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_vectored_context_save Cortex-A9/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -78,7 +78,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_vectored_context_save(VOID) diff --git a/ports/cortex_a9/gnu/src/tx_timer_interrupt.S b/ports/cortex_a9/gnu/src/tx_timer_interrupt.S index 00512a4d..92365206 100644 --- a/ports/cortex_a9/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_a9/gnu/src/tx_timer_interrupt.S @@ -71,7 +71,7 @@ $_tx_timer_interrupt: @/* FUNCTION RELEASE */ @/* */ @/* _tx_timer_interrupt Cortex-A9/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -105,7 +105,7 @@ $_tx_timer_interrupt: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_a9/green/example_build/azure_rtos_workspace.gpj b/ports/cortex_a9/green/example_build/azure_rtos_workspace.gpj new file mode 100644 index 00000000..5a87a744 --- /dev/null +++ b/ports/cortex_a9/green/example_build/azure_rtos_workspace.gpj @@ -0,0 +1,12 @@ +#!gbuild +primaryTarget=arm_standalone.tgt +[Project] + -bsp generic + -G + -cpu=cortexa9 + -littleendian +sample_threadx.gpj [Program] +sample_threadx_el.gpj [Program] +tx.gpj [Library] +txe.gpj [Library] +..\readme_threadx.txt diff --git a/ports/cortex_a9/green/example_build/reset.arm b/ports/cortex_a9/green/example_build/reset.arm new file mode 100644 index 00000000..f4d4edea --- /dev/null +++ b/ports/cortex_a9/green/example_build/reset.arm @@ -0,0 +1,45 @@ +# +# +#/* Define the Cortex-A9 vector area. This should be located or copied to 0. */ +# + + .section ".reset", .text + .globl __vectors +__vectors: + B __entry # Reset goes to the entry function + LDR pc,UNDEFINED # Undefined handler + LDR pc,SWI # Software interrupt handler + LDR pc,PREFETCH # Prefetch exception handler + LDR pc,ABORT # Abort exception handler + LDR pc,RESERVED # Reserved exception handler + LDR pc,IRQ # IRQ interrupt handler + LDR pc,FIQ # FIQ interrupt handler +# +# +__entry: + LDR sp,STACK # Setup stack pointer + LDR pc,START # Jump to Green Hills startup +# +# +STACK: + .data.w __ghsend_stack +START: + .data.w _start # Reset goes to startup function +UNDEFINED: + .data.w __tx_undefined # Undefined handler +SWI: + .data.w __tx_swi_interrupt # Software interrupt handler +PREFETCH: + .data.w __tx_prefetch_handler # Prefetch exception handler +ABORT: + .data.w __tx_abort_handler # Abort exception handler +RESERVED: + .data.w __tx_reserved_handler # Reserved exception handler +IRQ: + .data.w __tx_irq_handler # IRQ interrupt handler +FIQ: + .data.w __tx_fiq_handler # FIQ interrupt handler +# +# + .type __vectors,$function + .size __vectors,.-__vectors diff --git a/ports/cortex_a9/green/example_build/sample_threadx.c b/ports/cortex_a9/green/example_build/sample_threadx.c new file mode 100644 index 00000000..418ec634 --- /dev/null +++ b/ports/cortex_a9/green/example_build/sample_threadx.c @@ -0,0 +1,369 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_a9/green/example_build/sample_threadx.con b/ports/cortex_a9/green/example_build/sample_threadx.con new file mode 100644 index 00000000..f5b28afa --- /dev/null +++ b/ports/cortex_a9/green/example_build/sample_threadx.con @@ -0,0 +1,11 @@ +target_connection.00000000.title="Simulator connection for ThreadX" +target_connection.00000000.type="Custom" +target_connection.00000000.short_type="Custom" +target_connection.00000000.args="simarm -cpu=cortexa9 -fpu -rom" +target_connection.00000000.command="simarm -cpu=cortexa9 -fpu -rom" +target_connection.00000000.logfile="" +target_connection.00000000.mode="download" +target_connection.00000000.setup_script="" +target_connection.00000000.sane="yes" +target_connection.00000000.log="no" +target_connection.00000000.timestamp="1192825758" diff --git a/ports/cortex_a9/green/example_build/sample_threadx.gpj b/ports/cortex_a9/green/example_build/sample_threadx.gpj new file mode 100644 index 00000000..b9b2c04c --- /dev/null +++ b/ports/cortex_a9/green/example_build/sample_threadx.gpj @@ -0,0 +1,11 @@ +#!gbuild +[Program] + -I../../../../common/inc + -I../../../../ports_common_green/inc + -I../inc +reset.arm +tx_initialize_low_level.arm +sample_threadx.c +tx.a +sample_threadx.ld +sample_threadx.con diff --git a/ports/cortex_a9/green/example_build/sample_threadx.ld b/ports/cortex_a9/green/example_build/sample_threadx.ld new file mode 100644 index 00000000..8d1ab4df --- /dev/null +++ b/ports/cortex_a9/green/example_build/sample_threadx.ld @@ -0,0 +1,44 @@ +# The following explains what the default Green Hills sections are for: +# +# picbase - base of the text sections, relocatable in -pic mode +# text - text section +# syscall - syscall section, for host I/O under Multi +# fixaddr/fixtype - for PIC/PID fixups +# rodata - read only data +# romdata - the ROM image of .data +# romsdata - the ROM image of .sdata +# secinfo - section information section, used by the start-up code +# pidbase - base of the data sections, relocatable in -pid mode +# sdabase - base of the small data area section pointer +# sbss - small BSS (zeroed data) section +# sdata - small data section +# data - non-zeroed writeable data section +# bss - zeroed data section +# heap - the heap, grows upward +# stack - the stack, grows downward + +-sec +{ + .reset 0x000000 : + .picbase 0x1000 : + .text : + .comment : + .intercall : + .interfunc : + .syscall : + .fixaddr : + .fixtype : + .rodata : + .romdata ROM(.data) : + .romsdata ROM(.sdata) : + .secinfo : + .pidbase align(16) : + .sdabase : + .sbss : + .sdata : + .data : + .bss : + .heap align(16) pad(0x10000) : + .stack align(16) pad(0x1000) : + .free_mem align(16) pad(0x10000) : +} diff --git a/ports/cortex_a9/green/example_build/sample_threadx_el.gpj b/ports/cortex_a9/green/example_build/sample_threadx_el.gpj new file mode 100644 index 00000000..a51049ca --- /dev/null +++ b/ports/cortex_a9/green/example_build/sample_threadx_el.gpj @@ -0,0 +1,13 @@ +#!gbuild +[Program] + -DTX_ENABLE_EVENT_LOGGING + -I../../../../common/inc + -I../../../../ports_common_green/inc + -I../inc +reset.arm +tx_initialize_low_level.arm +sample_threadx.c +txe.a +sample_threadx_el.ld +sample_threadx.con +readme_threadx.txt diff --git a/ports/cortex_a9/green/example_build/sample_threadx_el.ld b/ports/cortex_a9/green/example_build/sample_threadx_el.ld new file mode 100644 index 00000000..33c0f934 --- /dev/null +++ b/ports/cortex_a9/green/example_build/sample_threadx_el.ld @@ -0,0 +1,45 @@ +# The following explains what the default Green Hills sections are for: +# +# picbase - base of the text sections, relocatable in -pic mode +# text - text section +# syscall - syscall section, for host I/O under Multi +# fixaddr/fixtype - for PIC/PID fixups +# rodata - read only data +# romdata - the ROM image of .data +# romsdata - the ROM image of .sdata +# secinfo - section information section, used by the start-up code +# pidbase - base of the data sections, relocatable in -pid mode +# sdabase - base of the small data area section pointer +# sbss - small BSS (zeroed data) section +# sdata - small data section +# data - non-zeroed writeable data section +# bss - zeroed data section +# heap - the heap, grows upward +# stack - the stack, grows downward + +-sec +{ + .reset 0x000000 : + .picbase 0x1000 : + .text : + .comment : + .intercall : + .interfunc : + .syscall : + .fixaddr : + .fixtype : + .rodata : + .romdata ROM(.data) : + .romsdata ROM(.sdata) : + .secinfo : + .pidbase align(16) : + .sdabase : + .sbss : + .sdata : + .data : + .bss : + .heap align(16) pad(0x1000) : + .stack align(16) pad(0x1000) : + .eventlog align(16) pad(0x10000) : + .free_mem align(16) pad(0x10000) : +} diff --git a/ports/cortex_a9/green/example_build/tx.gpj b/ports/cortex_a9/green/example_build/tx.gpj new file mode 100644 index 00000000..afbd6bef --- /dev/null +++ b/ports/cortex_a9/green/example_build/tx.gpj @@ -0,0 +1,283 @@ +#!gbuild +[Library] + -I../../../../common/inc + -I../../../../ports_common_green/inc + -I../inc +..\..\..\..\common\inc\tx_api.h +..\..\..\..\common\inc\tx_block_pool.h +..\..\..\..\common\inc\tx_byte_pool.h +..\..\..\..\common\inc\tx_event_flags.h +..\..\..\..\common\inc\tx_initialize.h +..\..\..\..\common\inc\tx_mutex.h +..\..\..\..\common\inc\tx_queue.h +..\..\..\..\common\inc\tx_semaphore.h +..\..\..\..\common\inc\tx_thread.h +..\..\..\..\common\inc\tx_timer.h +..\..\..\..\common\inc\tx_trace.h +..\..\..\..\common\inc\tx_user_sample.h +..\inc\tx_port.h +..\..\..\..\ports_common_green\inc\tx_el.h +..\..\..\..\ports_common_green\inc\tx_ghs.h +..\src\tx_thread_context_restore.arm +..\src\tx_thread_context_save.arm +..\src\tx_thread_fiq_context_restore.arm +..\src\tx_thread_fiq_context_save.arm +..\src\tx_thread_fiq_nesting_end.arm +..\src\tx_thread_fiq_nesting_start.arm +..\src\tx_thread_interrupt_control.arm +..\src\tx_thread_interrupt_disable.arm +..\src\tx_thread_interrupt_restore.arm +..\src\tx_thread_irq_nesting_end.arm +..\src\tx_thread_irq_nesting_start.arm +..\src\tx_thread_schedule.arm +..\src\tx_thread_stack_build.arm +..\src\tx_thread_system_return.arm +..\src\tx_thread_vectored_context_save.arm +..\src\tx_timer_interrupt.arm +..\..\..\..\common\src\tx_block_allocate.c +..\..\..\..\common\src\tx_block_pool_cleanup.c +..\..\..\..\common\src\tx_block_pool_create.c +..\..\..\..\common\src\tx_block_pool_delete.c +..\..\..\..\common\src\tx_block_pool_info_get.c +..\..\..\..\common\src\tx_block_pool_initialize.c +..\..\..\..\common\src\tx_block_pool_performance_info_get.c +..\..\..\..\common\src\tx_block_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_block_pool_prioritize.c +..\..\..\..\common\src\tx_block_release.c +..\..\..\..\common\src\tx_byte_allocate.c +..\..\..\..\common\src\tx_byte_pool_cleanup.c +..\..\..\..\common\src\tx_byte_pool_create.c +..\..\..\..\common\src\tx_byte_pool_delete.c +..\..\..\..\common\src\tx_byte_pool_info_get.c +..\..\..\..\common\src\tx_byte_pool_initialize.c +..\..\..\..\common\src\tx_byte_pool_performance_info_get.c +..\..\..\..\common\src\tx_byte_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_byte_pool_prioritize.c +..\..\..\..\common\src\tx_byte_pool_search.c +..\..\..\..\common\src\tx_byte_release.c +..\..\..\..\common\src\tx_event_flags_cleanup.c +..\..\..\..\common\src\tx_event_flags_create.c +..\..\..\..\common\src\tx_event_flags_delete.c +..\..\..\..\common\src\tx_event_flags_get.c +..\..\..\..\common\src\tx_event_flags_info_get.c +..\..\..\..\common\src\tx_event_flags_initialize.c +..\..\..\..\common\src\tx_event_flags_performance_info_get.c +..\..\..\..\common\src\tx_event_flags_performance_system_info_get.c +..\..\..\..\common\src\tx_event_flags_set.c +..\..\..\..\common\src\tx_event_flags_set_notify.c +..\..\..\..\common\src\tx_initialize_high_level.c +..\..\..\..\common\src\tx_initialize_kernel_enter.c +..\..\..\..\common\src\tx_initialize_kernel_setup.c +..\..\..\..\common\src\tx_mutex_cleanup.c +..\..\..\..\common\src\tx_mutex_create.c +..\..\..\..\common\src\tx_mutex_delete.c +..\..\..\..\common\src\tx_mutex_get.c +..\..\..\..\common\src\tx_mutex_info_get.c +..\..\..\..\common\src\tx_mutex_initialize.c +..\..\..\..\common\src\tx_mutex_performance_info_get.c +..\..\..\..\common\src\tx_mutex_performance_system_info_get.c +..\..\..\..\common\src\tx_mutex_prioritize.c +..\..\..\..\common\src\tx_mutex_priority_change.c +..\..\..\..\common\src\tx_mutex_put.c +..\..\..\..\common\src\tx_queue_cleanup.c +..\..\..\..\common\src\tx_queue_create.c +..\..\..\..\common\src\tx_queue_delete.c +..\..\..\..\common\src\tx_queue_flush.c +..\..\..\..\common\src\tx_queue_front_send.c +..\..\..\..\common\src\tx_queue_info_get.c +..\..\..\..\common\src\tx_queue_initialize.c +..\..\..\..\common\src\tx_queue_performance_info_get.c +..\..\..\..\common\src\tx_queue_performance_system_info_get.c +..\..\..\..\common\src\tx_queue_prioritize.c +..\..\..\..\common\src\tx_queue_receive.c +..\..\..\..\common\src\tx_queue_send.c +..\..\..\..\common\src\tx_queue_send_notify.c +..\..\..\..\common\src\tx_semaphore_ceiling_put.c +..\..\..\..\common\src\tx_semaphore_cleanup.c +..\..\..\..\common\src\tx_semaphore_create.c +..\..\..\..\common\src\tx_semaphore_delete.c +..\..\..\..\common\src\tx_semaphore_get.c +..\..\..\..\common\src\tx_semaphore_info_get.c +..\..\..\..\common\src\tx_semaphore_initialize.c +..\..\..\..\common\src\tx_semaphore_performance_info_get.c +..\..\..\..\common\src\tx_semaphore_performance_system_info_get.c +..\..\..\..\common\src\tx_semaphore_prioritize.c +..\..\..\..\common\src\tx_semaphore_put.c +..\..\..\..\common\src\tx_semaphore_put_notify.c +..\..\..\..\common\src\tx_thread_create.c +..\..\..\..\common\src\tx_thread_delete.c +..\..\..\..\common\src\tx_thread_entry_exit_notify.c +..\..\..\..\common\src\tx_thread_identify.c +..\..\..\..\common\src\tx_thread_info_get.c +..\..\..\..\common\src\tx_thread_initialize.c +..\..\..\..\common\src\tx_thread_performance_info_get.c +..\..\..\..\common\src\tx_thread_performance_system_info_get.c +..\..\..\..\common\src\tx_thread_preemption_change.c +..\..\..\..\common\src\tx_thread_priority_change.c +..\..\..\..\common\src\tx_thread_relinquish.c +..\..\..\..\common\src\tx_thread_reset.c +..\..\..\..\common\src\tx_thread_resume.c +..\..\..\..\common\src\tx_thread_shell_entry.c +..\..\..\..\common\src\tx_thread_sleep.c +..\..\..\..\common\src\tx_thread_stack_analyze.c +..\..\..\..\common\src\tx_thread_stack_error_handler.c +..\..\..\..\common\src\tx_thread_stack_error_notify.c +..\..\..\..\common\src\tx_thread_suspend.c +..\..\..\..\common\src\tx_thread_system_preempt_check.c +..\..\..\..\common\src\tx_thread_system_resume.c +..\..\..\..\common\src\tx_thread_system_suspend.c +..\..\..\..\common\src\tx_thread_terminate.c +..\..\..\..\common\src\tx_thread_time_slice.c +..\..\..\..\common\src\tx_thread_time_slice_change.c +..\..\..\..\common\src\tx_thread_timeout.c +..\..\..\..\common\src\tx_thread_wait_abort.c +..\..\..\..\common\src\tx_time_get.c +..\..\..\..\common\src\tx_time_set.c +..\..\..\..\common\src\tx_timer_activate.c +..\..\..\..\common\src\tx_timer_change.c +..\..\..\..\common\src\tx_timer_create.c +..\..\..\..\common\src\tx_timer_deactivate.c +..\..\..\..\common\src\tx_timer_delete.c +..\..\..\..\common\src\tx_timer_expiration_process.c +..\..\..\..\common\src\tx_timer_info_get.c +..\..\..\..\common\src\tx_timer_initialize.c +..\..\..\..\common\src\tx_timer_performance_info_get.c +..\..\..\..\common\src\tx_timer_performance_system_info_get.c +..\..\..\..\common\src\tx_timer_system_activate.c +..\..\..\..\common\src\tx_timer_system_deactivate.c +..\..\..\..\common\src\tx_timer_thread_entry.c +..\..\..\..\common\src\tx_trace_buffer_full_notify.c +..\..\..\..\common\src\tx_trace_disable.c +..\..\..\..\common\src\tx_trace_enable.c +..\..\..\..\common\src\tx_trace_event_filter.c +..\..\..\..\common\src\tx_trace_event_unfilter.c +..\..\..\..\common\src\tx_trace_initialize.c +..\..\..\..\common\src\tx_trace_interrupt_control.c +..\..\..\..\common\src\tx_trace_isr_enter_insert.c +..\..\..\..\common\src\tx_trace_isr_exit_insert.c +..\..\..\..\common\src\tx_trace_object_register.c +..\..\..\..\common\src\tx_trace_object_unregister.c +..\..\..\..\common\src\tx_trace_user_event_insert.c +..\..\..\..\common\src\txe_block_allocate.c +..\..\..\..\common\src\txe_block_pool_create.c +..\..\..\..\common\src\txe_block_pool_delete.c +..\..\..\..\common\src\txe_block_pool_info_get.c +..\..\..\..\common\src\txe_block_pool_prioritize.c +..\..\..\..\common\src\txe_block_release.c +..\..\..\..\common\src\txe_byte_allocate.c +..\..\..\..\common\src\txe_byte_pool_create.c +..\..\..\..\common\src\txe_byte_pool_delete.c +..\..\..\..\common\src\txe_byte_pool_info_get.c +..\..\..\..\common\src\txe_byte_pool_prioritize.c +..\..\..\..\common\src\txe_byte_release.c +..\..\..\..\common\src\txe_event_flags_create.c +..\..\..\..\common\src\txe_event_flags_delete.c +..\..\..\..\common\src\txe_event_flags_get.c +..\..\..\..\common\src\txe_event_flags_info_get.c +..\..\..\..\common\src\txe_event_flags_set.c +..\..\..\..\common\src\txe_event_flags_set_notify.c +..\..\..\..\common\src\txe_mutex_create.c +..\..\..\..\common\src\txe_mutex_delete.c +..\..\..\..\common\src\txe_mutex_get.c +..\..\..\..\common\src\txe_mutex_info_get.c +..\..\..\..\common\src\txe_mutex_prioritize.c +..\..\..\..\common\src\txe_mutex_put.c +..\..\..\..\common\src\txe_queue_create.c +..\..\..\..\common\src\txe_queue_delete.c +..\..\..\..\common\src\txe_queue_flush.c +..\..\..\..\common\src\txe_queue_front_send.c +..\..\..\..\common\src\txe_queue_info_get.c +..\..\..\..\common\src\txe_queue_prioritize.c +..\..\..\..\common\src\txe_queue_receive.c +..\..\..\..\common\src\txe_queue_send.c +..\..\..\..\common\src\txe_queue_send_notify.c +..\..\..\..\common\src\txe_semaphore_ceiling_put.c +..\..\..\..\common\src\txe_semaphore_create.c +..\..\..\..\common\src\txe_semaphore_delete.c +..\..\..\..\common\src\txe_semaphore_get.c +..\..\..\..\common\src\txe_semaphore_info_get.c +..\..\..\..\common\src\txe_semaphore_prioritize.c +..\..\..\..\common\src\txe_semaphore_put.c +..\..\..\..\common\src\txe_semaphore_put_notify.c +..\..\..\..\common\src\txe_thread_create.c +..\..\..\..\common\src\txe_thread_delete.c +..\..\..\..\common\src\txe_thread_entry_exit_notify.c +..\..\..\..\common\src\txe_thread_info_get.c +..\..\..\..\common\src\txe_thread_preemption_change.c +..\..\..\..\common\src\txe_thread_priority_change.c +..\..\..\..\common\src\txe_thread_relinquish.c +..\..\..\..\common\src\txe_thread_reset.c +..\..\..\..\common\src\txe_thread_resume.c +..\..\..\..\common\src\txe_thread_suspend.c +..\..\..\..\common\src\txe_thread_terminate.c +..\..\..\..\common\src\txe_thread_time_slice_change.c +..\..\..\..\common\src\txe_thread_wait_abort.c +..\..\..\..\common\src\txe_timer_activate.c +..\..\..\..\common\src\txe_timer_change.c +..\..\..\..\common\src\txe_timer_create.c +..\..\..\..\common\src\txe_timer_deactivate.c +..\..\..\..\common\src\txe_timer_delete.c +..\..\..\..\common\src\txe_timer_info_get.c +..\..\..\..\ports_common_green\src\tx_el.c +..\..\..\..\ports_common_green\src\tx_ghs.c +..\..\..\..\ports_common_green\src\tx_ghse.c +..\..\..\..\ports_common_green\src\txr_block_allocate.c +..\..\..\..\ports_common_green\src\txr_block_pool_create.c +..\..\..\..\ports_common_green\src\txr_block_pool_delete.c +..\..\..\..\ports_common_green\src\txr_block_pool_info_get.c +..\..\..\..\ports_common_green\src\txr_block_pool_prioritize.c +..\..\..\..\ports_common_green\src\txr_block_release.c +..\..\..\..\ports_common_green\src\txr_byte_allocate.c +..\..\..\..\ports_common_green\src\txr_byte_pool_create.c +..\..\..\..\ports_common_green\src\txr_byte_pool_delete.c +..\..\..\..\ports_common_green\src\txr_byte_pool_info_get.c +..\..\..\..\ports_common_green\src\txr_byte_pool_prioritize.c +..\..\..\..\ports_common_green\src\txr_byte_release.c +..\..\..\..\ports_common_green\src\txr_event_flags_create.c +..\..\..\..\ports_common_green\src\txr_event_flags_delete.c +..\..\..\..\ports_common_green\src\txr_event_flags_get.c +..\..\..\..\ports_common_green\src\txr_event_flags_info_get.c +..\..\..\..\ports_common_green\src\txr_event_flags_set.c +..\..\..\..\ports_common_green\src\txr_event_flags_set_notify.c +..\..\..\..\ports_common_green\src\txr_ghs.c +..\..\..\..\ports_common_green\src\txr_mutex_create.c +..\..\..\..\ports_common_green\src\txr_mutex_delete.c +..\..\..\..\ports_common_green\src\txr_mutex_get.c +..\..\..\..\ports_common_green\src\txr_mutex_info_get.c +..\..\..\..\ports_common_green\src\txr_mutex_prioritize.c +..\..\..\..\ports_common_green\src\txr_mutex_put.c +..\..\..\..\ports_common_green\src\txr_queue_create.c +..\..\..\..\ports_common_green\src\txr_queue_delete.c +..\..\..\..\ports_common_green\src\txr_queue_flush.c +..\..\..\..\ports_common_green\src\txr_queue_front_send.c +..\..\..\..\ports_common_green\src\txr_queue_info_get.c +..\..\..\..\ports_common_green\src\txr_queue_prioritize.c +..\..\..\..\ports_common_green\src\txr_queue_receive.c +..\..\..\..\ports_common_green\src\txr_queue_send.c +..\..\..\..\ports_common_green\src\txr_queue_send_notify.c +..\..\..\..\ports_common_green\src\txr_semaphore_ceiling_put.c +..\..\..\..\ports_common_green\src\txr_semaphore_create.c +..\..\..\..\ports_common_green\src\txr_semaphore_delete.c +..\..\..\..\ports_common_green\src\txr_semaphore_get.c +..\..\..\..\ports_common_green\src\txr_semaphore_info_get.c +..\..\..\..\ports_common_green\src\txr_semaphore_prioritize.c +..\..\..\..\ports_common_green\src\txr_semaphore_put.c +..\..\..\..\ports_common_green\src\txr_semaphore_put_notify.c +..\..\..\..\ports_common_green\src\txr_thread_create.c +..\..\..\..\ports_common_green\src\txr_thread_delete.c +..\..\..\..\ports_common_green\src\txr_thread_entry_exit_notify.c +..\..\..\..\ports_common_green\src\txr_thread_info_get.c +..\..\..\..\ports_common_green\src\txr_thread_preemption_change.c +..\..\..\..\ports_common_green\src\txr_thread_priority_change.c +..\..\..\..\ports_common_green\src\txr_thread_reset.c +..\..\..\..\ports_common_green\src\txr_thread_resume.c +..\..\..\..\ports_common_green\src\txr_thread_suspend.c +..\..\..\..\ports_common_green\src\txr_thread_terminate.c +..\..\..\..\ports_common_green\src\txr_thread_time_slice_change.c +..\..\..\..\ports_common_green\src\txr_thread_wait_abort.c +..\..\..\..\ports_common_green\src\txr_timer_activate.c +..\..\..\..\ports_common_green\src\txr_timer_change.c +..\..\..\..\ports_common_green\src\txr_timer_create.c +..\..\..\..\ports_common_green\src\txr_timer_deactivate.c +..\..\..\..\ports_common_green\src\txr_timer_delete.c +..\..\..\..\ports_common_green\src\txr_timer_info_get.c diff --git a/ports/cortex_a9/green/example_build/tx_initialize_low_level.arm b/ports/cortex_a9/green/example_build/tx_initialize_low_level.arm new file mode 100644 index 00000000..604586e2 --- /dev/null +++ b/ports/cortex_a9/green/example_build/tx_initialize_low_level.arm @@ -0,0 +1,319 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_initialize.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + SVC_MODE = 0xD3 # Disable IRQ/FIQ SVC mode + IRQ_MODE = 0xD2 # Disable IRQ/FIQ IRQ mode + FIQ_MODE = 0xD1 # Disable IRQ/FIQ FIQ mode + SYS_MODE = 0xDF # Disable IRQ/FIQ SYS mode + MODE_MASK = 0x1F # Mode mask + FIQ_STACK_SIZE = 512 # FIQ stack size + IRQ_STACK_SIZE = 1024 # IRQ stack size + SYS_STACK_SIZE = 1024 # SYS stack size + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-A9/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_initialize_low_level(VOID) +{ */ + .globl _tx_initialize_low_level +_tx_initialize_low_level: + + /****** NOTE ****** We must be in SVC MODE at this point. Some monitors + enter this routine in USER mode and require a software interrupt to + change into SVC mode. */ + + /* Save the system stack pointer. */ + /* _tx_thread_system_stack_ptr = (VOID_PTR) (sp); */ + + LDR r1,=_tx_thread_system_stack_ptr # Pickup address of system stack ptr + STR sp, [r1] # Save system stack + + /* Pickup the first available memory address. */ + + LDR r0,=__ghsbegin_free_mem # Pickup free memory address + + /* Setup initial stack pointers for IRQ and FIQ modes. */ + + MRS r12, CPSR # Pickup current CPSR + MOV r1, r0 # Get first available memory +#ifdef TX_ENABLE_IRQ_NESTING + /* Setup the system mode stack for nested interrupt support */ + LDR r2, =SYS_STACK_SIZE # Pickup stack size + BIC r3, r12, MODE_MASK # Clear mode bits + ORR r3, r3, SYS_MODE # Build SYS mode CPSR + MSR CPSR_c, r3 # Enter SYS mode + ADD r1, r1, r2 # Calculate start of SYS stack + SUB r1, r1, 1 # Backup one byte + BIC r1, r1, 7 # Insure 8-byte alignment + MOV sp, r1 # Setup SYS stack pointer +#endif + LDR r2, =FIQ_STACK_SIZE # Pickup stack size + BIC r3, r12, MODE_MASK # Clear mode bits + ORR r3, r3, FIQ_MODE # Build FIQ mode CPSR + MSR CPSR_c, r3 # Enter FIQ mode + ADD r1, r1, r2 # Calculate start of FIQ stack + SUB r1, r1, 1 # Backup one byte + BIC r1, r1, 7 # Insure 8-byte alignment + MOV sp, r1 # Setup FIQ stack pointer + MOV r10, 0 # Clear sl + MOV r11, 0 # Clear fp + LDR r2, =IRQ_STACK_SIZE # Pickup IRQ (system stack size) + BIC r3, r12, MODE_MASK # Clear mode bits + ORR r3, r3, IRQ_MODE # Build IRQ mode CPSR + MSR CPSR_c, r3 # Enter IRQ mode + ADD r1, r1, r2 # Calculate start of IRQ stack + SUB r1, r1, 1 # Backup one byte + BIC r1, r1, 7 # Insure 8-byte alignment + MOV sp, r1 # Setup IRQ stack pointer + MSR CPSR_c, r12 # Restore previous mode + ADD r0, r1, 4 # Adjust the new free memory + + + /* Save the first available memory address. */ + /* _tx_initialize_unused_memory = (VOID_PTR) __ghsbegin_free_mem + [SYS_STACK] + FIQ_STACK + IRQ_STACK; */ + + LDR r2,=_tx_initialize_unused_memory # Pickup unused memory ptr address + STR r0, [r2] # Save first free memory address + + + /* Setup Timer for periodic interrupts. To generate timer interrupts with + the Green Hills simulator, enter the following command in the target + window: timer 9999 irq */ + + /* Done, return to caller. */ + + RET # Return to caller + + .type _tx_initialize_low_level,$function + .size _tx_initialize_low_level,.-_tx_initialize_low_level +/* } */ + + +/* Define shells for each of the interrupt vectors. */ + + .globl __tx_undefined +__tx_undefined: + B __tx_undefined # Undefined handler + + .type __tx_undefined,$function + .size __tx_undefined,.-__tx_undefined + + .globl __tx_swi_interrupt +__tx_swi_interrupt: + B __tx_swi_interrupt # Software interrupt handler + + .type __tx_swi_interrupt,$function + .size __tx_swi_interrupt,.-__tx_swi_interrupt + + .globl __tx_prefetch_handler +__tx_prefetch_handler: + B __tx_prefetch_handler # Prefetch exception handler + + .type __tx_prefetch_handler,$function + .size __tx_prefetch_handler,.-__tx_prefetch_handler + + .globl __tx_abort_handler +__tx_abort_handler: + B __tx_abort_handler # Abort exception handler + + .type __tx_abort_handler,$function + .size __tx_abort_handler,.-__tx_abort_handler + + .globl __tx_reserved_handler +__tx_reserved_handler: + B __tx_reserved_handler # Reserved exception handler + + .type __tx_reserved_handler,$function + .size __tx_reserved_handler,.-__tx_reserved_handler + + .globl __tx_irq_handler + .globl __tx_irq_processing_return +__tx_irq_handler: + + /* Jump to context save to save system context. */ + B _tx_thread_context_save + + .type __tx_irq_handler,$function + .size __tx_irq_handler,.-__tx_irq_handler + +__tx_irq_processing_return: + + /* At this point execution is still in the IRQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. */ + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 0 # Build interrupt code + BL _tx_el_interrupt # Call interrupt event logging +#endif + + /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start + from IRQ mode with interrupts disabled. This routine switches to the + system mode and returns with IRQ interrupts enabled. + + NOTE: It is very important to ensure all IRQ interrupts are cleared + prior to enabling nested IRQ interrupts. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_start +#endif + + + /* For debug purpose, execute the timer interrupt processing here. In + a real system, some kind of status indication would have to be checked + before the timer interrupt handler could be called. */ + BL _tx_timer_interrupt # Timer interrupt handler + + /* Application IRQ handlers can be called here! */ + + /* If interrupt nesting was started earlier, the end of interrupt nesting + service must be called before returning to _tx_thread_context_restore. + This routine returns in processing in IRQ mode with interrupts disabled. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_end +#endif + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 0 # Build interrupt code + BL _tx_el_interrupt_end # Call interrupt event logging +#endif + + /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + .type __tx_irq_processing_return,$function + .size __tx_irq_processing_return,.-__tx_irq_processing_return + +#ifdef TX_ENABLE_FIQ_SUPPORT + + .globl __tx_fiq_handler + .globl __tx_fiq_processing_return +__tx_fiq_handler: + /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save + + .type __tx_fiq_handler,$function + .size __tx_fiq_handler,.-__tx_fiq_handler + +__tx_fiq_processing_return: + + /* At this point execution is still in the FIQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. */ + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 1 # Build interrupt code + BL _tx_el_interrupt # Call interrupt event logging +#endif + + /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start + from FIQ mode with interrupts disabled. This routine switches to the + system mode and returns with FIQ interrupts enabled. + + NOTE: It is very important to ensure all FIQ interrupts are cleared + prior to enabling nested FIQ interrupts. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_start +#endif + + /* Application FIQ handlers can be called here! */ + + /* If interrupt nesting was started earlier, the end of interrupt nesting + service must be called before returning to _tx_thread_fiq_context_restore. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_end +#endif + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 1 # Build interrupt code + BL _tx_el_interrupt_end # Call interrupt event logging +#endif + + /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + .type __tx_fiq_processing_return,$function + .size __tx_fiq_processing_return,.-__tx_fiq_processing_return + +#else + .globl __tx_fiq_handler +__tx_fiq_handler: + B __tx_fiq_handler # FIQ interrupt handler + + .type __tx_fiq_handler,$function + .size __tx_fiq_handler,.-__tx_fiq_handler +#endif + + /* Reference build options and version ID to ensure they come in. */ + +BUILD_OPTIONS: + .data.w _tx_build_options +VERSION_ID: + .data.w _tx_version_id diff --git a/ports/cortex_a9/green/example_build/txe.gpj b/ports/cortex_a9/green/example_build/txe.gpj new file mode 100644 index 00000000..662bcd16 --- /dev/null +++ b/ports/cortex_a9/green/example_build/txe.gpj @@ -0,0 +1,284 @@ +#!gbuild +[Library] + -DTX_ENABLE_EVENT_LOGGING + -I../../../../common/inc + -I../../../../ports_common_green/inc + -I../inc +..\..\..\..\common\inc\tx_api.h +..\..\..\..\common\inc\tx_block_pool.h +..\..\..\..\common\inc\tx_byte_pool.h +..\..\..\..\common\inc\tx_event_flags.h +..\..\..\..\common\inc\tx_initialize.h +..\..\..\..\common\inc\tx_mutex.h +..\..\..\..\common\inc\tx_queue.h +..\..\..\..\common\inc\tx_semaphore.h +..\..\..\..\common\inc\tx_thread.h +..\..\..\..\common\inc\tx_timer.h +..\..\..\..\common\inc\tx_trace.h +..\..\..\..\common\inc\tx_user_sample.h +..\inc\tx_port.h +..\..\..\..\ports_common_green\inc\tx_el.h +..\..\..\..\ports_common_green\inc\tx_ghs.h +..\src\tx_thread_context_restore.arm +..\src\tx_thread_context_save.arm +..\src\tx_thread_fiq_context_restore.arm +..\src\tx_thread_fiq_context_save.arm +..\src\tx_thread_fiq_nesting_end.arm +..\src\tx_thread_fiq_nesting_start.arm +..\src\tx_thread_interrupt_control.arm +..\src\tx_thread_interrupt_disable.arm +..\src\tx_thread_interrupt_restore.arm +..\src\tx_thread_irq_nesting_end.arm +..\src\tx_thread_irq_nesting_start.arm +..\src\tx_thread_schedule.arm +..\src\tx_thread_stack_build.arm +..\src\tx_thread_system_return.arm +..\src\tx_thread_vectored_context_save.arm +..\src\tx_timer_interrupt.arm +..\..\..\..\common\src\tx_block_allocate.c +..\..\..\..\common\src\tx_block_pool_cleanup.c +..\..\..\..\common\src\tx_block_pool_create.c +..\..\..\..\common\src\tx_block_pool_delete.c +..\..\..\..\common\src\tx_block_pool_info_get.c +..\..\..\..\common\src\tx_block_pool_initialize.c +..\..\..\..\common\src\tx_block_pool_performance_info_get.c +..\..\..\..\common\src\tx_block_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_block_pool_prioritize.c +..\..\..\..\common\src\tx_block_release.c +..\..\..\..\common\src\tx_byte_allocate.c +..\..\..\..\common\src\tx_byte_pool_cleanup.c +..\..\..\..\common\src\tx_byte_pool_create.c +..\..\..\..\common\src\tx_byte_pool_delete.c +..\..\..\..\common\src\tx_byte_pool_info_get.c +..\..\..\..\common\src\tx_byte_pool_initialize.c +..\..\..\..\common\src\tx_byte_pool_performance_info_get.c +..\..\..\..\common\src\tx_byte_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_byte_pool_prioritize.c +..\..\..\..\common\src\tx_byte_pool_search.c +..\..\..\..\common\src\tx_byte_release.c +..\..\..\..\common\src\tx_event_flags_cleanup.c +..\..\..\..\common\src\tx_event_flags_create.c +..\..\..\..\common\src\tx_event_flags_delete.c +..\..\..\..\common\src\tx_event_flags_get.c +..\..\..\..\common\src\tx_event_flags_info_get.c +..\..\..\..\common\src\tx_event_flags_initialize.c +..\..\..\..\common\src\tx_event_flags_performance_info_get.c +..\..\..\..\common\src\tx_event_flags_performance_system_info_get.c +..\..\..\..\common\src\tx_event_flags_set.c +..\..\..\..\common\src\tx_event_flags_set_notify.c +..\..\..\..\common\src\tx_initialize_high_level.c +..\..\..\..\common\src\tx_initialize_kernel_enter.c +..\..\..\..\common\src\tx_initialize_kernel_setup.c +..\..\..\..\common\src\tx_mutex_cleanup.c +..\..\..\..\common\src\tx_mutex_create.c +..\..\..\..\common\src\tx_mutex_delete.c +..\..\..\..\common\src\tx_mutex_get.c +..\..\..\..\common\src\tx_mutex_info_get.c +..\..\..\..\common\src\tx_mutex_initialize.c +..\..\..\..\common\src\tx_mutex_performance_info_get.c +..\..\..\..\common\src\tx_mutex_performance_system_info_get.c +..\..\..\..\common\src\tx_mutex_prioritize.c +..\..\..\..\common\src\tx_mutex_priority_change.c +..\..\..\..\common\src\tx_mutex_put.c +..\..\..\..\common\src\tx_queue_cleanup.c +..\..\..\..\common\src\tx_queue_create.c +..\..\..\..\common\src\tx_queue_delete.c +..\..\..\..\common\src\tx_queue_flush.c +..\..\..\..\common\src\tx_queue_front_send.c +..\..\..\..\common\src\tx_queue_info_get.c +..\..\..\..\common\src\tx_queue_initialize.c +..\..\..\..\common\src\tx_queue_performance_info_get.c +..\..\..\..\common\src\tx_queue_performance_system_info_get.c +..\..\..\..\common\src\tx_queue_prioritize.c +..\..\..\..\common\src\tx_queue_receive.c +..\..\..\..\common\src\tx_queue_send.c +..\..\..\..\common\src\tx_queue_send_notify.c +..\..\..\..\common\src\tx_semaphore_ceiling_put.c +..\..\..\..\common\src\tx_semaphore_cleanup.c +..\..\..\..\common\src\tx_semaphore_create.c +..\..\..\..\common\src\tx_semaphore_delete.c +..\..\..\..\common\src\tx_semaphore_get.c +..\..\..\..\common\src\tx_semaphore_info_get.c +..\..\..\..\common\src\tx_semaphore_initialize.c +..\..\..\..\common\src\tx_semaphore_performance_info_get.c +..\..\..\..\common\src\tx_semaphore_performance_system_info_get.c +..\..\..\..\common\src\tx_semaphore_prioritize.c +..\..\..\..\common\src\tx_semaphore_put.c +..\..\..\..\common\src\tx_semaphore_put_notify.c +..\..\..\..\common\src\tx_thread_create.c +..\..\..\..\common\src\tx_thread_delete.c +..\..\..\..\common\src\tx_thread_entry_exit_notify.c +..\..\..\..\common\src\tx_thread_identify.c +..\..\..\..\common\src\tx_thread_info_get.c +..\..\..\..\common\src\tx_thread_initialize.c +..\..\..\..\common\src\tx_thread_performance_info_get.c +..\..\..\..\common\src\tx_thread_performance_system_info_get.c +..\..\..\..\common\src\tx_thread_preemption_change.c +..\..\..\..\common\src\tx_thread_priority_change.c +..\..\..\..\common\src\tx_thread_relinquish.c +..\..\..\..\common\src\tx_thread_reset.c +..\..\..\..\common\src\tx_thread_resume.c +..\..\..\..\common\src\tx_thread_shell_entry.c +..\..\..\..\common\src\tx_thread_sleep.c +..\..\..\..\common\src\tx_thread_stack_analyze.c +..\..\..\..\common\src\tx_thread_stack_error_handler.c +..\..\..\..\common\src\tx_thread_stack_error_notify.c +..\..\..\..\common\src\tx_thread_suspend.c +..\..\..\..\common\src\tx_thread_system_preempt_check.c +..\..\..\..\common\src\tx_thread_system_resume.c +..\..\..\..\common\src\tx_thread_system_suspend.c +..\..\..\..\common\src\tx_thread_terminate.c +..\..\..\..\common\src\tx_thread_time_slice.c +..\..\..\..\common\src\tx_thread_time_slice_change.c +..\..\..\..\common\src\tx_thread_timeout.c +..\..\..\..\common\src\tx_thread_wait_abort.c +..\..\..\..\common\src\tx_time_get.c +..\..\..\..\common\src\tx_time_set.c +..\..\..\..\common\src\tx_timer_activate.c +..\..\..\..\common\src\tx_timer_change.c +..\..\..\..\common\src\tx_timer_create.c +..\..\..\..\common\src\tx_timer_deactivate.c +..\..\..\..\common\src\tx_timer_delete.c +..\..\..\..\common\src\tx_timer_expiration_process.c +..\..\..\..\common\src\tx_timer_info_get.c +..\..\..\..\common\src\tx_timer_initialize.c +..\..\..\..\common\src\tx_timer_performance_info_get.c +..\..\..\..\common\src\tx_timer_performance_system_info_get.c +..\..\..\..\common\src\tx_timer_system_activate.c +..\..\..\..\common\src\tx_timer_system_deactivate.c +..\..\..\..\common\src\tx_timer_thread_entry.c +..\..\..\..\common\src\tx_trace_buffer_full_notify.c +..\..\..\..\common\src\tx_trace_disable.c +..\..\..\..\common\src\tx_trace_enable.c +..\..\..\..\common\src\tx_trace_event_filter.c +..\..\..\..\common\src\tx_trace_event_unfilter.c +..\..\..\..\common\src\tx_trace_initialize.c +..\..\..\..\common\src\tx_trace_interrupt_control.c +..\..\..\..\common\src\tx_trace_isr_enter_insert.c +..\..\..\..\common\src\tx_trace_isr_exit_insert.c +..\..\..\..\common\src\tx_trace_object_register.c +..\..\..\..\common\src\tx_trace_object_unregister.c +..\..\..\..\common\src\tx_trace_user_event_insert.c +..\..\..\..\common\src\txe_block_allocate.c +..\..\..\..\common\src\txe_block_pool_create.c +..\..\..\..\common\src\txe_block_pool_delete.c +..\..\..\..\common\src\txe_block_pool_info_get.c +..\..\..\..\common\src\txe_block_pool_prioritize.c +..\..\..\..\common\src\txe_block_release.c +..\..\..\..\common\src\txe_byte_allocate.c +..\..\..\..\common\src\txe_byte_pool_create.c +..\..\..\..\common\src\txe_byte_pool_delete.c +..\..\..\..\common\src\txe_byte_pool_info_get.c +..\..\..\..\common\src\txe_byte_pool_prioritize.c +..\..\..\..\common\src\txe_byte_release.c +..\..\..\..\common\src\txe_event_flags_create.c +..\..\..\..\common\src\txe_event_flags_delete.c +..\..\..\..\common\src\txe_event_flags_get.c +..\..\..\..\common\src\txe_event_flags_info_get.c +..\..\..\..\common\src\txe_event_flags_set.c +..\..\..\..\common\src\txe_event_flags_set_notify.c +..\..\..\..\common\src\txe_mutex_create.c +..\..\..\..\common\src\txe_mutex_delete.c +..\..\..\..\common\src\txe_mutex_get.c +..\..\..\..\common\src\txe_mutex_info_get.c +..\..\..\..\common\src\txe_mutex_prioritize.c +..\..\..\..\common\src\txe_mutex_put.c +..\..\..\..\common\src\txe_queue_create.c +..\..\..\..\common\src\txe_queue_delete.c +..\..\..\..\common\src\txe_queue_flush.c +..\..\..\..\common\src\txe_queue_front_send.c +..\..\..\..\common\src\txe_queue_info_get.c +..\..\..\..\common\src\txe_queue_prioritize.c +..\..\..\..\common\src\txe_queue_receive.c +..\..\..\..\common\src\txe_queue_send.c +..\..\..\..\common\src\txe_queue_send_notify.c +..\..\..\..\common\src\txe_semaphore_ceiling_put.c +..\..\..\..\common\src\txe_semaphore_create.c +..\..\..\..\common\src\txe_semaphore_delete.c +..\..\..\..\common\src\txe_semaphore_get.c +..\..\..\..\common\src\txe_semaphore_info_get.c +..\..\..\..\common\src\txe_semaphore_prioritize.c +..\..\..\..\common\src\txe_semaphore_put.c +..\..\..\..\common\src\txe_semaphore_put_notify.c +..\..\..\..\common\src\txe_thread_create.c +..\..\..\..\common\src\txe_thread_delete.c +..\..\..\..\common\src\txe_thread_entry_exit_notify.c +..\..\..\..\common\src\txe_thread_info_get.c +..\..\..\..\common\src\txe_thread_preemption_change.c +..\..\..\..\common\src\txe_thread_priority_change.c +..\..\..\..\common\src\txe_thread_relinquish.c +..\..\..\..\common\src\txe_thread_reset.c +..\..\..\..\common\src\txe_thread_resume.c +..\..\..\..\common\src\txe_thread_suspend.c +..\..\..\..\common\src\txe_thread_terminate.c +..\..\..\..\common\src\txe_thread_time_slice_change.c +..\..\..\..\common\src\txe_thread_wait_abort.c +..\..\..\..\common\src\txe_timer_activate.c +..\..\..\..\common\src\txe_timer_change.c +..\..\..\..\common\src\txe_timer_create.c +..\..\..\..\common\src\txe_timer_deactivate.c +..\..\..\..\common\src\txe_timer_delete.c +..\..\..\..\common\src\txe_timer_info_get.c +..\..\..\..\ports_common_green\src\tx_el.c +..\..\..\..\ports_common_green\src\tx_ghs.c +..\..\..\..\ports_common_green\src\tx_ghse.c +..\..\..\..\ports_common_green\src\txr_block_allocate.c +..\..\..\..\ports_common_green\src\txr_block_pool_create.c +..\..\..\..\ports_common_green\src\txr_block_pool_delete.c +..\..\..\..\ports_common_green\src\txr_block_pool_info_get.c +..\..\..\..\ports_common_green\src\txr_block_pool_prioritize.c +..\..\..\..\ports_common_green\src\txr_block_release.c +..\..\..\..\ports_common_green\src\txr_byte_allocate.c +..\..\..\..\ports_common_green\src\txr_byte_pool_create.c +..\..\..\..\ports_common_green\src\txr_byte_pool_delete.c +..\..\..\..\ports_common_green\src\txr_byte_pool_info_get.c +..\..\..\..\ports_common_green\src\txr_byte_pool_prioritize.c +..\..\..\..\ports_common_green\src\txr_byte_release.c +..\..\..\..\ports_common_green\src\txr_event_flags_create.c +..\..\..\..\ports_common_green\src\txr_event_flags_delete.c +..\..\..\..\ports_common_green\src\txr_event_flags_get.c +..\..\..\..\ports_common_green\src\txr_event_flags_info_get.c +..\..\..\..\ports_common_green\src\txr_event_flags_set.c +..\..\..\..\ports_common_green\src\txr_event_flags_set_notify.c +..\..\..\..\ports_common_green\src\txr_ghs.c +..\..\..\..\ports_common_green\src\txr_mutex_create.c +..\..\..\..\ports_common_green\src\txr_mutex_delete.c +..\..\..\..\ports_common_green\src\txr_mutex_get.c +..\..\..\..\ports_common_green\src\txr_mutex_info_get.c +..\..\..\..\ports_common_green\src\txr_mutex_prioritize.c +..\..\..\..\ports_common_green\src\txr_mutex_put.c +..\..\..\..\ports_common_green\src\txr_queue_create.c +..\..\..\..\ports_common_green\src\txr_queue_delete.c +..\..\..\..\ports_common_green\src\txr_queue_flush.c +..\..\..\..\ports_common_green\src\txr_queue_front_send.c +..\..\..\..\ports_common_green\src\txr_queue_info_get.c +..\..\..\..\ports_common_green\src\txr_queue_prioritize.c +..\..\..\..\ports_common_green\src\txr_queue_receive.c +..\..\..\..\ports_common_green\src\txr_queue_send.c +..\..\..\..\ports_common_green\src\txr_queue_send_notify.c +..\..\..\..\ports_common_green\src\txr_semaphore_ceiling_put.c +..\..\..\..\ports_common_green\src\txr_semaphore_create.c +..\..\..\..\ports_common_green\src\txr_semaphore_delete.c +..\..\..\..\ports_common_green\src\txr_semaphore_get.c +..\..\..\..\ports_common_green\src\txr_semaphore_info_get.c +..\..\..\..\ports_common_green\src\txr_semaphore_prioritize.c +..\..\..\..\ports_common_green\src\txr_semaphore_put.c +..\..\..\..\ports_common_green\src\txr_semaphore_put_notify.c +..\..\..\..\ports_common_green\src\txr_thread_create.c +..\..\..\..\ports_common_green\src\txr_thread_delete.c +..\..\..\..\ports_common_green\src\txr_thread_entry_exit_notify.c +..\..\..\..\ports_common_green\src\txr_thread_info_get.c +..\..\..\..\ports_common_green\src\txr_thread_preemption_change.c +..\..\..\..\ports_common_green\src\txr_thread_priority_change.c +..\..\..\..\ports_common_green\src\txr_thread_reset.c +..\..\..\..\ports_common_green\src\txr_thread_resume.c +..\..\..\..\ports_common_green\src\txr_thread_suspend.c +..\..\..\..\ports_common_green\src\txr_thread_terminate.c +..\..\..\..\ports_common_green\src\txr_thread_time_slice_change.c +..\..\..\..\ports_common_green\src\txr_thread_wait_abort.c +..\..\..\..\ports_common_green\src\txr_timer_activate.c +..\..\..\..\ports_common_green\src\txr_timer_change.c +..\..\..\..\ports_common_green\src\txr_timer_create.c +..\..\..\..\ports_common_green\src\txr_timer_deactivate.c +..\..\..\..\ports_common_green\src\txr_timer_delete.c +..\..\..\..\ports_common_green\src\txr_timer_info_get.c diff --git a/ports/cortex_a9/green/inc/tx_port.h b/ports/cortex_a9/green/inc/tx_port.h new file mode 100644 index 00000000..ba01cbdc --- /dev/null +++ b/ports/cortex_a9/green/inc/tx_port.h @@ -0,0 +1,402 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A9/Green Hills */ +/* 6.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include +#include +#include "tx_ghs.h" + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define constants for Green Hills EventAnalyzer. */ + +/* Define the number of ticks per second. This informs the EventAnalyzer what the timestamps + represent. By default, this is set to 1,000,000 i.e., one tick every microsecond. */ + +#define TX_EL_TICKS_PER_SECOND 1000000 + +/* Define the method of how to get the upper and lower 32-bits of the time stamp. By default, simply + simulate the time-stamp source with a counter. */ + +#define read_tbu() _tx_el_time_base_upper +#define read_tbl() ++_tx_el_time_base_lower + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ + VOID * tx_thread_eh_globals; \ + int Errno; /* errno. */ \ + char * strtok_saved_pos; /* strtok() position. */ +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + +#if (__GHS_VERSION_NUMBER >= 500) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) \ + { \ + extern void __tx_cpp_exception_init(TX_THREAD *thread_ptr); \ + __tx_cpp_exception_init(thread_ptr); \ + } +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) \ + { \ + #pragma weak __cpp_exception_init \ + extern void __cpp_exception_init(void **); \ + static void (*const cpp_init_funcp)(void **) = __cpp_exception_init; \ + if (cpp_init_funcp) \ + __cpp_exception_init(&(thread_ptr -> tx_thread_eh_globals)); \ + } +#endif + +#if (__GHS_VERSION_NUMBER >= 500) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) \ + { \ + extern void __tx_cpp_exception_cleanup(TX_THREAD *thread_ptr); \ + __tx_cpp_exception_cleanup(thread_ptr); \ + } +#else +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) \ + { \ + #pragma weak __cpp_exception_cleanup \ + extern void __cpp_exception_cleanup(void **); \ + static void (*const cpp_cleanup_funcp)(void **) = \ + __cpp_exception_cleanup; \ + if (cpp_cleanup_funcp) \ + __cpp_exception_cleanup(&(thread_ptr -> tx_thread_eh_globals)); \ + } +#endif + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + b = __CLZ32(m); \ + b = 31 - b; + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#if defined(__THUMB) + +unsigned int _tx_thread_interrupt_disable(void); +void _tx_thread_interrupt_restore(unsigned int new_posture); + +#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); + +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; + +#if defined(__GHS_VERSION_NUMBER) && (__GHS_VERSION_NUMBER >= 350) + +/* Define ThreadX interrupt lockout and restore macros using + compiler built-in functions if using Green Hills ARM compiler + version 3.5 or later. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_DISABLE interrupt_save = __GETSR(); \ + __SETSR(interrupt_save | 0xC0); + +#define TX_RESTORE __SETSR(interrupt_save); +#else +#define TX_DISABLE interrupt_save = __GETSR(); \ + __SETSR(interrupt_save | 0x80); + +#define TX_RESTORE __SETSR(interrupt_save); +#endif + +#else + +/* Define ThreadX interrupt lockout and restore macros using + asm macros if using Green Hills ARM compiler earlier than + version 3.5. */ + +asm int disable_ints(void) +{ +% + MRS r0,CPSR +#ifdef TX_BEFORE_ARMV6 +#ifdef TX_ENABLE_FIQ_SUPPORT + ORR r1,r0,0xC0 +#else + ORR r1,r0,0x80 +#endif + MSR CPSR_c,r1 +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if +#else + CPSID i +#endif +#endif +%error +} + +asm void restore_ints(int a) +{ +%reg a + MSR CPSR_c,a +%mem a + LDR r0,a + MSR CPSR_c,r0 +%error +} + +#define TX_DISABLE interrupt_save = disable_ints(); + +#define TX_RESTORE restore_ints(interrupt_save); +#endif +#endif + + +/* Define VFP extension for the Cortex-A8. Each is assumed to be called in the context of the executing + thread. */ + +void tx_thread_vfp_enable(void); +void tx_thread_vfp_disable(void); + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A9/Green Hills Version 6.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + diff --git a/ports/cortex_a9/green/readme_threadx.txt b/ports/cortex_a9/green/readme_threadx.txt new file mode 100644 index 00000000..18e4fcdf --- /dev/null +++ b/ports/cortex_a9/green/readme_threadx.txt @@ -0,0 +1,527 @@ + Microsoft's Azure RTOS ThreadX for Cortex-A9 + + Using the Green Hills Software Tools + +1. Open the ThreadX Project Workspace + +In order to build the ThreadX library and the ThreadX demonstration first load +the Azure RTOS Workspace azure_rtos_workspace.gpj, which is located inside the +"example_build" directory. + + +2. Building the ThreadX run-time Library + +Building the ThreadX library is easy; simply select the MULTI project file +tx.gpj and then select the build button. You should now observe the +compilation and assembly of the ThreadX library. This project build produces +the ThreadX library file tx.a. + + +3. Demonstration System + +The ThreadX demonstration is designed to execute under the MULTI environment +on the Green Hills Cortex-A9 simulator. The instructions that follow describe +how to get the ThreadX evaluation running under the MULTI Cortex-A9 simulation +environment. + +Building the demonstration is easy; simply select the MULTI project file +sample_threadx.gpj. At this point, select the "Project Build" button and observe +the compilation, assembly, and linkage of the ThreadX demonstration application. + +After the demonstration is built, invoke the MULTI ARM simulator by selecting +the simulator connection from within the sample_threadx.con connection file. +Once connected to the simulator, select the "Debug" button. You should now +observe the main function of sample_threadx.c. + +At this point, you should setup a simulated timer interrupt for ThreadX +by entering "timer 9999 irq" in the "target" window of the debugger. + +You are now ready to execute the ThreadX demonstration system. Select +breakpoints and data watches to observe the execution of the sample_threadx.c +application. + + +4. EventAnalyzer Demonstration + +To build a demonstration system that also logs events for the MULTI EventAnalyzer, +perform the same steps as the regular demo, except build the ThreadX library with +txe.gpj file and use the sample_threadx_el.gpj build file to build the demonstration. +The resulting image will log all system events, which can then be displayed by the +MULTI EventAnalyzer. + + +5. System Initialization + +The system entry point using the Green Hills tools is at the label _start. +This is defined within the crt0.arm file supplied by Green Hills. In addition, +this is where all static and global preset C variable initialization +processing is called from. + +After the Green Hills startup function returns, ThreadX initialization is +called. The main initialization function is _tx_initialize_low_level and +is located in the file tx_initialize_low_level.arm. This function is responsible +for setting up various system data structures, interrupt vectors, and the +periodic timer interrupt source of ThreadX. + +In addition, _tx_initialize_low_level determines where the first available +RAM memory address is located. This address is supplied to tx_application_define. + +By default, the first available RAM memory address is assumed to start at the +beginning of the ThreadX section .free_mem. If changes are made to the +sample_threadx.ld file, the .free_mem section should remain the last allocated +section in the main RAM area. The starting address of this section is passed +to tx_application_define. + + +6. User defines + +The following defines and their associated action are as follows: + + Define Meaning + + TX_ENABLE_IRQ_NESTING If defined, this brings in special IRQ + interrupt nesting logic into the ThreadX + library. This define should be applied + to the entire ThreadX library. + + TX_ENABLE_FIQ_NESTING If defined, this brings in special FIQ + interrupt nesting logic into the ThreadX + library. This define should be applied + to the entire ThreadX library and the + define TX_ENABLE_FIQ_SUPPORT should also + be defined. + + TX_ENABLE_FIQ_SUPPORT If defined, this brings in FIQ context + save and restore logic necessary for + applications to call ThreadX services from + FIQ interrupt handlers. This define + should be applied to the entire ThreadX + library. + + + TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, + this define causes basic ThreadX error + checking to be disabled. Please see + Chapter 4 in the "ThreadX User Guide" + for more details. + + TX_ENABLE_EVENT_LOGGING This define enables event logging for any + or all of the ThreadX source code. If this + option is used anywhere, the tx_initialize_high_level.c + file must be compiled with it as well, since this + is where the event log is initialized. + + TX_NO_EVENT_INFO This is a sub-option for event logging. + If this is enabled, only basic information + is saved in the log. + + TX_ENABLE_EVENT_FILTERS This is also a sub-option for event-logging. + If this is enabled, run-time filtering logic + is added to the event logging code. + + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By + default, this value is set to 32 priority levels. + + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found + in tx_port.h. + + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default + value is port-specific and is found in tx_port.h. + + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined + in tx_port.h. + + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. + By default, this option is not defined. + + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. + By default, this option is not defined. + + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is + not defined. + + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. + By default, this option is not defined. + + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. + By default, this option is not defined. + + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. + By default, this option is not defined. + + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size + and improves performance. + + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is + not defined. + + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is + not defined. + + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option + is not defined. + + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is + not defined. + + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is + not defined. + + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is + not defined. + + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is + not defined. + + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is + not defined. + + + +7. Register Usage and Stack Frames + +The Green Hills compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) +are scratch registers for each function. All other registers used by a C +function must be preserved by the function. ThreadX takes advantage of this +in situations where a context switch happens as a result of making a ThreadX +service call (which is itself a C function). In such cases, the saved +context of a thread is only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 CPSR CPSR + 0x08 r0 (a1) r4 (v1) + 0x0C r1 (a2) r5 (v2) + 0x10 r2 (a3) r6 (v3) + 0x14 r3 (a4) r7 (v4) + 0x18 r4 (v1) r8 (v5) + 0x1C r5 (v2) r9 (v6) + 0x20 r6 (v3) r10 (v7) + 0x24 r7 (v4) r11 (fp) + 0x28 r8 (v5) r14 (lr) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) + 0x3C r14 (lr) + 0x40 PC + + +8. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make ThreadX run faster, you can change the tx.gpj project +to disable debug information and enable the desired optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined before tx_api.h is included. + + +9. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-A9 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +9.1 Vector Area + +The Cortex-A9 vectors start at address zero. The demonstration system reset.arm +file contains the reset section (which contains all the ARM vectors) and is +typically loaded at address zero. On actual hardware platforms, this section +might have to be copied to address 0. + +9.2 IRQ ISRs + +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested +IRQ interrupts. The following sub-sections define the IRQ capabilities. + + +9.2.1 Standard IRQ ISRs + +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +is the default IRQ handler defined in tx_initialize_low_level.arm: + + + .globl __tx_irq_handler + .globl __tx_irq_processing_return +__tx_irq_handler: + + /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return: + + /* At this point execution is still in the IRQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. Note + that IRQ interrupts are still disabled upon return from the context + save function. */ + + /* Application ISR call(s) go here! */ + + /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +9.2.2 Vectored IRQ ISRs + +The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified +by the particular implementation. The following is an example IRQ handler defined in +tx_initialize_low_level.arm: + + .globl __tx_irq_example_handler +__tx_irq_example_handler: + + /* Call context save to save system context. */ + + STMDB sp!, {r0-r3} # Save some scratch registers + MRS r0, SPSR # Pickup saved SPSR + SUB lr, lr, #4 # Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} # Store other scratch registers + BL _tx_thread_vectored_context_save # Call the vectored IRQ context save + + /* At this point execution is still in the IRQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. Note + that IRQ interrupts are still disabled upon return from the context + save function. */ + + /* Application ISR call goes here! */ + + /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +9.2.3 Nested IRQ Support + +By default, nested IRQ interrupt support is not enabled. To enable nested +IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING +defined. With this defined, two new IRQ interrupt management services are +available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. +These function should be called between the IRQ context save and restore +calls. + +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +by switching from IRQ mode to SYS mode and enabling IRQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.arm. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables nesting +by disabling IRQ interrupts and switching back to IRQ mode in preparation for +the IRQ context restore service. + +The following is an example of enabling IRQ nested interrupts in the +typical IRQ handler: + + .globl __tx_irq_handler + .globl __tx_irq_processing_return +__tx_irq_handler: + + /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return: + + /* Enable nested IRQ interrupts. NOTE: Since this service returns + with IRQ interrupts enabled, all IRQ interrupt sources must be + cleared prior to calling this service. */ + BL _tx_thread_irq_nesting_start + + /* Application ISR call(s) go here! */ + + /* Disable nested IRQ interrupts. The mode is switched back to + IRQ mode and IRQ interrupts are disable upon return. */ + BL _tx_thread_irq_nesting_end + + /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +9.3 FIQ Interrupts + +By default, Cortex-A9 FIQ interrupts are left completely enabled by ThreadX. +Of course, this means that the application is fully responsible for +saving/restoring any registers used in the FIQ ISR processing. In addition, +no ThreadX service calls are allowed from the default FIQ ISRs. The default +FIQ interrupt shell is located in tx_initialize_low_level.arm. + +9.3.1 Managed FIQ Interrupts + +Full ThreadX management of FIQ interrupts is provided if the ThreadX sources +are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built +this way, the FIQ interrupt handlers are very similar to the IRQ interrupt +handlers defined previously. The following is default FIQ handler +defined in tx_initialize_low_level.arm: + + + .globl __tx_fiq_handler + .globl __tx_fiq_processing_return +__tx_fiq_handler: + + /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: + + /* At this point execution is still in the FIQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. */ + + /* Application FIQ handlers can be called here! */ + + /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +9.3.1.1 Nested FIQ Support + +By default, nested FIQ interrupt support is not enabled. To enable nested +FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING +defined. With this defined, two new FIQ interrupt management services are +available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. +These function should be called between the FIQ context save and restore +calls. + +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +by switching from FIQ mode to SYS mode and enabling FIQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.arm. When nested FIQ interrupts are no longer +required, calling the _tx_thread_fiq_nesting_end service disables nesting by +disabling FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +context restore service. + +The following is an example of enabling FIQ nested interrupts in the +typical FIQ handler: + + + .globl __tx_fiq_handler + .globl __tx_fiq_processing_return +__tx_fiq_handler: + + /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: + + /* At this point execution is still in the FIQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. */ + + /* Enable nested FIQ interrupts. NOTE: Since this service returns + with FIQ interrupts enabled, all FIQ interrupt sources must be + cleared prior to calling this service. */ + BL _tx_thread_fiq_nesting_start + + /* Application FIQ handlers can be called here! */ + + /* Disable nested FIQ interrupts. The mode is switched back to + FIQ mode and FIQ interrupts are disable upon return. */ + BL _tx_thread_fiq_nesting_end + + /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + + +10. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional. However, all other +ThreadX services are operational without a periodic timer source. + +To add the timer interrupt processing, simply make a call to +_tx_timer_interrupt in the IRQ processing. An example of this can be +found in the file tx_initialize_low_level.arm. + + +11. Thumb/Cortex-A9 Mixed Mode + +By default, ThreadX is setup for running in Cortex-A9 32-bit mode. This is +also true for the demonstration system. It is possible to build any +ThreadX file and/or the application in Thumb mode. The only exception +to this is the file tx_thread_shell_entry.c. This file must always be +built in 32-bit mode. + + +12. VFP Support + +By default, VFP support is disabled for each thread. If saving the context of the VFP registers +is needed, the following API call must be made from the context of the application thread - before +the VFP usage: + +void tx_thread_vfp_enable(void); + +After this API is called in the application, VFP registers will be saved/restored for this thread if it +is preempted via an interrupt. All other suspension of the this thread will not require the VFP registers +to be saved/restored. + +To disable VFP register context saving, simply call the following API: + +void tx_thread_vfp_disable(void); + + +13. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +05/19/2020 Initial ThreadX version of Cortex-A9/Green Hills port. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_a9/green/src/tx_thread_context_restore.arm b/ports/cortex_a9/green/src/tx_thread_context_restore.arm new file mode 100644 index 00000000..3b7ee0fd --- /dev/null +++ b/ports/cortex_a9/green/src/tx_thread_context_restore.arm @@ -0,0 +1,259 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # Disable IRQ and FIQ interrupts +#else + DISABLE_INTS = 0x80 # Disable IRQ interrupts +#endif + SVC_MODE = (0x13 | DISABLE_INTS) # SVC mode + IRQ_MODE = (0x12 | DISABLE_INTS) # IRQ mode + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore Cortex-A9/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores the interrupt context if it is processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_restore(VOID) +{ */ + .globl _tx_thread_context_restore +_tx_thread_context_restore: + + /* Lockout interrupts. */ + +#ifdef TX_BEFORE_ARMV6 + MRS r3, CPSR # Pickup current CPSR + ORR r0, r3, DISABLE_INTS # Build interrupt disable value + MSR CPSR_c, r0 # Lockout interrupts +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if # Disable IRQ and FIQ interrupts +#else + CPSID i # Disable IRQ interrupts +#endif +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR exit function to indicate an ISR is complete. */ + + BL _tx_execution_isr_exit # Call the ISR exit function +#endif + + /* Determine if interrupts are nested. */ + /* if (--_tx_thread_system_state) + { */ + + LDR r3, =_tx_thread_system_state # Pickup address of system state var + LDR r2, [r3] # Pickup system state + SUB r2, r2, 1 # Decrement the counter + STR r2, [r3] # Store the counter + CMP r2, 0 # Was this the first interrupt? + BEQ __tx_thread_not_nested_restore # If so, not a nested restore + + /* Interrupts are nested. */ + + /* Just recover the saved registers and return to the point of + interrupt. */ + + LDMIA sp!, {r0, r10, r12, lr} # Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 # Put SPSR back + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOVS pc, lr # Return to point of interrupt + + /* } */ +__tx_thread_not_nested_restore: + + /* Determine if a thread was interrupted and no preemption is required. */ + /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) + || (_tx_thread_preempt_disable)) + { */ + + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup actual current thread pointer + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_idle_system_restore # Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable # Pickup preempt disable address + LDR r2, [r3] # Pickup actual preempt disable flag + CMP r2, 0 # Is it set? + BNE __tx_thread_no_preempt_restore # Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr # Pickup address of execute thread ptr + LDR r2, [r3] # Pickup actual execute thread pointer + CMP r0, r2 # Is the same thread highest priority? + BNE __tx_thread_preempt_restore # No, preemption needs to happen + + +__tx_thread_no_preempt_restore: + + /* Restore interrupted thread or ISR. */ + + /* Pickup the saved stack pointer. */ + /* tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; */ + + /* Recover the saved context and return to the point of interrupt. */ + + LDMIA sp!, {r0, r10, r12, lr} # Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 # Put SPSR back + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOVS pc, lr # Return to point of interrupt + + /* } + else + { */ +__tx_thread_preempt_restore: + + LDMIA sp!, {r3, r10, r12, lr} # Recover temporarily saved registers + MOV r1, lr # Save lr (point of interrupt) + MOV r2, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r2 # Enter SVC mode + STR r1, [sp, -4]! # Save point of interrupt + STMDB sp!, {r4-r12, lr} # Save upper half of registers + MOV r4, r3 # Save SPSR in r4 + MOV r2, IRQ_MODE # Build IRQ mode CPSR + MSR CPSR_c, r2 # Re-enter IRQ mode + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOV r5, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r5 # Enter SVC mode + STMDB sp!, {r0-r3} # Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup current thread pointer + +#ifdef __VFP__ + LDR r2, [r0, 144] # Pickup the VFP enabled flag + CMP r2, 0 # Is the VFP enabled? + BEQ _tx_skip_irq_vfp_save # No, skip VFP IRQ save + VMRS r2, FPSCR # Pickup the FPSCR + STR r2, [sp, -4]! # Save FPSCR + VSTMDB sp!, {D16-D31} # Save D16-D31 + VSTMDB sp!, {D0-D15} # Save D0-D15 +_tx_skip_irq_vfp_save: +#endif + + MOV r3, 1 # Build interrupt stack type + STMDB sp!, {r3, r4} # Save interrupt stack type and SPSR + STR sp, [r0, 8] # Save stack pointer in thread control + /* # block */ + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r4, r0 # Save r0 + MOV r5, r1 # Save r1 + BL _tx_el_thread_preempted # Call thread preempted routine + MOV r0, r4 # Restore r0 + MOV r1, r5 # Restore r1 +#endif + + /* Save the remaining time-slice and disable it. */ + /* if (_tx_timer_time_slice) + { */ + + LDR r3, =_tx_timer_time_slice # Pickup time-slice variable address + LDR r2, [r3] # Pickup time-slice + CMP r2, 0 # Is it active? + BEQ __tx_thread_dont_save_ts # No, don't save it + + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + STR r2, [r0, 24] # Save thread's time-slice + MOV r2, 0 # Clear value + STR r2, [r3] # Disable global time-slice flag + + /* } */ +__tx_thread_dont_save_ts: + + + /* Clear the current task pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + MOV r0, 0 # NULL value + STR r0, [r1] # Clear current thread pointer + + /* Return to the scheduler. */ + /* _tx_thread_schedule(); */ + + B _tx_thread_schedule # Return to scheduler + /* } */ + +__tx_thread_idle_system_restore: + + /* Just return back to the scheduler! */ + + + MOV r3, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r3 # Lockout interrupts + B _tx_thread_schedule # Return to scheduler + + .type _tx_thread_context_restore,$function + .size _tx_thread_context_restore,.-_tx_thread_context_restore + +/* } */ + diff --git a/ports/cortex_a9/green/src/tx_thread_context_save.arm b/ports/cortex_a9/green/src/tx_thread_context_save.arm new file mode 100644 index 00000000..88c9ed9b --- /dev/null +++ b/ports/cortex_a9/green/src/tx_thread_context_save.arm @@ -0,0 +1,207 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # IRQ & FIQ interrupts disabled +#else + DISABLE_INTS = 0x80 # IRQ interrupts disabled +#endif + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save Cortex-A9/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_save(VOID) +{ */ + .globl _tx_thread_context_save +_tx_thread_context_save: + + /* Upon entry to this routine, it is assumed that IRQ interrupts are locked + out, we are in IRQ mode, and all registers are intact. */ + + /* Check for a nested interrupt condition. */ + /* if (_tx_thread_system_state++) + { */ + + STMDB sp!, {r0-r3} # Save some working registers + +#ifdef TX_ENABLE_FIQ_SUPPORT +#ifdef TX_BEFORE_ARMV6 + MRS r0, CPSR # Pickup the CPSR + ORR r0, r0, DISABLE_INTS # Build disable interrupt CPSR + MSR CPSR_c, r0 # Disable interrupts +#else + CPSID if # Disable FIQ interrupts +#endif +#endif + + LDR r3, =_tx_thread_system_state # Pickup address of system state var + LDR r2, [r3] # Pickup system state + CMP r2, 0 # Is this the first interrupt? + BEQ __tx_thread_not_nested_save # Yes, not a nested context save + + /* Nested interrupt condition. */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + + /* Save the rest of the scratch registers on the stack and return to the + calling ISR. */ + + MRS r0, SPSR # Pickup saved SPSR + SUB lr, lr, 4 # Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} # Store other registers + + /* Return to the ISR. */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + B __tx_irq_processing_return # Continue IRQ processing + +__tx_thread_not_nested_save: + /* } */ + + /* Otherwise, not nested, check to see if a thread was running. */ + /* else if (_tx_thread_current_ptr) + { */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup current thread pointer + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_idle_system_save # If so, interrupt occurred in + /* # scheduling loop - nothing needs saving! */ + + /* Save minimal context of interrupted thread. */ + + MRS r2, SPSR # Pickup saved SPSR + SUB lr, lr, 4 # Adjust point of interrupt + STMDB sp!, {r2, r10, r12, lr} # Store other registers + + /* Save the current stack pointer in the thread's control block. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ + + /* Switch to the system stack. */ + /* sp = _tx_thread_system_stack_ptr; */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + B __tx_irq_processing_return # Continue IRQ processing + + /* } + else + { */ + +__tx_thread_idle_system_save: + + /* Interrupt occurred in the scheduling loop. */ + + /* Not much to do here, just adjust the stack pointer, and return to IRQ + processing. */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + ADD sp, sp, 16 # Recover saved registers + B __tx_irq_processing_return # Continue IRQ processing + + .type _tx_thread_context_save,$function + .size _tx_thread_context_save,.-_tx_thread_context_save + + /* } +} */ + diff --git a/ports/cortex_a9/green/src/tx_thread_fiq_context_restore.arm b/ports/cortex_a9/green/src/tx_thread_fiq_context_restore.arm new file mode 100644 index 00000000..9f6fde91 --- /dev/null +++ b/ports/cortex_a9/green/src/tx_thread_fiq_context_restore.arm @@ -0,0 +1,264 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + SVC_MODE = 0xD3 # SVC mode + FIQ_MODE = 0xD1 # FIQ mode +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # Disable IRQ and FIQ interrupts +#else + DISABLE_INTS = 0x80 # Disable IRQ interrupts +#endif + MODE_MASK = 0x1F # Mode mask + IRQ_MODE_BITS = 0x12 # IRQ mode bits + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_context_restore Cortex-A9/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores the fiq interrupt context when processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* FIQ ISR Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_fiq_context_restore(VOID) +{ */ + .globl _tx_thread_fiq_context_restore +_tx_thread_fiq_context_restore: + + /* Lockout interrupts. */ + +#ifdef TX_BEFORE_ARMV6 + MRS r3, CPSR # Pickup current CPSR + ORR r0, r3, DISABLE_INTS # Build interrupt disable value + MSR CPSR_c, r0 # Lockout interrupts +#else + CPSID if # Disable IRQ and FIQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR exit function to indicate an ISR is complete. */ + + BL _tx_execution_isr_exit # Call the ISR exit function +#endif + + /* Determine if interrupts are nested. */ + /* if (--_tx_thread_system_state) + { */ + + LDR r3, =_tx_thread_system_state # Pickup address of system state var + LDR r2, [r3] # Pickup system state + SUB r2, r2, 1 # Decrement the counter + STR r2, [r3] # Store the counter + CMP r2, 0 # Was this the first interrupt? + BEQ __tx_thread_fiq_not_nested_restore # If so, not a nested restore + + /* Interrupts are nested. */ + + /* Just recover the saved registers and return to the point of + interrupt. */ + + LDMIA sp!, {r0, r10, r12, lr} # Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 # Put SPSR back + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOVS pc, lr # Return to point of interrupt + + /* } */ +__tx_thread_fiq_not_nested_restore: + + /* Determine if a thread was interrupted and no preemption is required. */ + /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) + || (_tx_thread_preempt_disable)) + { */ + + LDR r1, [sp] # Pickup the saved SPSR + MOV r2, MODE_MASK # Build mask to isolate the interrupted mode + AND r1, r1, r2 # Isolate mode bits + CMP r1, IRQ_MODE_BITS # Was an interrupt taken in IRQ mode before we + /* # got to context save? */ + BEQ __tx_thread_fiq_no_preempt_restore # Yes, just go back to point of interrupt + + + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup actual current thread pointer + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_fiq_idle_system_restore # Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable # Pickup preempt disable address + LDR r2, [r3] # Pickup actual preempt disable flag + CMP r2, 0 # Is it set? + BNE __tx_thread_fiq_no_preempt_restore # Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr # Pickup address of execute thread ptr + LDR r2, [r3] # Pickup actual execute thread pointer + CMP r0, r2 # Is the same thread highest priority? + BNE __tx_thread_fiq_preempt_restore # No, preemption needs to happen + + +__tx_thread_fiq_no_preempt_restore: + + /* Restore interrupted thread or ISR. */ + + /* Pickup the saved stack pointer. */ + /* tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; */ + + /* Recover the saved context and return to the point of interrupt. */ + + LDMIA sp!, {r0, lr} # Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 # Put SPSR back + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOVS pc, lr # Return to point of interrupt + + /* } + else + { */ +__tx_thread_fiq_preempt_restore: + + LDMIA sp!, {r3, lr} # Recover temporarily saved registers + MOV r1, lr # Save lr (point of interrupt) + MOV r2, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r2 # Enter SVC mode + STR r1, [sp, -4]! # Save point of interrupt + STMDB sp!, {r4-r12, lr} # Save upper half of registers + MOV r4, r3 # Save SPSR in r4 + MOV r2, FIQ_MODE # Build FIQ mode CPSR + MSR CPSR_c, r2 # Re-enter FIQ mode + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOV r5, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r5 # Enter SVC mode + STMDB sp!, {r0-r3} # Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup current thread pointer + +#ifdef __VFP__ + LDR r2, [r0, 144] # Pickup the VFP enabled flag + CMP r2, 0 # Is the VFP enabled? + BEQ _tx_skip_fiq_vfp_save # No, skip VFP IRQ save + VMRS r2, FPSCR # Pickup the FPSCR + STR r2, [sp, -4]! # Save FPSCR + VSTMDB sp!, {D16-D31} # Save D16-D31 + VSTMDB sp!, {D0-D15} # Save D0-D15 +_tx_skip_fiq_vfp_save: +#endif + + MOV r3, 1 # Build interrupt stack type + STMDB sp!, {r3, r4} # Save interrupt stack type and SPSR + STR sp, [r0, 8] # Save stack pointer in thread control + /* # block */ + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r4, r0 # Save r0 + MOV r5, r1 # Save r1 + BL _tx_el_thread_preempted # Call thread preempted routine + MOV r0, r4 # Restore r0 + MOV r1, r5 # Restore r1 +#endif + + /* Save the remaining time-slice and disable it. */ + /* if (_tx_timer_time_slice) + { */ + + LDR r3, =_tx_timer_time_slice # Pickup time-slice variable address + LDR r2, [r3] # Pickup time-slice + CMP r2, 0 # Is it active? + BEQ __tx_thread_fiq_dont_save_ts # No, don't save it + + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + STR r2, [r0, 24] # Save thread's time-slice + MOV r2, 0 # Clear value + STR r2, [r3] # Disable global time-slice flag + + /* } */ +__tx_thread_fiq_dont_save_ts: + + + /* Clear the current task pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + MOV r0, 0 # NULL value + STR r0, [r1] # Clear current thread pointer + + /* Return to the scheduler. */ + /* _tx_thread_schedule(); */ + + B _tx_thread_schedule # Return to scheduler + /* } */ + +__tx_thread_fiq_idle_system_restore: + + /* Just return back to the scheduler! */ + + ADD sp, sp, 24 # Recover FIQ stack space + MOV r3, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r3 # Lockout interrupts + B _tx_thread_schedule # Return to scheduler + + .type _tx_thread_fiq_context_restore,$function + .size _tx_thread_fiq_context_restore,.-_tx_thread_fiq_context_restore + +/* } */ + diff --git a/ports/cortex_a9/green/src/tx_thread_fiq_context_save.arm b/ports/cortex_a9/green/src/tx_thread_fiq_context_save.arm new file mode 100644 index 00000000..337622ab --- /dev/null +++ b/ports/cortex_a9/green/src/tx_thread_fiq_context_save.arm @@ -0,0 +1,197 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_context_save Cortex-A9/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_fiq_context_save(VOID) +{ */ + .globl _tx_thread_fiq_context_save +_tx_thread_fiq_context_save: + + /* Upon entry to this routine, it is assumed that IRQ interrupts are locked + out, we are in IRQ mode, and all registers are intact. */ + + /* Check for a nested interrupt condition. */ + /* if (_tx_thread_system_state++) + { */ + + STMDB sp!, {r0-r3} # Save some working registers + LDR r3, =_tx_thread_system_state # Pickup address of system state var + LDR r2, [r3] # Pickup system state + CMP r2, 0 # Is this the first interrupt? + BEQ __tx_thread_fiq_not_nested_save # Yes, not a nested context save + + /* Nested interrupt condition. */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + + /* Save the rest of the scratch registers on the stack and return to the + calling ISR. */ + + MRS r0, SPSR # Pickup saved SPSR + SUB lr, lr, 4 # Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} # Store other registers + + /* Return to the ISR. */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + B __tx_fiq_processing_return # Continue FIQ processing + +__tx_thread_fiq_not_nested_save: + /* } */ + + /* Otherwise, not nested, check to see if a thread was running. */ + /* else if (_tx_thread_current_ptr) + { */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup current thread pointer + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_fiq_idle_system_save # If so, interrupt occurred in + /* # scheduling loop - nothing needs saving! */ + + /* Save minimal context of interrupted thread. */ + + MRS r2, SPSR # Pickup saved SPSR + SUB lr, lr, 4 # Adjust point of interrupt + STMDB sp!, {r2, lr} # Store other registers, Note that we don't + /* # need to save sl and ip since FIQ has + # copies of these registers. Nested + # interrupt processing does need to save + # these registers. */ + + /* Save the current stack pointer in the thread's control block. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ + + /* Switch to the system stack. */ + /* sp = _tx_thread_system_stack_ptr; */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + B __tx_fiq_processing_return # Continue FIQ processing + + /* } + else + { */ + +__tx_thread_fiq_idle_system_save: + + /* Interrupt occurred in the scheduling loop. */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + /* Not much to do here, save the current SPSR and LR for possible + use in IRQ interrupted in idle system conditions, and return to + FIQ interrupt processing. */ + + MRS r0, SPSR # Pickup saved SPSR + SUB lr, lr, 4 # Adjust point of interrupt + STMDB sp!, {r0, lr} # Store other registers that will get used + /* # or stripped off the stack in context + # restore */ + B __tx_fiq_processing_return # Continue FIQ processing + + .type _tx_thread_fiq_context_save,$function + .size _tx_thread_fiq_context_save,.-_tx_thread_fiq_context_save + + /* } +} */ + diff --git a/ports/cortex_a9/green/src/tx_thread_fiq_nesting_end.arm b/ports/cortex_a9/green/src/tx_thread_fiq_nesting_end.arm new file mode 100644 index 00000000..5c5de37f --- /dev/null +++ b/ports/cortex_a9/green/src/tx_thread_fiq_nesting_end.arm @@ -0,0 +1,109 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # Disable IRQ and FIQ interrupts +#else + DISABLE_INTS = 0x80 # Disable IRQ interrupts +#endif + MODE_MASK = 0x1F # Mode mask + FIQ_MODE_BITS = 0x11 # FIQ mode bits + SVC_MODE_BITS = 0x13 # SVC mode value */ + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_nesting_end Cortex-A9/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from FIQ mode after */ +/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +/* processing from system mode back to FIQ mode prior to the ISR */ +/* calling _tx_thread_fiq_context_restore. Note that this function */ +/* assumes the system stack pointer is in the same position after */ +/* nesting start function was called. */ +/* */ +/* This function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.arm). */ +/* */ +/* This function returns with FIQ interrupts disabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_fiq_nesting_end(VOID) +{ */ + .globl _tx_thread_fiq_nesting_end +_tx_thread_fiq_nesting_end: + MOV r3,lr # Save ISR return address + MRS r0, CPSR # Pickup the CPSR + ORR r0, r0, DISABLE_INTS # Build disable interrupt value + MSR CPSR_c, r0 # Disable interrupts + LDR lr, [sp] # Pickup saved lr + ADD sp, sp, 4 # Adjust stack pointer + BIC r0, r0, MODE_MASK # Clear mode bits + ORR r0, r0, FIQ_MODE_BITS # Build IRQ mode CPSR + MSR CPSR_c, r0 # Re-enter IRQ mode + MOV pc, r3 # Return to ISR + + .type _tx_thread_fiq_nesting_end,$function + .size _tx_thread_fiq_nesting_end,.-_tx_thread_fiq_nesting_end +/* } */ + diff --git a/ports/cortex_a9/green/src/tx_thread_fiq_nesting_start.arm b/ports/cortex_a9/green/src/tx_thread_fiq_nesting_start.arm new file mode 100644 index 00000000..a2f57b23 --- /dev/null +++ b/ports/cortex_a9/green/src/tx_thread_fiq_nesting_start.arm @@ -0,0 +1,103 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + + FIQ_DISABLE = 0x40 # FIQ disable bit + MODE_MASK = 0x1F # Mode mask + SYS_MODE_BITS = 0x1F # System mode bits + + + .text + .align 4 + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_nesting_start Cortex-A9/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from FIQ mode after */ +/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +/* processing to the system mode so nested FIQ interrupt processing */ +/* is possible (system mode has its own "lr" register). Note that */ +/* this function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.arm). */ +/* */ +/* This function returns with FIQ interrupts enabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_fiq_nesting_start(VOID) +{ */ + .globl _tx_thread_fiq_nesting_start +_tx_thread_fiq_nesting_start: + MOV r3,lr # Save ISR return address + MRS r0, CPSR # Pickup the CPSR + BIC r0, r0, MODE_MASK # Clear the mode bits + ORR r0, r0, SYS_MODE_BITS # Build system mode CPSR + MSR CPSR_c, r0 # Enter system mode + STR lr, [sp, -4]! # Push the system mode lr on the system mode stack + BIC r0, r0, FIQ_DISABLE # Build enable FIQ CPSR + MSR CPSR_c, r0 # Enter system mode + MOV pc, r3 # Return to ISR + + .type _tx_thread_fiq_nesting_start,$function + .size _tx_thread_fiq_nesting_start,.-_tx_thread_fiq_nesting_start +/* } */ + diff --git a/ports/cortex_a9/green/src/tx_thread_interrupt_control.arm b/ports/cortex_a9/green/src/tx_thread_interrupt_control.arm new file mode 100644 index 00000000..c1533232 --- /dev/null +++ b/ports/cortex_a9/green/src/tx_thread_interrupt_control.arm @@ -0,0 +1,101 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" */ + + +#ifdef TX_ENABLE_FIQ_SUPPORT + INT_MASK = 0xC0 # Interrupt bit mask +#else + INT_MASK = 0x80 # Interrupt bit mask +#endif + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control Cortex-A9/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_control(UINT new_posture) +{ */ + .globl _tx_thread_interrupt_control +_tx_thread_interrupt_control: + + /* Pickup current interrupt lockout posture. */ + + MRS r3, CPSR # Pickup current CPSR + BIC r1, r3, INT_MASK # Clear interrupt lockout bits + ORR r1, r1, r0 # Or-in new interrupt lockout bits + + /* Apply the new interrupt posture. */ + + MSR CPSR_c, r1 # Setup new CPSR + AND r0, r3, INT_MASK # Return previous interrupt mask + RET # Return to caller + + .type _tx_thread_interrupt_control,$function + .size _tx_thread_interrupt_control,.-_tx_thread_interrupt_control +/* } */ + + + diff --git a/ports/cortex_a9/green/src/tx_thread_interrupt_disable.arm b/ports/cortex_a9/green/src/tx_thread_interrupt_disable.arm new file mode 100644 index 00000000..9ee497a9 --- /dev/null +++ b/ports/cortex_a9/green/src/tx_thread_interrupt_disable.arm @@ -0,0 +1,105 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" */ + + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # IRQ & FIQ interrupts disabled +#else + DISABLE_INTS = 0x80 # IRQ interrupts disabled +#endif + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_disable Cortex-A9/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for disabling interrupts */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_disable(void) +{ */ + .globl _tx_thread_interrupt_disable +_tx_thread_interrupt_disable: + + /* Pickup current interrupt lockout posture. */ + + MRS r0, CPSR # Pickup current CPSR + + /* Mask interrupts. */ + +#ifdef TX_BEFORE_ARMV6 + ORR r1, r0, DISABLE_INTS # Mask interrupts + MSR CPSR_c, r1 # Setup new CPSR +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if # Disable IRQ and FIQ +#else + CPSID i # Disable IRQ +#endif +#endif + + RET # Return previous CPSR value + + .type _tx_thread_interrupt_disable,$function + .size _tx_thread_interrupt_disable,.-_tx_thread_interrupt_disable +/* } */ + diff --git a/ports/cortex_a9/green/src/tx_thread_interrupt_restore.arm b/ports/cortex_a9/green/src/tx_thread_interrupt_restore.arm new file mode 100644 index 00000000..a8db80f8 --- /dev/null +++ b/ports/cortex_a9/green/src/tx_thread_interrupt_restore.arm @@ -0,0 +1,85 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" */ + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_restore Cortex-A9/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for restoring interrupts to the state */ +/* returned by a previous _tx_thread_interrupt_disable call. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_interrupt_restore(UINT new_posture) +{ */ + .globl _tx_thread_interrupt_restore +_tx_thread_interrupt_restore: + + /* Apply the new interrupt posture. */ + + MSR CPSR_c, r0 # Setup new CPSR + RET + + .type _tx_thread_interrupt_restore,$function + .size _tx_thread_interrupt_restore,.-_tx_thread_interrupt_restore +/* } */ + diff --git a/ports/cortex_a9/green/src/tx_thread_irq_nesting_end.arm b/ports/cortex_a9/green/src/tx_thread_irq_nesting_end.arm new file mode 100644 index 00000000..4dfb1075 --- /dev/null +++ b/ports/cortex_a9/green/src/tx_thread_irq_nesting_end.arm @@ -0,0 +1,109 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # Disable IRQ and FIQ interrupts +#else + DISABLE_INTS = 0x80 # Disable IRQ interrupts +#endif + MODE_MASK = 0x1F # Mode mask + IRQ_MODE_BITS = 0x12 # IRQ mode bits + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_irq_nesting_end Cortex-A9/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from IRQ mode after */ +/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +/* processing from system mode back to IRQ mode prior to the ISR */ +/* calling _tx_thread_context_restore. Note that this function */ +/* assumes the system stack pointer is in the same position after */ +/* nesting start function was called. */ +/* */ +/* This function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.arm). */ +/* */ +/* This function returns with IRQ interrupts disabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_irq_nesting_end(VOID) +{ */ + .globl _tx_thread_irq_nesting_end +_tx_thread_irq_nesting_end: + MOV r3,lr # Save ISR return address + MRS r0, CPSR # Pickup the CPSR + ORR r0, r0, DISABLE_INTS # Build disable interrupt value + MSR CPSR_c, r0 # Disable interrupts + LDR lr, [sp] # Pickup saved lr + ADD sp, sp, 4 # Adjust stack pointer + BIC r0, r0, MODE_MASK # Clear mode bits + ORR r0, r0, IRQ_MODE_BITS # Build IRQ mode CPSR + MSR CPSR_c, r0 # Re-enter IRQ mode + MOV pc, r3 # Return to ISR + + .type _tx_thread_irq_nesting_end,$function + .size _tx_thread_irq_nesting_end,.-_tx_thread_irq_nesting_end + +/* } */ + diff --git a/ports/cortex_a9/green/src/tx_thread_irq_nesting_start.arm b/ports/cortex_a9/green/src/tx_thread_irq_nesting_start.arm new file mode 100644 index 00000000..e9fbc1d4 --- /dev/null +++ b/ports/cortex_a9/green/src/tx_thread_irq_nesting_start.arm @@ -0,0 +1,102 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + + IRQ_DISABLE = 0x80 # IRQ disable bit + MODE_MASK = 0x1F # Mode mask + SYS_MODE_BITS = 0x1F # System mode bits + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_irq_nesting_start Cortex-A9/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from IRQ mode after */ +/* _tx_thread_context_save has been called and switches the IRQ */ +/* processing to the system mode so nested IRQ interrupt processing */ +/* is possible (system mode has its own "lr" register). Note that */ +/* this function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.arm). */ +/* */ +/* This function returns with IRQ interrupts enabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_irq_nesting_start(VOID) +{ */ + .globl _tx_thread_irq_nesting_start +_tx_thread_irq_nesting_start: + MOV r3,lr # Save ISR return address + MRS r0, CPSR # Pickup the CPSR + BIC r0, r0, MODE_MASK # Clear the mode bits + ORR r0, r0, SYS_MODE_BITS # Build system mode CPSR + MSR CPSR_c, r0 # Enter system mode + STR lr, [sp, -4]! # Push the system mode lr on the system mode stack + BIC r0, r0, IRQ_DISABLE # Build enable IRQ CPSR + MSR CPSR_c, r0 # Enter system mode + MOV pc, r3 # Return to ISR + + .type _tx_thread_irq_nesting_start,$function + .size _tx_thread_irq_nesting_start,.-_tx_thread_irq_nesting_start +/* } */ + diff --git a/ports/cortex_a9/green/src/tx_thread_schedule.arm b/ports/cortex_a9/green/src/tx_thread_schedule.arm new file mode 100644 index 00000000..8087d028 --- /dev/null +++ b/ports/cortex_a9/green/src/tx_thread_schedule.arm @@ -0,0 +1,254 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + ENABLE_INTS = 0xC0 # IRQ & FIQ Interrupts enabled mask +#else + ENABLE_INTS = 0x80 # IRQ Interrupts enabled mask +#endif + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule Cortex-A9/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* _tx_thread_context_restore Restore thread's context */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_schedule(VOID) +{ */ + .globl _tx_thread_schedule +_tx_thread_schedule: + + /* Enable interrupts. */ + +#ifdef TX_BEFORE_ARMV6 + MRS r2, CPSR # Pickup CPSR + BIC r0, r2, ENABLE_INTS # Clear the disable bit(s) + MSR CPSR_c, r0 # Enable interrupts +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSIE if # Enable IRQ and FIQ interrupts +#else + CPSIE i # Enable IRQ interrupts +#endif +#endif + + /* Wait for a thread to execute. */ + /* do + { */ + LDR r1, =_tx_thread_execute_ptr # Address of thread execute ptr + +__tx_thread_schedule_loop: + + LDR r0, [r1] # Pickup next thread to execute + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_schedule_loop # If so, keep looking for a thread + + /* } + while(_tx_thread_execute_ptr == TX_NULL); */ + + /* Yes! We have a thread to execute. Lockout interrupts and + transfer control to it. */ + +#ifdef TX_BEFORE_ARMV6 + MSR CPSR_c, r2 # Disable interrupts +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if # Disable IRQ and FIQ interrupts +#else + CPSID i # Disable IRQ interrupts +#endif +#endif + + /* Setup the current thread pointer. */ + /* _tx_thread_current_ptr = _tx_thread_execute_ptr; */ + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV v1, r0 # Save temp register in non-volatile register + BL _tx_el_thread_running # Call event logging routine + MOV r0, v1 # Restore temp register +#endif + + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread + STR r0, [r1] # Setup current thread pointer + + /* Increment the run count for this thread. */ + /* _tx_thread_current_ptr -> tx_thread_run_count++; */ + + LDR r2, [r0, 4] # Pickup run counter + LDR r3, [r0, 24] # Pickup time-slice for this thread + ADD r2, r2, 1 # Increment thread run-counter + STR r2, [r0, 4] # Store the new run counter + + /* Setup time-slice, if present. */ + /* _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; */ + + LDR r2, =_tx_timer_time_slice # Pickup address of time slice + /* # variable */ + LDR sp, [r0, 8] # Switch stack pointers + STR r3, [r2] # Setup time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread entry function to indicate the thread is executing. */ + + MOV r5, r0 # Save r0 + BL _tx_execution_thread_enter # Call the thread execution enter function + MOV r0, r5 # Restore r0 +#endif + + /* Switch to the thread's stack. */ + /* sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; */ + + /* Determine if an interrupt frame or a synchronous task suspension frame + is present. */ + + LDMIA sp!, {r4, r5} # Pickup the stack type and saved CPSR + CMP r4, 0 # Check for synchronous context switch + BEQ _tx_solicited_return + MSR SPSR_cxsf, r5 # Setup SPSR for return +#ifdef __VFP__ + LDR r1, [r0, 144] # Pickup the VFP enabled flag + CMP r1, 0 # Is the VFP enabled? + BEQ _tx_skip_interrupt_vfp_restore # No, skip VFP interrupt restore + VLDMIA sp!, {D0-D15} # Recover D0-D15 + VLDMIA sp!, {D16-D31} # Recover D16-D31 + LDR r4, [sp], 4 # Pickup FPSCR + VMSR FPSCR, r4 # Restore FPSCR +_tx_skip_interrupt_vfp_restore: +#endif + LDMIA sp!, {r0-r12, lr, pc}^ # Return to point of thread interrupt + +_tx_solicited_return: +#ifdef __VFP__ + LDR r1, [r0, 144] # Pickup the VFP enabled flag + CMP r1, 0 # Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_restore # No, skip VFP solicited restore + VLDMIA sp!, {D8-D15} # Recover D8-D15 + VLDMIA sp!, {D16-D31} # Recover D16-D31 + LDR r4, [sp], 4 # Pickup FPSCR + VMSR FPSCR, r4 # Restore FPSCR +_tx_skip_solicited_vfp_restore: +#endif + MSR CPSR_cxsf, r5 # Recover CPSR + LDMIA sp!, {r4-r11, lr} # Return to thread synchronously + RET # Return to caller (Thumb safe) + + .type _tx_thread_schedule,$function + .size _tx_thread_schedule,.-_tx_thread_schedule + +#ifdef __VFP__ + .globl tx_thread_vfp_enable +tx_thread_vfp_enable: + MRS r2, CPSR # Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSIE if # Enable IRQ and FIQ interrupts +#else + CPSIE i # Enable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr # Build current thread pointer address + LDR r1, [r0] # Pickup current thread pointer + CMP r1, 0 # Check for NULL thread pointer + BEQ __tx_no_thread_to_enable # If NULL, skip VFP enable + MOV r0, 1 # Build enable value + STR r0, [r1, 144] # Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_enable: + MSR CPSR_cxsf, r2 # Recover CPSR + RET # Return to caller (Thumb safe) + + .type tx_thread_vfp_enable,$function + .size tx_thread_vfp_enable,.-tx_thread_vfp_enable + + + .globl tx_thread_vfp_disable +tx_thread_vfp_disable: + MRS r2, CPSR # Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSIE if # Enable IRQ and FIQ interrupts +#else + CPSIE i # Enable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr # Build current thread pointer address + LDR r1, [r0] # Pickup current thread pointer + CMP r1, 0 # Check for NULL thread pointer + BEQ __tx_no_thread_to_disable # If NULL, skip VFP disable + MOV r0, 0 # Build disable value + STR r0, [r1, 144] # Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_disable: + MSR CPSR_cxsf, r2 # Recover CPSR + RET # Return to caller (Thumb safe) + + .type tx_thread_vfp_disable,$function + .size tx_thread_vfp_disable,.-tx_thread_vfp_disable + +#endif + +/* } */ + + + diff --git a/ports/cortex_a9/green/src/tx_thread_stack_build.arm b/ports/cortex_a9/green/src/tx_thread_stack_build.arm new file mode 100644 index 00000000..2bbdce05 --- /dev/null +++ b/ports/cortex_a9/green/src/tx_thread_stack_build.arm @@ -0,0 +1,161 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" */ + + SVC_MODE = 0x13 # SVC mode +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSR_MASK = 0xDF # Mask initial CPSR, IRQ & FIQ ints enabled +#else + CPSR_MASK = 0x9F # Mask initial CPSR, IRQ ints enabled +#endif + + THUMB_BIT = 0x20 # Thumb-bit + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build Cortex-A9/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +{ */ + .globl _tx_thread_stack_build +_tx_thread_stack_build: + + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-A9 should look like the following after it is built: + + Stack Top: 1 Interrupt stack frame type + CPSR Initial value for CPSR + r0 (a1) Initial value for r0 + r1 (a2) Initial value for r1 + r2 (a3) Initial value for r2 + r3 (a4) Initial value for r3 + r4 (v1) Initial value for r4 + r5 (v2) Initial value for r5 + r6 (v3) Initial value for r6 + r7 (v4) Initial value for r7 + r8 (v5) Initial value for r8 + r9 (sb) Initial value for r9 + r10 (sl) Initial value for r10 + r11 (fp) Initial value for r11 + r12 (ip) Initial value for r12 + lr Initial value for lr + pc Initial value for pc + 0 For stack backtracing + + Stack Bottom: (higher memory address) */ + + LDR r2, [r0, 16] # Pickup end of stack area + BIC r2, r2, 7 # Ensure 8-byte alignment + SUB r2, r2, 76 # Allocate space for the stack frame + + /* Actually build the stack frame. */ + + MOV r3, 1 # Build interrupt stack type + STR r3, [r2] # Store stack type + MOV r3, 0 # Build initial register value + STR r3, [r2, 8] # Store initial r0 + STR r3, [r2, 12] # Store initial r1 + STR r3, [r2, 16] # Store initial r2 + STR r3, [r2, 20] # Store initial r3 + STR r3, [r2, 24] # Store initial r4 + STR r3, [r2, 28] # Store initial r5 + STR r3, [r2, 32] # Store initial r6 + STR r3, [r2, 36] # Store initial r7 + STR r3, [r2, 40] # Store initial r8 + STR r3, [r2, 44] # Store initial r9 + LDR r3, [r0, 12] # Pickup stack starting address + STR r3, [r2, 48] # Store initial r10 + MOV r3, 0 # Build initial register value + STR r3, [r2, 52] # Store initial r11 + STR r3, [r2, 56] # Store initial r12 + STR r3, [r2, 60] # Store initial lr + STR r1, [r2, 64] # Store initial pc + STR r3, [r2, 68] # 0 for back-trace + + MRS r3, CPSR # Pickup CPSR + BIC r3, r3, CPSR_MASK # Mask mode bits of CPSR + ORR r3, r3, SVC_MODE # Build CPSR, SVC mode, interrupts enabled + BIC r3, r3, #THUMB_BIT # Clear Thumb-bit by default + AND r1, r1, #1 # Determine if the entry function is in Thumb mode + CMP r1, 1 # Is the Thumb-bit set? + ORREQ r3, r3, #THUMB_BIT # Yes, set the Thumb-bit + STR r3, [r2, 4] # Store initial CPSR + + /* Setup stack pointer. */ + /* thread_ptr -> tx_thread_stack_ptr = r2; */ + + STR r2, [r0, 8] # Save stack pointer in thread's + /* # control block */ + RET # Return to caller + + .type _tx_thread_stack_build,$function + .size _tx_thread_stack_build,.-_tx_thread_stack_build +/* } */ + diff --git a/ports/cortex_a9/green/src/tx_thread_system_return.arm b/ports/cortex_a9/green/src/tx_thread_system_return.arm new file mode 100644 index 00000000..1c4dedc4 --- /dev/null +++ b/ports/cortex_a9/green/src/tx_thread_system_return.arm @@ -0,0 +1,167 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # IRQ & FIQ interrupts disabled +#else + DISABLE_INTS = 0x80 # IRQ interrupts disabled +#endif + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return Cortex-A9/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the ThreadX system. Only a */ +/* minimal context is saved since the compiler assumes temp registers */ +/* are going to get slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_system_return(VOID) +{ */ + .globl _tx_thread_system_return +_tx_thread_system_return: + + /* Save minimal context on the stack. */ + + MOV r0, 0 # Build a solicited stack type + MRS r1, CPSR # Pickup the CPSR + STMDB sp!, {r4-r11, lr} # Save minimal context + + LDR r4, =_tx_thread_current_ptr # Pickup address of current ptr + LDR r5, [r4] # Pickup current thread pointer + +#ifdef __VFP__ + LDR r1, [r5, 144] # Pickup the VFP enabled flag + CMP r1, 0 # Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_save # No, skip VFP solicited save + VMRS r1, FPSCR # Pickup the FPSCR + STR r1, [sp, -4]! # Save FPSCR + VSTMDB sp!, {D16-D31} # Save D16-D31 + VSTMDB sp!, {D8-D15} # Save D8-D15 +_tx_skip_solicited_vfp_save: +#endif + + MOV r0, #0 # Build a solicited stack type + MRS r1, CPSR # Pickup the CPSR + STMDB sp!, {r0-r1} # Save type and CPSR + + /* Lockout interrupts. */ + +#ifdef TX_BEFORE_ARMV6 + ORR r2, r1, DISABLE_INTS # Build disable interrupt CPSR + MSR CPSR_c, r2 # Disable interrupts +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if # Disable IRQ and FIQ interrupts +#else + CPSID i # Disable IRQ interrutps +#endif +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread exit function to indicate the thread is no longer executing. */ + + BL _tx_execution_thread_exit # Call the thread exit function +#endif + + MOV r3, r4 # Pickup address of current ptr + MOV r0, r5 # Pickup current thread pointer + LDR r2, =_tx_timer_time_slice # Pickup address of time slice + LDR r1, [r2] # Pickup current time slice + + /* Save current stack and switch to system stack. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; + sp = _tx_thread_system_stack_ptr; */ + + STR sp, [r0, 8] # Save thread stack pointer + + /* Determine if the time-slice is active. */ + /* if (_tx_timer_time_slice) + { */ + + MOV r4, 0 # Build clear value + CMP r1, 0 # Is a time-slice active? + BEQ __tx_thread_dont_save_ts # No, don't save the current time-slice + + /* Save time-slice for the thread and clear the current time-slice. */ + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + STR r4, [r2, 0] # Clear time-slice + STR r1, [r0, 24] # Save current time-slice + + /* } */ +__tx_thread_dont_save_ts: + + /* Clear the current thread pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + STR r4, [r3] # Clear current thread pointer + B _tx_thread_schedule # Jump to scheduler! + + .type _tx_thread_system_return,$function + .size _tx_thread_system_return,.-_tx_thread_system_return +/* } */ + diff --git a/ports/cortex_a9/green/src/tx_thread_vectored_context_save.arm b/ports/cortex_a9/green/src/tx_thread_vectored_context_save.arm new file mode 100644 index 00000000..1398fbae --- /dev/null +++ b/ports/cortex_a9/green/src/tx_thread_vectored_context_save.arm @@ -0,0 +1,196 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # IRQ & FIQ interrupts disabled +#else + DISABLE_INTS = 0x80 # IRQ interrupts disabled +#endif + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_vectored_context_save Cortex-A9/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_vectored_context_save(VOID) +{ */ + .globl _tx_thread_vectored_context_save +_tx_thread_vectored_context_save: + + /* Upon entry to this routine, it is assumed that IRQ interrupts are locked + out, we are in IRQ mode, the minimal context is already saved, and the + lr register contains the return ISR address. */ + + /* Check for a nested interrupt condition. */ + /* if (_tx_thread_system_state++) + { */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#ifdef TX_BEFORE_ARMV6 + MRS r0, CPSR # Pickup the CPSR + ORR r0, r0, DISABLE_INTS # Build disable interrupt CPSR + MSR CPSR_c, r0 # Disable interrupts +#else + CPSID if # Disable IRQ and FIQ interrupts +#endif +#endif + LDR r3, =_tx_thread_system_state # Pickup address of system state var + LDR r2, [r3] # Pickup system state + CMP r2, 0 # Is this the first interrupt? + BEQ __tx_thread_not_nested_save # Yes, not a nested context save + + /* Nested interrupt condition. */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + + /* Note: Minimal context of interrupted thread is already saved. */ + + /* Return to the ISR. */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + MOV pc, lr # Return to caller + +__tx_thread_not_nested_save: + /* } */ + + /* Otherwise, not nested, check to see if a thread was running. */ + /* else if (_tx_thread_current_ptr) + { */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup current thread pointer + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_idle_system_save # If so, interrupt occurred in + /* # scheduling loop - nothing needs saving! */ + + /* Note: Minimal context of interrupted thread is already saved. */ + + /* Save the current stack pointer in the thread's control block. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ + + /* Switch to the system stack. */ + /* sp = _tx_thread_system_stack_ptr; */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + MOV pc, lr # Return to caller + + /* } + else + { */ + +__tx_thread_idle_system_save: + + /* Interrupt occurred in the scheduling loop. */ + + /* Not much to do here, just adjust the stack pointer, and return to IRQ + processing. */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + ADD sp, sp, 32 # Recover saved registers + MOV pc, lr # Return to caller + + .type _tx_thread_vectored_context_save,$function + .size _tx_thread_vectored_context_save,.-_tx_thread_vectored_context_save + + /* } +} */ + diff --git a/ports/cortex_a9/green/src/tx_timer_interrupt.arm b/ports/cortex_a9/green/src/tx_timer_interrupt.arm new file mode 100644 index 00000000..ac7a6ae9 --- /dev/null +++ b/ports/cortex_a9/green/src/tx_timer_interrupt.arm @@ -0,0 +1,241 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_timer.h" + #include "tx_thread.h" */ + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt Cortex-A9/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Process timer expiration */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_timer_interrupt(VOID) +{ */ + .globl _tx_timer_interrupt +_tx_timer_interrupt: + + /* Upon entry to this routine, it is assumed that context save has already + been called, and therefore the compiler scratch registers are available + for use. */ + + /* Increment the system clock. */ + /* _tx_timer_system_clock++; */ + + LDR r1, =_tx_timer_system_clock # Pickup address of system clock + LDR r0, [r1] # Pickup system clock + ADD r0, r0, 1 # Increment system clock + STR r0, [r1] # Store new system clock + + /* Test for time-slice expiration. */ + /* if (_tx_timer_time_slice) + { */ + + LDR r3, =_tx_timer_time_slice # Pickup address of time-slice + LDR r2, [r3] # Pickup time-slice + CMP r2, 0 # Is it non-active? + BEQ __tx_timer_no_time_slice # Yes, skip time-slice processing + + /* Decrement the time_slice. */ + /* _tx_timer_time_slice--; */ + + SUB r2, r2, 1 # Decrement the time-slice + STR r2, [r3] # Store new time-slice value + + /* Check for expiration. */ + /* if (__tx_timer_time_slice == 0) */ + + CMP r2, 0 # Has it expired? + BNE __tx_timer_no_time_slice # No, skip expiration processing + + /* Set the time-slice expired flag. */ + /* _tx_timer_expired_time_slice = TX_TRUE; */ + + LDR r3,=_tx_timer_expired_time_slice # Pickup address of expired flag + MOV r0, 1 # Build expired value + STR r0, [r3] # Set time-slice expiration flag + + /* } */ + +__tx_timer_no_time_slice: + + /* Test for timer expiration. */ + /* if (*_tx_timer_current_ptr) + { */ + + LDR r1, =_tx_timer_current_ptr # Pickup current timer pointer addr + LDR r0, [r1] # Pickup current timer + LDR r2, [r0] # Pickup timer list entry + CMP r2, 0 # Is there anything in the list? + BEQ __tx_timer_no_timer # No, just increment the timer + + /* Set expiration flag. */ + /* _tx_timer_expired = TX_TRUE; */ + + LDR r3, =_tx_timer_expired # Pickup expiration flag address + MOV r2, 1 # Build expired value + STR r2, [r3] # Set expired flag + B __tx_timer_done # Finished timer processing + + /* } + else + { */ +__tx_timer_no_timer: + + /* No timer expired, increment the timer pointer. */ + /* _tx_timer_current_ptr++; */ + + ADD r0, r0, 4 # Move to next timer + + /* Check for wrap-around. */ + /* if (_tx_timer_current_ptr == _tx_timer_list_end) */ + + LDR r3, =_tx_timer_list_end # Pickup addr of timer list end + LDR r2, [r3] # Pickup list end + CMP r0, r2 # Are we at list end? + BNE __tx_timer_skip_wrap # No, skip wrap-around logic + + /* Wrap to beginning of list. */ + /* _tx_timer_current_ptr = _tx_timer_list_start; */ + + LDR r3, =_tx_timer_list_start # Pickup addr of timer list start + LDR r0, [r3] # Set current pointer to list start + +__tx_timer_skip_wrap: + + STR r0, [r1] # Store new current timer pointer + /* } */ + +__tx_timer_done: + + + /* See if anything has expired. */ + /* if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) + { */ + + LDR r3, =_tx_timer_expired_time_slice # Pickup addr of expired flag + LDR r2, [r3] # Pickup time-slice expired flag + CMP r2, 0 # Did a time-slice expire? + BNE __tx_something_expired # If non-zero, time-slice expired + LDR r1, =_tx_timer_expired # Pickup addr of other expired flag + LDR r0, [r1] # Pickup timer expired flag + CMP r0, 0 # Did a timer expire? + BEQ __tx_timer_nothing_expired # No, nothing expired + +__tx_something_expired: + + + STMDB sp!, {r0, lr} # Save the lr register on the stack + /* # and save r0 just to keep 8-byte alignment */ + + /* Did a timer expire? */ + /* if (_tx_timer_expired) + { */ + + LDR r1, =_tx_timer_expired # Pickup addr of expired flag + LDR r0, [r1] # Pickup timer expired flag + CMP r0, 0 # Check for timer expiration + BEQ __tx_timer_dont_activate # If not set, skip timer activation + + /* Process the timer expiration. */ + /* _tx_timer_expiration_process(); */ + BL _tx_timer_expiration_process # Call the timer expiration handling routine + + /* } */ +__tx_timer_dont_activate: + + /* Did time slice expire? */ + /* if (_tx_timer_expired_time_slice) + { */ + + LDR r3, =_tx_timer_expired_time_slice # Pickup addr of time-slice expired + LDR r2, [r3] # Pickup the actual flag + CMP r2, 0 # See if the flag is set + BEQ __tx_timer_not_ts_expiration # No, skip time-slice processing + + /* Time slice interrupted thread. */ + /* _tx_thread_time_slice(); */ + + BL _tx_thread_time_slice # Call time-slice processing + + /* } */ +__tx_timer_not_ts_expiration: + + + LDMIA sp!, {r0, lr} # Recover lr register (r0 is just there for + /* # the 8-byte stack alignment */ + + /* } */ + +__tx_timer_nothing_expired: + + RET # Return to caller + + .type _tx_timer_interrupt,$function + .size _tx_timer_interrupt,.-_tx_timer_interrupt +/* } */ + diff --git a/ports/cortex_a9/iar/example_build/tx_initialize_low_level.s b/ports/cortex_a9/iar/example_build/tx_initialize_low_level.s index e9a16771..0dba479f 100644 --- a/ports/cortex_a9/iar/example_build/tx_initialize_low_level.s +++ b/ports/cortex_a9/iar/example_build/tx_initialize_low_level.s @@ -81,7 +81,7 @@ __tx_free_memory_start ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level Cortex-A9/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -114,7 +114,7 @@ __tx_free_memory_start ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_a9/iar/inc/tx_port.h b/ports/cortex_a9/iar/inc/tx_port.h index 4d6d1537..b67dafed 100644 --- a/ports/cortex_a9/iar/inc/tx_port.h +++ b/ports/cortex_a9/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A9/IAR */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -382,7 +382,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A9/IAR Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A9/IAR Version 6.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_a9/iar/readme_threadx.txt b/ports/cortex_a9/iar/readme_threadx.txt index f2221ee0..a9882a81 100644 --- a/ports/cortex_a9/iar/readme_threadx.txt +++ b/ports/cortex_a9/iar/readme_threadx.txt @@ -534,7 +534,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX version 6.0.1 for Cortex-A9 using IAR's ARM tools. +09-30-2020 Initial ThreadX version 6.1 for Cortex-A9 using IAR's ARM tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_a9/iar/src/tx_thread_context_restore.s b/ports/cortex_a9/iar/src/tx_thread_context_restore.s index fbdffc78..06b3e53d 100644 --- a/ports/cortex_a9/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_a9/iar/src/tx_thread_context_restore.s @@ -57,7 +57,7 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore Cortex-A9/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -89,7 +89,7 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_a9/iar/src/tx_thread_context_save.s b/ports/cortex_a9/iar/src/tx_thread_context_save.s index 63f4792a..220fe9eb 100644 --- a/ports/cortex_a9/iar/src/tx_thread_context_save.s +++ b/ports/cortex_a9/iar/src/tx_thread_context_save.s @@ -49,7 +49,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save Cortex-A9/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -80,7 +80,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_a9/iar/src/tx_thread_fiq_context_restore.s b/ports/cortex_a9/iar/src/tx_thread_fiq_context_restore.s index 566dcd15..0d6a7b02 100644 --- a/ports/cortex_a9/iar/src/tx_thread_fiq_context_restore.s +++ b/ports/cortex_a9/iar/src/tx_thread_fiq_context_restore.s @@ -58,7 +58,7 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_context_restore Cortex-A9/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -90,7 +90,7 @@ SVC_MODE_BITS DEFINE 0x13 ; SVC mode value ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_context_restore(VOID) diff --git a/ports/cortex_a9/iar/src/tx_thread_fiq_context_save.s b/ports/cortex_a9/iar/src/tx_thread_fiq_context_save.s index c60ea9a4..8b7572fc 100644 --- a/ports/cortex_a9/iar/src/tx_thread_fiq_context_save.s +++ b/ports/cortex_a9/iar/src/tx_thread_fiq_context_save.s @@ -42,7 +42,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_context_save Cortex-A9/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -73,7 +73,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ; VOID _tx_thread_fiq_context_save(VOID) diff --git a/ports/cortex_a9/iar/src/tx_thread_fiq_nesting_end.s b/ports/cortex_a9/iar/src/tx_thread_fiq_nesting_end.s index 15350c38..c40fe06e 100644 --- a/ports/cortex_a9/iar/src/tx_thread_fiq_nesting_end.s +++ b/ports/cortex_a9/iar/src/tx_thread_fiq_nesting_end.s @@ -44,7 +44,7 @@ FIQ_MODE_BITS DEFINE 0x11 ; FIQ mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_nesting_end Cortex-A9/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -83,7 +83,7 @@ FIQ_MODE_BITS DEFINE 0x11 ; FIQ mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_end(VOID) diff --git a/ports/cortex_a9/iar/src/tx_thread_fiq_nesting_start.s b/ports/cortex_a9/iar/src/tx_thread_fiq_nesting_start.s index 75cb6a98..799a7e3b 100644 --- a/ports/cortex_a9/iar/src/tx_thread_fiq_nesting_start.s +++ b/ports/cortex_a9/iar/src/tx_thread_fiq_nesting_start.s @@ -41,7 +41,7 @@ SYS_MODE_BITS DEFINE 0x1F ; System mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_nesting_start Cortex-A9/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ SYS_MODE_BITS DEFINE 0x1F ; System mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/cortex_a9/iar/src/tx_thread_interrupt_control.s b/ports/cortex_a9/iar/src/tx_thread_interrupt_control.s index 4ad92728..d47eceb5 100644 --- a/ports/cortex_a9/iar/src/tx_thread_interrupt_control.s +++ b/ports/cortex_a9/iar/src/tx_thread_interrupt_control.s @@ -41,7 +41,7 @@ INT_MASK DEFINE 0x80 ; Interrupt bit mask ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control Cortex-A9/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ INT_MASK DEFINE 0x80 ; Interrupt bit mask ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_a9/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_a9/iar/src/tx_thread_interrupt_disable.s index 31680cbb..15b4877b 100644 --- a/ports/cortex_a9/iar/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_a9/iar/src/tx_thread_interrupt_disable.s @@ -42,7 +42,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_disable Cortex-A9/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports/cortex_a9/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_a9/iar/src/tx_thread_interrupt_restore.s index 78eeeb68..41335c97 100644 --- a/ports/cortex_a9/iar/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_a9/iar/src/tx_thread_interrupt_restore.s @@ -34,7 +34,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-A9/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -64,7 +64,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;void _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_a9/iar/src/tx_thread_irq_nesting_end.s b/ports/cortex_a9/iar/src/tx_thread_irq_nesting_end.s index cb0976d2..a239b0fc 100644 --- a/ports/cortex_a9/iar/src/tx_thread_irq_nesting_end.s +++ b/ports/cortex_a9/iar/src/tx_thread_irq_nesting_end.s @@ -45,7 +45,7 @@ IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_irq_nesting_end Cortex-A9/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -84,7 +84,7 @@ IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports/cortex_a9/iar/src/tx_thread_irq_nesting_start.s b/ports/cortex_a9/iar/src/tx_thread_irq_nesting_start.s index 512ef7f2..67e3bddb 100644 --- a/ports/cortex_a9/iar/src/tx_thread_irq_nesting_start.s +++ b/ports/cortex_a9/iar/src/tx_thread_irq_nesting_start.s @@ -41,7 +41,7 @@ SYS_MODE_BITS DEFINE 0x1F ; System mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_irq_nesting_start Cortex-A9/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ SYS_MODE_BITS DEFINE 0x1F ; System mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_a9/iar/src/tx_thread_schedule.s b/ports/cortex_a9/iar/src/tx_thread_schedule.s index 4c8eabbf..2c713691 100644 --- a/ports/cortex_a9/iar/src/tx_thread_schedule.s +++ b/ports/cortex_a9/iar/src/tx_thread_schedule.s @@ -49,7 +49,7 @@ ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-A9/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_a9/iar/src/tx_thread_stack_build.s b/ports/cortex_a9/iar/src/tx_thread_stack_build.s index 04876d27..968bc296 100644 --- a/ports/cortex_a9/iar/src/tx_thread_stack_build.s +++ b/ports/cortex_a9/iar/src/tx_thread_stack_build.s @@ -43,7 +43,7 @@ CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints en ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build Cortex-A9/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -75,7 +75,7 @@ CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints en ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_a9/iar/src/tx_thread_system_return.s b/ports/cortex_a9/iar/src/tx_thread_system_return.s index 2e4e661d..f7911cdb 100644 --- a/ports/cortex_a9/iar/src/tx_thread_system_return.s +++ b/ports/cortex_a9/iar/src/tx_thread_system_return.s @@ -48,7 +48,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return Cortex-A9/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -80,7 +80,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_a9/iar/src/tx_thread_vectored_context_save.s b/ports/cortex_a9/iar/src/tx_thread_vectored_context_save.s index 54bf3ea3..391a911f 100644 --- a/ports/cortex_a9/iar/src/tx_thread_vectored_context_save.s +++ b/ports/cortex_a9/iar/src/tx_thread_vectored_context_save.s @@ -47,7 +47,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_vectored_context_save Cortex-A9/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -78,7 +78,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) diff --git a/ports/cortex_a9/iar/src/tx_timer_interrupt.s b/ports/cortex_a9/iar/src/tx_timer_interrupt.s index 629a76c5..400c1128 100644 --- a/ports/cortex_a9/iar/src/tx_timer_interrupt.s +++ b/ports/cortex_a9/iar/src/tx_timer_interrupt.s @@ -49,7 +49,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt Cortex-A9/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -83,7 +83,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s index 7c1a82e6..11b81ac8 100644 --- a/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s @@ -92,7 +92,7 @@ Reset_Handler ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level Cortex-M0/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -125,10 +125,7 @@ Reset_Handler ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_m0/ac5/inc/tx_port.h b/ports/cortex_m0/ac5/inc/tx_port.h index 31bb6d4d..ce6a88c2 100644 --- a/ports/cortex_m0/ac5/inc/tx_port.h +++ b/ports/cortex_m0/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M0/AC5 */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -318,7 +318,7 @@ unsigned int was_masked; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0/AC5 Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0/AC5 Version 6.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m0/ac5/readme_threadx.txt b/ports/cortex_m0/ac5/readme_threadx.txt index a5ddf83c..09f9cd83 100644 --- a/ports/cortex_m0/ac5/readme_threadx.txt +++ b/ports/cortex_m0/ac5/readme_threadx.txt @@ -133,12 +133,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -08-14-2020 ThreadX update of Cortex-M0/AC5 port. The following files were - changed/added for port specific version 6.0.2: - - *.s Modified comments and whitespace. - -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M0 using AC5 tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-M0 using AC5 tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_m0/ac5/src/tx_thread_context_restore.s b/ports/cortex_m0/ac5/src/tx_thread_context_restore.s index a461fc2a..8a85dc39 100644 --- a/ports/cortex_m0/ac5/src/tx_thread_context_restore.s +++ b/ports/cortex_m0/ac5/src/tx_thread_context_restore.s @@ -32,7 +32,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore Cortex-M0/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -66,10 +66,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m0/ac5/src/tx_thread_context_save.s b/ports/cortex_m0/ac5/src/tx_thread_context_save.s index 0b9606dd..cda02b79 100644 --- a/ports/cortex_m0/ac5/src/tx_thread_context_save.s +++ b/ports/cortex_m0/ac5/src/tx_thread_context_save.s @@ -33,7 +33,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save Cortex-M0/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -66,10 +66,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m0/ac5/src/tx_thread_interrupt_control.s b/ports/cortex_m0/ac5/src/tx_thread_interrupt_control.s index a615bda2..b083779b 100644 --- a/ports/cortex_m0/ac5/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m0/ac5/src/tx_thread_interrupt_control.s @@ -27,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control Cortex-M0/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -57,10 +57,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_m0/ac5/src/tx_thread_interrupt_disable.s b/ports/cortex_m0/ac5/src/tx_thread_interrupt_disable.s index 60c8eb0d..49eaf8a1 100644 --- a/ports/cortex_m0/ac5/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m0/ac5/src/tx_thread_interrupt_disable.s @@ -27,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_disable Cortex-M0/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -57,10 +57,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(UINT new_posture) diff --git a/ports/cortex_m0/ac5/src/tx_thread_interrupt_restore.s b/ports/cortex_m0/ac5/src/tx_thread_interrupt_restore.s index 8357b420..16995474 100644 --- a/ports/cortex_m0/ac5/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m0/ac5/src/tx_thread_interrupt_restore.s @@ -27,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-M0/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -57,10 +57,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_interrupt_restore(UINT new_posture) diff --git a/ports/cortex_m0/ac5/src/tx_thread_schedule.s b/ports/cortex_m0/ac5/src/tx_thread_schedule.s index 7c8c468a..d30a2fb6 100644 --- a/ports/cortex_m0/ac5/src/tx_thread_schedule.s +++ b/ports/cortex_m0/ac5/src/tx_thread_schedule.s @@ -39,7 +39,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M0/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -72,10 +72,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_m0/ac5/src/tx_thread_stack_build.s b/ports/cortex_m0/ac5/src/tx_thread_stack_build.s index 142c48a4..efff7a6a 100644 --- a/ports/cortex_m0/ac5/src/tx_thread_stack_build.s +++ b/ports/cortex_m0/ac5/src/tx_thread_stack_build.s @@ -27,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build Cortex-M0/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -59,10 +59,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_m0/ac5/src/tx_thread_system_return.s b/ports/cortex_m0/ac5/src/tx_thread_system_return.s index 58db7a75..1b90d79e 100644 --- a/ports/cortex_m0/ac5/src/tx_thread_system_return.s +++ b/ports/cortex_m0/ac5/src/tx_thread_system_return.s @@ -27,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return Cortex-M0/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -59,10 +59,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_m0/ac5/src/tx_timer_interrupt.s b/ports/cortex_m0/ac5/src/tx_timer_interrupt.s index eff615bf..c30d881a 100644 --- a/ports/cortex_m0/ac5/src/tx_timer_interrupt.s +++ b/ports/cortex_m0/ac5/src/tx_timer_interrupt.s @@ -42,7 +42,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt Cortex-M0/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -76,10 +76,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_m0/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_m0/ac6/example_build/sample_threadx/tx_initialize_low_level.S index 2ed5b0b4..9dc3ea55 100644 --- a/ports/cortex_m0/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports/cortex_m0/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -39,7 +39,7 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* FUNCTION RELEASE */ @/* */ @/* _tx_initialize_low_level Cortex-M0/AC6 */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -72,11 +72,7 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -@/* 08-14-2020 Scott Larson Modified comment(s), and */ -@/* commented out code for */ -@/* enabling DWT, */ -@/* resulting in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_m0/ac6/inc/tx_port.h b/ports/cortex_m0/ac6/inc/tx_port.h index 10e7557c..6205113d 100644 --- a/ports/cortex_m0/ac6/inc/tx_port.h +++ b/ports/cortex_m0/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M0/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -359,7 +359,7 @@ unsigned int interrupt_save; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0/AC6 Version 6.0.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0/AC6 Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_m0/ac6/readme_threadx.txt b/ports/cortex_m0/ac6/readme_threadx.txt index a68481bf..5cd3eb05 100644 --- a/ports/cortex_m0/ac6/readme_threadx.txt +++ b/ports/cortex_m0/ac6/readme_threadx.txt @@ -148,13 +148,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -08-14-2020 ThreadX update of Cortex-M0/AC6 port. The following files were - changed/added for port specific version 6.0.2: - - tx_initialize_low_level.S Comment out DWT code. - *.S Modified comments and whitespace. - -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M0 using AC6 tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-M0 using AC6 tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_m0/ac6/src/tx_thread_context_restore.S b/ports/cortex_m0/ac6/src/tx_thread_context_restore.S index 1432d485..38959c32 100644 --- a/ports/cortex_m0/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_m0/ac6/src/tx_thread_context_restore.S @@ -38,7 +38,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_restore Cortex-M0/AC6 */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -72,10 +72,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m0/ac6/src/tx_thread_context_save.S b/ports/cortex_m0/ac6/src/tx_thread_context_save.S index 6374ef8e..a83ba2a0 100644 --- a/ports/cortex_m0/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_m0/ac6/src/tx_thread_context_save.S @@ -33,7 +33,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_save Cortex-M0/AC6 */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -66,10 +66,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m0/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_m0/ac6/src/tx_thread_interrupt_control.S index 716ee64b..7d538cd4 100644 --- a/ports/cortex_m0/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m0/ac6/src/tx_thread_interrupt_control.S @@ -30,7 +30,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_control Cortex-M0/AC6 */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -60,10 +60,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @/* UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_m0/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_m0/ac6/src/tx_thread_interrupt_disable.S index 6712d457..eac3a523 100644 --- a/ports/cortex_m0/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m0/ac6/src/tx_thread_interrupt_disable.S @@ -30,7 +30,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_disable Cortex-M0/AC6 */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -59,10 +59,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @/* UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports/cortex_m0/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_m0/ac6/src/tx_thread_interrupt_restore.S index da390d82..5a702257 100644 --- a/ports/cortex_m0/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m0/ac6/src/tx_thread_interrupt_restore.S @@ -30,7 +30,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_restore Cortex-M0/AC6 */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -60,10 +60,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @/* VOID _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_m0/ac6/src/tx_thread_schedule.S b/ports/cortex_m0/ac6/src/tx_thread_schedule.S index 7fbe0bb6..8563a92f 100644 --- a/ports/cortex_m0/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_m0/ac6/src/tx_thread_schedule.S @@ -35,7 +35,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule Cortex-M0/AC6 */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -68,10 +68,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_m0/ac6/src/tx_thread_stack_build.S b/ports/cortex_m0/ac6/src/tx_thread_stack_build.S index 7e6e0244..cde38281 100644 --- a/ports/cortex_m0/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_m0/ac6/src/tx_thread_stack_build.S @@ -29,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_stack_build Cortex-M0/AC6 */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -61,10 +61,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_m0/ac6/src/tx_thread_system_return.S b/ports/cortex_m0/ac6/src/tx_thread_system_return.S index d9e87e43..9cc2834f 100644 --- a/ports/cortex_m0/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_m0/ac6/src/tx_thread_system_return.S @@ -29,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_system_return Cortex-M0/AC6 */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -61,10 +61,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @/* VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_m0/ac6/src/tx_timer_interrupt.S b/ports/cortex_m0/ac6/src/tx_timer_interrupt.S index acfee45e..8c4fe2a6 100644 --- a/ports/cortex_m0/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_m0/ac6/src/tx_timer_interrupt.S @@ -40,7 +40,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_timer_interrupt Cortex-M0/AC6 */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -74,10 +74,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_m0/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_m0/gnu/example_build/tx_initialize_low_level.S index c9e5ec34..b4c52df3 100644 --- a/ports/cortex_m0/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_m0/gnu/example_build/tx_initialize_low_level.S @@ -51,7 +51,7 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* FUNCTION RELEASE */ @/* */ @/* _tx_initialize_low_level Cortex-M0/GNU */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -85,10 +85,10 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 08-14-2020 Scott Larson Modified comment(s), and */ +@/* 09-30-2020 Scott Larson Modified comment(s), and */ @/* commented out code for */ @/* enabling DWT, */ -@/* resulting in version 6.0.2 */ +@/* resulting in version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_m0/gnu/inc/tx_port.h b/ports/cortex_m0/gnu/inc/tx_port.h index 2f798966..63d7d427 100644 --- a/ports/cortex_m0/gnu/inc/tx_port.h +++ b/ports/cortex_m0/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M0/GNU */ -/* 6.0 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ @@ -359,7 +361,7 @@ unsigned int interrupt_save; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0/GNU Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0/GNU Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_m0/gnu/readme_threadx.txt b/ports/cortex_m0/gnu/readme_threadx.txt index cdafb926..b3eef8d0 100644 --- a/ports/cortex_m0/gnu/readme_threadx.txt +++ b/ports/cortex_m0/gnu/readme_threadx.txt @@ -145,8 +145,8 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -08-14-2020 ThreadX update of Cortex-M0/GNU port. The following files were - changed/added for port specific version 6.0.2: +09-30-2020 ThreadX update of Cortex-M0/GNU port. The following files were + changed/added for port specific version 6.1: tx_initialize_low_level.S Comment out DWT code. *.S Modified comments and whitespace. diff --git a/ports/cortex_m0/gnu/src/tx_thread_context_restore.S b/ports/cortex_m0/gnu/src/tx_thread_context_restore.S index 19d94db9..fc453b61 100755 --- a/ports/cortex_m0/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_m0/gnu/src/tx_thread_context_restore.S @@ -39,7 +39,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_restore Cortex-M0/GNU */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -74,9 +74,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 Scott Larson Modified comment(s), and */ +@/* cleaned up whitespace, */ +@/* resulting in version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m0/gnu/src/tx_thread_context_save.S b/ports/cortex_m0/gnu/src/tx_thread_context_save.S index 501e826f..710f5e26 100755 --- a/ports/cortex_m0/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_m0/gnu/src/tx_thread_context_save.S @@ -34,7 +34,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_save Cortex-M0/GNU */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -68,9 +68,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 Scott Larson Modified comment(s), and */ +@/* cleaned up whitespace, */ +@/* resulting in version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m0/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_m0/gnu/src/tx_thread_interrupt_control.S index 828a080a..4854108c 100755 --- a/ports/cortex_m0/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m0/gnu/src/tx_thread_interrupt_control.S @@ -30,7 +30,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_control Cortex-M0/GNU */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -61,9 +61,8 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Modified comment(s), */ +@/* resulting in version 6.1 */ @/* */ @/**************************************************************************/ @/* UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_m0/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_m0/gnu/src/tx_thread_interrupt_disable.S index 8d6ffd0c..96c9f60c 100755 --- a/ports/cortex_m0/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m0/gnu/src/tx_thread_interrupt_disable.S @@ -30,7 +30,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_disable Cortex-M0/GNU */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -60,9 +60,8 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Modified comment(s), */ +@/* resulting in version 6.1 */ @/* */ @/**************************************************************************/ @/* UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports/cortex_m0/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_m0/gnu/src/tx_thread_interrupt_restore.S index c6163fb7..9591c805 100755 --- a/ports/cortex_m0/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m0/gnu/src/tx_thread_interrupt_restore.S @@ -30,7 +30,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_restore Cortex-M0/GNU */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -61,9 +61,8 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Modified comment(s), */ +@/* resulting in version 6.1 */ @/* */ @/**************************************************************************/ @/* VOID _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_m0/gnu/src/tx_thread_schedule.S b/ports/cortex_m0/gnu/src/tx_thread_schedule.S index 3b850788..788eddde 100755 --- a/ports/cortex_m0/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_m0/gnu/src/tx_thread_schedule.S @@ -37,7 +37,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule Cortex-M0/GNU */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -71,9 +71,8 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Modified comment(s), */ +@/* resulting in version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_m0/gnu/src/tx_thread_stack_build.S b/ports/cortex_m0/gnu/src/tx_thread_stack_build.S index bb0c6395..352739b1 100755 --- a/ports/cortex_m0/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_m0/gnu/src/tx_thread_stack_build.S @@ -29,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_stack_build Cortex-M0/GNU */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -62,14 +62,12 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 06-30-2020 William E. Lamie Modified Comment(s), setting */ -@/* R10 to top of stack is not */ -@/* needed. Removed references */ -@/* to stack frame, resulting */ -@/* in version 6.0.1 */ -@/* 08-14-2020 William E. Lamie Modified Comment(s), clean up */ +@/* 09-30-2020 William E. Lamie Modified Comment(s), setting */ +@/* R10 to top of stack is not */ +@/* needed. Removed references */ +@/* to stack frame, clean up */ @/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* in version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_m0/gnu/src/tx_thread_system_return.S b/ports/cortex_m0/gnu/src/tx_thread_system_return.S index e8cb536f..a6a9109e 100755 --- a/ports/cortex_m0/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_m0/gnu/src/tx_thread_system_return.S @@ -29,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_system_return Cortex-M0/GNU */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -62,9 +62,8 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Modified comment(s), */ +@/* resulting in version 6.1 */ @/* */ @/**************************************************************************/ @/* VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_m0/gnu/src/tx_timer_interrupt.S b/ports/cortex_m0/gnu/src/tx_timer_interrupt.S index 27fa6ec1..9a61b0d3 100755 --- a/ports/cortex_m0/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_m0/gnu/src/tx_timer_interrupt.S @@ -40,7 +40,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_timer_interrupt Cortex-M0/GNU */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -75,9 +75,8 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Modified comment(s), */ +@/* resulting in version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_m0/iar/example_build/tx_initialize_low_level.s b/ports/cortex_m0/iar/example_build/tx_initialize_low_level.s index 061505ff..ce79ceca 100644 --- a/ports/cortex_m0/iar/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m0/iar/example_build/tx_initialize_low_level.s @@ -46,7 +46,7 @@ __tx_free_memory_start ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level Cortex-M0/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -79,11 +79,7 @@ __tx_free_memory_start ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), and */ -;/* commented out code for */ -;/* enabling DWT, */ -;/* resulting in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_m0/iar/inc/tx_port.h b/ports/cortex_m0/iar/inc/tx_port.h index d4501e76..b8175994 100644 --- a/ports/cortex_m0/iar/inc/tx_port.h +++ b/ports/cortex_m0/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M0/IAR */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -349,7 +349,7 @@ __istate_t interrupt_save; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0/IAR Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0/IAR Version 6.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m0/iar/readme_threadx.txt b/ports/cortex_m0/iar/readme_threadx.txt index 0d528857..2be2813d 100644 --- a/ports/cortex_m0/iar/readme_threadx.txt +++ b/ports/cortex_m0/iar/readme_threadx.txt @@ -148,13 +148,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -08-14-2020 ThreadX update of Cortex-M0/IAR port. The following files were - changed/added for port specific version 6.0.2: - - tx_initialize_low_level.s Comment out DWT code. - *.s Modified comments and whitespace. - -06/30/2020 Initial ThreadX version 6.0.1 for Cortex-M0 using IAR's ARM tools. +09-30-2020 Initial ThreadX version 6.1 for Cortex-M0 using IAR's ARM tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_m0/iar/src/tx_thread_context_restore.s b/ports/cortex_m0/iar/src/tx_thread_context_restore.s index cae92740..0facd555 100644 --- a/ports/cortex_m0/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_m0/iar/src/tx_thread_context_restore.s @@ -38,7 +38,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore Cortex-M0/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -72,10 +72,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m0/iar/src/tx_thread_context_save.s b/ports/cortex_m0/iar/src/tx_thread_context_save.s index 1990adc9..6d9e8ec6 100644 --- a/ports/cortex_m0/iar/src/tx_thread_context_save.s +++ b/ports/cortex_m0/iar/src/tx_thread_context_save.s @@ -33,7 +33,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save Cortex-M0/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -66,10 +66,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m0/iar/src/tx_thread_interrupt_control.s b/ports/cortex_m0/iar/src/tx_thread_interrupt_control.s index c60541a2..781d2381 100644 --- a/ports/cortex_m0/iar/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m0/iar/src/tx_thread_interrupt_control.s @@ -28,7 +28,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control Cortex-M0/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -58,10 +58,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_m0/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_m0/iar/src/tx_thread_interrupt_disable.s index fe575c2d..f8413ffb 100644 --- a/ports/cortex_m0/iar/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m0/iar/src/tx_thread_interrupt_disable.s @@ -28,7 +28,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-M0/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -58,10 +58,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(UINT new_posture) diff --git a/ports/cortex_m0/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_m0/iar/src/tx_thread_interrupt_restore.s index 884f815e..a41e9cc5 100644 --- a/ports/cortex_m0/iar/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m0/iar/src/tx_thread_interrupt_restore.s @@ -28,7 +28,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-M0/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -58,10 +58,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_interrupt_restore(UINT new_posture) diff --git a/ports/cortex_m0/iar/src/tx_thread_schedule.s b/ports/cortex_m0/iar/src/tx_thread_schedule.s index 26ee0f12..02c60b6e 100644 --- a/ports/cortex_m0/iar/src/tx_thread_schedule.s +++ b/ports/cortex_m0/iar/src/tx_thread_schedule.s @@ -37,7 +37,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M0/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -70,10 +70,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_m0/iar/src/tx_thread_stack_build.s b/ports/cortex_m0/iar/src/tx_thread_stack_build.s index c688c01c..7e40608d 100644 --- a/ports/cortex_m0/iar/src/tx_thread_stack_build.s +++ b/ports/cortex_m0/iar/src/tx_thread_stack_build.s @@ -28,7 +28,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build Cortex-M0/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -60,10 +60,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_m0/iar/src/tx_thread_system_return.s b/ports/cortex_m0/iar/src/tx_thread_system_return.s index 83bc5617..f0abecf0 100644 --- a/ports/cortex_m0/iar/src/tx_thread_system_return.s +++ b/ports/cortex_m0/iar/src/tx_thread_system_return.s @@ -28,7 +28,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return Cortex-M0/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -60,10 +60,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_m0/iar/src/tx_timer_interrupt.s b/ports/cortex_m0/iar/src/tx_timer_interrupt.s index 1452a7de..df31bfb0 100644 --- a/ports/cortex_m0/iar/src/tx_timer_interrupt.s +++ b/ports/cortex_m0/iar/src/tx_timer_interrupt.s @@ -42,7 +42,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt Cortex-M0/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -76,10 +76,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_m0/keil/example_build/tx_initialize_low_level.s b/ports/cortex_m0/keil/example_build/tx_initialize_low_level.s index 992c196f..11b81ac8 100644 --- a/ports/cortex_m0/keil/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m0/keil/example_build/tx_initialize_low_level.s @@ -92,7 +92,7 @@ Reset_Handler ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level Cortex-M0/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -125,10 +125,7 @@ Reset_Handler ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) @@ -273,4 +270,3 @@ __tx_DBGHandler ALIGN LTORG END - diff --git a/ports/cortex_m0/keil/inc/tx_port.h b/ports/cortex_m0/keil/inc/tx_port.h index 104fc4de..593e734b 100644 --- a/ports/cortex_m0/keil/inc/tx_port.h +++ b/ports/cortex_m0/keil/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M0/AC5 */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -318,7 +318,7 @@ unsigned int was_masked; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0/AC5 Version 6.0.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0/AC5 Version 6.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m0/keil/readme_threadx.txt b/ports/cortex_m0/keil/readme_threadx.txt index c1c26b3d..44075b3a 100644 --- a/ports/cortex_m0/keil/readme_threadx.txt +++ b/ports/cortex_m0/keil/readme_threadx.txt @@ -139,12 +139,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -08-14-2020 ThreadX update of Cortex-M0/Keil port. The following files were - changed/added for port specific version 6.0.2: - - *.s Modified comments and whitespace. - -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M0 using Keil tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-M0 using Keil tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_m0/keil/src/tx_thread_context_restore.s b/ports/cortex_m0/keil/src/tx_thread_context_restore.s index 2c61ab0d..8a85dc39 100644 --- a/ports/cortex_m0/keil/src/tx_thread_context_restore.s +++ b/ports/cortex_m0/keil/src/tx_thread_context_restore.s @@ -32,7 +32,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore Cortex-M0/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -66,10 +66,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) @@ -93,4 +90,3 @@ _tx_thread_context_restore ALIGN LTORG END - diff --git a/ports/cortex_m0/keil/src/tx_thread_context_save.s b/ports/cortex_m0/keil/src/tx_thread_context_save.s index 834ab578..cda02b79 100644 --- a/ports/cortex_m0/keil/src/tx_thread_context_save.s +++ b/ports/cortex_m0/keil/src/tx_thread_context_save.s @@ -33,7 +33,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save Cortex-M0/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -66,10 +66,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -93,4 +90,3 @@ _tx_thread_context_save ALIGN LTORG END - diff --git a/ports/cortex_m0/keil/src/tx_thread_interrupt_control.s b/ports/cortex_m0/keil/src/tx_thread_interrupt_control.s index 8d8a6cac..b083779b 100644 --- a/ports/cortex_m0/keil/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m0/keil/src/tx_thread_interrupt_control.s @@ -27,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control Cortex-M0/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -57,10 +57,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) @@ -79,4 +76,3 @@ _tx_thread_interrupt_control ALIGN LTORG END - diff --git a/ports/cortex_m0/keil/src/tx_thread_interrupt_disable.s b/ports/cortex_m0/keil/src/tx_thread_interrupt_disable.s index 60c8eb0d..49eaf8a1 100644 --- a/ports/cortex_m0/keil/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m0/keil/src/tx_thread_interrupt_disable.s @@ -27,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_disable Cortex-M0/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -57,10 +57,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(UINT new_posture) diff --git a/ports/cortex_m0/keil/src/tx_thread_interrupt_restore.s b/ports/cortex_m0/keil/src/tx_thread_interrupt_restore.s index 8357b420..16995474 100644 --- a/ports/cortex_m0/keil/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m0/keil/src/tx_thread_interrupt_restore.s @@ -27,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-M0/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -57,10 +57,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_interrupt_restore(UINT new_posture) diff --git a/ports/cortex_m0/keil/src/tx_thread_schedule.s b/ports/cortex_m0/keil/src/tx_thread_schedule.s index 6222286d..c1699d87 100644 --- a/ports/cortex_m0/keil/src/tx_thread_schedule.s +++ b/ports/cortex_m0/keil/src/tx_thread_schedule.s @@ -39,7 +39,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M0/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -72,10 +72,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_m0/keil/src/tx_thread_stack_build.s b/ports/cortex_m0/keil/src/tx_thread_stack_build.s index 142c48a4..efff7a6a 100644 --- a/ports/cortex_m0/keil/src/tx_thread_stack_build.s +++ b/ports/cortex_m0/keil/src/tx_thread_stack_build.s @@ -27,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build Cortex-M0/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -59,10 +59,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_m0/keil/src/tx_thread_system_return.s b/ports/cortex_m0/keil/src/tx_thread_system_return.s index a896d2aa..1b90d79e 100644 --- a/ports/cortex_m0/keil/src/tx_thread_system_return.s +++ b/ports/cortex_m0/keil/src/tx_thread_system_return.s @@ -27,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return Cortex-M0/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -59,10 +59,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -87,4 +84,3 @@ _isr_context NOP ;} END - diff --git a/ports/cortex_m0/keil/src/tx_timer_interrupt.s b/ports/cortex_m0/keil/src/tx_timer_interrupt.s index eff615bf..c30d881a 100644 --- a/ports/cortex_m0/keil/src/tx_timer_interrupt.s +++ b/ports/cortex_m0/keil/src/tx_timer_interrupt.s @@ -42,7 +42,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt Cortex-M0/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -76,10 +76,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_m23/ac5/example_build/ARMCM23_TZ_config.txt b/ports/cortex_m23/ac5/example_build/ARMCM23_TZ_config.txt new file mode 100644 index 00000000..0d31ad76 --- /dev/null +++ b/ports/cortex_m23/ac5/example_build/ARMCM23_TZ_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2] +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +#---------------------------------------------------------------------------------------------- diff --git a/ports/cortex_m23/ac5/example_build/AzureRTOS.uvmpw b/ports/cortex_m23/ac5/example_build/AzureRTOS.uvmpw new file mode 100644 index 00000000..860a1c52 --- /dev/null +++ b/ports/cortex_m23/ac5/example_build/AzureRTOS.uvmpw @@ -0,0 +1,26 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + WorkSpace + + + .\demo_secure_zone\demo_secure_zone.uvprojx + 1 + + + + .\demo_threadx_non-secure_zone\demo_threadx_non-secure_zone.uvprojx + 1 + + + + .\ThreadX_Library.uvprojx + 1 + 1 + + + diff --git a/ports/cortex_m23/ac5/example_build/Debug.ini b/ports/cortex_m23/ac5/example_build/Debug.ini new file mode 100644 index 00000000..2a9dfba0 --- /dev/null +++ b/ports/cortex_m23/ac5/example_build/Debug.ini @@ -0,0 +1,4 @@ +LOAD "..\\demo_threadx_non-secure_zone\\Objects\\demo_threadx_non-secure_zone.axf" incremental +LOAD "..\\demo_secure_zone\\Objects\\demo_secure_zone.axf" incremental +RESET +g, \\demo_secure_zone\main_s\main \ No newline at end of file diff --git a/ports/cortex_m23/ac5/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h b/ports/cortex_m23/ac5/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h new file mode 100644 index 00000000..476361d7 --- /dev/null +++ b/ports/cortex_m23/ac5/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'ThreadX_Library' + * Target: 'ThreadX_Library_Project' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM23_TZ.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/ports/cortex_m23/ac5/example_build/ThreadX_Library.uvoptx b/ports/cortex_m23/ac5/example_build/ThreadX_Library.uvoptx new file mode 100644 index 00000000..0757f5f4 --- /dev/null +++ b/ports/cortex_m23/ac5/example_build/ThreadX_Library.uvoptx @@ -0,0 +1,2564 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + ThreadX_Library_Project + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 13 + + + + + + + + + + + BIN\UL2V8M.DLL + + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Source Group + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\..\..\common\src\tx_block_allocate.c + tx_block_allocate.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\common\src\tx_block_pool_cleanup.c + tx_block_pool_cleanup.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 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..\..\..\..\common\src\txe_mutex_info_get.c + + + txe_mutex_prioritize.c + 1 + ..\..\..\..\common\src\txe_mutex_prioritize.c + + + txe_mutex_put.c + 1 + ..\..\..\..\common\src\txe_mutex_put.c + + + txe_queue_create.c + 1 + ..\..\..\..\common\src\txe_queue_create.c + + + txe_queue_delete.c + 1 + ..\..\..\..\common\src\txe_queue_delete.c + + + txe_queue_flush.c + 1 + ..\..\..\..\common\src\txe_queue_flush.c + + + txe_queue_front_send.c + 1 + ..\..\..\..\common\src\txe_queue_front_send.c + + + txe_queue_info_get.c + 1 + ..\..\..\..\common\src\txe_queue_info_get.c + + + txe_queue_prioritize.c + 1 + ..\..\..\..\common\src\txe_queue_prioritize.c + + + txe_queue_receive.c + 1 + ..\..\..\..\common\src\txe_queue_receive.c + + + txe_queue_send.c + 1 + ..\..\..\..\common\src\txe_queue_send.c + + + txe_queue_send_notify.c + 1 + ..\..\..\..\common\src\txe_queue_send_notify.c + + + txe_semaphore_ceiling_put.c + 1 + ..\..\..\..\common\src\txe_semaphore_ceiling_put.c + + + txe_semaphore_create.c + 1 + ..\..\..\..\common\src\txe_semaphore_create.c + + + txe_semaphore_delete.c + 1 + ..\..\..\..\common\src\txe_semaphore_delete.c + + + txe_semaphore_get.c + 1 + ..\..\..\..\common\src\txe_semaphore_get.c + + + txe_semaphore_info_get.c + 1 + ..\..\..\..\common\src\txe_semaphore_info_get.c + + + txe_semaphore_prioritize.c + 1 + ..\..\..\..\common\src\txe_semaphore_prioritize.c + + + txe_semaphore_put.c + 1 + ..\..\..\..\common\src\txe_semaphore_put.c + + + txe_semaphore_put_notify.c + 1 + ..\..\..\..\common\src\txe_semaphore_put_notify.c + + + txe_thread_create.c + 1 + ..\..\..\..\common\src\txe_thread_create.c + + + txe_thread_delete.c + 1 + ..\..\..\..\common\src\txe_thread_delete.c + + + txe_thread_entry_exit_notify.c + 1 + ..\..\..\..\common\src\txe_thread_entry_exit_notify.c + + + txe_thread_info_get.c + 1 + ..\..\..\..\common\src\txe_thread_info_get.c + + + txe_thread_preemption_change.c + 1 + ..\..\..\..\common\src\txe_thread_preemption_change.c + + + txe_thread_priority_change.c + 1 + ..\..\..\..\common\src\txe_thread_priority_change.c + + + txe_thread_relinquish.c + 1 + ..\..\..\..\common\src\txe_thread_relinquish.c + + + txe_thread_reset.c + 1 + ..\..\..\..\common\src\txe_thread_reset.c + + + txe_thread_resume.c + 1 + ..\..\..\..\common\src\txe_thread_resume.c + + + txe_thread_suspend.c + 1 + ..\..\..\..\common\src\txe_thread_suspend.c + + + txe_thread_terminate.c + 1 + ..\..\..\..\common\src\txe_thread_terminate.c + + + txe_thread_time_slice_change.c + 1 + ..\..\..\..\common\src\txe_thread_time_slice_change.c + + + txe_thread_wait_abort.c + 1 + ..\..\..\..\common\src\txe_thread_wait_abort.c + + + txe_timer_activate.c + 1 + ..\..\..\..\common\src\txe_timer_activate.c + + + txe_timer_change.c + 1 + ..\..\..\..\common\src\txe_timer_change.c + + + txe_timer_create.c + 1 + ..\..\..\..\common\src\txe_timer_create.c + + + txe_timer_deactivate.c + 1 + ..\..\..\..\common\src\txe_timer_deactivate.c + + + txe_timer_delete.c + 1 + ..\..\..\..\common\src\txe_timer_delete.c + + + txe_timer_info_get.c + 1 + ..\..\..\..\common\src\txe_timer_info_get.c + + + tx_timer_interrupt.s + 2 + ..\src\tx_timer_interrupt.s + + + tx_thread_context_restore.s + 2 + ..\src\tx_thread_context_restore.s + + + tx_thread_context_save.s + 2 + ..\src\tx_thread_context_save.s + + + tx_thread_interrupt_control.s + 2 + ..\src\tx_thread_interrupt_control.s + + + tx_thread_schedule.s + 2 + ..\src\tx_thread_schedule.s + + + tx_thread_stack_build.s + 2 + ..\src\tx_thread_stack_build.s + + + tx_thread_system_return.s + 2 + ..\src\tx_thread_system_return.s + + + tx_trace_buffer_full_notify.c + 1 + ..\..\..\..\common\src\tx_trace_buffer_full_notify.c + + + tx_trace_event_filter.c + 1 + ..\..\..\..\common\src\tx_trace_event_filter.c + + + tx_trace_event_unfilter.c + 1 + ..\..\..\..\common\src\tx_trace_event_unfilter.c + + + tx_thread_interrupt_disable.s + 2 + ..\src\tx_thread_interrupt_disable.s + + + tx_thread_interrupt_restore.s + 2 + ..\src\tx_thread_interrupt_restore.s + + + txe_thread_secure_stack_allocate.c + 1 + ..\src\txe_thread_secure_stack_allocate.c + + + txe_thread_secure_stack_free.c + 1 + ..\src\txe_thread_secure_stack_free.c + + + tx_thread_secure_stack_allocate.s + 2 + ..\src\tx_thread_secure_stack_allocate.s + + + tx_thread_secure_stack_free.s + 2 + ..\src\tx_thread_secure_stack_free.s + + + tx_initialize_low_level.s + 2 + .\tx_initialize_low_level.s + + + tx_thread_stack_error_handler.c + 1 + ..\src\tx_thread_stack_error_handler.c + + + tx_thread_stack_error_notify.c + 1 + ..\src\tx_thread_stack_error_notify.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/ports/cortex_m23/ac5/example_build/demo_secure_zone/Abstract.txt b/ports/cortex_m23/ac5/example_build/demo_secure_zone/Abstract.txt new file mode 100644 index 00000000..0d1d8c52 --- /dev/null +++ b/ports/cortex_m23/ac5/example_build/demo_secure_zone/Abstract.txt @@ -0,0 +1,19 @@ +This ARM Cortex-M33 secure/non-secure example project that +shows the setup of the CMSIS-RTOS2 RTX for TrustZone for +ARMv8-M applications. + +The application uses CMSIS and can be executed on a Fixed +Virtual Platform (FVP) simulation model. The application +demonstrates three RTOS threads. + + +Secure application: + - Setup code and start non-secure application. + +Non-secure application: + - Calls a secure function from non-secure state. + - Calls a secure function that call back to a non-secure function. + +Output: +Variables used in this application can be viewed in the Debugger +Watch window. \ No newline at end of file diff --git a/ports/cortex_m23/ac5/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/ARMCM23_ac6.sct b/ports/cortex_m23/ac5/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/ARMCM23_ac6.sct new file mode 100644 index 00000000..abbe02af --- /dev/null +++ b/ports/cortex_m23/ac5/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/ARMCM23_ac6.sct @@ -0,0 +1,74 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc +; command above MUST be in first line (no comment above!) + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x00000000 +#define __ROM_SIZE 0x00080000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00040000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000200 +#define __HEAP_SIZE 0x00000C00 + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundery definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ +#define __RO_BASE __ROM_BASE +#define __RO_SIZE __ROM_SIZE + +#define __RW_BASE (__RAM_BASE ) +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) + + + +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) +; *(Veneer$$CMSE) ; uncomment for secure applications + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } +} diff --git a/ports/cortex_m23/ac5/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h b/ports/cortex_m23/ac5/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h new file mode 100644 index 00000000..a7a090e7 --- /dev/null +++ b/ports/cortex_m23/ac5/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h @@ -0,0 +1,832 @@ +/**************************************************************************//** + * @file partition_ARMCM23.h + * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM23 + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PARTITION_ARMCM23_H +#define PARTITION_ARMCM23_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 1 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x00200000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x003FFFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x20200000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x203FFFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x40040000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 1 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 1 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 1 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x80-0xFF +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 1 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + + +/* +// Setup behaviour of single SysTick +*/ +#define SCB_ICSR_INIT 0 + +/* +// in a single SysTick implementation, SysTick is +// <0=>Secure +// <1=>Non-Secure +// Value for SCB->ICSR register bit STTNS +// only for single SysTick implementation +*/ +#define SCB_ICSR_STTNS_VAL 0 + +/* +// +*/ + + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// Interrupt 0 <0=> Secure state <1=> Non-Secure state +// Interrupt 1 <0=> Secure state <1=> Non-Secure state +// Interrupt 2 <0=> Secure state <1=> Non-Secure state +// Interrupt 3 <0=> Secure state <1=> Non-Secure state +// Interrupt 4 <0=> Secure state <1=> Non-Secure state +// Interrupt 5 <0=> Secure state <1=> Non-Secure state +// Interrupt 6 <0=> Secure state <1=> Non-Secure state +// Interrupt 7 <0=> Secure state <1=> Non-Secure state +// Interrupt 8 <0=> Secure state <1=> Non-Secure state +// Interrupt 9 <0=> Secure state <1=> Non-Secure state +// Interrupt 10 <0=> Secure state <1=> Non-Secure state +// Interrupt 11 <0=> Secure state <1=> Non-Secure state +// Interrupt 12 <0=> Secure state <1=> Non-Secure state +// Interrupt 13 <0=> Secure state <1=> Non-Secure state +// Interrupt 14 <0=> Secure state <1=> Non-Secure state +// Interrupt 15 <0=> Secure state <1=> Non-Secure state +// Interrupt 16 <0=> Secure state <1=> Non-Secure state +// Interrupt 17 <0=> Secure state <1=> Non-Secure state +// Interrupt 18 <0=> Secure state <1=> Non-Secure state +// Interrupt 19 <0=> Secure state <1=> Non-Secure state +// Interrupt 20 <0=> Secure state <1=> Non-Secure state +// Interrupt 21 <0=> Secure state <1=> Non-Secure state +// Interrupt 22 <0=> Secure state <1=> Non-Secure state +// Interrupt 23 <0=> Secure state <1=> Non-Secure state +// Interrupt 24 <0=> Secure state <1=> Non-Secure state +// Interrupt 25 <0=> Secure state <1=> Non-Secure state +// Interrupt 26 <0=> Secure state <1=> Non-Secure state +// Interrupt 27 <0=> Secure state <1=> Non-Secure state +// Interrupt 28 <0=> Secure state <1=> Non-Secure state +// Interrupt 29 <0=> Secure state <1=> Non-Secure state +// Interrupt 30 <0=> Secure state <1=> Non-Secure state +// Interrupt 31 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// Interrupt 32 <0=> Secure state <1=> Non-Secure state +// Interrupt 33 <0=> Secure state <1=> Non-Secure state +// Interrupt 34 <0=> Secure state <1=> Non-Secure state +// Interrupt 35 <0=> Secure state <1=> Non-Secure state +// Interrupt 36 <0=> Secure state <1=> Non-Secure state +// Interrupt 37 <0=> Secure state <1=> Non-Secure state +// Interrupt 38 <0=> Secure state <1=> Non-Secure state +// Interrupt 39 <0=> Secure state <1=> Non-Secure state +// Interrupt 40 <0=> Secure state <1=> Non-Secure state +// Interrupt 41 <0=> Secure state <1=> Non-Secure state +// Interrupt 42 <0=> Secure state <1=> Non-Secure state +// Interrupt 43 <0=> Secure state <1=> Non-Secure state +// Interrupt 44 <0=> Secure state <1=> Non-Secure state +// Interrupt 45 <0=> Secure state <1=> Non-Secure state +// Interrupt 46 <0=> Secure state <1=> Non-Secure state +// Interrupt 47 <0=> Secure state <1=> Non-Secure state +// Interrupt 48 <0=> Secure state <1=> Non-Secure state +// Interrupt 49 <0=> Secure state <1=> Non-Secure state +// Interrupt 50 <0=> Secure state <1=> Non-Secure state +// Interrupt 51 <0=> Secure state <1=> Non-Secure state +// Interrupt 52 <0=> Secure state <1=> Non-Secure state +// Interrupt 53 <0=> Secure state <1=> Non-Secure state +// Interrupt 54 <0=> Secure state <1=> Non-Secure state +// Interrupt 55 <0=> Secure state <1=> Non-Secure state +// Interrupt 56 <0=> Secure state <1=> Non-Secure state +// Interrupt 57 <0=> Secure state <1=> Non-Secure state +// Interrupt 58 <0=> Secure state <1=> Non-Secure state +// Interrupt 59 <0=> Secure state <1=> Non-Secure state +// Interrupt 60 <0=> Secure state <1=> Non-Secure state +// Interrupt 61 <0=> Secure state <1=> Non-Secure state +// Interrupt 62 <0=> Secure state <1=> Non-Secure state +// Interrupt 63 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 0 + +/* +// Interrupts 64..95 +// Interrupt 64 <0=> Secure state <1=> Non-Secure state +// Interrupt 65 <0=> Secure state <1=> Non-Secure state +// Interrupt 66 <0=> Secure state <1=> Non-Secure state +// Interrupt 67 <0=> Secure state <1=> Non-Secure state +// Interrupt 68 <0=> Secure state <1=> Non-Secure state +// Interrupt 69 <0=> Secure state <1=> Non-Secure state +// Interrupt 70 <0=> Secure state <1=> Non-Secure state +// Interrupt 71 <0=> Secure state <1=> Non-Secure state +// Interrupt 72 <0=> Secure state <1=> Non-Secure state +// Interrupt 73 <0=> Secure state <1=> Non-Secure state +// Interrupt 74 <0=> Secure state <1=> Non-Secure state +// Interrupt 75 <0=> Secure state <1=> Non-Secure state +// Interrupt 76 <0=> Secure state <1=> Non-Secure state +// Interrupt 77 <0=> Secure state <1=> Non-Secure state +// Interrupt 78 <0=> Secure state <1=> Non-Secure state +// Interrupt 79 <0=> Secure state <1=> Non-Secure state +// Interrupt 80 <0=> Secure state <1=> Non-Secure state +// Interrupt 81 <0=> Secure state <1=> Non-Secure state +// Interrupt 82 <0=> Secure state <1=> Non-Secure state +// Interrupt 83 <0=> Secure state <1=> Non-Secure state +// Interrupt 84 <0=> Secure state <1=> Non-Secure state +// Interrupt 85 <0=> Secure state <1=> Non-Secure state +// Interrupt 86 <0=> Secure state <1=> Non-Secure state +// Interrupt 87 <0=> Secure state <1=> Non-Secure state +// Interrupt 88 <0=> Secure state <1=> Non-Secure state +// Interrupt 89 <0=> Secure state <1=> Non-Secure state +// Interrupt 90 <0=> Secure state <1=> Non-Secure state +// Interrupt 91 <0=> Secure state <1=> Non-Secure state +// Interrupt 92 <0=> Secure state <1=> Non-Secure state +// Interrupt 93 <0=> Secure state <1=> Non-Secure state +// Interrupt 94 <0=> Secure state <1=> Non-Secure state +// Interrupt 95 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 0 + +/* +// Interrupts 96..127 +// Interrupt 96 <0=> Secure state <1=> Non-Secure state +// Interrupt 97 <0=> Secure state <1=> Non-Secure state +// Interrupt 98 <0=> Secure state <1=> Non-Secure state +// Interrupt 99 <0=> Secure state <1=> Non-Secure state +// Interrupt 100 <0=> Secure state <1=> Non-Secure state +// Interrupt 101 <0=> Secure state <1=> Non-Secure state +// Interrupt 102 <0=> Secure state <1=> Non-Secure state +// Interrupt 103 <0=> Secure state <1=> Non-Secure state +// Interrupt 104 <0=> Secure state <1=> Non-Secure state +// Interrupt 105 <0=> Secure state <1=> Non-Secure state +// Interrupt 106 <0=> Secure state <1=> Non-Secure state +// Interrupt 107 <0=> Secure state <1=> Non-Secure state +// Interrupt 108 <0=> Secure state <1=> Non-Secure state +// Interrupt 109 <0=> Secure state <1=> Non-Secure state +// Interrupt 110 <0=> Secure state <1=> Non-Secure state +// Interrupt 111 <0=> Secure state <1=> Non-Secure state +// Interrupt 112 <0=> Secure state <1=> Non-Secure state +// Interrupt 113 <0=> Secure state <1=> Non-Secure state +// Interrupt 114 <0=> Secure state <1=> Non-Secure state +// Interrupt 115 <0=> Secure state <1=> Non-Secure state +// Interrupt 116 <0=> Secure state <1=> Non-Secure state +// Interrupt 117 <0=> Secure state <1=> Non-Secure state +// Interrupt 118 <0=> Secure state <1=> Non-Secure state +// Interrupt 119 <0=> Secure state <1=> Non-Secure state +// Interrupt 120 <0=> Secure state <1=> Non-Secure state +// Interrupt 121 <0=> Secure state <1=> Non-Secure state +// Interrupt 122 <0=> Secure state <1=> Non-Secure state +// Interrupt 123 <0=> Secure state <1=> Non-Secure state +// Interrupt 124 <0=> Secure state <1=> Non-Secure state +// Interrupt 125 <0=> Secure state <1=> Non-Secure state +// Interrupt 126 <0=> Secure state <1=> Non-Secure state +// Interrupt 127 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 128..159) +*/ +#define NVIC_INIT_ITNS4 0 + +/* +// Interrupts 128..159 +// Interrupt 128 <0=> Secure state <1=> Non-Secure state +// Interrupt 129 <0=> Secure state <1=> Non-Secure state +// Interrupt 130 <0=> Secure state <1=> Non-Secure state +// Interrupt 131 <0=> Secure state <1=> Non-Secure state +// Interrupt 132 <0=> Secure state <1=> Non-Secure state +// Interrupt 133 <0=> Secure state <1=> Non-Secure state +// Interrupt 134 <0=> Secure state <1=> Non-Secure state +// Interrupt 135 <0=> Secure state <1=> Non-Secure state +// Interrupt 136 <0=> Secure state <1=> Non-Secure state +// Interrupt 137 <0=> Secure state <1=> Non-Secure state +// Interrupt 138 <0=> Secure state <1=> Non-Secure state +// Interrupt 139 <0=> Secure state <1=> Non-Secure state +// Interrupt 140 <0=> Secure state <1=> Non-Secure state +// Interrupt 141 <0=> Secure state <1=> Non-Secure state +// Interrupt 142 <0=> Secure state <1=> Non-Secure state +// Interrupt 143 <0=> Secure state <1=> Non-Secure state +// Interrupt 144 <0=> Secure state <1=> Non-Secure state +// Interrupt 145 <0=> Secure state <1=> Non-Secure state +// Interrupt 146 <0=> Secure state <1=> Non-Secure state +// Interrupt 147 <0=> Secure state <1=> Non-Secure state +// Interrupt 148 <0=> Secure state <1=> Non-Secure state +// Interrupt 149 <0=> Secure state <1=> Non-Secure state +// Interrupt 150 <0=> Secure state <1=> Non-Secure state +// Interrupt 151 <0=> Secure state <1=> Non-Secure state +// Interrupt 152 <0=> Secure state <1=> Non-Secure state +// Interrupt 153 <0=> Secure state <1=> Non-Secure state +// Interrupt 154 <0=> Secure state <1=> Non-Secure state +// Interrupt 155 <0=> Secure state <1=> Non-Secure state +// Interrupt 156 <0=> Secure state <1=> Non-Secure state +// Interrupt 157 <0=> Secure state <1=> Non-Secure state +// Interrupt 158 <0=> Secure state <1=> Non-Secure state +// Interrupt 159 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 5 (Interrupts 160..191) +*/ +#define NVIC_INIT_ITNS5 0 + +/* +// Interrupts 160..191 +// Interrupt 160 <0=> Secure state <1=> Non-Secure state +// Interrupt 161 <0=> Secure state <1=> Non-Secure state +// Interrupt 162 <0=> Secure state <1=> Non-Secure state +// Interrupt 163 <0=> Secure state <1=> Non-Secure state +// Interrupt 164 <0=> Secure state <1=> Non-Secure state +// Interrupt 165 <0=> Secure state <1=> Non-Secure state +// Interrupt 166 <0=> Secure state <1=> Non-Secure state +// Interrupt 167 <0=> Secure state <1=> Non-Secure state +// Interrupt 168 <0=> Secure state <1=> Non-Secure state +// Interrupt 169 <0=> Secure state <1=> Non-Secure state +// Interrupt 170 <0=> Secure state <1=> Non-Secure state +// Interrupt 171 <0=> Secure state <1=> Non-Secure state +// Interrupt 172 <0=> Secure state <1=> Non-Secure state +// Interrupt 173 <0=> Secure state <1=> Non-Secure state +// Interrupt 174 <0=> Secure state <1=> Non-Secure state +// Interrupt 175 <0=> Secure state <1=> Non-Secure state +// Interrupt 176 <0=> Secure state <1=> Non-Secure state +// Interrupt 177 <0=> Secure state <1=> Non-Secure state +// Interrupt 178 <0=> Secure state <1=> Non-Secure state +// Interrupt 179 <0=> Secure state <1=> Non-Secure state +// Interrupt 180 <0=> Secure state <1=> Non-Secure state +// Interrupt 181 <0=> Secure state <1=> Non-Secure state +// Interrupt 182 <0=> Secure state <1=> Non-Secure state +// Interrupt 183 <0=> Secure state <1=> Non-Secure state +// Interrupt 184 <0=> Secure state <1=> Non-Secure state +// Interrupt 185 <0=> Secure state <1=> Non-Secure state +// Interrupt 186 <0=> Secure state <1=> Non-Secure state +// Interrupt 187 <0=> Secure state <1=> Non-Secure state +// Interrupt 188 <0=> Secure state <1=> Non-Secure state +// Interrupt 189 <0=> Secure state <1=> Non-Secure state +// Interrupt 190 <0=> Secure state <1=> Non-Secure state +// Interrupt 191 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS5_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 6 (Interrupts 192..223) +*/ +#define NVIC_INIT_ITNS6 0 + +/* +// Interrupts 192..223 +// Interrupt 192 <0=> Secure state <1=> Non-Secure state +// Interrupt 193 <0=> Secure state <1=> Non-Secure state +// Interrupt 194 <0=> Secure state <1=> Non-Secure state +// Interrupt 195 <0=> Secure state <1=> Non-Secure state +// Interrupt 196 <0=> Secure state <1=> Non-Secure state +// Interrupt 197 <0=> Secure state <1=> Non-Secure state +// Interrupt 198 <0=> Secure state <1=> Non-Secure state +// Interrupt 199 <0=> Secure state <1=> Non-Secure state +// Interrupt 200 <0=> Secure state <1=> Non-Secure state +// Interrupt 201 <0=> Secure state <1=> Non-Secure state +// Interrupt 202 <0=> Secure state <1=> Non-Secure state +// Interrupt 203 <0=> Secure state <1=> Non-Secure state +// Interrupt 204 <0=> Secure state <1=> Non-Secure state +// Interrupt 205 <0=> Secure state <1=> Non-Secure state +// Interrupt 206 <0=> Secure state <1=> Non-Secure state +// Interrupt 207 <0=> Secure state <1=> Non-Secure state +// Interrupt 208 <0=> Secure state <1=> Non-Secure state +// Interrupt 209 <0=> Secure state <1=> Non-Secure state +// Interrupt 210 <0=> Secure state <1=> Non-Secure state +// Interrupt 211 <0=> Secure state <1=> Non-Secure state +// Interrupt 212 <0=> Secure state <1=> Non-Secure state +// Interrupt 213 <0=> Secure state <1=> Non-Secure state +// Interrupt 214 <0=> Secure state <1=> Non-Secure state +// Interrupt 215 <0=> Secure state <1=> Non-Secure state +// Interrupt 216 <0=> Secure state <1=> Non-Secure state +// Interrupt 217 <0=> Secure state <1=> Non-Secure state +// Interrupt 218 <0=> Secure state <1=> Non-Secure state +// Interrupt 219 <0=> Secure state <1=> Non-Secure state +// Interrupt 220 <0=> Secure state <1=> Non-Secure state +// Interrupt 221 <0=> Secure state <1=> Non-Secure state +// Interrupt 222 <0=> Secure state <1=> Non-Secure state +// Interrupt 223 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS6_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 7 (Interrupts 224..255) +*/ +#define NVIC_INIT_ITNS7 0 + +/* +// Interrupts 224..255 +// Interrupt 224 <0=> Secure state <1=> Non-Secure state +// Interrupt 225 <0=> Secure state <1=> Non-Secure state +// Interrupt 226 <0=> Secure state <1=> Non-Secure state +// Interrupt 227 <0=> Secure state <1=> Non-Secure state +// Interrupt 228 <0=> Secure state <1=> Non-Secure state +// Interrupt 229 <0=> Secure state <1=> Non-Secure state +// Interrupt 230 <0=> Secure state <1=> Non-Secure state +// Interrupt 231 <0=> Secure state <1=> Non-Secure state +// Interrupt 232 <0=> Secure state <1=> Non-Secure state +// Interrupt 233 <0=> Secure state <1=> Non-Secure state +// Interrupt 234 <0=> Secure state <1=> Non-Secure state +// Interrupt 235 <0=> Secure state <1=> Non-Secure state +// Interrupt 236 <0=> Secure state <1=> Non-Secure state +// Interrupt 237 <0=> Secure state <1=> Non-Secure state +// Interrupt 238 <0=> Secure state <1=> Non-Secure state +// Interrupt 239 <0=> Secure state <1=> Non-Secure state +// Interrupt 240 <0=> Secure state <1=> Non-Secure state +// Interrupt 241 <0=> Secure state <1=> Non-Secure state +// Interrupt 242 <0=> Secure state <1=> Non-Secure state +// Interrupt 243 <0=> Secure state <1=> Non-Secure state +// Interrupt 244 <0=> Secure state <1=> Non-Secure state +// Interrupt 245 <0=> Secure state <1=> Non-Secure state +// Interrupt 246 <0=> Secure state <1=> Non-Secure state +// Interrupt 247 <0=> Secure state <1=> Non-Secure state +// Interrupt 248 <0=> Secure state <1=> Non-Secure state +// Interrupt 249 <0=> Secure state <1=> Non-Secure state +// Interrupt 250 <0=> Secure state <1=> Non-Secure state +// Interrupt 251 <0=> Secure state <1=> Non-Secure state +// Interrupt 252 <0=> Secure state <1=> Non-Secure state +// Interrupt 253 <0=> Secure state <1=> Non-Secure state +// Interrupt 254 <0=> Secure state <1=> Non-Secure state +// Interrupt 255 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS7_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + + + +/* + max 128 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) + SCB->ICSR = (SCB->ICSR & ~(SCB_ICSR_STTNS_Msk )) | + ((SCB_ICSR_STTNS_VAL << SCB_ICSR_STTNS_Pos) & SCB_ICSR_STTNS_Msk); + #endif /* defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) */ + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + + #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) + NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; + #endif + + #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) + NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; + #endif + + #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) + NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; + #endif + + /* repeat this for all possible ITNS elements */ + +} + +#endif /* PARTITION_ARMCM23_H */ diff --git a/ports/cortex_m23/ac5/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c b/ports/cortex_m23/ac5/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c new file mode 100644 index 00000000..30dc1dfd --- /dev/null +++ b/ports/cortex_m23/ac5/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c @@ -0,0 +1,137 @@ +/****************************************************************************** + * @file startup_ARMCM23.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M23 Device + * @version V2.0.0 + * @date 04. June 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM23) + #include "ARMCM23.h" +#elif defined (ARMCM23_TZ) + #include "ARMCM23_TZ.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler Function Prototype + *----------------------------------------------------------------------------*/ +typedef void( *pFunc )( void ); + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const pFunc __VECTOR_TABLE[240]; + const pFunc __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/ports/cortex_m23/ac5/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/system_ARMCM23.c b/ports/cortex_m23/ac5/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/system_ARMCM23.c new file mode 100644 index 00000000..1052b383 --- /dev/null +++ b/ports/cortex_m23/ac5/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/system_ARMCM23.c @@ -0,0 +1,98 @@ +/**************************************************************************//** + * @file system_ARMCM23.c + * @brief CMSIS Device System Source File for + * ARMCM23 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM23) + #include "ARMCM23.h" +#elif defined (ARMCM23_TZ) + #include "ARMCM23_TZ.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM23.h" + #endif +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __VECTOR_TABLE; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__VECTOR_TABLE; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; + + *(uint32_t *)0xE000ED24 = 0x000F0000; /* S: enable secure, usage, bus, mem faults */ + *(uint32_t *)0xE002ED24 = 0x000F0000; /* NS: enable secure, usage, bus, mem faults */ +} + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +void HardFault_Handler(void) +{ + while(1); + +} + +void UsageFault_Handler(void) +{ + while(1); +} +#endif diff --git a/ports/cortex_m23/ac5/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h b/ports/cortex_m23/ac5/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h new file mode 100644 index 00000000..a37b412e --- /dev/null +++ b/ports/cortex_m23/ac5/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'demo_secure_zone' + * Target: 'FVP Simulation Model' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM23_TZ.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/ports/cortex_m23/ac5/example_build/demo_secure_zone/demo_secure_zone.uvoptx b/ports/cortex_m23/ac5/example_build/demo_secure_zone/demo_secure_zone.uvoptx new file mode 100644 index 00000000..91ee646d --- /dev/null +++ b/ports/cortex_m23/ac5/example_build/demo_secure_zone/demo_secure_zone.uvoptx @@ -0,0 +1,328 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + FVP Simulation Model + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 15 + + + + + + + + + + ..\Debug.ini + BIN\DbgFMv8M.DLL + + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FC1000 -FD20000000 + + + 0 + DbgFMv8M + -I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M23_MDK.exe" -MF"..\ARMCM23_TZ_config.txt" -PF -MA + + + 0 + DLGTARM + (6010=3649,-370,4126,226,0)(6018=2033,530,2222,894,0)(6019=-1,-1,-1,-1,0)(6008=1847,-259,2141,-74,0)(6009=2148,-261,2442,-76,0)(6014=1836,-490,2094,241,0)(6015=-1,-1,-1,-1,0)(6003=-1,-1,-1,-1,0)(6000=75,104,528,436,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0) + + + + + + 0 + 1 + _tx_thread_current_ptr + + + 1 + 1 + thread_0_counter + + + 2 + 1 + thread_1_counter + + + 3 + 1 + thread_2_counter + + + 4 + 1 + thread_3_counter + + + 5 + 1 + thread_4_counter + + + 6 + 1 + thread_5_counter + + + 7 + 1 + thread_6_counter + + + 8 + 1 + thread_7_counter + + + 9 + 1 + _tx_timer_system_clock + + + + + 1 + 2 + 0x2003ffd8 + 0 + + + + + 2 + 2 + 0xE000ED28 + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Secure Code + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\src\tx_thread_secure_stack.c + tx_thread_secure_stack.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + .\main_s.c + main_s.c + 0 + 0 + + + + + Interface + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + .\interface.c + interface.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 1 + 0 + 0 + 1 + + + diff --git a/ports/cortex_m23/ac5/example_build/demo_secure_zone/demo_secure_zone.uvprojx b/ports/cortex_m23/ac5/example_build/demo_secure_zone/demo_secure_zone.uvprojx new file mode 100644 index 00000000..9b49855d --- /dev/null +++ b/ports/cortex_m23/ac5/example_build/demo_secure_zone/demo_secure_zone.uvprojx @@ -0,0 +1,521 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + FVP Simulation Model + 0x4 + ARM-ADS + 6140000::V6.14::ARMCLANG + 1 + + + ARMCM23_TZ + ARM + ARM.CMSIS.5.7.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("Cortex-M23") TZ CLOCK(12000000) ESEL ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM23_TZ$Device\ARM\ARMCM23\Include\ARMCM23_TZ.h + + + + + + + + + + + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + demo_secure_zone + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + -MPU + TCM.DLL + -pCM23 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 0 + 4101 + + 1 + BIN\UL2V8M.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M23" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 8 + 1 + 1 + 0 + 1 + 4 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x200000 + + + 1 + 0x200000 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x20200000 + 0x20000 + + + + + + 1 + 7 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 0 + 0 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\..\common\inc, ..\..\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\RTE\Device\ARMCM23_TZ\ARMCM23_ac6.sct + + + + + + + + + + + Secure Code + + + tx_thread_secure_stack.c + 1 + ..\..\src\tx_thread_secure_stack.c + + + main_s.c + 1 + .\main_s.c + + + + + Interface + + + interface.c + 1 + .\interface.c + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + RTE\Device\ARMCM23_TZ\ARMCM23_ac6.sct + + + + + + + + RTE\Device\ARMCM23_TZ\partition_ARMCM23.h + + + + + + + + RTE\Device\ARMCM23_TZ\startup_ARMCM23.c + + + + + + + + RTE\Device\ARMCM23_TZ\system_ARMCM23.c + + + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\ARMCM33_ac6.sct + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\partition_ARMCM33.h + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.c + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.s + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\system_ARMCM33.c + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/ports/cortex_m23/ac5/example_build/demo_secure_zone/interface.c b/ports/cortex_m23/ac5/example_build/demo_secure_zone/interface.c new file mode 100644 index 00000000..4e6e8eee --- /dev/null +++ b/ports/cortex_m23/ac5/example_build/demo_secure_zone/interface.c @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * interface.c Secure/non-secure callable application code + * + * Version 1.0 + * Initial Release + *---------------------------------------------------------------------------*/ + + +#include // CMSE definitions +#include "interface.h" // Header file with secure interface API + +/* typedef for non-secure callback functions */ +typedef funcptr funcptr_NS __attribute__((cmse_nonsecure_call)); + +/* Non-secure callable (entry) function */ +int func1(int x) __attribute__((cmse_nonsecure_entry)) { + return x+3; +} + +/* Non-secure callable (entry) function, calling a non-secure callback function */ +int func2(funcptr callback, int x) __attribute__((cmse_nonsecure_entry)) { + funcptr_NS callback_NS; // non-secure callback function pointer + int y; + + /* return function pointer with cleared LSB */ + callback_NS = (funcptr_NS)cmse_nsfptr_create(callback); + + y = callback_NS (x+1); + + return (y+2); +} diff --git a/ports/cortex_m23/ac5/example_build/demo_secure_zone/interface.h b/ports/cortex_m23/ac5/example_build/demo_secure_zone/interface.h new file mode 100644 index 00000000..8215d5a3 --- /dev/null +++ b/ports/cortex_m23/ac5/example_build/demo_secure_zone/interface.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * interface.h API definition for the non-secure state + * + * Version 1.0 + * Initial Release + *---------------------------------------------------------------------------*/ + +/* Function pointer declaration */ +typedef int (*funcptr)(int); + +/* Non-secure callable functions */ +extern int func1(int x); +extern int func2(funcptr callback, int x); diff --git a/ports/cortex_m23/ac5/example_build/demo_secure_zone/main_ns.c b/ports/cortex_m23/ac5/example_build/demo_secure_zone/main_ns.c new file mode 100644 index 00000000..5d16e1bb --- /dev/null +++ b/ports/cortex_m23/ac5/example_build/demo_secure_zone/main_ns.c @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * main_ns.c Non-secure main function - RTOS demo + * + * Version 1.0 + * Initial Release + *---------------------------------------------------------------------------*/ + +#include "interface.h" // Interface API +//#include "cmsis_os2.h" // ARM::CMSIS:RTOS2:Keil RTX5 + +//static osStatus_t Status; + +//static osThreadId_t ThreadA_Id; +//static osThreadId_t ThreadB_Id; +//static osThreadId_t ThreadC_Id; + +void ThreadA (void *argument); +void ThreadB (void *argument); +void ThreadC (void *argument); + + +extern volatile int counterA; +extern volatile int counterB; +extern volatile int counterC; + +volatile int counterA; +volatile int counterB; +volatile int counterC; + +/* +static int callbackA (int val) { + return (val); +} + +__attribute__((noreturn)) +void ThreadA (void *argument) { + (void)argument; + + for (;;) { + counterA = func1 (counterA); + counterA = func2 (callbackA, counterA); + osDelay(2U); + } +} + +static int callbackB (int val) { + uint32_t flags; + + flags = osThreadFlagsWait (1U, osFlagsWaitAny, osWaitForever); + if (flags == 1U) { + return (val+1); + } else { + return (0); + } +} + + +__attribute__((noreturn)) +void ThreadB (void *argument) { + (void)argument; + + for (;;) { + counterB = func1 (counterB); + counterB = func2 (callbackB, counterB); + } +} + +__attribute__((noreturn)) +void ThreadC (void *argument) { + (void)argument; + + for (;;) { + counterC = counterC + 1; + if ((counterC % 0x10) == 0) { + osThreadFlagsSet (ThreadB_Id, 1); + } + osDelay(1U); + } +} + +static const osThreadAttr_t ThreadAttr = { + .tz_module = 1U, // indicate calls to secure mode +}; +*/ +#if 1 +int main (void) { + + for (;;); +} +#endif diff --git a/ports/cortex_m23/ac5/example_build/demo_secure_zone/main_s.c b/ports/cortex_m23/ac5/example_build/demo_secure_zone/main_s.c new file mode 100644 index 00000000..2c667821 --- /dev/null +++ b/ports/cortex_m23/ac5/example_build/demo_secure_zone/main_s.c @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 15. October 2016 + * $Revision: 1.1.0 + * + * Project: TrustZone for ARMv8-M + * Title: Code template for secure main function + * + *---------------------------------------------------------------------------*/ + +/* Use CMSE intrinsics */ +#include + #include +#include "RTE_Components.h" +#include CMSIS_device_header + +/* TZ_START_NS: Start address of non-secure application */ +#ifndef TZ_START_NS +#define TZ_START_NS (0x200000U) +#endif + +/* typedef for non-secure callback functions */ +typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call)); + +/* Secure main() */ +int main(void) { + funcptr_void NonSecure_ResetHandler; + + /* Add user setup code for secure part here*/ + + /* Set non-secure main stack (MSP_NS) */ + __TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS))); + + /* Get non-secure reset handler */ + NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U))); + + /* Start non-secure state software application */ + NonSecure_ResetHandler(); + + /* Non-secure software does not return, this code is not executed */ + while (1) { + __NOP(); + } +} diff --git a/ports/cortex_m23/ac5/example_build/demo_secure_zone/tz_context.c b/ports/cortex_m23/ac5/example_build/demo_secure_zone/tz_context.c new file mode 100644 index 00000000..f3152890 --- /dev/null +++ b/ports/cortex_m23/ac5/example_build/demo_secure_zone/tz_context.c @@ -0,0 +1,203 @@ +/* + * Copyright (c) 2015-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------------- + * + * $Date: 15. October 2016 + * $Revision: 1.1.0 + * + * Project: TrustZone for ARMv8-M + * Title: Context Management for ARMv8-M TrustZone - Sample implementation + * + *---------------------------------------------------------------------------*/ + +#include "RTE_Components.h" +#include CMSIS_device_header +#include "tz_context.h" + +/// Number of process slots (threads may call secure library code) +#ifndef TZ_PROCESS_STACK_SLOTS +#define TZ_PROCESS_STACK_SLOTS 8U +#endif + +/// Stack size of the secure library code +#ifndef TZ_PROCESS_STACK_SIZE +#define TZ_PROCESS_STACK_SIZE 256U +#endif + +typedef struct { + uint32_t sp_top; // stack space top + uint32_t sp_limit; // stack space limit + uint32_t sp; // current stack pointer +} stack_info_t; + +static stack_info_t ProcessStackInfo [TZ_PROCESS_STACK_SLOTS]; +static uint64_t ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/8U]; +static uint32_t ProcessStackFreeSlot = 0xFFFFFFFFU; + + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_InitContextSystem_S (void) { + uint32_t n; + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) { + ProcessStackInfo[n].sp = 0U; + ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n]; + ProcessStackInfo[n].sp_top = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE; + *((uint32_t *)ProcessStackMemory[n]) = n + 1U; + } + *((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU; + + ProcessStackFreeSlot = 0U; + + // Default process stack pointer and stack limit + __set_PSPLIM((uint32_t)ProcessStackMemory); + __set_PSP ((uint32_t)ProcessStackMemory); + + // Privileged Thread Mode using PSP + __set_CONTROL(0x02U); + + return 1U; // Success +} + + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +__attribute__((cmse_nonsecure_entry)) +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) { + uint32_t slot; + + (void)module; // Ignore (fixed Stack size) + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + if (ProcessStackFreeSlot == 0xFFFFFFFFU) { + return 0U; // No slot available + } + + slot = ProcessStackFreeSlot; + ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]); + + ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top; + + return (slot + 1U); +} + + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) { + uint32_t slot; + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + ProcessStackInfo[slot].sp = 0U; + + *((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot; + ProcessStackFreeSlot = slot; + + return 1U; // Success +} + + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id) { + uint32_t slot; + + if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { + return 0U; // Thread Mode or using Main Stack for threads + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + + // Setup process stack pointer and stack limit + __set_PSPLIM(ProcessStackInfo[slot].sp_limit); + __set_PSP (ProcessStackInfo[slot].sp); + + return 1U; // Success +} + + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id) { + uint32_t slot; + uint32_t sp; + + if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { + return 0U; // Thread Mode or using Main Stack for threads + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + + sp = __get_PSP(); + if ((sp < ProcessStackInfo[slot].sp_limit) || + (sp > ProcessStackInfo[slot].sp_top)) { + return 0U; // SP out of range + } + ProcessStackInfo[slot].sp = sp; + + // Default process stack pointer and stack limit + __set_PSPLIM((uint32_t)ProcessStackMemory); + __set_PSP ((uint32_t)ProcessStackMemory); + + return 1U; // Success +} diff --git a/ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c b/ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c new file mode 100644 index 00000000..e4871014 --- /dev/null +++ b/ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + + for (;;) {} +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; + + switch (code) { + case osRtxErrorStackUnderflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +} diff --git a/ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h b/ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h new file mode 100644 index 00000000..3021efbc --- /dev/null +++ b/ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,578 @@ +/* + * Copyright (c) 2013-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.5.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 4096 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 4096 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 0 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 1 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 0 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 256 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 256 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 256 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 256 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch. +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 256 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 256 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial recording level applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Recording levels for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Recording level for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_LEVEL +#define OS_EVR_MEMORY_LEVEL 0x01U +#endif + +// Kernel +// Recording level for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_LEVEL +#define OS_EVR_KERNEL_LEVEL 0x01U +#endif + +// Thread +// Recording level for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_LEVEL +#define OS_EVR_THREAD_LEVEL 0x05U +#endif + +// Generic Wait +// Recording level for Generic Wait events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_WAIT_LEVEL +#define OS_EVR_WAIT_LEVEL 0x01U +#endif + +// Thread Flags +// Recording level for Thread Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THFLAGS_LEVEL +#define OS_EVR_THFLAGS_LEVEL 0x01U +#endif + +// Event Flags +// Recording level for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_LEVEL +#define OS_EVR_EVFLAGS_LEVEL 0x01U +#endif + +// Timer +// Recording level for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_LEVEL +#define OS_EVR_TIMER_LEVEL 0x01U +#endif + +// Mutex +// Recording level for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_LEVEL +#define OS_EVR_MUTEX_LEVEL 0x01U +#endif + +// Semaphore +// Recording level for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_LEVEL +#define OS_EVR_SEMAPHORE_LEVEL 0x01U +#endif + +// Memory Pool +// Recording level for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_LEVEL +#define OS_EVR_MEMPOOL_LEVEL 0x01U +#endif + +// Message Queue +// Recording level for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_LEVEL +#define OS_EVR_MSGQUEUE_LEVEL 0x01U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Generic Wait +// Enables Generic Wait event generation. +#ifndef OS_EVR_WAIT +#define OS_EVR_WAIT 1 +#endif + +// Thread Flags +// Enables Thread Flags event generation. +#ifndef OS_EVR_THFLAGS +#define OS_EVR_THFLAGS 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#define OS_THREAD_LIBSPACE_NUM 4 +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/ARMCM23_ac6.sct b/ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/ARMCM23_ac6.sct new file mode 100644 index 00000000..7b796b29 --- /dev/null +++ b/ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/ARMCM23_ac6.sct @@ -0,0 +1,74 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc +; command above MUST be in first line (no comment above!) + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x00200000 +#define __ROM_SIZE 0x00080000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x20200000 +#define __RAM_SIZE 0x00040000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000200 +#define __HEAP_SIZE 0x00000C00 + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundery definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ +#define __RO_BASE __ROM_BASE +#define __RO_SIZE __ROM_SIZE + +#define __RW_BASE (__RAM_BASE ) +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) + + + +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) +; *(Veneer$$CMSE) ; uncomment for secure applications + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } +} diff --git a/ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h b/ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h new file mode 100644 index 00000000..a7a090e7 --- /dev/null +++ b/ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h @@ -0,0 +1,832 @@ +/**************************************************************************//** + * @file partition_ARMCM23.h + * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM23 + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PARTITION_ARMCM23_H +#define PARTITION_ARMCM23_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 1 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x00200000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x003FFFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x20200000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x203FFFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x40040000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 1 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 1 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 1 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x80-0xFF +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 1 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + + +/* +// Setup behaviour of single SysTick +*/ +#define SCB_ICSR_INIT 0 + +/* +// in a single SysTick implementation, SysTick is +// <0=>Secure +// <1=>Non-Secure +// Value for SCB->ICSR register bit STTNS +// only for single SysTick implementation +*/ +#define SCB_ICSR_STTNS_VAL 0 + +/* +// +*/ + + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// Interrupt 0 <0=> Secure state <1=> Non-Secure state +// Interrupt 1 <0=> Secure state <1=> Non-Secure state +// Interrupt 2 <0=> Secure state <1=> Non-Secure state +// Interrupt 3 <0=> Secure state <1=> Non-Secure state +// Interrupt 4 <0=> Secure state <1=> Non-Secure state +// Interrupt 5 <0=> Secure state <1=> Non-Secure state +// Interrupt 6 <0=> Secure state <1=> Non-Secure state +// Interrupt 7 <0=> Secure state <1=> Non-Secure state +// Interrupt 8 <0=> Secure state <1=> Non-Secure state +// Interrupt 9 <0=> Secure state <1=> Non-Secure state +// Interrupt 10 <0=> Secure state <1=> Non-Secure state +// Interrupt 11 <0=> Secure state <1=> Non-Secure state +// Interrupt 12 <0=> Secure state <1=> Non-Secure state +// Interrupt 13 <0=> Secure state <1=> Non-Secure state +// Interrupt 14 <0=> Secure state <1=> Non-Secure state +// Interrupt 15 <0=> Secure state <1=> Non-Secure state +// Interrupt 16 <0=> Secure state <1=> Non-Secure state +// Interrupt 17 <0=> Secure state <1=> Non-Secure state +// Interrupt 18 <0=> Secure state <1=> Non-Secure state +// Interrupt 19 <0=> Secure state <1=> Non-Secure state +// Interrupt 20 <0=> Secure state <1=> Non-Secure state +// Interrupt 21 <0=> Secure state <1=> Non-Secure state +// Interrupt 22 <0=> Secure state <1=> Non-Secure state +// Interrupt 23 <0=> Secure state <1=> Non-Secure state +// Interrupt 24 <0=> Secure state <1=> Non-Secure state +// Interrupt 25 <0=> Secure state <1=> Non-Secure state +// Interrupt 26 <0=> Secure state <1=> Non-Secure state +// Interrupt 27 <0=> Secure state <1=> Non-Secure state +// Interrupt 28 <0=> Secure state <1=> Non-Secure state +// Interrupt 29 <0=> Secure state <1=> Non-Secure state +// Interrupt 30 <0=> Secure state <1=> Non-Secure state +// Interrupt 31 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// Interrupt 32 <0=> Secure state <1=> Non-Secure state +// Interrupt 33 <0=> Secure state <1=> Non-Secure state +// Interrupt 34 <0=> Secure state <1=> Non-Secure state +// Interrupt 35 <0=> Secure state <1=> Non-Secure state +// Interrupt 36 <0=> Secure state <1=> Non-Secure state +// Interrupt 37 <0=> Secure state <1=> Non-Secure state +// Interrupt 38 <0=> Secure state <1=> Non-Secure state +// Interrupt 39 <0=> Secure state <1=> Non-Secure state +// Interrupt 40 <0=> Secure state <1=> Non-Secure state +// Interrupt 41 <0=> Secure state <1=> Non-Secure state +// Interrupt 42 <0=> Secure state <1=> Non-Secure state +// Interrupt 43 <0=> Secure state <1=> Non-Secure state +// Interrupt 44 <0=> Secure state <1=> Non-Secure state +// Interrupt 45 <0=> Secure state <1=> Non-Secure state +// Interrupt 46 <0=> Secure state <1=> Non-Secure state +// Interrupt 47 <0=> Secure state <1=> Non-Secure state +// Interrupt 48 <0=> Secure state <1=> Non-Secure state +// Interrupt 49 <0=> Secure state <1=> Non-Secure state +// Interrupt 50 <0=> Secure state <1=> Non-Secure state +// Interrupt 51 <0=> Secure state <1=> Non-Secure state +// Interrupt 52 <0=> Secure state <1=> Non-Secure state +// Interrupt 53 <0=> Secure state <1=> Non-Secure state +// Interrupt 54 <0=> Secure state <1=> Non-Secure state +// Interrupt 55 <0=> Secure state <1=> Non-Secure state +// Interrupt 56 <0=> Secure state <1=> Non-Secure state +// Interrupt 57 <0=> Secure state <1=> Non-Secure state +// Interrupt 58 <0=> Secure state <1=> Non-Secure state +// Interrupt 59 <0=> Secure state <1=> Non-Secure state +// Interrupt 60 <0=> Secure state <1=> Non-Secure state +// Interrupt 61 <0=> Secure state <1=> Non-Secure state +// Interrupt 62 <0=> Secure state <1=> Non-Secure state +// Interrupt 63 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 0 + +/* +// Interrupts 64..95 +// Interrupt 64 <0=> Secure state <1=> Non-Secure state +// Interrupt 65 <0=> Secure state <1=> Non-Secure state +// Interrupt 66 <0=> Secure state <1=> Non-Secure state +// Interrupt 67 <0=> Secure state <1=> Non-Secure state +// Interrupt 68 <0=> Secure state <1=> Non-Secure state +// Interrupt 69 <0=> Secure state <1=> Non-Secure state +// Interrupt 70 <0=> Secure state <1=> Non-Secure state +// Interrupt 71 <0=> Secure state <1=> Non-Secure state +// Interrupt 72 <0=> Secure state <1=> Non-Secure state +// Interrupt 73 <0=> Secure state <1=> Non-Secure state +// Interrupt 74 <0=> Secure state <1=> Non-Secure state +// Interrupt 75 <0=> Secure state <1=> Non-Secure state +// Interrupt 76 <0=> Secure state <1=> Non-Secure state +// Interrupt 77 <0=> Secure state <1=> Non-Secure state +// Interrupt 78 <0=> Secure state <1=> Non-Secure state +// Interrupt 79 <0=> Secure state <1=> Non-Secure state +// Interrupt 80 <0=> Secure state <1=> Non-Secure state +// Interrupt 81 <0=> Secure state <1=> Non-Secure state +// Interrupt 82 <0=> Secure state <1=> Non-Secure state +// Interrupt 83 <0=> Secure state <1=> Non-Secure state +// Interrupt 84 <0=> Secure state <1=> Non-Secure state +// Interrupt 85 <0=> Secure state <1=> Non-Secure state +// Interrupt 86 <0=> Secure state <1=> Non-Secure state +// Interrupt 87 <0=> Secure state <1=> Non-Secure state +// Interrupt 88 <0=> Secure state <1=> Non-Secure state +// Interrupt 89 <0=> Secure state <1=> Non-Secure state +// Interrupt 90 <0=> Secure state <1=> Non-Secure state +// Interrupt 91 <0=> Secure state <1=> Non-Secure state +// Interrupt 92 <0=> Secure state <1=> Non-Secure state +// Interrupt 93 <0=> Secure state <1=> Non-Secure state +// Interrupt 94 <0=> Secure state <1=> Non-Secure state +// Interrupt 95 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 0 + +/* +// Interrupts 96..127 +// Interrupt 96 <0=> Secure state <1=> Non-Secure state +// Interrupt 97 <0=> Secure state <1=> Non-Secure state +// Interrupt 98 <0=> Secure state <1=> Non-Secure state +// Interrupt 99 <0=> Secure state <1=> Non-Secure state +// Interrupt 100 <0=> Secure state <1=> Non-Secure state +// Interrupt 101 <0=> Secure state <1=> Non-Secure state +// Interrupt 102 <0=> Secure state <1=> Non-Secure state +// Interrupt 103 <0=> Secure state <1=> Non-Secure state +// Interrupt 104 <0=> Secure state <1=> Non-Secure state +// Interrupt 105 <0=> Secure state <1=> Non-Secure state +// Interrupt 106 <0=> Secure state <1=> Non-Secure state +// Interrupt 107 <0=> Secure state <1=> Non-Secure state +// Interrupt 108 <0=> Secure state <1=> Non-Secure state +// Interrupt 109 <0=> Secure state <1=> Non-Secure state +// Interrupt 110 <0=> Secure state <1=> Non-Secure state +// Interrupt 111 <0=> Secure state <1=> Non-Secure state +// Interrupt 112 <0=> Secure state <1=> Non-Secure state +// Interrupt 113 <0=> Secure state <1=> Non-Secure state +// Interrupt 114 <0=> Secure state <1=> Non-Secure state +// Interrupt 115 <0=> Secure state <1=> Non-Secure state +// Interrupt 116 <0=> Secure state <1=> Non-Secure state +// Interrupt 117 <0=> Secure state <1=> Non-Secure state +// Interrupt 118 <0=> Secure state <1=> Non-Secure state +// Interrupt 119 <0=> Secure state <1=> Non-Secure state +// Interrupt 120 <0=> Secure state <1=> Non-Secure state +// Interrupt 121 <0=> Secure state <1=> Non-Secure state +// Interrupt 122 <0=> Secure state <1=> Non-Secure state +// Interrupt 123 <0=> Secure state <1=> Non-Secure state +// Interrupt 124 <0=> Secure state <1=> Non-Secure state +// Interrupt 125 <0=> Secure state <1=> Non-Secure state +// Interrupt 126 <0=> Secure state <1=> Non-Secure state +// Interrupt 127 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 128..159) +*/ +#define NVIC_INIT_ITNS4 0 + +/* +// Interrupts 128..159 +// Interrupt 128 <0=> Secure state <1=> Non-Secure state +// Interrupt 129 <0=> Secure state <1=> Non-Secure state +// Interrupt 130 <0=> Secure state <1=> Non-Secure state +// Interrupt 131 <0=> Secure state <1=> Non-Secure state +// Interrupt 132 <0=> Secure state <1=> Non-Secure state +// Interrupt 133 <0=> Secure state <1=> Non-Secure state +// Interrupt 134 <0=> Secure state <1=> Non-Secure state +// Interrupt 135 <0=> Secure state <1=> Non-Secure state +// Interrupt 136 <0=> Secure state <1=> Non-Secure state +// Interrupt 137 <0=> Secure state <1=> Non-Secure state +// Interrupt 138 <0=> Secure state <1=> Non-Secure state +// Interrupt 139 <0=> Secure state <1=> Non-Secure state +// Interrupt 140 <0=> Secure state <1=> Non-Secure state +// Interrupt 141 <0=> Secure state <1=> Non-Secure state +// Interrupt 142 <0=> Secure state <1=> Non-Secure state +// Interrupt 143 <0=> Secure state <1=> Non-Secure state +// Interrupt 144 <0=> Secure state <1=> Non-Secure state +// Interrupt 145 <0=> Secure state <1=> Non-Secure state +// Interrupt 146 <0=> Secure state <1=> Non-Secure state +// Interrupt 147 <0=> Secure state <1=> Non-Secure state +// Interrupt 148 <0=> Secure state <1=> Non-Secure state +// Interrupt 149 <0=> Secure state <1=> Non-Secure state +// Interrupt 150 <0=> Secure state <1=> Non-Secure state +// Interrupt 151 <0=> Secure state <1=> Non-Secure state +// Interrupt 152 <0=> Secure state <1=> Non-Secure state +// Interrupt 153 <0=> Secure state <1=> Non-Secure state +// Interrupt 154 <0=> Secure state <1=> Non-Secure state +// Interrupt 155 <0=> Secure state <1=> Non-Secure state +// Interrupt 156 <0=> Secure state <1=> Non-Secure state +// Interrupt 157 <0=> Secure state <1=> Non-Secure state +// Interrupt 158 <0=> Secure state <1=> Non-Secure state +// Interrupt 159 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 5 (Interrupts 160..191) +*/ +#define NVIC_INIT_ITNS5 0 + +/* +// Interrupts 160..191 +// Interrupt 160 <0=> Secure state <1=> Non-Secure state +// Interrupt 161 <0=> Secure state <1=> Non-Secure state +// Interrupt 162 <0=> Secure state <1=> Non-Secure state +// Interrupt 163 <0=> Secure state <1=> Non-Secure state +// Interrupt 164 <0=> Secure state <1=> Non-Secure state +// Interrupt 165 <0=> Secure state <1=> Non-Secure state +// Interrupt 166 <0=> Secure state <1=> Non-Secure state +// Interrupt 167 <0=> Secure state <1=> Non-Secure state +// Interrupt 168 <0=> Secure state <1=> Non-Secure state +// Interrupt 169 <0=> Secure state <1=> Non-Secure state +// Interrupt 170 <0=> Secure state <1=> Non-Secure state +// Interrupt 171 <0=> Secure state <1=> Non-Secure state +// Interrupt 172 <0=> Secure state <1=> Non-Secure state +// Interrupt 173 <0=> Secure state <1=> Non-Secure state +// Interrupt 174 <0=> Secure state <1=> Non-Secure state +// Interrupt 175 <0=> Secure state <1=> Non-Secure state +// Interrupt 176 <0=> Secure state <1=> Non-Secure state +// Interrupt 177 <0=> Secure state <1=> Non-Secure state +// Interrupt 178 <0=> Secure state <1=> Non-Secure state +// Interrupt 179 <0=> Secure state <1=> Non-Secure state +// Interrupt 180 <0=> Secure state <1=> Non-Secure state +// Interrupt 181 <0=> Secure state <1=> Non-Secure state +// Interrupt 182 <0=> Secure state <1=> Non-Secure state +// Interrupt 183 <0=> Secure state <1=> Non-Secure state +// Interrupt 184 <0=> Secure state <1=> Non-Secure state +// Interrupt 185 <0=> Secure state <1=> Non-Secure state +// Interrupt 186 <0=> Secure state <1=> Non-Secure state +// Interrupt 187 <0=> Secure state <1=> Non-Secure state +// Interrupt 188 <0=> Secure state <1=> Non-Secure state +// Interrupt 189 <0=> Secure state <1=> Non-Secure state +// Interrupt 190 <0=> Secure state <1=> Non-Secure state +// Interrupt 191 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS5_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 6 (Interrupts 192..223) +*/ +#define NVIC_INIT_ITNS6 0 + +/* +// Interrupts 192..223 +// Interrupt 192 <0=> Secure state <1=> Non-Secure state +// Interrupt 193 <0=> Secure state <1=> Non-Secure state +// Interrupt 194 <0=> Secure state <1=> Non-Secure state +// Interrupt 195 <0=> Secure state <1=> Non-Secure state +// Interrupt 196 <0=> Secure state <1=> Non-Secure state +// Interrupt 197 <0=> Secure state <1=> Non-Secure state +// Interrupt 198 <0=> Secure state <1=> Non-Secure state +// Interrupt 199 <0=> Secure state <1=> Non-Secure state +// Interrupt 200 <0=> Secure state <1=> Non-Secure state +// Interrupt 201 <0=> Secure state <1=> Non-Secure state +// Interrupt 202 <0=> Secure state <1=> Non-Secure state +// Interrupt 203 <0=> Secure state <1=> Non-Secure state +// Interrupt 204 <0=> Secure state <1=> Non-Secure state +// Interrupt 205 <0=> Secure state <1=> Non-Secure state +// Interrupt 206 <0=> Secure state <1=> Non-Secure state +// Interrupt 207 <0=> Secure state <1=> Non-Secure state +// Interrupt 208 <0=> Secure state <1=> Non-Secure state +// Interrupt 209 <0=> Secure state <1=> Non-Secure state +// Interrupt 210 <0=> Secure state <1=> Non-Secure state +// Interrupt 211 <0=> Secure state <1=> Non-Secure state +// Interrupt 212 <0=> Secure state <1=> Non-Secure state +// Interrupt 213 <0=> Secure state <1=> Non-Secure state +// Interrupt 214 <0=> Secure state <1=> Non-Secure state +// Interrupt 215 <0=> Secure state <1=> Non-Secure state +// Interrupt 216 <0=> Secure state <1=> Non-Secure state +// Interrupt 217 <0=> Secure state <1=> Non-Secure state +// Interrupt 218 <0=> Secure state <1=> Non-Secure state +// Interrupt 219 <0=> Secure state <1=> Non-Secure state +// Interrupt 220 <0=> Secure state <1=> Non-Secure state +// Interrupt 221 <0=> Secure state <1=> Non-Secure state +// Interrupt 222 <0=> Secure state <1=> Non-Secure state +// Interrupt 223 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS6_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 7 (Interrupts 224..255) +*/ +#define NVIC_INIT_ITNS7 0 + +/* +// Interrupts 224..255 +// Interrupt 224 <0=> Secure state <1=> Non-Secure state +// Interrupt 225 <0=> Secure state <1=> Non-Secure state +// Interrupt 226 <0=> Secure state <1=> Non-Secure state +// Interrupt 227 <0=> Secure state <1=> Non-Secure state +// Interrupt 228 <0=> Secure state <1=> Non-Secure state +// Interrupt 229 <0=> Secure state <1=> Non-Secure state +// Interrupt 230 <0=> Secure state <1=> Non-Secure state +// Interrupt 231 <0=> Secure state <1=> Non-Secure state +// Interrupt 232 <0=> Secure state <1=> Non-Secure state +// Interrupt 233 <0=> Secure state <1=> Non-Secure state +// Interrupt 234 <0=> Secure state <1=> Non-Secure state +// Interrupt 235 <0=> Secure state <1=> Non-Secure state +// Interrupt 236 <0=> Secure state <1=> Non-Secure state +// Interrupt 237 <0=> Secure state <1=> Non-Secure state +// Interrupt 238 <0=> Secure state <1=> Non-Secure state +// Interrupt 239 <0=> Secure state <1=> Non-Secure state +// Interrupt 240 <0=> Secure state <1=> Non-Secure state +// Interrupt 241 <0=> Secure state <1=> Non-Secure state +// Interrupt 242 <0=> Secure state <1=> Non-Secure state +// Interrupt 243 <0=> Secure state <1=> Non-Secure state +// Interrupt 244 <0=> Secure state <1=> Non-Secure state +// Interrupt 245 <0=> Secure state <1=> Non-Secure state +// Interrupt 246 <0=> Secure state <1=> Non-Secure state +// Interrupt 247 <0=> Secure state <1=> Non-Secure state +// Interrupt 248 <0=> Secure state <1=> Non-Secure state +// Interrupt 249 <0=> Secure state <1=> Non-Secure state +// Interrupt 250 <0=> Secure state <1=> Non-Secure state +// Interrupt 251 <0=> Secure state <1=> Non-Secure state +// Interrupt 252 <0=> Secure state <1=> Non-Secure state +// Interrupt 253 <0=> Secure state <1=> Non-Secure state +// Interrupt 254 <0=> Secure state <1=> Non-Secure state +// Interrupt 255 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS7_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + + + +/* + max 128 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) + SCB->ICSR = (SCB->ICSR & ~(SCB_ICSR_STTNS_Msk )) | + ((SCB_ICSR_STTNS_VAL << SCB_ICSR_STTNS_Pos) & SCB_ICSR_STTNS_Msk); + #endif /* defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) */ + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + + #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) + NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; + #endif + + #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) + NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; + #endif + + #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) + NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; + #endif + + /* repeat this for all possible ITNS elements */ + +} + +#endif /* PARTITION_ARMCM23_H */ diff --git a/ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c b/ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c new file mode 100644 index 00000000..30dc1dfd --- /dev/null +++ b/ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c @@ -0,0 +1,137 @@ +/****************************************************************************** + * @file startup_ARMCM23.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M23 Device + * @version V2.0.0 + * @date 04. June 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM23) + #include "ARMCM23.h" +#elif defined (ARMCM23_TZ) + #include "ARMCM23_TZ.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler Function Prototype + *----------------------------------------------------------------------------*/ +typedef void( *pFunc )( void ); + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const pFunc __VECTOR_TABLE[240]; + const pFunc __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/system_ARMCM23.c b/ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/system_ARMCM23.c new file mode 100644 index 00000000..61ef3fe6 --- /dev/null +++ b/ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/system_ARMCM23.c @@ -0,0 +1,82 @@ +/**************************************************************************//** + * @file system_ARMCM23.c + * @brief CMSIS Device System Source File for + * ARMCM23 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM23) + #include "ARMCM23.h" +#elif defined (ARMCM23_TZ) + #include "ARMCM23_TZ.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM23.h" + #endif +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __VECTOR_TABLE; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__VECTOR_TABLE; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h b/ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h new file mode 100644 index 00000000..1cde6a79 --- /dev/null +++ b/ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'demo_threadx_non-secure_zone' + * Target: 'FVP Simulation Model' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM23_TZ.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h b/ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h new file mode 100644 index 00000000..476361d7 --- /dev/null +++ b/ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'ThreadX_Library' + * Target: 'ThreadX_Library_Project' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM23_TZ.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/ThreadX_Demo.uvopt b/ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/ThreadX_Demo.uvopt new file mode 100644 index 00000000..7ec4b36b --- /dev/null +++ b/ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/ThreadX_Demo.uvopt @@ -0,0 +1,305 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + ThreadX_Demo + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 1 + 0 + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + -1 + + + + + + + + + + + + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0) + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(102=-1,-1,-1,-1,0)(103=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(163=-1,-1,-1,-1,0)(164=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)(152=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)(1013=-1,-1,-1,-1,0)(171=-1,-1,-1,-1,0)(172=-1,-1,-1,-1,0)(173=-1,-1,-1,-1,0)(1014=-1,-1,-1,-1,0)(1016=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T5F + + + 0 + UL2CM3 + -UV0289BJE -O14 -S0 -C0 -N00("ARM CoreSight JTAG-DP") -D00(3BA00477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_16 -FS00 -FL04000 + + + + + + 0 + 1 + thread_0_counter + + + 1 + 1 + thread_1_counter + + + 2 + 1 + thread_2_counter + + + 3 + 1 + thread_3_counter + + + 4 + 1 + thread_4_counter + + + 5 + 1 + thread_5_counter + + + 6 + 1 + _tx_thread_current_ptr + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Source Group + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + .\tx_initialize_low_level.s + tx_initialize_low_level.s + 0 + 0 + + + 1 + 2 + 1 + 1 + 0 + 0 + .\demo_threadx.c + demo_threadx.c + 0 + 0 + + 44 + 0 + 1 + + -1 + -1 + + + -1 + -1 + + + 56 + 12 + 1633 + 671 + + + + + + + Library_Group + 1 + 0 + 0 + 0 + + 2 + 3 + 4 + 0 + 0 + 0 + .\ThreadX_Library.lib + ThreadX_Library.lib + 0 + 0 + + + + diff --git a/ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/ThreadX_Demo.uvproj b/ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/ThreadX_Demo.uvproj new file mode 100644 index 00000000..5f5dcbdb --- /dev/null +++ b/ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/ThreadX_Demo.uvproj @@ -0,0 +1,556 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + ThreadX_Demo + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + Cortex-M4 FPU + ARM + CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 + + + + 5237 + + + + + + + + + + + + 0 + 0 + + + + Luminary\ + Luminary\ + + 0 + 0 + 0 + 0 + 1 + + .\ + threadx_demo + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DCM.DLL + -pCM4F + SARMCM3.DLL + + TCM.DLL + -pCM4F + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + + 0 + -1 + + + + + + + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 4096 + + 0 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + --first __tx_vectors --entry=__main + + + + + + + + Source Group + + + 0 + 1 + 1 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 0 + + + + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + tx_initialize_low_level.s + 2 + .\tx_initialize_low_level.s + + + 2 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 2 + 2 + 1 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + demo_threadx.c + 1 + .\demo_threadx.c + + + + + Library_Group + + + ThreadX_Library.lib + 4 + .\ThreadX_Library.lib + + + + + + + + diff --git a/ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/demo_threadx.c b/ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/demo_threadx.c new file mode 100644 index 00000000..34ae21af --- /dev/null +++ b/ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/demo_threadx.c @@ -0,0 +1,428 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. Please refer to Chapter 6 of the ThreadX User Guide for a complete + description of this demonstration. */ + +#include "tx_api.h" +#include "..\demo_secure_zone\interface.h" /* Interface to sample secure functions. */ + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +static TX_THREAD thread_0; +static TX_THREAD thread_1; +static TX_THREAD thread_2; +static TX_THREAD thread_3; +static TX_THREAD thread_4; +static TX_THREAD thread_5; +static TX_THREAD thread_6; +static TX_THREAD thread_7; +static TX_QUEUE queue_0; +static TX_SEMAPHORE semaphore_0; +static TX_MUTEX mutex_0; +static TX_EVENT_FLAGS_GROUP event_flags_0; +static TX_BYTE_POOL byte_pool_0; +static TX_BLOCK_POOL block_pool_0; + +/* Define byte pool memory. */ + +static UCHAR byte_pool_memory[DEMO_BYTE_POOL_SIZE]; + + +/* Define event buffer. */ + +#ifdef TX_ENABLE_EVENT_TRACE +UCHAR trace_buffer[0x10000]; +#endif + + +/* Define the counters used in the demo application... */ + +static ULONG thread_0_counter; +static ULONG thread_1_counter; +static ULONG thread_1_messages_sent; +static ULONG thread_2_counter; +static ULONG thread_2_messages_received; +static ULONG thread_3_counter; +static ULONG thread_4_counter; +static ULONG thread_5_counter; +static ULONG thread_6_counter; +static ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Please refer to Chapter 6 of the ThreadX User Guide for a complete + description of this demonstration. */ + + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer; + + (VOID)first_unused_memory; /* unused parameter. */ + +#ifdef TX_ENABLE_EVENT_TRACE + tx_trace_enable(trace_buffer, sizeof(trace_buffer), 32); +#endif + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", byte_pool_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate secure stack space for thread. */ + tx_thread_secure_stack_allocate(&thread_0,256); + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate secure stack space for thread. */ + tx_thread_secure_stack_allocate(&thread_1,256); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate secure stack space for thread. */ + tx_thread_secure_stack_allocate(&thread_2,256); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate secure stack space for thread. */ + tx_thread_secure_stack_allocate(&thread_3,256); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate secure stack space for thread. */ + tx_thread_secure_stack_allocate(&thread_4,256); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate secure stack space for thread. */ + tx_thread_secure_stack_allocate(&thread_5,256); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate secure stack space for thread. */ + tx_thread_secure_stack_allocate(&thread_6,256); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate secure stack space for thread. */ + tx_thread_secure_stack_allocate(&thread_7,256); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + +static int callbackA (int val) +{ + return (val+1); +} + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ +UINT status; +INT test_secure; + + (VOID)thread_input; /* unused parameter. */ + + #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + /* Secure call and callback example. + Only to be used when not running in a single mode. */ + test_secure = func1(3); + test_secure = func2(callbackA, test_secure); + tx_thread_secure_stack_free(&thread_0); + #endif + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + (VOID)thread_input; /* unused parameter. */ + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + (VOID)thread_input; /* unused parameter. */ + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + (VOID)thread_input; /* unused parameter. */ + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/demo_threadx_non-secure_zone.uvoptx b/ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/demo_threadx_non-secure_zone.uvoptx new file mode 100644 index 00000000..d3d8bdd6 --- /dev/null +++ b/ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/demo_threadx_non-secure_zone.uvoptx @@ -0,0 +1,357 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + FVP Simulation Model + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 15 + + + + + + + + + + ..\Debug.ini + BIN\DbgFMv8M.DLL + + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FC1000 -FD20000000 + + + 0 + DbgFMv8M + -I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M23_MDK.exe" -MF"..\ARMCM23_TZ_config.txt" -PF -MA + + + 0 + PWSTATINFO + 200,50,700 + + + 0 + DLGTARM + (6010=3439,45,3916,641,1)(6018=1284,352,1473,701,0)(6019=1328,34,1517,370,0)(6008=1878,-297,2172,-112,1)(6009=2170,-278,2464,-93,1)(6014=1111,129,1369,860,0)(6015=872,146,1130,768,0)(6003=-1,-1,-1,-1,0)(6000=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=150,186,829,544,0)(106=511,345,1277,659,0)(107=-1,-1,-1,-1,0) + + + + + 0 + 0 + 246 + 1 +
8470
+ 0 + 0 + 0 + 0 + 0 + 1 + <3>.\tx_initialize_low_level.s + + \\demo_secure_zone\tx_initialize_low_level.s\246 + + + + + 0 + 1 + thread_0_counter + + + 1 + 1 + thread_1_counter + + + 2 + 1 + thread_2_counter + + + 3 + 1 + thread_3_counter + + + 4 + 1 + thread_4_counter + + + 5 + 1 + thread_5_counter + + + 6 + 1 + thread_6_counter + + + 7 + 1 + thread_7_counter + + + 8 + 1 + _tx_thread_current_ptr + + + + + 1 + 2 + 0x2023ffb8 + 0 + + + + + 2 + 2 + 0xE000ED28 + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Non-secure Code + 1 + 0 + 0 + 0 + + 1 + 1 + 4 + 0 + 0 + 0 + ..\ThreadX_Library.lib + ThreadX_Library.lib + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + .\demo_threadx.c + demo_threadx.c + 0 + 0 + + + + + CMSE Library + 1 + 0 + 0 + 0 + + 2 + 3 + 5 + 0 + 0 + 0 + ..\demo_secure_zone\interface.h + interface.h + 0 + 0 + + + 2 + 4 + 3 + 0 + 0 + 0 + ..\demo_secure_zone\Objects\demo_secure_zone_CMSE_Lib.o + demo_secure_zone_CMSE_Lib.o + 0 + 0 + + + + + ::CMSIS + 1 + 0 + 0 + 1 + + + + ::Device + 1 + 0 + 0 + 1 + + + diff --git a/ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/demo_threadx_non-secure_zone.uvprojx b/ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/demo_threadx_non-secure_zone.uvprojx new file mode 100644 index 00000000..ef9a5e79 --- /dev/null +++ b/ports/cortex_m23/ac5/example_build/demo_threadx_non-secure_zone/demo_threadx_non-secure_zone.uvprojx @@ -0,0 +1,602 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + FVP Simulation Model + 0x4 + ARM-ADS + 6140000::V6.14::ARMCLANG + 1 + + + ARMCM23_TZ + ARM + ARM.CMSIS.5.7.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("Cortex-M23") TZ CLOCK(12000000) ESEL ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM23_TZ$Device\ARM\ARMCM23\Include\ARMCM23_TZ.h + + + + + + + + + + + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + demo_threadx_non-secure_zone + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + -MPU + TCM.DLL + -pCM23 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 0 + -1 + + 1 + BIN\UL2V8M.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M23" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 8 + 1 + 1 + 0 + 0 + 4 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x200000 + + + 1 + 0x200000 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x20200000 + 0x20000 + + + + + + 1 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 3 + 1 + 1 + 1 + 0 + 0 + 0 + + -Wno-unused-function -Wno-visibility + + + ..\..\..\..\..\common\inc, ..\..\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\RTE\Device\ARMCM23_TZ\ARMCM23_ac6.sct + + + + + + + + + + + Non-secure Code + + + ThreadX_Library.lib + 4 + ..\ThreadX_Library.lib + + + demo_threadx.c + 1 + .\demo_threadx.c + + + + + CMSE Library + + + interface.h + 5 + ..\demo_secure_zone\interface.h + + + demo_secure_zone_CMSE_Lib.o + 3 + ..\demo_secure_zone\Objects\demo_secure_zone_CMSE_Lib.o + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + RTE\Device\ARMCM23_TZ\ARMCM23_ac6.sct + + + + + + + + RTE\Device\ARMCM23_TZ\partition_ARMCM23.h + + + + + + RTE\Device\ARMCM23_TZ\startup_ARMCM23.c + + + + + + + + RTE\Device\ARMCM23_TZ\system_ARMCM23.c + + + + + + + + RTE\Device\ARMCM33_DSP_FP\startup_ARMCM33.s + + + + + + RTE\Device\ARMCM33_DSP_FP\system_ARMCM33.c + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\ARMCM33_ac6.sct + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\partition_ARMCM33.h + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.c + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.s + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\system_ARMCM33.c + + + + + + RTE\Device\ARMCM33_TZ\partition_ARMCM33.h + + + + + + RTE\Device\ARMCM33_TZ\startup_ARMCM33.s + + + + + + RTE\Device\ARMCM33_TZ\system_ARMCM33.c + + + + + + RTE\Device\ARMv8MBL\partition_ARMv8MBL.h + + + + + + RTE\Device\ARMv8MBL\startup_ARMv8MBL.s + + + + + + RTE\Device\ARMv8MBL\system_ARMv8MBL.c + + + + + + RTE\Device\CMSDK_ARMv8MBL\RTE_Device.h + + + + + + RTE\Device\CMSDK_ARMv8MBL\partition_CMSDK_ARMv8MBL.h + + + + + + RTE\Device\CMSDK_ARMv8MBL\startup_CMSDK_ARMv8MBL.s + + + + + + RTE\Device\CMSDK_ARMv8MBL\system_CMSDK_ARMv8MBL.c + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/ports/cortex_m23/ac5/example_build/tx_initialize_low_level.S b/ports/cortex_m23/ac5/example_build/tx_initialize_low_level.S new file mode 100644 index 00000000..44135051 --- /dev/null +++ b/ports/cortex_m23/ac5/example_build/tx_initialize_low_level.S @@ -0,0 +1,240 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + IMPORT _tx_thread_system_stack_ptr + IMPORT _tx_initialize_unused_memory + IMPORT _tx_thread_context_save + IMPORT _tx_thread_context_restore + IMPORT _tx_timer_interrupt + IMPORT __main + IMPORT |Image$$RW_RAM$$ZI$$Limit| + IMPORT __Vectors + IMPORT SystemInit + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_stack_error_handler +; +; +SYSTEM_CLOCK EQU 6000000 +SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1) +; +; +;/* Setup the stack and heap areas. */ +; +STACK_SIZE EQU 0x00000400 +HEAP_SIZE EQU 0x00000000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +StackMem + SPACE STACK_SIZE +__initial_sp + + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +HeapMem + SPACE HEAP_SIZE +__heap_limit + + + AREA ||.text||, CODE, READONLY + PRESERVE8 + + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-M23/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + EXPORT _tx_initialize_low_level +_tx_initialize_low_level FUNCTION +; +; /* Disable interrupts during ThreadX initialization. */ +; + CPSID i +; +; /* Set base of available memory to end of non-initialised RAM area. */ +; + LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer + LDR r1, =|Image$$RW_RAM$$ZI$$Limit| ; Build first free address + ADDS r1, r1, #4 ; + STR r1, [r0] ; Setup first unused memory pointer +; +; /* Setup Vector Table Offset Register. */ +; + LDR r0, =0xE000ED08 ; Build address of NVIC registers + LDR r1, =__Vectors ; Pickup address of vector table + STR r1, [r0] ; Set vector table address +; +; /* Enable the cycle count register. */ +; +; LDR r0, =0xE0001000 ; Build address of DWT register +; LDR r1, [r0] ; Pickup the current value +; ORR r1, r1, #1 ; Set the CYCCNTENA bit +; STR r1, [r0] ; Enable the cycle count register +; +; /* Set system stack pointer from vector value. */ +; + LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer + LDR r1, =__Vectors ; Pickup address of vector table + LDR r1, [r1] ; Pickup reset stack pointer + STR r1, [r0] ; Save system stack pointer +; +; /* Configure SysTick. */ +; + LDR r0, =0xE000E000 ; Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] ; Setup SysTick Reload Value + MOV r1, #0x7 ; Build SysTick Control Enable Value + STR r1, [r0, #0x10] ; Setup SysTick Control +; +; /* Configure handler priorities. */ +; + LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM + LDR r0, =0xE000E000 ; Build address of NVIC registers + LDR r2, =0xD18 ; + ADD r0, r0, r2 ; + STR r1, [r0] ; Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv + LDR r0, =0xE000E000 ; Build address of NVIC registers + LDR r2, =0xD1C ; + ADD r0, r0, r2 ; + STR r1, [r0] ; Setup System Handlers 8-11 Priority Registers + ; Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM + LDR r0, =0xE000E000 ; Build address of NVIC registers + LDR r2, =0xD20 ; + ADD r0, r0, r2 ; + STR r1, [r0] ; Setup System Handlers 12-15 Priority Registers + ; Note: PnSV must be lowest priority, which is 0xFF +; +; /* Return to caller. */ +; + BX lr + ENDFUNC +;} +; +; +;/* Define initial heap/stack routine for the ARM startup code. +; This routine will set the initial stack and heap locations. */ +; + EXPORT __user_initial_stackheap +__user_initial_stackheap FUNCTION + LDR r0, =HeapMem + LDR r1, =(StackMem + STACK_SIZE) + LDR r2, =(HeapMem + HEAP_SIZE) + LDR r3, =StackMem + BX lr + ENDFUNC +; +; +;/* Define shells for each of the unused vectors. */ +; + EXPORT __tx_BadHandler +__tx_BadHandler FUNCTION + B __tx_BadHandler + ENDFUNC + + EXPORT __tx_IntHandler +__tx_IntHandler FUNCTION +; VOID InterruptHandler (VOID) +; { + PUSH {r0, lr} ; Save LR (and dummy r0 to maintain stack alignment) + +; /* Do interrupt handler work here */ +; /* .... */ + + POP {r0, r1} + MOV lr, r1 + BX lr +; } + ENDFUNC + + + EXPORT __tx_SysTickHandler + EXPORT SysTick_Handler +SysTick_Handler FUNCTION +__tx_SysTickHandler +; VOID TimerInterruptHandler (VOID) +; { +; + PUSH {r0, lr} ; Save LR (and dummy r0 to maintain stack alignment) + BL _tx_timer_interrupt + POP {r0, r1} + MOV lr, r1 + BX lr +; } + ENDFUNC + + + EXPORT HardFault_Handler +HardFault_Handler FUNCTION + ; A stack overflow will trigger a hardfault. + ; There is no CFSR in M23, so we will not try to + ; determine if the fault is caused by a stack overflow + ; or some other condition. + B HardFault_Handler + ENDFUNC + + ALIGN + LTORG + END diff --git a/ports/cortex_m23/ac5/inc/tx_port.h b/ports/cortex_m23/ac5/inc/tx_port.h new file mode 100644 index 00000000..0ac7a7ff --- /dev/null +++ b/ports/cortex_m23/ac5/inc/tx_port.h @@ -0,0 +1,418 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-M23/AC5 */ +/* 6.1 */ +/* */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + +/* Determine if the optional ThreadX user define file should be used. */ +#ifdef TX_INCLUDE_USER_DEFINE_FILE + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + +/* Define compiler library include files. */ + +#include +#include +#include +#include "ARMCM23_TZ.h" /* For intrinsic functions. */ + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef unsigned long long ULONG64; +typedef short SHORT; +typedef unsigned short USHORT; + +/* Function prototypes for this port. */ +struct TX_THREAD_STRUCT; +UINT _txe_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *thread_ptr, ULONG stack_size); +UINT _txe_thread_secure_stack_free(struct TX_THREAD_STRUCT *thread_ptr); +UINT _tx_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *tx_thread, ULONG stack_size); +UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); + +/* This hardware has stack checking that we take advantage of - do NOT define. */ +#ifdef TX_ENABLE_STACK_CHECKING + #error "Do not define TX_ENABLE_STACK_CHECKING" +#endif + +/* If user does not want to terminate thread on stack overflow, + #define the TX_THREAD_NO_TERMINATE_STACK_ERROR symbol. + The thread will be rescheduled and continue to cause the exception. + It is suggested user code handle this by registering a notification with the + tx_thread_stack_error_notify function. */ +/*#define TX_THREAD_NO_TERMINATE_STACK_ERROR */ + +/* Define the system API mappings based on the error checking + selected by the user. Note: this section is only applicable to + application source code, hence the conditional that turns off this + stuff when the include file is processed by the ThreadX source. */ + +#ifndef TX_SOURCE_CODE + + +/* Determine if error checking is desired. If so, map API functions + to the appropriate error checking front-ends. Otherwise, map API + functions to the core functions that actually perform the work. + Note: error checking is enabled by default. */ + +#ifdef TX_DISABLE_ERROR_CHECKING + +/* Services without error checking. */ + +#define tx_thread_secure_stack_allocate _tx_thread_secure_stack_allocate +#define tx_thread_secure_stack_free _tx_thread_secure_stack_free + +#else + +/* Services with error checking. */ + +#define tx_thread_secure_stack_allocate _txe_thread_secure_stack_allocate +#define tx_thread_secure_stack_free _txe_thread_secure_stack_free + +#endif +#endif + + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX Cortex-M23 port. */ + +#define TX_INT_DISABLE 1 /* Disable interrupts */ +#define TX_INT_ENABLE 0 /* Enable interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) +#endif +#else +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif + +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_secure_stack_context; +#else +#define TX_THREAD_EXTENSION_2 +#endif +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) if(thread_ptr -> tx_thread_secure_stack_context){_tx_thread_secure_stack_free(thread_ptr);} +#else +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +/* Define the size of the secure stack for the timer thread and use the extension to allocate the secure stack. */ +#define TX_TIMER_THREAD_SECURE_STACK_SIZE 256 +#define TX_TIMER_INITIALIZE_EXTENSION(status) _tx_thread_secure_stack_allocate(&_tx_timer_thread, TX_TIMER_THREAD_SECURE_STACK_SIZE); +#endif + + +#ifndef TX_MISRA_ENABLE + +//register unsigned int _ipsr __asm ("MRS %[result], ipsr" : [result] "=r" (_ipsr) : ); +inline static unsigned int _get_ipsr(void); +inline static unsigned int _get_ipsr(void) +{ + unsigned int _ipsr; + __asm("MRS %[result], ipsr" : [result] "=r" (_ipsr) : ); + return _ipsr; +} + +#endif + + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define the get system state macro. */ + +#ifndef TX_THREAD_GET_SYSTEM_STATE +#ifndef TX_MISRA_ENABLE +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _get_ipsr()) +#else +ULONG _tx_misra_ipsr_get(VOID); +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get()) +#endif +#endif + + +/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value + indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h + for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always + zero after initialization for Cortex-M ports. */ + +#ifndef TX_THREAD_SYSTEM_RETURN_CHECK +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#endif + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +/* Initialize secure stacks for threads calling secure functions. */ +extern void _tx_thread_secure_stack_initialize(void); +#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION _tx_thread_secure_stack_initialize(); +#endif + +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to + prevent early scheduling on Cortex-M parts. */ + +#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); + +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifdef TX_DISABLE_INLINE + +UINT _tx_thread_interrupt_disable(VOID); +VOID _tx_thread_interrupt_restore(UINT previous_posture); + +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); + +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA unsigned int was_masked; +#define TX_DISABLE was_masked = __disable_irq(); +#define TX_RESTORE if (was_masked == 0) __enable_irq(); + +#define _tx_thread_system_return _tx_thread_system_return_inline + + +static void _tx_thread_system_return_inline(void) +{ +unsigned int was_masked; + + + /* Set PendSV to invoke ThreadX scheduler. */ + *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + if (_get_ipsr() == 0) + { + was_masked = __disable_irq(); + __enable_irq(); + if (was_masked != 0) + __disable_irq(); + } +} +#endif + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/AC5 Version 6.1 *"; +#else +#ifdef TX_MISRA_ENABLE +extern CHAR _tx_version_id[100]; +#else +extern CHAR _tx_version_id[]; +#endif +#endif + +#endif diff --git a/ports/cortex_m23/ac5/inc/tx_secure_interface.h b/ports/cortex_m23/ac5/inc/tx_secure_interface.h new file mode 100644 index 00000000..976f32be --- /dev/null +++ b/ports/cortex_m23/ac5/inc/tx_secure_interface.h @@ -0,0 +1,60 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* tx_secure_interface.h Cortex-M23 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the ThreadX secure thread stack components, */ +/* including data types and external references. */ +/* It is assumed that tx_api.h and tx_port.h have already been */ +/* included. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_SECURE_INTERFACE_H +#define TX_SECURE_INTERFACE_H + +/* Define internal secure thread stack function prototypes. */ + +extern void _tx_thread_secure_stack_initialize(void); +extern UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size); +extern UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr); +extern void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr); +extern void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr); + +#endif diff --git a/ports/cortex_m23/ac5/readme_threadx.txt b/ports/cortex_m23/ac5/readme_threadx.txt new file mode 100644 index 00000000..7c60c2c4 --- /dev/null +++ b/ports/cortex_m23/ac5/readme_threadx.txt @@ -0,0 +1,154 @@ + Microsoft's Azure RTOS ThreadX for Cortex-M23 + + Using the AC5 Tools in Keil uVision + +1. Import the ThreadX Projects + +In order to build the ThreadX library and the ThreadX demonstration, first open +the AzureRTOS.uvmpw workspace (located in the "example_build" directory) +into Keil. + + +2. Building the ThreadX run-time Library + +Building the ThreadX library is easy; simply set the ThreadX_Library project +as active, then then build the library. You should now observe the compilation +and assembly of the ThreadX library. This project build produces the ThreadX +library file ThreadX_Library.lib. + + +3. Demonstration System + +The ThreadX demonstration is designed to execute under the Keil debugger on the +FVP_MPS2_Cortex-M23_MDK simulator. + +Building the demonstration is easy; simply select the "Batch Build" button. +You should now observe the compilation and assembly of the ThreadX demonstration of +both the demo_secure_zone and demo_threadx_non-secure_zone projects. +Then click the Start/Stop Debug Session button to start the simulator and begin debugging. +You are now ready to execute the ThreadX demonstration. + + +4. System Initialization + +The entry point in ThreadX for the Cortex-M23 using AC5 tools uses the standard AC5 +Cortex-M23 reset sequence. From the reset vector the C runtime will be initialized. + +The ThreadX tx_initialize_low_level.S file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. + +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input +parameter to your application definition function, tx_application_define. + + +5. Register Usage and Stack Frames + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have the same stack frame in the Cortex-M23 version of +ThreadX. The top of the suspended thread's stack is pointed to by +tx_thread_stack_ptr in the associated thread control block TX_THREAD. + + + Stack Offset Stack Contents + + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 r8 + 0x08 r9 + 0x0C r10 + 0x10 r11 + 0x14 r4 + 0x18 r5 + 0x1C r6 + 0x20 r7 + 0x24 r0 (Hardware stack starts here!!) + 0x28 r1 + 0x2C r2 + 0x30 r3 + 0x34 r12 + 0x38 lr + 0x3C pc + 0x40 xPSR + + +6. Improving Performance + +To make ThreadX and the application(s) run faster, you can enable +all compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-M23 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +7.1 Vector Area + +The Cortex-M23 vectors start at the label __Vectors or similar. The application may modify +the vector area according to its needs. There is code in tx_initialize_low_level() that will +configure the vector base register. + + +7.2 Managed Interrupts + +ISRs can be written completely in C (or assembly language) without any calls to +_tx_thread_context_save or _tx_thread_context_restore. These ISRs are allowed access to the +ThreadX API that is available to ISRs. + +ISRs written in C will take the form (where "your_C_isr" is an entry in the vector table): + +void your_C_isr(void) +{ + + /* ISR processing goes here, including any needed function calls. */ +} + +ISRs written in assembly language will take the form: + + + .global your_assembly_isr + .thumb_func +your_assembly_isr: +; VOID your_assembly_isr(VOID) +; { + PUSH {r0, lr} +; +; /* Do interrupt handler work here */ +; /* BL */ + + POP {r0, r1} + MOV lr, r1 + BX lr +; } + + +Note: the Cortex-M23 requires exception handlers to be thumb labels, this implies bit 0 set. +To accomplish this, the declaration of the label has to be preceded by the assembler directive +.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to +be inserted in the correct location in the interrupt vector table. This table is typically +located in either your runtime startup file or in the tx_initialize_low_level.S file. + + +8. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + + +09-30-2020 Initial ThreadX 6.1 version for Cortex-M23 using AC5 tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_m23/ac5/src/tx_thread_context_restore.s b/ports/cortex_m23/ac5/src/tx_thread_context_restore.s new file mode 100644 index 00000000..6a3e9a49 --- /dev/null +++ b/ports/cortex_m23/ac5/src/tx_thread_context_restore.s @@ -0,0 +1,75 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-M23/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is not needed for Cortex-M. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* None */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + EXPORT _tx_thread_context_restore +_tx_thread_context_restore FUNCTION +; +; /* Return to interrupt processing. */ +; + BX lr +;} + ENDFUNC + ALIGN + LTORG + END diff --git a/ports/cortex_m23/ac5/src/tx_thread_context_save.s b/ports/cortex_m23/ac5/src/tx_thread_context_save.s new file mode 100644 index 00000000..6db66b25 --- /dev/null +++ b/ports/cortex_m23/ac5/src/tx_thread_context_save.s @@ -0,0 +1,75 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-M23/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is not needed for Cortex-M. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* None */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + EXPORT _tx_thread_context_save +_tx_thread_context_save FUNCTION +; +; /* Return to interrupt processing. */ +; + BX lr +;} + ENDFUNC + ALIGN + LTORG + END diff --git a/ports/cortex_m23/ac5/src/tx_thread_interrupt_control.s b/ports/cortex_m23/ac5/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..3065564b --- /dev/null +++ b/ports/cortex_m23/ac5/src/tx_thread_interrupt_control.s @@ -0,0 +1,78 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-M23/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + EXPORT _tx_thread_interrupt_control +_tx_thread_interrupt_control FUNCTION +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r1, PRIMASK + MSR PRIMASK, r0 + MOV r0, r1 + BX lr +; +;} + ENDFUNC + END diff --git a/ports/cortex_m23/ac5/src/tx_thread_interrupt_disable.s b/ports/cortex_m23/ac5/src/tx_thread_interrupt_disable.s new file mode 100644 index 00000000..89ada0be --- /dev/null +++ b/ports/cortex_m23/ac5/src/tx_thread_interrupt_disable.s @@ -0,0 +1,77 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-M23/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts and returning */ +;/* the previous interrupt lockout posture. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_disable(UINT new_posture) +;{ + EXPORT _tx_thread_interrupt_disable +_tx_thread_interrupt_disable FUNCTION +; +; /* Return current interrupt lockout posture. */ +; + MRS r0, PRIMASK + CPSID i + BX lr +; +;} + ENDFUNC + END diff --git a/ports/cortex_m23/ac5/src/tx_thread_interrupt_restore.s b/ports/cortex_m23/ac5/src/tx_thread_interrupt_restore.s new file mode 100644 index 00000000..30723b44 --- /dev/null +++ b/ports/cortex_m23/ac5/src/tx_thread_interrupt_restore.s @@ -0,0 +1,76 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-M23/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for restoring the previous */ +;/* interrupt lockout posture. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* previous_posture Previous interrupt posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_interrupt_restore(UINT new_posture) +;{ + EXPORT _tx_thread_interrupt_restore +_tx_thread_interrupt_restore FUNCTION +; +; /* Restore previous interrupt lockout posture. */ +; + MSR PRIMASK, r0 + BX lr +; +;} + ENDFUNC + END diff --git a/ports/cortex_m23/ac5/src/tx_thread_schedule.s b/ports/cortex_m23/ac5/src/tx_thread_schedule.s new file mode 100644 index 00000000..84ac8c15 --- /dev/null +++ b/ports/cortex_m23/ac5/src/tx_thread_schedule.s @@ -0,0 +1,347 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_execute_ptr + IMPORT _tx_timer_time_slice + IMPORT _tx_thread_system_stack_ptr + IMPORT _tx_thread_preempt_disable + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_thread_enter + IMPORT _tx_execution_thread_exit + ENDIF + + IF :LNOT::DEF: TX_SINGLE_MODE_SECURE :LAND: :LNOT::DEF: TX_SINGLE_MODE_NON_SECURE + IMPORT _tx_thread_secure_stack_context_restore + IMPORT _tx_thread_secure_stack_context_save + IMPORT _tx_thread_secure_mode_stack_allocate + IMPORT _tx_thread_secure_mode_stack_free + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-M23/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + EXPORT _tx_thread_schedule +_tx_thread_schedule FUNCTION +; +; /* This function should only ever be called on Cortex-M +; from the first schedule request. Subsequent scheduling occurs +; from the PendSV handling routines below. */ +; +; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ +; + MOV r0, #0 ; Build value for TX_FALSE + LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag + STR r0, [r2, #0] ; Clear preempt disable flag +; +; /* Enable interrupts */ +; + CPSIE i +; +; /* Enter the scheduler for the first time. */ +; + LDR r0, =0x10000000 ; Load PENDSVSET bit + LDR r1, =0xE000ED04 ; Load ICSR address + STR r0, [r1] ; Set PENDSVBIT in ICSR + DSB ; Complete all memory accesses + ISB ; Flush pipeline +; +; /* Wait here for the PendSV to take place. */ +; +__tx_wait_here + B __tx_wait_here ; Wait for the PendSV to happen + ENDFUNC +;} +; +; /* Generic context switching PendSV handler. */ +; + EXPORT PendSV_Handler +PendSV_Handler FUNCTION +; +; /* Get current thread value and new thread pointer. */ +; +__tx_ts_handler + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + CPSID i ; Disable interrupts + PUSH {r0, lr} ; Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit ; Call the thread exit function + POP {r0, r1} ; Recover LR + MOV lr, r1 ; + CPSIE i ; Enable interrupts + ENDIF + + MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address + MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address + MOV r3, #0 ; Build NULL value + LDR r1, [r0] ; Pickup current thread pointer +; +; /* Determine if there is a current thread to finish preserving. */ +; + CBZ r1, __tx_ts_new ; If NULL, skip preservation +; +; /* Recover PSP and preserve current thread context. */ +; + STR r3, [r0] ; Set _tx_thread_current_ptr to NULL + MRS r3, PSP ; Pickup PSP pointer (thread's stack pointer) + SUBS r3, r3, #16 ; Allocate stack space + STM r3!, {r4-r7} ; Save its remaining registers (M3 Instruction: STMDB r12!, {r4-r11}) + MOV r4, r8 ; + MOV r5, r9 ; + MOV r6, r10 ; + MOV r7, r11 ; + SUBS r3, r3, #32 ; Allocate stack space + STM r3!, {r4-r7} ; + SUBS r3, r3, #20 ; Allocate stack space + MOV r5, lr ; + STR r5, [r3] ; Save LR on the stack + STR r3, [r1, #8] ; Save its stack pointer + + IF :LNOT::DEF: TX_SINGLE_MODE_SECURE :LAND: :LNOT::DEF: TX_SINGLE_MODE_NON_SECURE + ; Save secure context + LDR r5, =0x90 ; Secure stack index offset + LDR r5, [r1, r5] ; Load secure stack index + CBZ r5, _skip_secure_save ; Skip save if there is no secure context + PUSH {r0, r1, r2, r3} ; Save scratch registers + MOV r0, r1 ; Move thread ptr to r0 + BL _tx_thread_secure_stack_context_save ; Save secure stack + POP {r0, r1, r2, r3} ; Restore secure registers +_skip_secure_save + ENDIF +; +; /* Determine if time-slice is active. If it isn't, skip time handling processing. */ +; + LDR r4, =_tx_timer_time_slice ; Build address of time-slice variable + LDR r5, [r4] ; Pickup current time-slice + CBZ r5, __tx_ts_new ; If not active, skip processing +; +; /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ +; + STR r5, [r1, #24] ; Save current time-slice +; +; /* Clear the global time-slice. */ +; + MOVS r5, #0 ; Build clear value + STR r5, [r4] ; Clear time-slice +; +; /* Executing thread is now completely preserved!!! */ +; +__tx_ts_new +; +; /* Now we are looking for a new thread to execute! */ +; + CPSID i ; Disable interrupts + LDR r1, [r2] ; Is there another thread ready to execute? + CBZ r1, __tx_ts_wait ; No, skip to the wait processing +; +; /* Yes, another thread is ready for else, make the current thread the new thread. */ +; + STR r1, [r0] ; Setup the current thread pointer to the new thread + CPSIE i ; Enable interrupts +; +; /* Increment the thread run count. */ +; +__tx_ts_restore + LDR r7, [r1, #4] ; Pickup the current thread run count + MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable + LDR r5, [r1, #24] ; Pickup thread's current time-slice + ADDS r7, r7, #1 ; Increment the thread run count + STR r7, [r1, #4] ; Store the new run count +; +; /* Setup global time-slice with thread's current time-slice. */ +; + STR r5, [r4] ; Setup global time-slice + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + PUSH {r0, r1} ; Save r0/r1 + BL _tx_execution_thread_enter ; Call the thread execution enter function + POP {r0, r1} ; Recover r0/r1 + ENDIF + + IF :LNOT::DEF: TX_SINGLE_MODE_SECURE :LAND: :LNOT::DEF: TX_SINGLE_MODE_NON_SECURE + ; Restore secure context + LDR r5, =0x90 ; Secure stack index offset + LDR r0, [r1, r5] ; Load secure stack index + CBZ r0, _skip_secure_restore ; Skip restore if there is no secure context + PUSH {r0, r1} ; Save r1 (and dummy r0) + MOV r0, r1 ; Move thread ptr to r0 + BL _tx_thread_secure_stack_context_restore ; Restore secure stack + POP {r0, r1} ; Restore r1 (and dummy r0) +_skip_secure_restore + ENDIF + +; +; /* Restore the thread context and PSP. */ +; + IF :DEF: TX_SINGLE_MODE_SECURE + ; There are only stack limit registers in secure mode on the M23 + LDR r3, [r1, #12] ; Get stack start + MSR PSPLIM, r3 ; Set stack limit + ENDIF + + LDR r3, [r1, #8] ; Pickup thread's stack pointer + LDR r5, [r3] ; Recover saved LR + ADDS r3, r3, #4 ; Position past LR + MOV lr, r5 ; Restore LR + LDM r3!, {r4-r7} ; Recover thread's registers (r4-r11) + MOV r11, r7 ; + MOV r10, r6 ; + MOV r9, r5 ; + MOV r8, r4 ; + LDM r3!, {r4-r7} ; + MSR PSP, r3 ; Setup the thread's stack pointer +; +; /* Return to thread. */ +; + BX lr ; Return to thread! +; +; /* The following is the idle wait processing... in this case, no threads are ready for execution and the +; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +; are disabled to allow use of WFI for waiting for a thread to arrive. */ +; +__tx_ts_wait + CPSID i ; Disable interrupts + LDR r1, [r2] ; Pickup the next thread to execute pointer + STR r1, [r0] ; Store it in the current pointer + CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready! + IF :DEF:TX_ENABLE_WFI + DSB ; Ensure no outstanding memory transactions + WFI ; Wait for interrupt + ISB ; Ensure pipeline is flushed + ENDIF + CPSIE i ; Enable interrupts + B __tx_ts_wait ; Loop to continue waiting +; +; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +; already in the handler! */ +; +__tx_ts_ready + LDR r7, =0x08000000 ; Build clear PendSV value + LDR r5, =0xE000ED04 ; Build ICSR address + STR r7, [r5] ; Clear any PendSV +; +; /* Re-enable interrupts and restore new thread. */ +; + CPSIE i ; Enable interrupts + B __tx_ts_restore ; Restore the thread + ENDFUNC + + + + IF :LNOT::DEF: TX_SINGLE_MODE_SECURE :LAND: :LNOT::DEF: TX_SINGLE_MODE_NON_SECURE + ; SVC_Handler is not needed when ThreadX is running in single mode. + EXPORT SVC_Handler +SVC_Handler FUNCTION + MOVS r0, #4 + MOV r1, lr + TST r1, r0 ; Determine return stack from EXC_RETURN bit 2 + BEQ _tx_get_msp + MRS r0, PSP ; Get PSP if return stack is PSP + B _tx_got_sp +_tx_get_msp + MRS r0, MSP ; Get MSP if return stack is MSP +_tx_got_sp + LDR r1, [r0, #24] ; Load saved PC from stack + SUBS r1, r1, #2 ; Calculate SVC number address + LDRB r1, [r1] ; Load SVC number + + CMP r1, #1 ; Is it a secure stack allocate request? + BEQ _tx_svc_secure_alloc ; Yes, go there + + CMP r1, #2 ; Is it a secure stack free request? + BEQ _tx_svc_secure_free ; Yes, go there + + ; Unknown SVC argument - just return + BX lr + +_tx_svc_secure_alloc + PUSH {r0, lr} ; Save SP and EXC_RETURN + LDM r0, {r0-r3} ; Load function parameters from stack + BL _tx_thread_secure_mode_stack_allocate + POP {r1, r2} ; Restore SP and EXC_RETURN + STR r0, [r1] ; Store function return value + MOV lr, r2 + BX lr +_tx_svc_secure_free + PUSH {r0, lr} ; Save SP and EXC_RETURN + LDM r0, {r0-r3} ; Load function parameters from stack + BL _tx_thread_secure_mode_stack_free + POP {r1, r2} ; Restore SP and EXC_RETURN + STR r0, [r1] ; Store function return value + MOV lr, r2 + BX lr + ENDFUNC + ENDIF ; End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE + + ALIGN + LTORG + END diff --git a/ports/cortex_m23/ac5/src/tx_thread_secure_stack.c b/ports/cortex_m23/ac5/src/tx_thread_secure_stack.c new file mode 100644 index 00000000..43a31427 --- /dev/null +++ b/ports/cortex_m23/ac5/src/tx_thread_secure_stack.c @@ -0,0 +1,467 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +#include "tx_api.h" + +/* If TX_SINGLE_MODE_SECURE or TX_SINGLE_MODE_NON_SECURE is defined, + no secure stack functionality is needed. */ +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + +#define TX_SOURCE_CODE + +#include "ARMCM23_TZ.h" /* For intrinsic functions. */ +#include "tx_secure_interface.h" /* Interface for NS code. */ + +/* Minimum size of secure stack. */ +#ifndef TX_THREAD_SECURE_STACK_MINIMUM +#define TX_THREAD_SECURE_STACK_MINIMUM 256 +#endif +/* Maximum size of secure stack. */ +#ifndef TX_THREAD_SECURE_STACK_MAXIMUM +#define TX_THREAD_SECURE_STACK_MAXIMUM 1024 +#endif + +/* Secure stack info struct to hold stack start, stack limit, + current stack pointer, and pointer to owning thread. + This will be allocated for each thread with a secure stack. */ +typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT +{ + VOID *tx_thread_secure_stack_ptr; /* Thread's secure stack current pointer */ + VOID *tx_thread_secure_stack_start; /* Thread's secure stack start address */ + VOID *tx_thread_secure_stack_limit; /* Thread's secure stack limit */ + TX_THREAD *tx_thread_ptr; /* Keep track of thread for error handling */ +} TX_THREAD_SECURE_STACK_INFO; + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_initialize Cortex-M23/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes secure mode to use PSP stack. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __get_CONTROL Intrinsic to get CONTROL */ +/* __set_CONTROL Intrinsic to set CONTROL */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +void _tx_thread_secure_stack_initialize(void) +{ + + /* Set secure mode to use PSP. */ + __set_CONTROL(__get_CONTROL() | 2); + + /* Set process stack pointer and stack limit to 0 to throw exception when a thread + without a secure stack calls a secure function that tries to use secure stack. */ + __set_PSPLIM(0); + __set_PSP(0); + + return; +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_mode_stack_allocate Cortex-M23/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function allocates a thread's secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* stack_size Size of stack to allocates */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_SIZE_ERROR Invalid stack size */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* calloc Compiler's calloc function */ +/* malloc Compiler's malloc function */ +/* free Compiler's free() function */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* __TZ_get_PSPLIM_NS Intrinsic to get NS PSP */ +/* */ +/* CALLED BY */ +/* */ +/* SVC Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +{ +UINT status; +TX_THREAD_SECURE_STACK_INFO *info_ptr; +UCHAR *stack_mem; +ULONG sp; + + status = TX_SUCCESS; + + /* Make sure function is called from interrupt (threads should not call). */ + if (__get_IPSR() == 0) + { + status = TX_CALLER_ERROR; + } + else if (stack_size < TX_THREAD_SECURE_STACK_MINIMUM || stack_size > TX_THREAD_SECURE_STACK_MAXIMUM) + { + status = TX_SIZE_ERROR; + } + + /* Check if thread already has secure stack allocated. */ + else if (thread_ptr -> tx_thread_secure_stack_context != 0) + { + status = TX_THREAD_ERROR; + } + + else + { + /* Allocate space for secure stack info. */ + info_ptr = calloc(1, sizeof(TX_THREAD_SECURE_STACK_INFO)); + + if(info_ptr != TX_NULL) + { + /* If stack info allocated, allocate a stack. */ + stack_mem = malloc(stack_size); + + if(stack_mem != TX_NULL) + { + /* Secure stack has been allocated, save in the stack info struct. */ + info_ptr -> tx_thread_secure_stack_limit = stack_mem; + info_ptr -> tx_thread_secure_stack_start = stack_mem + stack_size; + info_ptr -> tx_thread_secure_stack_ptr = info_ptr -> tx_thread_secure_stack_start; + info_ptr -> tx_thread_ptr = thread_ptr; + + /* Save info pointer in thread. */ + thread_ptr -> tx_thread_secure_stack_context = info_ptr; + + /* Check if this thread is running by looking at PSP_NS and seeing if it is within + the stack_start and stack_end range. */ + sp = __TZ_get_PSP_NS(); + if(sp > ((ULONG) thread_ptr -> tx_thread_stack_start) && sp < ((ULONG) thread_ptr -> tx_thread_stack_end)) + { + /* If this thread is running, set Secure PSP and PSPLIM. */ + __set_PSPLIM((ULONG)(info_ptr -> tx_thread_secure_stack_limit)); + __set_PSP((ULONG)(info_ptr -> tx_thread_secure_stack_ptr)); + } + } + + else + { + /* Stack not allocated, free the info struct. */ + free(info_ptr); + status = TX_NO_MEMORY; + } + } + + else + { + status = TX_NO_MEMORY; + } + } + + return(status); +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_mode_stack_free Cortex-M23/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function frees a thread's secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* free Compiler's free() function */ +/* */ +/* CALLED BY */ +/* */ +/* SVC Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr) +{ +UINT status; +TX_THREAD_SECURE_STACK_INFO *info_ptr; + + status = TX_SUCCESS; + + /* Pickup stack info from thread. */ + info_ptr = thread_ptr -> tx_thread_secure_stack_context; + + /* Make sure function is called from interrupt (threads should not call). */ + if (__get_IPSR() == 0) + { + status = TX_CALLER_ERROR; + } + + /* Check that this secure context is for this thread. */ + else if (info_ptr -> tx_thread_ptr != thread_ptr) + { + status = TX_THREAD_ERROR; + } + + else + { + + /* Free secure stack. */ + free(info_ptr -> tx_thread_secure_stack_limit); + + /* Free info struct. */ + free(info_ptr); + + /* Clear secure context from thread. */ + thread_ptr -> tx_thread_secure_stack_context = 0; + } + + return(status); +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_context_save Cortex-M23/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves context of the secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* __get_PSP Intrinsic to get PSP */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* */ +/* CALLED BY */ +/* */ +/* PendSV Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr) +{ +TX_THREAD_SECURE_STACK_INFO *info_ptr; +ULONG sp; + + /* This function should be called from scheduler only. */ + if (__get_IPSR() == 0) + { + return; + } + + /* Pickup the secure context pointer. */ + info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); + + /* Check that this secure context is for this thread. */ + if (info_ptr -> tx_thread_ptr != thread_ptr) + { + return; + } + + /* Check that stack pointer is in range */ + sp = __get_PSP(); + if ((sp < (ULONG)info_ptr -> tx_thread_secure_stack_limit) || + (sp > (ULONG)info_ptr -> tx_thread_secure_stack_start)) + { + return; + } + + /* Save stack pointer. */ + *(ULONG *) info_ptr -> tx_thread_secure_stack_ptr = sp; + + /* Set process stack pointer and stack limit to 0 to throw exception when a thread + without a secure stack calls a secure function that tries to use secure stack. */ + __set_PSPLIM(0); + __set_PSP(0); + + return; +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_context_restore Cortex-M23/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores context of the secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* */ +/* CALLED BY */ +/* */ +/* PendSV Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr) +{ +TX_THREAD_SECURE_STACK_INFO *info_ptr; + + /* This function should be called from scheduler only. */ + if (__get_IPSR() == 0) + { + return; + } + + /* Pickup the secure context pointer. */ + info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); + + /* Check that this secure context is for this thread. */ + if (info_ptr -> tx_thread_ptr != thread_ptr) + { + return; + } + + /* Set stack pointer and limit. */ + __set_PSPLIM((ULONG)info_ptr -> tx_thread_secure_stack_limit); + __set_PSP ((ULONG)info_ptr -> tx_thread_secure_stack_ptr); + + return; +} + +#endif diff --git a/ports/cortex_m23/ac5/src/tx_thread_secure_stack_allocate.s b/ports/cortex_m23/ac5/src/tx_thread_secure_stack_allocate.s new file mode 100644 index 00000000..ffceb7ec --- /dev/null +++ b/ports/cortex_m23/ac5/src/tx_thread_secure_stack_allocate.s @@ -0,0 +1,82 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_secure_stack_allocate Cortex-M23/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function enters the SVC handler to allocate a secure stack. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Thread control block pointer */ +;/* stack_size Size of secure stack to */ +;/* allocate */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* status Actual completion status */ +;/* */ +;/* CALLS */ +;/* */ +;/* SVC 1 */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +;{ + EXPORT _tx_thread_secure_stack_allocate +_tx_thread_secure_stack_allocate FUNCTION + IF :LNOT::DEF: TX_SINGLE_MODE_SECURE :LAND: :LNOT::DEF: TX_SINGLE_MODE_NON_SECURE + MRS r3, PRIMASK ; Save interrupt mask + CPSIE i ; Enable interrupts for SVC call + SVC 1 + CMP r3, #0 ; If interrupts enabled, just return + BEQ _alloc_return_interrupt_enabled + CPSID i ; Otherwise, disable interrupts + ELSE + MOV32 r0, #0xFF ; Feature not enabled + ENDIF +_alloc_return_interrupt_enabled + BX lr + ENDFUNC + END diff --git a/ports/cortex_m23/ac5/src/tx_thread_secure_stack_free.s b/ports/cortex_m23/ac5/src/tx_thread_secure_stack_free.s new file mode 100644 index 00000000..efee2766 --- /dev/null +++ b/ports/cortex_m23/ac5/src/tx_thread_secure_stack_free.s @@ -0,0 +1,80 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_secure_stack_free Cortex-M23/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function enters the SVC handler to free a secure stack. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Thread control block pointer */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* status Actual completion status */ +;/* */ +;/* CALLS */ +;/* */ +;/* SVC 2 */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) +;{ + EXPORT _tx_thread_secure_stack_free +_tx_thread_secure_stack_free FUNCTION + IF :LNOT::DEF: TX_SINGLE_MODE_SECURE :LAND: :LNOT::DEF: TX_SINGLE_MODE_NON_SECURE + MRS r3, PRIMASK ; Save interrupt mask + CPSIE i ; Enable interrupts for SVC call + SVC 2 + CMP r3, #0 ; If interrupts enabled, just return + BEQ _free_return_interrupt_enabled + CPSID i ; Otherwise, disable interrupts + ELSE + MOV32 r0, #0xFF ; Feature not enabled + ENDIF +_free_return_interrupt_enabled + BX lr + ENDFUNC + END diff --git a/ports/cortex_m23/ac5/src/tx_thread_stack_build.s b/ports/cortex_m23/ac5/src/tx_thread_stack_build.s new file mode 100644 index 00000000..4fdd0a07 --- /dev/null +++ b/ports/cortex_m23/ac5/src/tx_thread_stack_build.s @@ -0,0 +1,139 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-M23/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + EXPORT _tx_thread_stack_build +_tx_thread_stack_build FUNCTION +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-M23 should look like the following after it is built: +; +; Stack Top: +; LR Interrupted LR (LR at time of PENDSV) +; r8 Initial value for r8 +; r9 Initial value for r9 +; r10 Initial value for r10 +; r11 Initial value for r11 +; r4 Initial value for r4 +; r5 Initial value for r5 +; r6 Initial value for r6 +; r7 Initial value for r7 +; r0 Initial value for r0 (Hardware stack starts here!!) +; r1 Initial value for r1 +; r2 Initial value for r2 +; r3 Initial value for r3 +; r12 Initial value for r12 +; lr Initial value for lr +; pc Initial value for pc +; xPSR Initial value for xPSR +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + MOVS r3, #0x7 ; + BICS r2, r2, r3 ; Align frame for 8-byte alignment + SUBS r2, r2, #68 ; Subtract frame size + IF :DEF: TX_SINGLE_MODE_SECURE + LDR r3, =0xFFFFFFFD ; Build initial LR value for secure mode + ELSE + LDR r3, =0xFFFFFFBC ; Build initial LR value to return to non-secure PSP + ENDIF + STR r3, [r2, #0] ; Save on the stack +; +; /* Actually build the stack frame. */ +; + MOV r3, #0 ; Build initial register value + STR r3, [r2, #4] ; Store initial r8 + STR r3, [r2, #8] ; Store initial r9 + STR r3, [r2, #12] ; Store initial r10 + STR r3, [r2, #16] ; Store initial r11 + STR r3, [r2, #20] ; Store initial r4 + STR r3, [r2, #24] ; Store initial r5 + STR r3, [r2, #28] ; Store initial r6 + STR r3, [r2, #32] ; Store initial r7 +; +; /* Hardware stack follows. */ +; + STR r3, [r2, #36] ; Store initial r0 + STR r3, [r2, #40] ; Store initial r1 + STR r3, [r2, #44] ; Store initial r2 + STR r3, [r2, #48] ; Store initial r3 + STR r3, [r2, #52] ; Store initial r12 + LDR r3, =0xFFFFFFFF ; Poison EXC_RETURN value + STR r3, [r2, #56] ; Store initial lr + STR r1, [r2, #60] ; Store initial pc + LDR r3, =0x01000000 ; Only T-bit need be set + STR r3, [r2, #64] ; Store initial xPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block + BX lr ; Return to caller +;} + ENDFUNC + END diff --git a/ports/cortex_m23/ac5/src/tx_thread_stack_error_handler.c b/ports/cortex_m23/ac5/src/tx_thread_stack_error_handler.c new file mode 100644 index 00000000..ef98240c --- /dev/null +++ b/ports/cortex_m23/ac5/src/tx_thread_stack_error_handler.c @@ -0,0 +1,93 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + +/* Define the global function pointer for stack error handling. If a stack error is + detected and the application has registered a stack error handler, it will be + called via this function pointer. */ + +VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_error_handler Cortex-M23 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes stack errors detected during run-time. */ +/* */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_terminate */ +/* _tx_thread_application_stack_error_handler */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX internal code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) +{ + #ifndef TX_THREAD_NO_TERMINATE_STACK_ERROR + /* Is there a thread? */ + if (thread_ptr) + { + /* Terminate the current thread. */ + _tx_thread_terminate(_tx_thread_current_ptr); + } + #endif + + /* Determine if the application has registered an error handler. */ + if (_tx_thread_application_stack_error_handler != TX_NULL) + { + /* Yes, an error handler is present, simply call the application error handler. */ + (_tx_thread_application_stack_error_handler)(thread_ptr); + } +} diff --git a/ports/cortex_m23/ac5/src/tx_thread_stack_error_notify.c b/ports/cortex_m23/ac5/src/tx_thread_stack_error_notify.c new file mode 100644 index 00000000..ffd78d08 --- /dev/null +++ b/ports/cortex_m23/ac5/src/tx_thread_stack_error_notify.c @@ -0,0 +1,96 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_trace.h" + +extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_error_notify Cortex-M23 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application stack error handler. If */ +/* ThreadX detects a stack error, this application handler is called. */ +/* */ +/* */ +/* INPUT */ +/* */ +/* stack_error_handler Pointer to stack error */ +/* handler, TX_NULL to disable */ +/* */ +/* OUTPUT */ +/* */ +/* status Service return status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr)) +{ + +TX_INTERRUPT_SAVE_AREA + + /* Disable interrupts. */ + TX_DISABLE + + /* Make entry in event log. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_STACK_ERROR_NOTIFY, 0, 0, 0, 0, TX_TRACE_THREAD_EVENTS) + + /* Make entry in event log. */ + TX_EL_THREAD_STACK_ERROR_NOTIFY_INSERT + + /* Setup global thread stack error handler. */ + _tx_thread_application_stack_error_handler = stack_error_handler; + + /* Restore interrupts. */ + TX_RESTORE + + /* Return success to caller. */ + return(TX_SUCCESS); +} diff --git a/ports/cortex_m23/ac5/src/tx_thread_system_return.s b/ports/cortex_m23/ac5/src/tx_thread_system_return.s new file mode 100644 index 00000000..d2a1bf52 --- /dev/null +++ b/ports/cortex_m23/ac5/src/tx_thread_system_return.s @@ -0,0 +1,88 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-M23/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + EXPORT _tx_thread_system_return +_tx_thread_system_return FUNCTION +; +; /* Return to real scheduler via PendSV. Note that this routine is often +; replaced with in-line assembly in tx_port.h to improved performance. */ +; + LDR r0, =0x10000000 ; Load PENDSVSET bit + LDR r1, =0xE000ED04 ; Load ICSR address + STR r0, [r1] ; Set PENDSVBIT in ICSR + MRS r0, IPSR ; Pickup IPSR + CMP r0, #0 ; Is it a thread returning? + BNE _isr_context ; If ISR, skip interrupt enable + MRS r1, PRIMASK ; Thread context returning, pickup PRIMASK + CPSIE i ; Enable interrupts + MSR PRIMASK, r1 ; Restore original interrupt posture +_isr_context + BX lr ; Return to caller + NOP ; To remove added padding warning +;} + ENDFUNC + END diff --git a/ports/cortex_m23/ac5/src/tx_timer_interrupt.s b/ports/cortex_m23/ac5/src/tx_timer_interrupt.s new file mode 100644 index 00000000..73705511 --- /dev/null +++ b/ports/cortex_m23/ac5/src/tx_timer_interrupt.s @@ -0,0 +1,259 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + IMPORT _tx_timer_time_slice + IMPORT _tx_timer_system_clock + IMPORT _tx_timer_current_ptr + IMPORT _tx_timer_list_start + IMPORT _tx_timer_list_end + IMPORT _tx_timer_expired_time_slice + IMPORT _tx_timer_expired + IMPORT _tx_thread_time_slice + IMPORT _tx_timer_expiration_process + IMPORT _tx_thread_preempt_disable + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_execute_ptr +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-M23/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* the expiration functions are called. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + EXPORT _tx_timer_interrupt +_tx_timer_interrupt FUNCTION +; +; /* Upon entry to this routine, it is assumed that the compiler scratch registers are available +; for use. */ +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + MOV32 r1, _tx_timer_system_clock ; Pickup address of system clock + LDR r0, [r1, #0] ; Pickup system clock + ADDS r0, r0, #1 ; Increment system clock + STR r0, [r1, #0] ; Store new system clock +; +; /* Test for time-slice expiration. */ +; if (_tx_timer_time_slice) +; { +; + MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice + LDR r2, [r3, #0] ; Pickup time-slice + CBZ r2, __tx_timer_no_time_slice ; Is it non-active? + ; Yes, skip time-slice processing +; +; /* Decrement the time_slice. */ +; _tx_timer_time_slice--; +; + SUBS r2, r2, #1 ; Decrement the time-slice + STR r2, [r3, #0] ; Store new time-slice value +; +; /* Check for expiration. */ +; if (__tx_timer_time_slice == 0) +; + CBNZ r2, __tx_timer_no_time_slice ; Has it expired? +; +; /* Set the time-slice expired flag. */ +; _tx_timer_expired_time_slice = TX_TRUE; +; + MOV32 r3, _tx_timer_expired_time_slice ; Pickup address of expired flag + MOV r0, #1 ; Build expired value + STR r0, [r3, #0] ; Set time-slice expiration flag +; +; } +; +__tx_timer_no_time_slice +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + MOV32 r1, _tx_timer_current_ptr ; Pickup current timer pointer address + LDR r0, [r1, #0] ; Pickup current timer + LDR r2, [r0, #0] ; Pickup timer list entry + CBZ r2, __tx_timer_no_timer ; Is there anything in the list? + ; No, just increment the timer +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + MOV32 r3, _tx_timer_expired ; Pickup expiration flag address + MOV r2, #1 ; Build expired value + STR r2, [r3, #0] ; Set expired flag + B __tx_timer_done ; Finished timer processing +; +; } +; else +; { +__tx_timer_no_timer +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ADDS r0, r0, #4 ; Move to next timer +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + MOV32 r3, _tx_timer_list_end ; Pickup addr of timer list end + LDR r2, [r3, #0] ; Pickup list end + CMP r0, r2 ; Are we at list end? + BNE __tx_timer_skip_wrap ; No, skip wrap-around logic +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + MOV32 r3, _tx_timer_list_start ; Pickup addr of timer list start + LDR r0, [r3, #0] ; Set current pointer to list start +; +__tx_timer_skip_wrap +; + STR r0, [r1, #0] ; Store new current timer pointer +; } +; +__tx_timer_done +; +; +; /* See if anything has expired. */ +; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +; { +; + MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of expired flag + LDR r2, [r3, #0] ; Pickup time-slice expired flag + CBNZ r2, __tx_something_expired ; Did a time-slice expire? + ; If non-zero, time-slice expired + MOV32 r1, _tx_timer_expired ; Pickup addr of other expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CBZ r0, __tx_timer_nothing_expired ; Did a timer expire? + ; No, nothing expired +; +__tx_something_expired +; +; + STMDB sp!, {r0, lr} ; Save the lr register on the stack + ; and save r0 just to keep 8-byte alignment +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + MOV32 r1, _tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CBZ r0, __tx_timer_dont_activate ; Check for timer expiration + ; If not set, skip timer activation +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + BL _tx_timer_expiration_process ; Call the timer expiration handling routine +; +; } +__tx_timer_dont_activate +; +; /* Did time slice expire? */ +; if (_tx_timer_expired_time_slice) +; { +; + MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r2, [r3, #0] ; Pickup the actual flag + CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set + ; No, skip time-slice processing +; +; /* Time slice interrupted thread. */ +; _tx_thread_time_slice(); + + BL _tx_thread_time_slice ; Call time-slice processing + MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag + LDR r1, [r0] ; Is the preempt disable flag set? + CBNZ r1, __tx_timer_skip_time_slice ; Yes, skip the PendSV logic + MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup the current thread pointer + MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address + LDR r3, [r2] ; Pickup the execute thread pointer + MOV32 r0, 0xE000ED04 ; Build address of control register + MOV32 r2, 0x10000000 ; Build value for PendSV bit + CMP r1, r3 ; Are they the same? + BEQ __tx_timer_skip_time_slice ; If the same, there was no time-slice performed + STR r2, [r0] ; Not the same, issue the PendSV for preemption +__tx_timer_skip_time_slice +; +; } +; +__tx_timer_not_ts_expiration +; + POP {r0, r1} ; Recover lr register (r0 is just there for + MOV lr, r1 ; the 8-byte stack alignment +; +; } +; +__tx_timer_nothing_expired + + DSB ; Complete all memory access + BX lr ; Return to caller +; +;} + ENDFUNC + ALIGN + LTORG + END diff --git a/ports/cortex_m23/ac5/src/txe_thread_secure_stack_allocate.c b/ports/cortex_m23/ac5/src/txe_thread_secure_stack_allocate.c new file mode 100644 index 00000000..35482b6c --- /dev/null +++ b/ports/cortex_m23/ac5/src/txe_thread_secure_stack_allocate.c @@ -0,0 +1,119 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_secure_stack_allocate Cortex-M23 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the secure stack allocate */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* stack_size Size of secure stack to */ +/* allocate */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_secure_stack_allocate Actual stack alloc function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +{ +#if defined(TX_SINGLE_MODE_SECURE) || defined(TX_SINGLE_MODE_NON_SECURE) + return(TX_FEATURE_NOT_ENABLED); +#else +UINT status; + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid thread pointer. */ + if (thread_ptr == TX_NULL) + { + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Now check for invalid thread ID. */ + else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) + { + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Check for interrupt call. */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + /* Is call from an interrupt and not initialization? */ + if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS) + { + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + /* Call actual secure stack allocate function. */ + status = _tx_thread_secure_stack_allocate(thread_ptr, stack_size); + } + + /* Return completion status. */ + return(status); +#endif +} diff --git a/ports/cortex_m23/ac5/src/txe_thread_secure_stack_free.c b/ports/cortex_m23/ac5/src/txe_thread_secure_stack_free.c new file mode 100644 index 00000000..950e8ec0 --- /dev/null +++ b/ports/cortex_m23/ac5/src/txe_thread_secure_stack_free.c @@ -0,0 +1,120 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_secure_stack_free Cortex-M23 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the secure stack free */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_secure_stack_free Actual stack free function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) +{ +#if defined(TX_SINGLE_MODE_SECURE) || defined(TX_SINGLE_MODE_NON_SECURE) + return(TX_FEATURE_NOT_ENABLED); +#else +UINT status; + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid thread pointer. */ + if (thread_ptr == TX_NULL) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Now check for invalid thread ID. */ + else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Check for interrupt call. */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + /* Is call from an interrupt and not initialization? */ + if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS) + { + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + + /* Call actual secure stack allocate function. */ + status = _tx_thread_secure_stack_free(thread_ptr); + } + + /* Return completion status. */ + return(status); +#endif +} diff --git a/ports/cortex_m23/ac6/example_build/ARMCM23_TZ_config.txt b/ports/cortex_m23/ac6/example_build/ARMCM23_TZ_config.txt new file mode 100644 index 00000000..0d31ad76 --- /dev/null +++ b/ports/cortex_m23/ac6/example_build/ARMCM23_TZ_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2] +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +#---------------------------------------------------------------------------------------------- diff --git a/ports/cortex_m23/ac6/example_build/AzureRTOS.uvmpw b/ports/cortex_m23/ac6/example_build/AzureRTOS.uvmpw new file mode 100644 index 00000000..860a1c52 --- /dev/null +++ b/ports/cortex_m23/ac6/example_build/AzureRTOS.uvmpw @@ -0,0 +1,26 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + WorkSpace + + + .\demo_secure_zone\demo_secure_zone.uvprojx + 1 + + + + .\demo_threadx_non-secure_zone\demo_threadx_non-secure_zone.uvprojx + 1 + + + + .\ThreadX_Library.uvprojx + 1 + 1 + + + diff --git a/ports/cortex_m23/ac6/example_build/Debug.ini b/ports/cortex_m23/ac6/example_build/Debug.ini new file mode 100644 index 00000000..2a9dfba0 --- /dev/null +++ b/ports/cortex_m23/ac6/example_build/Debug.ini @@ -0,0 +1,4 @@ +LOAD "..\\demo_threadx_non-secure_zone\\Objects\\demo_threadx_non-secure_zone.axf" incremental +LOAD "..\\demo_secure_zone\\Objects\\demo_secure_zone.axf" incremental +RESET +g, \\demo_secure_zone\main_s\main \ No newline at end of file diff --git a/ports/cortex_m23/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h b/ports/cortex_m23/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h new file mode 100644 index 00000000..476361d7 --- /dev/null +++ b/ports/cortex_m23/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'ThreadX_Library' + * Target: 'ThreadX_Library_Project' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM23_TZ.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/ports/cortex_m23/ac6/example_build/ThreadX_Library.uvoptx b/ports/cortex_m23/ac6/example_build/ThreadX_Library.uvoptx new file mode 100644 index 00000000..d296ddd6 --- /dev/null +++ b/ports/cortex_m23/ac6/example_build/ThreadX_Library.uvoptx @@ -0,0 +1,2564 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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..\..\..\..\common\src\tx_trace_object_register.c + + + tx_trace_object_unregister.c + 1 + ..\..\..\..\common\src\tx_trace_object_unregister.c + + + tx_trace_user_event_insert.c + 1 + ..\..\..\..\common\src\tx_trace_user_event_insert.c + + + txe_block_allocate.c + 1 + ..\..\..\..\common\src\txe_block_allocate.c + + + txe_block_pool_create.c + 1 + ..\..\..\..\common\src\txe_block_pool_create.c + + + txe_block_pool_delete.c + 1 + ..\..\..\..\common\src\txe_block_pool_delete.c + + + txe_block_pool_info_get.c + 1 + ..\..\..\..\common\src\txe_block_pool_info_get.c + + + txe_block_pool_prioritize.c + 1 + ..\..\..\..\common\src\txe_block_pool_prioritize.c + + + txe_block_release.c + 1 + ..\..\..\..\common\src\txe_block_release.c + + + txe_byte_allocate.c + 1 + ..\..\..\..\common\src\txe_byte_allocate.c + + + txe_byte_pool_create.c + 1 + ..\..\..\..\common\src\txe_byte_pool_create.c + + + txe_byte_pool_delete.c + 1 + ..\..\..\..\common\src\txe_byte_pool_delete.c + + + txe_byte_pool_info_get.c + 1 + ..\..\..\..\common\src\txe_byte_pool_info_get.c + + + txe_byte_pool_prioritize.c + 1 + ..\..\..\..\common\src\txe_byte_pool_prioritize.c + + + txe_byte_release.c + 1 + ..\..\..\..\common\src\txe_byte_release.c + + + txe_event_flags_create.c + 1 + ..\..\..\..\common\src\txe_event_flags_create.c + + + txe_event_flags_delete.c + 1 + ..\..\..\..\common\src\txe_event_flags_delete.c + + + txe_event_flags_get.c + 1 + ..\..\..\..\common\src\txe_event_flags_get.c + + + txe_event_flags_info_get.c + 1 + ..\..\..\..\common\src\txe_event_flags_info_get.c + + + txe_event_flags_set.c + 1 + ..\..\..\..\common\src\txe_event_flags_set.c + + + txe_event_flags_set_notify.c + 1 + ..\..\..\..\common\src\txe_event_flags_set_notify.c + + + txe_mutex_create.c + 1 + ..\..\..\..\common\src\txe_mutex_create.c + + + txe_mutex_delete.c + 1 + ..\..\..\..\common\src\txe_mutex_delete.c + + + txe_mutex_get.c + 1 + ..\..\..\..\common\src\txe_mutex_get.c + + + txe_mutex_info_get.c + 1 + ..\..\..\..\common\src\txe_mutex_info_get.c + + + txe_mutex_prioritize.c + 1 + ..\..\..\..\common\src\txe_mutex_prioritize.c + + + txe_mutex_put.c + 1 + ..\..\..\..\common\src\txe_mutex_put.c + + + txe_queue_create.c + 1 + ..\..\..\..\common\src\txe_queue_create.c + + + txe_queue_delete.c + 1 + ..\..\..\..\common\src\txe_queue_delete.c + + + txe_queue_flush.c + 1 + ..\..\..\..\common\src\txe_queue_flush.c + + + txe_queue_front_send.c + 1 + ..\..\..\..\common\src\txe_queue_front_send.c + + + txe_queue_info_get.c + 1 + ..\..\..\..\common\src\txe_queue_info_get.c + + + txe_queue_prioritize.c + 1 + ..\..\..\..\common\src\txe_queue_prioritize.c + + + txe_queue_receive.c + 1 + ..\..\..\..\common\src\txe_queue_receive.c + + + txe_queue_send.c + 1 + ..\..\..\..\common\src\txe_queue_send.c + + + txe_queue_send_notify.c + 1 + ..\..\..\..\common\src\txe_queue_send_notify.c + + + txe_semaphore_ceiling_put.c + 1 + ..\..\..\..\common\src\txe_semaphore_ceiling_put.c + + + txe_semaphore_create.c + 1 + ..\..\..\..\common\src\txe_semaphore_create.c + + + txe_semaphore_delete.c + 1 + ..\..\..\..\common\src\txe_semaphore_delete.c + + + txe_semaphore_get.c + 1 + ..\..\..\..\common\src\txe_semaphore_get.c + + + txe_semaphore_info_get.c + 1 + ..\..\..\..\common\src\txe_semaphore_info_get.c + + + txe_semaphore_prioritize.c + 1 + ..\..\..\..\common\src\txe_semaphore_prioritize.c + + + txe_semaphore_put.c + 1 + ..\..\..\..\common\src\txe_semaphore_put.c + + + txe_semaphore_put_notify.c + 1 + ..\..\..\..\common\src\txe_semaphore_put_notify.c + + + txe_thread_create.c + 1 + ..\..\..\..\common\src\txe_thread_create.c + + + txe_thread_delete.c + 1 + ..\..\..\..\common\src\txe_thread_delete.c + + + txe_thread_entry_exit_notify.c + 1 + ..\..\..\..\common\src\txe_thread_entry_exit_notify.c + + + txe_thread_info_get.c + 1 + ..\..\..\..\common\src\txe_thread_info_get.c + + + txe_thread_preemption_change.c + 1 + ..\..\..\..\common\src\txe_thread_preemption_change.c + + + txe_thread_priority_change.c + 1 + ..\..\..\..\common\src\txe_thread_priority_change.c + + + txe_thread_relinquish.c + 1 + ..\..\..\..\common\src\txe_thread_relinquish.c + + + txe_thread_reset.c + 1 + ..\..\..\..\common\src\txe_thread_reset.c + + + txe_thread_resume.c + 1 + ..\..\..\..\common\src\txe_thread_resume.c + + + txe_thread_suspend.c + 1 + ..\..\..\..\common\src\txe_thread_suspend.c + + + txe_thread_terminate.c + 1 + ..\..\..\..\common\src\txe_thread_terminate.c + + + txe_thread_time_slice_change.c + 1 + ..\..\..\..\common\src\txe_thread_time_slice_change.c + + + txe_thread_wait_abort.c + 1 + ..\..\..\..\common\src\txe_thread_wait_abort.c + + + txe_timer_activate.c + 1 + ..\..\..\..\common\src\txe_timer_activate.c + + + txe_timer_change.c + 1 + ..\..\..\..\common\src\txe_timer_change.c + + + txe_timer_create.c + 1 + ..\..\..\..\common\src\txe_timer_create.c + + + txe_timer_deactivate.c + 1 + ..\..\..\..\common\src\txe_timer_deactivate.c + + + txe_timer_delete.c + 1 + ..\..\..\..\common\src\txe_timer_delete.c + + + txe_timer_info_get.c + 1 + ..\..\..\..\common\src\txe_timer_info_get.c + + + tx_timer_interrupt.S + 2 + ..\src\tx_timer_interrupt.S + + + tx_thread_context_restore.S + 2 + ..\src\tx_thread_context_restore.S + + + tx_thread_context_save.S + 2 + ..\src\tx_thread_context_save.S + + + tx_thread_interrupt_control.S + 2 + ..\src\tx_thread_interrupt_control.S + + + tx_thread_schedule.S + 2 + ..\src\tx_thread_schedule.S + + + tx_thread_stack_build.S + 2 + ..\src\tx_thread_stack_build.S + + + tx_thread_system_return.S + 2 + ..\src\tx_thread_system_return.S + + + tx_trace_buffer_full_notify.c + 1 + ..\..\..\..\common\src\tx_trace_buffer_full_notify.c + + + tx_trace_event_filter.c + 1 + ..\..\..\..\common\src\tx_trace_event_filter.c + + + tx_trace_event_unfilter.c + 1 + ..\..\..\..\common\src\tx_trace_event_unfilter.c + + + tx_thread_interrupt_disable.S + 2 + ..\src\tx_thread_interrupt_disable.S + + + tx_thread_interrupt_restore.S + 2 + ..\src\tx_thread_interrupt_restore.S + + + txe_thread_secure_stack_allocate.c + 1 + ..\src\txe_thread_secure_stack_allocate.c + + + txe_thread_secure_stack_free.c + 1 + ..\src\txe_thread_secure_stack_free.c + + + tx_thread_secure_stack_allocate.S + 2 + ..\src\tx_thread_secure_stack_allocate.S + + + tx_thread_secure_stack_free.S + 2 + ..\src\tx_thread_secure_stack_free.S + + + tx_initialize_low_level.S + 2 + .\tx_initialize_low_level.S + + + tx_thread_stack_error_handler.c + 1 + ..\src\tx_thread_stack_error_handler.c + + + tx_thread_stack_error_notify.c + 1 + ..\src\tx_thread_stack_error_notify.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/ports/cortex_m23/ac6/example_build/demo_secure_zone/Abstract.txt b/ports/cortex_m23/ac6/example_build/demo_secure_zone/Abstract.txt new file mode 100644 index 00000000..0d1d8c52 --- /dev/null +++ b/ports/cortex_m23/ac6/example_build/demo_secure_zone/Abstract.txt @@ -0,0 +1,19 @@ +This ARM Cortex-M33 secure/non-secure example project that +shows the setup of the CMSIS-RTOS2 RTX for TrustZone for +ARMv8-M applications. + +The application uses CMSIS and can be executed on a Fixed +Virtual Platform (FVP) simulation model. The application +demonstrates three RTOS threads. + + +Secure application: + - Setup code and start non-secure application. + +Non-secure application: + - Calls a secure function from non-secure state. + - Calls a secure function that call back to a non-secure function. + +Output: +Variables used in this application can be viewed in the Debugger +Watch window. \ No newline at end of file diff --git a/ports/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/ARMCM23_ac6.sct b/ports/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/ARMCM23_ac6.sct new file mode 100644 index 00000000..abbe02af --- /dev/null +++ b/ports/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/ARMCM23_ac6.sct @@ -0,0 +1,74 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc +; command above MUST be in first line (no comment above!) + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x00000000 +#define __ROM_SIZE 0x00080000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00040000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000200 +#define __HEAP_SIZE 0x00000C00 + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundery definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ +#define __RO_BASE __ROM_BASE +#define __RO_SIZE __ROM_SIZE + +#define __RW_BASE (__RAM_BASE ) +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) + + + +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) +; *(Veneer$$CMSE) ; uncomment for secure applications + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } +} diff --git a/ports/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h b/ports/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h new file mode 100644 index 00000000..a7a090e7 --- /dev/null +++ b/ports/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h @@ -0,0 +1,832 @@ +/**************************************************************************//** + * @file partition_ARMCM23.h + * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM23 + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PARTITION_ARMCM23_H +#define PARTITION_ARMCM23_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 1 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x00200000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x003FFFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x20200000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x203FFFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x40040000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 1 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 1 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 1 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x80-0xFF +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 1 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + + +/* +// Setup behaviour of single SysTick +*/ +#define SCB_ICSR_INIT 0 + +/* +// in a single SysTick implementation, SysTick is +// <0=>Secure +// <1=>Non-Secure +// Value for SCB->ICSR register bit STTNS +// only for single SysTick implementation +*/ +#define SCB_ICSR_STTNS_VAL 0 + +/* +// +*/ + + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// Interrupt 0 <0=> Secure state <1=> Non-Secure state +// Interrupt 1 <0=> Secure state <1=> Non-Secure state +// Interrupt 2 <0=> Secure state <1=> Non-Secure state +// Interrupt 3 <0=> Secure state <1=> Non-Secure state +// Interrupt 4 <0=> Secure state <1=> Non-Secure state +// Interrupt 5 <0=> Secure state <1=> Non-Secure state +// Interrupt 6 <0=> Secure state <1=> Non-Secure state +// Interrupt 7 <0=> Secure state <1=> Non-Secure state +// Interrupt 8 <0=> Secure state <1=> Non-Secure state +// Interrupt 9 <0=> Secure state <1=> Non-Secure state +// Interrupt 10 <0=> Secure state <1=> Non-Secure state +// Interrupt 11 <0=> Secure state <1=> Non-Secure state +// Interrupt 12 <0=> Secure state <1=> Non-Secure state +// Interrupt 13 <0=> Secure state <1=> Non-Secure state +// Interrupt 14 <0=> Secure state <1=> Non-Secure state +// Interrupt 15 <0=> Secure state <1=> Non-Secure state +// Interrupt 16 <0=> Secure state <1=> Non-Secure state +// Interrupt 17 <0=> Secure state <1=> Non-Secure state +// Interrupt 18 <0=> Secure state <1=> Non-Secure state +// Interrupt 19 <0=> Secure state <1=> Non-Secure state +// Interrupt 20 <0=> Secure state <1=> Non-Secure state +// Interrupt 21 <0=> Secure state <1=> Non-Secure state +// Interrupt 22 <0=> Secure state <1=> Non-Secure state +// Interrupt 23 <0=> Secure state <1=> Non-Secure state +// Interrupt 24 <0=> Secure state <1=> Non-Secure state +// Interrupt 25 <0=> Secure state <1=> Non-Secure state +// Interrupt 26 <0=> Secure state <1=> Non-Secure state +// Interrupt 27 <0=> Secure state <1=> Non-Secure state +// Interrupt 28 <0=> Secure state <1=> Non-Secure state +// Interrupt 29 <0=> Secure state <1=> Non-Secure state +// Interrupt 30 <0=> Secure state <1=> Non-Secure state +// Interrupt 31 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// Interrupt 32 <0=> Secure state <1=> Non-Secure state +// Interrupt 33 <0=> Secure state <1=> Non-Secure state +// Interrupt 34 <0=> Secure state <1=> Non-Secure state +// Interrupt 35 <0=> Secure state <1=> Non-Secure state +// Interrupt 36 <0=> Secure state <1=> Non-Secure state +// Interrupt 37 <0=> Secure state <1=> Non-Secure state +// Interrupt 38 <0=> Secure state <1=> Non-Secure state +// Interrupt 39 <0=> Secure state <1=> Non-Secure state +// Interrupt 40 <0=> Secure state <1=> Non-Secure state +// Interrupt 41 <0=> Secure state <1=> Non-Secure state +// Interrupt 42 <0=> Secure state <1=> Non-Secure state +// Interrupt 43 <0=> Secure state <1=> Non-Secure state +// Interrupt 44 <0=> Secure state <1=> Non-Secure state +// Interrupt 45 <0=> Secure state <1=> Non-Secure state +// Interrupt 46 <0=> Secure state <1=> Non-Secure state +// Interrupt 47 <0=> Secure state <1=> Non-Secure state +// Interrupt 48 <0=> Secure state <1=> Non-Secure state +// Interrupt 49 <0=> Secure state <1=> Non-Secure state +// Interrupt 50 <0=> Secure state <1=> Non-Secure state +// Interrupt 51 <0=> Secure state <1=> Non-Secure state +// Interrupt 52 <0=> Secure state <1=> Non-Secure state +// Interrupt 53 <0=> Secure state <1=> Non-Secure state +// Interrupt 54 <0=> Secure state <1=> Non-Secure state +// Interrupt 55 <0=> Secure state <1=> Non-Secure state +// Interrupt 56 <0=> Secure state <1=> Non-Secure state +// Interrupt 57 <0=> Secure state <1=> Non-Secure state +// Interrupt 58 <0=> Secure state <1=> Non-Secure state +// Interrupt 59 <0=> Secure state <1=> Non-Secure state +// Interrupt 60 <0=> Secure state <1=> Non-Secure state +// Interrupt 61 <0=> Secure state <1=> Non-Secure state +// Interrupt 62 <0=> Secure state <1=> Non-Secure state +// Interrupt 63 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 0 + +/* +// Interrupts 64..95 +// Interrupt 64 <0=> Secure state <1=> Non-Secure state +// Interrupt 65 <0=> Secure state <1=> Non-Secure state +// Interrupt 66 <0=> Secure state <1=> Non-Secure state +// Interrupt 67 <0=> Secure state <1=> Non-Secure state +// Interrupt 68 <0=> Secure state <1=> Non-Secure state +// Interrupt 69 <0=> Secure state <1=> Non-Secure state +// Interrupt 70 <0=> Secure state <1=> Non-Secure state +// Interrupt 71 <0=> Secure state <1=> Non-Secure state +// Interrupt 72 <0=> Secure state <1=> Non-Secure state +// Interrupt 73 <0=> Secure state <1=> Non-Secure state +// Interrupt 74 <0=> Secure state <1=> Non-Secure state +// Interrupt 75 <0=> Secure state <1=> Non-Secure state +// Interrupt 76 <0=> Secure state <1=> Non-Secure state +// Interrupt 77 <0=> Secure state <1=> Non-Secure state +// Interrupt 78 <0=> Secure state <1=> Non-Secure state +// Interrupt 79 <0=> Secure state <1=> Non-Secure state +// Interrupt 80 <0=> Secure state <1=> Non-Secure state +// Interrupt 81 <0=> Secure state <1=> Non-Secure state +// Interrupt 82 <0=> Secure state <1=> Non-Secure state +// Interrupt 83 <0=> Secure state <1=> Non-Secure state +// Interrupt 84 <0=> Secure state <1=> Non-Secure state +// Interrupt 85 <0=> Secure state <1=> Non-Secure state +// Interrupt 86 <0=> Secure state <1=> Non-Secure state +// Interrupt 87 <0=> Secure state <1=> Non-Secure state +// Interrupt 88 <0=> Secure state <1=> Non-Secure state +// Interrupt 89 <0=> Secure state <1=> Non-Secure state +// Interrupt 90 <0=> Secure state <1=> Non-Secure state +// Interrupt 91 <0=> Secure state <1=> Non-Secure state +// Interrupt 92 <0=> Secure state <1=> Non-Secure state +// Interrupt 93 <0=> Secure state <1=> Non-Secure state +// Interrupt 94 <0=> Secure state <1=> Non-Secure state +// Interrupt 95 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 0 + +/* +// Interrupts 96..127 +// Interrupt 96 <0=> Secure state <1=> Non-Secure state +// Interrupt 97 <0=> Secure state <1=> Non-Secure state +// Interrupt 98 <0=> Secure state <1=> Non-Secure state +// Interrupt 99 <0=> Secure state <1=> Non-Secure state +// Interrupt 100 <0=> Secure state <1=> Non-Secure state +// Interrupt 101 <0=> Secure state <1=> Non-Secure state +// Interrupt 102 <0=> Secure state <1=> Non-Secure state +// Interrupt 103 <0=> Secure state <1=> Non-Secure state +// Interrupt 104 <0=> Secure state <1=> Non-Secure state +// Interrupt 105 <0=> Secure state <1=> Non-Secure state +// Interrupt 106 <0=> Secure state <1=> Non-Secure state +// Interrupt 107 <0=> Secure state <1=> Non-Secure state +// Interrupt 108 <0=> Secure state <1=> Non-Secure state +// Interrupt 109 <0=> Secure state <1=> Non-Secure state +// Interrupt 110 <0=> Secure state <1=> Non-Secure state +// Interrupt 111 <0=> Secure state <1=> Non-Secure state +// Interrupt 112 <0=> Secure state <1=> Non-Secure state +// Interrupt 113 <0=> Secure state <1=> Non-Secure state +// Interrupt 114 <0=> Secure state <1=> Non-Secure state +// Interrupt 115 <0=> Secure state <1=> Non-Secure state +// Interrupt 116 <0=> Secure state <1=> Non-Secure state +// Interrupt 117 <0=> Secure state <1=> Non-Secure state +// Interrupt 118 <0=> Secure state <1=> Non-Secure state +// Interrupt 119 <0=> Secure state <1=> Non-Secure state +// Interrupt 120 <0=> Secure state <1=> Non-Secure state +// Interrupt 121 <0=> Secure state <1=> Non-Secure state +// Interrupt 122 <0=> Secure state <1=> Non-Secure state +// Interrupt 123 <0=> Secure state <1=> Non-Secure state +// Interrupt 124 <0=> Secure state <1=> Non-Secure state +// Interrupt 125 <0=> Secure state <1=> Non-Secure state +// Interrupt 126 <0=> Secure state <1=> Non-Secure state +// Interrupt 127 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 128..159) +*/ +#define NVIC_INIT_ITNS4 0 + +/* +// Interrupts 128..159 +// Interrupt 128 <0=> Secure state <1=> Non-Secure state +// Interrupt 129 <0=> Secure state <1=> Non-Secure state +// Interrupt 130 <0=> Secure state <1=> Non-Secure state +// Interrupt 131 <0=> Secure state <1=> Non-Secure state +// Interrupt 132 <0=> Secure state <1=> Non-Secure state +// Interrupt 133 <0=> Secure state <1=> Non-Secure state +// Interrupt 134 <0=> Secure state <1=> Non-Secure state +// Interrupt 135 <0=> Secure state <1=> Non-Secure state +// Interrupt 136 <0=> Secure state <1=> Non-Secure state +// Interrupt 137 <0=> Secure state <1=> Non-Secure state +// Interrupt 138 <0=> Secure state <1=> Non-Secure state +// Interrupt 139 <0=> Secure state <1=> Non-Secure state +// Interrupt 140 <0=> Secure state <1=> Non-Secure state +// Interrupt 141 <0=> Secure state <1=> Non-Secure state +// Interrupt 142 <0=> Secure state <1=> Non-Secure state +// Interrupt 143 <0=> Secure state <1=> Non-Secure state +// Interrupt 144 <0=> Secure state <1=> Non-Secure state +// Interrupt 145 <0=> Secure state <1=> Non-Secure state +// Interrupt 146 <0=> Secure state <1=> Non-Secure state +// Interrupt 147 <0=> Secure state <1=> Non-Secure state +// Interrupt 148 <0=> Secure state <1=> Non-Secure state +// Interrupt 149 <0=> Secure state <1=> Non-Secure state +// Interrupt 150 <0=> Secure state <1=> Non-Secure state +// Interrupt 151 <0=> Secure state <1=> Non-Secure state +// Interrupt 152 <0=> Secure state <1=> Non-Secure state +// Interrupt 153 <0=> Secure state <1=> Non-Secure state +// Interrupt 154 <0=> Secure state <1=> Non-Secure state +// Interrupt 155 <0=> Secure state <1=> Non-Secure state +// Interrupt 156 <0=> Secure state <1=> Non-Secure state +// Interrupt 157 <0=> Secure state <1=> Non-Secure state +// Interrupt 158 <0=> Secure state <1=> Non-Secure state +// Interrupt 159 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 5 (Interrupts 160..191) +*/ +#define NVIC_INIT_ITNS5 0 + +/* +// Interrupts 160..191 +// Interrupt 160 <0=> Secure state <1=> Non-Secure state +// Interrupt 161 <0=> Secure state <1=> Non-Secure state +// Interrupt 162 <0=> Secure state <1=> Non-Secure state +// Interrupt 163 <0=> Secure state <1=> Non-Secure state +// Interrupt 164 <0=> Secure state <1=> Non-Secure state +// Interrupt 165 <0=> Secure state <1=> Non-Secure state +// Interrupt 166 <0=> Secure state <1=> Non-Secure state +// Interrupt 167 <0=> Secure state <1=> Non-Secure state +// Interrupt 168 <0=> Secure state <1=> Non-Secure state +// Interrupt 169 <0=> Secure state <1=> Non-Secure state +// Interrupt 170 <0=> Secure state <1=> Non-Secure state +// Interrupt 171 <0=> Secure state <1=> Non-Secure state +// Interrupt 172 <0=> Secure state <1=> Non-Secure state +// Interrupt 173 <0=> Secure state <1=> Non-Secure state +// Interrupt 174 <0=> Secure state <1=> Non-Secure state +// Interrupt 175 <0=> Secure state <1=> Non-Secure state +// Interrupt 176 <0=> Secure state <1=> Non-Secure state +// Interrupt 177 <0=> Secure state <1=> Non-Secure state +// Interrupt 178 <0=> Secure state <1=> Non-Secure state +// Interrupt 179 <0=> Secure state <1=> Non-Secure state +// Interrupt 180 <0=> Secure state <1=> Non-Secure state +// Interrupt 181 <0=> Secure state <1=> Non-Secure state +// Interrupt 182 <0=> Secure state <1=> Non-Secure state +// Interrupt 183 <0=> Secure state <1=> Non-Secure state +// Interrupt 184 <0=> Secure state <1=> Non-Secure state +// Interrupt 185 <0=> Secure state <1=> Non-Secure state +// Interrupt 186 <0=> Secure state <1=> Non-Secure state +// Interrupt 187 <0=> Secure state <1=> Non-Secure state +// Interrupt 188 <0=> Secure state <1=> Non-Secure state +// Interrupt 189 <0=> Secure state <1=> Non-Secure state +// Interrupt 190 <0=> Secure state <1=> Non-Secure state +// Interrupt 191 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS5_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 6 (Interrupts 192..223) +*/ +#define NVIC_INIT_ITNS6 0 + +/* +// Interrupts 192..223 +// Interrupt 192 <0=> Secure state <1=> Non-Secure state +// Interrupt 193 <0=> Secure state <1=> Non-Secure state +// Interrupt 194 <0=> Secure state <1=> Non-Secure state +// Interrupt 195 <0=> Secure state <1=> Non-Secure state +// Interrupt 196 <0=> Secure state <1=> Non-Secure state +// Interrupt 197 <0=> Secure state <1=> Non-Secure state +// Interrupt 198 <0=> Secure state <1=> Non-Secure state +// Interrupt 199 <0=> Secure state <1=> Non-Secure state +// Interrupt 200 <0=> Secure state <1=> Non-Secure state +// Interrupt 201 <0=> Secure state <1=> Non-Secure state +// Interrupt 202 <0=> Secure state <1=> Non-Secure state +// Interrupt 203 <0=> Secure state <1=> Non-Secure state +// Interrupt 204 <0=> Secure state <1=> Non-Secure state +// Interrupt 205 <0=> Secure state <1=> Non-Secure state +// Interrupt 206 <0=> Secure state <1=> Non-Secure state +// Interrupt 207 <0=> Secure state <1=> Non-Secure state +// Interrupt 208 <0=> Secure state <1=> Non-Secure state +// Interrupt 209 <0=> Secure state <1=> Non-Secure state +// Interrupt 210 <0=> Secure state <1=> Non-Secure state +// Interrupt 211 <0=> Secure state <1=> Non-Secure state +// Interrupt 212 <0=> Secure state <1=> Non-Secure state +// Interrupt 213 <0=> Secure state <1=> Non-Secure state +// Interrupt 214 <0=> Secure state <1=> Non-Secure state +// Interrupt 215 <0=> Secure state <1=> Non-Secure state +// Interrupt 216 <0=> Secure state <1=> Non-Secure state +// Interrupt 217 <0=> Secure state <1=> Non-Secure state +// Interrupt 218 <0=> Secure state <1=> Non-Secure state +// Interrupt 219 <0=> Secure state <1=> Non-Secure state +// Interrupt 220 <0=> Secure state <1=> Non-Secure state +// Interrupt 221 <0=> Secure state <1=> Non-Secure state +// Interrupt 222 <0=> Secure state <1=> Non-Secure state +// Interrupt 223 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS6_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 7 (Interrupts 224..255) +*/ +#define NVIC_INIT_ITNS7 0 + +/* +// Interrupts 224..255 +// Interrupt 224 <0=> Secure state <1=> Non-Secure state +// Interrupt 225 <0=> Secure state <1=> Non-Secure state +// Interrupt 226 <0=> Secure state <1=> Non-Secure state +// Interrupt 227 <0=> Secure state <1=> Non-Secure state +// Interrupt 228 <0=> Secure state <1=> Non-Secure state +// Interrupt 229 <0=> Secure state <1=> Non-Secure state +// Interrupt 230 <0=> Secure state <1=> Non-Secure state +// Interrupt 231 <0=> Secure state <1=> Non-Secure state +// Interrupt 232 <0=> Secure state <1=> Non-Secure state +// Interrupt 233 <0=> Secure state <1=> Non-Secure state +// Interrupt 234 <0=> Secure state <1=> Non-Secure state +// Interrupt 235 <0=> Secure state <1=> Non-Secure state +// Interrupt 236 <0=> Secure state <1=> Non-Secure state +// Interrupt 237 <0=> Secure state <1=> Non-Secure state +// Interrupt 238 <0=> Secure state <1=> Non-Secure state +// Interrupt 239 <0=> Secure state <1=> Non-Secure state +// Interrupt 240 <0=> Secure state <1=> Non-Secure state +// Interrupt 241 <0=> Secure state <1=> Non-Secure state +// Interrupt 242 <0=> Secure state <1=> Non-Secure state +// Interrupt 243 <0=> Secure state <1=> Non-Secure state +// Interrupt 244 <0=> Secure state <1=> Non-Secure state +// Interrupt 245 <0=> Secure state <1=> Non-Secure state +// Interrupt 246 <0=> Secure state <1=> Non-Secure state +// Interrupt 247 <0=> Secure state <1=> Non-Secure state +// Interrupt 248 <0=> Secure state <1=> Non-Secure state +// Interrupt 249 <0=> Secure state <1=> Non-Secure state +// Interrupt 250 <0=> Secure state <1=> Non-Secure state +// Interrupt 251 <0=> Secure state <1=> Non-Secure state +// Interrupt 252 <0=> Secure state <1=> Non-Secure state +// Interrupt 253 <0=> Secure state <1=> Non-Secure state +// Interrupt 254 <0=> Secure state <1=> Non-Secure state +// Interrupt 255 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS7_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + + + +/* + max 128 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) + SCB->ICSR = (SCB->ICSR & ~(SCB_ICSR_STTNS_Msk )) | + ((SCB_ICSR_STTNS_VAL << SCB_ICSR_STTNS_Pos) & SCB_ICSR_STTNS_Msk); + #endif /* defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) */ + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + + #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) + NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; + #endif + + #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) + NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; + #endif + + #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) + NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; + #endif + + /* repeat this for all possible ITNS elements */ + +} + +#endif /* PARTITION_ARMCM23_H */ diff --git a/ports/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c b/ports/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c new file mode 100644 index 00000000..30dc1dfd --- /dev/null +++ b/ports/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c @@ -0,0 +1,137 @@ +/****************************************************************************** + * @file startup_ARMCM23.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M23 Device + * @version V2.0.0 + * @date 04. June 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM23) + #include "ARMCM23.h" +#elif defined (ARMCM23_TZ) + #include "ARMCM23_TZ.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler Function Prototype + *----------------------------------------------------------------------------*/ +typedef void( *pFunc )( void ); + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const pFunc __VECTOR_TABLE[240]; + const pFunc __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/ports/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/system_ARMCM23.c b/ports/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/system_ARMCM23.c new file mode 100644 index 00000000..1052b383 --- /dev/null +++ b/ports/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/system_ARMCM23.c @@ -0,0 +1,98 @@ +/**************************************************************************//** + * @file system_ARMCM23.c + * @brief CMSIS Device System Source File for + * ARMCM23 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM23) + #include "ARMCM23.h" +#elif defined (ARMCM23_TZ) + #include "ARMCM23_TZ.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM23.h" + #endif +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __VECTOR_TABLE; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__VECTOR_TABLE; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; + + *(uint32_t *)0xE000ED24 = 0x000F0000; /* S: enable secure, usage, bus, mem faults */ + *(uint32_t *)0xE002ED24 = 0x000F0000; /* NS: enable secure, usage, bus, mem faults */ +} + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +void HardFault_Handler(void) +{ + while(1); + +} + +void UsageFault_Handler(void) +{ + while(1); +} +#endif diff --git a/ports/cortex_m23/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h b/ports/cortex_m23/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h new file mode 100644 index 00000000..a37b412e --- /dev/null +++ b/ports/cortex_m23/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'demo_secure_zone' + * Target: 'FVP Simulation Model' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM23_TZ.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/ports/cortex_m23/ac6/example_build/demo_secure_zone/demo_secure_zone.uvoptx b/ports/cortex_m23/ac6/example_build/demo_secure_zone/demo_secure_zone.uvoptx new file mode 100644 index 00000000..3933a171 --- /dev/null +++ b/ports/cortex_m23/ac6/example_build/demo_secure_zone/demo_secure_zone.uvoptx @@ -0,0 +1,328 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + FVP Simulation Model + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 15 + + + + + + + + + + ..\Debug.ini + BIN\DbgFMv8M.DLL + + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FC1000 -FD20000000 + + + 0 + DbgFMv8M + -I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M23_MDK.exe" -MF"..\ARMCM23_TZ_config.txt" -PF -MA + + + 0 + DLGTARM + (6010=1818,430,2295,1026,0)(6018=2033,530,2222,879,0)(6019=-1,-1,-1,-1,0)(6008=1845,239,2139,424,0)(6009=-1,-1,-1,-1,0)(6014=1836,-490,2094,241,0)(6015=-1,-1,-1,-1,0)(6003=-1,-1,-1,-1,0)(6000=75,104,528,436,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0) + + + + + + 0 + 1 + _tx_thread_current_ptr + + + 1 + 1 + thread_0_counter + + + 2 + 1 + thread_1_counter + + + 3 + 1 + thread_2_counter + + + 4 + 1 + thread_3_counter + + + 5 + 1 + thread_4_counter + + + 6 + 1 + thread_5_counter + + + 7 + 1 + thread_6_counter + + + 8 + 1 + thread_7_counter + + + 9 + 1 + _tx_timer_system_clock + + + + + 1 + 2 + 0 + 0 + + + + + 2 + 2 + 0xE000ED28 + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Secure Code + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\src\tx_thread_secure_stack.c + tx_thread_secure_stack.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + .\main_s.c + main_s.c + 0 + 0 + + + + + Interface + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + .\interface.c + interface.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 0 + 0 + 0 + 1 + + + diff --git a/ports/cortex_m23/ac6/example_build/demo_secure_zone/demo_secure_zone.uvprojx b/ports/cortex_m23/ac6/example_build/demo_secure_zone/demo_secure_zone.uvprojx new file mode 100644 index 00000000..9b49855d --- /dev/null +++ b/ports/cortex_m23/ac6/example_build/demo_secure_zone/demo_secure_zone.uvprojx @@ -0,0 +1,521 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + FVP Simulation Model + 0x4 + ARM-ADS + 6140000::V6.14::ARMCLANG + 1 + + + ARMCM23_TZ + ARM + ARM.CMSIS.5.7.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("Cortex-M23") TZ CLOCK(12000000) ESEL ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM23_TZ$Device\ARM\ARMCM23\Include\ARMCM23_TZ.h + + + + + + + + + + + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + demo_secure_zone + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + -MPU + TCM.DLL + -pCM23 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 0 + 4101 + + 1 + BIN\UL2V8M.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M23" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 8 + 1 + 1 + 0 + 1 + 4 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x200000 + + + 1 + 0x200000 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x20200000 + 0x20000 + + + + + + 1 + 7 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 0 + 0 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\..\common\inc, ..\..\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\RTE\Device\ARMCM23_TZ\ARMCM23_ac6.sct + + + + + + + + + + + Secure Code + + + tx_thread_secure_stack.c + 1 + ..\..\src\tx_thread_secure_stack.c + + + main_s.c + 1 + .\main_s.c + + + + + Interface + + + interface.c + 1 + .\interface.c + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + RTE\Device\ARMCM23_TZ\ARMCM23_ac6.sct + + + + + + + + RTE\Device\ARMCM23_TZ\partition_ARMCM23.h + + + + + + + + RTE\Device\ARMCM23_TZ\startup_ARMCM23.c + + + + + + + + RTE\Device\ARMCM23_TZ\system_ARMCM23.c + + + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\ARMCM33_ac6.sct + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\partition_ARMCM33.h + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.c + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.s + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\system_ARMCM33.c + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/ports/cortex_m23/ac6/example_build/demo_secure_zone/interface.c b/ports/cortex_m23/ac6/example_build/demo_secure_zone/interface.c new file mode 100644 index 00000000..4e6e8eee --- /dev/null +++ b/ports/cortex_m23/ac6/example_build/demo_secure_zone/interface.c @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * interface.c Secure/non-secure callable application code + * + * Version 1.0 + * Initial Release + *---------------------------------------------------------------------------*/ + + +#include // CMSE definitions +#include "interface.h" // Header file with secure interface API + +/* typedef for non-secure callback functions */ +typedef funcptr funcptr_NS __attribute__((cmse_nonsecure_call)); + +/* Non-secure callable (entry) function */ +int func1(int x) __attribute__((cmse_nonsecure_entry)) { + return x+3; +} + +/* Non-secure callable (entry) function, calling a non-secure callback function */ +int func2(funcptr callback, int x) __attribute__((cmse_nonsecure_entry)) { + funcptr_NS callback_NS; // non-secure callback function pointer + int y; + + /* return function pointer with cleared LSB */ + callback_NS = (funcptr_NS)cmse_nsfptr_create(callback); + + y = callback_NS (x+1); + + return (y+2); +} diff --git a/ports/cortex_m23/ac6/example_build/demo_secure_zone/interface.h b/ports/cortex_m23/ac6/example_build/demo_secure_zone/interface.h new file mode 100644 index 00000000..8215d5a3 --- /dev/null +++ b/ports/cortex_m23/ac6/example_build/demo_secure_zone/interface.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * interface.h API definition for the non-secure state + * + * Version 1.0 + * Initial Release + *---------------------------------------------------------------------------*/ + +/* Function pointer declaration */ +typedef int (*funcptr)(int); + +/* Non-secure callable functions */ +extern int func1(int x); +extern int func2(funcptr callback, int x); diff --git a/ports/cortex_m23/ac6/example_build/demo_secure_zone/main_ns.c b/ports/cortex_m23/ac6/example_build/demo_secure_zone/main_ns.c new file mode 100644 index 00000000..5d16e1bb --- /dev/null +++ b/ports/cortex_m23/ac6/example_build/demo_secure_zone/main_ns.c @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * main_ns.c Non-secure main function - RTOS demo + * + * Version 1.0 + * Initial Release + *---------------------------------------------------------------------------*/ + +#include "interface.h" // Interface API +//#include "cmsis_os2.h" // ARM::CMSIS:RTOS2:Keil RTX5 + +//static osStatus_t Status; + +//static osThreadId_t ThreadA_Id; +//static osThreadId_t ThreadB_Id; +//static osThreadId_t ThreadC_Id; + +void ThreadA (void *argument); +void ThreadB (void *argument); +void ThreadC (void *argument); + + +extern volatile int counterA; +extern volatile int counterB; +extern volatile int counterC; + +volatile int counterA; +volatile int counterB; +volatile int counterC; + +/* +static int callbackA (int val) { + return (val); +} + +__attribute__((noreturn)) +void ThreadA (void *argument) { + (void)argument; + + for (;;) { + counterA = func1 (counterA); + counterA = func2 (callbackA, counterA); + osDelay(2U); + } +} + +static int callbackB (int val) { + uint32_t flags; + + flags = osThreadFlagsWait (1U, osFlagsWaitAny, osWaitForever); + if (flags == 1U) { + return (val+1); + } else { + return (0); + } +} + + +__attribute__((noreturn)) +void ThreadB (void *argument) { + (void)argument; + + for (;;) { + counterB = func1 (counterB); + counterB = func2 (callbackB, counterB); + } +} + +__attribute__((noreturn)) +void ThreadC (void *argument) { + (void)argument; + + for (;;) { + counterC = counterC + 1; + if ((counterC % 0x10) == 0) { + osThreadFlagsSet (ThreadB_Id, 1); + } + osDelay(1U); + } +} + +static const osThreadAttr_t ThreadAttr = { + .tz_module = 1U, // indicate calls to secure mode +}; +*/ +#if 1 +int main (void) { + + for (;;); +} +#endif diff --git a/ports/cortex_m23/ac6/example_build/demo_secure_zone/main_s.c b/ports/cortex_m23/ac6/example_build/demo_secure_zone/main_s.c new file mode 100644 index 00000000..2c667821 --- /dev/null +++ b/ports/cortex_m23/ac6/example_build/demo_secure_zone/main_s.c @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 15. October 2016 + * $Revision: 1.1.0 + * + * Project: TrustZone for ARMv8-M + * Title: Code template for secure main function + * + *---------------------------------------------------------------------------*/ + +/* Use CMSE intrinsics */ +#include + #include +#include "RTE_Components.h" +#include CMSIS_device_header + +/* TZ_START_NS: Start address of non-secure application */ +#ifndef TZ_START_NS +#define TZ_START_NS (0x200000U) +#endif + +/* typedef for non-secure callback functions */ +typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call)); + +/* Secure main() */ +int main(void) { + funcptr_void NonSecure_ResetHandler; + + /* Add user setup code for secure part here*/ + + /* Set non-secure main stack (MSP_NS) */ + __TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS))); + + /* Get non-secure reset handler */ + NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U))); + + /* Start non-secure state software application */ + NonSecure_ResetHandler(); + + /* Non-secure software does not return, this code is not executed */ + while (1) { + __NOP(); + } +} diff --git a/ports/cortex_m23/ac6/example_build/demo_secure_zone/tx_secure_interface.h b/ports/cortex_m23/ac6/example_build/demo_secure_zone/tx_secure_interface.h new file mode 100644 index 00000000..976f32be --- /dev/null +++ b/ports/cortex_m23/ac6/example_build/demo_secure_zone/tx_secure_interface.h @@ -0,0 +1,60 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* tx_secure_interface.h Cortex-M23 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the ThreadX secure thread stack components, */ +/* including data types and external references. */ +/* It is assumed that tx_api.h and tx_port.h have already been */ +/* included. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_SECURE_INTERFACE_H +#define TX_SECURE_INTERFACE_H + +/* Define internal secure thread stack function prototypes. */ + +extern void _tx_thread_secure_stack_initialize(void); +extern UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size); +extern UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr); +extern void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr); +extern void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr); + +#endif diff --git a/ports/cortex_m23/ac6/example_build/demo_secure_zone/tz_context.c b/ports/cortex_m23/ac6/example_build/demo_secure_zone/tz_context.c new file mode 100644 index 00000000..f3152890 --- /dev/null +++ b/ports/cortex_m23/ac6/example_build/demo_secure_zone/tz_context.c @@ -0,0 +1,203 @@ +/* + * Copyright (c) 2015-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------------- + * + * $Date: 15. October 2016 + * $Revision: 1.1.0 + * + * Project: TrustZone for ARMv8-M + * Title: Context Management for ARMv8-M TrustZone - Sample implementation + * + *---------------------------------------------------------------------------*/ + +#include "RTE_Components.h" +#include CMSIS_device_header +#include "tz_context.h" + +/// Number of process slots (threads may call secure library code) +#ifndef TZ_PROCESS_STACK_SLOTS +#define TZ_PROCESS_STACK_SLOTS 8U +#endif + +/// Stack size of the secure library code +#ifndef TZ_PROCESS_STACK_SIZE +#define TZ_PROCESS_STACK_SIZE 256U +#endif + +typedef struct { + uint32_t sp_top; // stack space top + uint32_t sp_limit; // stack space limit + uint32_t sp; // current stack pointer +} stack_info_t; + +static stack_info_t ProcessStackInfo [TZ_PROCESS_STACK_SLOTS]; +static uint64_t ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/8U]; +static uint32_t ProcessStackFreeSlot = 0xFFFFFFFFU; + + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_InitContextSystem_S (void) { + uint32_t n; + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) { + ProcessStackInfo[n].sp = 0U; + ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n]; + ProcessStackInfo[n].sp_top = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE; + *((uint32_t *)ProcessStackMemory[n]) = n + 1U; + } + *((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU; + + ProcessStackFreeSlot = 0U; + + // Default process stack pointer and stack limit + __set_PSPLIM((uint32_t)ProcessStackMemory); + __set_PSP ((uint32_t)ProcessStackMemory); + + // Privileged Thread Mode using PSP + __set_CONTROL(0x02U); + + return 1U; // Success +} + + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +__attribute__((cmse_nonsecure_entry)) +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) { + uint32_t slot; + + (void)module; // Ignore (fixed Stack size) + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + if (ProcessStackFreeSlot == 0xFFFFFFFFU) { + return 0U; // No slot available + } + + slot = ProcessStackFreeSlot; + ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]); + + ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top; + + return (slot + 1U); +} + + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) { + uint32_t slot; + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + ProcessStackInfo[slot].sp = 0U; + + *((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot; + ProcessStackFreeSlot = slot; + + return 1U; // Success +} + + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id) { + uint32_t slot; + + if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { + return 0U; // Thread Mode or using Main Stack for threads + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + + // Setup process stack pointer and stack limit + __set_PSPLIM(ProcessStackInfo[slot].sp_limit); + __set_PSP (ProcessStackInfo[slot].sp); + + return 1U; // Success +} + + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id) { + uint32_t slot; + uint32_t sp; + + if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { + return 0U; // Thread Mode or using Main Stack for threads + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + + sp = __get_PSP(); + if ((sp < ProcessStackInfo[slot].sp_limit) || + (sp > ProcessStackInfo[slot].sp_top)) { + return 0U; // SP out of range + } + ProcessStackInfo[slot].sp = sp; + + // Default process stack pointer and stack limit + __set_PSPLIM((uint32_t)ProcessStackMemory); + __set_PSP ((uint32_t)ProcessStackMemory); + + return 1U; // Success +} diff --git a/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c new file mode 100644 index 00000000..e4871014 --- /dev/null +++ b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + + for (;;) {} +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; + + switch (code) { + case osRtxErrorStackUnderflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +} diff --git a/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h new file mode 100644 index 00000000..3021efbc --- /dev/null +++ b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,578 @@ +/* + * Copyright (c) 2013-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.5.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 4096 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 4096 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 0 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 1 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 0 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 256 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 256 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 256 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 256 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch. +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 256 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 256 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial recording level applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Recording levels for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Recording level for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_LEVEL +#define OS_EVR_MEMORY_LEVEL 0x01U +#endif + +// Kernel +// Recording level for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_LEVEL +#define OS_EVR_KERNEL_LEVEL 0x01U +#endif + +// Thread +// Recording level for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_LEVEL +#define OS_EVR_THREAD_LEVEL 0x05U +#endif + +// Generic Wait +// Recording level for Generic Wait events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_WAIT_LEVEL +#define OS_EVR_WAIT_LEVEL 0x01U +#endif + +// Thread Flags +// Recording level for Thread Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THFLAGS_LEVEL +#define OS_EVR_THFLAGS_LEVEL 0x01U +#endif + +// Event Flags +// Recording level for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_LEVEL +#define OS_EVR_EVFLAGS_LEVEL 0x01U +#endif + +// Timer +// Recording level for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_LEVEL +#define OS_EVR_TIMER_LEVEL 0x01U +#endif + +// Mutex +// Recording level for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_LEVEL +#define OS_EVR_MUTEX_LEVEL 0x01U +#endif + +// Semaphore +// Recording level for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_LEVEL +#define OS_EVR_SEMAPHORE_LEVEL 0x01U +#endif + +// Memory Pool +// Recording level for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_LEVEL +#define OS_EVR_MEMPOOL_LEVEL 0x01U +#endif + +// Message Queue +// Recording level for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_LEVEL +#define OS_EVR_MSGQUEUE_LEVEL 0x01U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Generic Wait +// Enables Generic Wait event generation. +#ifndef OS_EVR_WAIT +#define OS_EVR_WAIT 1 +#endif + +// Thread Flags +// Enables Thread Flags event generation. +#ifndef OS_EVR_THFLAGS +#define OS_EVR_THFLAGS 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#define OS_THREAD_LIBSPACE_NUM 4 +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/ARMCM23_ac6.sct b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/ARMCM23_ac6.sct new file mode 100644 index 00000000..7b796b29 --- /dev/null +++ b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/ARMCM23_ac6.sct @@ -0,0 +1,74 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc +; command above MUST be in first line (no comment above!) + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x00200000 +#define __ROM_SIZE 0x00080000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x20200000 +#define __RAM_SIZE 0x00040000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000200 +#define __HEAP_SIZE 0x00000C00 + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundery definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ +#define __RO_BASE __ROM_BASE +#define __RO_SIZE __ROM_SIZE + +#define __RW_BASE (__RAM_BASE ) +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) + + + +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) +; *(Veneer$$CMSE) ; uncomment for secure applications + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } +} diff --git a/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h new file mode 100644 index 00000000..a7a090e7 --- /dev/null +++ b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h @@ -0,0 +1,832 @@ +/**************************************************************************//** + * @file partition_ARMCM23.h + * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM23 + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PARTITION_ARMCM23_H +#define PARTITION_ARMCM23_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 1 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x00200000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x003FFFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x20200000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x203FFFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x40040000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 1 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 1 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 1 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x80-0xFF +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 1 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + + +/* +// Setup behaviour of single SysTick +*/ +#define SCB_ICSR_INIT 0 + +/* +// in a single SysTick implementation, SysTick is +// <0=>Secure +// <1=>Non-Secure +// Value for SCB->ICSR register bit STTNS +// only for single SysTick implementation +*/ +#define SCB_ICSR_STTNS_VAL 0 + +/* +// +*/ + + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// Interrupt 0 <0=> Secure state <1=> Non-Secure state +// Interrupt 1 <0=> Secure state <1=> Non-Secure state +// Interrupt 2 <0=> Secure state <1=> Non-Secure state +// Interrupt 3 <0=> Secure state <1=> Non-Secure state +// Interrupt 4 <0=> Secure state <1=> Non-Secure state +// Interrupt 5 <0=> Secure state <1=> Non-Secure state +// Interrupt 6 <0=> Secure state <1=> Non-Secure state +// Interrupt 7 <0=> Secure state <1=> Non-Secure state +// Interrupt 8 <0=> Secure state <1=> Non-Secure state +// Interrupt 9 <0=> Secure state <1=> Non-Secure state +// Interrupt 10 <0=> Secure state <1=> Non-Secure state +// Interrupt 11 <0=> Secure state <1=> Non-Secure state +// Interrupt 12 <0=> Secure state <1=> Non-Secure state +// Interrupt 13 <0=> Secure state <1=> Non-Secure state +// Interrupt 14 <0=> Secure state <1=> Non-Secure state +// Interrupt 15 <0=> Secure state <1=> Non-Secure state +// Interrupt 16 <0=> Secure state <1=> Non-Secure state +// Interrupt 17 <0=> Secure state <1=> Non-Secure state +// Interrupt 18 <0=> Secure state <1=> Non-Secure state +// Interrupt 19 <0=> Secure state <1=> Non-Secure state +// Interrupt 20 <0=> Secure state <1=> Non-Secure state +// Interrupt 21 <0=> Secure state <1=> Non-Secure state +// Interrupt 22 <0=> Secure state <1=> Non-Secure state +// Interrupt 23 <0=> Secure state <1=> Non-Secure state +// Interrupt 24 <0=> Secure state <1=> Non-Secure state +// Interrupt 25 <0=> Secure state <1=> Non-Secure state +// Interrupt 26 <0=> Secure state <1=> Non-Secure state +// Interrupt 27 <0=> Secure state <1=> Non-Secure state +// Interrupt 28 <0=> Secure state <1=> Non-Secure state +// Interrupt 29 <0=> Secure state <1=> Non-Secure state +// Interrupt 30 <0=> Secure state <1=> Non-Secure state +// Interrupt 31 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// Interrupt 32 <0=> Secure state <1=> Non-Secure state +// Interrupt 33 <0=> Secure state <1=> Non-Secure state +// Interrupt 34 <0=> Secure state <1=> Non-Secure state +// Interrupt 35 <0=> Secure state <1=> Non-Secure state +// Interrupt 36 <0=> Secure state <1=> Non-Secure state +// Interrupt 37 <0=> Secure state <1=> Non-Secure state +// Interrupt 38 <0=> Secure state <1=> Non-Secure state +// Interrupt 39 <0=> Secure state <1=> Non-Secure state +// Interrupt 40 <0=> Secure state <1=> Non-Secure state +// Interrupt 41 <0=> Secure state <1=> Non-Secure state +// Interrupt 42 <0=> Secure state <1=> Non-Secure state +// Interrupt 43 <0=> Secure state <1=> Non-Secure state +// Interrupt 44 <0=> Secure state <1=> Non-Secure state +// Interrupt 45 <0=> Secure state <1=> Non-Secure state +// Interrupt 46 <0=> Secure state <1=> Non-Secure state +// Interrupt 47 <0=> Secure state <1=> Non-Secure state +// Interrupt 48 <0=> Secure state <1=> Non-Secure state +// Interrupt 49 <0=> Secure state <1=> Non-Secure state +// Interrupt 50 <0=> Secure state <1=> Non-Secure state +// Interrupt 51 <0=> Secure state <1=> Non-Secure state +// Interrupt 52 <0=> Secure state <1=> Non-Secure state +// Interrupt 53 <0=> Secure state <1=> Non-Secure state +// Interrupt 54 <0=> Secure state <1=> Non-Secure state +// Interrupt 55 <0=> Secure state <1=> Non-Secure state +// Interrupt 56 <0=> Secure state <1=> Non-Secure state +// Interrupt 57 <0=> Secure state <1=> Non-Secure state +// Interrupt 58 <0=> Secure state <1=> Non-Secure state +// Interrupt 59 <0=> Secure state <1=> Non-Secure state +// Interrupt 60 <0=> Secure state <1=> Non-Secure state +// Interrupt 61 <0=> Secure state <1=> Non-Secure state +// Interrupt 62 <0=> Secure state <1=> Non-Secure state +// Interrupt 63 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 0 + +/* +// Interrupts 64..95 +// Interrupt 64 <0=> Secure state <1=> Non-Secure state +// Interrupt 65 <0=> Secure state <1=> Non-Secure state +// Interrupt 66 <0=> Secure state <1=> Non-Secure state +// Interrupt 67 <0=> Secure state <1=> Non-Secure state +// Interrupt 68 <0=> Secure state <1=> Non-Secure state +// Interrupt 69 <0=> Secure state <1=> Non-Secure state +// Interrupt 70 <0=> Secure state <1=> Non-Secure state +// Interrupt 71 <0=> Secure state <1=> Non-Secure state +// Interrupt 72 <0=> Secure state <1=> Non-Secure state +// Interrupt 73 <0=> Secure state <1=> Non-Secure state +// Interrupt 74 <0=> Secure state <1=> Non-Secure state +// Interrupt 75 <0=> Secure state <1=> Non-Secure state +// Interrupt 76 <0=> Secure state <1=> Non-Secure state +// Interrupt 77 <0=> Secure state <1=> Non-Secure state +// Interrupt 78 <0=> Secure state <1=> Non-Secure state +// Interrupt 79 <0=> Secure state <1=> Non-Secure state +// Interrupt 80 <0=> Secure state <1=> Non-Secure state +// Interrupt 81 <0=> Secure state <1=> Non-Secure state +// Interrupt 82 <0=> Secure state <1=> Non-Secure state +// Interrupt 83 <0=> Secure state <1=> Non-Secure state +// Interrupt 84 <0=> Secure state <1=> Non-Secure state +// Interrupt 85 <0=> Secure state <1=> Non-Secure state +// Interrupt 86 <0=> Secure state <1=> Non-Secure state +// Interrupt 87 <0=> Secure state <1=> Non-Secure state +// Interrupt 88 <0=> Secure state <1=> Non-Secure state +// Interrupt 89 <0=> Secure state <1=> Non-Secure state +// Interrupt 90 <0=> Secure state <1=> Non-Secure state +// Interrupt 91 <0=> Secure state <1=> Non-Secure state +// Interrupt 92 <0=> Secure state <1=> Non-Secure state +// Interrupt 93 <0=> Secure state <1=> Non-Secure state +// Interrupt 94 <0=> Secure state <1=> Non-Secure state +// Interrupt 95 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 0 + +/* +// Interrupts 96..127 +// Interrupt 96 <0=> Secure state <1=> Non-Secure state +// Interrupt 97 <0=> Secure state <1=> Non-Secure state +// Interrupt 98 <0=> Secure state <1=> Non-Secure state +// Interrupt 99 <0=> Secure state <1=> Non-Secure state +// Interrupt 100 <0=> Secure state <1=> Non-Secure state +// Interrupt 101 <0=> Secure state <1=> Non-Secure state +// Interrupt 102 <0=> Secure state <1=> Non-Secure state +// Interrupt 103 <0=> Secure state <1=> Non-Secure state +// Interrupt 104 <0=> Secure state <1=> Non-Secure state +// Interrupt 105 <0=> Secure state <1=> Non-Secure state +// Interrupt 106 <0=> Secure state <1=> Non-Secure state +// Interrupt 107 <0=> Secure state <1=> Non-Secure state +// Interrupt 108 <0=> Secure state <1=> Non-Secure state +// Interrupt 109 <0=> Secure state <1=> Non-Secure state +// Interrupt 110 <0=> Secure state <1=> Non-Secure state +// Interrupt 111 <0=> Secure state <1=> Non-Secure state +// Interrupt 112 <0=> Secure state <1=> Non-Secure state +// Interrupt 113 <0=> Secure state <1=> Non-Secure state +// Interrupt 114 <0=> Secure state <1=> Non-Secure state +// Interrupt 115 <0=> Secure state <1=> Non-Secure state +// Interrupt 116 <0=> Secure state <1=> Non-Secure state +// Interrupt 117 <0=> Secure state <1=> Non-Secure state +// Interrupt 118 <0=> Secure state <1=> Non-Secure state +// Interrupt 119 <0=> Secure state <1=> Non-Secure state +// Interrupt 120 <0=> Secure state <1=> Non-Secure state +// Interrupt 121 <0=> Secure state <1=> Non-Secure state +// Interrupt 122 <0=> Secure state <1=> Non-Secure state +// Interrupt 123 <0=> Secure state <1=> Non-Secure state +// Interrupt 124 <0=> Secure state <1=> Non-Secure state +// Interrupt 125 <0=> Secure state <1=> Non-Secure state +// Interrupt 126 <0=> Secure state <1=> Non-Secure state +// Interrupt 127 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 128..159) +*/ +#define NVIC_INIT_ITNS4 0 + +/* +// Interrupts 128..159 +// Interrupt 128 <0=> Secure state <1=> Non-Secure state +// Interrupt 129 <0=> Secure state <1=> Non-Secure state +// Interrupt 130 <0=> Secure state <1=> Non-Secure state +// Interrupt 131 <0=> Secure state <1=> Non-Secure state +// Interrupt 132 <0=> Secure state <1=> Non-Secure state +// Interrupt 133 <0=> Secure state <1=> Non-Secure state +// Interrupt 134 <0=> Secure state <1=> Non-Secure state +// Interrupt 135 <0=> Secure state <1=> Non-Secure state +// Interrupt 136 <0=> Secure state <1=> Non-Secure state +// Interrupt 137 <0=> Secure state <1=> Non-Secure state +// Interrupt 138 <0=> Secure state <1=> Non-Secure state +// Interrupt 139 <0=> Secure state <1=> Non-Secure state +// Interrupt 140 <0=> Secure state <1=> Non-Secure state +// Interrupt 141 <0=> Secure state <1=> Non-Secure state +// Interrupt 142 <0=> Secure state <1=> Non-Secure state +// Interrupt 143 <0=> Secure state <1=> Non-Secure state +// Interrupt 144 <0=> Secure state <1=> Non-Secure state +// Interrupt 145 <0=> Secure state <1=> Non-Secure state +// Interrupt 146 <0=> Secure state <1=> Non-Secure state +// Interrupt 147 <0=> Secure state <1=> Non-Secure state +// Interrupt 148 <0=> Secure state <1=> Non-Secure state +// Interrupt 149 <0=> Secure state <1=> Non-Secure state +// Interrupt 150 <0=> Secure state <1=> Non-Secure state +// Interrupt 151 <0=> Secure state <1=> Non-Secure state +// Interrupt 152 <0=> Secure state <1=> Non-Secure state +// Interrupt 153 <0=> Secure state <1=> Non-Secure state +// Interrupt 154 <0=> Secure state <1=> Non-Secure state +// Interrupt 155 <0=> Secure state <1=> Non-Secure state +// Interrupt 156 <0=> Secure state <1=> Non-Secure state +// Interrupt 157 <0=> Secure state <1=> Non-Secure state +// Interrupt 158 <0=> Secure state <1=> Non-Secure state +// Interrupt 159 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 5 (Interrupts 160..191) +*/ +#define NVIC_INIT_ITNS5 0 + +/* +// Interrupts 160..191 +// Interrupt 160 <0=> Secure state <1=> Non-Secure state +// Interrupt 161 <0=> Secure state <1=> Non-Secure state +// Interrupt 162 <0=> Secure state <1=> Non-Secure state +// Interrupt 163 <0=> Secure state <1=> Non-Secure state +// Interrupt 164 <0=> Secure state <1=> Non-Secure state +// Interrupt 165 <0=> Secure state <1=> Non-Secure state +// Interrupt 166 <0=> Secure state <1=> Non-Secure state +// Interrupt 167 <0=> Secure state <1=> Non-Secure state +// Interrupt 168 <0=> Secure state <1=> Non-Secure state +// Interrupt 169 <0=> Secure state <1=> Non-Secure state +// Interrupt 170 <0=> Secure state <1=> Non-Secure state +// Interrupt 171 <0=> Secure state <1=> Non-Secure state +// Interrupt 172 <0=> Secure state <1=> Non-Secure state +// Interrupt 173 <0=> Secure state <1=> Non-Secure state +// Interrupt 174 <0=> Secure state <1=> Non-Secure state +// Interrupt 175 <0=> Secure state <1=> Non-Secure state +// Interrupt 176 <0=> Secure state <1=> Non-Secure state +// Interrupt 177 <0=> Secure state <1=> Non-Secure state +// Interrupt 178 <0=> Secure state <1=> Non-Secure state +// Interrupt 179 <0=> Secure state <1=> Non-Secure state +// Interrupt 180 <0=> Secure state <1=> Non-Secure state +// Interrupt 181 <0=> Secure state <1=> Non-Secure state +// Interrupt 182 <0=> Secure state <1=> Non-Secure state +// Interrupt 183 <0=> Secure state <1=> Non-Secure state +// Interrupt 184 <0=> Secure state <1=> Non-Secure state +// Interrupt 185 <0=> Secure state <1=> Non-Secure state +// Interrupt 186 <0=> Secure state <1=> Non-Secure state +// Interrupt 187 <0=> Secure state <1=> Non-Secure state +// Interrupt 188 <0=> Secure state <1=> Non-Secure state +// Interrupt 189 <0=> Secure state <1=> Non-Secure state +// Interrupt 190 <0=> Secure state <1=> Non-Secure state +// Interrupt 191 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS5_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 6 (Interrupts 192..223) +*/ +#define NVIC_INIT_ITNS6 0 + +/* +// Interrupts 192..223 +// Interrupt 192 <0=> Secure state <1=> Non-Secure state +// Interrupt 193 <0=> Secure state <1=> Non-Secure state +// Interrupt 194 <0=> Secure state <1=> Non-Secure state +// Interrupt 195 <0=> Secure state <1=> Non-Secure state +// Interrupt 196 <0=> Secure state <1=> Non-Secure state +// Interrupt 197 <0=> Secure state <1=> Non-Secure state +// Interrupt 198 <0=> Secure state <1=> Non-Secure state +// Interrupt 199 <0=> Secure state <1=> Non-Secure state +// Interrupt 200 <0=> Secure state <1=> Non-Secure state +// Interrupt 201 <0=> Secure state <1=> Non-Secure state +// Interrupt 202 <0=> Secure state <1=> Non-Secure state +// Interrupt 203 <0=> Secure state <1=> Non-Secure state +// Interrupt 204 <0=> Secure state <1=> Non-Secure state +// Interrupt 205 <0=> Secure state <1=> Non-Secure state +// Interrupt 206 <0=> Secure state <1=> Non-Secure state +// Interrupt 207 <0=> Secure state <1=> Non-Secure state +// Interrupt 208 <0=> Secure state <1=> Non-Secure state +// Interrupt 209 <0=> Secure state <1=> Non-Secure state +// Interrupt 210 <0=> Secure state <1=> Non-Secure state +// Interrupt 211 <0=> Secure state <1=> Non-Secure state +// Interrupt 212 <0=> Secure state <1=> Non-Secure state +// Interrupt 213 <0=> Secure state <1=> Non-Secure state +// Interrupt 214 <0=> Secure state <1=> Non-Secure state +// Interrupt 215 <0=> Secure state <1=> Non-Secure state +// Interrupt 216 <0=> Secure state <1=> Non-Secure state +// Interrupt 217 <0=> Secure state <1=> Non-Secure state +// Interrupt 218 <0=> Secure state <1=> Non-Secure state +// Interrupt 219 <0=> Secure state <1=> Non-Secure state +// Interrupt 220 <0=> Secure state <1=> Non-Secure state +// Interrupt 221 <0=> Secure state <1=> Non-Secure state +// Interrupt 222 <0=> Secure state <1=> Non-Secure state +// Interrupt 223 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS6_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 7 (Interrupts 224..255) +*/ +#define NVIC_INIT_ITNS7 0 + +/* +// Interrupts 224..255 +// Interrupt 224 <0=> Secure state <1=> Non-Secure state +// Interrupt 225 <0=> Secure state <1=> Non-Secure state +// Interrupt 226 <0=> Secure state <1=> Non-Secure state +// Interrupt 227 <0=> Secure state <1=> Non-Secure state +// Interrupt 228 <0=> Secure state <1=> Non-Secure state +// Interrupt 229 <0=> Secure state <1=> Non-Secure state +// Interrupt 230 <0=> Secure state <1=> Non-Secure state +// Interrupt 231 <0=> Secure state <1=> Non-Secure state +// Interrupt 232 <0=> Secure state <1=> Non-Secure state +// Interrupt 233 <0=> Secure state <1=> Non-Secure state +// Interrupt 234 <0=> Secure state <1=> Non-Secure state +// Interrupt 235 <0=> Secure state <1=> Non-Secure state +// Interrupt 236 <0=> Secure state <1=> Non-Secure state +// Interrupt 237 <0=> Secure state <1=> Non-Secure state +// Interrupt 238 <0=> Secure state <1=> Non-Secure state +// Interrupt 239 <0=> Secure state <1=> Non-Secure state +// Interrupt 240 <0=> Secure state <1=> Non-Secure state +// Interrupt 241 <0=> Secure state <1=> Non-Secure state +// Interrupt 242 <0=> Secure state <1=> Non-Secure state +// Interrupt 243 <0=> Secure state <1=> Non-Secure state +// Interrupt 244 <0=> Secure state <1=> Non-Secure state +// Interrupt 245 <0=> Secure state <1=> Non-Secure state +// Interrupt 246 <0=> Secure state <1=> Non-Secure state +// Interrupt 247 <0=> Secure state <1=> Non-Secure state +// Interrupt 248 <0=> Secure state <1=> Non-Secure state +// Interrupt 249 <0=> Secure state <1=> Non-Secure state +// Interrupt 250 <0=> Secure state <1=> Non-Secure state +// Interrupt 251 <0=> Secure state <1=> Non-Secure state +// Interrupt 252 <0=> Secure state <1=> Non-Secure state +// Interrupt 253 <0=> Secure state <1=> Non-Secure state +// Interrupt 254 <0=> Secure state <1=> Non-Secure state +// Interrupt 255 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS7_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + + + +/* + max 128 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) + SCB->ICSR = (SCB->ICSR & ~(SCB_ICSR_STTNS_Msk )) | + ((SCB_ICSR_STTNS_VAL << SCB_ICSR_STTNS_Pos) & SCB_ICSR_STTNS_Msk); + #endif /* defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) */ + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + + #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) + NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; + #endif + + #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) + NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; + #endif + + #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) + NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; + #endif + + /* repeat this for all possible ITNS elements */ + +} + +#endif /* PARTITION_ARMCM23_H */ diff --git a/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c new file mode 100644 index 00000000..30dc1dfd --- /dev/null +++ b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c @@ -0,0 +1,137 @@ +/****************************************************************************** + * @file startup_ARMCM23.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M23 Device + * @version V2.0.0 + * @date 04. June 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM23) + #include "ARMCM23.h" +#elif defined (ARMCM23_TZ) + #include "ARMCM23_TZ.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler Function Prototype + *----------------------------------------------------------------------------*/ +typedef void( *pFunc )( void ); + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const pFunc __VECTOR_TABLE[240]; + const pFunc __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/system_ARMCM23.c b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/system_ARMCM23.c new file mode 100644 index 00000000..61ef3fe6 --- /dev/null +++ b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/system_ARMCM23.c @@ -0,0 +1,82 @@ +/**************************************************************************//** + * @file system_ARMCM23.c + * @brief CMSIS Device System Source File for + * ARMCM23 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM23) + #include "ARMCM23.h" +#elif defined (ARMCM23_TZ) + #include "ARMCM23_TZ.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM23.h" + #endif +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __VECTOR_TABLE; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__VECTOR_TABLE; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h new file mode 100644 index 00000000..1cde6a79 --- /dev/null +++ b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'demo_threadx_non-secure_zone' + * Target: 'FVP Simulation Model' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM23_TZ.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h new file mode 100644 index 00000000..476361d7 --- /dev/null +++ b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'ThreadX_Library' + * Target: 'ThreadX_Library_Project' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM23_TZ.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/ThreadX_Demo.uvopt b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/ThreadX_Demo.uvopt new file mode 100644 index 00000000..7ec4b36b --- /dev/null +++ b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/ThreadX_Demo.uvopt @@ -0,0 +1,305 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + ThreadX_Demo + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 1 + 0 + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + -1 + + + + + + + + + + + + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0) + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(102=-1,-1,-1,-1,0)(103=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(163=-1,-1,-1,-1,0)(164=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)(152=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)(1013=-1,-1,-1,-1,0)(171=-1,-1,-1,-1,0)(172=-1,-1,-1,-1,0)(173=-1,-1,-1,-1,0)(1014=-1,-1,-1,-1,0)(1016=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T5F + + + 0 + UL2CM3 + -UV0289BJE -O14 -S0 -C0 -N00("ARM CoreSight JTAG-DP") -D00(3BA00477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_16 -FS00 -FL04000 + + + + + + 0 + 1 + thread_0_counter + + + 1 + 1 + thread_1_counter + + + 2 + 1 + thread_2_counter + + + 3 + 1 + thread_3_counter + + + 4 + 1 + thread_4_counter + + + 5 + 1 + thread_5_counter + + + 6 + 1 + _tx_thread_current_ptr + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Source Group + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + .\tx_initialize_low_level.s + tx_initialize_low_level.s + 0 + 0 + + + 1 + 2 + 1 + 1 + 0 + 0 + .\demo_threadx.c + demo_threadx.c + 0 + 0 + + 44 + 0 + 1 + + -1 + -1 + + + -1 + -1 + + + 56 + 12 + 1633 + 671 + + + + + + + Library_Group + 1 + 0 + 0 + 0 + + 2 + 3 + 4 + 0 + 0 + 0 + .\ThreadX_Library.lib + ThreadX_Library.lib + 0 + 0 + + + + diff --git a/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/ThreadX_Demo.uvproj b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/ThreadX_Demo.uvproj new file mode 100644 index 00000000..5f5dcbdb --- /dev/null +++ b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/ThreadX_Demo.uvproj @@ -0,0 +1,556 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + ThreadX_Demo + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + Cortex-M4 FPU + ARM + CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 + + + + 5237 + + + + + + + + + + + + 0 + 0 + + + + Luminary\ + Luminary\ + + 0 + 0 + 0 + 0 + 1 + + .\ + threadx_demo + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DCM.DLL + -pCM4F + SARMCM3.DLL + + TCM.DLL + -pCM4F + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + + 0 + -1 + + + + + + + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 4096 + + 0 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + --first __tx_vectors --entry=__main + + + + + + + + Source Group + + + 0 + 1 + 1 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 0 + + + + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + tx_initialize_low_level.s + 2 + .\tx_initialize_low_level.s + + + 2 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 2 + 2 + 1 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + demo_threadx.c + 1 + .\demo_threadx.c + + + + + Library_Group + + + ThreadX_Library.lib + 4 + .\ThreadX_Library.lib + + + + + + + + diff --git a/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx.c b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx.c new file mode 100644 index 00000000..7320b94d --- /dev/null +++ b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx.c @@ -0,0 +1,428 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. Please refer to Chapter 6 of the ThreadX User Guide for a complete + description of this demonstration. */ + +#include "tx_api.h" +#include "..\demo_secure_zone\interface.h" /* Interface to sample secure functions. */ + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +static TX_THREAD thread_0; +static TX_THREAD thread_1; +static TX_THREAD thread_2; +static TX_THREAD thread_3; +static TX_THREAD thread_4; +static TX_THREAD thread_5; +static TX_THREAD thread_6; +static TX_THREAD thread_7; +static TX_QUEUE queue_0; +static TX_SEMAPHORE semaphore_0; +static TX_MUTEX mutex_0; +static TX_EVENT_FLAGS_GROUP event_flags_0; +static TX_BYTE_POOL byte_pool_0; +static TX_BLOCK_POOL block_pool_0; + +/* Define byte pool memory. */ + +static UCHAR byte_pool_memory[DEMO_BYTE_POOL_SIZE]; + + +/* Define event buffer. */ + +#ifdef TX_ENABLE_EVENT_TRACE +UCHAR trace_buffer[0x10000]; +#endif + + +/* Define the counters used in the demo application... */ + +static ULONG thread_0_counter; +static ULONG thread_1_counter; +static ULONG thread_1_messages_sent; +static ULONG thread_2_counter; +static ULONG thread_2_messages_received; +static ULONG thread_3_counter; +static ULONG thread_4_counter; +static ULONG thread_5_counter; +static ULONG thread_6_counter; +static ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Please refer to Chapter 6 of the ThreadX User Guide for a complete + description of this demonstration. */ + + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer; + + (VOID)first_unused_memory; /* unused parameter. */ + +#ifdef TX_ENABLE_EVENT_TRACE + tx_trace_enable(trace_buffer, sizeof(trace_buffer), 32); +#endif + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", byte_pool_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate secure stack space for thread. */ + tx_thread_secure_stack_allocate(&thread_0,256); + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate secure stack space for thread. */ + tx_thread_secure_stack_allocate(&thread_1,256); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate secure stack space for thread. */ + tx_thread_secure_stack_allocate(&thread_2,256); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate secure stack space for thread. */ + tx_thread_secure_stack_allocate(&thread_3,256); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate secure stack space for thread. */ + tx_thread_secure_stack_allocate(&thread_4,256); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate secure stack space for thread. */ + tx_thread_secure_stack_allocate(&thread_5,256); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate secure stack space for thread. */ + tx_thread_secure_stack_allocate(&thread_6,256); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate secure stack space for thread. */ + tx_thread_secure_stack_allocate(&thread_7,256); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + +static int callbackA (int val) +{ + return (val+1); +} + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ +UINT status; +INT test_secure; + + (VOID)thread_input; /* unused parameter. */ + + #if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + /* Secure call and callback example. + Only to be used when not running in a single mode. */ + test_secure = func1(3); + test_secure = func2(callbackA, test_secure); + tx_thread_secure_stack_free(&thread_0); + #endif + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + (VOID)thread_input; /* unused parameter. */ + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + (VOID)thread_input; /* unused parameter. */ + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + (VOID)thread_input; /* unused parameter. */ + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx_non-secure_zone.uvoptx b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx_non-secure_zone.uvoptx new file mode 100644 index 00000000..ea78cfd6 --- /dev/null +++ b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx_non-secure_zone.uvoptx @@ -0,0 +1,373 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + FVP Simulation Model + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 15 + + + + + + + + + + ..\Debug.ini + BIN\DbgFMv8M.DLL + + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FC1000 -FD20000000 + + + 0 + DbgFMv8M + -I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M23_MDK.exe" -MF"..\ARMCM23_TZ_config.txt" -PF -MA + + + 0 + PWSTATINFO + 200,50,700 + + + 0 + DLGTARM + (6010=1830,250,2307,846,0)(6018=1284,352,1473,701,0)(6019=1328,34,1517,370,0)(6008=1865,39,2159,224,0)(6009=1860,848,2154,1033,0)(6014=1111,129,1369,860,0)(6015=872,146,1130,768,0)(6003=-1,-1,-1,-1,0)(6000=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=150,186,829,544,0)(106=511,345,1277,659,0)(107=-1,-1,-1,-1,0) + + + + + 0 + 0 + 89 + 1 +
1046
+ 0 + 0 + 0 + 0 + 0 + 1 + <1>RTE\Device\ARMCM23_TZ\system_ARMCM23.c + + \\demo_secure_zone\RTE/Device/ARMCM23_TZ/system_ARMCM23.c\89 + + + 1 + 0 + 0 + 1 +
2107412
+ 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + 0 + 1 + thread_0_counter + + + 1 + 1 + thread_1_counter + + + 2 + 1 + thread_2_counter + + + 3 + 1 + thread_3_counter + + + 4 + 1 + thread_4_counter + + + 5 + 1 + thread_5_counter + + + 6 + 1 + thread_6_counter + + + 7 + 1 + thread_7_counter + + + 8 + 1 + _tx_thread_current_ptr + + + + + 1 + 2 + 0x2023ffb8 + 0 + + + + + 2 + 2 + 0xE000ED28 + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Non-secure Code + 1 + 0 + 0 + 0 + + 1 + 1 + 4 + 0 + 0 + 0 + ..\ThreadX_Library.lib + ThreadX_Library.lib + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + .\demo_threadx.c + demo_threadx.c + 0 + 0 + + + + + CMSE Library + 0 + 0 + 0 + 0 + + 2 + 3 + 5 + 0 + 0 + 0 + ..\demo_secure_zone\interface.h + interface.h + 0 + 0 + + + 2 + 4 + 3 + 0 + 0 + 0 + ..\demo_secure_zone\Objects\demo_secure_zone_CMSE_Lib.o + demo_secure_zone_CMSE_Lib.o + 0 + 0 + + + + + ::CMSIS + 1 + 0 + 0 + 1 + + + + ::Device + 0 + 0 + 0 + 1 + + + diff --git a/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx_non-secure_zone.uvprojx b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx_non-secure_zone.uvprojx new file mode 100644 index 00000000..ef9a5e79 --- /dev/null +++ b/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx_non-secure_zone.uvprojx @@ -0,0 +1,602 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + FVP Simulation Model + 0x4 + ARM-ADS + 6140000::V6.14::ARMCLANG + 1 + + + ARMCM23_TZ + ARM + ARM.CMSIS.5.7.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("Cortex-M23") TZ CLOCK(12000000) ESEL ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM23_TZ$Device\ARM\ARMCM23\Include\ARMCM23_TZ.h + + + + + + + + + + + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + demo_threadx_non-secure_zone + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + -MPU + TCM.DLL + -pCM23 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 0 + -1 + + 1 + BIN\UL2V8M.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M23" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 8 + 1 + 1 + 0 + 0 + 4 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x200000 + + + 1 + 0x200000 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x20200000 + 0x20000 + + + + + + 1 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 3 + 1 + 1 + 1 + 0 + 0 + 0 + + -Wno-unused-function -Wno-visibility + + + ..\..\..\..\..\common\inc, ..\..\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\RTE\Device\ARMCM23_TZ\ARMCM23_ac6.sct + + + + + + + + + + + Non-secure Code + + + ThreadX_Library.lib + 4 + ..\ThreadX_Library.lib + + + demo_threadx.c + 1 + .\demo_threadx.c + + + + + CMSE Library + + + interface.h + 5 + ..\demo_secure_zone\interface.h + + + demo_secure_zone_CMSE_Lib.o + 3 + ..\demo_secure_zone\Objects\demo_secure_zone_CMSE_Lib.o + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + RTE\Device\ARMCM23_TZ\ARMCM23_ac6.sct + + + + + + + + RTE\Device\ARMCM23_TZ\partition_ARMCM23.h + + + + + + RTE\Device\ARMCM23_TZ\startup_ARMCM23.c + + + + + + + + RTE\Device\ARMCM23_TZ\system_ARMCM23.c + + + + + + + + RTE\Device\ARMCM33_DSP_FP\startup_ARMCM33.s + + + + + + RTE\Device\ARMCM33_DSP_FP\system_ARMCM33.c + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\ARMCM33_ac6.sct + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\partition_ARMCM33.h + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.c + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.s + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\system_ARMCM33.c + + + + + + RTE\Device\ARMCM33_TZ\partition_ARMCM33.h + + + + + + RTE\Device\ARMCM33_TZ\startup_ARMCM33.s + + + + + + RTE\Device\ARMCM33_TZ\system_ARMCM33.c + + + + + + RTE\Device\ARMv8MBL\partition_ARMv8MBL.h + + + + + + RTE\Device\ARMv8MBL\startup_ARMv8MBL.s + + + + + + RTE\Device\ARMv8MBL\system_ARMv8MBL.c + + + + + + RTE\Device\CMSDK_ARMv8MBL\RTE_Device.h + + + + + + RTE\Device\CMSDK_ARMv8MBL\partition_CMSDK_ARMv8MBL.h + + + + + + RTE\Device\CMSDK_ARMv8MBL\startup_CMSDK_ARMv8MBL.s + + + + + + RTE\Device\CMSDK_ARMv8MBL\system_CMSDK_ARMv8MBL.c + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/ports/cortex_m23/ac6/example_build/tx_initialize_low_level.S b/ports/cortex_m23/ac6/example_build/tx_initialize_low_level.S new file mode 100644 index 00000000..3ea33abb --- /dev/null +++ b/ports/cortex_m23/ac6/example_build/tx_initialize_low_level.S @@ -0,0 +1,210 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +SYSTEM_CLOCK = 6000000 +SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) + +/* Setup the stack and heap areas. */ + +STACK_SIZE = 0x00000400 +HEAP_SIZE = 0x00000000 + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-M23/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_initialize_low_level(VOID) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_initialize_low_level + .thumb_func +.type _tx_initialize_low_level, function +_tx_initialize_low_level: + + /* Disable interrupts during ThreadX initialization. */ + CPSID i + + /* Set base of available memory to end of non-initialised RAM area. */ + LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer + LDR r1, =Image$$ARM_LIB_STACK$$ZI$$Limit // Build first free address + ADDS r1, r1, #4 // + STR r1, [r0] // Setup first unused memory pointer + + /* Setup Vector Table Offset Register. */ + LDR r0, =0xE000ED08 // Build address of NVIC registers + LDR r1, =__Vectors // Pickup address of vector table + STR r1, [r0] // Set vector table address + +// /* Enable the cycle count register. */ +// +// LDR r0, =0xE0001000 // Build address of DWT register +// LDR r1, [r0] // Pickup the current value +// ORR r1, r1, #1 // Set the CYCCNTENA bit +// STR r1, [r0] // Enable the cycle count register + + /* Set system stack pointer from vector value. */ + LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer + LDR r1, =__Vectors // Pickup address of vector table + LDR r1, [r1] // Pickup reset stack pointer + STR r1, [r0] // Save system stack pointer + + /* Configure SysTick. */ + LDR r0, =0xE000E000 // Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] // Setup SysTick Reload Value + MOVW r1, #0x7 // Build SysTick Control Enable Value + STR r1, [r0, #0x10] // Setup SysTick Control + + /* Configure handler priorities. */ + LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM + LDR r0, =0xE000E000 // Build address of NVIC registers + LDR r2, =0xD18 // + ADD r0, r0, r2 // + STR r1, [r0] // Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv + LDR r0, =0xE000E000 // Build address of NVIC registers + LDR r2, =0xD1C // + ADD r0, r0, r2 // + STR r1, [r0] // Setup System Handlers 8-11 Priority Registers + // Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM + LDR r0, =0xE000E000 // Build address of NVIC registers + LDR r2, =0xD20 // + ADD r0, r0, r2 // + STR r1, [r0] // Setup System Handlers 12-15 Priority Registers + // Note: PnSV must be lowest priority, which is 0xFF + + /* Return to caller. */ + BX lr +// } + + +/* Define shells for each of the unused vectors. */ + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global __tx_BadHandler + .thumb_func +.type __tx_BadHandler, function +__tx_BadHandler: + B __tx_BadHandler + + + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global __tx_IntHandler + .thumb_func +.type __tx_IntHandler, function +__tx_IntHandler: +// VOID InterruptHandler (VOID) +// { + PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) + + /* Do interrupt handler work here */ + /* .... */ + + POP {r0, r1} + MOV lr, r1 + BX lr +// } + + + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global SysTick_Handler + .thumb_func +.type SysTick_Handler, function +SysTick_Handler: +// VOID TimerInterruptHandler (VOID) +// { + PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) + BL _tx_timer_interrupt + POP {r0, r1} + MOV lr, r1 + BX lr +// } + + + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global HardFault_Handler + .thumb_func +.type HardFault_Handler, function +HardFault_Handler: + // A stack overflow will trigger a hardfault. + // There is no CFSR in M23, so we will not try to + // determine if the fault is caused by a stack overflow + // or some other condition. + B HardFault_Handler + + .end diff --git a/ports/cortex_m23/ac6/inc/tx_port.h b/ports/cortex_m23/ac6/inc/tx_port.h new file mode 100644 index 00000000..9a185550 --- /dev/null +++ b/ports/cortex_m23/ac6/inc/tx_port.h @@ -0,0 +1,418 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-M23/AC6 */ +/* 6.1 */ +/* */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + +/* Determine if the optional ThreadX user define file should be used. */ +#ifdef TX_INCLUDE_USER_DEFINE_FILE + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + +/* Define compiler library include files. */ + +#include +#include +#include +#include "ARMCM23_TZ.h" /* For intrinsic functions. */ + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef unsigned long long ULONG64; +typedef short SHORT; +typedef unsigned short USHORT; + +/* Function prototypes for this port. */ +struct TX_THREAD_STRUCT; +UINT _txe_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *thread_ptr, ULONG stack_size); +UINT _txe_thread_secure_stack_free(struct TX_THREAD_STRUCT *thread_ptr); +UINT _tx_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *tx_thread, ULONG stack_size); +UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); + +/* This hardware has stack checking that we take advantage of - do NOT define. */ +#ifdef TX_ENABLE_STACK_CHECKING + #error "Do not define TX_ENABLE_STACK_CHECKING" +#endif + +/* If user does not want to terminate thread on stack overflow, + #define the TX_THREAD_NO_TERMINATE_STACK_ERROR symbol. + The thread will be rescheduled and continue to cause the exception. + It is suggested user code handle this by registering a notification with the + tx_thread_stack_error_notify function. */ +/*#define TX_THREAD_NO_TERMINATE_STACK_ERROR */ + +/* Define the system API mappings based on the error checking + selected by the user. Note: this section is only applicable to + application source code, hence the conditional that turns off this + stuff when the include file is processed by the ThreadX source. */ + +#ifndef TX_SOURCE_CODE + + +/* Determine if error checking is desired. If so, map API functions + to the appropriate error checking front-ends. Otherwise, map API + functions to the core functions that actually perform the work. + Note: error checking is enabled by default. */ + +#ifdef TX_DISABLE_ERROR_CHECKING + +/* Services without error checking. */ + +#define tx_thread_secure_stack_allocate _tx_thread_secure_stack_allocate +#define tx_thread_secure_stack_free _tx_thread_secure_stack_free + +#else + +/* Services with error checking. */ + +#define tx_thread_secure_stack_allocate _txe_thread_secure_stack_allocate +#define tx_thread_secure_stack_free _txe_thread_secure_stack_free + +#endif +#endif + + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX Cortex-M23 port. */ + +#define TX_INT_DISABLE 1 /* Disable interrupts */ +#define TX_INT_ENABLE 0 /* Enable interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) +#endif +#else +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif + +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_secure_stack_context; +#else +#define TX_THREAD_EXTENSION_2 +#endif +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) if(thread_ptr -> tx_thread_secure_stack_context){_tx_thread_secure_stack_free(thread_ptr);} +#else +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +/* Define the size of the secure stack for the timer thread and use the extension to allocate the secure stack. */ +#define TX_TIMER_THREAD_SECURE_STACK_SIZE 256 +#define TX_TIMER_INITIALIZE_EXTENSION(status) _tx_thread_secure_stack_allocate(&_tx_timer_thread, TX_TIMER_THREAD_SECURE_STACK_SIZE); +#endif + + +#ifndef TX_MISRA_ENABLE + +//register unsigned int _ipsr __asm ("MRS %[result], ipsr" : [result] "=r" (_ipsr) : ); +inline static unsigned int _get_ipsr(void); +inline static unsigned int _get_ipsr(void) +{ + unsigned int _ipsr; + __asm("MRS %[result], ipsr" : [result] "=r" (_ipsr) : ); + return _ipsr; +} + +#endif + + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define the get system state macro. */ + +#ifndef TX_THREAD_GET_SYSTEM_STATE +#ifndef TX_MISRA_ENABLE +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _get_ipsr()) +#else +ULONG _tx_misra_ipsr_get(VOID); +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get()) +#endif +#endif + + +/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value + indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h + for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always + zero after initialization for Cortex-M ports. */ + +#ifndef TX_THREAD_SYSTEM_RETURN_CHECK +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#endif + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +/* Initialize secure stacks for threads calling secure functions. */ +extern void _tx_thread_secure_stack_initialize(void); +#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION _tx_thread_secure_stack_initialize(); +#endif + +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to + prevent early scheduling on Cortex-M parts. */ + +#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); + +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifdef TX_DISABLE_INLINE + +UINT _tx_thread_interrupt_disable(VOID); +VOID _tx_thread_interrupt_restore(UINT previous_posture); + +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); + +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA unsigned int was_masked; +#define TX_DISABLE was_masked = __disable_irq(); +#define TX_RESTORE if (was_masked == 0) __enable_irq(); + +#define _tx_thread_system_return _tx_thread_system_return_inline + + +static void _tx_thread_system_return_inline(void) +{ +unsigned int was_masked; + + + /* Set PendSV to invoke ThreadX scheduler. */ + *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + if (_get_ipsr() == 0) + { + was_masked = __disable_irq(); + __enable_irq(); + if (was_masked != 0) + __disable_irq(); + } +} +#endif + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/AC6 Version 6.1 *"; +#else +#ifdef TX_MISRA_ENABLE +extern CHAR _tx_version_id[100]; +#else +extern CHAR _tx_version_id[]; +#endif +#endif + +#endif diff --git a/ports/cortex_m23/ac6/inc/tx_secure_interface.h b/ports/cortex_m23/ac6/inc/tx_secure_interface.h new file mode 100644 index 00000000..976f32be --- /dev/null +++ b/ports/cortex_m23/ac6/inc/tx_secure_interface.h @@ -0,0 +1,60 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* tx_secure_interface.h Cortex-M23 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the ThreadX secure thread stack components, */ +/* including data types and external references. */ +/* It is assumed that tx_api.h and tx_port.h have already been */ +/* included. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_SECURE_INTERFACE_H +#define TX_SECURE_INTERFACE_H + +/* Define internal secure thread stack function prototypes. */ + +extern void _tx_thread_secure_stack_initialize(void); +extern UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size); +extern UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr); +extern void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr); +extern void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr); + +#endif diff --git a/ports/cortex_m23/ac6/readme_threadx.txt b/ports/cortex_m23/ac6/readme_threadx.txt new file mode 100644 index 00000000..0b5ace53 --- /dev/null +++ b/ports/cortex_m23/ac6/readme_threadx.txt @@ -0,0 +1,154 @@ + Microsoft's Azure RTOS ThreadX for Cortex-M23 + + Using the AC6 Tools in Keil uVision + +1. Import the ThreadX Projects + +In order to build the ThreadX library and the ThreadX demonstration, first open +the AzureRTOS.uvmpw workspace (located in the "example_build" directory) +into Keil. + + +2. Building the ThreadX run-time Library + +Building the ThreadX library is easy; simply set the ThreadX_Library project +as active, then then build the library. You should now observe the compilation +and assembly of the ThreadX library. This project build produces the ThreadX +library file ThreadX_Library.lib. + + +3. Demonstration System + +The ThreadX demonstration is designed to execute under the Keil debugger on the +FVP_MPS2_Cortex-M23_MDK simulator. + +Building the demonstration is easy; simply select the "Batch Build" button. +You should now observe the compilation and assembly of the ThreadX demonstration of +both the demo_secure_zone and demo_threadx_non-secure_zone projects. +Then click the Start/Stop Debug Session button to start the simulator and begin debugging. +You are now ready to execute the ThreadX demonstration. + + +4. System Initialization + +The entry point in ThreadX for the Cortex-M23 using AC6 tools uses the standard AC6 +Cortex-M23 reset sequence. From the reset vector the C runtime will be initialized. + +The ThreadX tx_initialize_low_level.S file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. + +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input +parameter to your application definition function, tx_application_define. + + +5. Register Usage and Stack Frames + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have the same stack frame in the Cortex-M23 version of +ThreadX. The top of the suspended thread's stack is pointed to by +tx_thread_stack_ptr in the associated thread control block TX_THREAD. + + + Stack Offset Stack Contents + + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 r8 + 0x08 r9 + 0x0C r10 + 0x10 r11 + 0x14 r4 + 0x18 r5 + 0x1C r6 + 0x20 r7 + 0x24 r0 (Hardware stack starts here!!) + 0x28 r1 + 0x2C r2 + 0x30 r3 + 0x34 r12 + 0x38 lr + 0x3C pc + 0x40 xPSR + + +6. Improving Performance + +To make ThreadX and the application(s) run faster, you can enable +all compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-M23 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +7.1 Vector Area + +The Cortex-M23 vectors start at the label __Vectors or similar. The application may modify +the vector area according to its needs. There is code in tx_initialize_low_level() that will +configure the vector base register. + + +7.2 Managed Interrupts + +ISRs can be written completely in C (or assembly language) without any calls to +_tx_thread_context_save or _tx_thread_context_restore. These ISRs are allowed access to the +ThreadX API that is available to ISRs. + +ISRs written in C will take the form (where "your_C_isr" is an entry in the vector table): + +void your_C_isr(void) +{ + + /* ISR processing goes here, including any needed function calls. */ +} + +ISRs written in assembly language will take the form: + + + .global your_assembly_isr + .thumb_func +your_assembly_isr: +; VOID your_assembly_isr(VOID) +; { + PUSH {r0, lr} +; +; /* Do interrupt handler work here */ +; /* BL */ + + POP {r0, r1} + MOV lr, r1 + BX lr +; } + + +Note: the Cortex-M23 requires exception handlers to be thumb labels, this implies bit 0 set. +To accomplish this, the declaration of the label has to be preceded by the assembler directive +.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to +be inserted in the correct location in the interrupt vector table. This table is typically +located in either your runtime startup file or in the tx_initialize_low_level.S file. + + +8. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + + +09-30-2020 Initial ThreadX 6.1 version for Cortex-M23 using AC6 tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_m23/ac6/src/tx_thread_context_restore.s b/ports/cortex_m23/ac6/src/tx_thread_context_restore.s new file mode 100644 index 00000000..b2989990 --- /dev/null +++ b/ports/cortex_m23/ac6/src/tx_thread_context_restore.s @@ -0,0 +1,74 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore Cortex-M23/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is not needed for Cortex-M. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* None */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_context_restore(VOID) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_context_restore + .thumb_func +.type _tx_thread_context_restore, function +_tx_thread_context_restore: + /* Return to interrupt processing. */ + BX lr +// } + .end diff --git a/ports/cortex_m23/ac6/src/tx_thread_context_save.s b/ports/cortex_m23/ac6/src/tx_thread_context_save.s new file mode 100644 index 00000000..fefeb7b0 --- /dev/null +++ b/ports/cortex_m23/ac6/src/tx_thread_context_save.s @@ -0,0 +1,74 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save Cortex-M23/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is not needed for Cortex-M. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* None */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_context_save(VOID) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_context_save + .thumb_func +.type _tx_thread_context_save, function +_tx_thread_context_save: + /* Return to interrupt processing. */ + BX lr +// } + .end diff --git a/ports/cortex_m23/ac6/src/tx_thread_interrupt_control.s b/ports/cortex_m23/ac6/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..7a24fffd --- /dev/null +++ b/ports/cortex_m23/ac6/src/tx_thread_interrupt_control.s @@ -0,0 +1,78 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control Cortex-M23/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_interrupt_control(UINT new_posture) +// { + .section .text + .balign 4 + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_interrupt_control + .thumb_func +.type _tx_thread_interrupt_control, function +_tx_thread_interrupt_control: + + /* Pickup current interrupt lockout posture. */ + MRS r1, PRIMASK + MSR PRIMASK, r0 + MOV r0, r1 + BX lr +// } + .end diff --git a/ports/cortex_m23/ac6/src/tx_thread_interrupt_disable.s b/ports/cortex_m23/ac6/src/tx_thread_interrupt_disable.s new file mode 100644 index 00000000..d99f1713 --- /dev/null +++ b/ports/cortex_m23/ac6/src/tx_thread_interrupt_disable.s @@ -0,0 +1,77 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_disable Cortex-M23/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for disabling interrupts and returning */ +/* the previous interrupt lockout posture. */ +/* */ +/* INPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_interrupt_disable(UINT new_posture) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_interrupt_disable + .thumb_func +.type _tx_thread_interrupt_disable, function +_tx_thread_interrupt_disable: + /* Return current interrupt lockout posture. */ + MRS r0, PRIMASK + CPSID i + BX lr +// } + .end diff --git a/ports/cortex_m23/ac6/src/tx_thread_interrupt_restore.s b/ports/cortex_m23/ac6/src/tx_thread_interrupt_restore.s new file mode 100644 index 00000000..b03ad941 --- /dev/null +++ b/ports/cortex_m23/ac6/src/tx_thread_interrupt_restore.s @@ -0,0 +1,76 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_restore Cortex-M23/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for restoring the previous */ +/* interrupt lockout posture. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* previous_posture Previous interrupt posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_interrupt_restore(UINT new_posture) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_interrupt_restore + .thumb_func +.type _tx_thread_interrupt_restore, function +_tx_thread_interrupt_restore: + /* Restore previous interrupt lockout posture. */ + MSR PRIMASK, r0 + BX lr +// } + .end diff --git a/ports/cortex_m23/ac6/src/tx_thread_schedule.s b/ports/cortex_m23/ac6/src/tx_thread_schedule.s new file mode 100644 index 00000000..442a0567 --- /dev/null +++ b/ports/cortex_m23/ac6/src/tx_thread_schedule.s @@ -0,0 +1,327 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule Cortex-M23/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_schedule(VOID) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_schedule + .thumb_func +.type _tx_thread_schedule, function +_tx_thread_schedule: + /* This function should only ever be called on Cortex-M + from the first schedule request. Subsequent scheduling occurs + from the PendSV handling routine below. */ + + /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ + MOVW r0, #0 // Build value for TX_FALSE + LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag + STR r0, [r2, #0] // Clear preempt disable flag + + /* Enable interrupts */ + CPSIE i + + /* Enter the scheduler for the first time. */ + + LDR r0, =0x10000000 // Load PENDSVSET bit + LDR r1, =0xE000ED04 // Load ICSR address + STR r0, [r1] // Set PENDSVBIT in ICSR + DSB // Complete all memory accesses + ISB // Flush pipeline + + /* Wait here for the PendSV to take place. */ + +__tx_wait_here: + B __tx_wait_here // Wait for the PendSV to happen +// } + + /* Generic context switching PendSV handler. */ + + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global PendSV_Handler + .thumb_func +.type PendSV_Handler, function + /* Get current thread value and new thread pointer. */ +PendSV_Handler: +__tx_ts_handler: + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + /* Call the thread exit function to indicate the thread is no longer executing. */ + CPSID i // Disable interrupts + PUSH {r0, lr} // Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit // Call the thread exit function + POP {r0, r1} // Recover LR + MOV lr, r1 + CPSIE i // Enable interrupts +#endif + + MOVW r0, #:lower16:_tx_thread_current_ptr // Build current thread pointer address + MOVT r0, #:upper16:_tx_thread_current_ptr + MOVW r2, #:lower16:_tx_thread_execute_ptr // Build execute thread pointer address + MOVT r2, #:upper16:_tx_thread_execute_ptr + MOVW r3, #0 // Build NULL value + LDR r1, [r0] // Pickup current thread pointer + + /* Determine if there is a current thread to finish preserving. */ + + CBZ r1, __tx_ts_new // If NULL, skip preservation + + /* Recover PSP and preserve current thread context. */ + + STR r3, [r0] // Set _tx_thread_current_ptr to NULL + MRS r3, PSP // Pickup PSP pointer (thread's stack pointer) + SUBS r3, r3, #16 // Allocate stack space + STM r3!, {r4-r7} // Save its remaining registers (M3 Instruction: STMDB r12!, {r4-r11}) + MOV r4, r8 // + MOV r5, r9 // + MOV r6, r10 // + MOV r7, r11 // + SUBS r3, r3, #32 // Allocate stack space + STM r3!, {r4-r7} // + SUBS r3, r3, #20 // Allocate stack space + MOV r5, lr // + STR r5, [r3] // Save LR on the stack + STR r3, [r1, #8] // Save the thread stack pointer + +#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) + // Save secure context + LDR r5, =0x90 // Secure stack index offset + LDR r5, [r1, r5] // Load secure stack index + CBZ r5, _skip_secure_save // Skip save if there is no secure context + PUSH {r0, r1, r2, r3} // Save scratch registers + MOV r0, r1 // Move thread ptr to r0 + BL _tx_thread_secure_stack_context_save // Save secure stack + POP {r0, r1, r2, r3} // Restore secure registers +_skip_secure_save: +#endif + + /* Determine if time-slice is active. If it isn't, skip time handling processing. */ + + LDR r4, =_tx_timer_time_slice // Build address of time-slice variable + LDR r5, [r4] // Pickup current time-slice + CBZ r5, __tx_ts_new // If not active, skip processing + + /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ + + STR r5, [r1, #24] // Save current time-slice + + /* Clear the global time-slice. */ + + MOVW r5, #0 // Build clear value + STR r5, [r4] // Clear time-slice + + /* Executing thread is now completely preserved!!! */ + +__tx_ts_new: + + /* Now we are looking for a new thread to execute! */ + + CPSID i // Disable interrupts + LDR r1, [r2] // Is there another thread ready to execute? + CBZ r1, __tx_ts_wait // No, skip to the wait processing + + /* Yes, another thread is ready for else, make the current thread the new thread. */ + + STR r1, [r0] // Setup the current thread pointer to the new thread + CPSIE i // Enable interrupts + + /* Increment the thread run count. */ + +__tx_ts_restore: + LDR r7, [r1, #4] // Pickup the current thread run count + MOVW r4, #:lower16:_tx_timer_time_slice // Build address of time-slice variable + MOVT r4, #:upper16:_tx_timer_time_slice + LDR r5, [r1, #24] // Pickup thread's current time-slice + ADDS r7, r7, #1 // Increment the thread run count + STR r7, [r1, #4] // Store the new run count + + /* Setup global time-slice with thread's current time-slice. */ + + STR r5, [r4] // Setup global time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + /* Call the thread entry function to indicate the thread is executing. */ + PUSH {r0, r1} // Save r0/r1 + BL _tx_execution_thread_enter // Call the thread execution enter function + POP {r0, r1} // Recover r0/r1 +#endif + +#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) + // Restore secure context + LDR r5, =0x90 // Secure stack index offset + LDR r0, [r1, r5] // Load secure stack index + CBZ r0, _skip_secure_restore // Skip restore if there is no secure context + PUSH {r0, r1} // Save r1 (and dummy r0) + MOV r0, r1 // Move thread ptr to r0 + BL _tx_thread_secure_stack_context_restore // Restore secure stack + POP {r0, r1} // Restore r1 (and dummy r0) +_skip_secure_restore: +#endif + + /* Restore the thread context and PSP. */ +#ifdef TX_SINGLE_MODE_SECURE + // There are only stack limit registers in secure mode on the M23 + LDR r3, [r1, #12] // Get stack start + MSR PSPLIM, r3 // Set stack limit +#endif + LDR r3, [r1, #8] // Pickup thread's stack pointer + LDR r5, [r3] // Recover saved LR + ADDS r3, r3, #4 // Position past LR + MOV lr, r5 // Restore LR + LDM r3!, {r4-r7} // Recover thread's registers (r4-r11) + MOV r11, r7 // + MOV r10, r6 // + MOV r9, r5 // + MOV r8, r4 // + LDM r3!, {r4-r7} // + MSR PSP, r3 // Setup the thread's stack pointer + + /* Return to thread. */ + BX lr // Return to thread! + + /* The following is the idle wait processing... in this case, no threads are ready for execution and the + system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts + are disabled to allow use of WFI for waiting for a thread to arrive. */ + +__tx_ts_wait: + CPSID i // Disable interrupts + LDR r1, [r2] // Pickup the next thread to execute pointer + STR r1, [r0] // Store it in the current pointer + CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! +#ifdef TX_ENABLE_WFI + DSB // Ensure no outstanding memory transactions + WFI // Wait for interrupt + ISB // Ensure pipeline is flushed +#endif + CPSIE i // Enable interrupts + B __tx_ts_wait // Loop to continue waiting + + /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are + already in the handler! */ + +__tx_ts_ready: + LDR r7, =0x08000000 // Build clear PendSV value + LDR r5, =0xE000ED04 // Build ICSR address + STR r7, [r5] // Clear any PendSV + + /* Re-enable interrupts and restore new thread. */ + CPSIE i // Enable interrupts + B __tx_ts_restore // Restore the thread + + +#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) + // SVC_Handler is not needed when ThreadX is running in single mode. + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global SVC_Handler + .thumb_func +.type SVC_Handler, function +SVC_Handler: + MOVW r0, #4 + MOV r1, lr + TST r1, r0 // Determine return stack from EXC_RETURN bit 2 + BEQ _tx_get_msp + MRS r0, PSP // Get PSP if return stack is PSP + B _tx_got_sp +_tx_get_msp: + MRS r0, MSP // Get MSP if return stack is MSP +_tx_got_sp: + LDR r1, [r0, #24] // Load saved PC from stack + SUBS r1, r1, #2 // Calculate SVC number address + LDRB r1, [r1] // Load SVC number + + CMP r1, #1 // Is it a secure stack allocate request? + BEQ _tx_svc_secure_alloc // Yes, go there + + CMP r1, #2 // Is it a secure stack free request? + BEQ _tx_svc_secure_free // Yes, go there + + // Unknown SVC argument - just return + BX lr + +_tx_svc_secure_alloc: + PUSH {r0, lr} // Save SP and EXC_RETURN + LDM r0, {r0-r3} // Load function parameters from stack + BL _tx_thread_secure_mode_stack_allocate + POP {r1, r2} // Restore SP and EXC_RETURN + STR r0, [r1] // Store function return value + MOV lr, r2 + BX lr +_tx_svc_secure_free: + PUSH {r0, lr} // Save SP and EXC_RETURN + LDM r0, {r0-r3} // Load function parameters from stack + BL _tx_thread_secure_mode_stack_free + POP {r1, r2} // Restore SP and EXC_RETURN + STR r0, [r1] // Store function return value + MOV lr, r2 + BX lr +#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE + +.end diff --git a/ports/cortex_m23/ac6/src/tx_thread_secure_stack.c b/ports/cortex_m23/ac6/src/tx_thread_secure_stack.c new file mode 100644 index 00000000..0a48556e --- /dev/null +++ b/ports/cortex_m23/ac6/src/tx_thread_secure_stack.c @@ -0,0 +1,467 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +#include "tx_api.h" + +/* If TX_SINGLE_MODE_SECURE or TX_SINGLE_MODE_NON_SECURE is defined, + no secure stack functionality is needed. */ +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + +#define TX_SOURCE_CODE + +#include "ARMCM23_TZ.h" /* For intrinsic functions. */ +#include "tx_secure_interface.h" /* Interface for NS code. */ + +/* Minimum size of secure stack. */ +#ifndef TX_THREAD_SECURE_STACK_MINIMUM +#define TX_THREAD_SECURE_STACK_MINIMUM 256 +#endif +/* Maximum size of secure stack. */ +#ifndef TX_THREAD_SECURE_STACK_MAXIMUM +#define TX_THREAD_SECURE_STACK_MAXIMUM 1024 +#endif + +/* Secure stack info struct to hold stack start, stack limit, + current stack pointer, and pointer to owning thread. + This will be allocated for each thread with a secure stack. */ +typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT +{ + VOID *tx_thread_secure_stack_ptr; /* Thread's secure stack current pointer */ + VOID *tx_thread_secure_stack_start; /* Thread's secure stack start address */ + VOID *tx_thread_secure_stack_limit; /* Thread's secure stack limit */ + TX_THREAD *tx_thread_ptr; /* Keep track of thread for error handling */ +} TX_THREAD_SECURE_STACK_INFO; + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_initialize Cortex-M23/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes secure mode to use PSP stack. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __get_CONTROL Intrinsic to get CONTROL */ +/* __set_CONTROL Intrinsic to set CONTROL */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +void _tx_thread_secure_stack_initialize(void) +{ + + /* Set secure mode to use PSP. */ + __set_CONTROL(__get_CONTROL() | 2); + + /* Set process stack pointer and stack limit to 0 to throw exception when a thread + without a secure stack calls a secure function that tries to use secure stack. */ + __set_PSPLIM(0); + __set_PSP(0); + + return; +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_mode_stack_allocate Cortex-M23/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function allocates a thread's secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* stack_size Size of stack to allocates */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_SIZE_ERROR Invalid stack size */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* calloc Compiler's calloc function */ +/* malloc Compiler's malloc function */ +/* free Compiler's free() function */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* __TZ_get_PSPLIM_NS Intrinsic to get NS PSP */ +/* */ +/* CALLED BY */ +/* */ +/* SVC Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +{ +UINT status; +TX_THREAD_SECURE_STACK_INFO *info_ptr; +UCHAR *stack_mem; +ULONG sp; + + status = TX_SUCCESS; + + /* Make sure function is called from interrupt (threads should not call). */ + if (__get_IPSR() == 0) + { + status = TX_CALLER_ERROR; + } + else if (stack_size < TX_THREAD_SECURE_STACK_MINIMUM || stack_size > TX_THREAD_SECURE_STACK_MAXIMUM) + { + status = TX_SIZE_ERROR; + } + + /* Check if thread already has secure stack allocated. */ + else if (thread_ptr -> tx_thread_secure_stack_context != 0) + { + status = TX_THREAD_ERROR; + } + + else + { + /* Allocate space for secure stack info. */ + info_ptr = calloc(1, sizeof(TX_THREAD_SECURE_STACK_INFO)); + + if(info_ptr != TX_NULL) + { + /* If stack info allocated, allocate a stack. */ + stack_mem = malloc(stack_size); + + if(stack_mem != TX_NULL) + { + /* Secure stack has been allocated, save in the stack info struct. */ + info_ptr -> tx_thread_secure_stack_limit = stack_mem; + info_ptr -> tx_thread_secure_stack_start = stack_mem + stack_size; + info_ptr -> tx_thread_secure_stack_ptr = info_ptr -> tx_thread_secure_stack_start; + info_ptr -> tx_thread_ptr = thread_ptr; + + /* Save info pointer in thread. */ + thread_ptr -> tx_thread_secure_stack_context = info_ptr; + + /* Check if this thread is running by looking at PSP_NS and seeing if it is within + the stack_start and stack_end range. */ + sp = __TZ_get_PSP_NS(); + if(sp > ((ULONG) thread_ptr -> tx_thread_stack_start) && sp < ((ULONG) thread_ptr -> tx_thread_stack_end)) + { + /* If this thread is running, set Secure PSP and PSPLIM. */ + __set_PSPLIM((ULONG)(info_ptr -> tx_thread_secure_stack_limit)); + __set_PSP((ULONG)(info_ptr -> tx_thread_secure_stack_ptr)); + } + } + + else + { + /* Stack not allocated, free the info struct. */ + free(info_ptr); + status = TX_NO_MEMORY; + } + } + + else + { + status = TX_NO_MEMORY; + } + } + + return(status); +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_mode_stack_free Cortex-M23/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function frees a thread's secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* free Compiler's free() function */ +/* */ +/* CALLED BY */ +/* */ +/* SVC Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr) +{ +UINT status; +TX_THREAD_SECURE_STACK_INFO *info_ptr; + + status = TX_SUCCESS; + + /* Pickup stack info from thread. */ + info_ptr = thread_ptr -> tx_thread_secure_stack_context; + + /* Make sure function is called from interrupt (threads should not call). */ + if (__get_IPSR() == 0) + { + status = TX_CALLER_ERROR; + } + + /* Check that this secure context is for this thread. */ + else if (info_ptr -> tx_thread_ptr != thread_ptr) + { + status = TX_THREAD_ERROR; + } + + else + { + + /* Free secure stack. */ + free(info_ptr -> tx_thread_secure_stack_limit); + + /* Free info struct. */ + free(info_ptr); + + /* Clear secure context from thread. */ + thread_ptr -> tx_thread_secure_stack_context = 0; + } + + return(status); +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_context_save Cortex-M23/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves context of the secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* __get_PSP Intrinsic to get PSP */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* */ +/* CALLED BY */ +/* */ +/* PendSV Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr) +{ +TX_THREAD_SECURE_STACK_INFO *info_ptr; +ULONG sp; + + /* This function should be called from scheduler only. */ + if (__get_IPSR() == 0) + { + return; + } + + /* Pickup the secure context pointer. */ + info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); + + /* Check that this secure context is for this thread. */ + if (info_ptr -> tx_thread_ptr != thread_ptr) + { + return; + } + + /* Check that stack pointer is in range */ + sp = __get_PSP(); + if ((sp < (ULONG)info_ptr -> tx_thread_secure_stack_limit) || + (sp > (ULONG)info_ptr -> tx_thread_secure_stack_start)) + { + return; + } + + /* Save stack pointer. */ + *(ULONG *) info_ptr -> tx_thread_secure_stack_ptr = sp; + + /* Set process stack pointer and stack limit to 0 to throw exception when a thread + without a secure stack calls a secure function that tries to use secure stack. */ + __set_PSPLIM(0); + __set_PSP(0); + + return; +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_context_restore Cortex-M23/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores context of the secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* */ +/* CALLED BY */ +/* */ +/* PendSV Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr) +{ +TX_THREAD_SECURE_STACK_INFO *info_ptr; + + /* This function should be called from scheduler only. */ + if (__get_IPSR() == 0) + { + return; + } + + /* Pickup the secure context pointer. */ + info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); + + /* Check that this secure context is for this thread. */ + if (info_ptr -> tx_thread_ptr != thread_ptr) + { + return; + } + + /* Set stack pointer and limit. */ + __set_PSPLIM((ULONG)info_ptr -> tx_thread_secure_stack_limit); + __set_PSP ((ULONG)info_ptr -> tx_thread_secure_stack_ptr); + + return; +} + +#endif diff --git a/ports/cortex_m23/ac6/src/tx_thread_secure_stack_allocate.s b/ports/cortex_m23/ac6/src/tx_thread_secure_stack_allocate.s new file mode 100644 index 00000000..8abd3686 --- /dev/null +++ b/ports/cortex_m23/ac6/src/tx_thread_secure_stack_allocate.s @@ -0,0 +1,86 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_allocate Cortex-M23/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function enters the SVC handler to allocate a secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* stack_size Size of secure stack to */ +/* allocate */ +/* */ +/* OUTPUT */ +/* */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* SVC 1 */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_secure_stack_allocate + .thumb_func +.type _tx_thread_secure_stack_allocate, function +_tx_thread_secure_stack_allocate: +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + MRS r3, PRIMASK // Save interrupt mask + CPSIE i // Enable interrupts for SVC call + SVC 1 + CMP r3, #0 // If interrupts enabled, just return + BEQ _alloc_return_interrupt_enabled + CPSID i // Otherwise, disable interrupts +#else + // Executing in single mode - this function is not needed. + MOVS r0, #0xFF // Feature not enabled +#endif +_alloc_return_interrupt_enabled: + BX lr + .end diff --git a/ports/cortex_m23/ac6/src/tx_thread_secure_stack_free.s b/ports/cortex_m23/ac6/src/tx_thread_secure_stack_free.s new file mode 100644 index 00000000..b142c5da --- /dev/null +++ b/ports/cortex_m23/ac6/src/tx_thread_secure_stack_free.s @@ -0,0 +1,84 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_free Cortex-M23/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function enters the SVC handler to free a secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* SVC 2 */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_secure_stack_free + .thumb_func +.type _tx_thread_secure_stack_free, function +_tx_thread_secure_stack_free: +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + MRS r3, PRIMASK // Save interrupt mask + CPSIE i // Enable interrupts for SVC call + SVC 2 + CMP r3, #0 // If interrupts enabled, just return + BEQ _free_return_interrupt_enabled + CPSID i // Otherwise, disable interrupts +#else + // Executing in single mode - this function is not needed. + MOVS r0, #0xFF // Feature not enabled +#endif +_free_return_interrupt_enabled: + BX lr + .end diff --git a/ports/cortex_m23/ac6/src/tx_thread_stack_build.s b/ports/cortex_m23/ac6/src/tx_thread_stack_build.s new file mode 100644 index 00000000..5a95a14f --- /dev/null +++ b/ports/cortex_m23/ac6/src/tx_thread_stack_build.s @@ -0,0 +1,141 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build Cortex-M23/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_stack_build + .thumb_func +.type _tx_thread_stack_build, function +_tx_thread_stack_build: + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-M23 should look like the following after it is built: + + Stack Top: + LR Interrupted LR (LR at time of PENDSV) + r8 Initial value for r8 + r9 Initial value for r9 + r10 Initial value for r10 + r11 Initial value for r11 + r4 Initial value for r4 + r5 Initial value for r5 + r6 Initial value for r6 + r7 Initial value for r7 + r0 Initial value for r0 (Hardware stack starts here!!) + r1 Initial value for r1 + r2 Initial value for r2 + r3 Initial value for r3 + r12 Initial value for r12 + lr Initial value for lr + pc Initial value for pc + xPSR Initial value for xPSR + + Stack Bottom: (higher memory address) */ + + LDR r2, [r0, #16] // Pickup end of stack area + MOVW r3, #0x7 // + BICS r2, r2, r3 // Align frame for 8-byte alignment + SUBS r2, r2, #68 // Subtract frame size +#ifdef TX_SINGLE_MODE_SECURE + LDR r3, =0xFFFFFFFD // Build initial LR value for secure mode +#else + LDR r3, =0xFFFFFFBC // Build initial LR value to return to non-secure PSP +#endif + STR r3, [r2, #0] // Save on the stack + + /* Actually build the stack frame. */ + + MOVW r3, #0 // Build initial register value + STR r3, [r2, #4] // Store initial r8 + STR r3, [r2, #8] // Store initial r9 + STR r3, [r2, #12] // Store initial r10 + STR r3, [r2, #16] // Store initial r11 + STR r3, [r2, #20] // Store initial r4 + STR r3, [r2, #24] // Store initial r5 + STR r3, [r2, #28] // Store initial r6 + STR r3, [r2, #32] // Store initial r7 + + /* Hardware stack follows. */ + + STR r3, [r2, #36] // Store initial r0 + STR r3, [r2, #40] // Store initial r1 + STR r3, [r2, #44] // Store initial r2 + STR r3, [r2, #48] // Store initial r3 + STR r3, [r2, #52] // Store initial r12 + LDR r3, =0xFFFFFFFF // Poison EXC_RETURN value + STR r3, [r2, #56] // Store initial lr + STR r1, [r2, #60] // Store initial pc + LDR r3, =0x01000000 // Only T-bit need be set + STR r3, [r2, #64] // Store initial xPSR + + /* Setup stack pointer. */ + // thread_ptr -> tx_thread_stack_ptr = r2; + + STR r2, [r0, #8] // Save stack pointer in thread's + // control block + BX lr // Return to caller +// } + .end diff --git a/ports/cortex_m23/ac6/src/tx_thread_stack_error_handler.c b/ports/cortex_m23/ac6/src/tx_thread_stack_error_handler.c new file mode 100644 index 00000000..ef98240c --- /dev/null +++ b/ports/cortex_m23/ac6/src/tx_thread_stack_error_handler.c @@ -0,0 +1,93 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + +/* Define the global function pointer for stack error handling. If a stack error is + detected and the application has registered a stack error handler, it will be + called via this function pointer. */ + +VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_error_handler Cortex-M23 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes stack errors detected during run-time. */ +/* */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_terminate */ +/* _tx_thread_application_stack_error_handler */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX internal code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) +{ + #ifndef TX_THREAD_NO_TERMINATE_STACK_ERROR + /* Is there a thread? */ + if (thread_ptr) + { + /* Terminate the current thread. */ + _tx_thread_terminate(_tx_thread_current_ptr); + } + #endif + + /* Determine if the application has registered an error handler. */ + if (_tx_thread_application_stack_error_handler != TX_NULL) + { + /* Yes, an error handler is present, simply call the application error handler. */ + (_tx_thread_application_stack_error_handler)(thread_ptr); + } +} diff --git a/ports/cortex_m23/ac6/src/tx_thread_stack_error_notify.c b/ports/cortex_m23/ac6/src/tx_thread_stack_error_notify.c new file mode 100644 index 00000000..ffd78d08 --- /dev/null +++ b/ports/cortex_m23/ac6/src/tx_thread_stack_error_notify.c @@ -0,0 +1,96 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_trace.h" + +extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_error_notify Cortex-M23 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application stack error handler. If */ +/* ThreadX detects a stack error, this application handler is called. */ +/* */ +/* */ +/* INPUT */ +/* */ +/* stack_error_handler Pointer to stack error */ +/* handler, TX_NULL to disable */ +/* */ +/* OUTPUT */ +/* */ +/* status Service return status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr)) +{ + +TX_INTERRUPT_SAVE_AREA + + /* Disable interrupts. */ + TX_DISABLE + + /* Make entry in event log. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_STACK_ERROR_NOTIFY, 0, 0, 0, 0, TX_TRACE_THREAD_EVENTS) + + /* Make entry in event log. */ + TX_EL_THREAD_STACK_ERROR_NOTIFY_INSERT + + /* Setup global thread stack error handler. */ + _tx_thread_application_stack_error_handler = stack_error_handler; + + /* Restore interrupts. */ + TX_RESTORE + + /* Return success to caller. */ + return(TX_SUCCESS); +} diff --git a/ports/cortex_m23/ac6/src/tx_thread_system_return.s b/ports/cortex_m23/ac6/src/tx_thread_system_return.s new file mode 100644 index 00000000..175a9109 --- /dev/null +++ b/ports/cortex_m23/ac6/src/tx_thread_system_return.s @@ -0,0 +1,89 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return Cortex-M23/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the ThreadX system. Only a */ +/* minimal context is saved since the compiler assumes temp registers */ +/* are going to get slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_system_return(VOID) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_system_return + .thumb_func +.type _tx_thread_system_return, function +_tx_thread_system_return: + /* Return to real scheduler via PendSV. Note that this routine is often + replaced with in-line assembly in tx_port.h to improved performance. */ + + LDR r0, =0x10000000 // Load PENDSVSET bit + LDR r1, =0xE000ED04 // Load ICSR address + STR r0, [r1] // Set PENDSVBIT in ICSR + MRS r0, IPSR // Pickup IPSR + CMP r0, #0 // Is it a thread returning? + BNE _isr_context // If ISR, skip interrupt enable + MRS r1, PRIMASK // Thread context returning, pickup PRIMASK + CPSIE i // Enable interrupts + MSR PRIMASK, r1 // Restore original interrupt posture +_isr_context: + BX lr // Return to caller +// } + .end diff --git a/ports/cortex_m23/ac6/src/tx_timer_interrupt.s b/ports/cortex_m23/ac6/src/tx_timer_interrupt.s new file mode 100644 index 00000000..fdfcdcc5 --- /dev/null +++ b/ports/cortex_m23/ac6/src/tx_timer_interrupt.s @@ -0,0 +1,262 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt Cortex-M23/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_timer_interrupt(VOID) +{ */ + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_timer_interrupt + .thumb_func +.type _tx_timer_interrupt, function +_tx_timer_interrupt: + + /* Upon entry to this routine, it is assumed that the compiler scratch registers are available + for use. */ + + /* Increment the system clock. */ + // _tx_timer_system_clock++; + + MOVW r1, #:lower16:_tx_timer_system_clock // Pickup address of system clock + MOVT r1, #:upper16:_tx_timer_system_clock + LDR r0, [r1, #0] // Pickup system clock + ADDS r0, r0, #1 // Increment system clock + STR r0, [r1, #0] // Store new system clock + + /* Test for time-slice expiration. */ + // if (_tx_timer_time_slice) + // { + + MOVW r3, #:lower16:_tx_timer_time_slice // Pickup address of time-slice + MOVT r3, #:upper16:_tx_timer_time_slice + LDR r2, [r3, #0] // Pickup time-slice + CBZ r2, __tx_timer_no_time_slice // Is it non-active? + // Yes, skip time-slice processing + + /* Decrement the time_slice. */ + // _tx_timer_time_slice--; + + SUBS r2, r2, #1 // Decrement the time-slice + STR r2, [r3, #0] // Store new time-slice value + + /* Check for expiration. */ + // if (__tx_timer_time_slice == 0) + + CBNZ r2, __tx_timer_no_time_slice // Has it expired? + + /* Set the time-slice expired flag. */ + // _tx_timer_expired_time_slice = TX_TRUE; + + MOVW r3, #:lower16:_tx_timer_expired_time_slice // Pickup address of expired flag + MOVT r3, #:upper16:_tx_timer_expired_time_slice + MOVW r0, #1 // Build expired value + STR r0, [r3, #0] // Set time-slice expiration flag + + // } + +__tx_timer_no_time_slice: + + /* Test for timer expiration. */ + // if (*_tx_timer_current_ptr) + // { + + MOVW r1, #:lower16:_tx_timer_current_ptr // Pickup current timer pointer address + MOVT r1, #:upper16:_tx_timer_current_ptr + LDR r0, [r1, #0] // Pickup current timer + LDR r2, [r0, #0] // Pickup timer list entry + CBZ r2, __tx_timer_no_timer // Is there anything in the list? + // No, just increment the timer + + /* Set expiration flag. */ + // _tx_timer_expired = TX_TRUE; + + MOVW r3, #:lower16:_tx_timer_expired // Pickup expiration flag address + MOVT r3, #:upper16:_tx_timer_expired + MOVW r2, #1 // Build expired value + STR r2, [r3, #0] // Set expired flag + B __tx_timer_done // Finished timer processing + + // } + // else + // { +__tx_timer_no_timer: + + /* No timer expired, increment the timer pointer. */ + // _tx_timer_current_ptr++; + + ADDS r0, r0, #4 // Move to next timer + + /* Check for wrap-around. */ + // if (_tx_timer_current_ptr == _tx_timer_list_end) + + MOVW r3, #:lower16:_tx_timer_list_end // Pickup addr of timer list end + MOVT r3, #:upper16:_tx_timer_list_end + LDR r2, [r3, #0] // Pickup list end + CMP r0, r2 // Are we at list end? + BNE __tx_timer_skip_wrap // No, skip wrap-around logic + + /* Wrap to beginning of list. */ + // _tx_timer_current_ptr = _tx_timer_list_start; + + MOVW r3, #:lower16:_tx_timer_list_start // Pickup addr of timer list start + MOVT r3, #:upper16:_tx_timer_list_start + LDR r0, [r3, #0] // Set current pointer to list start + +__tx_timer_skip_wrap: + + STR r0, [r1, #0] // Store new current timer pointer + // } + +__tx_timer_done: + + + /* See if anything has expired. */ + // if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) + // { + + MOVW r3, #:lower16:_tx_timer_expired_time_slice // Pickup addr of expired flag + MOVT r3, #:upper16:_tx_timer_expired_time_slice + LDR r2, [r3, #0] // Pickup time-slice expired flag + CBNZ r2, __tx_something_expired // Did a time-slice expire? + // If non-zero, time-slice expired + MOVW r1, #:lower16:_tx_timer_expired // Pickup addr of other expired flag + MOVT r1, #:upper16:_tx_timer_expired + LDR r0, [r1, #0] // Pickup timer expired flag + CBZ r0, __tx_timer_nothing_expired // Did a timer expire? + // No, nothing expired + +__tx_something_expired: + + PUSH {r0, lr} // Save the lr register on the stack + // and save r0 just to keep 8-byte alignment + + /* Did a timer expire? */ + // if (_tx_timer_expired) + // { + + MOVW r1, #:lower16:_tx_timer_expired // Pickup addr of expired flag + MOVT r1, #:upper16:_tx_timer_expired + LDR r0, [r1, #0] // Pickup timer expired flag + CBZ r0, __tx_timer_dont_activate // Check for timer expiration + // If not set, skip timer activation + + /* Process timer expiration. */ + // _tx_timer_expiration_process(); + + BL _tx_timer_expiration_process // Call the timer expiration handling routine + + // } +__tx_timer_dont_activate: + + /* Did time slice expire? */ + // if (_tx_timer_expired_time_slice) + // { + + MOVW r3, #:lower16:_tx_timer_expired_time_slice // Pickup addr of time-slice expired + MOVT r3, #:upper16:_tx_timer_expired_time_slice + LDR r2, [r3, #0] // Pickup the actual flag + CBZ r2, __tx_timer_not_ts_expiration // See if the flag is set + // No, skip time-slice processing + + /* Time slice interrupted thread. */ + // _tx_thread_time_slice(); + + BL _tx_thread_time_slice // Call time-slice processing + MOVW r0, #:lower16:_tx_thread_preempt_disable // Build address of preempt disable flag + MOVT r0, #:upper16:_tx_thread_preempt_disable + + LDR r1, [r0] // Is the preempt disable flag set? + CBNZ r1, __tx_timer_skip_time_slice // Yes, skip the PendSV logic + MOVW r0, #:lower16:_tx_thread_current_ptr // Build current thread pointer address + MOVT r0, #:upper16:_tx_thread_current_ptr + + LDR r1, [r0] // Pickup the current thread pointer + MOVW r2, #:lower16:_tx_thread_execute_ptr // Build execute thread pointer address + MOVT r2, #:upper16:_tx_thread_execute_ptr + + LDR r3, [r2] // Pickup the execute thread pointer + LDR r0, =0xE000ED04 // Build address of control register + LDR r2, =0x10000000 // Build value for PendSV bit + CMP r1, r3 // Are they the same? + BEQ __tx_timer_skip_time_slice // If the same, there was no time-slice performed + STR r2, [r0] // Not the same, issue the PendSV for preemption +__tx_timer_skip_time_slice: + // } + +__tx_timer_not_ts_expiration: + + POP {r0, r1} // Recover lr register (r0 is just there for + MOV lr, r1 // the 8-byte stack alignment + + // } + +__tx_timer_nothing_expired: + + DSB // Complete all memory access + BX lr // Return to caller + +// } + .end diff --git a/ports/cortex_m23/ac6/src/txe_thread_secure_stack_allocate.c b/ports/cortex_m23/ac6/src/txe_thread_secure_stack_allocate.c new file mode 100644 index 00000000..35482b6c --- /dev/null +++ b/ports/cortex_m23/ac6/src/txe_thread_secure_stack_allocate.c @@ -0,0 +1,119 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_secure_stack_allocate Cortex-M23 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the secure stack allocate */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* stack_size Size of secure stack to */ +/* allocate */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_secure_stack_allocate Actual stack alloc function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +{ +#if defined(TX_SINGLE_MODE_SECURE) || defined(TX_SINGLE_MODE_NON_SECURE) + return(TX_FEATURE_NOT_ENABLED); +#else +UINT status; + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid thread pointer. */ + if (thread_ptr == TX_NULL) + { + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Now check for invalid thread ID. */ + else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) + { + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Check for interrupt call. */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + /* Is call from an interrupt and not initialization? */ + if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS) + { + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + /* Call actual secure stack allocate function. */ + status = _tx_thread_secure_stack_allocate(thread_ptr, stack_size); + } + + /* Return completion status. */ + return(status); +#endif +} diff --git a/ports/cortex_m23/ac6/src/txe_thread_secure_stack_free.c b/ports/cortex_m23/ac6/src/txe_thread_secure_stack_free.c new file mode 100644 index 00000000..950e8ec0 --- /dev/null +++ b/ports/cortex_m23/ac6/src/txe_thread_secure_stack_free.c @@ -0,0 +1,120 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_secure_stack_free Cortex-M23 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the secure stack free */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_secure_stack_free Actual stack free function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) +{ +#if defined(TX_SINGLE_MODE_SECURE) || defined(TX_SINGLE_MODE_NON_SECURE) + return(TX_FEATURE_NOT_ENABLED); +#else +UINT status; + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid thread pointer. */ + if (thread_ptr == TX_NULL) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Now check for invalid thread ID. */ + else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Check for interrupt call. */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + /* Is call from an interrupt and not initialization? */ + if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS) + { + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + + /* Call actual secure stack allocate function. */ + status = _tx_thread_secure_stack_free(thread_ptr); + } + + /* Return completion status. */ + return(status); +#endif +} diff --git a/ports/cortex_m23/gnu/inc/tx_port.h b/ports/cortex_m23/gnu/inc/tx_port.h new file mode 100644 index 00000000..69acde04 --- /dev/null +++ b/ports/cortex_m23/gnu/inc/tx_port.h @@ -0,0 +1,418 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-M23/GNU */ +/* 6.1 */ +/* */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + +/* Determine if the optional ThreadX user define file should be used. */ +#ifdef TX_INCLUDE_USER_DEFINE_FILE + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + +/* Define compiler library include files. */ + +#include +#include +#include +#include "ARMCM23_TZ.h" /* For intrinsic functions. */ + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef unsigned long long ULONG64; +typedef short SHORT; +typedef unsigned short USHORT; + +/* Function prototypes for this port. */ +struct TX_THREAD_STRUCT; +UINT _txe_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *thread_ptr, ULONG stack_size); +UINT _txe_thread_secure_stack_free(struct TX_THREAD_STRUCT *thread_ptr); +UINT _tx_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *tx_thread, ULONG stack_size); +UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); + +/* This hardware has stack checking that we take advantage of - do NOT define. */ +#ifdef TX_ENABLE_STACK_CHECKING + #error "Do not define TX_ENABLE_STACK_CHECKING" +#endif + +/* If user does not want to terminate thread on stack overflow, + #define the TX_THREAD_NO_TERMINATE_STACK_ERROR symbol. + The thread will be rescheduled and continue to cause the exception. + It is suggested user code handle this by registering a notification with the + tx_thread_stack_error_notify function. */ +/*#define TX_THREAD_NO_TERMINATE_STACK_ERROR */ + +/* Define the system API mappings based on the error checking + selected by the user. Note: this section is only applicable to + application source code, hence the conditional that turns off this + stuff when the include file is processed by the ThreadX source. */ + +#ifndef TX_SOURCE_CODE + + +/* Determine if error checking is desired. If so, map API functions + to the appropriate error checking front-ends. Otherwise, map API + functions to the core functions that actually perform the work. + Note: error checking is enabled by default. */ + +#ifdef TX_DISABLE_ERROR_CHECKING + +/* Services without error checking. */ + +#define tx_thread_secure_stack_allocate _tx_thread_secure_stack_allocate +#define tx_thread_secure_stack_free _tx_thread_secure_stack_free + +#else + +/* Services with error checking. */ + +#define tx_thread_secure_stack_allocate _txe_thread_secure_stack_allocate +#define tx_thread_secure_stack_free _txe_thread_secure_stack_free + +#endif +#endif + + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX Cortex-M23 port. */ + +#define TX_INT_DISABLE 1 /* Disable interrupts */ +#define TX_INT_ENABLE 0 /* Enable interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) +#endif +#else +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif + +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_secure_stack_context; +#else +#define TX_THREAD_EXTENSION_2 +#endif +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) if(thread_ptr -> tx_thread_secure_stack_context){_tx_thread_secure_stack_free(thread_ptr);} +#else +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +/* Define the size of the secure stack for the timer thread and use the extension to allocate the secure stack. */ +#define TX_TIMER_THREAD_SECURE_STACK_SIZE 256 +#define TX_TIMER_INITIALIZE_EXTENSION(status) _tx_thread_secure_stack_allocate(&_tx_timer_thread, TX_TIMER_THREAD_SECURE_STACK_SIZE); +#endif + + +#ifndef TX_MISRA_ENABLE + +//register unsigned int _ipsr __asm ("MRS %[result], ipsr" : [result] "=r" (_ipsr) : ); +inline static unsigned int _get_ipsr(void); +inline static unsigned int _get_ipsr(void) +{ + unsigned int _ipsr; + __asm("MRS %[result], ipsr" : [result] "=r" (_ipsr) : ); + return _ipsr; +} + +#endif + + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define the get system state macro. */ + +#ifndef TX_THREAD_GET_SYSTEM_STATE +#ifndef TX_MISRA_ENABLE +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _get_ipsr()) +#else +ULONG _tx_misra_ipsr_get(VOID); +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get()) +#endif +#endif + + +/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value + indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h + for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always + zero after initialization for Cortex-M ports. */ + +#ifndef TX_THREAD_SYSTEM_RETURN_CHECK +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#endif + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +/* Initialize secure stacks for threads calling secure functions. */ +extern void _tx_thread_secure_stack_initialize(void); +#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION _tx_thread_secure_stack_initialize(); +#endif + +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to + prevent early scheduling on Cortex-M parts. */ + +#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); + +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifdef TX_DISABLE_INLINE + +UINT _tx_thread_interrupt_disable(VOID); +VOID _tx_thread_interrupt_restore(UINT previous_posture); + +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); + +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA unsigned int was_masked; +#define TX_DISABLE was_masked = __disable_irq(); +#define TX_RESTORE if (was_masked == 0) __enable_irq(); + +#define _tx_thread_system_return _tx_thread_system_return_inline + + +static void _tx_thread_system_return_inline(void) +{ +unsigned int was_masked; + + + /* Set PendSV to invoke ThreadX scheduler. */ + *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + if (_get_ipsr() == 0) + { + was_masked = __disable_irq(); + __enable_irq(); + if (was_masked != 0) + __disable_irq(); + } +} +#endif + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/GNU Version 6.1 *"; +#else +#ifdef TX_MISRA_ENABLE +extern CHAR _tx_version_id[100]; +#else +extern CHAR _tx_version_id[]; +#endif +#endif + +#endif diff --git a/ports/cortex_m23/gnu/inc/tx_secure_interface.h b/ports/cortex_m23/gnu/inc/tx_secure_interface.h new file mode 100644 index 00000000..976f32be --- /dev/null +++ b/ports/cortex_m23/gnu/inc/tx_secure_interface.h @@ -0,0 +1,60 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* tx_secure_interface.h Cortex-M23 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the ThreadX secure thread stack components, */ +/* including data types and external references. */ +/* It is assumed that tx_api.h and tx_port.h have already been */ +/* included. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_SECURE_INTERFACE_H +#define TX_SECURE_INTERFACE_H + +/* Define internal secure thread stack function prototypes. */ + +extern void _tx_thread_secure_stack_initialize(void); +extern UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size); +extern UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr); +extern void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr); +extern void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr); + +#endif diff --git a/ports/cortex_m23/gnu/readme_threadx.txt b/ports/cortex_m23/gnu/readme_threadx.txt new file mode 100644 index 00000000..fa581684 --- /dev/null +++ b/ports/cortex_m23/gnu/readme_threadx.txt @@ -0,0 +1,137 @@ + Microsoft's Azure RTOS ThreadX for Cortex-M23 + + Using the GNU Tools + + +1. Building the ThreadX run-time Library + + + + +2. Demonstration System + + + + +3. System Initialization + +The entry point in ThreadX for the Cortex-M23 using gnu tools uses the standard GNU +Cortex-M23 reset sequence. From the reset vector the C runtime will be initialized. + +The ThreadX tx_initialize_low_level.S file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. + +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input +parameter to your application definition function, tx_application_define. + + +4. Register Usage and Stack Frames + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have the same stack frame in the Cortex-M23 version of +ThreadX. The top of the suspended thread's stack is pointed to by +tx_thread_stack_ptr in the associated thread control block TX_THREAD. + + + Stack Offset Stack Contents + + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 r8 + 0x08 r9 + 0x0C r10 + 0x10 r11 + 0x14 r4 + 0x18 r5 + 0x1C r6 + 0x20 r7 + 0x24 r0 (Hardware stack starts here!!) + 0x28 r1 + 0x2C r2 + 0x30 r3 + 0x34 r12 + 0x38 lr + 0x3C pc + 0x40 xPSR + + +5. Improving Performance + +To make ThreadX and the application(s) run faster, you can enable +all compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +6. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-M23 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +6.1 Vector Area + +The Cortex-M23 vectors start at the label __tx_vectors or similar. The application may modify +the vector area according to its needs. There is code in tx_initialize_low_level() that will +configure the vector base register. + + +6.2 Managed Interrupts + +ISRs can be written completely in C (or assembly language) without any calls to +_tx_thread_context_save or _tx_thread_context_restore. These ISRs are allowed access to the +ThreadX API that is available to ISRs. + +ISRs written in C will take the form (where "your_C_isr" is an entry in the vector table): + +void your_C_isr(void) +{ + + /* ISR processing goes here, including any needed function calls. */ +} + +ISRs written in assembly language will take the form: + + + .global your_assembly_isr + .thumb_func +your_assembly_isr: +; VOID your_assembly_isr(VOID) +; { + PUSH {r0, lr} +; +; /* Do interrupt handler work here */ +; /* BL */ + + POP {r0, r1} + MOV lr, r1 + BX lr +; } + + +Note: the Cortex-M23 requires exception handlers to be thumb labels, this implies bit 0 set. +To accomplish this, the declaration of the label has to be preceded by the assembler directive +.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to +be inserted in the correct location in the interrupt vector table. This table is typically +located in either your runtime startup file or in the tx_initialize_low_level.S file. + + +7. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +09-30-2020 Initial ThreadX 6.1 version for Cortex-M23 using GNU tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_m23/gnu/src/tx_initialize_low_level.S b/ports/cortex_m23/gnu/src/tx_initialize_low_level.S new file mode 100644 index 00000000..08b635c4 --- /dev/null +++ b/ports/cortex_m23/gnu/src/tx_initialize_low_level.S @@ -0,0 +1,210 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +SYSTEM_CLOCK = 6000000 +SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) + +/* Setup the stack and heap areas. */ + +STACK_SIZE = 0x00000400 +HEAP_SIZE = 0x00000000 + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-M23/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_initialize_low_level(VOID) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_initialize_low_level + .thumb_func +.type _tx_initialize_low_level, function +_tx_initialize_low_level: + + /* Disable interrupts during ThreadX initialization. */ + CPSID i + + /* Set base of available memory to end of non-initialised RAM area. */ + LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer + LDR r1, =Image$$ARM_LIB_STACK$$ZI$$Limit // Build first free address + ADDS r1, r1, #4 // + STR r1, [r0] // Setup first unused memory pointer + + /* Setup Vector Table Offset Register. */ + LDR r0, =0xE000ED08 // Build address of NVIC registers + LDR r1, =__Vectors // Pickup address of vector table + STR r1, [r0] // Set vector table address + +// /* Enable the cycle count register. */ +// +// LDR r0, =0xE0001000 // Build address of DWT register +// LDR r1, [r0] // Pickup the current value +// ORR r1, r1, #1 // Set the CYCCNTENA bit +// STR r1, [r0] // Enable the cycle count register + + /* Set system stack pointer from vector value. */ + LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer + LDR r1, =__Vectors // Pickup address of vector table + LDR r1, [r1] // Pickup reset stack pointer + STR r1, [r0] // Save system stack pointer + + /* Configure SysTick. */ + LDR r0, =0xE000E000 // Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] // Setup SysTick Reload Value + MOVW r1, #0x7 // Build SysTick Control Enable Value + STR r1, [r0, #0x10] // Setup SysTick Control + + /* Configure handler priorities. */ + LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM + LDR r0, =0xE000E000 // Build address of NVIC registers + LDR r2, =0xD18 // + ADD r0, r0, r2 // + STR r1, [r0] // Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv + LDR r0, =0xE000E000 // Build address of NVIC registers + LDR r2, =0xD1C // + ADD r0, r0, r2 // + STR r1, [r0] // Setup System Handlers 8-11 Priority Registers + // Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM + LDR r0, =0xE000E000 // Build address of NVIC registers + LDR r2, =0xD20 // + ADD r0, r0, r2 // + STR r1, [r0] // Setup System Handlers 12-15 Priority Registers + // Note: PnSV must be lowest priority, which is 0xFF + + /* Return to caller. */ + BX lr +// } + + +/* Define shells for each of the unused vectors. */ + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global __tx_BadHandler + .thumb_func +.type __tx_BadHandler, function +__tx_BadHandler: + B __tx_BadHandler + + + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global __tx_IntHandler + .thumb_func +.type __tx_IntHandler, function +__tx_IntHandler: +// VOID InterruptHandler (VOID) +// { + PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) + + /* Do interrupt handler work here */ + /* .... */ + + POP {r0, r1} + MOV lr, r1 + BX lr +// } + + + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global SysTick_Handler + .thumb_func +.type SysTick_Handler, function +SysTick_Handler: +// VOID TimerInterruptHandler (VOID) +// { + PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) + BL _tx_timer_interrupt + POP {r0, r1} + MOV lr, r1 + BX lr +// } + + + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global HardFault_Handler + .thumb_func +.type HardFault_Handler, function +HardFault_Handler: + // A stack overflow will trigger a hardfault. + // There is no CFSR in M23, so we will not try to + // determine if the fault is caused by a stack overflow + // or some other condition. + B HardFault_Handler + + .end diff --git a/ports/cortex_m23/gnu/src/tx_thread_context_restore.s b/ports/cortex_m23/gnu/src/tx_thread_context_restore.s new file mode 100644 index 00000000..14d772fb --- /dev/null +++ b/ports/cortex_m23/gnu/src/tx_thread_context_restore.s @@ -0,0 +1,74 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore Cortex-M23/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is not needed for Cortex-M. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* None */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_context_restore(VOID) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_context_restore + .thumb_func +.type _tx_thread_context_restore, function +_tx_thread_context_restore: + /* Return to interrupt processing. */ + BX lr +// } + .end diff --git a/ports/cortex_m23/gnu/src/tx_thread_context_save.s b/ports/cortex_m23/gnu/src/tx_thread_context_save.s new file mode 100644 index 00000000..25050678 --- /dev/null +++ b/ports/cortex_m23/gnu/src/tx_thread_context_save.s @@ -0,0 +1,74 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save Cortex-M23/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is not needed for Cortex-M. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* None */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_context_save(VOID) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_context_save + .thumb_func +.type _tx_thread_context_save, function +_tx_thread_context_save: + /* Return to interrupt processing. */ + BX lr +// } + .end diff --git a/ports/cortex_m23/gnu/src/tx_thread_interrupt_control.s b/ports/cortex_m23/gnu/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..4f05f3ff --- /dev/null +++ b/ports/cortex_m23/gnu/src/tx_thread_interrupt_control.s @@ -0,0 +1,78 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control Cortex-M23/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_interrupt_control(UINT new_posture) +// { + .section .text + .balign 4 + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_interrupt_control + .thumb_func +.type _tx_thread_interrupt_control, function +_tx_thread_interrupt_control: + + /* Pickup current interrupt lockout posture. */ + MRS r1, PRIMASK + MSR PRIMASK, r0 + MOV r0, r1 + BX lr +// } + .end diff --git a/ports/cortex_m23/gnu/src/tx_thread_interrupt_disable.s b/ports/cortex_m23/gnu/src/tx_thread_interrupt_disable.s new file mode 100644 index 00000000..3a1fc9f6 --- /dev/null +++ b/ports/cortex_m23/gnu/src/tx_thread_interrupt_disable.s @@ -0,0 +1,77 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_disable Cortex-M23/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for disabling interrupts and returning */ +/* the previous interrupt lockout posture. */ +/* */ +/* INPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_interrupt_disable(UINT new_posture) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_interrupt_disable + .thumb_func +.type _tx_thread_interrupt_disable, function +_tx_thread_interrupt_disable: + /* Return current interrupt lockout posture. */ + MRS r0, PRIMASK + CPSID i + BX lr +// } + .end diff --git a/ports/cortex_m23/gnu/src/tx_thread_interrupt_restore.s b/ports/cortex_m23/gnu/src/tx_thread_interrupt_restore.s new file mode 100644 index 00000000..696c227b --- /dev/null +++ b/ports/cortex_m23/gnu/src/tx_thread_interrupt_restore.s @@ -0,0 +1,76 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_restore Cortex-M23/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for restoring the previous */ +/* interrupt lockout posture. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* previous_posture Previous interrupt posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_interrupt_restore(UINT new_posture) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_interrupt_restore + .thumb_func +.type _tx_thread_interrupt_restore, function +_tx_thread_interrupt_restore: + /* Restore previous interrupt lockout posture. */ + MSR PRIMASK, r0 + BX lr +// } + .end diff --git a/ports/cortex_m23/gnu/src/tx_thread_schedule.s b/ports/cortex_m23/gnu/src/tx_thread_schedule.s new file mode 100644 index 00000000..9fefdb6e --- /dev/null +++ b/ports/cortex_m23/gnu/src/tx_thread_schedule.s @@ -0,0 +1,327 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule Cortex-M23/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_schedule(VOID) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_schedule + .thumb_func +.type _tx_thread_schedule, function +_tx_thread_schedule: + /* This function should only ever be called on Cortex-M + from the first schedule request. Subsequent scheduling occurs + from the PendSV handling routine below. */ + + /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ + MOVW r0, #0 // Build value for TX_FALSE + LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag + STR r0, [r2, #0] // Clear preempt disable flag + + /* Enable interrupts */ + CPSIE i + + /* Enter the scheduler for the first time. */ + + LDR r0, =0x10000000 // Load PENDSVSET bit + LDR r1, =0xE000ED04 // Load ICSR address + STR r0, [r1] // Set PENDSVBIT in ICSR + DSB // Complete all memory accesses + ISB // Flush pipeline + + /* Wait here for the PendSV to take place. */ + +__tx_wait_here: + B __tx_wait_here // Wait for the PendSV to happen +// } + + /* Generic context switching PendSV handler. */ + + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global PendSV_Handler + .thumb_func +.type PendSV_Handler, function + /* Get current thread value and new thread pointer. */ +PendSV_Handler: +__tx_ts_handler: + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + /* Call the thread exit function to indicate the thread is no longer executing. */ + CPSID i // Disable interrupts + PUSH {r0, lr} // Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit // Call the thread exit function + POP {r0, r1} // Recover LR + MOV lr, r1 + CPSIE i // Enable interrupts +#endif + + MOVW r0, #:lower16:_tx_thread_current_ptr // Build current thread pointer address + MOVT r0, #:upper16:_tx_thread_current_ptr + MOVW r2, #:lower16:_tx_thread_execute_ptr // Build execute thread pointer address + MOVT r2, #:upper16:_tx_thread_execute_ptr + MOVW r3, #0 // Build NULL value + LDR r1, [r0] // Pickup current thread pointer + + /* Determine if there is a current thread to finish preserving. */ + + CBZ r1, __tx_ts_new // If NULL, skip preservation + + /* Recover PSP and preserve current thread context. */ + + STR r3, [r0] // Set _tx_thread_current_ptr to NULL + MRS r3, PSP // Pickup PSP pointer (thread's stack pointer) + SUBS r3, r3, #16 // Allocate stack space + STM r3!, {r4-r7} // Save its remaining registers (M3 Instruction: STMDB r12!, {r4-r11}) + MOV r4, r8 // + MOV r5, r9 // + MOV r6, r10 // + MOV r7, r11 // + SUBS r3, r3, #32 // Allocate stack space + STM r3!, {r4-r7} // + SUBS r3, r3, #20 // Allocate stack space + MOV r5, lr // + STR r5, [r3] // Save LR on the stack + STR r3, [r1, #8] // Save the thread stack pointer + +#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) + // Save secure context + LDR r5, =0x90 // Secure stack index offset + LDR r5, [r1, r5] // Load secure stack index + CBZ r5, _skip_secure_save // Skip save if there is no secure context + PUSH {r0, r1, r2, r3} // Save scratch registers + MOV r0, r1 // Move thread ptr to r0 + BL _tx_thread_secure_stack_context_save // Save secure stack + POP {r0, r1, r2, r3} // Restore secure registers +_skip_secure_save: +#endif + + /* Determine if time-slice is active. If it isn't, skip time handling processing. */ + + LDR r4, =_tx_timer_time_slice // Build address of time-slice variable + LDR r5, [r4] // Pickup current time-slice + CBZ r5, __tx_ts_new // If not active, skip processing + + /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ + + STR r5, [r1, #24] // Save current time-slice + + /* Clear the global time-slice. */ + + MOVW r5, #0 // Build clear value + STR r5, [r4] // Clear time-slice + + /* Executing thread is now completely preserved!!! */ + +__tx_ts_new: + + /* Now we are looking for a new thread to execute! */ + + CPSID i // Disable interrupts + LDR r1, [r2] // Is there another thread ready to execute? + CBZ r1, __tx_ts_wait // No, skip to the wait processing + + /* Yes, another thread is ready for else, make the current thread the new thread. */ + + STR r1, [r0] // Setup the current thread pointer to the new thread + CPSIE i // Enable interrupts + + /* Increment the thread run count. */ + +__tx_ts_restore: + LDR r7, [r1, #4] // Pickup the current thread run count + MOVW r4, #:lower16:_tx_timer_time_slice // Build address of time-slice variable + MOVT r4, #:upper16:_tx_timer_time_slice + LDR r5, [r1, #24] // Pickup thread's current time-slice + ADDS r7, r7, #1 // Increment the thread run count + STR r7, [r1, #4] // Store the new run count + + /* Setup global time-slice with thread's current time-slice. */ + + STR r5, [r4] // Setup global time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + /* Call the thread entry function to indicate the thread is executing. */ + PUSH {r0, r1} // Save r0/r1 + BL _tx_execution_thread_enter // Call the thread execution enter function + POP {r0, r1} // Recover r0/r1 +#endif + +#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) + // Restore secure context + LDR r5, =0x90 // Secure stack index offset + LDR r0, [r1, r5] // Load secure stack index + CBZ r0, _skip_secure_restore // Skip restore if there is no secure context + PUSH {r0, r1} // Save r1 (and dummy r0) + MOV r0, r1 // Move thread ptr to r0 + BL _tx_thread_secure_stack_context_restore // Restore secure stack + POP {r0, r1} // Restore r1 (and dummy r0) +_skip_secure_restore: +#endif + + /* Restore the thread context and PSP. */ +#ifdef TX_SINGLE_MODE_SECURE + // There are only stack limit registers in secure mode on the M23 + LDR r3, [r1, #12] // Get stack start + MSR PSPLIM, r3 // Set stack limit +#endif + LDR r3, [r1, #8] // Pickup thread's stack pointer + LDR r5, [r3] // Recover saved LR + ADDS r3, r3, #4 // Position past LR + MOV lr, r5 // Restore LR + LDM r3!, {r4-r7} // Recover thread's registers (r4-r11) + MOV r11, r7 // + MOV r10, r6 // + MOV r9, r5 // + MOV r8, r4 // + LDM r3!, {r4-r7} // + MSR PSP, r3 // Setup the thread's stack pointer + + /* Return to thread. */ + BX lr // Return to thread! + + /* The following is the idle wait processing... in this case, no threads are ready for execution and the + system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts + are disabled to allow use of WFI for waiting for a thread to arrive. */ + +__tx_ts_wait: + CPSID i // Disable interrupts + LDR r1, [r2] // Pickup the next thread to execute pointer + STR r1, [r0] // Store it in the current pointer + CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! +#ifdef TX_ENABLE_WFI + DSB // Ensure no outstanding memory transactions + WFI // Wait for interrupt + ISB // Ensure pipeline is flushed +#endif + CPSIE i // Enable interrupts + B __tx_ts_wait // Loop to continue waiting + + /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are + already in the handler! */ + +__tx_ts_ready: + LDR r7, =0x08000000 // Build clear PendSV value + LDR r5, =0xE000ED04 // Build ICSR address + STR r7, [r5] // Clear any PendSV + + /* Re-enable interrupts and restore new thread. */ + CPSIE i // Enable interrupts + B __tx_ts_restore // Restore the thread + + +#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) + // SVC_Handler is not needed when ThreadX is running in single mode. + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global SVC_Handler + .thumb_func +.type SVC_Handler, function +SVC_Handler: + MOVW r0, #4 + MOV r1, lr + TST r1, r0 // Determine return stack from EXC_RETURN bit 2 + BEQ _tx_get_msp + MRS r0, PSP // Get PSP if return stack is PSP + B _tx_got_sp +_tx_get_msp: + MRS r0, MSP // Get MSP if return stack is MSP +_tx_got_sp: + LDR r1, [r0, #24] // Load saved PC from stack + SUBS r1, r1, #2 // Calculate SVC number address + LDRB r1, [r1] // Load SVC number + + CMP r1, #1 // Is it a secure stack allocate request? + BEQ _tx_svc_secure_alloc // Yes, go there + + CMP r1, #2 // Is it a secure stack free request? + BEQ _tx_svc_secure_free // Yes, go there + + // Unknown SVC argument - just return + BX lr + +_tx_svc_secure_alloc: + PUSH {r0, lr} // Save SP and EXC_RETURN + LDM r0, {r0-r3} // Load function parameters from stack + BL _tx_thread_secure_mode_stack_allocate + POP {r1, r2} // Restore SP and EXC_RETURN + STR r0, [r1] // Store function return value + MOV lr, r2 + BX lr +_tx_svc_secure_free: + PUSH {r0, lr} // Save SP and EXC_RETURN + LDM r0, {r0-r3} // Load function parameters from stack + BL _tx_thread_secure_mode_stack_free + POP {r1, r2} // Restore SP and EXC_RETURN + STR r0, [r1] // Store function return value + MOV lr, r2 + BX lr +#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE + +.end diff --git a/ports/cortex_m23/gnu/src/tx_thread_secure_stack.c b/ports/cortex_m23/gnu/src/tx_thread_secure_stack.c new file mode 100644 index 00000000..0c9317c8 --- /dev/null +++ b/ports/cortex_m23/gnu/src/tx_thread_secure_stack.c @@ -0,0 +1,467 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +#include "tx_api.h" + +/* If TX_SINGLE_MODE_SECURE or TX_SINGLE_MODE_NON_SECURE is defined, + no secure stack functionality is needed. */ +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + +#define TX_SOURCE_CODE + +#include "ARMCM23_TZ.h" /* For intrinsic functions. */ +#include "tx_secure_interface.h" /* Interface for NS code. */ + +/* Minimum size of secure stack. */ +#ifndef TX_THREAD_SECURE_STACK_MINIMUM +#define TX_THREAD_SECURE_STACK_MINIMUM 256 +#endif +/* Maximum size of secure stack. */ +#ifndef TX_THREAD_SECURE_STACK_MAXIMUM +#define TX_THREAD_SECURE_STACK_MAXIMUM 1024 +#endif + +/* Secure stack info struct to hold stack start, stack limit, + current stack pointer, and pointer to owning thread. + This will be allocated for each thread with a secure stack. */ +typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT +{ + VOID *tx_thread_secure_stack_ptr; /* Thread's secure stack current pointer */ + VOID *tx_thread_secure_stack_start; /* Thread's secure stack start address */ + VOID *tx_thread_secure_stack_limit; /* Thread's secure stack limit */ + TX_THREAD *tx_thread_ptr; /* Keep track of thread for error handling */ +} TX_THREAD_SECURE_STACK_INFO; + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_initialize Cortex-M23/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes secure mode to use PSP stack. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __get_CONTROL Intrinsic to get CONTROL */ +/* __set_CONTROL Intrinsic to set CONTROL */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +void _tx_thread_secure_stack_initialize(void) +{ + + /* Set secure mode to use PSP. */ + __set_CONTROL(__get_CONTROL() | 2); + + /* Set process stack pointer and stack limit to 0 to throw exception when a thread + without a secure stack calls a secure function that tries to use secure stack. */ + __set_PSPLIM(0); + __set_PSP(0); + + return; +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_mode_stack_allocate Cortex-M23/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function allocates a thread's secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* stack_size Size of stack to allocates */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_SIZE_ERROR Invalid stack size */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* calloc Compiler's calloc function */ +/* malloc Compiler's malloc function */ +/* free Compiler's free() function */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* __TZ_get_PSPLIM_NS Intrinsic to get NS PSP */ +/* */ +/* CALLED BY */ +/* */ +/* SVC Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +{ +UINT status; +TX_THREAD_SECURE_STACK_INFO *info_ptr; +UCHAR *stack_mem; +ULONG sp; + + status = TX_SUCCESS; + + /* Make sure function is called from interrupt (threads should not call). */ + if (__get_IPSR() == 0) + { + status = TX_CALLER_ERROR; + } + else if (stack_size < TX_THREAD_SECURE_STACK_MINIMUM || stack_size > TX_THREAD_SECURE_STACK_MAXIMUM) + { + status = TX_SIZE_ERROR; + } + + /* Check if thread already has secure stack allocated. */ + else if (thread_ptr -> tx_thread_secure_stack_context != 0) + { + status = TX_THREAD_ERROR; + } + + else + { + /* Allocate space for secure stack info. */ + info_ptr = calloc(1, sizeof(TX_THREAD_SECURE_STACK_INFO)); + + if(info_ptr != TX_NULL) + { + /* If stack info allocated, allocate a stack. */ + stack_mem = malloc(stack_size); + + if(stack_mem != TX_NULL) + { + /* Secure stack has been allocated, save in the stack info struct. */ + info_ptr -> tx_thread_secure_stack_limit = stack_mem; + info_ptr -> tx_thread_secure_stack_start = stack_mem + stack_size; + info_ptr -> tx_thread_secure_stack_ptr = info_ptr -> tx_thread_secure_stack_start; + info_ptr -> tx_thread_ptr = thread_ptr; + + /* Save info pointer in thread. */ + thread_ptr -> tx_thread_secure_stack_context = info_ptr; + + /* Check if this thread is running by looking at PSP_NS and seeing if it is within + the stack_start and stack_end range. */ + sp = __TZ_get_PSP_NS(); + if(sp > ((ULONG) thread_ptr -> tx_thread_stack_start) && sp < ((ULONG) thread_ptr -> tx_thread_stack_end)) + { + /* If this thread is running, set Secure PSP and PSPLIM. */ + __set_PSPLIM((ULONG)(info_ptr -> tx_thread_secure_stack_limit)); + __set_PSP((ULONG)(info_ptr -> tx_thread_secure_stack_ptr)); + } + } + + else + { + /* Stack not allocated, free the info struct. */ + free(info_ptr); + status = TX_NO_MEMORY; + } + } + + else + { + status = TX_NO_MEMORY; + } + } + + return(status); +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_mode_stack_free Cortex-M23/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function frees a thread's secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* free Compiler's free() function */ +/* */ +/* CALLED BY */ +/* */ +/* SVC Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr) +{ +UINT status; +TX_THREAD_SECURE_STACK_INFO *info_ptr; + + status = TX_SUCCESS; + + /* Pickup stack info from thread. */ + info_ptr = thread_ptr -> tx_thread_secure_stack_context; + + /* Make sure function is called from interrupt (threads should not call). */ + if (__get_IPSR() == 0) + { + status = TX_CALLER_ERROR; + } + + /* Check that this secure context is for this thread. */ + else if (info_ptr -> tx_thread_ptr != thread_ptr) + { + status = TX_THREAD_ERROR; + } + + else + { + + /* Free secure stack. */ + free(info_ptr -> tx_thread_secure_stack_limit); + + /* Free info struct. */ + free(info_ptr); + + /* Clear secure context from thread. */ + thread_ptr -> tx_thread_secure_stack_context = 0; + } + + return(status); +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_context_save Cortex-M23/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves context of the secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* __get_PSP Intrinsic to get PSP */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* */ +/* CALLED BY */ +/* */ +/* PendSV Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr) +{ +TX_THREAD_SECURE_STACK_INFO *info_ptr; +ULONG sp; + + /* This function should be called from scheduler only. */ + if (__get_IPSR() == 0) + { + return; + } + + /* Pickup the secure context pointer. */ + info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); + + /* Check that this secure context is for this thread. */ + if (info_ptr -> tx_thread_ptr != thread_ptr) + { + return; + } + + /* Check that stack pointer is in range */ + sp = __get_PSP(); + if ((sp < (ULONG)info_ptr -> tx_thread_secure_stack_limit) || + (sp > (ULONG)info_ptr -> tx_thread_secure_stack_start)) + { + return; + } + + /* Save stack pointer. */ + *(ULONG *) info_ptr -> tx_thread_secure_stack_ptr = sp; + + /* Set process stack pointer and stack limit to 0 to throw exception when a thread + without a secure stack calls a secure function that tries to use secure stack. */ + __set_PSPLIM(0); + __set_PSP(0); + + return; +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_context_restore Cortex-M23/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores context of the secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* */ +/* CALLED BY */ +/* */ +/* PendSV Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr) +{ +TX_THREAD_SECURE_STACK_INFO *info_ptr; + + /* This function should be called from scheduler only. */ + if (__get_IPSR() == 0) + { + return; + } + + /* Pickup the secure context pointer. */ + info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); + + /* Check that this secure context is for this thread. */ + if (info_ptr -> tx_thread_ptr != thread_ptr) + { + return; + } + + /* Set stack pointer and limit. */ + __set_PSPLIM((ULONG)info_ptr -> tx_thread_secure_stack_limit); + __set_PSP ((ULONG)info_ptr -> tx_thread_secure_stack_ptr); + + return; +} + +#endif diff --git a/ports/cortex_m23/gnu/src/tx_thread_secure_stack_allocate.s b/ports/cortex_m23/gnu/src/tx_thread_secure_stack_allocate.s new file mode 100644 index 00000000..527a0332 --- /dev/null +++ b/ports/cortex_m23/gnu/src/tx_thread_secure_stack_allocate.s @@ -0,0 +1,86 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_allocate Cortex-M23/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function enters the SVC handler to allocate a secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* stack_size Size of secure stack to */ +/* allocate */ +/* */ +/* OUTPUT */ +/* */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* SVC 1 */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_secure_stack_allocate + .thumb_func +.type _tx_thread_secure_stack_allocate, function +_tx_thread_secure_stack_allocate: +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + MRS r3, PRIMASK // Save interrupt mask + CPSIE i // Enable interrupts for SVC call + SVC 1 + CMP r3, #0 // If interrupts enabled, just return + BEQ _alloc_return_interrupt_enabled + CPSID i // Otherwise, disable interrupts +#else + // Executing in single mode - this function is not needed. + MOVS r0, #0xFF // Feature not enabled +#endif +_alloc_return_interrupt_enabled: + BX lr + .end diff --git a/ports/cortex_m23/gnu/src/tx_thread_secure_stack_free.s b/ports/cortex_m23/gnu/src/tx_thread_secure_stack_free.s new file mode 100644 index 00000000..94ef8f55 --- /dev/null +++ b/ports/cortex_m23/gnu/src/tx_thread_secure_stack_free.s @@ -0,0 +1,84 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_free Cortex-M23/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function enters the SVC handler to free a secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* SVC 2 */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_secure_stack_free + .thumb_func +.type _tx_thread_secure_stack_free, function +_tx_thread_secure_stack_free: +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + MRS r3, PRIMASK // Save interrupt mask + CPSIE i // Enable interrupts for SVC call + SVC 2 + CMP r3, #0 // If interrupts enabled, just return + BEQ _free_return_interrupt_enabled + CPSID i // Otherwise, disable interrupts +#else + // Executing in single mode - this function is not needed. + MOVS r0, #0xFF // Feature not enabled +#endif +_free_return_interrupt_enabled: + BX lr + .end diff --git a/ports/cortex_m23/gnu/src/tx_thread_stack_build.s b/ports/cortex_m23/gnu/src/tx_thread_stack_build.s new file mode 100644 index 00000000..704c5dfd --- /dev/null +++ b/ports/cortex_m23/gnu/src/tx_thread_stack_build.s @@ -0,0 +1,141 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build Cortex-M23/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_stack_build + .thumb_func +.type _tx_thread_stack_build, function +_tx_thread_stack_build: + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-M23 should look like the following after it is built: + + Stack Top: + LR Interrupted LR (LR at time of PENDSV) + r8 Initial value for r8 + r9 Initial value for r9 + r10 Initial value for r10 + r11 Initial value for r11 + r4 Initial value for r4 + r5 Initial value for r5 + r6 Initial value for r6 + r7 Initial value for r7 + r0 Initial value for r0 (Hardware stack starts here!!) + r1 Initial value for r1 + r2 Initial value for r2 + r3 Initial value for r3 + r12 Initial value for r12 + lr Initial value for lr + pc Initial value for pc + xPSR Initial value for xPSR + + Stack Bottom: (higher memory address) */ + + LDR r2, [r0, #16] // Pickup end of stack area + MOVW r3, #0x7 // + BICS r2, r2, r3 // Align frame for 8-byte alignment + SUBS r2, r2, #68 // Subtract frame size +#ifdef TX_SINGLE_MODE_SECURE + LDR r3, =0xFFFFFFFD // Build initial LR value for secure mode +#else + LDR r3, =0xFFFFFFBC // Build initial LR value to return to non-secure PSP +#endif + STR r3, [r2, #0] // Save on the stack + + /* Actually build the stack frame. */ + + MOVW r3, #0 // Build initial register value + STR r3, [r2, #4] // Store initial r8 + STR r3, [r2, #8] // Store initial r9 + STR r3, [r2, #12] // Store initial r10 + STR r3, [r2, #16] // Store initial r11 + STR r3, [r2, #20] // Store initial r4 + STR r3, [r2, #24] // Store initial r5 + STR r3, [r2, #28] // Store initial r6 + STR r3, [r2, #32] // Store initial r7 + + /* Hardware stack follows. */ + + STR r3, [r2, #36] // Store initial r0 + STR r3, [r2, #40] // Store initial r1 + STR r3, [r2, #44] // Store initial r2 + STR r3, [r2, #48] // Store initial r3 + STR r3, [r2, #52] // Store initial r12 + LDR r3, =0xFFFFFFFF // Poison EXC_RETURN value + STR r3, [r2, #56] // Store initial lr + STR r1, [r2, #60] // Store initial pc + LDR r3, =0x01000000 // Only T-bit need be set + STR r3, [r2, #64] // Store initial xPSR + + /* Setup stack pointer. */ + // thread_ptr -> tx_thread_stack_ptr = r2; + + STR r2, [r0, #8] // Save stack pointer in thread's + // control block + BX lr // Return to caller +// } + .end diff --git a/ports/cortex_m23/gnu/src/tx_thread_stack_error_handler.c b/ports/cortex_m23/gnu/src/tx_thread_stack_error_handler.c new file mode 100644 index 00000000..ef98240c --- /dev/null +++ b/ports/cortex_m23/gnu/src/tx_thread_stack_error_handler.c @@ -0,0 +1,93 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + +/* Define the global function pointer for stack error handling. If a stack error is + detected and the application has registered a stack error handler, it will be + called via this function pointer. */ + +VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_error_handler Cortex-M23 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes stack errors detected during run-time. */ +/* */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_terminate */ +/* _tx_thread_application_stack_error_handler */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX internal code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) +{ + #ifndef TX_THREAD_NO_TERMINATE_STACK_ERROR + /* Is there a thread? */ + if (thread_ptr) + { + /* Terminate the current thread. */ + _tx_thread_terminate(_tx_thread_current_ptr); + } + #endif + + /* Determine if the application has registered an error handler. */ + if (_tx_thread_application_stack_error_handler != TX_NULL) + { + /* Yes, an error handler is present, simply call the application error handler. */ + (_tx_thread_application_stack_error_handler)(thread_ptr); + } +} diff --git a/ports/cortex_m23/gnu/src/tx_thread_stack_error_notify.c b/ports/cortex_m23/gnu/src/tx_thread_stack_error_notify.c new file mode 100644 index 00000000..ffd78d08 --- /dev/null +++ b/ports/cortex_m23/gnu/src/tx_thread_stack_error_notify.c @@ -0,0 +1,96 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_trace.h" + +extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_error_notify Cortex-M23 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application stack error handler. If */ +/* ThreadX detects a stack error, this application handler is called. */ +/* */ +/* */ +/* INPUT */ +/* */ +/* stack_error_handler Pointer to stack error */ +/* handler, TX_NULL to disable */ +/* */ +/* OUTPUT */ +/* */ +/* status Service return status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr)) +{ + +TX_INTERRUPT_SAVE_AREA + + /* Disable interrupts. */ + TX_DISABLE + + /* Make entry in event log. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_STACK_ERROR_NOTIFY, 0, 0, 0, 0, TX_TRACE_THREAD_EVENTS) + + /* Make entry in event log. */ + TX_EL_THREAD_STACK_ERROR_NOTIFY_INSERT + + /* Setup global thread stack error handler. */ + _tx_thread_application_stack_error_handler = stack_error_handler; + + /* Restore interrupts. */ + TX_RESTORE + + /* Return success to caller. */ + return(TX_SUCCESS); +} diff --git a/ports/cortex_m23/gnu/src/tx_thread_system_return.s b/ports/cortex_m23/gnu/src/tx_thread_system_return.s new file mode 100644 index 00000000..7aa911b0 --- /dev/null +++ b/ports/cortex_m23/gnu/src/tx_thread_system_return.s @@ -0,0 +1,89 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return Cortex-M23/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the ThreadX system. Only a */ +/* minimal context is saved since the compiler assumes temp registers */ +/* are going to get slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_system_return(VOID) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_system_return + .thumb_func +.type _tx_thread_system_return, function +_tx_thread_system_return: + /* Return to real scheduler via PendSV. Note that this routine is often + replaced with in-line assembly in tx_port.h to improved performance. */ + + LDR r0, =0x10000000 // Load PENDSVSET bit + LDR r1, =0xE000ED04 // Load ICSR address + STR r0, [r1] // Set PENDSVBIT in ICSR + MRS r0, IPSR // Pickup IPSR + CMP r0, #0 // Is it a thread returning? + BNE _isr_context // If ISR, skip interrupt enable + MRS r1, PRIMASK // Thread context returning, pickup PRIMASK + CPSIE i // Enable interrupts + MSR PRIMASK, r1 // Restore original interrupt posture +_isr_context: + BX lr // Return to caller +// } + .end diff --git a/ports/cortex_m23/gnu/src/tx_timer_interrupt.s b/ports/cortex_m23/gnu/src/tx_timer_interrupt.s new file mode 100644 index 00000000..0e2ea836 --- /dev/null +++ b/ports/cortex_m23/gnu/src/tx_timer_interrupt.s @@ -0,0 +1,262 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt Cortex-M23/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_timer_interrupt(VOID) +{ */ + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_timer_interrupt + .thumb_func +.type _tx_timer_interrupt, function +_tx_timer_interrupt: + + /* Upon entry to this routine, it is assumed that the compiler scratch registers are available + for use. */ + + /* Increment the system clock. */ + // _tx_timer_system_clock++; + + MOVW r1, #:lower16:_tx_timer_system_clock // Pickup address of system clock + MOVT r1, #:upper16:_tx_timer_system_clock + LDR r0, [r1, #0] // Pickup system clock + ADDS r0, r0, #1 // Increment system clock + STR r0, [r1, #0] // Store new system clock + + /* Test for time-slice expiration. */ + // if (_tx_timer_time_slice) + // { + + MOVW r3, #:lower16:_tx_timer_time_slice // Pickup address of time-slice + MOVT r3, #:upper16:_tx_timer_time_slice + LDR r2, [r3, #0] // Pickup time-slice + CBZ r2, __tx_timer_no_time_slice // Is it non-active? + // Yes, skip time-slice processing + + /* Decrement the time_slice. */ + // _tx_timer_time_slice--; + + SUBS r2, r2, #1 // Decrement the time-slice + STR r2, [r3, #0] // Store new time-slice value + + /* Check for expiration. */ + // if (__tx_timer_time_slice == 0) + + CBNZ r2, __tx_timer_no_time_slice // Has it expired? + + /* Set the time-slice expired flag. */ + // _tx_timer_expired_time_slice = TX_TRUE; + + MOVW r3, #:lower16:_tx_timer_expired_time_slice // Pickup address of expired flag + MOVT r3, #:upper16:_tx_timer_expired_time_slice + MOVW r0, #1 // Build expired value + STR r0, [r3, #0] // Set time-slice expiration flag + + // } + +__tx_timer_no_time_slice: + + /* Test for timer expiration. */ + // if (*_tx_timer_current_ptr) + // { + + MOVW r1, #:lower16:_tx_timer_current_ptr // Pickup current timer pointer address + MOVT r1, #:upper16:_tx_timer_current_ptr + LDR r0, [r1, #0] // Pickup current timer + LDR r2, [r0, #0] // Pickup timer list entry + CBZ r2, __tx_timer_no_timer // Is there anything in the list? + // No, just increment the timer + + /* Set expiration flag. */ + // _tx_timer_expired = TX_TRUE; + + MOVW r3, #:lower16:_tx_timer_expired // Pickup expiration flag address + MOVT r3, #:upper16:_tx_timer_expired + MOVW r2, #1 // Build expired value + STR r2, [r3, #0] // Set expired flag + B __tx_timer_done // Finished timer processing + + // } + // else + // { +__tx_timer_no_timer: + + /* No timer expired, increment the timer pointer. */ + // _tx_timer_current_ptr++; + + ADDS r0, r0, #4 // Move to next timer + + /* Check for wrap-around. */ + // if (_tx_timer_current_ptr == _tx_timer_list_end) + + MOVW r3, #:lower16:_tx_timer_list_end // Pickup addr of timer list end + MOVT r3, #:upper16:_tx_timer_list_end + LDR r2, [r3, #0] // Pickup list end + CMP r0, r2 // Are we at list end? + BNE __tx_timer_skip_wrap // No, skip wrap-around logic + + /* Wrap to beginning of list. */ + // _tx_timer_current_ptr = _tx_timer_list_start; + + MOVW r3, #:lower16:_tx_timer_list_start // Pickup addr of timer list start + MOVT r3, #:upper16:_tx_timer_list_start + LDR r0, [r3, #0] // Set current pointer to list start + +__tx_timer_skip_wrap: + + STR r0, [r1, #0] // Store new current timer pointer + // } + +__tx_timer_done: + + + /* See if anything has expired. */ + // if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) + // { + + MOVW r3, #:lower16:_tx_timer_expired_time_slice // Pickup addr of expired flag + MOVT r3, #:upper16:_tx_timer_expired_time_slice + LDR r2, [r3, #0] // Pickup time-slice expired flag + CBNZ r2, __tx_something_expired // Did a time-slice expire? + // If non-zero, time-slice expired + MOVW r1, #:lower16:_tx_timer_expired // Pickup addr of other expired flag + MOVT r1, #:upper16:_tx_timer_expired + LDR r0, [r1, #0] // Pickup timer expired flag + CBZ r0, __tx_timer_nothing_expired // Did a timer expire? + // No, nothing expired + +__tx_something_expired: + + PUSH {r0, lr} // Save the lr register on the stack + // and save r0 just to keep 8-byte alignment + + /* Did a timer expire? */ + // if (_tx_timer_expired) + // { + + MOVW r1, #:lower16:_tx_timer_expired // Pickup addr of expired flag + MOVT r1, #:upper16:_tx_timer_expired + LDR r0, [r1, #0] // Pickup timer expired flag + CBZ r0, __tx_timer_dont_activate // Check for timer expiration + // If not set, skip timer activation + + /* Process timer expiration. */ + // _tx_timer_expiration_process(); + + BL _tx_timer_expiration_process // Call the timer expiration handling routine + + // } +__tx_timer_dont_activate: + + /* Did time slice expire? */ + // if (_tx_timer_expired_time_slice) + // { + + MOVW r3, #:lower16:_tx_timer_expired_time_slice // Pickup addr of time-slice expired + MOVT r3, #:upper16:_tx_timer_expired_time_slice + LDR r2, [r3, #0] // Pickup the actual flag + CBZ r2, __tx_timer_not_ts_expiration // See if the flag is set + // No, skip time-slice processing + + /* Time slice interrupted thread. */ + // _tx_thread_time_slice(); + + BL _tx_thread_time_slice // Call time-slice processing + MOVW r0, #:lower16:_tx_thread_preempt_disable // Build address of preempt disable flag + MOVT r0, #:upper16:_tx_thread_preempt_disable + + LDR r1, [r0] // Is the preempt disable flag set? + CBNZ r1, __tx_timer_skip_time_slice // Yes, skip the PendSV logic + MOVW r0, #:lower16:_tx_thread_current_ptr // Build current thread pointer address + MOVT r0, #:upper16:_tx_thread_current_ptr + + LDR r1, [r0] // Pickup the current thread pointer + MOVW r2, #:lower16:_tx_thread_execute_ptr // Build execute thread pointer address + MOVT r2, #:upper16:_tx_thread_execute_ptr + + LDR r3, [r2] // Pickup the execute thread pointer + LDR r0, =0xE000ED04 // Build address of control register + LDR r2, =0x10000000 // Build value for PendSV bit + CMP r1, r3 // Are they the same? + BEQ __tx_timer_skip_time_slice // If the same, there was no time-slice performed + STR r2, [r0] // Not the same, issue the PendSV for preemption +__tx_timer_skip_time_slice: + // } + +__tx_timer_not_ts_expiration: + + POP {r0, r1} // Recover lr register (r0 is just there for + MOV lr, r1 // the 8-byte stack alignment + + // } + +__tx_timer_nothing_expired: + + DSB // Complete all memory access + BX lr // Return to caller + +// } + .end diff --git a/ports/cortex_m23/gnu/src/txe_thread_secure_stack_allocate.c b/ports/cortex_m23/gnu/src/txe_thread_secure_stack_allocate.c new file mode 100644 index 00000000..35482b6c --- /dev/null +++ b/ports/cortex_m23/gnu/src/txe_thread_secure_stack_allocate.c @@ -0,0 +1,119 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_secure_stack_allocate Cortex-M23 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the secure stack allocate */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* stack_size Size of secure stack to */ +/* allocate */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_secure_stack_allocate Actual stack alloc function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +{ +#if defined(TX_SINGLE_MODE_SECURE) || defined(TX_SINGLE_MODE_NON_SECURE) + return(TX_FEATURE_NOT_ENABLED); +#else +UINT status; + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid thread pointer. */ + if (thread_ptr == TX_NULL) + { + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Now check for invalid thread ID. */ + else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) + { + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Check for interrupt call. */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + /* Is call from an interrupt and not initialization? */ + if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS) + { + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + /* Call actual secure stack allocate function. */ + status = _tx_thread_secure_stack_allocate(thread_ptr, stack_size); + } + + /* Return completion status. */ + return(status); +#endif +} diff --git a/ports/cortex_m23/gnu/src/txe_thread_secure_stack_free.c b/ports/cortex_m23/gnu/src/txe_thread_secure_stack_free.c new file mode 100644 index 00000000..950e8ec0 --- /dev/null +++ b/ports/cortex_m23/gnu/src/txe_thread_secure_stack_free.c @@ -0,0 +1,120 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_secure_stack_free Cortex-M23 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the secure stack free */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_secure_stack_free Actual stack free function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) +{ +#if defined(TX_SINGLE_MODE_SECURE) || defined(TX_SINGLE_MODE_NON_SECURE) + return(TX_FEATURE_NOT_ENABLED); +#else +UINT status; + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid thread pointer. */ + if (thread_ptr == TX_NULL) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Now check for invalid thread ID. */ + else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Check for interrupt call. */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + /* Is call from an interrupt and not initialization? */ + if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS) + { + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + + /* Call actual secure stack allocate function. */ + status = _tx_thread_secure_stack_free(thread_ptr); + } + + /* Return completion status. */ + return(status); +#endif +} diff --git a/ports/cortex_m23/iar/inc/tx_port.h b/ports/cortex_m23/iar/inc/tx_port.h new file mode 100644 index 00000000..bd9aa33b --- /dev/null +++ b/ports/cortex_m23/iar/inc/tx_port.h @@ -0,0 +1,455 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-M23/IAR */ +/* 6.1 */ +/* */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + +/* Determine if the optional ThreadX user define file should be used. */ +#ifdef TX_INCLUDE_USER_DEFINE_FILE + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + +/* Define compiler library include files. */ + +#include +#include +#include +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef unsigned long long ULONG64; +typedef short SHORT; +typedef unsigned short USHORT; + +/* Function prototypes for this port. */ +struct TX_THREAD_STRUCT; +UINT _txe_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *thread_ptr, ULONG stack_size); +UINT _txe_thread_secure_stack_free(struct TX_THREAD_STRUCT *thread_ptr); +UINT _tx_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *tx_thread, ULONG stack_size); +UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); + +/* This hardware has stack checking that we take advantage of - do NOT define. */ +#ifdef TX_ENABLE_STACK_CHECKING + #error "Do not define TX_ENABLE_STACK_CHECKING" +#endif + +/* If user does not want to terminate thread on stack overflow, + #define the TX_THREAD_NO_TERMINATE_STACK_ERROR symbol. + The thread will be rescheduled and continue to cause the exception. + It is suggested user code handle this by registering a notification with the + tx_thread_stack_error_notify function. */ +/*#define TX_THREAD_NO_TERMINATE_STACK_ERROR */ + +/* Define the system API mappings based on the error checking + selected by the user. Note: this section is only applicable to + application source code, hence the conditional that turns off this + stuff when the include file is processed by the ThreadX source. */ + +#ifndef TX_SOURCE_CODE + + +/* Determine if error checking is desired. If so, map API functions + to the appropriate error checking front-ends. Otherwise, map API + functions to the core functions that actually perform the work. + Note: error checking is enabled by default. */ + +#ifdef TX_DISABLE_ERROR_CHECKING + +/* Services without error checking. */ + +#define tx_thread_secure_stack_allocate _tx_thread_secure_stack_allocate +#define tx_thread_secure_stack_free _tx_thread_secure_stack_free + +#else + +/* Services with error checking. */ + +#define tx_thread_secure_stack_allocate _txe_thread_secure_stack_allocate +#define tx_thread_secure_stack_free _txe_thread_secure_stack_free + +#endif +#endif + + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX Cortex-M23 port. */ + +#define TX_INT_DISABLE 1 /* Disable interrupts */ +#define TX_INT_ENABLE 0 /* Enable interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) +#endif +#else +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif + +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +/* IAR library support */ +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +/* ThreadX in non-secure zone with calls to secure zone. */ +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_secure_stack_context; \ + VOID *tx_thread_iar_tls_pointer; +#else +/* ThreadX in only one zone. */ +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#endif + +#else +/* No IAR library support */ +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +/* ThreadX in non-secure zone with calls to secure zone. */ +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_secure_stack_context; +#else +/* ThreadX in only one zone. */ +#define TX_THREAD_EXTENSION_2 +#endif + +#endif + + +#ifndef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#define TX_THREAD_EXTENSION_3 +#else +#define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ + unsigned long long tx_thread_execution_time_last_start; +#endif + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +void *_tx_iar_create_per_thread_tls_area(void); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); +void __iar_Initlocks(void); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); \ + if(thread_ptr -> tx_thread_secure_stack_context){_tx_thread_secure_stack_free(thread_ptr);} +#else +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); +#endif +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#else +/* No IAR library support. */ +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) if(thread_ptr -> tx_thread_secure_stack_context){_tx_thread_secure_stack_free(thread_ptr);} +#else +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif +#endif + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +/* Define the size of the secure stack for the timer thread and use the extension to allocate the secure stack. */ +#define TX_TIMER_THREAD_SECURE_STACK_SIZE 256 +#define TX_TIMER_INITIALIZE_EXTENSION(status) _tx_thread_secure_stack_allocate(&_tx_timer_thread, TX_TIMER_THREAD_SECURE_STACK_SIZE); +#endif + + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define the get system state macro. */ + +#ifndef TX_THREAD_GET_SYSTEM_STATE +#ifndef TX_MISRA_ENABLE +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | __get_IPSR()) +#else +ULONG _tx_misra_ipsr_get(VOID); +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get()) +#endif +#endif + + +/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value + indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h + for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always + zero after initialization for Cortex-M ports. */ + +#ifndef TX_THREAD_SYSTEM_RETURN_CHECK +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#endif + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +/* Initialize secure stacks for threads calling secure functions. */ +extern void _tx_thread_secure_stack_initialize(void); +#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION _tx_thread_secure_stack_initialize(); +#endif + +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to + prevent early scheduling on Cortex-M parts. */ + +#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT)__CLZ(__RBIT((m))); + +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifdef TX_DISABLE_INLINE + +UINT _tx_thread_interrupt_disable(VOID); +VOID _tx_thread_interrupt_restore(UINT previous_posture); + +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); + +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA __istate_t interrupt_save; +#define TX_DISABLE {interrupt_save = __get_interrupt_state();__disable_interrupt();}; +#define TX_RESTORE {__set_interrupt_state(interrupt_save);}; + +#define _tx_thread_system_return _tx_thread_system_return_inline + +static void _tx_thread_system_return_inline(void) +{ +__istate_t interrupt_save; + + /* Set PendSV to invoke ThreadX scheduler. */ + *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + if (__get_IPSR() == 0) + { + interrupt_save = __get_interrupt_state(); + __enable_interrupt(); + __set_interrupt_state(interrupt_save); + } +} + +#endif + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/IAR Version 6.1 *"; +#else +#ifdef TX_MISRA_ENABLE +extern CHAR _tx_version_id[100]; +#else +extern CHAR _tx_version_id[]; +#endif +#endif + +#endif diff --git a/ports/cortex_m23/iar/inc/tx_secure_interface.h b/ports/cortex_m23/iar/inc/tx_secure_interface.h new file mode 100644 index 00000000..976f32be --- /dev/null +++ b/ports/cortex_m23/iar/inc/tx_secure_interface.h @@ -0,0 +1,60 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* tx_secure_interface.h Cortex-M23 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the ThreadX secure thread stack components, */ +/* including data types and external references. */ +/* It is assumed that tx_api.h and tx_port.h have already been */ +/* included. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_SECURE_INTERFACE_H +#define TX_SECURE_INTERFACE_H + +/* Define internal secure thread stack function prototypes. */ + +extern void _tx_thread_secure_stack_initialize(void); +extern UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size); +extern UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr); +extern void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr); +extern void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr); + +#endif diff --git a/ports/cortex_m23/iar/readme_threadx.txt b/ports/cortex_m23/iar/readme_threadx.txt new file mode 100644 index 00000000..83cd5e2b --- /dev/null +++ b/ports/cortex_m23/iar/readme_threadx.txt @@ -0,0 +1,145 @@ + Microsoft's Azure RTOS ThreadX for Cortex-M23 + + Using the IAR Tools + + +1. Building the ThreadX run-time Library + +Import all ThreadX common and port-specific source files into an IAR project. +Configure the project to build a library rather than an executable. This +results in the ThreadX run-time library file tx.a, which is needed by +the application. + + +2. Demonstration System + +No demonstration is provided because the IAR EWARM 8.50 simulator does +not simulate the Cortex-M23 correctly. + + +3. System Initialization + +The entry point in ThreadX for the Cortex-M23 using IAR tools is at label +__iar_program_start. This is defined within the IAR compiler's startup code. +In addition, this is where all static and global preset C variable +initialization processing takes place. + +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, and a periodic timer interrupt source. + +The _tx_initialize_low_level function inside of tx_initialize_low_level.s +also determines the first available address for use by the application, which +is supplied as the sole input parameter to your application definition function, +tx_application_define. To accomplish this, a section is created in +tx_initialize_low_level.s called FREE_MEM, which must be located after all +other RAM sections in memory. + + +4. Register Usage and Stack Frames + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have the same stack frame in the Cortex-M23 version of +ThreadX. The top of the suspended thread's stack is pointed to by +tx_thread_stack_ptr in the associated thread control block TX_THREAD. + + Stack Offset Stack Contents + + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 r8 + 0x08 r9 + 0x0C r10 + 0x10 r11 + 0x14 r4 + 0x18 r5 + 0x1C r6 + 0x20 r7 + 0x24 r0 (Hardware stack starts here!!) + 0x28 r1 + 0x2C r2 + 0x30 r3 + 0x34 r12 + 0x38 lr + 0x3C pc + 0x40 xPSR + + +5. Improving Performance + +To make ThreadX and the application(s) run faster, you can enable +all compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +6. Interrupt Handling + +The Cortex-M23 vectors start at the label __vector_table and is typically defined in a +startup.s file (or similar). The application may modify the vector area according to its needs. + + +6.1 Managed Interrupts + +ISRs for Cortex-M using the IAR tools can be written completely in C (or assembly +language) without any calls to _tx_thread_context_save or _tx_thread_context_restore. +These ISRs are allowed access to the ThreadX API that is available to ISRs. + +ISRs written in C will take the form (where "your_C_isr" is an entry in the vector table): + +void your_C_isr(void) +{ + + /* ISR processing goes here, including any needed function calls. */ +} + +ISRs written in assembly language will take the form: + + PUBLIC your_assembly_isr +your_assembly_isr: + + PUSH {r0, lr} + + ; ISR processing goes here, including any needed function calls. + + POP {r0, r1} + MOV lr, r1 + BX lr + + +7. IAR Thread-safe Library Support + +Thread-safe support for the IAR tools is easily enabled by building the ThreadX library +and the application with TX_ENABLE_IAR_LIBRARY_SUPPORT. Also, the linker control file +should have the following line added (if not already in place): + +initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application + + +7. IAR Thread-safe Library Support + +Thread-safe support for the IAR tools is easily enabled by building the ThreadX library +and the application with TX_ENABLE_IAR_LIBRARY_SUPPORT. Also, the linker control file +should have the following line added (if not already in place): + +initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application + +The project options "General Options -> Library Configuration" should also have the +"Enable thread support in library" box selected. + + +8. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +09-30-2020 Initial ThreadX 6.1 version for Cortex-M23 using IAR's ARM tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_m23/iar/src/tx_iar.c b/ports/cortex_m23/iar/src/tx_iar.c new file mode 100644 index 00000000..dd719370 --- /dev/null +++ b/ports/cortex_m23/iar/src/tx_iar.c @@ -0,0 +1,804 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** IAR Multithreaded Library Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Define IAR library for tools prior to version 8. */ + +#if (__VER__ < 8000000) + + +/* IAR version 7 and below. */ + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_mutex.h" + + +/* This implementation requires that the following macros are defined in the + tx_port.h file and is included with the following code segments: + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. + + Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. +*/ + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT + +#include + + +#if _MULTI_THREAD + +TX_MUTEX __tx_iar_system_lock_mutexes[_MAX_LOCK]; +UINT __tx_iar_system_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_system_lock_no_mutexes; +UINT __tx_iar_system_lock_internal_errors; +UINT __tx_iar_system_lock_isr_caller; + + +/* Define the TLS access function for the IAR library. */ + +void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) +{ + +char _DLIB_TLS_MEMORY *p = 0; + + /* Is there a current thread? */ + if (_tx_thread_current_ptr) + p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; + else + p = (void _DLIB_TLS_MEMORY *) __segment_begin("__DLIB_PERTHREAD"); + p += __IAR_DLIB_PERTHREAD_SYMBOL_OFFSET(symbp); + return (void _DLIB_TLS_MEMORY *) p; +} + + +/* Define mutexes for IAR library. */ + +void __iar_system_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_LOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_system_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_system_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_system_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_system_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_system_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } +} + +void __iar_system_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } +} + + +#if _DLIB_FILE_DESCRIPTOR + +TX_MUTEX __tx_iar_file_lock_mutexes[_MAX_FLOCK]; +UINT __tx_iar_file_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_file_lock_no_mutexes; +UINT __tx_iar_file_lock_internal_errors; +UINT __tx_iar_file_lock_isr_caller; + + +void __iar_file_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_FLOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_file_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_file_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_file_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_file_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_file_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} + +void __iar_file_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} +#endif /* _DLIB_FILE_DESCRIPTOR */ + +#endif /* _MULTI_THREAD */ + +#endif /* TX_ENABLE_IAR_LIBRARY_SUPPORT */ + +#else /* IAR version 8 and above. */ + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_mutex.h" + +/* This implementation requires that the following macros are defined in the + tx_port.h file and is included with the following code segments: + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +void *_tx_iar_create_per_thread_tls_area(void); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); +void __iar_Initlocks(void); + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. + + Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. +*/ + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT + +#include + + +void * __aeabi_read_tp(); + +void* _tx_iar_create_per_thread_tls_area(); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); + +#pragma section="__iar_tls$$DATA" + +/* Define the TLS access function for the IAR library. */ +void * __aeabi_read_tp(void) +{ + void *p = 0; + TX_THREAD *thread_ptr = _tx_thread_current_ptr; + if (thread_ptr) + { + p = thread_ptr->tx_thread_iar_tls_pointer; + } + else + { + p = __section_begin("__iar_tls$$DATA"); + } + return p; +} + +/* Define the TLS creation and destruction to use malloc/free. */ + +void* _tx_iar_create_per_thread_tls_area() +{ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ + void *p = malloc(tls_size); + + /* Initialize TLS-area and run constructors for objects in TLS */ + __iar_tls_init(p); + return p; +} + +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) +{ + /* Destroy objects living in TLS */ + __call_thread_dtors(); + free(tls_ptr); +} + +#ifndef _MAX_LOCK +#define _MAX_LOCK 4 +#endif + +static TX_MUTEX __tx_iar_system_lock_mutexes[_MAX_LOCK]; +static UINT __tx_iar_system_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_system_lock_no_mutexes; +UINT __tx_iar_system_lock_internal_errors; +UINT __tx_iar_system_lock_isr_caller; + + +/* Define mutexes for IAR library. */ + +void __iar_system_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_LOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_system_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_system_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_system_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_system_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_system_Mtxlock(__iar_Rmtx *m) +{ + if (*m) + { + UINT status; + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } + } +} + +void __iar_system_Mtxunlock(__iar_Rmtx *m) +{ + if (*m) + { + UINT status; + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } + } +} + + +#if _DLIB_FILE_DESCRIPTOR + +#include /* Added to get access to FOPEN_MAX */ +#ifndef _MAX_FLOCK +#define _MAX_FLOCK FOPEN_MAX /* Define _MAX_FLOCK as the maximum number of open files */ +#endif + + +TX_MUTEX __tx_iar_file_lock_mutexes[_MAX_FLOCK]; +UINT __tx_iar_file_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_file_lock_no_mutexes; +UINT __tx_iar_file_lock_internal_errors; +UINT __tx_iar_file_lock_isr_caller; + + +void __iar_file_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_FLOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_file_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_file_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_file_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_file_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_file_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} + +void __iar_file_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} +#endif /* _DLIB_FILE_DESCRIPTOR */ + +#endif /* TX_ENABLE_IAR_LIBRARY_SUPPORT */ + +#endif /* IAR version 8 and above. */ diff --git a/ports/cortex_m23/iar/src/tx_initialize_low_level.s b/ports/cortex_m23/iar/src/tx_initialize_low_level.s new file mode 100644 index 00000000..92a5f4d2 --- /dev/null +++ b/ports/cortex_m23/iar/src/tx_initialize_low_level.s @@ -0,0 +1,204 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_initialize_unused_memory + EXTERN _tx_timer_interrupt + EXTERN __main + EXTERN __vector_table + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_stack_error_handler +; +; +SYSTEM_CLOCK EQU 96000000 +SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1) +; +; + RSEG FREE_MEM:DATA + PUBLIC __tx_free_memory_start +__tx_free_memory_start + DS32 4 +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-M23/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + PUBLIC _tx_initialize_low_level +_tx_initialize_low_level: +; +; /* Disable interrupts during ThreadX initialization. */ +; + CPSID i +; +; /* Set base of available memory to end of non-initialised RAM area. */ +; + LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer + LDR r1, =__tx_free_memory_start ; Build first free address + STR r1, [r0] ; Setup first unused memory pointer +; +; /* Setup Vector Table Offset Register. */ +; + LDR r0, =0xE000ED08 ; Build address of NVIC registers + LDR r1, =__vector_table ; Pickup address of vector table + STR r1, [r0] ; Set vector table address +; +; /* Enable the cycle count register. */ +; +; LDR r0, =0xE0001000 ; Build address of DWT register +; LDR r1, [r0] ; Pickup the current value +; ORR r1, r1, #1 ; Set the CYCCNTENA bit +; STR r1, [r0] ; Enable the cycle count register +; +; /* Set system stack pointer from vector value. */ +; + LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer + LDR r1, =__vector_table ; Pickup address of vector table + LDR r1, [r1] ; Pickup reset stack pointer + STR r1, [r0] ; Save system stack pointer +; +; /* Configure SysTick. */ +; + LDR r0, =0xE000E000 ; Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] ; Setup SysTick Reload Value + MOV r1, #0x7 ; Build SysTick Control Enable Value + STR r1, [r0, #0x10] ; Setup SysTick Control +; +; /* Configure handler priorities. */ +; + LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM + LDR r0, =0xE000E000 ; Build address of NVIC registers + LDR r2, =0xD18 ; + ADD r0, r0, r2 ; + STR r1, [r0] ; Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv + LDR r0, =0xE000E000 ; Build address of NVIC registers + LDR r2, =0xD1C ; + ADD r0, r0, r2 ; + STR r1, [r0] ; Setup System Handlers 8-11 Priority Registers + ; Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM + LDR r0, =0xE000E000 ; Build address of NVIC registers + LDR r2, =0xD20 ; + ADD r0, r0, r2 ; + STR r1, [r0] ; Setup System Handlers 12-15 Priority Registers + ; Note: PnSV must be lowest priority, which is 0xFF +; +; /* Return to caller. */ +; + BX lr +;} +; +; +;/* Define shells for each of the unused vectors. */ +; + PUBLIC __tx_BadHandler +__tx_BadHandler: + B __tx_BadHandler + + + PUBLIC __tx_IntHandler +__tx_IntHandler: +; VOID InterruptHandler (VOID) +; { + PUSH {r0, lr} ; Save LR (and dummy r0 to maintain stack alignment) + +; /* Do interrupt handler work here */ +; /* .... */ + + POP {r0, r1} + MOV lr, r1 + BX lr +; } + + + PUBLIC __tx_SysTickHandler + PUBLIC SysTick_Handler +SysTick_Handler: +__tx_SysTickHandler: +; VOID TimerInterruptHandler (VOID) +; { +; + PUSH {r0, lr} ; Save LR (and dummy r0 to maintain stack alignment) + BL _tx_timer_interrupt + POP {r0, r1} + MOV lr, r1 + BX lr +; } + + + PUBLIC HardFault_Handler +HardFault_Handler: + ; A stack overflow will trigger a hardfault. + ; There is no CFSR in M23, so we will not try to + ; determine if the fault is caused by a stack overflow + ; or some other condition. + B HardFault_Handler + + + END diff --git a/ports/cortex_m23/iar/src/tx_misra.s b/ports/cortex_m23/iar/src/tx_misra.s new file mode 100644 index 00000000..acb85cc9 --- /dev/null +++ b/ports/cortex_m23/iar/src/tx_misra.s @@ -0,0 +1,1003 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** ThreadX MISRA Compliance */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + #define SHT_PROGBITS 0x1 + + EXTERN __aeabi_memset + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_interrupt_disable + EXTERN _tx_thread_interrupt_restore + EXTERN _tx_thread_stack_analyze + EXTERN _tx_thread_stack_error_handler + EXTERN _tx_thread_system_state +#ifdef TX_ENABLE_EVENT_TRACE + EXTERN _tx_trace_buffer_current_ptr + EXTERN _tx_trace_buffer_end_ptr + EXTERN _tx_trace_buffer_start_ptr + EXTERN _tx_trace_event_enable_bits + EXTERN _tx_trace_full_notify_function + EXTERN _tx_trace_header_ptr +#endif + + PUBLIC _tx_misra_always_true + PUBLIC _tx_misra_block_pool_to_uchar_pointer_convert + PUBLIC _tx_misra_byte_pool_to_uchar_pointer_convert + PUBLIC _tx_misra_char_to_uchar_pointer_convert + PUBLIC _tx_misra_const_char_to_char_pointer_convert +#ifdef TX_ENABLE_EVENT_TRACE + PUBLIC _tx_misra_entry_to_uchar_pointer_convert +#endif + PUBLIC _tx_misra_indirect_void_to_uchar_pointer_convert + PUBLIC _tx_misra_memset + PUBLIC _tx_misra_message_copy +#ifdef TX_ENABLE_EVENT_TRACE + PUBLIC _tx_misra_object_to_uchar_pointer_convert +#endif + PUBLIC _tx_misra_pointer_to_ulong_convert + PUBLIC _tx_misra_status_get + PUBLIC _tx_misra_thread_stack_check +#ifdef TX_ENABLE_EVENT_TRACE + PUBLIC _tx_misra_time_stamp_get +#endif + PUBLIC _tx_misra_timer_indirect_to_void_pointer_convert + PUBLIC _tx_misra_timer_pointer_add + PUBLIC _tx_misra_timer_pointer_dif +#ifdef TX_ENABLE_EVENT_TRACE + PUBLIC _tx_misra_trace_event_insert +#endif + PUBLIC _tx_misra_uchar_pointer_add + PUBLIC _tx_misra_uchar_pointer_dif + PUBLIC _tx_misra_uchar_pointer_sub + PUBLIC _tx_misra_uchar_to_align_type_pointer_convert + PUBLIC _tx_misra_uchar_to_block_pool_pointer_convert +#ifdef TX_ENABLE_EVENT_TRACE + PUBLIC _tx_misra_uchar_to_entry_pointer_convert + PUBLIC _tx_misra_uchar_to_header_pointer_convert +#endif + PUBLIC _tx_misra_uchar_to_indirect_byte_pool_pointer_convert + PUBLIC _tx_misra_uchar_to_indirect_uchar_pointer_convert +#ifdef TX_ENABLE_EVENT_TRACE + PUBLIC _tx_misra_uchar_to_object_pointer_convert +#endif + PUBLIC _tx_misra_uchar_to_void_pointer_convert + PUBLIC _tx_misra_ulong_pointer_add + PUBLIC _tx_misra_ulong_pointer_dif + PUBLIC _tx_misra_ulong_pointer_sub + PUBLIC _tx_misra_ulong_to_pointer_convert + PUBLIC _tx_misra_ulong_to_thread_pointer_convert + PUBLIC _tx_misra_user_timer_pointer_get + PUBLIC _tx_misra_void_to_block_pool_pointer_convert + PUBLIC _tx_misra_void_to_byte_pool_pointer_convert + PUBLIC _tx_misra_void_to_event_flags_pointer_convert + PUBLIC _tx_misra_void_to_indirect_uchar_pointer_convert + PUBLIC _tx_misra_void_to_mutex_pointer_convert + PUBLIC _tx_misra_void_to_queue_pointer_convert + PUBLIC _tx_misra_void_to_semaphore_pointer_convert + PUBLIC _tx_misra_void_to_thread_pointer_convert + PUBLIC _tx_misra_void_to_uchar_pointer_convert + PUBLIC _tx_misra_void_to_ulong_pointer_convert + PUBLIC _tx_misra_ipsr_get + PUBLIC _tx_version_id + + + SECTION `.data`:DATA:REORDER:NOROOT(2) + DATA +// 51 CHAR _tx_version_id[100] = "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX 6.1 MISRA C Compliant *"; +_tx_version_id: + DC8 43H, 6FH, 70H, 79H, 72H, 69H, 67H, 68H + DC8 74H, 20H, 28H, 63H, 29H, 20H, 31H, 39H + DC8 39H, 36H, 2DH, 32H, 30H, 31H, 38H, 20H + DC8 45H, 78H, 70H, 72H, 65H, 73H, 73H, 20H + DC8 4CH, 6FH, 67H, 69H, 63H, 20H, 49H, 6EH + DC8 63H, 2EH, 20H, 2AH, 20H, 54H, 68H, 72H + DC8 65H, 61H, 64H, 58H, 20H, 36H, 2EH, 30H + DC8 20H, 4DH, 49H, 53H, 52H, 41H, 20H, 43H + DC8 20H, 43H, 6FH, 6DH, 70H, 6CH, 69H, 61H + DC8 6EH, 74H, 20H, 2AH, 0 + DC8 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_memset(VOID *ptr, UINT value, UINT size); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_memset: + PUSH {R4,LR} + MOVS R4,R0 + MOVS R0,R2 + MOVS R2,R1 + MOVS R1,R0 + MOVS R0,R4 + BL __aeabi_memset + POP {R4,PC} ;; return + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UCHAR *_tx_misra_uchar_pointer_add(UCHAR *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_pointer_add: + ADD R0,R0,R1 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UCHAR *_tx_misra_uchar_pointer_sub(UCHAR *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_pointer_sub: + RSBS R1,R1,#+0 + ADD R0,R0,R1 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_uchar_pointer_dif(UCHAR *ptr1, UCHAR *ptr2); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_pointer_dif: + SUBS R0,R0,R1 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_pointer_to_ulong_convert: + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG *_tx_misra_ulong_pointer_add(ULONG *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_ulong_pointer_add: + ADD R0,R0,R1, LSL #+2 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG *_tx_misra_ulong_pointer_sub(ULONG *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_ulong_pointer_sub: + MVNS R2,#+3 + MULS R1,R2,R1 + ADD R0,R0,R1 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_ulong_pointer_dif(ULONG *ptr1, ULONG *ptr2); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_ulong_pointer_dif: + SUBS R0,R0,R1 + ASRS R0,R0,#+2 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID *_tx_misra_ulong_to_pointer_convert(ULONG input); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_ulong_to_pointer_convert: + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_message_copy(ULONG **source, ULONG **destination, */ +/** UINT size); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_message_copy: + PUSH {R4,R5} + LDR R3,[R0, #+0] + LDR R4,[R1, #+0] + LDR R5,[R3, #+0] + STR R5,[R4, #+0] + ADDS R4,R4,#+4 + ADDS R3,R3,#+4 + CMP R2,#+2 + BCC.N ??_tx_misra_message_copy_0 + SUBS R2,R2,#+1 + B.N ??_tx_misra_message_copy_1 +??_tx_misra_message_copy_2: + LDR R5,[R3, #+0] + STR R5,[R4, #+0] + ADDS R4,R4,#+4 + ADDS R3,R3,#+4 + SUBS R2,R2,#+1 +??_tx_misra_message_copy_1: + CMP R2,#+0 + BNE.N ??_tx_misra_message_copy_2 +??_tx_misra_message_copy_0: + STR R3,[R0, #+0] + STR R4,[R1, #+0] + POP {R4,R5} + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_timer_pointer_dif(TX_TIMER_INTERNAL **ptr1, */ +/** TX_TIMER_INTERNAL **ptr2); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_timer_pointer_dif: + SUBS R0,R0,R1 + ASRS R0,R0,#+2 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** TX_TIMER_INTERNAL **_tx_misra_timer_pointer_add(TX_TIMER_INTERNAL */ +/** **ptr1, ULONG size); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_timer_pointer_add: + ADD R0,R0,R1, LSL #+2 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_user_timer_pointer_get(TX_TIMER_INTERNAL */ +/** *internal_timer, TX_TIMER **user_timer); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_user_timer_pointer_get: + ADDS R2,R0,#+8 + SUBS R2,R2,R0 + RSBS R2,R2,#+0 + ADD R0,R0,R2 + STR R0,[R1, #+0] + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_thread_stack_check(TX_THREAD *thread_ptr, */ +/** VOID **highest_stack); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_thread_stack_check: + PUSH {R3-R5,LR} + MOVS R4,R0 + MOVS R5,R1 + BL _tx_thread_interrupt_disable + CMP R4,#+0 + BEQ.N ??_tx_misra_thread_stack_check_0 + LDR R1,[R4, #+0] + LDR.N R2,??DataTable2 ;; 0x54485244 + CMP R1,R2 + BNE.N ??_tx_misra_thread_stack_check_0 + LDR R1,[R4, #+8] + LDR R2,[R5, #+0] + CMP R1,R2 + BCS.N ??_tx_misra_thread_stack_check_1 + LDR R1,[R4, #+8] + STR R1,[R5, #+0] +??_tx_misra_thread_stack_check_1: + LDR R1,[R4, #+12] + LDR R1,[R1, #+0] + CMP R1,#-269488145 + BNE.N ??_tx_misra_thread_stack_check_2 + LDR R1,[R4, #+16] + LDR R1,[R1, #+1] + CMP R1,#-269488145 + BNE.N ??_tx_misra_thread_stack_check_2 + LDR R1,[R5, #+0] + LDR R2,[R4, #+12] + CMP R1,R2 + BCS.N ??_tx_misra_thread_stack_check_3 +??_tx_misra_thread_stack_check_2: + BL _tx_thread_interrupt_restore + MOVS R0,R4 + BL _tx_thread_stack_error_handler + BL _tx_thread_interrupt_disable +??_tx_misra_thread_stack_check_3: + LDR R1,[R5, #+0] + LDR R1,[R1, #-4] + CMP R1,#-269488145 + BEQ.N ??_tx_misra_thread_stack_check_0 + BL _tx_thread_interrupt_restore + MOVS R0,R4 + BL _tx_thread_stack_analyze + BL _tx_thread_interrupt_disable +??_tx_misra_thread_stack_check_0: + BL _tx_thread_interrupt_restore + POP {R0,R4,R5,PC} ;; return + +#ifdef TX_ENABLE_EVENT_TRACE + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_trace_event_insert(ULONG event_id, */ +/** VOID *info_field_1, ULONG info_field_2, ULONG info_field_3, */ +/** ULONG info_field_4, ULONG filter, ULONG time_stamp); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_trace_event_insert: + PUSH {R3-R7,LR} + LDR.N R4,??DataTable2_1 + LDR R4,[R4, #+0] + CMP R4,#+0 + BEQ.N ??_tx_misra_trace_event_insert_0 + LDR.N R5,??DataTable2_2 + LDR R5,[R5, #+0] + LDR R6,[SP, #+28] + TST R5,R6 + BEQ.N ??_tx_misra_trace_event_insert_0 + LDR.N R5,??DataTable2_3 + LDR R5,[R5, #+0] + LDR.N R6,??DataTable2_4 + LDR R6,[R6, #+0] + CMP R5,#+0 + BNE.N ??_tx_misra_trace_event_insert_1 + LDR R5,[R6, #+44] + LDR R7,[R6, #+60] + LSLS R7,R7,#+16 + ORRS R7,R7,#0x80000000 + ORRS R5,R7,R5 + B.N ??_tx_misra_trace_event_insert_2 +??_tx_misra_trace_event_insert_1: + CMP R5,#-252645136 + BCS.N ??_tx_misra_trace_event_insert_3 + MOVS R5,R6 + MOVS R6,#-1 + B.N ??_tx_misra_trace_event_insert_2 +??_tx_misra_trace_event_insert_3: + MOVS R6,#-252645136 + MOVS R5,#+0 +??_tx_misra_trace_event_insert_2: + STR R6,[R4, #+0] + STR R5,[R4, #+4] + STR R0,[R4, #+8] + LDR R0,[SP, #+32] + STR R0,[R4, #+12] + STR R1,[R4, #+16] + STR R2,[R4, #+20] + STR R3,[R4, #+24] + LDR R0,[SP, #+24] + STR R0,[R4, #+28] + ADDS R4,R4,#+32 + LDR.N R0,??DataTable2_5 + LDR R0,[R0, #+0] + CMP R4,R0 + BCC.N ??_tx_misra_trace_event_insert_4 + LDR.N R0,??DataTable2_6 + LDR R4,[R0, #+0] + LDR.N R0,??DataTable2_1 + STR R4,[R0, #+0] + LDR.N R0,??DataTable2_7 + LDR R0,[R0, #+0] + STR R4,[R0, #+32] + LDR.N R0,??DataTable2_8 + LDR R0,[R0, #+0] + CMP R0,#+0 + BEQ.N ??_tx_misra_trace_event_insert_0 + LDR.N R0,??DataTable2_7 + LDR R0,[R0, #+0] + LDR.N R1,??DataTable2_8 + LDR R1,[R1, #+0] + BLX R1 + B.N ??_tx_misra_trace_event_insert_0 +??_tx_misra_trace_event_insert_4: + LDR.N R0,??DataTable2_1 + STR R4,[R0, #+0] + LDR.N R0,??DataTable2_7 + LDR R0,[R0, #+0] + STR R4,[R0, #+32] +??_tx_misra_trace_event_insert_0: + POP {R0,R4-R7,PC} ;; return + + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_1: + DC32 _tx_trace_buffer_current_ptr + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_2: + DC32 _tx_trace_event_enable_bits + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_5: + DC32 _tx_trace_buffer_end_ptr + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_6: + DC32 _tx_trace_buffer_start_ptr + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_7: + DC32 _tx_trace_header_ptr + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_8: + DC32 _tx_trace_full_notify_function + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_time_stamp_get(VOID); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_time_stamp_get: + MOVS R0,#+0 + BX LR ;; return + +#endif + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2: + DC32 0x54485244 + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_3: + DC32 _tx_thread_system_state + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_4: + DC32 _tx_thread_current_ptr + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UINT _tx_misra_always_true(void); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_always_true: + MOVS R0,#+1 + BX LR ;; return + + +/******************************************************************************************/ +/******************************************************************************************/ +/** */ +/** UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr); */ +/** */ +/******************************************************************************************/ +/******************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_indirect_void_to_uchar_pointer_convert: + BX LR ;; return + + +/***************************************************************************************/ +/***************************************************************************************/ +/** */ +/** UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer); */ +/** */ +/***************************************************************************************/ +/***************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_indirect_uchar_pointer_convert: + BX LR ;; return + + +/***********************************************************************************/ +/***********************************************************************************/ +/** */ +/** UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool); */ +/** */ +/***********************************************************************************/ +/***********************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_block_pool_to_uchar_pointer_convert: + BX LR ;; return + + +/******************************************************************************************/ +/******************************************************************************************/ +/** */ +/** TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer); */ +/** */ +/******************************************************************************************/ +/******************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_block_pool_pointer_convert: + BX LR ;; return + + +/*****************************************************************************/ +/*****************************************************************************/ +/** */ +/** UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer); */ +/** */ +/*****************************************************************************/ +/*****************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_uchar_pointer_convert: + BX LR ;; return + + +/************************************************************************************/ +/************************************************************************************/ +/** */ +/** TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer); */ +/** */ +/************************************************************************************/ +/************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_block_pool_pointer_convert: + BX LR ;; return + + +/**************************************************************************************/ +/**************************************************************************************/ +/** */ +/** UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer); */ +/** */ +/**************************************************************************************/ +/**************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_indirect_uchar_pointer_convert: + BX LR ;; return + + +/*****************************************************************************************/ +/*****************************************************************************************/ +/** */ +/** TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer); */ +/** */ +/*****************************************************************************************/ +/*****************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_byte_pool_pointer_convert: + BX LR ;; return + + +/***************************************************************************************/ +/***************************************************************************************/ +/** */ +/** UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool); */ +/** */ +/***************************************************************************************/ +/***************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_byte_pool_to_uchar_pointer_convert: + BX LR ;; return + + +/*****************************************************************************************/ +/*****************************************************************************************/ +/** */ +/** ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer); */ +/** */ +/*****************************************************************************************/ +/*****************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_align_type_pointer_convert: + BX LR ;; return + + +/****************************************************************************************************/ +/****************************************************************************************************/ +/** */ +/** TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer); */ +/** */ +/****************************************************************************************************/ +/****************************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_indirect_byte_pool_pointer_convert: + BX LR ;; return + + +/**************************************************************************************************/ +/**************************************************************************************************/ +/** */ +/** TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer); */ +/** */ +/**************************************************************************************************/ +/**************************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_event_flags_pointer_convert: + BX LR ;; return + + +/*****************************************************************************/ +/*****************************************************************************/ +/** */ +/** ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer); */ +/** */ +/*****************************************************************************/ +/*****************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_ulong_pointer_convert: + BX LR ;; return + + +/********************************************************************************/ +/********************************************************************************/ +/** */ +/** TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer); */ +/** */ +/********************************************************************************/ +/********************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_mutex_pointer_convert: + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UINT _tx_misra_status_get(UINT status); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_status_get: + MOVS R0,#+0 + BX LR ;; return + + +/********************************************************************************/ +/********************************************************************************/ +/** */ +/** TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer); */ +/** */ +/********************************************************************************/ +/********************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_queue_pointer_convert: + BX LR ;; return + + +/****************************************************************************************/ +/****************************************************************************************/ +/** */ +/** TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer); */ +/** */ +/****************************************************************************************/ +/****************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_semaphore_pointer_convert: + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_void_pointer_convert: + BX LR ;; return + + +/*********************************************************************************/ +/*********************************************************************************/ +/** */ +/** TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value); */ +/** */ +/*********************************************************************************/ +/*********************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_ulong_to_thread_pointer_convert: + BX LR ;; return + + +/***************************************************************************************************/ +/***************************************************************************************************/ +/** */ +/** VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer); */ +/** */ +/***************************************************************************************************/ +/***************************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_timer_indirect_to_void_pointer_convert: + BX LR ;; return + + +/***************************************************************************************/ +/***************************************************************************************/ +/** */ +/** CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer); */ +/** */ +/***************************************************************************************/ +/***************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_const_char_to_char_pointer_convert: + BX LR ;; return + + +/**********************************************************************************/ +/**********************************************************************************/ +/** */ +/** TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer); */ +/** */ +/**********************************************************************************/ +/**********************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_thread_pointer_convert: + BX LR ;; return + + +#ifdef TX_ENABLE_EVENT_TRACE + +/************************************************************************************************/ +/************************************************************************************************/ +/** */ +/** UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer); */ +/** */ +/************************************************************************************************/ +/************************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_object_to_uchar_pointer_convert: + BX LR ;; return + + +/************************************************************************************************/ +/************************************************************************************************/ +/** */ +/** TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer); */ +/** */ +/************************************************************************************************/ +/************************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_object_pointer_convert: + BX LR ;; return + + +/******************************************************************************************/ +/******************************************************************************************/ +/** */ +/** TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer); */ +/** */ +/******************************************************************************************/ +/******************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_header_pointer_convert: + BX LR ;; return + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_entry_pointer_convert: + BX LR ;; return + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_entry_to_uchar_pointer_convert: + BX LR ;; return +#endif + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_char_to_uchar_pointer_convert: + BX LR ;; return + + +***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** ULONG _tx_misra_ipsr_get(void); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_ipsr_get: + MRS R0, IPSR + BX LR ;; return + + + SECTION `.iar_vfe_header`:DATA:NOALLOC:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA + DC32 0 + + END diff --git a/ports/cortex_m23/iar/src/tx_thread_context_restore.s b/ports/cortex_m23/iar/src/tx_thread_context_restore.s new file mode 100644 index 00000000..48300c4d --- /dev/null +++ b/ports/cortex_m23/iar/src/tx_thread_context_restore.s @@ -0,0 +1,72 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-M23/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is not needed for Cortex-M. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* None */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + PUBLIC _tx_thread_context_restore +_tx_thread_context_restore: +; +; /* Return to interrupt processing. */ +; + BX lr +;} + END diff --git a/ports/cortex_m23/iar/src/tx_thread_context_save.s b/ports/cortex_m23/iar/src/tx_thread_context_save.s new file mode 100644 index 00000000..f666d4a4 --- /dev/null +++ b/ports/cortex_m23/iar/src/tx_thread_context_save.s @@ -0,0 +1,72 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-M23/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is not needed for Cortex-M. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* None */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + PUBLIC _tx_thread_context_save +_tx_thread_context_save: +; +; /* Return to interrupt processing. */ +; + BX lr +;} + END diff --git a/ports/cortex_m23/iar/src/tx_thread_interrupt_control.s b/ports/cortex_m23/iar/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..83381d72 --- /dev/null +++ b/ports/cortex_m23/iar/src/tx_thread_interrupt_control.s @@ -0,0 +1,77 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-M23/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + PUBLIC _tx_thread_interrupt_control +_tx_thread_interrupt_control: +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r1, PRIMASK + MSR PRIMASK, r0 + MOV r0, r1 + BX lr +; +;} + END diff --git a/ports/cortex_m23/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_m23/iar/src/tx_thread_interrupt_disable.s new file mode 100644 index 00000000..41ad894f --- /dev/null +++ b/ports/cortex_m23/iar/src/tx_thread_interrupt_disable.s @@ -0,0 +1,76 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-M23/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts and returning */ +;/* the previous interrupt lockout posture. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_disable(UINT new_posture) +;{ + PUBLIC _tx_thread_interrupt_disable +_tx_thread_interrupt_disable: +; +; /* Return current interrupt lockout posture. */ +; + MRS r0, PRIMASK + CPSID i + BX lr +; +;} + END diff --git a/ports/cortex_m23/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_m23/iar/src/tx_thread_interrupt_restore.s new file mode 100644 index 00000000..dd1c2985 --- /dev/null +++ b/ports/cortex_m23/iar/src/tx_thread_interrupt_restore.s @@ -0,0 +1,75 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-M23/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for restoring the previous */ +;/* interrupt lockout posture. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* previous_posture Previous interrupt posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_interrupt_restore(UINT new_posture) +;{ + PUBLIC _tx_thread_interrupt_restore +_tx_thread_interrupt_restore: +; +; /* Restore previous interrupt lockout posture. */ +; + MSR PRIMASK, r0 + BX lr +; +;} + END diff --git a/ports/cortex_m23/iar/src/tx_thread_schedule.s b/ports/cortex_m23/iar/src/tx_thread_schedule.s new file mode 100644 index 00000000..53b92102 --- /dev/null +++ b/ports/cortex_m23/iar/src/tx_thread_schedule.s @@ -0,0 +1,336 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_thread_preempt_disable + EXTERN _tx_execution_thread_enter + EXTERN _tx_execution_thread_exit + EXTERN _tx_thread_secure_stack_context_restore + EXTERN _tx_thread_secure_stack_context_save + EXTERN _tx_thread_secure_mode_stack_allocate + EXTERN _tx_thread_secure_mode_stack_free +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-M23/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + PUBLIC _tx_thread_schedule +_tx_thread_schedule: +; +; /* This function should only ever be called on Cortex-M +; from the first schedule request. Subsequent scheduling occurs +; from the PendSV handling routines below. */ +; +; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ +; + MOV r0, #0 ; Build value for TX_FALSE + LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag + STR r0, [r2, #0] ; Clear preempt disable flag +; +; /* Enable interrupts */ +; + CPSIE i +; +; /* Enter the scheduler for the first time. */ +; + LDR r0, =0x10000000 ; Load PENDSVSET bit + LDR r1, =0xE000ED04 ; Load ICSR address + STR r0, [r1] ; Set PENDSVBIT in ICSR + DSB ; Complete all memory accesses + ISB ; Flush pipeline +; +; /* Wait here for the PendSV to take place. */ +; +__tx_wait_here: + B __tx_wait_here ; Wait for the PendSV to happen +;} +; +; /* Generic context switching PendSV handler. */ +; + PUBLIC PendSV_Handler +PendSV_Handler: +; +; /* Get current thread value and new thread pointer. */ +; +__tx_ts_handler: + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + CPSID i ; Disable interrupts + PUSH {r0, lr} ; Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit ; Call the thread exit function + POP {r0, r1} ; Recover LR + MOV lr, r1 ; + CPSIE i ; Enable interrupts +#endif + + MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address + MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address + MOV r3, #0 ; Build NULL value + LDR r1, [r0] ; Pickup current thread pointer +; +; /* Determine if there is a current thread to finish preserving. */ +; + CBZ r1, __tx_ts_new ; If NULL, skip preservation +; +; /* Recover PSP and preserve current thread context. */ +; + STR r3, [r0] ; Set _tx_thread_current_ptr to NULL + MRS r3, PSP ; Pickup PSP pointer (thread's stack pointer) + SUBS r3, r3, #16 ; Allocate stack space + STM r3!, {r4-r7} ; Save its remaining registers (M3 Instruction: STMDB r12!, {r4-r11}) + MOV r4, r8 ; + MOV r5, r9 ; + MOV r6, r10 ; + MOV r7, r11 ; + SUBS r3, r3, #32 ; Allocate stack space + STM r3!, {r4-r7} ; + SUBS r3, r3, #20 ; Allocate stack space + MOV r5, lr ; + STR r5, [r3] ; Save LR on the stack + STR r3, [r1, #8] ; Save its stack pointer + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + ; Save secure context + LDR r5, =0x90 ; Secure stack index offset + LDR r5, [r1, r5] ; Load secure stack index + CBZ r5, _skip_secure_save ; Skip save if there is no secure context + PUSH {r0, r1, r2, r3} ; Save scratch registers + MOV r0, r1 ; Move thread ptr to r0 + BL _tx_thread_secure_stack_context_save ; Save secure stack + POP {r0, r1, r2, r3} ; Restore secure registers +_skip_secure_save: +#endif +; +; /* Determine if time-slice is active. If it isn't, skip time handling processing. */ +; + LDR r4, =_tx_timer_time_slice ; Build address of time-slice variable + LDR r5, [r4] ; Pickup current time-slice + CBZ r5, __tx_ts_new ; If not active, skip processing +; +; /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ +; + STR r5, [r1, #24] ; Save current time-slice +; +; /* Clear the global time-slice. */ +; + MOVS r5, #0 ; Build clear value + STR r5, [r4] ; Clear time-slice +; +; /* Executing thread is now completely preserved!!! */ +; +__tx_ts_new: +; +; /* Now we are looking for a new thread to execute! */ +; + CPSID i ; Disable interrupts + LDR r1, [r2] ; Is there another thread ready to execute? + CBZ r1, __tx_ts_wait ; No, skip to the wait processing +; +; /* Yes, another thread is ready for else, make the current thread the new thread. */ +; + STR r1, [r0] ; Setup the current thread pointer to the new thread + CPSIE i ; Enable interrupts +; +; /* Increment the thread run count. */ +; +__tx_ts_restore: + LDR r7, [r1, #4] ; Pickup the current thread run count + MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable + LDR r5, [r1, #24] ; Pickup thread's current time-slice + ADDS r7, r7, #1 ; Increment the thread run count + STR r7, [r1, #4] ; Store the new run count +; +; /* Setup global time-slice with thread's current time-slice. */ +; + STR r5, [r4] ; Setup global time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + PUSH {r0, r1} ; Save r0/r1 + BL _tx_execution_thread_enter ; Call the thread execution enter function + POP {r0, r1} ; Recover r0/r1 +#endif + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + ; Restore secure context + LDR r5, =0x90 ; Secure stack index offset + LDR r0, [r1, r5] ; Load secure stack index + CBZ r0, _skip_secure_restore ; Skip restore if there is no secure context + PUSH {r0, r1} ; Save r1 (and dummy r0) + MOV r0, r1 ; Move thread ptr to r0 + BL _tx_thread_secure_stack_context_restore ; Restore secure stack + POP {r0, r1} ; Restore r1 (and dummy r0) +_skip_secure_restore: +#endif + +; +; /* Restore the thread context and PSP. */ +; +#ifdef TX_SINGLE_MODE_SECURE + ; There are only stack limit registers in secure mode on the M23 + LDR r3, [r1, #12] ; Get stack start + MSR PSPLIM, r3 ; Set stack limit +#endif + + LDR r3, [r1, #8] ; Pickup thread's stack pointer + LDR r5, [r3] ; Recover saved LR + ADDS r3, r3, #4 ; Position past LR + MOV lr, r5 ; Restore LR + LDM r3!, {r4-r7} ; Recover thread's registers (r4-r11) + MOV r11, r7 ; + MOV r10, r6 ; + MOV r9, r5 ; + MOV r8, r4 ; + LDM r3!, {r4-r7} ; + MSR PSP, r3 ; Setup the thread's stack pointer +; +; /* Return to thread. */ +; + BX lr ; Return to thread! +; +; /* The following is the idle wait processing... in this case, no threads are ready for execution and the +; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +; are disabled to allow use of WFI for waiting for a thread to arrive. */ +; +__tx_ts_wait: + CPSID i ; Disable interrupts + LDR r1, [r2] ; Pickup the next thread to execute pointer + STR r1, [r0] ; Store it in the current pointer + CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready! +#ifdef TX_ENABLE_WFI + DSB ; Ensure no outstanding memory transactions + WFI ; Wait for interrupt + ISB ; Ensure pipeline is flushed +#endif + CPSIE i ; Enable interrupts + B __tx_ts_wait ; Loop to continue waiting +; +; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +; already in the handler! */ +; +__tx_ts_ready: + LDR r7, =0x08000000 ; Build clear PendSV value + LDR r5, =0xE000ED04 ; Build ICSR address + STR r7, [r5] ; Clear any PendSV +; +; /* Re-enable interrupts and restore new thread. */ +; + CPSIE i ; Enable interrupts + B __tx_ts_restore ; Restore the thread + + + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + ; SVC_Handler is not needed when ThreadX is running in single mode. + PUBLIC SVC_Handler +SVC_Handler: + MOVS r0, #4 + MOV r1, lr + TST r1, r0 ; Determine return stack from EXC_RETURN bit 2 + BEQ _tx_get_msp + MRS r0, PSP ; Get PSP if return stack is PSP + B _tx_got_sp +_tx_get_msp: + MRS r0, MSP ; Get MSP if return stack is MSP +_tx_got_sp: + LDR r1, [r0, #24] ; Load saved PC from stack + SUBS r1, r1, #2 ; Calculate SVC number address + LDRB r1, [r1] ; Load SVC number + + CMP r1, #1 ; Is it a secure stack allocate request? + BEQ _tx_svc_secure_alloc ; Yes, go there + + CMP r1, #2 ; Is it a secure stack free request? + BEQ _tx_svc_secure_free ; Yes, go there + + ; Unknown SVC argument - just return + BX lr + +_tx_svc_secure_alloc: + PUSH {r0, lr} ; Save SP and EXC_RETURN + LDM r0, {r0-r3} ; Load function parameters from stack + BL _tx_thread_secure_mode_stack_allocate + POP {r1, r2} ; Restore SP and EXC_RETURN + STR r0, [r1] ; Store function return value + MOV lr, r2 + BX lr +_tx_svc_secure_free: + PUSH {r0, lr} ; Save SP and EXC_RETURN + LDM r0, {r0-r3} ; Load function parameters from stack + BL _tx_thread_secure_mode_stack_free + POP {r1, r2} ; Restore SP and EXC_RETURN + STR r0, [r1] ; Store function return value + MOV lr, r2 + BX lr +#endif ; End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE + + END diff --git a/ports/cortex_m23/iar/src/tx_thread_secure_stack.c b/ports/cortex_m23/iar/src/tx_thread_secure_stack.c new file mode 100644 index 00000000..8cc66628 --- /dev/null +++ b/ports/cortex_m23/iar/src/tx_thread_secure_stack.c @@ -0,0 +1,467 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +#include "tx_api.h" + +/* If TX_SINGLE_MODE_SECURE or TX_SINGLE_MODE_NON_SECURE is defined, + no secure stack functionality is needed. */ +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + +#define TX_SOURCE_CODE + +#include /* For intrinsic functions. */ +#include "tx_secure_interface.h" /* Interface for NS code. */ + +/* Minimum size of secure stack. */ +#ifndef TX_THREAD_SECURE_STACK_MINIMUM +#define TX_THREAD_SECURE_STACK_MINIMUM 256 +#endif +/* Maximum size of secure stack. */ +#ifndef TX_THREAD_SECURE_STACK_MAXIMUM +#define TX_THREAD_SECURE_STACK_MAXIMUM 1024 +#endif + +/* Secure stack info struct to hold stack start, stack limit, + current stack pointer, and pointer to owning thread. + This will be allocated for each thread with a secure stack. */ +typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT +{ + VOID *tx_thread_secure_stack_ptr; /* Thread's secure stack current pointer */ + VOID *tx_thread_secure_stack_start; /* Thread's secure stack start address */ + VOID *tx_thread_secure_stack_limit; /* Thread's secure stack limit */ + TX_THREAD *tx_thread_ptr; /* Keep track of thread for error handling */ +} TX_THREAD_SECURE_STACK_INFO; + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_initialize Cortex-M23/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes secure mode to use PSP stack. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __get_CONTROL Intrinsic to get CONTROL */ +/* __set_CONTROL Intrinsic to set CONTROL */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +void _tx_thread_secure_stack_initialize(void) +{ + + /* Set secure mode to use PSP. */ + __set_CONTROL(__get_CONTROL() | 2); + + /* Set process stack pointer and stack limit to 0 to throw exception when a thread + without a secure stack calls a secure function that tries to use secure stack. */ + __set_PSPLIM(0); + __set_PSP(0); + + return; +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_mode_stack_allocate Cortex-M23/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function allocates a thread's secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* stack_size Size of stack to allocates */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_SIZE_ERROR Invalid stack size */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* calloc Compiler's calloc function */ +/* malloc Compiler's malloc function */ +/* free Compiler's free() function */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* __TZ_get_PSPLIM_NS Intrinsic to get NS PSP */ +/* */ +/* CALLED BY */ +/* */ +/* SVC Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +{ +UINT status; +TX_THREAD_SECURE_STACK_INFO *info_ptr; +UCHAR *stack_mem; +ULONG sp; + + status = TX_SUCCESS; + + /* Make sure function is called from interrupt (threads should not call). */ + if (__get_IPSR() == 0) + { + status = TX_CALLER_ERROR; + } + else if (stack_size < TX_THREAD_SECURE_STACK_MINIMUM || stack_size > TX_THREAD_SECURE_STACK_MAXIMUM) + { + status = TX_SIZE_ERROR; + } + + /* Check if thread already has secure stack allocated. */ + else if (thread_ptr -> tx_thread_secure_stack_context != 0) + { + status = TX_THREAD_ERROR; + } + + else + { + /* Allocate space for secure stack info. */ + info_ptr = calloc(1, sizeof(TX_THREAD_SECURE_STACK_INFO)); + + if(info_ptr != TX_NULL) + { + /* If stack info allocated, allocate a stack. */ + stack_mem = malloc(stack_size); + + if(stack_mem != TX_NULL) + { + /* Secure stack has been allocated, save in the stack info struct. */ + info_ptr -> tx_thread_secure_stack_limit = stack_mem; + info_ptr -> tx_thread_secure_stack_start = stack_mem + stack_size; + info_ptr -> tx_thread_secure_stack_ptr = info_ptr -> tx_thread_secure_stack_start; + info_ptr -> tx_thread_ptr = thread_ptr; + + /* Save info pointer in thread. */ + thread_ptr -> tx_thread_secure_stack_context = info_ptr; + + /* Check if this thread is running by looking at PSP_NS and seeing if it is within + the stack_start and stack_end range. */ + sp = __TZ_get_PSP_NS(); + if(sp > ((ULONG) thread_ptr -> tx_thread_stack_start) && sp < ((ULONG) thread_ptr -> tx_thread_stack_end)) + { + /* If this thread is running, set Secure PSP and PSPLIM. */ + __set_PSPLIM((ULONG)(info_ptr -> tx_thread_secure_stack_limit)); + __set_PSP((ULONG)(info_ptr -> tx_thread_secure_stack_ptr)); + } + } + + else + { + /* Stack not allocated, free the info struct. */ + free(info_ptr); + status = TX_NO_MEMORY; + } + } + + else + { + status = TX_NO_MEMORY; + } + } + + return(status); +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_mode_stack_free Cortex-M23/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function frees a thread's secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* free Compiler's free() function */ +/* */ +/* CALLED BY */ +/* */ +/* SVC Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr) +{ +UINT status; +TX_THREAD_SECURE_STACK_INFO *info_ptr; + + status = TX_SUCCESS; + + /* Pickup stack info from thread. */ + info_ptr = thread_ptr -> tx_thread_secure_stack_context; + + /* Make sure function is called from interrupt (threads should not call). */ + if (__get_IPSR() == 0) + { + status = TX_CALLER_ERROR; + } + + /* Check that this secure context is for this thread. */ + else if (info_ptr -> tx_thread_ptr != thread_ptr) + { + status = TX_THREAD_ERROR; + } + + else + { + + /* Free secure stack. */ + free(info_ptr -> tx_thread_secure_stack_limit); + + /* Free info struct. */ + free(info_ptr); + + /* Clear secure context from thread. */ + thread_ptr -> tx_thread_secure_stack_context = 0; + } + + return(status); +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_context_save Cortex-M23/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves context of the secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* __get_PSP Intrinsic to get PSP */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* */ +/* CALLED BY */ +/* */ +/* PendSV Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr) +{ +TX_THREAD_SECURE_STACK_INFO *info_ptr; +ULONG sp; + + /* This function should be called from scheduler only. */ + if (__get_IPSR() == 0) + { + return; + } + + /* Pickup the secure context pointer. */ + info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); + + /* Check that this secure context is for this thread. */ + if (info_ptr -> tx_thread_ptr != thread_ptr) + { + return; + } + + /* Check that stack pointer is in range */ + sp = __get_PSP(); + if ((sp < (ULONG)info_ptr -> tx_thread_secure_stack_limit) || + (sp > (ULONG)info_ptr -> tx_thread_secure_stack_start)) + { + return; + } + + /* Save stack pointer. */ + *(ULONG *) info_ptr -> tx_thread_secure_stack_ptr = sp; + + /* Set process stack pointer and stack limit to 0 to throw exception when a thread + without a secure stack calls a secure function that tries to use secure stack. */ + __set_PSPLIM(0); + __set_PSP(0); + + return; +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_context_restore Cortex-M23/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores context of the secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* */ +/* CALLED BY */ +/* */ +/* PendSV Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr) +{ +TX_THREAD_SECURE_STACK_INFO *info_ptr; + + /* This function should be called from scheduler only. */ + if (__get_IPSR() == 0) + { + return; + } + + /* Pickup the secure context pointer. */ + info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); + + /* Check that this secure context is for this thread. */ + if (info_ptr -> tx_thread_ptr != thread_ptr) + { + return; + } + + /* Set stack pointer and limit. */ + __set_PSPLIM((ULONG)info_ptr -> tx_thread_secure_stack_limit); + __set_PSP ((ULONG)info_ptr -> tx_thread_secure_stack_ptr); + + return; +} + +#endif diff --git a/ports/cortex_m23/iar/src/tx_thread_secure_stack_allocate.s b/ports/cortex_m23/iar/src/tx_thread_secure_stack_allocate.s new file mode 100644 index 00000000..9ae3dcdb --- /dev/null +++ b/ports/cortex_m23/iar/src/tx_thread_secure_stack_allocate.s @@ -0,0 +1,82 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_secure_stack_allocate Cortex-M23/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function enters the SVC handler to allocate a secure stack. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Thread control block pointer */ +;/* stack_size Size of secure stack to */ +;/* allocate */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* status Actual completion status */ +;/* */ +;/* CALLS */ +;/* */ +;/* SVC 1 */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +;{ + EXPORT _tx_thread_secure_stack_allocate +_tx_thread_secure_stack_allocate: +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + MRS r3, PRIMASK ; Save interrupt mask + CPSIE i ; Enable interrupts for SVC call + SVC 1 + CMP r3, #0 ; If interrupts enabled, just return + BEQ _alloc_return_interrupt_enabled + CPSID i ; Otherwise, disable interrupts +#else + MOV32 r0, #0xFF ; Feature not enabled +#endif +_alloc_return_interrupt_enabled + BX lr + + END diff --git a/ports/cortex_m23/iar/src/tx_thread_secure_stack_free.s b/ports/cortex_m23/iar/src/tx_thread_secure_stack_free.s new file mode 100644 index 00000000..b8e5bef8 --- /dev/null +++ b/ports/cortex_m23/iar/src/tx_thread_secure_stack_free.s @@ -0,0 +1,79 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_secure_stack_free Cortex-M23/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function enters the SVC handler to free a secure stack. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Thread control block pointer */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* status Actual completion status */ +;/* */ +;/* CALLS */ +;/* */ +;/* SVC 2 */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) +;{ + EXPORT _tx_thread_secure_stack_free +_tx_thread_secure_stack_free: +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + MRS r3, PRIMASK ; Save interrupt mask + CPSIE i ; Enable interrupts for SVC call + SVC 2 + CMP r3, #0 ; If interrupts enabled, just return + BEQ _free_return_interrupt_enabled + CPSID i ; Otherwise, disable interrupts +#else + MOV32 r0, #0xFF ; Feature not enabled +#endif +_free_return_interrupt_enabled + BX lr + END diff --git a/ports/cortex_m23/iar/src/tx_thread_stack_build.s b/ports/cortex_m23/iar/src/tx_thread_stack_build.s new file mode 100644 index 00000000..6525df4a --- /dev/null +++ b/ports/cortex_m23/iar/src/tx_thread_stack_build.s @@ -0,0 +1,138 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-M23/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + PUBLIC _tx_thread_stack_build +_tx_thread_stack_build: +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-M23 should look like the following after it is built: +; +; Stack Top: +; LR Interrupted LR (LR at time of PENDSV) +; r8 Initial value for r8 +; r9 Initial value for r9 +; r10 Initial value for r10 +; r11 Initial value for r11 +; r4 Initial value for r4 +; r5 Initial value for r5 +; r6 Initial value for r6 +; r7 Initial value for r7 +; r0 Initial value for r0 (Hardware stack starts here!!) +; r1 Initial value for r1 +; r2 Initial value for r2 +; r3 Initial value for r3 +; r12 Initial value for r12 +; lr Initial value for lr +; pc Initial value for pc +; xPSR Initial value for xPSR +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + MOVS r3, #0x7 ; + BICS r2, r2, r3 ; Align frame for 8-byte alignment + SUBS r2, r2, #68 ; Subtract frame size +#ifdef TX_SINGLE_MODE_SECURE + LDR r3, =0xFFFFFFFD ; Build initial LR value for secure mode +#else + LDR r3, =0xFFFFFFBC ; Build initial LR value to return to non-secure PSP +#endif + STR r3, [r2, #0] ; Save on the stack +; +; /* Actually build the stack frame. */ +; + MOV r3, #0 ; Build initial register value + STR r3, [r2, #4] ; Store initial r8 + STR r3, [r2, #8] ; Store initial r9 + STR r3, [r2, #12] ; Store initial r10 + STR r3, [r2, #16] ; Store initial r11 + STR r3, [r2, #20] ; Store initial r4 + STR r3, [r2, #24] ; Store initial r5 + STR r3, [r2, #28] ; Store initial r6 + STR r3, [r2, #32] ; Store initial r7 +; +; /* Hardware stack follows. */ +; + STR r3, [r2, #36] ; Store initial r0 + STR r3, [r2, #40] ; Store initial r1 + STR r3, [r2, #44] ; Store initial r2 + STR r3, [r2, #48] ; Store initial r3 + STR r3, [r2, #52] ; Store initial r12 + LDR r3, =0xFFFFFFFF ; Poison EXC_RETURN value + STR r3, [r2, #56] ; Store initial lr + STR r1, [r2, #60] ; Store initial pc + LDR r3, =0x01000000 ; Only T-bit need be set + STR r3, [r2, #64] ; Store initial xPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block + BX lr ; Return to caller +;} + END diff --git a/ports/cortex_m23/iar/src/tx_thread_stack_error_handler.c b/ports/cortex_m23/iar/src/tx_thread_stack_error_handler.c new file mode 100644 index 00000000..ef98240c --- /dev/null +++ b/ports/cortex_m23/iar/src/tx_thread_stack_error_handler.c @@ -0,0 +1,93 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + +/* Define the global function pointer for stack error handling. If a stack error is + detected and the application has registered a stack error handler, it will be + called via this function pointer. */ + +VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_error_handler Cortex-M23 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes stack errors detected during run-time. */ +/* */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_terminate */ +/* _tx_thread_application_stack_error_handler */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX internal code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) +{ + #ifndef TX_THREAD_NO_TERMINATE_STACK_ERROR + /* Is there a thread? */ + if (thread_ptr) + { + /* Terminate the current thread. */ + _tx_thread_terminate(_tx_thread_current_ptr); + } + #endif + + /* Determine if the application has registered an error handler. */ + if (_tx_thread_application_stack_error_handler != TX_NULL) + { + /* Yes, an error handler is present, simply call the application error handler. */ + (_tx_thread_application_stack_error_handler)(thread_ptr); + } +} diff --git a/ports/cortex_m23/iar/src/tx_thread_stack_error_notify.c b/ports/cortex_m23/iar/src/tx_thread_stack_error_notify.c new file mode 100644 index 00000000..ffd78d08 --- /dev/null +++ b/ports/cortex_m23/iar/src/tx_thread_stack_error_notify.c @@ -0,0 +1,96 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_trace.h" + +extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_error_notify Cortex-M23 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application stack error handler. If */ +/* ThreadX detects a stack error, this application handler is called. */ +/* */ +/* */ +/* INPUT */ +/* */ +/* stack_error_handler Pointer to stack error */ +/* handler, TX_NULL to disable */ +/* */ +/* OUTPUT */ +/* */ +/* status Service return status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr)) +{ + +TX_INTERRUPT_SAVE_AREA + + /* Disable interrupts. */ + TX_DISABLE + + /* Make entry in event log. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_STACK_ERROR_NOTIFY, 0, 0, 0, 0, TX_TRACE_THREAD_EVENTS) + + /* Make entry in event log. */ + TX_EL_THREAD_STACK_ERROR_NOTIFY_INSERT + + /* Setup global thread stack error handler. */ + _tx_thread_application_stack_error_handler = stack_error_handler; + + /* Restore interrupts. */ + TX_RESTORE + + /* Return success to caller. */ + return(TX_SUCCESS); +} diff --git a/ports/cortex_m23/iar/src/tx_thread_system_return.s b/ports/cortex_m23/iar/src/tx_thread_system_return.s new file mode 100644 index 00000000..1afb41f6 --- /dev/null +++ b/ports/cortex_m23/iar/src/tx_thread_system_return.s @@ -0,0 +1,87 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-M23/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + PUBLIC _tx_thread_system_return +_tx_thread_system_return??rA: +_tx_thread_system_return: +; +; /* Return to real scheduler via PendSV. Note that this routine is often +; replaced with in-line assembly in tx_port.h to improved performance. */ +; + LDR r0, =0x10000000 ; Load PENDSVSET bit + LDR r1, =0xE000ED04 ; Load ICSR address + STR r0, [r1] ; Set PENDSVBIT in ICSR + MRS r0, IPSR ; Pickup IPSR + CMP r0, #0 ; Is it a thread returning? + BNE _isr_context ; If ISR, skip interrupt enable + MRS r1, PRIMASK ; Thread context returning, pickup PRIMASK + CPSIE i ; Enable interrupts + MSR PRIMASK, r1 ; Restore original interrupt posture +_isr_context: + BX lr ; Return to caller +;} + END diff --git a/ports/cortex_m23/iar/src/tx_timer_interrupt.s b/ports/cortex_m23/iar/src/tx_timer_interrupt.s new file mode 100644 index 00000000..89e185b3 --- /dev/null +++ b/ports/cortex_m23/iar/src/tx_timer_interrupt.s @@ -0,0 +1,256 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + EXTERN _tx_timer_time_slice + EXTERN _tx_timer_system_clock + EXTERN _tx_timer_current_ptr + EXTERN _tx_timer_list_start + EXTERN _tx_timer_list_end + EXTERN _tx_timer_expired_time_slice + EXTERN _tx_timer_expired + EXTERN _tx_thread_time_slice + EXTERN _tx_timer_expiration_process + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_thread_preempt_disable +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-M23/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* the expiration functions are called. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + PUBLIC _tx_timer_interrupt +_tx_timer_interrupt: +; +; /* Upon entry to this routine, it is assumed that the compiler scratch registers are available +; for use. */ +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + MOV32 r1, _tx_timer_system_clock ; Pickup address of system clock + LDR r0, [r1, #0] ; Pickup system clock + ADDS r0, r0, #1 ; Increment system clock + STR r0, [r1, #0] ; Store new system clock +; +; /* Test for time-slice expiration. */ +; if (_tx_timer_time_slice) +; { +; + MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice + LDR r2, [r3, #0] ; Pickup time-slice + CBZ r2, __tx_timer_no_time_slice ; Is it non-active? + ; Yes, skip time-slice processing +; +; /* Decrement the time_slice. */ +; _tx_timer_time_slice--; +; + SUBS r2, r2, #1 ; Decrement the time-slice + STR r2, [r3, #0] ; Store new time-slice value +; +; /* Check for expiration. */ +; if (__tx_timer_time_slice == 0) +; + CBNZ r2, __tx_timer_no_time_slice ; Has it expired? +; +; /* Set the time-slice expired flag. */ +; _tx_timer_expired_time_slice = TX_TRUE; +; + MOV32 r3, _tx_timer_expired_time_slice ; Pickup address of expired flag + MOV r0, #1 ; Build expired value + STR r0, [r3, #0] ; Set time-slice expiration flag +; +; } +; +__tx_timer_no_time_slice: +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + MOV32 r1, _tx_timer_current_ptr ; Pickup current timer pointer address + LDR r0, [r1, #0] ; Pickup current timer + LDR r2, [r0, #0] ; Pickup timer list entry + CBZ r2, __tx_timer_no_timer ; Is there anything in the list? + ; No, just increment the timer +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + MOV32 r3, _tx_timer_expired ; Pickup expiration flag address + MOV r2, #1 ; Build expired value + STR r2, [r3, #0] ; Set expired flag + B __tx_timer_done ; Finished timer processing +; +; } +; else +; { +__tx_timer_no_timer: +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ADDS r0, r0, #4 ; Move to next timer +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + MOV32 r3, _tx_timer_list_end ; Pickup addr of timer list end + LDR r2, [r3, #0] ; Pickup list end + CMP r0, r2 ; Are we at list end? + BNE __tx_timer_skip_wrap ; No, skip wrap-around logic +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + MOV32 r3, _tx_timer_list_start ; Pickup addr of timer list start + LDR r0, [r3, #0] ; Set current pointer to list start +; +__tx_timer_skip_wrap: +; + STR r0, [r1, #0] ; Store new current timer pointer +; } +; +__tx_timer_done: +; +; +; /* See if anything has expired. */ +; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +; { +; + MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of expired flag + LDR r2, [r3, #0] ; Pickup time-slice expired flag + CBNZ r2, __tx_something_expired ; Did a time-slice expire? + ; If non-zero, time-slice expired + MOV32 r1, _tx_timer_expired ; Pickup addr of other expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CBZ r0, __tx_timer_nothing_expired ; Did a timer expire? + ; No, nothing expired +; +__tx_something_expired: +; +; + STMDB sp!, {r0, lr} ; Save the lr register on the stack + ; and save r0 just to keep 8-byte alignment +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + MOV32 r1, _tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CBZ r0, __tx_timer_dont_activate ; Check for timer expiration + ; If not set, skip timer activation +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + BL _tx_timer_expiration_process ; Call the timer expiration handling routine +; +; } +__tx_timer_dont_activate: +; +; /* Did time slice expire? */ +; if (_tx_timer_expired_time_slice) +; { +; + MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r2, [r3, #0] ; Pickup the actual flag + CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set + ; No, skip time-slice processing +; +; /* Time slice interrupted thread. */ +; _tx_thread_time_slice(); + + BL _tx_thread_time_slice ; Call time-slice processing + MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag + LDR r1, [r0] ; Is the preempt disable flag set? + CBNZ r1, __tx_timer_skip_time_slice ; Yes, skip the PendSV logic + MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup the current thread pointer + MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address + LDR r3, [r2] ; Pickup the execute thread pointer + MOV32 r0, 0xE000ED04 ; Build address of control register + MOV32 r2, 0x10000000 ; Build value for PendSV bit + CMP r1, r3 ; Are they the same? + BEQ __tx_timer_skip_time_slice ; If the same, there was no time-slice performed + STR r2, [r0] ; Not the same, issue the PendSV for preemption +__tx_timer_skip_time_slice: +; +; } +; +__tx_timer_not_ts_expiration: +; + POP {r0, r1} ; Recover lr register (r0 is just there for + MOV lr, r1 ; the 8-byte stack alignment +; +; } +; +__tx_timer_nothing_expired: + + DSB ; Complete all memory access + BX lr ; Return to caller +; +;} + END diff --git a/ports/cortex_m23/iar/src/txe_thread_secure_stack_allocate.c b/ports/cortex_m23/iar/src/txe_thread_secure_stack_allocate.c new file mode 100644 index 00000000..35482b6c --- /dev/null +++ b/ports/cortex_m23/iar/src/txe_thread_secure_stack_allocate.c @@ -0,0 +1,119 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_secure_stack_allocate Cortex-M23 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the secure stack allocate */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* stack_size Size of secure stack to */ +/* allocate */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_secure_stack_allocate Actual stack alloc function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +{ +#if defined(TX_SINGLE_MODE_SECURE) || defined(TX_SINGLE_MODE_NON_SECURE) + return(TX_FEATURE_NOT_ENABLED); +#else +UINT status; + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid thread pointer. */ + if (thread_ptr == TX_NULL) + { + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Now check for invalid thread ID. */ + else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) + { + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Check for interrupt call. */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + /* Is call from an interrupt and not initialization? */ + if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS) + { + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + /* Call actual secure stack allocate function. */ + status = _tx_thread_secure_stack_allocate(thread_ptr, stack_size); + } + + /* Return completion status. */ + return(status); +#endif +} diff --git a/ports/cortex_m23/iar/src/txe_thread_secure_stack_free.c b/ports/cortex_m23/iar/src/txe_thread_secure_stack_free.c new file mode 100644 index 00000000..950e8ec0 --- /dev/null +++ b/ports/cortex_m23/iar/src/txe_thread_secure_stack_free.c @@ -0,0 +1,120 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_secure_stack_free Cortex-M23 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the secure stack free */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_secure_stack_free Actual stack free function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) +{ +#if defined(TX_SINGLE_MODE_SECURE) || defined(TX_SINGLE_MODE_NON_SECURE) + return(TX_FEATURE_NOT_ENABLED); +#else +UINT status; + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid thread pointer. */ + if (thread_ptr == TX_NULL) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Now check for invalid thread ID. */ + else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Check for interrupt call. */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + /* Is call from an interrupt and not initialization? */ + if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS) + { + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + + /* Call actual secure stack allocate function. */ + status = _tx_thread_secure_stack_free(thread_ptr); + } + + /* Return completion status. */ + return(status); +#endif +} diff --git a/ports/cortex_m3/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_m3/ac5/example_build/tx_initialize_low_level.s index 04ddfc47..27a8ae29 100644 --- a/ports/cortex_m3/ac5/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m3/ac5/example_build/tx_initialize_low_level.s @@ -94,7 +94,7 @@ Reset_Handler ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level Cortex-M3/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -127,10 +127,7 @@ Reset_Handler ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_m3/ac5/inc/tx_port.h b/ports/cortex_m3/ac5/inc/tx_port.h index 259deceb..b68f3659 100644 --- a/ports/cortex_m3/ac5/inc/tx_port.h +++ b/ports/cortex_m3/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M3/AC5 */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -329,7 +329,7 @@ unsigned int was_masked; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/AC5 Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/AC5 Version 6.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m3/ac5/readme_threadx.txt b/ports/cortex_m3/ac5/readme_threadx.txt index f428a26f..43e0057b 100644 --- a/ports/cortex_m3/ac5/readme_threadx.txt +++ b/ports/cortex_m3/ac5/readme_threadx.txt @@ -135,12 +135,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -08-14-2020 ThreadX update of Cortex-M3/AC5 port. The following files were - changed/added for port specific version 6.0.2: - - *.s Modified comments and whitespace. - -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M3 using AC5 tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-M3 using AC5 tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_m3/ac5/src/tx_thread_context_restore.s b/ports/cortex_m3/ac5/src/tx_thread_context_restore.s index 67731bce..14b1da0e 100644 --- a/ports/cortex_m3/ac5/src/tx_thread_context_restore.s +++ b/ports/cortex_m3/ac5/src/tx_thread_context_restore.s @@ -33,7 +33,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore Cortex-M3/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -67,10 +67,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m3/ac5/src/tx_thread_context_save.s b/ports/cortex_m3/ac5/src/tx_thread_context_save.s index f11b9a70..ae21c768 100644 --- a/ports/cortex_m3/ac5/src/tx_thread_context_save.s +++ b/ports/cortex_m3/ac5/src/tx_thread_context_save.s @@ -33,7 +33,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save Cortex-M3/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -66,10 +66,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m3/ac5/src/tx_thread_interrupt_control.s b/ports/cortex_m3/ac5/src/tx_thread_interrupt_control.s index 22ad0fb7..3c0f1768 100644 --- a/ports/cortex_m3/ac5/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m3/ac5/src/tx_thread_interrupt_control.s @@ -27,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control Cortex-M3/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -57,10 +57,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_m3/ac5/src/tx_thread_interrupt_disable.s b/ports/cortex_m3/ac5/src/tx_thread_interrupt_disable.s index 6fe29368..d66a11f0 100644 --- a/ports/cortex_m3/ac5/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m3/ac5/src/tx_thread_interrupt_disable.s @@ -27,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_disable Cortex-M3/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -57,10 +57,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(UINT new_posture) diff --git a/ports/cortex_m3/ac5/src/tx_thread_interrupt_restore.s b/ports/cortex_m3/ac5/src/tx_thread_interrupt_restore.s index e27d5cfc..361af42f 100644 --- a/ports/cortex_m3/ac5/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m3/ac5/src/tx_thread_interrupt_restore.s @@ -27,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-M3/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -57,10 +57,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(UINT new_posture) diff --git a/ports/cortex_m3/ac5/src/tx_thread_schedule.s b/ports/cortex_m3/ac5/src/tx_thread_schedule.s index c4e749b5..c0753dfe 100644 --- a/ports/cortex_m3/ac5/src/tx_thread_schedule.s +++ b/ports/cortex_m3/ac5/src/tx_thread_schedule.s @@ -39,7 +39,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M3/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -72,10 +72,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_m3/ac5/src/tx_thread_stack_build.s b/ports/cortex_m3/ac5/src/tx_thread_stack_build.s index 8c3d7d17..0e0e1c9d 100644 --- a/ports/cortex_m3/ac5/src/tx_thread_stack_build.s +++ b/ports/cortex_m3/ac5/src/tx_thread_stack_build.s @@ -15,15 +15,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; ; AREA ||.text||, CODE, READONLY ;/**************************************************************************/ @@ -31,7 +22,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build Cortex-M3/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -63,10 +54,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -117,7 +105,7 @@ _tx_thread_stack_build STR r3, [r2, #28] ; Store initial r10 STR r3, [r2, #32] ; Store initial r11 ; -; /* Hardware stack follows. / +; /* Hardware stack follows. */ ; STR r3, [r2, #36] ; Store initial r0 STR r3, [r2, #40] ; Store initial r1 diff --git a/ports/cortex_m3/ac5/src/tx_thread_system_return.s b/ports/cortex_m3/ac5/src/tx_thread_system_return.s index b097896c..4988ce82 100644 --- a/ports/cortex_m3/ac5/src/tx_thread_system_return.s +++ b/ports/cortex_m3/ac5/src/tx_thread_system_return.s @@ -22,7 +22,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return Cortex-M3/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -54,10 +54,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_m3/ac5/src/tx_timer_interrupt.s b/ports/cortex_m3/ac5/src/tx_timer_interrupt.s index ef7a55f4..8c20a222 100644 --- a/ports/cortex_m3/ac5/src/tx_timer_interrupt.s +++ b/ports/cortex_m3/ac5/src/tx_timer_interrupt.s @@ -37,7 +37,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt Cortex-M3/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -71,10 +71,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_m3/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_m3/ac6/example_build/sample_threadx/tx_initialize_low_level.S index c04e3f81..46190007 100644 --- a/ports/cortex_m3/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports/cortex_m3/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -47,7 +47,7 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* FUNCTION RELEASE */ @/* */ @/* _tx_initialize_low_level Cortex-M3/AC6 */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -80,10 +80,7 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_m3/ac6/inc/tx_port.h b/ports/cortex_m3/ac6/inc/tx_port.h index fcf9412f..71b052e8 100644 --- a/ports/cortex_m3/ac6/inc/tx_port.h +++ b/ports/cortex_m3/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M3/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -343,7 +343,7 @@ unsigned int interrupt_save; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/AC6 Version 6.0.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/AC6 Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_m3/ac6/readme_threadx.txt b/ports/cortex_m3/ac6/readme_threadx.txt index 828e24da..a9383f96 100644 --- a/ports/cortex_m3/ac6/readme_threadx.txt +++ b/ports/cortex_m3/ac6/readme_threadx.txt @@ -146,12 +146,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -08-14-2020 ThreadX update of Cortex-M3/AC6 port. The following files were - changed/added for port specific version 6.0.2: - - *.S Modified comments and whitespace. - -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M3 using AC6 tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-M3 using AC6 tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_m3/ac6/src/tx_thread_context_restore.S b/ports/cortex_m3/ac6/src/tx_thread_context_restore.S index 90afa28c..db417745 100644 --- a/ports/cortex_m3/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_m3/ac6/src/tx_thread_context_restore.S @@ -38,7 +38,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_restore Cortex-M3/AC6 */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -72,10 +72,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m3/ac6/src/tx_thread_context_save.S b/ports/cortex_m3/ac6/src/tx_thread_context_save.S index 35ebcdd3..e6acd5bb 100644 --- a/ports/cortex_m3/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_m3/ac6/src/tx_thread_context_save.S @@ -33,7 +33,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_save Cortex-M3/AC6 */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -66,10 +66,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m3/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_m3/ac6/src/tx_thread_interrupt_control.S index 0ab24fa8..ce0f19de 100644 --- a/ports/cortex_m3/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m3/ac6/src/tx_thread_interrupt_control.S @@ -29,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_control Cortex-M3/AC6 */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -59,10 +59,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @/* UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_m3/ac6/src/tx_thread_schedule.S b/ports/cortex_m3/ac6/src/tx_thread_schedule.S index bf30619e..526bfd35 100644 --- a/ports/cortex_m3/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_m3/ac6/src/tx_thread_schedule.S @@ -35,7 +35,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule Cortex-M3/AC6 */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -68,10 +68,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) @@ -241,4 +238,3 @@ __tx_ts_ready: @ CPSIE i @ Enable interrupts B __tx_ts_restore @ Restore the thread - diff --git a/ports/cortex_m3/ac6/src/tx_thread_stack_build.S b/ports/cortex_m3/ac6/src/tx_thread_stack_build.S index a6740472..5643695f 100644 --- a/ports/cortex_m3/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_m3/ac6/src/tx_thread_stack_build.S @@ -29,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_stack_build Cortex-M3/AC6 */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -61,10 +61,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_m3/ac6/src/tx_thread_system_return.S b/ports/cortex_m3/ac6/src/tx_thread_system_return.S index bb24456d..cccfcb9c 100644 --- a/ports/cortex_m3/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_m3/ac6/src/tx_thread_system_return.S @@ -29,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_system_return Cortex-M3/AC6 */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -61,10 +61,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @/* VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_m3/ac6/src/tx_timer_interrupt.S b/ports/cortex_m3/ac6/src/tx_timer_interrupt.S index 060b7f9e..35edc665 100644 --- a/ports/cortex_m3/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_m3/ac6/src/tx_timer_interrupt.S @@ -40,7 +40,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_timer_interrupt Cortex-M3/AC6 */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -74,10 +74,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_m3/ghs/example_build/azure_rtos_workspace.gpj b/ports/cortex_m3/ghs/example_build/azure_rtos_workspace.gpj new file mode 100644 index 00000000..ace2bd46 --- /dev/null +++ b/ports/cortex_m3/ghs/example_build/azure_rtos_workspace.gpj @@ -0,0 +1,12 @@ +#!gbuild +primaryTarget=arm_standalone.tgt +[Project] + -bsp generic + -G + -littleendian + -cpu=cortexm3 +sample_threadx.gpj [Program] +sample_threadx_el.gpj [Program] +tx.gpj [Library] +txe.gpj [Library] +..\readme_threadx.txt diff --git a/ports/cortex_m3/ghs/example_build/reset.arm b/ports/cortex_m3/ghs/example_build/reset.arm new file mode 100644 index 00000000..09d288c4 --- /dev/null +++ b/ports/cortex_m3/ghs/example_build/reset.arm @@ -0,0 +1,40 @@ +# +# +#/* Define the Cortex-M3 vector area. */ +# + + .section ".reset", .text + .globl __vectors +__vectors: + .data.w __ghsend_stack # Reset and system stack ptr + .data.w __Reset_Handler # Reset goes to Reset Handler + .data.w __tx_NMIHandler # NMI + .data.w __tx_BadHandler # HardFault + .data.w 0 # MemManage + .data.w 0 # BusFault + .data.w 0 # UsageFault + .data.w 0 # 7 + .data.w 0 # 8 + .data.w 0 # 9 + .data.w 0 # 10 + .data.w __tx_SVCallHandler # SVCall + .data.w __tx_DBGHandler # Monitor + .data.w 0 # 13 + .data.w __tx_PendSVHandler # PendSV + .data.w __tx_SysTickHandler # SysTick + .data.w __tx_IntHandler # Int 0 + .data.w __tx_IntHandler # Int 1 + .data.w __tx_IntHandler # Int 2 + .data.w __tx_IntHandler # Int 3 + .type __vectors,$object + .size __vectors,.-__vectors +# +# + .globl __Reset_Handler +__Reset_Handler: + CPSID i # Disable interrupts + LDR r0,=_start # Build address of GHS startup code + BX r0 # Enter GHS startup + + .type __Reset_Handler,$function + .size __Reset_Handler,.-__Reset_Handler diff --git a/ports/cortex_m3/ghs/example_build/sample_threadx.c b/ports/cortex_m3/ghs/example_build/sample_threadx.c new file mode 100644 index 00000000..418ec634 --- /dev/null +++ b/ports/cortex_m3/ghs/example_build/sample_threadx.c @@ -0,0 +1,369 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_m3/ghs/example_build/sample_threadx.con b/ports/cortex_m3/ghs/example_build/sample_threadx.con new file mode 100644 index 00000000..1178f4be --- /dev/null +++ b/ports/cortex_m3/ghs/example_build/sample_threadx.con @@ -0,0 +1,17 @@ +target_connection { + { + title = "Simulator" + type = "Custom" + short_type = "Custom" + args = "simarm -cpu=cortexm3 -rom_use_entry" + command = "simarm -cpu=cortexm3 -rom_use_entry" + logfile = "" + mode = "" + setup_script = "" + run_mode_partner = "" + run_mode_policy = "" + sane = "yes" + log = "no" + timestamp = "0" + } +} diff --git a/ports/cortex_m3/ghs/example_build/sample_threadx.gpj b/ports/cortex_m3/ghs/example_build/sample_threadx.gpj new file mode 100644 index 00000000..b9b2c04c --- /dev/null +++ b/ports/cortex_m3/ghs/example_build/sample_threadx.gpj @@ -0,0 +1,11 @@ +#!gbuild +[Program] + -I../../../../common/inc + -I../../../../ports_common_green/inc + -I../inc +reset.arm +tx_initialize_low_level.arm +sample_threadx.c +tx.a +sample_threadx.ld +sample_threadx.con diff --git a/ports/cortex_m3/ghs/example_build/sample_threadx.ld b/ports/cortex_m3/ghs/example_build/sample_threadx.ld new file mode 100644 index 00000000..a5cfce73 --- /dev/null +++ b/ports/cortex_m3/ghs/example_build/sample_threadx.ld @@ -0,0 +1,45 @@ +# The following explains what the default Green Hills sections are for: +# +# picbase - base of the text sections, relocatable in -pic mode +# text - text section +# syscall - syscall section, for host I/O under Multi +# fixaddr/fixtype - for PIC/PID fixups +# rodata - read only data +# romdata - the ROM image of .data +# romsdata - the ROM image of .sdata +# secinfo - section information section, used by the start-up code +# pidbase - base of the data sections, relocatable in -pid mode +# sdabase - base of the small data area section pointer +# sbss - small BSS (zeroed data) section +# sdata - small data section +# data - non-zeroed writeable data section +# bss - zeroed data section +# heap - the heap, grows upward +# stack - the stack, grows downward + +-sec +{ + .reset 0x000000 : + .picbase 0x1000 : + .text : + .comment : + .intercall : + .interfunc : + .syscall : + .fixaddr : + .fixtype : + .rodata : + .romdata ROM(.data) : + .romsdata ROM(.sdata) : + .secinfo : + .pidbase align(16) : + .sdabase : + .sbss : + .sdata : + .data : + .bss : + .heap align(16) pad(0x10000) : + .stack align(16) pad(0x1000) : + .free_mem align(16) pad(0x10000) : + .sys_regs 0xE0000000 pad(0xe000) : +} diff --git a/ports/cortex_m3/ghs/example_build/sample_threadx_el.gpj b/ports/cortex_m3/ghs/example_build/sample_threadx_el.gpj new file mode 100644 index 00000000..a51049ca --- /dev/null +++ b/ports/cortex_m3/ghs/example_build/sample_threadx_el.gpj @@ -0,0 +1,13 @@ +#!gbuild +[Program] + -DTX_ENABLE_EVENT_LOGGING + -I../../../../common/inc + -I../../../../ports_common_green/inc + -I../inc +reset.arm +tx_initialize_low_level.arm +sample_threadx.c +txe.a +sample_threadx_el.ld +sample_threadx.con +readme_threadx.txt diff --git a/ports/cortex_m3/ghs/example_build/sample_threadx_el.ld b/ports/cortex_m3/ghs/example_build/sample_threadx_el.ld new file mode 100644 index 00000000..753374c7 --- /dev/null +++ b/ports/cortex_m3/ghs/example_build/sample_threadx_el.ld @@ -0,0 +1,46 @@ +# The following explains what the default Green Hills sections are for: +# +# picbase - base of the text sections, relocatable in -pic mode +# text - text section +# syscall - syscall section, for host I/O under Multi +# fixaddr/fixtype - for PIC/PID fixups +# rodata - read only data +# romdata - the ROM image of .data +# romsdata - the ROM image of .sdata +# secinfo - section information section, used by the start-up code +# pidbase - base of the data sections, relocatable in -pid mode +# sdabase - base of the small data area section pointer +# sbss - small BSS (zeroed data) section +# sdata - small data section +# data - non-zeroed writeable data section +# bss - zeroed data section +# heap - the heap, grows upward +# stack - the stack, grows downward + +-sec +{ + .reset 0x000000 : + .picbase 0x1000 : + .text : + .comment : + .intercall : + .interfunc : + .syscall : + .fixaddr : + .fixtype : + .rodata : + .romdata ROM(.data) : + .romsdata ROM(.sdata) : + .secinfo : + .pidbase align(16) : + .sdabase : + .sbss : + .sdata : + .data : + .bss : + .heap align(16) pad(0x1000) : + .stack align(16) pad(0x1000) : + .eventlog align(16) pad(0x10000) : + .free_mem align(16) pad(0x10000) : + .sys_regs 0xE0000000 pad(0xe000) : +} diff --git a/ports/cortex_m3/ghs/example_build/tx.gpj b/ports/cortex_m3/ghs/example_build/tx.gpj new file mode 100644 index 00000000..ca9baa41 --- /dev/null +++ b/ports/cortex_m3/ghs/example_build/tx.gpj @@ -0,0 +1,215 @@ +#!gbuild +[Library] + -I../../../../common/inc + -I../inc +..\..\..\..\common\inc\tx_api.h +..\..\..\..\common\inc\tx_block_pool.h +..\..\..\..\common\inc\tx_byte_pool.h +..\..\..\..\common\inc\tx_event_flags.h +..\..\..\..\common\inc\tx_initialize.h +..\..\..\..\common\inc\tx_mutex.h +..\..\..\..\common\inc\tx_queue.h +..\..\..\..\common\inc\tx_semaphore.h +..\..\..\..\common\inc\tx_thread.h +..\..\..\..\common\inc\tx_timer.h +..\..\..\..\common\inc\tx_trace.h +..\..\..\..\common\inc\tx_user_sample.h +..\inc\tx_port.h +..\inc\tx_el.h +..\inc\tx_ghs.h +..\src\tx_el.c +..\src\tx_ghs.c +..\src\tx_ghse.c +..\src\tx_thread_context_restore.arm +..\src\tx_thread_context_save.arm +..\src\tx_thread_interrupt_control.arm +..\src\tx_thread_interrupt_disable.arm +..\src\tx_thread_interrupt_restore.arm +..\src\tx_thread_schedule.arm +..\src\tx_thread_stack_build.arm +..\src\tx_thread_system_return.arm +..\src\tx_timer_interrupt.arm +..\..\..\..\common\src\tx_block_allocate.c +..\..\..\..\common\src\tx_block_pool_cleanup.c +..\..\..\..\common\src\tx_block_pool_create.c +..\..\..\..\common\src\tx_block_pool_delete.c +..\..\..\..\common\src\tx_block_pool_info_get.c +..\..\..\..\common\src\tx_block_pool_initialize.c +..\..\..\..\common\src\tx_block_pool_performance_info_get.c +..\..\..\..\common\src\tx_block_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_block_pool_prioritize.c +..\..\..\..\common\src\tx_block_release.c +..\..\..\..\common\src\tx_byte_allocate.c +..\..\..\..\common\src\tx_byte_pool_cleanup.c +..\..\..\..\common\src\tx_byte_pool_create.c +..\..\..\..\common\src\tx_byte_pool_delete.c +..\..\..\..\common\src\tx_byte_pool_info_get.c +..\..\..\..\common\src\tx_byte_pool_initialize.c +..\..\..\..\common\src\tx_byte_pool_performance_info_get.c +..\..\..\..\common\src\tx_byte_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_byte_pool_prioritize.c +..\..\..\..\common\src\tx_byte_pool_search.c +..\..\..\..\common\src\tx_byte_release.c +..\..\..\..\common\src\tx_event_flags_cleanup.c +..\..\..\..\common\src\tx_event_flags_create.c +..\..\..\..\common\src\tx_event_flags_delete.c +..\..\..\..\common\src\tx_event_flags_get.c +..\..\..\..\common\src\tx_event_flags_info_get.c +..\..\..\..\common\src\tx_event_flags_initialize.c +..\..\..\..\common\src\tx_event_flags_performance_info_get.c +..\..\..\..\common\src\tx_event_flags_performance_system_info_get.c +..\..\..\..\common\src\tx_event_flags_set.c +..\..\..\..\common\src\tx_event_flags_set_notify.c +..\..\..\..\common\src\tx_initialize_high_level.c +..\..\..\..\common\src\tx_initialize_kernel_enter.c +..\..\..\..\common\src\tx_initialize_kernel_setup.c +..\..\..\..\common\src\tx_mutex_cleanup.c +..\..\..\..\common\src\tx_mutex_create.c +..\..\..\..\common\src\tx_mutex_delete.c +..\..\..\..\common\src\tx_mutex_get.c +..\..\..\..\common\src\tx_mutex_info_get.c +..\..\..\..\common\src\tx_mutex_initialize.c +..\..\..\..\common\src\tx_mutex_performance_info_get.c +..\..\..\..\common\src\tx_mutex_performance_system_info_get.c +..\..\..\..\common\src\tx_mutex_prioritize.c +..\..\..\..\common\src\tx_mutex_priority_change.c +..\..\..\..\common\src\tx_mutex_put.c +..\..\..\..\common\src\tx_queue_cleanup.c +..\..\..\..\common\src\tx_queue_create.c +..\..\..\..\common\src\tx_queue_delete.c +..\..\..\..\common\src\tx_queue_flush.c +..\..\..\..\common\src\tx_queue_front_send.c +..\..\..\..\common\src\tx_queue_info_get.c +..\..\..\..\common\src\tx_queue_initialize.c +..\..\..\..\common\src\tx_queue_performance_info_get.c +..\..\..\..\common\src\tx_queue_performance_system_info_get.c +..\..\..\..\common\src\tx_queue_prioritize.c +..\..\..\..\common\src\tx_queue_receive.c +..\..\..\..\common\src\tx_queue_send.c +..\..\..\..\common\src\tx_queue_send_notify.c +..\..\..\..\common\src\tx_semaphore_ceiling_put.c +..\..\..\..\common\src\tx_semaphore_cleanup.c +..\..\..\..\common\src\tx_semaphore_create.c +..\..\..\..\common\src\tx_semaphore_delete.c +..\..\..\..\common\src\tx_semaphore_get.c +..\..\..\..\common\src\tx_semaphore_info_get.c +..\..\..\..\common\src\tx_semaphore_initialize.c +..\..\..\..\common\src\tx_semaphore_performance_info_get.c +..\..\..\..\common\src\tx_semaphore_performance_system_info_get.c +..\..\..\..\common\src\tx_semaphore_prioritize.c +..\..\..\..\common\src\tx_semaphore_put.c +..\..\..\..\common\src\tx_semaphore_put_notify.c +..\..\..\..\common\src\tx_thread_create.c +..\..\..\..\common\src\tx_thread_delete.c +..\..\..\..\common\src\tx_thread_entry_exit_notify.c +..\..\..\..\common\src\tx_thread_identify.c +..\..\..\..\common\src\tx_thread_info_get.c +..\..\..\..\common\src\tx_thread_initialize.c +..\..\..\..\common\src\tx_thread_performance_info_get.c +..\..\..\..\common\src\tx_thread_performance_system_info_get.c +..\..\..\..\common\src\tx_thread_preemption_change.c +..\..\..\..\common\src\tx_thread_priority_change.c +..\..\..\..\common\src\tx_thread_relinquish.c +..\..\..\..\common\src\tx_thread_reset.c +..\..\..\..\common\src\tx_thread_resume.c +..\..\..\..\common\src\tx_thread_shell_entry.c +..\..\..\..\common\src\tx_thread_sleep.c +..\..\..\..\common\src\tx_thread_stack_analyze.c +..\..\..\..\common\src\tx_thread_stack_error_handler.c +..\..\..\..\common\src\tx_thread_stack_error_notify.c +..\..\..\..\common\src\tx_thread_suspend.c +..\..\..\..\common\src\tx_thread_system_preempt_check.c +..\..\..\..\common\src\tx_thread_system_resume.c +..\..\..\..\common\src\tx_thread_system_suspend.c +..\..\..\..\common\src\tx_thread_terminate.c +..\..\..\..\common\src\tx_thread_time_slice.c +..\..\..\..\common\src\tx_thread_time_slice_change.c +..\..\..\..\common\src\tx_thread_timeout.c +..\..\..\..\common\src\tx_thread_wait_abort.c +..\..\..\..\common\src\tx_time_get.c +..\..\..\..\common\src\tx_time_set.c +..\..\..\..\common\src\tx_timer_activate.c +..\..\..\..\common\src\tx_timer_change.c +..\..\..\..\common\src\tx_timer_create.c +..\..\..\..\common\src\tx_timer_deactivate.c +..\..\..\..\common\src\tx_timer_delete.c +..\..\..\..\common\src\tx_timer_expiration_process.c +..\..\..\..\common\src\tx_timer_info_get.c +..\..\..\..\common\src\tx_timer_initialize.c +..\..\..\..\common\src\tx_timer_performance_info_get.c +..\..\..\..\common\src\tx_timer_performance_system_info_get.c +..\..\..\..\common\src\tx_timer_system_activate.c +..\..\..\..\common\src\tx_timer_system_deactivate.c +..\..\..\..\common\src\tx_timer_thread_entry.c +..\..\..\..\common\src\tx_trace_buffer_full_notify.c +..\..\..\..\common\src\tx_trace_disable.c +..\..\..\..\common\src\tx_trace_enable.c +..\..\..\..\common\src\tx_trace_event_filter.c +..\..\..\..\common\src\tx_trace_event_unfilter.c +..\..\..\..\common\src\tx_trace_initialize.c +..\..\..\..\common\src\tx_trace_interrupt_control.c +..\..\..\..\common\src\tx_trace_isr_enter_insert.c +..\..\..\..\common\src\tx_trace_isr_exit_insert.c +..\..\..\..\common\src\tx_trace_object_register.c +..\..\..\..\common\src\tx_trace_object_unregister.c +..\..\..\..\common\src\tx_trace_user_event_insert.c +..\..\..\..\common\src\txe_block_allocate.c +..\..\..\..\common\src\txe_block_pool_create.c +..\..\..\..\common\src\txe_block_pool_delete.c +..\..\..\..\common\src\txe_block_pool_info_get.c +..\..\..\..\common\src\txe_block_pool_prioritize.c +..\..\..\..\common\src\txe_block_release.c +..\..\..\..\common\src\txe_byte_allocate.c +..\..\..\..\common\src\txe_byte_pool_create.c +..\..\..\..\common\src\txe_byte_pool_delete.c +..\..\..\..\common\src\txe_byte_pool_info_get.c +..\..\..\..\common\src\txe_byte_pool_prioritize.c +..\..\..\..\common\src\txe_byte_release.c +..\..\..\..\common\src\txe_event_flags_create.c +..\..\..\..\common\src\txe_event_flags_delete.c +..\..\..\..\common\src\txe_event_flags_get.c +..\..\..\..\common\src\txe_event_flags_info_get.c +..\..\..\..\common\src\txe_event_flags_set.c +..\..\..\..\common\src\txe_event_flags_set_notify.c +..\..\..\..\common\src\txe_mutex_create.c +..\..\..\..\common\src\txe_mutex_delete.c +..\..\..\..\common\src\txe_mutex_get.c +..\..\..\..\common\src\txe_mutex_info_get.c +..\..\..\..\common\src\txe_mutex_prioritize.c +..\..\..\..\common\src\txe_mutex_put.c +..\..\..\..\common\src\txe_queue_create.c +..\..\..\..\common\src\txe_queue_delete.c +..\..\..\..\common\src\txe_queue_flush.c +..\..\..\..\common\src\txe_queue_front_send.c +..\..\..\..\common\src\txe_queue_info_get.c +..\..\..\..\common\src\txe_queue_prioritize.c +..\..\..\..\common\src\txe_queue_receive.c +..\..\..\..\common\src\txe_queue_send.c +..\..\..\..\common\src\txe_queue_send_notify.c +..\..\..\..\common\src\txe_semaphore_ceiling_put.c +..\..\..\..\common\src\txe_semaphore_create.c +..\..\..\..\common\src\txe_semaphore_delete.c +..\..\..\..\common\src\txe_semaphore_get.c +..\..\..\..\common\src\txe_semaphore_info_get.c +..\..\..\..\common\src\txe_semaphore_prioritize.c +..\..\..\..\common\src\txe_semaphore_put.c +..\..\..\..\common\src\txe_semaphore_put_notify.c +..\..\..\..\common\src\txe_thread_create.c +..\..\..\..\common\src\txe_thread_delete.c +..\..\..\..\common\src\txe_thread_entry_exit_notify.c +..\..\..\..\common\src\txe_thread_info_get.c +..\..\..\..\common\src\txe_thread_preemption_change.c +..\..\..\..\common\src\txe_thread_priority_change.c +..\..\..\..\common\src\txe_thread_relinquish.c +..\..\..\..\common\src\txe_thread_reset.c +..\..\..\..\common\src\txe_thread_resume.c +..\..\..\..\common\src\txe_thread_suspend.c +..\..\..\..\common\src\txe_thread_terminate.c +..\..\..\..\common\src\txe_thread_time_slice_change.c +..\..\..\..\common\src\txe_thread_wait_abort.c +..\..\..\..\common\src\txe_timer_activate.c +..\..\..\..\common\src\txe_timer_change.c +..\..\..\..\common\src\txe_timer_create.c +..\..\..\..\common\src\txe_timer_deactivate.c +..\..\..\..\common\src\txe_timer_delete.c +..\..\..\..\common\src\txe_timer_info_get.c diff --git a/ports/cortex_m3/ghs/example_build/tx_initialize_low_level.arm b/ports/cortex_m3/ghs/example_build/tx_initialize_low_level.arm new file mode 100644 index 00000000..21f4797c --- /dev/null +++ b/ports/cortex_m3/ghs/example_build/tx_initialize_low_level.arm @@ -0,0 +1,224 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SYSTEM_CLOCK = 6000000 + SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-M3/GHS */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_initialize_low_level(VOID) +{ */ + .globl _tx_initialize_low_level +_tx_initialize_low_level: + + /* Disable interrupts. */ + + CPSID i ; Disable interrupts + + + /* Save the system stack pointer. */ + /* _tx_thread_system_stack_ptr = (VOID_PTR) (sp); */ + + LDR r1,=_tx_thread_system_stack_ptr ; Pickup address of system stack ptr + STR sp, [r1] ; Save system stack + + + /* Save the first available memory address. */ + /* _tx_initialize_unused_memory = (VOID_PTR) __ghsbegin_free_mem; */ + + LDR r0,=__ghsbegin_free_mem ; Pickup free memory address + LDR r2,=_tx_initialize_unused_memory ; Pickup unused memory ptr address + STR r0, [r2] ; Save first free memory address + + + /* Enable the cycle count register. */ + + LDR r0, =0xE0001000 ; Build address of DWT register + LDR r1, [r0] ; Pickup the current value + ORR r1, r1, 1 ; Set the CYCCNTENA bit + STR r1, [r0] ; Enable the cycle count register + + + /* Setup Vector Table Offset Register. */ + + MOV r0, 0xE000E000 ; Build address of NVIC registers + LDR r1, =__vectors ; Pickup address of vector table + STR r1, [r0, 0xD08] ; Set vector table address + + + /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ + + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, 0x14] ; Setup SysTick Reload Value + MOV r1, 0x7 ; Build SysTick Control Enable Value + STR r1, [r0, 0x10] ; Setup SysTick Control + + /* Configure handler priorities. */ + + LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM + STR r1, [r0, 0xD18] ; Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, 0xD1C] ; Setup System Handlers 8-11 Priority Registers + ; Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM + STR r1, [r0, 0xD20] ; Setup System Handlers 12-15 Priority Registers + ; Note: PnSV must be lowest priority, which is 0xFF + + /* Return to caller. */ + + BX lr ; Return to caller + + .type _tx_initialize_low_level,$function + .size _tx_initialize_low_level,.-_tx_initialize_low_level +/* } */ + + +/* Define shells for each of the interrupt vectors. */ + + .globl __tx_BadHandler +__tx_BadHandler: + B __tx_BadHandler + + .type __tx_BadHandler,$function + .size __tx_BadHandler,.-__tx_BadHandler + + + .globl __tx_IntHandler +__tx_IntHandler: + PUSH {lr} + BL _tx_thread_context_save + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 0 ; Build interrupt code + BL _tx_el_interrupt ; Call interrupt event logging +#endif + +; /* Do interrupt handler work here */ +; /* .... */ + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 0 ; Build interrupt code + BL _tx_el_interrupt_end ; Call interrupt event logging +#endif + + B _tx_thread_context_restore + + .type __tx_IntHandler,$function + .size __tx_IntHandler,.-__tx_IntHandler + + + .globl __tx_SysTickHandler +__tx_SysTickHandler: + PUSH {lr} + BL _tx_thread_context_save + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 15 ; Build interrupt code + BL _tx_el_interrupt ; Call interrupt event logging +#endif + + BL _tx_timer_interrupt + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 15 ; Build interrupt code + BL _tx_el_interrupt_end ; Call interrupt event logging +#endif + + B _tx_thread_context_restore + + .type __tx_SysTickHandler,$function + .size __tx_SysTickHandler,.-__tx_SysTickHandler + + + .globl __tx_NMIHandler +__tx_NMIHandler: + B __tx_NMIHandler + + .type __tx_NMIHandler,$function + .size __tx_NMIHandler,.-__tx_NMIHandler + + + .globl __tx_DBGHandler +__tx_DBGHandler: + B __tx_DBGHandler + + .type __tx_DBGHandler,$function + .size __tx_DBGHandler,.-__tx_DBGHandler + + + .globl __tx_SVCallHandler +__tx_SVCallHandler: + B __tx_SVCallHandler + + .type __tx_SVCallHandler,$function + .size __tx_SVCallHandler,.-__tx_SVCallHandler + + + /* Reference build options and version ID to ensure they come in. */ + +BUILD_OPTIONS: + .data.w _tx_build_options +VERSION_ID: + .data.w _tx_version_id diff --git a/ports/cortex_m3/ghs/example_build/txe.gpj b/ports/cortex_m3/ghs/example_build/txe.gpj new file mode 100644 index 00000000..c7825b04 --- /dev/null +++ b/ports/cortex_m3/ghs/example_build/txe.gpj @@ -0,0 +1,216 @@ +#!gbuild +[Library] + -DTX_ENABLE_EVENT_LOGGING + -I../../../../common/inc + -I../inc +..\..\..\..\common\inc\tx_api.h +..\..\..\..\common\inc\tx_block_pool.h +..\..\..\..\common\inc\tx_byte_pool.h +..\..\..\..\common\inc\tx_event_flags.h +..\..\..\..\common\inc\tx_initialize.h +..\..\..\..\common\inc\tx_mutex.h +..\..\..\..\common\inc\tx_queue.h +..\..\..\..\common\inc\tx_semaphore.h +..\..\..\..\common\inc\tx_thread.h +..\..\..\..\common\inc\tx_timer.h +..\..\..\..\common\inc\tx_trace.h +..\..\..\..\common\inc\tx_user_sample.h +..\inc\tx_port.h +..\inc\tx_el.h +..\inc\tx_ghs.h +..\src\tx_el.c +..\src\tx_ghs.c +..\src\tx_ghse.c +..\src\tx_thread_context_restore.arm +..\src\tx_thread_context_save.arm +..\src\tx_thread_interrupt_control.arm +..\src\tx_thread_interrupt_disable.arm +..\src\tx_thread_interrupt_restore.arm +..\src\tx_thread_schedule.arm +..\src\tx_thread_stack_build.arm +..\src\tx_thread_system_return.arm +..\src\tx_timer_interrupt.arm +..\..\..\..\common\src\tx_block_allocate.c +..\..\..\..\common\src\tx_block_pool_cleanup.c +..\..\..\..\common\src\tx_block_pool_create.c +..\..\..\..\common\src\tx_block_pool_delete.c +..\..\..\..\common\src\tx_block_pool_info_get.c +..\..\..\..\common\src\tx_block_pool_initialize.c +..\..\..\..\common\src\tx_block_pool_performance_info_get.c +..\..\..\..\common\src\tx_block_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_block_pool_prioritize.c +..\..\..\..\common\src\tx_block_release.c +..\..\..\..\common\src\tx_byte_allocate.c +..\..\..\..\common\src\tx_byte_pool_cleanup.c +..\..\..\..\common\src\tx_byte_pool_create.c +..\..\..\..\common\src\tx_byte_pool_delete.c +..\..\..\..\common\src\tx_byte_pool_info_get.c +..\..\..\..\common\src\tx_byte_pool_initialize.c +..\..\..\..\common\src\tx_byte_pool_performance_info_get.c +..\..\..\..\common\src\tx_byte_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_byte_pool_prioritize.c +..\..\..\..\common\src\tx_byte_pool_search.c +..\..\..\..\common\src\tx_byte_release.c +..\..\..\..\common\src\tx_event_flags_cleanup.c +..\..\..\..\common\src\tx_event_flags_create.c +..\..\..\..\common\src\tx_event_flags_delete.c +..\..\..\..\common\src\tx_event_flags_get.c +..\..\..\..\common\src\tx_event_flags_info_get.c +..\..\..\..\common\src\tx_event_flags_initialize.c +..\..\..\..\common\src\tx_event_flags_performance_info_get.c +..\..\..\..\common\src\tx_event_flags_performance_system_info_get.c +..\..\..\..\common\src\tx_event_flags_set.c +..\..\..\..\common\src\tx_event_flags_set_notify.c +..\..\..\..\common\src\tx_initialize_high_level.c +..\..\..\..\common\src\tx_initialize_kernel_enter.c +..\..\..\..\common\src\tx_initialize_kernel_setup.c +..\..\..\..\common\src\tx_mutex_cleanup.c +..\..\..\..\common\src\tx_mutex_create.c +..\..\..\..\common\src\tx_mutex_delete.c +..\..\..\..\common\src\tx_mutex_get.c +..\..\..\..\common\src\tx_mutex_info_get.c +..\..\..\..\common\src\tx_mutex_initialize.c +..\..\..\..\common\src\tx_mutex_performance_info_get.c +..\..\..\..\common\src\tx_mutex_performance_system_info_get.c +..\..\..\..\common\src\tx_mutex_prioritize.c +..\..\..\..\common\src\tx_mutex_priority_change.c +..\..\..\..\common\src\tx_mutex_put.c +..\..\..\..\common\src\tx_queue_cleanup.c +..\..\..\..\common\src\tx_queue_create.c +..\..\..\..\common\src\tx_queue_delete.c +..\..\..\..\common\src\tx_queue_flush.c +..\..\..\..\common\src\tx_queue_front_send.c +..\..\..\..\common\src\tx_queue_info_get.c +..\..\..\..\common\src\tx_queue_initialize.c +..\..\..\..\common\src\tx_queue_performance_info_get.c +..\..\..\..\common\src\tx_queue_performance_system_info_get.c +..\..\..\..\common\src\tx_queue_prioritize.c +..\..\..\..\common\src\tx_queue_receive.c +..\..\..\..\common\src\tx_queue_send.c +..\..\..\..\common\src\tx_queue_send_notify.c +..\..\..\..\common\src\tx_semaphore_ceiling_put.c +..\..\..\..\common\src\tx_semaphore_cleanup.c +..\..\..\..\common\src\tx_semaphore_create.c +..\..\..\..\common\src\tx_semaphore_delete.c +..\..\..\..\common\src\tx_semaphore_get.c +..\..\..\..\common\src\tx_semaphore_info_get.c +..\..\..\..\common\src\tx_semaphore_initialize.c +..\..\..\..\common\src\tx_semaphore_performance_info_get.c +..\..\..\..\common\src\tx_semaphore_performance_system_info_get.c +..\..\..\..\common\src\tx_semaphore_prioritize.c +..\..\..\..\common\src\tx_semaphore_put.c +..\..\..\..\common\src\tx_semaphore_put_notify.c +..\..\..\..\common\src\tx_thread_create.c +..\..\..\..\common\src\tx_thread_delete.c +..\..\..\..\common\src\tx_thread_entry_exit_notify.c +..\..\..\..\common\src\tx_thread_identify.c +..\..\..\..\common\src\tx_thread_info_get.c +..\..\..\..\common\src\tx_thread_initialize.c +..\..\..\..\common\src\tx_thread_performance_info_get.c +..\..\..\..\common\src\tx_thread_performance_system_info_get.c +..\..\..\..\common\src\tx_thread_preemption_change.c +..\..\..\..\common\src\tx_thread_priority_change.c +..\..\..\..\common\src\tx_thread_relinquish.c +..\..\..\..\common\src\tx_thread_reset.c +..\..\..\..\common\src\tx_thread_resume.c +..\..\..\..\common\src\tx_thread_shell_entry.c +..\..\..\..\common\src\tx_thread_sleep.c +..\..\..\..\common\src\tx_thread_stack_analyze.c +..\..\..\..\common\src\tx_thread_stack_error_handler.c +..\..\..\..\common\src\tx_thread_stack_error_notify.c +..\..\..\..\common\src\tx_thread_suspend.c +..\..\..\..\common\src\tx_thread_system_preempt_check.c +..\..\..\..\common\src\tx_thread_system_resume.c +..\..\..\..\common\src\tx_thread_system_suspend.c +..\..\..\..\common\src\tx_thread_terminate.c +..\..\..\..\common\src\tx_thread_time_slice.c +..\..\..\..\common\src\tx_thread_time_slice_change.c +..\..\..\..\common\src\tx_thread_timeout.c +..\..\..\..\common\src\tx_thread_wait_abort.c +..\..\..\..\common\src\tx_time_get.c +..\..\..\..\common\src\tx_time_set.c +..\..\..\..\common\src\tx_timer_activate.c +..\..\..\..\common\src\tx_timer_change.c +..\..\..\..\common\src\tx_timer_create.c +..\..\..\..\common\src\tx_timer_deactivate.c +..\..\..\..\common\src\tx_timer_delete.c +..\..\..\..\common\src\tx_timer_expiration_process.c +..\..\..\..\common\src\tx_timer_info_get.c +..\..\..\..\common\src\tx_timer_initialize.c +..\..\..\..\common\src\tx_timer_performance_info_get.c +..\..\..\..\common\src\tx_timer_performance_system_info_get.c +..\..\..\..\common\src\tx_timer_system_activate.c +..\..\..\..\common\src\tx_timer_system_deactivate.c +..\..\..\..\common\src\tx_timer_thread_entry.c +..\..\..\..\common\src\tx_trace_buffer_full_notify.c +..\..\..\..\common\src\tx_trace_disable.c +..\..\..\..\common\src\tx_trace_enable.c +..\..\..\..\common\src\tx_trace_event_filter.c +..\..\..\..\common\src\tx_trace_event_unfilter.c +..\..\..\..\common\src\tx_trace_initialize.c +..\..\..\..\common\src\tx_trace_interrupt_control.c +..\..\..\..\common\src\tx_trace_isr_enter_insert.c +..\..\..\..\common\src\tx_trace_isr_exit_insert.c +..\..\..\..\common\src\tx_trace_object_register.c +..\..\..\..\common\src\tx_trace_object_unregister.c +..\..\..\..\common\src\tx_trace_user_event_insert.c +..\..\..\..\common\src\txe_block_allocate.c +..\..\..\..\common\src\txe_block_pool_create.c +..\..\..\..\common\src\txe_block_pool_delete.c +..\..\..\..\common\src\txe_block_pool_info_get.c +..\..\..\..\common\src\txe_block_pool_prioritize.c +..\..\..\..\common\src\txe_block_release.c +..\..\..\..\common\src\txe_byte_allocate.c +..\..\..\..\common\src\txe_byte_pool_create.c +..\..\..\..\common\src\txe_byte_pool_delete.c +..\..\..\..\common\src\txe_byte_pool_info_get.c +..\..\..\..\common\src\txe_byte_pool_prioritize.c +..\..\..\..\common\src\txe_byte_release.c +..\..\..\..\common\src\txe_event_flags_create.c +..\..\..\..\common\src\txe_event_flags_delete.c +..\..\..\..\common\src\txe_event_flags_get.c +..\..\..\..\common\src\txe_event_flags_info_get.c +..\..\..\..\common\src\txe_event_flags_set.c +..\..\..\..\common\src\txe_event_flags_set_notify.c +..\..\..\..\common\src\txe_mutex_create.c +..\..\..\..\common\src\txe_mutex_delete.c +..\..\..\..\common\src\txe_mutex_get.c +..\..\..\..\common\src\txe_mutex_info_get.c +..\..\..\..\common\src\txe_mutex_prioritize.c +..\..\..\..\common\src\txe_mutex_put.c +..\..\..\..\common\src\txe_queue_create.c +..\..\..\..\common\src\txe_queue_delete.c +..\..\..\..\common\src\txe_queue_flush.c +..\..\..\..\common\src\txe_queue_front_send.c +..\..\..\..\common\src\txe_queue_info_get.c +..\..\..\..\common\src\txe_queue_prioritize.c +..\..\..\..\common\src\txe_queue_receive.c +..\..\..\..\common\src\txe_queue_send.c +..\..\..\..\common\src\txe_queue_send_notify.c +..\..\..\..\common\src\txe_semaphore_ceiling_put.c +..\..\..\..\common\src\txe_semaphore_create.c +..\..\..\..\common\src\txe_semaphore_delete.c +..\..\..\..\common\src\txe_semaphore_get.c +..\..\..\..\common\src\txe_semaphore_info_get.c +..\..\..\..\common\src\txe_semaphore_prioritize.c +..\..\..\..\common\src\txe_semaphore_put.c +..\..\..\..\common\src\txe_semaphore_put_notify.c +..\..\..\..\common\src\txe_thread_create.c +..\..\..\..\common\src\txe_thread_delete.c +..\..\..\..\common\src\txe_thread_entry_exit_notify.c +..\..\..\..\common\src\txe_thread_info_get.c +..\..\..\..\common\src\txe_thread_preemption_change.c +..\..\..\..\common\src\txe_thread_priority_change.c +..\..\..\..\common\src\txe_thread_relinquish.c +..\..\..\..\common\src\txe_thread_reset.c +..\..\..\..\common\src\txe_thread_resume.c +..\..\..\..\common\src\txe_thread_suspend.c +..\..\..\..\common\src\txe_thread_terminate.c +..\..\..\..\common\src\txe_thread_time_slice_change.c +..\..\..\..\common\src\txe_thread_wait_abort.c +..\..\..\..\common\src\txe_timer_activate.c +..\..\..\..\common\src\txe_timer_change.c +..\..\..\..\common\src\txe_timer_create.c +..\..\..\..\common\src\txe_timer_deactivate.c +..\..\..\..\common\src\txe_timer_delete.c +..\..\..\..\common\src\txe_timer_info_get.c diff --git a/ports/cortex_m3/ghs/inc/tx_el.h b/ports/cortex_m3/ghs/inc/tx_el.h new file mode 100644 index 00000000..29c72370 --- /dev/null +++ b/ports/cortex_m3/ghs/inc/tx_el.h @@ -0,0 +1,765 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** ThreadX/GHS Event Log (EL) */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* tx_el.h PORTABLE C/GHS */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the ThreadX event log functions for the GHS MULTI */ +/* EventAnalyzer. It is assumed that tx_api.h and tx_port.h have */ +/* already been included. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_EL_H +#define TX_EL_H + + +/* Define Event Log specific data definitions. */ + +#define TX_EL_VERSION_ID 2 /* Event log version ID */ +#define TX_EL_HEADER_SIZE 24 /* Event log header size */ +#define TX_EL_TNIS 16 /* Number of thread names supported */ + /* If the application needs to */ + /* track more thread names, just */ + /* increase this number and re- */ + /* build the ThreadX library. */ +#define TX_EL_TNI_ENTRY_SIZE 44 /* Thread name entries are 44 bytes */ +#define TX_EL_TNI_NAME_SIZE 34 /* Thread name size in TNI */ +#define TX_EL_NO_MORE_TNI_ROOM 1 /* Error return from thread register*/ +#define TX_EL_NAME_NOT_FOUND 2 /* Error return from un-register */ +#define TX_EL_EVENT_SIZE 32 /* Number of bytes in each event */ +#define TX_EL_VALID_ENTRY 1 /* Valid log entry */ +#define TX_EL_INVALID_ENTRY 0 /* Invalid log entry */ + + +/* Define necessary offsets. */ + +#define TX_EL_TNI_VALID_OFFSET 34 +#define TX_EL_TNI_THREAD_ID_OFFSET 36 +#define TX_EL_TNI_THREAD_PRIORITY_OFF 40 +#define TX_EL_EVENT_TYPE_OFFSET 0 +#define TX_EL_EVENT_SUBTYPE_OFFSET 2 +#define TX_EL_EVENT_TIME_UPPER_OFFSET 4 +#define TX_EL_EVENT_TIME_LOWER_OFFSET 8 +#define TX_EL_EVENT_THREAD_OFFSET 12 +#define TX_EL_EVENT_INFO_1_OFFSET 16 +#define TX_EL_EVENT_INFO_2_OFFSET 20 +#define TX_EL_EVENT_INFO_3_OFFSET 24 +#define TX_EL_EVENT_INFO_4_OFFSET 28 + + +/* Undefine constants that might be been defined previously by tx_api.h. */ + +#undef TX_EL_INITIALIZE +#undef TX_EL_THREAD_REGISTER +#undef TX_EL_THREAD_UNREGISTER +#undef TX_EL_THREAD_STATUS_CHANGE_INSERT +#undef TX_EL_BYTE_ALLOCATE_INSERT +#undef TX_EL_BYTE_POOL_CREATE_INSERT +#undef TX_EL_BYTE_POOL_DELETE_INSERT +#undef TX_EL_BYTE_RELEASE_INSERT +#undef TX_EL_BLOCK_ALLOCATE_INSERT +#undef TX_EL_BLOCK_POOL_CREATE_INSERT +#undef TX_EL_BLOCK_POOL_DELETE_INSERT +#undef TX_EL_BLOCK_RELEASE_INSERT +#undef TX_EL_EVENT_FLAGS_CREATE_INSERT +#undef TX_EL_EVENT_FLAGS_DELETE_INSERT +#undef TX_EL_EVENT_FLAGS_GET_INSERT +#undef TX_EL_EVENT_FLAGS_SET_INSERT +#undef TX_EL_INTERRUPT_CONTROL_INSERT +#undef TX_EL_QUEUE_CREATE_INSERT +#undef TX_EL_QUEUE_DELETE_INSERT +#undef TX_EL_QUEUE_FLUSH_INSERT +#undef TX_EL_QUEUE_RECEIVE_INSERT +#undef TX_EL_QUEUE_SEND_INSERT +#undef TX_EL_SEMAPHORE_CREATE_INSERT +#undef TX_EL_SEMAPHORE_DELETE_INSERT +#undef TX_EL_SEMAPHORE_GET_INSERT +#undef TX_EL_SEMAPHORE_PUT_INSERT +#undef TX_EL_THREAD_CREATE_INSERT +#undef TX_EL_THREAD_DELETE_INSERT +#undef TX_EL_THREAD_IDENTIFY_INSERT +#undef TX_EL_THREAD_PREEMPTION_CHANGE_INSERT +#undef TX_EL_THREAD_PRIORITY_CHANGE_INSERT +#undef TX_EL_THREAD_RELINQUISH_INSERT +#undef TX_EL_THREAD_RESUME_INSERT +#undef TX_EL_THREAD_SLEEP_INSERT +#undef TX_EL_THREAD_SUSPEND_INSERT +#undef TX_EL_THREAD_TERMINATE_INSERT +#undef TX_EL_THREAD_TIME_SLICE_CHANGE_INSERT +#undef TX_EL_TIME_GET_INSERT +#undef TX_EL_TIME_SET_INSERT +#undef TX_EL_TIMER_ACTIVATE_INSERT +#undef TX_EL_TIMER_CHANGE_INSERT +#undef TX_EL_TIMER_CREATE_INSERT +#undef TX_EL_TIMER_DEACTIVATE_INSERT +#undef TX_EL_TIMER_DELETE_INSERT +#undef TX_EL_BLOCK_POOL_INFO_GET_INSERT +#undef TX_EL_BLOCK_POOL_PRIORITIZE_INSERT +#undef TX_EL_BYTE_POOL_INFO_GET_INSERT +#undef TX_EL_BYTE_POOL_PRIORITIZE_INSERT +#undef TX_EL_EVENT_FLAGS_INFO_GET_INSERT +#undef TX_EL_MUTEX_CREATE_INSERT +#undef TX_EL_MUTEX_DELETE_INSERT +#undef TX_EL_MUTEX_GET_INSERT +#undef TX_EL_MUTEX_INFO_GET_INSERT +#undef TX_EL_MUTEX_PRIORITIZE_INSERT +#undef TX_EL_MUTEX_PUT_INSERT +#undef TX_EL_QUEUE_INFO_GET_INSERT +#undef TX_EL_QUEUE_FRONT_SEND_INSERT +#undef TX_EL_QUEUE_PRIORITIZE_INSERT +#undef TX_EL_SEMAPHORE_INFO_GET_INSERT +#undef TX_EL_SEMAPHORE_PRIORITIZE_INSERT +#undef TX_EL_THREAD_INFO_GET_INSERT +#undef TX_EL_THREAD_WAIT_ABORT_INSERT +#undef TX_EL_TIMER_INFO_GET_INSERT +#undef TX_EL_BLOCK_POOL_PERFORMANCE_INFO_GET_INSERT +#undef TX_EL_BLOCK_POOL_PERFORMANCE_SYSTEM_INFO_GET_INSERT +#undef TX_EL_BYTE_POOL_PERFORMANCE_INFO_GET_INSERT +#undef TX_EL_BYTE_POOL_PERFORMANCE_SYSTEM_INFO_GET_INSERT +#undef TX_EL_EVENT_FLAGS_PERFORMANCE_INFO_GET_INSERT +#undef TX_EL_EVENT_FLAGS_PERFORMANCE_SYSTEM_INFO_GET_INSERT +#undef TX_EL_EVENT_FLAGS_SET_NOTIFY_INSERT +#undef TX_EL_MUTEX_PERFORMANCE_INFO_GET_INSERT +#undef TX_EL_MUTEX_PERFORMANCE_SYSTEM_INFO_GET_INSERT +#undef TX_EL_QUEUE_PERFORMANCE_INFO_GET_INSERT +#undef TX_EL_QUEUE_PERFORMANCE_SYSTEM_INFO_GET_INSERT +#undef TX_EL_QUEUE_SEND_NOTIFY_INSERT +#undef TX_EL_SEMAPHORE_CEILING_PUT_INSERT +#undef TX_EL_SEMAPHORE_PERFORMANCE_INFO_GET_INSERT +#undef TX_EL_SEMAPHORE_PERFORMANCE_SYSTEM_INFO_GET_INSERT +#undef TX_EL_SEMAPHORE_PUT_NOTIFY_INSERT +#undef TX_EL_THREAD_ENTRY_EXIT_NOTIFY_INSERT +#undef TX_EL_THREAD_RESET_INSERT +#undef TX_EL_THREAD_PERFORMANCE_INFO_GET_INSERT +#undef TX_EL_THREAD_PERFORMANCE_SYSTEM_INFO_GET_INSERT +#undef TX_EL_THREAD_STACK_ERROR_NOTIFY_INSERT +#undef TX_EL_TIMER_PERFORMANCE_INFO_GET_INSERT +#undef TX_EL_TIMER_PERFORMANCE_SYSTEM_INFO_GET_INSERT + + +/* Define Event Types. */ + +#define TX_EL_THREAD_CHANGE 1 +#define TX_EL_INTERRUPT 2 +#define TX_EL_THREADX_CALL 3 +#define TX_EL_USER_EVENT 4 +#define TX_EL_THREAD_STATUS_CHANGE 5 +#define TX_EL_REFRESH 6 /* Not implemented */ +#define TX_EL_TIMER 7 /* Not implemented */ +#define TX_EL_TIMESOURCE_DELTA 8 /* Not implemented */ + + +/* Define TX_EL_THREADX_CALL event sub-types. */ + +#define TX_EL_BYTE_ALLOCATE 0 +#define TX_EL_BYTE_POOL_CREATE 1 +#define TX_EL_BYTE_POOL_DELETE 2 +#define TX_EL_BYTE_RELEASE 3 +#define TX_EL_BLOCK_ALLOCATE 4 +#define TX_EL_BLOCK_POOL_CREATE 5 +#define TX_EL_BLOCK_POOL_DELETE 6 +#define TX_EL_BLOCK_RELEASE 7 +#define TX_EL_EVENT_FLAGS_CREATE 8 +#define TX_EL_EVENT_FLAGS_DELETE 9 +#define TX_EL_EVENT_FLAGS_GET 10 +#define TX_EL_EVENT_FLAGS_SET 11 +#define TX_EL_INTERRUPT_CONTROL 12 +#define TX_EL_QUEUE_CREATE 13 +#define TX_EL_QUEUE_DELETE 14 +#define TX_EL_QUEUE_FLUSH 15 +#define TX_EL_QUEUE_RECEIVE 16 +#define TX_EL_QUEUE_SEND 17 +#define TX_EL_SEMAPHORE_CREATE 18 +#define TX_EL_SEMAPHORE_DELETE 19 +#define TX_EL_SEMAPHORE_GET 20 +#define TX_EL_SEMAPHORE_PUT 21 +#define TX_EL_THREAD_CREATE 22 +#define TX_EL_THREAD_DELETE 23 +#define TX_EL_THREAD_IDENTIFY 24 +#define TX_EL_THREAD_PREEMPTION_CHANGE 25 +#define TX_EL_THREAD_PRIORITY_CHANGE 26 +#define TX_EL_THREAD_RELINQUISH 27 +#define TX_EL_THREAD_RESUME 28 +#define TX_EL_THREAD_SLEEP 29 +#define TX_EL_THREAD_SUSPEND 30 +#define TX_EL_THREAD_TERMINATE 31 +#define TX_EL_THREAD_TIME_SLICE_CHANGE 32 +#define TX_EL_TIME_GET 33 +#define TX_EL_TIME_SET 34 +#define TX_EL_TIMER_ACTIVATE 35 +#define TX_EL_TIMER_CHANGE 36 +#define TX_EL_TIMER_CREATE 37 +#define TX_EL_TIMER_DEACTIVATE 38 +#define TX_EL_TIMER_DELETE 39 +#define TX_EL_BLOCK_POOL_INFO_GET 40 +#define TX_EL_BLOCK_POOL_PRIORITIZE 41 +#define TX_EL_BYTE_POOL_INFO_GET 42 +#define TX_EL_BYTE_POOL_PRIORITIZE 43 +#define TX_EL_EVENT_FLAGS_INFO_GET 44 +#define TX_EL_MUTEX_CREATE 45 +#define TX_EL_MUTEX_DELETE 46 +#define TX_EL_MUTEX_GET 47 +#define TX_EL_MUTEX_INFO_GET 48 +#define TX_EL_MUTEX_PRIORITIZE 49 +#define TX_EL_MUTEX_PUT 50 +#define TX_EL_QUEUE_INFO_GET 51 +#define TX_EL_QUEUE_FRONT_SEND 52 +#define TX_EL_QUEUE_PRIORITIZE 53 +#define TX_EL_SEMAPHORE_INFO_GET 54 +#define TX_EL_SEMAPHORE_PRIORITIZE 55 +#define TX_EL_THREAD_INFO_GET 56 +#define TX_EL_THREAD_WAIT_ABORT 57 +#define TX_EL_TIMER_INFO_GET 58 +#define TX_EL_BLOCK_POOL_PERFORMANCE_INFO_GET 59 +#define TX_EL_BLOCK_POOL_PERFORMANCE_SYSTEM_INFO_GET 60 +#define TX_EL_BYTE_POOL_PERFORMANCE_INFO_GET 61 +#define TX_EL_BYTE_POOL_PERFORMANCE_SYSTEM_INFO_GET 62 +#define TX_EL_EVENT_FLAGS_PERFORMANCE_INFO_GET 63 +#define TX_EL_EVENT_FLAGS_PERFORMANCE_SYSTEM_INFO_GET 64 +#define TX_EL_EVENT_FLAGS_SET_NOTIFY 65 +#define TX_EL_MUTEX_PERFORMANCE_INFO_GET 66 +#define TX_EL_MUTEX_PERFORMANCE_SYSTEM_INFO_GET 67 +#define TX_EL_QUEUE_PERFORMANCE_INFO_GET 68 +#define TX_EL_QUEUE_PERFORMANCE_SYSTEM_INFO_GET 69 +#define TX_EL_QUEUE_SEND_NOTIFY 70 +#define TX_EL_SEMAPHORE_CEILING_PUT 71 +#define TX_EL_SEMAPHORE_PERFORMANCE_INFO_GET 72 +#define TX_EL_SEMAPHORE_PERFORMANCE_SYSTEM_INFO_GET 73 +#define TX_EL_SEMAPHORE_PUT_NOTIFY 74 +#define TX_EL_THREAD_ENTRY_EXIT_NOTIFY 75 +#define TX_EL_THREAD_RESET 76 +#define TX_EL_THREAD_PERFORMANCE_INFO_GET 77 +#define TX_EL_THREAD_PERFORMANCE_SYSTEM_INFO_GET 78 +#define TX_EL_THREAD_STACK_ERROR_NOTIFY 79 +#define TX_EL_TIMER_PERFORMANCE_INFO_GET 80 +#define TX_EL_TIMER_PERFORMANCE_SYSTEM_INFO_GET 81 + + +/* Define ThreadX sub-types. */ + +#define TX_EL_INTERRUPT_SUB_TYPE 1 +#define TX_EL_END_OF_INTERRUPT 3 + + +/* Define event logging filters, which may be used by the application program to + dynamically enable/disable events in run-time. */ + +#define TX_EL_FILTER_STATUS_CHANGE 0x0001 +#define TX_EL_FILTER_INTERRUPTS 0x0002 +#define TX_EL_FILTER_THREAD_CALLS 0x0004 +#define TX_EL_FILTER_TIMER_CALLS 0x0008 +#define TX_EL_FILTER_EVENT_FLAG_CALLS 0x0010 +#define TX_EL_FILTER_SEMAPHORE_CALLS 0x0020 +#define TX_EL_FILTER_QUEUE_CALLS 0x0040 +#define TX_EL_FILTER_BLOCK_CALLS 0x0080 +#define TX_EL_FILTER_BYTE_CALLS 0x0100 +#define TX_EL_FILTER_MUTEX_CALLS 0x0200 +#define TX_EL_FILTER_ALL_EVENTS 0xFFFF +#define TX_EL_ENABLE_ALL_EVENTS 0x0000 + + +/* Define filter macros that are inserted in-line with the other macros below. */ + +#ifdef TX_ENABLE_EVENT_FILTERS +#define TX_EL_NO_STATUS_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_STATUS_CHANGE)) { +#define TX_EL_NO_INTERRUPT_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_INTERRUPTS)) { +#define TX_EL_NO_THREAD_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_THREAD_CALLS)) { +#define TX_EL_NO_TIMER_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_TIMER_CALLS)) { +#define TX_EL_NO_EVENT_FLAG_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_EVENT_FLAG_CALLS)) { +#define TX_EL_NO_SEMAPHORE_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_SEMAPHORE_CALLS)) { +#define TX_EL_NO_QUEUE_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_QUEUE_CALLS)) { +#define TX_EL_NO_BLOCK_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_BLOCK_CALLS)) { +#define TX_EL_NO_BYTE_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_BYTE_CALLS)) { +#define TX_EL_NO_MUTEX_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_MUTEX_CALLS)) { +#define TX_EL_END_FILTER } +#else +#define TX_EL_NO_STATUS_EVENTS +#define TX_EL_NO_INTERRUPT_EVENTS +#define TX_EL_NO_THREAD_EVENTS +#define TX_EL_NO_TIMER_EVENTS +#define TX_EL_NO_EVENT_FLAG_EVENTS +#define TX_EL_NO_SEMAPHORE_EVENTS +#define TX_EL_NO_QUEUE_EVENTS +#define TX_EL_NO_BLOCK_EVENTS +#define TX_EL_NO_BYTE_EVENTS +#define TX_EL_NO_MUTEX_EVENTS +#define TX_EL_END_FILTER +#endif + +/* Define externs and constants for non-event log source modules. This is for + the in-line macros below. */ + +#ifndef TX_EL_SOURCE_CODE +extern UCHAR *_tx_el_tni_start; +extern UCHAR **_tx_el_current_event; +extern UCHAR *_tx_el_event_area_start; +extern UCHAR *_tx_el_event_area_end; +extern UINT _tx_el_maximum_events; +extern ULONG _tx_el_total_events; +extern TX_THREAD *_tx_thread_current_ptr; +extern UINT _tx_el_event_filter; +extern ULONG _tx_el_time_base_upper; +extern ULONG _tx_el_time_base_lower; + + +/* Define macros for event logging functions. */ + +#define TX_EL_THREAD_CREATE_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO4(TX_EL_THREAD_CREATE, thread_ptr, stack_start, stack_size, priority); TX_EL_END_FILTER +#define TX_EL_EVENT_FLAGS_SET_INSERT TX_EL_NO_EVENT_FLAG_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_EVENT_FLAGS_SET, group_ptr, flags_to_set, set_option); TX_EL_END_FILTER +#define TX_EL_THREAD_DELETE_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_DELETE, thread_ptr); TX_EL_END_FILTER +#define TX_EL_THREAD_INFO_GET_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_INFO_GET, thread_ptr); TX_EL_END_FILTER +#define TX_EL_THREAD_TIME_SLICE_CHANGE_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_THREAD_TIME_SLICE_CHANGE, thread_ptr, thread_ptr -> tx_thread_new_time_slice, new_time_slice); TX_EL_END_FILTER +#define TX_EL_THREAD_TERMINATE_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_TERMINATE, thread_ptr); TX_EL_END_FILTER +#define TX_EL_THREAD_SLEEP_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_SLEEP, timer_ticks); TX_EL_END_FILTER +#define TX_EL_THREAD_SUSPEND_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_SUSPEND, thread_ptr); TX_EL_END_FILTER +#define TX_EL_THREAD_RELINQUISH_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_THREAD_RELINQUISH); TX_EL_END_FILTER +#define TX_EL_THREAD_RESUME_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_RESUME, thread_ptr); TX_EL_END_FILTER +#define TX_EL_THREAD_PRIORITY_CHANGE_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_THREAD_PRIORITY_CHANGE, thread_ptr, thread_ptr -> tx_thread_priority, new_priority); TX_EL_END_FILTER +#define TX_EL_THREAD_PREEMPTION_CHANGE_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_THREAD_PREEMPTION_CHANGE, thread_ptr, thread_ptr -> tx_thread_preempt_threshold, new_threshold); TX_EL_END_FILTER +#define TX_EL_THREAD_WAIT_ABORT_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_WAIT_ABORT, thread_ptr); TX_EL_END_FILTER +#define TX_EL_THREAD_ENTRY_EXIT_NOTIFY_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_THREAD_ENTRY_EXIT_NOTIFY, thread_ptr, thread_entry_exit_notify); TX_EL_END_FILTER +#define TX_EL_THREAD_RESET_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_RESET, thread_ptr); TX_EL_END_FILTER +#define TX_EL_THREAD_PERFORMANCE_INFO_GET_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_PERFORMANCE_INFO_GET, thread_ptr); TX_EL_END_FILTER +#define TX_EL_THREAD_PERFORMANCE_SYSTEM_INFO_GET_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_THREAD_PERFORMANCE_SYSTEM_INFO_GET); TX_EL_END_FILTER +#define TX_EL_THREAD_STACK_ERROR_NOTIFY_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_STACK_ERROR_NOTIFY, stack_error_handler); TX_EL_END_FILTER +#define TX_EL_TIME_SET_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_TIME_SET, new_time); TX_EL_END_FILTER +#define TX_EL_TIME_GET_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_TIME_GET, _tx_timer_system_clock); TX_EL_END_FILTER +#define TX_EL_TIMER_DELETE_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_TIMER_DELETE, timer_ptr); TX_EL_END_FILTER +#define TX_EL_TIMER_CREATE_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO4(TX_EL_TIMER_CREATE, timer_ptr, initial_ticks, reschedule_ticks, auto_activate); TX_EL_END_FILTER +#define TX_EL_TIMER_CHANGE_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_TIMER_CHANGE, timer_ptr, initial_ticks, reschedule_ticks); TX_EL_END_FILTER +#define TX_EL_THREAD_IDENTIFY_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_THREAD_IDENTIFY); TX_EL_END_FILTER +#define TX_EL_TIMER_DEACTIVATE_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_TIMER_DEACTIVATE, timer_ptr); TX_EL_END_FILTER +#define TX_EL_TIMER_ACTIVATE_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_TIMER_ACTIVATE, timer_ptr); TX_EL_END_FILTER +#define TX_EL_TIMER_INFO_GET_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_TIMER_INFO_GET, timer_ptr); TX_EL_END_FILTER +#define TX_EL_TIMER_PERFORMANCE_INFO_GET_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_TIMER_PERFORMANCE_INFO_GET, timer_ptr); TX_EL_END_FILTER +#define TX_EL_TIMER_PERFORMANCE_SYSTEM_INFO_GET_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_TIMER_PERFORMANCE_SYSTEM_INFO_GET); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_PUT_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_SEMAPHORE_PUT, semaphore_ptr, semaphore_ptr -> tx_semaphore_count); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_GET_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_SEMAPHORE_GET, semaphore_ptr, semaphore_ptr -> tx_semaphore_count); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_DELETE_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_SEMAPHORE_DELETE, semaphore_ptr); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_CREATE_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_SEMAPHORE_CREATE, semaphore_ptr, initial_count); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_INFO_GET_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_SEMAPHORE_INFO_GET, semaphore_ptr); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_PRIORITIZE_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_SEMAPHORE_PRIORITIZE, semaphore_ptr); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_CEILING_PUT_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_SEMAPHORE_CEILING_PUT, semaphore_ptr, semaphore_ptr -> tx_semaphore_count, ceiling); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_PERFORMANCE_INFO_GET_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_SEMAPHORE_PERFORMANCE_INFO_GET, semaphore_ptr); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_PERFORMANCE_SYSTEM_INFO_GET_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_SEMAPHORE_PERFORMANCE_SYSTEM_INFO_GET); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_PUT_NOTIFY_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_SEMAPHORE_PUT_NOTIFY, semaphore_ptr, semaphore_put_notify); TX_EL_END_FILTER +#define TX_EL_QUEUE_FRONT_SEND_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_QUEUE_FRONT_SEND, queue_ptr, source_ptr); TX_EL_END_FILTER +#define TX_EL_QUEUE_SEND_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_QUEUE_SEND, queue_ptr, source_ptr); TX_EL_END_FILTER +#define TX_EL_QUEUE_RECEIVE_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_QUEUE_RECEIVE, queue_ptr, destination_ptr); TX_EL_END_FILTER +#define TX_EL_QUEUE_FLUSH_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_QUEUE_FLUSH, queue_ptr); TX_EL_END_FILTER +#define TX_EL_QUEUE_DELETE_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_QUEUE_DELETE, queue_ptr); TX_EL_END_FILTER +#define TX_EL_QUEUE_CREATE_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO4(TX_EL_QUEUE_CREATE, queue_ptr, queue_start, queue_size, message_size); TX_EL_END_FILTER +#define TX_EL_QUEUE_INFO_GET_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_QUEUE_INFO_GET, queue_ptr); TX_EL_END_FILTER +#define TX_EL_QUEUE_PRIORITIZE_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_QUEUE_PRIORITIZE, queue_ptr); TX_EL_END_FILTER +#define TX_EL_QUEUE_PERFORMANCE_INFO_GET_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_QUEUE_PERFORMANCE_INFO_GET, queue_ptr); TX_EL_END_FILTER +#define TX_EL_QUEUE_PERFORMANCE_SYSTEM_INFO_GET_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_QUEUE_PERFORMANCE_SYSTEM_INFO_GET); TX_EL_END_FILTER +#define TX_EL_QUEUE_SEND_NOTIFY_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_QUEUE_SEND_NOTIFY, queue_ptr, queue_send_notify); TX_EL_END_FILTER +#define TX_EL_EVENT_FLAGS_GET_INSERT TX_EL_NO_EVENT_FLAG_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_EVENT_FLAGS_GET, group_ptr, requested_flags, get_option); TX_EL_END_FILTER +#define TX_EL_EVENT_FLAGS_DELETE_INSERT TX_EL_NO_EVENT_FLAG_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_EVENT_FLAGS_DELETE, group_ptr); TX_EL_END_FILTER +#define TX_EL_EVENT_FLAGS_CREATE_INSERT TX_EL_NO_EVENT_FLAG_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_EVENT_FLAGS_CREATE, group_ptr); TX_EL_END_FILTER +#define TX_EL_EVENT_FLAGS_INFO_GET_INSERT TX_EL_NO_EVENT_FLAG_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_EVENT_FLAGS_INFO_GET, group_ptr); TX_EL_END_FILTER +#define TX_EL_EVENT_FLAGS_PERFORMANCE_INFO_GET_INSERT TX_EL_NO_EVENT_FLAG_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_EVENT_FLAGS_PERFORMANCE_INFO_GET, group_ptr); TX_EL_END_FILTER +#define TX_EL_EVENT_FLAGS_PERFORMANCE_SYSTEM_INFO_GET_INSERT TX_EL_NO_EVENT_FLAG_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_EVENT_FLAGS_PERFORMANCE_SYSTEM_INFO_GET); TX_EL_END_FILTER +#define TX_EL_EVENT_FLAGS_SET_NOTIFY_INSERT TX_EL_NO_EVENT_FLAG_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_EVENT_FLAGS_SET_NOTIFY, group_ptr, events_set_notify); TX_EL_END_FILTER +#define TX_EL_BYTE_RELEASE_INSERT TX_EL_NO_BYTE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_BYTE_RELEASE, pool_ptr, memory_ptr); TX_EL_END_FILTER +#define TX_EL_BYTE_POOL_DELETE_INSERT TX_EL_NO_BYTE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_BYTE_POOL_DELETE, pool_ptr); TX_EL_END_FILTER +#define TX_EL_BYTE_POOL_CREATE_INSERT TX_EL_NO_BYTE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_BYTE_POOL_CREATE, pool_ptr, pool_start, pool_size); TX_EL_END_FILTER +#define TX_EL_BYTE_POOL_INFO_GET_INSERT TX_EL_NO_BYTE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_BYTE_POOL_INFO_GET, pool_ptr); TX_EL_END_FILTER +#define TX_EL_BYTE_POOL_PRIORITIZE_INSERT TX_EL_NO_BYTE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_BYTE_POOL_PRIORITIZE, pool_ptr); TX_EL_END_FILTER +#define TX_EL_BYTE_ALLOCATE_INSERT TX_EL_NO_BYTE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_BYTE_ALLOCATE, pool_ptr, memory_ptr, memory_size); TX_EL_END_FILTER +#define TX_EL_BYTE_POOL_PERFORMANCE_INFO_GET_INSERT TX_EL_NO_BYTE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_BYTE_POOL_PERFORMANCE_INFO_GET, pool_ptr); TX_EL_END_FILTER +#define TX_EL_BYTE_POOL_PERFORMANCE_SYSTEM_INFO_GET_INSERT TX_EL_NO_BYTE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_BYTE_POOL_PERFORMANCE_SYSTEM_INFO_GET); TX_EL_END_FILTER +#define TX_EL_BLOCK_RELEASE_INSERT TX_EL_NO_BLOCK_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_BLOCK_RELEASE, pool_ptr, block_ptr); TX_EL_END_FILTER +#define TX_EL_BLOCK_POOL_DELETE_INSERT TX_EL_NO_BLOCK_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_BLOCK_POOL_DELETE, pool_ptr); TX_EL_END_FILTER +#define TX_EL_BLOCK_POOL_CREATE_INSERT TX_EL_NO_BLOCK_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO4(TX_EL_BLOCK_POOL_CREATE, pool_ptr, pool_start, pool_size, block_size); TX_EL_END_FILTER +#define TX_EL_BLOCK_POOL_INFO_GET_INSERT TX_EL_NO_BLOCK_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_BLOCK_POOL_INFO_GET, pool_ptr); TX_EL_END_FILTER +#define TX_EL_BLOCK_POOL_PRIORITIZE_INSERT TX_EL_NO_BLOCK_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_BLOCK_POOL_PRIORITIZE, pool_ptr); TX_EL_END_FILTER +#define TX_EL_BLOCK_ALLOCATE_INSERT TX_EL_NO_BLOCK_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_BLOCK_ALLOCATE, pool_ptr, block_ptr); TX_EL_END_FILTER +#define TX_EL_BLOCK_POOL_PERFORMANCE_INFO_GET_INSERT TX_EL_NO_BLOCK_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_BLOCK_POOL_PERFORMANCE_INFO_GET, pool_ptr); TX_EL_END_FILTER +#define TX_EL_BLOCK_POOL_PERFORMANCE_SYSTEM_INFO_GET_INSERT TX_EL_NO_BLOCK_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_BLOCK_POOL_PERFORMANCE_SYSTEM_INFO_GET); TX_EL_END_FILTER +#define TX_EL_MUTEX_CREATE_INSERT TX_EL_NO_MUTEX_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_MUTEX_CREATE, mutex_ptr, inherit); TX_EL_END_FILTER +#define TX_EL_MUTEX_DELETE_INSERT TX_EL_NO_MUTEX_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_MUTEX_DELETE, mutex_ptr); TX_EL_END_FILTER +#define TX_EL_MUTEX_GET_INSERT TX_EL_NO_MUTEX_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_MUTEX_GET, mutex_ptr, mutex_ptr -> tx_mutex_owner, mutex_ptr -> tx_mutex_ownership_count); TX_EL_END_FILTER +#define TX_EL_MUTEX_INFO_GET_INSERT TX_EL_NO_MUTEX_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_MUTEX_INFO_GET, mutex_ptr); TX_EL_END_FILTER +#define TX_EL_MUTEX_PRIORITIZE_INSERT TX_EL_NO_MUTEX_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_MUTEX_PRIORITIZE, mutex_ptr); TX_EL_END_FILTER +#define TX_EL_MUTEX_PUT_INSERT TX_EL_NO_MUTEX_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_MUTEX_PUT, mutex_ptr, mutex_ptr -> tx_mutex_owner, mutex_ptr -> tx_mutex_ownership_count); TX_EL_END_FILTER +#define TX_EL_MUTEX_PERFORMANCE_INFO_GET_INSERT TX_EL_NO_MUTEX_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_MUTEX_PERFORMANCE_INFO_GET, mutex_ptr); TX_EL_END_FILTER +#define TX_EL_MUTEX_PERFORMANCE_SYSTEM_INFO_GET_INSERT TX_EL_NO_MUTEX_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_MUTEX_PERFORMANCE_SYSTEM_INFO_GET); TX_EL_END_FILTER + + +#endif + + +/* Define Event Log function prototypes. */ + +VOID _tx_el_initialize(VOID); +UINT _tx_el_thread_register(TX_THREAD *thread_ptr); +UINT _tx_el_thread_unregister(TX_THREAD *thread_ptr); +VOID _tx_el_user_event_insert(UINT sub_type, ULONG info_1, ULONG info_2, + ULONG info_3, ULONG info_4); +VOID _tx_el_thread_running(TX_THREAD *thread_ptr); +VOID _tx_el_thread_preempted(TX_THREAD *thread_ptr); +VOID _tx_el_interrupt(UINT interrupt_number); +VOID _tx_el_interrupt_end(UINT interrupt_number); +VOID _tx_el_interrupt_control_call(void); +VOID _tx_el_event_log_on(void); +VOID _tx_el_event_log_off(void); +VOID _tx_el_event_filter_set(UINT filter); + + +/* Define macros that are used inside the ThreadX source code. + If event logging is disabled, these macros will be defined + as white space. */ + +#ifdef TX_ENABLE_EVENT_LOGGING +#ifndef TX_NO_EVENT_INFO +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO4(a, b, c, d, e) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_current_ptr;\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_1_OFFSET)) =\ + (ULONG) b;\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_2_OFFSET)) =\ + (ULONG) c;\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_3_OFFSET)) =\ + (ULONG) d;\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_4_OFFSET)) =\ + (ULONG) e;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(a, b, c, d) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_current_ptr;\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_1_OFFSET)) =\ + (ULONG) b;\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_2_OFFSET)) =\ + (ULONG) c;\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_3_OFFSET)) =\ + (ULONG) d;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(a, b, c) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_current_ptr;\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_1_OFFSET)) =\ + (ULONG) b;\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_2_OFFSET)) =\ + (ULONG) c;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(a, b) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_current_ptr;\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_1_OFFSET)) =\ + (ULONG) b;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(a) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_current_ptr;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_THREAD_STATUS_CHANGE_INSERT(a, b) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + TX_EL_NO_STATUS_EVENTS \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREAD_STATUS_CHANGE; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) b; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) a;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + TX_EL_END_FILTER \ + } +#define TX_EL_THREAD_REGISTER(a) \ + _tx_el_thread_register(a); +#define TX_EL_THREAD_UNREGISTER(a) \ + _tx_el_thread_unregister(a); +#define TX_EL_INITIALIZE _tx_el_initialize(); +#else +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO4(a, b, c, d, e) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_current_ptr;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(a, b, c, d) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_current_ptr;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(a, b, c) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_current_ptr;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(a, b) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_current_ptr;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(a) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_current_ptr;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_THREAD_STATUS_CHANGE_INSERT(a, b) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + TX_EL_NO_STATUS_EVENTS \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREAD_STATUS_CHANGE; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) b; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) a;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + TX_EL_END_FILTER \ + } +#define TX_EL_THREAD_REGISTER(a) \ + _tx_el_thread_register(a); +#define TX_EL_THREAD_UNREGISTER(a) \ + _tx_el_thread_unregister(a); +#define TX_EL_INITIALIZE _tx_el_initialize(); +#endif +#else +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO4(a, b, c, d, e) +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(a, b, c, d) +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(a, b, c) +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(a, b) +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(a) +#define TX_EL_THREAD_STATUS_CHANGE_INSERT(a, b) +#define TX_EL_THREAD_REGISTER(a) +#define TX_EL_THREAD_UNREGISTER(a) +#define TX_EL_INITIALIZE +#endif + +#endif + diff --git a/ports/cortex_m3/ghs/inc/tx_ghs.h b/ports/cortex_m3/ghs/inc/tx_ghs.h new file mode 100644 index 00000000..ca976916 --- /dev/null +++ b/ports/cortex_m3/ghs/inc/tx_ghs.h @@ -0,0 +1,77 @@ +/* + * ThreadX C/C++ Library Support + * + * Copyright 1983-2019 Green Hills Software LLC. + * + * This program is the property of Green Hills Software LLC., + * its contents are proprietary information and no part of it + * is to be disclosed to anyone except employees of Green Hills + * Software LLC., or as agreed in writing signed by the President + * of Green Hills Software LLC. + */ + +#ifndef _TX_GHS_H_ +#define _TX_GHS_H_ + +#include +#include +#include +#include + +#if defined(__ghs) && (__GHS_VERSION_NUMBER >= 500) +extern void *__ghs_GetThreadLocalStorageItem(int specifier); + +/* Thread-local storage routines for Green Hills releases 5.x and beyond. + The following specifiers are used when calling + __ghs_GetThreadLocalStorageItem. + + If __ghs_GetThreadLocalStorageItem is customized to + return a per-thread errno value, define the preprocessor symbol + USE_THREAD_LOCAL_ERRNO in ind_errn.c. + */ + +enum __ghs_ThreadLocalStorage_specifier { + __ghs_TLS_asctime_buff, + __ghs_TLS_tmpnam_space, + __ghs_TLS_strtok_saved_pos, + __ghs_TLS_Errno, + __ghs_TLS_gmtime_temp, + __ghs_TLS___eh_globals, + __ghs_TLS_SignalHandlers +}; +#else +/* Thread-local storage routines for Green Hills releases 4.x and 3.x . */ +typedef void (*SignalHandler)(int); + +typedef struct +{ + int Errno; /* errno. */ + SignalHandler SignalHandlers[_SIGMAX]; /* signal() buffer. */ + char tmpnam_space[L_tmpnam]; /* tmpnam(NULL) buffer. */ + char asctime_buff[30]; /* . */ + char *strtok_saved_pos; /* strtok() position. */ + struct tm gmtime_temp; /* gmtime() and localtime() buffer. */ + void *__eh_globals; /* Pointer for C++ exception handling. */ +} ThreadLocalStorage; + +ThreadLocalStorage *GetThreadLocalStorage(void); +#endif + + +void __ghsLock(void); +void __ghsUnlock(void); + +int __ghs_SaveSignalContext(jmp_buf); +void __ghs_RestoreSignalContext(jmp_buf); + +/* prototypes for FILE lock routines. */ +void __ghs_flock_file(void *); +void __ghs_funlock_file(void *); +int __ghs_ftrylock_file(void *); +void __ghs_flock_create(void **); +void __ghs_flock_destroy(void *); + +/* prototype for GHS/ThreadX error shell checking. */ +void __ghs_rnerr(char *errMsg, int stackLevels, int stackTraceDisplay, void *hexVal); + +#endif /* _TX_GHS_H_ */ diff --git a/ports/cortex_m3/ghs/inc/tx_port.h b/ports/cortex_m3/ghs/inc/tx_port.h new file mode 100644 index 00000000..3ba5b354 --- /dev/null +++ b/ports/cortex_m3/ghs/inc/tx_port.h @@ -0,0 +1,389 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-M3/GHS */ +/* 6.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include +#include +#include "tx_ghs.h" + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM Cortex-M port. */ + +#define TX_INT_DISABLE 1 /* Disable interrupts */ +#define TX_INT_ENABLE 0 /* Enable interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define constants for Green Hills EventAnalyzer. */ + +/* Define the number of ticks per second. This informs the EventAnalyzer what the timestamps + represent. By default, this is set to 1,000,000 i.e., one tick every microsecond. */ + +#define TX_EL_TICKS_PER_SECOND 1000000 + +/* Define the method of how to get the upper and lower 32-bits of the time stamp. By default, simply + simulate the time-stamp source with a counter. */ + +#define read_tbu() _tx_el_time_base_upper +#define read_tbl() ++_tx_el_time_base_lower + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 VOID * tx_thread_eh_globals; \ + int Errno; /* errno. */ \ + char * strtok_saved_pos; /* strtok() position. */ +#ifndef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#define TX_THREAD_EXTENSION_3 +#else +#define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ + unsigned long long tx_thread_execution_time_last_start; +#endif + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + +#if (__GHS_VERSION_NUMBER >= 500) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) \ + { \ + extern void __tx_cpp_exception_init(TX_THREAD *thread_ptr); \ + __tx_cpp_exception_init(thread_ptr); \ + } +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) \ + { \ + #pragma weak __cpp_exception_init \ + extern void __cpp_exception_init(void **); \ + static void (*const cpp_init_funcp)(void **) = __cpp_exception_init; \ + if (cpp_init_funcp) \ + __cpp_exception_init(&(thread_ptr -> tx_thread_eh_globals)); \ + } +#endif + +#if (__GHS_VERSION_NUMBER >= 500) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) \ + { \ + extern void __tx_cpp_exception_cleanup(TX_THREAD *thread_ptr); \ + __tx_cpp_exception_cleanup(thread_ptr); \ + } +#else +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) \ + { \ + #pragma weak __cpp_exception_cleanup \ + extern void __cpp_exception_cleanup(void **); \ + static void (*const cpp_cleanup_funcp)(void **) = \ + __cpp_exception_cleanup; \ + if (cpp_cleanup_funcp) \ + __cpp_exception_cleanup(&(thread_ptr -> tx_thread_eh_globals)); \ + } +#endif + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define the get system state macro. */ + +#ifndef TX_THREAD_GET_SYSTEM_STATE +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | __MRS(__IPSR)) +#endif + + +/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value + indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h + for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always + zero after initialization for Cortex-M ports. */ + +#ifndef TX_THREAD_SYSTEM_RETURN_CHECK +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#endif + + +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to + prevent early scheduling on Cortex-M parts. */ + +#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + b = __CLZ32(m); \ + b = 31 - b; + +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifdef TX_DISABLE_INLINE + +UINT _tx_thread_interrupt_disable(VOID); +VOID _tx_thread_interrupt_restore(UINT previous_posture); + +#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); + +#define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; + +/* Define ThreadX interrupt lockout and restore macros using + asm macros. */ + +asm int disable_ints(void) +{ +% + MRS r0,PRIMASK + MOV r1,1 + MSR PRIMASK,r1 +%error +} + +asm void restore_ints(int a) +{ +%reg a + MSR PRIMASK,a +%mem a + LDR r0,a + MSR PRIMASK,r0 +%error +} + +#define TX_DISABLE interrupt_save = disable_ints(); + +#define TX_RESTORE restore_ints(interrupt_save); + +#endif + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/GHS Version 6.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + + + diff --git a/ports/cortex_m3/ghs/readme_threadx.txt b/ports/cortex_m3/ghs/readme_threadx.txt new file mode 100644 index 00000000..71dd5083 --- /dev/null +++ b/ports/cortex_m3/ghs/readme_threadx.txt @@ -0,0 +1,158 @@ + Microsoft's Azure RTOS ThreadX for Cortex-M3 + + Using the Green Hills Software Tools + +1. Open the ThreadX Project Workspace + +In order to build the ThreadX library and the ThreadX demonstration first load +the Azure RTOS Workspace azure_rtos_workspace.gpj, which is located inside the +"example_build" directory. + + +2. Building the ThreadX run-time Library + +Building the ThreadX library is easy; simply select the MULTI project file +tx.gpj and then select the build button. You should now observe the +compilation and assembly of the ThreadX library. This project build produces +the ThreadX library file tx.a. + + +3. Demonstration System + +The ThreadX demonstration is designed to execute under the MULTI environment +on the Green Hills Cortex-M3 simulator. The instructions that follow describe +how to get the ThreadX evaluation running under the MULTI Cortex-M3 simulation +environment. + +Building the demonstration is easy; simply select the MULTI project file +sample_threadx.gpj. At this point, select the "Project Build" button and observe +the compilation, assembly, and linkage of the ThreadX demonstration application. + +After the demonstration is built, invoke the MULTI ARM simulator by selecting +the simulator connection from within the sample_threadx.con connection file. +Once connected to the simulator, select the "Debug" button. You should now +observe the main function of sample_threadx.c. + +You are now ready to execute the ThreadX demonstration system. Select +breakpoints and data watches to observe the execution of the sample_threadx.c +application. + + +4. EventAnalyzer Demonstration + +To build a demonstration system that also logs events for the MULTI EventAnalyzer, +perform the same steps as the regular demo, except build the ThreadX library with +txe.gpj file and use the sample_threadx_el.gpj build file to build the demonstration. +The resulting image will log all system events, which can then be displayed by the +MULTI EventAnalyzer. + + +5. System Initialization + +The system entry point using the Green Hills tools is at the label _start. +This is defined within the crt0.arm file supplied by Green Hills. In addition, +this is where all static and global preset C variable initialization +processing is called from. + +After the Green Hills startup function returns, ThreadX initialization is +called. The main initialization function is _tx_initialize_low_level and +is located in the file tx_initialize_low_level.arm. This function is responsible +for setting up various system data structures, interrupt vectors, and the +periodic timer interrupt source of ThreadX. + +In addition, _tx_initialize_low_level determines where the first available +RAM memory address is located. This address is supplied to tx_application_define. + +By default, the first available RAM memory address is assumed to start at the +beginning of the ThreadX section .free_mem. If changes are made to the +sample_threadx.ld file, the .free_mem section should remain the last allocated +section in the main RAM area. The starting address of this section is passed +to tx_application_define. + + +6. Register Usage and Stack Frames + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have the same stack frame in the Cortex-M3 version of +ThreadX. The top of the suspended thread's stack is pointed to by +tx_thread_stack_ptr in the associated thread control block TX_THREAD. + + + Stack Offset Stack Contents + + 0x00 r4 + 0x04 r5 + 0x08 r6 + 0x0C r7 + 0x10 r8 + 0x14 r9 + 0x18 r10 + 0x1C r11 + 0x20 r0 (Hardware stack starts here!!) + 0x24 r1 + 0x28 r2 + 0x2C r3 + 0x30 r12 + 0x34 lr + 0x38 pc + 0x3C xPSR + + +7. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make ThreadX run faster, you can change the tx.gpj project +to disable debug information and enable the desired optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined before tx_api.h is included. + + +8. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-M3 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +8.1 Vector Area + +The Cortex-M3 vectors start at the label __tx_vectors. The application may modify +the vector area according to its needs. + + +8.2 Managed Interrupts + +A ThreadX managed interrupt is defined below. By following these conventions, the +application ISR is then allowed access to various ThreadX services from the ISR. +Here is the standard template for managed ISRs in ThreadX: + + + .globl __tx_IntHandler +__tx_IntHandler: + PUSH {lr} + BL _tx_thread_context_save + + /* Do interrupt handler work here */ + + B _tx_thread_context_restore + + +9. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +05/19/2020 Initial ThreadX version of Cortex-M3/Green Hills port. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_m3/ghs/src/tx_el.c b/ports/cortex_m3/ghs/src/tx_el.c new file mode 100644 index 00000000..e2c39a1d --- /dev/null +++ b/ports/cortex_m3/ghs/src/tx_el.c @@ -0,0 +1,1165 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** ThreadX/GHS Event Log (EL) */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_EL_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_el.h" +#include "string.h" + + +/* Define global variables used to manage the event pool. */ + +UCHAR *_tx_el_tni_start; +UCHAR **_tx_el_current_event; +UCHAR *_tx_el_event_area_start; +UCHAR *_tx_el_event_area_end; +UINT _tx_el_maximum_events; +ULONG _tx_el_total_events; +UINT _tx_el_event_filter; +ULONG _tx_el_time_base_upper; +ULONG _tx_el_time_base_lower; + +extern char __ghsbegin_eventlog[]; +extern char __ghsend_eventlog[]; + +extern TX_THREAD *_tx_thread_current_ptr; +UINT _tx_thread_interrupt_control(UINT new_posture); + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_initialize PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates the Event Log (in the format dictated by the */ +/* GHS Event Analyzer) and sets up various information for subsequent */ +/* operation. The start and end of the Event Log is determined by the */ +/* .eventlog section in the linker control file. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_el_initialize(VOID) +{ + +UCHAR *work_ptr; +UCHAR *read_ptr; +ULONG event_log_size; +UCHAR *end_ptr; +UINT i; + + + /* Clear total event counter. */ + _tx_el_total_events = 0; + + /* Clear event filter. */ + _tx_el_event_filter = 0; + + /* First, pickup the starting and ending address of the Event Log memory. */ + work_ptr = (unsigned char *) __ghsbegin_eventlog; + end_ptr = (unsigned char *) __ghsend_eventlog; + + /* Calculate the event log size. */ + event_log_size = end_ptr - work_ptr; + + /* Subtract off the number of bytes in the header and the TNI area. */ + event_log_size = event_log_size - (TX_EL_HEADER_SIZE + + (TX_EL_TNI_ENTRY_SIZE * TX_EL_TNIS)); + + /* Make sure the event log is evenly divisible by the event size. */ + event_log_size = (event_log_size/TX_EL_EVENT_SIZE) * TX_EL_EVENT_SIZE; + + /* Build the Event Log header. */ + + /* Setup the Event Log Version ID. */ + *((unsigned short *) work_ptr) = (unsigned short) TX_EL_VERSION_ID; + work_ptr = work_ptr + sizeof(unsigned short); + + /* Setup the TNIS (number of thread names) field. */ + *((unsigned short *) work_ptr) = (unsigned short) TX_EL_TNIS; + work_ptr = work_ptr + sizeof(unsigned short); + + /* Setup the EVPS (event pool size) field. */ + *((ULONG *) work_ptr) = event_log_size; + work_ptr = work_ptr + sizeof(ULONG); + + /* Remember the maximum number of events. */ + _tx_el_maximum_events = event_log_size/TX_EL_EVENT_SIZE; + + /* Setup max_events field. */ + *((ULONG *) work_ptr) = _tx_el_maximum_events; + work_ptr = work_ptr + sizeof(ULONG); + + /* Setup the evploc (location of event pool). */ + *((ULONG *) work_ptr) = (ULONG) (((ULONG) __ghsbegin_eventlog) + TX_EL_HEADER_SIZE + + (TX_EL_TNIS * TX_EL_TNI_ENTRY_SIZE)); + work_ptr = work_ptr + sizeof(ULONG); + + /* Save the current event pointer. */ + _tx_el_current_event = (UCHAR **) work_ptr; + + /* Setup event_ptr (pointer to oldest event) field to the start + of the event pool. */ + *_tx_el_current_event = (UCHAR *) (((ULONG) __ghsbegin_eventlog) + TX_EL_HEADER_SIZE + + (TX_EL_TNIS * TX_EL_TNI_ENTRY_SIZE)); + work_ptr = work_ptr + sizeof(ULONG); + + /* Setup tbfreq (the number of ticks in a second) field. */ + *((ULONG *) work_ptr) = TX_EL_TICKS_PER_SECOND; + work_ptr = work_ptr + sizeof(ULONG); + + /* At this point we are pointing at the Thread Name Information (TNI) array. */ + + /* Remember the start of this for future updates. */ + _tx_el_tni_start = work_ptr; + + /* Clear the entire TNI array, this is the initial setting. */ + end_ptr = work_ptr + (TX_EL_TNIS * TX_EL_TNI_ENTRY_SIZE); + memset((void *)work_ptr, 0, (TX_EL_TNIS * TX_EL_TNI_ENTRY_SIZE)); + work_ptr = end_ptr; + + /* At this point, we are pointing at the actual Event Entry area. */ + + /* Remember the start of the actual event log area. */ + _tx_el_event_area_start = work_ptr; + + /* Clear the entire Event area. */ + end_ptr = work_ptr + event_log_size; + memset((void *)work_ptr, 0, event_log_size); + work_ptr = end_ptr; + + /* Save the end pointer for later use. */ + _tx_el_event_area_end = work_ptr; + + /* Setup an entry to resolve all activities from initialization and from + an idle system. */ + work_ptr = _tx_el_tni_start; + read_ptr = (UCHAR *) "Initialization/System Idle"; + i = 0; + while ((i < TX_EL_TNI_NAME_SIZE) && (*read_ptr)) + { + + /* Copy a character of thread's name into TNI area of log. */ + *work_ptr++ = *read_ptr++; + + /* Increment the character count. */ + i++; + } + + /* Determine if a NULL needs to be inserted. */ + if (i < TX_EL_TNI_NAME_SIZE) + { + + /* Yes, insert a NULL into the event log string. */ + *work_ptr = (unsigned char) 0; + } + + /* Setup the thread ID to NULL. */ + *((ULONG *) (_tx_el_tni_start + TX_EL_TNI_THREAD_ID_OFFSET)) = (ULONG) TX_NULL; + + /* Set the valid field to indicate the entry is complete. */ + *((UCHAR *) (_tx_el_tni_start + TX_EL_TNI_VALID_OFFSET)) = (ULONG) TX_EL_VALID_ENTRY; + + /* Clear the time base global variables. */ + _tx_el_time_base_upper = 0; + _tx_el_time_base_lower = 0; +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_thread_register PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers a thread in the event log for future */ +/* display purposes. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SUCCESS Thread was placed in TNI area */ +/* TX_ERROR No more room in the TNI area */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create ThreadX thread create function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _tx_el_thread_register(TX_THREAD *thread_ptr) +{ + +UCHAR *entry_ptr; +UCHAR *work_ptr; +UCHAR *read_ptr; +UINT i; + + + /* First of all, search for a free slot in the TNI area. */ + entry_ptr = _tx_el_tni_start; + i = 0; + while (i < TX_EL_TNIS) + { + + /* Determine if this entry is available. */ + if (*(entry_ptr + TX_EL_TNI_VALID_OFFSET) == TX_EL_INVALID_ENTRY) + break; + + /* Otherwise, increment the associated pointers and indices. */ + i++; + entry_ptr = entry_ptr + TX_EL_TNI_ENTRY_SIZE; + } + + /* Check to see if there were no more valid entries. */ + if (i >= TX_EL_TNIS) + return(TX_EL_NO_MORE_TNI_ROOM); + + /* Otherwise, we have room in the TNI and a valid record. */ + + /* Setup the thread's name. */ + work_ptr = entry_ptr; + read_ptr = (UCHAR *) thread_ptr -> tx_thread_name; + i = 0; + while ((i < TX_EL_TNI_NAME_SIZE) && (*read_ptr)) + { + + /* Copy a character of thread's name into TNI area of log. */ + *work_ptr++ = *read_ptr++; + + /* Increment the character count. */ + i++; + } + + /* Determine if a NULL needs to be inserted. */ + if (i < TX_EL_TNI_NAME_SIZE) + { + + /* Yes, insert a NULL into the event log string. */ + *work_ptr = (unsigned char) 0; + } + + /* Setup the thread ID. */ + *((ULONG *) (entry_ptr + TX_EL_TNI_THREAD_ID_OFFSET)) = (ULONG) thread_ptr; + + /* Setup the thread priority. */ + *((ULONG *) (entry_ptr + TX_EL_TNI_THREAD_PRIORITY_OFF)) = (ULONG) thread_ptr -> tx_thread_priority; + + /* Set the valid field to indicate the entry is complete. */ + *((UCHAR *) (entry_ptr + TX_EL_TNI_VALID_OFFSET)) = (ULONG) TX_EL_VALID_ENTRY; + + /* Thread name has been registered. */ + return(TX_SUCCESS); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_thread_unregister PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function unregisters a thread in the event log for future */ +/* display purposes. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SUCCESS Thread was placed in TNI area */ +/* TX_ERROR No more room in the TNI area */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create ThreadX thread create function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _tx_el_thread_unregister(TX_THREAD *thread_ptr) +{ + +UCHAR *entry_ptr; +UCHAR *work_ptr; +UCHAR *read_ptr; +UINT found; +UINT i, j; + + + /* First of all, search for a match in the TNI area. */ + entry_ptr = _tx_el_tni_start; + i = 0; + while (i < TX_EL_TNIS) + { + + /* Determine if this entry is a match. */ + work_ptr = entry_ptr; + read_ptr = (UCHAR *) thread_ptr -> tx_thread_name; + found = TX_TRUE; + j = 0; + do + { + + /* Determine if this character is the same. */ + if (*work_ptr != *read_ptr) + { + + /* Set found to false and fall out of the loop. */ + found = TX_FALSE; + break; + } + else if (*work_ptr == 0) + { + + /* Null terminated, just break the loop. */ + break; + } + else + { + + /* Copy a character of thread's name into TNI area of log. */ + *work_ptr++ = *read_ptr++; + } + + /* Increment the character count. */ + j++; + + } while(j < TX_EL_TNIS); + + + /* Was a match found? */ + if (found) + { + + /* Yes, mark the entry as available now. */ + *(entry_ptr + TX_EL_TNI_VALID_OFFSET) = TX_EL_INVALID_ENTRY; + + /* Get out of the loop! */ + break; + } + + /* Otherwise, increment the associated pointers and indices. */ + i++; + entry_ptr = entry_ptr + TX_EL_TNI_ENTRY_SIZE; + } + + /* Determine status to return. */ + if (found) + return(TX_SUCCESS); + else + return(TX_EL_NAME_NOT_FOUND); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_user_event_insert PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function inserts a user event into the event log. */ +/* If the event log is full, the oldest event is overwritten. */ +/* */ +/* INPUT */ +/* */ +/* sub_type Event subtype for kernel call */ +/* info_1 First information field */ +/* info_2 Second information field */ +/* info_3 Third information field */ +/* info_4 Fourth information field */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX services */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_el_user_event_insert(UINT sub_type, ULONG info_1, ULONG info_2, + ULONG info_3, ULONG info_4) +{ + +TX_INTERRUPT_SAVE_AREA + +UINT upper_tb; +UCHAR *entry_ptr; + + /* Disable interrupts. */ + TX_DISABLE + + /* Increment total event counter. */ + _tx_el_total_events++; + + /* Setup working entry pointer first. */ + entry_ptr = *_tx_el_current_event; + + /* Store the event type. */ + *((unsigned short *) entry_ptr) = (unsigned short) TX_EL_USER_EVENT; + + /* Store the event subtype. */ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = + (unsigned short) sub_type; + + /* Get time stamp. */ + do + { + + /* Pickup the upper tb. */ + upper_tb = (ULONG) read_tbu(); + + /* Store the upper time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = + (ULONG) upper_tb; + + /* Store the lower time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) = + (ULONG) read_tbl(); + } while (upper_tb != (ULONG) read_tbu()); + + /* Store the current thread. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) = + (ULONG) _tx_thread_current_ptr; + + /* Store the first info field. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_1_OFFSET)) = + (ULONG) info_1; + + /* Store the second info field. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_2_OFFSET)) = + (ULONG) info_2; + + /* Store the third info field. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_3_OFFSET)) = + (ULONG) info_3; + + /* Store the fourth info field. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_4_OFFSET)) = + (ULONG) info_4; + + /* Now move the current event log pointer. */ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE; + + /* Check for a wraparound condition. */ + if (entry_ptr >= _tx_el_event_area_end) + { + + /* Yes, we have wrapped around to the end of the event area. + Start back at the top! */ + entry_ptr = _tx_el_event_area_start; + } + + /* Write the entry pointer back into the header. */ + *_tx_el_current_event = entry_ptr; + + /* Restore interrupts. */ + TX_RESTORE +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_thread_running PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function inserts a thread change event into the event */ +/* log, which indicates that a context switch is taking place. */ +/* If the event log is full, the oldest event is overwritten. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread being */ +/* scheduled */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_schedule ThreadX scheduler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_el_thread_running(TX_THREAD *thread_ptr) +{ + +UINT upper_tb; +UCHAR *entry_ptr; + + TX_EL_NO_STATUS_EVENTS + + /* Increment total event counter. */ + _tx_el_total_events++; + + /* Setup working entry pointer first. */ + entry_ptr = *_tx_el_current_event; + + /* Store the event type. */ + *((unsigned short *) entry_ptr) = (unsigned short) TX_EL_THREAD_CHANGE; + + /* Store the event subtype. */ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = + (unsigned short) 0; + + /* Get time stamp. */ + do + { + + /* Pickup the upper tb. */ + upper_tb = (ULONG) read_tbu(); + + /* Store the upper time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = + (ULONG) upper_tb; + + /* Store the lower time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) = + (ULONG) read_tbl(); + } while (upper_tb != (ULONG) read_tbu()); + + /* Store the current thread. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) = + (ULONG) thread_ptr; + + /* Now move the current event log pointer. */ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE; + + /* Check for a wraparound condition. */ + if (entry_ptr >= _tx_el_event_area_end) + { + + /* Yes, we have wrapped around to the end of the event area. + Start back at the top! */ + entry_ptr = _tx_el_event_area_start; + } + + /* Write the entry pointer back into the header. */ + *_tx_el_current_event = entry_ptr; + + TX_EL_END_FILTER +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_thread_preempted PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function inserts a thread preempted event into the event */ +/* log, which indicates that an interrupt occurred that made a higher */ +/* priority thread ready for execution. In this case, the previously */ +/* executing thread has an event entered to indicate it is no longer */ +/* running. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread being */ +/* scheduled */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_context_restore ThreadX context restore */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_el_thread_preempted(TX_THREAD *thread_ptr) +{ + +UINT upper_tb; +UCHAR *entry_ptr; + + + TX_EL_NO_STATUS_EVENTS + + /* Increment total event counter. */ + _tx_el_total_events++; + + /* Setup working entry pointer first. */ + entry_ptr = *_tx_el_current_event; + + /* Store the event type. */ + *((unsigned short *) entry_ptr) = (unsigned short) TX_EL_THREAD_STATUS_CHANGE; + + /* Store the event subtype. */ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = + (unsigned short) TX_READY; + + /* Get time stamp. */ + do + { + + /* Pickup the upper tb. */ + upper_tb = (ULONG) read_tbu(); + + /* Store the upper time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = + (ULONG) upper_tb; + + /* Store the lower time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) = + (ULONG) read_tbl(); + } while (upper_tb != (ULONG) read_tbu()); + + /* Store the current thread. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) = + (ULONG) _tx_thread_current_ptr; + + /* Now move the current event log pointer. */ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE; + + /* Check for a wraparound condition. */ + if (entry_ptr >= _tx_el_event_area_end) + { + + /* Yes, we have wrapped around to the end of the event area. + Start back at the top! */ + entry_ptr = _tx_el_event_area_start; + } + + /* Write the entry pointer back into the header. */ + *_tx_el_current_event = entry_ptr; + + TX_EL_END_FILTER +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_interrupt PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function inserts an interrupt event into the log, which */ +/* indicates the start of interrupt processing for the specific */ +/* */ +/* INPUT */ +/* */ +/* interrupt_number Interrupt number supplied by */ +/* ISR */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISR processing */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_el_interrupt(UINT interrupt_number) +{ + +UINT upper_tb; +UCHAR *entry_ptr; + + + TX_EL_NO_INTERRUPT_EVENTS + + /* Increment total event counter. */ + _tx_el_total_events++; + + /* Setup working entry pointer first. */ + entry_ptr = *_tx_el_current_event; + + /* Store the event type. */ + *((unsigned short *) entry_ptr) = (unsigned short) TX_EL_INTERRUPT; + + /* Store the event subtype. */ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = + (unsigned short) TX_EL_INTERRUPT_SUB_TYPE; + + /* Get time stamp. */ + do + { + + /* Pickup the upper tb. */ + upper_tb = (ULONG) read_tbu(); + + /* Store the upper time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = + (ULONG) upper_tb; + + /* Store the lower time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) = + (ULONG) read_tbl(); + } while (upper_tb != (ULONG) read_tbu()); + + /* Store the current thread. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) = + (ULONG) _tx_thread_current_ptr; + + /* Store the first info word. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_1_OFFSET)) = + (ULONG) interrupt_number; + + /* Now move the current event log pointer. */ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE; + + /* Check for a wraparound condition. */ + if (entry_ptr >= _tx_el_event_area_end) + { + + /* Yes, we have wrapped around to the end of the event area. + Start back at the top! */ + entry_ptr = _tx_el_event_area_start; + } + + /* Write the entry pointer back into the header. */ + *_tx_el_current_event = entry_ptr; + + TX_EL_END_FILTER +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_interrupt_end PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function inserts an interrupt end event into the log, which */ +/* indicates the end of interrupt processing for the specific */ +/* */ +/* INPUT */ +/* */ +/* interrupt_number Interrupt number supplied by */ +/* ISR */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISR processing */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_el_interrupt_end(UINT interrupt_number) +{ + +UINT upper_tb; +UCHAR *entry_ptr; + + + TX_EL_NO_INTERRUPT_EVENTS + + /* Increment total event counter. */ + _tx_el_total_events++; + + /* Setup working entry pointer first. */ + entry_ptr = *_tx_el_current_event; + + /* Store the event type. */ + *((unsigned short *) entry_ptr) = (unsigned short) TX_EL_INTERRUPT; + + /* Store the event subtype. */ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = + (unsigned short) TX_EL_END_OF_INTERRUPT; + + /* Get time stamp. */ + do + { + + /* Pickup the upper tb. */ + upper_tb = (ULONG) read_tbu(); + + /* Store the upper time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = + (ULONG) upper_tb; + + /* Store the lower time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) = + (ULONG) read_tbl(); + } while (upper_tb != (ULONG) read_tbu()); + + /* Store the current thread. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) = + (ULONG) _tx_thread_current_ptr; + + /* Store the first info word. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_1_OFFSET)) = + (ULONG) interrupt_number; + + /* Now move the current event log pointer. */ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE; + + /* Check for a wraparound condition. */ + if (entry_ptr >= _tx_el_event_area_end) + { + + /* Yes, we have wrapped around to the end of the event area. + Start back at the top! */ + entry_ptr = _tx_el_event_area_start; + } + + /* Write the entry pointer back into the header. */ + *_tx_el_current_event = entry_ptr; + + TX_EL_END_FILTER +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_interrupt_control PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function remaps the tx_interrupt_control service call so that */ +/* it can be tracked in the event log. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt posture */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_interrupt_control Interrupt control service */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX services */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _tx_el_interrupt_control(UINT new_posture) +{ + +TX_INTERRUPT_SAVE_AREA +UINT old_posture; + + + TX_EL_NO_INTERRUPT_EVENTS + + TX_DISABLE + TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_INTERRUPT_CONTROL, _tx_thread_current_ptr, new_posture) + TX_RESTORE + + TX_EL_END_FILTER + + old_posture = _tx_thread_interrupt_control(new_posture); + return(old_posture); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_event_log_on PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function disables all event filters. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_el_event_log_on(void) +{ + + /* Disable all event filters. */ + _tx_el_event_filter = TX_EL_ENABLE_ALL_EVENTS; +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_event_log_off PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets all event filters, thereby turning event */ +/* logging off. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_el_event_log_off(void) +{ + + /* Set all event filters. */ + _tx_el_event_filter = TX_EL_FILTER_ALL_EVENTS; +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_event_log_set PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets the events filters specified by the user. */ +/* */ +/* INPUT */ +/* */ +/* filter Events to filter */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_el_event_filter_set(UINT filter) +{ + + /* Apply the user event filter. */ + _tx_el_event_filter = filter; +} + diff --git a/ports/cortex_m3/ghs/src/tx_ghs.c b/ports/cortex_m3/ghs/src/tx_ghs.c new file mode 100644 index 00000000..0be9d715 --- /dev/null +++ b/ports/cortex_m3/ghs/src/tx_ghs.c @@ -0,0 +1,485 @@ +/* + * ThreadX C/C++ Library Support + * + * Copyright 1983-2019 Green Hills Software LLC. + * + * This program is the property of Green Hills Software LLC., + * its contents are proprietary information and no part of it + * is to be disclosed to anyone except employees of Green Hills + * Software LLC., or as agreed in writing signed by the President + * of Green Hills Software LLC. + */ + +#include "tx_ghs.h" +#ifndef TX_DISABLE_ERROR_CHECKING +#define TX_DISABLE_ERROR_CHECKING +#endif +#include "tx_api.h" +#include +#include + +/* Allow these routines to access the following ThreadX global variables. */ +extern ULONG _tx_thread_created_count; +extern TX_THREAD *_tx_thread_created_ptr; +extern TX_THREAD *_tx_thread_current_ptr; + +#if defined(__ghs) && (__GHS_VERSION_NUMBER >= 500) +/* Thread-local storage routines for Green Hills releases 5.x and above. */ +/* + Thread-Local (Per-Thread) Library Data Retrieval + ================================================ + + __ghs_ThreadLocalStorage_specifier defines all library data items + that the Green Hills libraries allow to be allocated per-thread. + + An implementation can choose which of these data items to allocate + for each thread. For example, an implementation may choose to + allocate an errno value for each thread, but not the strtok_saved_pos + pointer. The application could then use strtok_r instead of strtok for + correct operation. + + To add per-thread library data, define one of the + TX_THREAD_EXTENSION_* macros in tx_port.h to include the data item + or items in each thread control block TX_THREAD. + + If C++ with exceptions is being used, the __eh_globals entry must be + allocated for each thread. This is typically done by default using + TX_THREAD_EXTENSION_1 in tx_port.h. + + If __ghs_GetThreadLocalStorageItem is customized to return a + per-thread errno value, you should also: + + * Customize the System Library for your project + * Define the preprocessor symbol USE_THREAD_LOCAL_ERRNO in + src/libsys/ind_errn.c + + If you customize the System Library, you should remove ind_thrd.c + from the libsys.gpj subproject. + + */ + +/* Provide global __eh_globals value to support C++ exception handling + outside a thread context. This name also forces this module to be + included in the linked program instead of the ind_thrd.o module from + the System Library libsys.a. + */ +static void *__eh_globals; + +#pragma ghs startnomisra +void *__ghs_GetThreadLocalStorageItem(int specifier) +{ + void *ptlsitem = (void *)0; + switch (specifier) { + case (int)__ghs_TLS_Errno: + /* Set ptslsitem to the address of the per-thread errno value. + The per-thread errno value should have the type int. + + If returning a per-thread errno value, follow the steps + above. + + This item is used by numerous library functions. + */ + break; + case (int)__ghs_TLS_SignalHandlers: + /* Set ptslsitem to the address of the per-thread SignalHandlers + array. The per-thread SignalHandlers array should have the + array type as in the following declaration: + SignalHandler SignalHandlers[_SIGMAX]; + The SignalHandler type and _SIGMAX constant are defined in + ind_thrd.h. + + This item is used by the library functions signal() and + raise(). + */ + break; + case (int)__ghs_TLS_asctime_buff: + /* Set ptslsitem to the address of the per-thread asctime_buff + array. The per-thread asctime_buff array should have the + array type as in the following declaration: + char asctime_buff[30]; + + This item is used by the library functions asctime() and + ctime(). The library provides asctime_r() and ctime_r(), + inherently thread-safe versions of these functions. + */ + break; + case (int)__ghs_TLS_tmpnam_space: + /* Set ptslsitem to the address of the per-thread tmpnam_space + array. The per-thread tmpnam_space array should have the + array type as in the following declaration: + char tmpnam_space[L_tmpnam]; + The constant is defined in + + This item is used by the library function tmpnam() when + passed NULL. The library provides tmpnam_r(), an + inherently thread-safe version of tmpnam(). + */ + break; + case (int)__ghs_TLS_strtok_saved_pos: + /* Set ptslsitem to the address of the per-thread + strtok_saved_pos pointer. The per-thread strtok_saved_pos + pointer should have the type "char *". + + This item is used by the library function strtok(). + The library provides strtok_r(), an inherently thread-safe + version of strtok(). + */ + break; + case (int)__ghs_TLS_gmtime_temp: + /* Set ptslsitem to the address of the per-thread gmtime_temp + value. The per-thread gmtime_temp value should have the + type "struct tm" defined in time.h, included by indos.h. + + This item is used by the library functions gmtime() and + localtime(). The library provides gmtime_r() and + localtime_r(), inherently thread-safe versions of these + functions. + */ + break; + case (int)__ghs_TLS___eh_globals: + /* Set ptslsitem to the address of the per-thread __eh_globals + value. The per-thread __eh_globals value should have the + type "void *". + + This item is used by C++ exception handling. + */ + if (_tx_thread_current_ptr) + ptlsitem = (void *)&(_tx_thread_current_ptr->tx_thread_eh_globals); + else + /* Use the global __eh_globals pointer. */ + ptlsitem = (void *)&__eh_globals; + break; + } + return ptlsitem; +} +#pragma ghs endnomisra +#else +/* Thread-local storage routines for Green Hills releases 4.x and 3.x . */ + +/* + * ThreadX C and C++ thread-safe library support routines. + * + * This implementation merely tries to guarantee thread safety within + * individual C library calls such as malloc() and free(), but it does + * not attempt to solve the problems associated with the following + * multithreaded issues: + * + * 1. Use of errno. This can be made thread-safe by adding errno + * to TX_THREAD_PORT_EXTENSION and using that within a modified + * version of libsys/ind_errno.c. + * + * 2. Thread safety ACROSS library calls. Certain C library calls either + * return pointers to statically-allocated data structures or maintain + * state across calls. These include strtok(), asctime(), gmtime(), + * tmpnam(NULL), signal(). To make such C library routines thread-safe + * would require adding a ThreadLocalStorage struct to the thread control + * block TX_THREAD. Since relatively few applications make use of these + * library routines, the implementation provided here uses a single, global + * ThreadLocalStorage data structure rather than greatly increasing the size + * of the thread control block TX_THREAD. + * + * The ThreadX global variable _tx_thread_current_ptr points to the + * current thread's control block TX_THREAD. If a ThreadLocalStorage struct + * called tx_tls is placed in TX_THREAD, the function GetThreadLocalStorage + * should be modified to return &(_tx_thread_current_ptr->tx_tls). + */ + +static ThreadLocalStorage GlobalTLS; + +ThreadLocalStorage *GetThreadLocalStorage() +{ + return &GlobalTLS; +} +#endif + +/* + * Use a global ThreadX mutex to implement thread safety within C and C++ + * library routines. + * + */ +TX_MUTEX __ghLockMutex; + +/* + * Acquire general lock. Blocks until the lock becomes available. + * Use tx_mutex_get to implement __ghsLock + */ +void __ghsLock(void) +{ + tx_mutex_get(&__ghLockMutex, TX_WAIT_FOREVER); +} + +/* + * Release general lock + * Use tx_mutex_put to implement __ghsUnlock + */ +void __ghsUnlock(void) +{ + tx_mutex_put(&__ghLockMutex); +} + +/* ThreadX Initialization function prototype. */ +void _tx_initialize_kernel_setup(void); + +void __gh_lock_init(void) +{ + /* Initialize the low-level portions of ThreadX. */ + _tx_initialize_kernel_setup(); + + /* Create the global thread lock mutex. */ + tx_mutex_create(&__ghLockMutex, "__ghLockMutex", TX_NO_INHERIT); +} + +/* + Saving State Across setjmp() Calls + ================================== + + These routines can be used to save and restore arbitrary state + across calls to setjmp() and longjmp(). +*/ +int __ghs_SaveSignalContext(jmp_buf jmpbuf) +{ + return 0; +} + +/* Restore arbitrary state across a longjmp() */ +void __ghs_RestoreSignalContext(jmp_buf jmpbuf) +{ +} + +#if defined(__GHS_VERSION_NUMBER) && (__GHS_VERSION_NUMBER < 560) +/* + C++ Exception Handling + ====================== + + These routines allow C++ exceptions to be used in multiple threads. + The default implementation uses __ghs_GetThreadLocalStorageItem + to return a thread-specific __eh_globals pointer. + +*/ + +/* Must be called after __cpp_exception_init() is called to allocate + * and initialize the per-thread exception handling structure */ +void *__get_eh_globals(void) +{ +#if defined(__ghs) && (__GHS_VERSION_NUMBER >= 500) + return *(void **)__ghs_GetThreadLocalStorageItem(__ghs_TLS___eh_globals); +#else + if (_tx_thread_current_ptr) + + /* Return thread-specific __eh_globals pointer. */ + return _tx_thread_current_ptr->tx_thread_eh_globals; + else + /* Return the global __eh_globals pointer. */ + return GlobalTLS.__eh_globals; +#endif +} +#endif + +#if defined(__ghs) && (__GHS_VERSION_NUMBER >= 500) +#pragma weak __cpp_exception_init +extern void __cpp_exception_init(void **); +#pragma weak __cpp_exception_cleanup +extern void __cpp_exception_cleanup(void **); + +/* __tx_cpp_exception_init retrieves the eh_globals field from + thread-local storage and calls __cpp_exception_init. + */ +void __tx_cpp_exception_init(TX_THREAD *thread_ptr) { + void **peh_globals; + if(__cpp_exception_init) { + if (thread_ptr) + peh_globals = &(thread_ptr->tx_thread_eh_globals); + else + /* Use the global __eh_globals pointer. */ + peh_globals = &__eh_globals; + __cpp_exception_init(peh_globals); + } +} + +/* __tx_cpp_exception_cleanup retrieves the eh_globals field from + thread-local storage and calls __cpp_exception_cleanup. + */ +void __tx_cpp_exception_cleanup(TX_THREAD *thread_ptr) { + void **peh_globals; + if(__cpp_exception_cleanup) { + if (thread_ptr) + peh_globals = &(thread_ptr->tx_thread_eh_globals); + else + /* Use the global __eh_globals pointer. */ + peh_globals = &__eh_globals; + __cpp_exception_cleanup(peh_globals); + } +} + +/* __ghs_cpp_exception_init is called from ind_crt1.o to initialize + exceptions for the global context. + */ +void __ghs_cpp_exception_init() { + __tx_cpp_exception_init((void *)0); +} + +/* __ghs_cpp_exception_cleanup is called from ind_exit.o to clean up + exceptions for the global context. + */ +void __ghs_cpp_exception_cleanup(TX_THREAD *thread_ptr) { + __tx_cpp_exception_cleanup((void *)0); +} +#endif + + +/* + File Locks + ====================== + + These routines can be customized to implement per-file locks to allow + thread-safe I/O. + +*/ + +/* Acquire lock for FILE *addr */ +void __ghs_flock_file(void *addr) +{ + tx_mutex_get((TX_MUTEX *)addr, TX_WAIT_FOREVER); +} + +/* Release lock for FILE *addr */ +void __ghs_funlock_file(void *addr) +{ + tx_mutex_put((TX_MUTEX *)addr); +} + +/* Non blocking acquire lock for FILE *addr. May return -1 if */ +/* not implemented. Returns 0 on success and nonzero otherwise. */ +int __ghs_ftrylock_file(void *addr) +{ + return -1; +} + +/* Calls to initialize local lock data structures before they */ +/* are used. */ +void __ghs_flock_create(void **addr) +{ + *addr = (void *)(&__ghLockMutex); +} +void __ghs_flock_destroy(void *addr) {} + + +/* + * ThreadX Peak Stack Checking support routines. + * + * All of these routines are called by MULTI's ThreadX-aware debugging + * package to determine the peak stack use for one thread or for all threads. + * + * These routines are included in this file in order to guarantee that they will + * be available while debugging with MULTI. These routines are not referenced by + * any other part of the ThreadX system. + * + * _txs_thread_stack_check: return the peak stack usage for a thread. + * + * _txs_thread_stack_check_2: store the peak stack usage for all threads + * in the tx_thread_stack_size field of each thread + * control block, TX_THREAD. This routine takes + * advantage of the redundancy within the TX_THREAD + * structure since tx_thread_stack_size can be computed + * from the tx_thread_stack_start and tx_thread_stack_end + * fields of TX_THREAD. + * + * _txs_thread_stack_check_2_fixup: clean up from the _txs_thread_stack_check_2 + * call by computing the stack size for each + * thread and storing the result in the + * tx_thread_stack_size field of each thread control + * block TX_THREAD. + * + * These three routines do not support architectures such as i960 or StarCore + * where the stack grows up instead of down. + * + */ +#ifndef TX_DISABLE_STACK_CHECKING + +ULONG _txs_thread_stack_check(TX_THREAD *thread_ptr) +{ + CHAR *cp; /* Pointer inside thread's stack. */ + + /* Search through the thread's stack to find the highest address modified. */ + for ( cp = (CHAR *)thread_ptr->tx_thread_stack_start; + cp <= (CHAR *)thread_ptr->tx_thread_stack_end; ++cp ) { + + /* Check if this byte in the stack contains something other than TX_STACK_FILL. */ + if (*cp != (char)TX_STACK_FILL) { + + /* Assume cp points to the locating marking the peak stack use. + Return the number of bytes from cp up to and including the + end of the stack. */ + return (((ULONG)thread_ptr->tx_thread_stack_end) - (ULONG)cp + 1); + } + } + return thread_ptr->tx_thread_stack_size; +} + + +int _txs_thread_stack_check_2(void) { + CHAR * cp; /* Pointer inside thread's stack. */ + TX_THREAD * tp; /* Pointer to each thread. */ + + /* If no threads are created, return immediately. */ + if (!_tx_thread_created_count) + return 0; + + /* Start iterating through the threads in the system. Assume that we always + have at least one thread (the system timer thread) in the system. */ + tp = _tx_thread_created_ptr; + + do { + + /* Search through the thread's stack to find the highest address modified. */ + for ( cp = (CHAR *)tp->tx_thread_stack_start; cp <= (CHAR *)tp->tx_thread_stack_end; + ++cp ) { + + /* Check if this byte in the stack contains something other than TX_STACK_FILL. */ + if (*cp != (char)TX_STACK_FILL) { + + /* Assume cp points to the locating marking the peak stack use. + Store the number of bytes from cp up to and including the + end of the stack in the tx_thread_stack_size field. */ + tp->tx_thread_stack_size = ((ULONG)tp->tx_thread_stack_end) - (ULONG)cp + 1; + break; + } + + } + + /* Continue with the next thread. */ + tp = tp->tx_thread_created_next; + + /* Loop until we point to the first thread again. */ + } while ( tp != _tx_thread_created_ptr ); + + return 0; +} + +int _txs_thread_stack_check_2_fixup(void) { + TX_THREAD * tp; /* Pointer to each thread. */ + + /* If no threads are created, return immediately. */ + if (!_tx_thread_created_count) + return 0; + + /* Start iterating through the threads in the system. Assume that we always + have at least one thread (the system timer thread) in the system. */ + tp = _tx_thread_created_ptr; + + do { + + /* Compute the tx_thread_stack_size field by using the tx_thread_stack_end and + tx_thread_stack_start fields. */ + tp->tx_thread_stack_size = (ULONG)tp->tx_thread_stack_end-(ULONG)tp->tx_thread_stack_start+1; + + /* Continue with the next thread. */ + tp = tp->tx_thread_created_next; + + /* Loop until we point to the first thread again. */ + } while ( tp != _tx_thread_created_ptr ); + + return 0; +} + +#endif /* TX_DISABLE_STACK_CHECKING */ diff --git a/ports/cortex_m3/ghs/src/tx_ghse.c b/ports/cortex_m3/ghs/src/tx_ghse.c new file mode 100644 index 00000000..6369df77 --- /dev/null +++ b/ports/cortex_m3/ghs/src/tx_ghse.c @@ -0,0 +1,49 @@ +/* + * ThreadX C++ Library Support + * + * Copyright 1983-2019 Green Hills Software LLC. + * + * This program is the property of Green Hills Software LLC., + * its contents are proprietary information and no part of it + * is to be disclosed to anyone except employees of Green Hills + * Software LLC., or as agreed in writing signed by the President + * of Green Hills Software LLC. + */ +#include "tx_ghs.h" +#ifndef TX_DISABLE_ERROR_CHECKING +#define TX_DISABLE_ERROR_CHECKING +#endif +#include "tx_api.h" + +/* + C++ Exception Handling + ====================== + + These routines allow C++ exceptions to be used in multiple threads. + The default implementation uses __ghs_GetThreadLocalStorageItem + to return a thread-specific __eh_globals pointer. + +*/ + +#if defined(__ghs) && (__GHS_VERSION_NUMBER >= 560) +#ifdef _WIN32 +/* Windows uses a different linker, so include a stub routine, never called, + to pull in __cpp_exception_init and __cpp_exception_cleanup */ +extern void __cpp_exception_init(void **); +extern void __cpp_exception_cleanup(void **); +void __tx_win32_pull_in_exceptions(void) { + __cpp_exception_init(0); + __cpp_exception_cleanup(0); +} +#else +#pragma ghs reference __cpp_exception_init +#pragma ghs reference __cpp_exception_cleanup +#endif + +/* Must be called after __cpp_exception_init() is called to allocate + * and initialize the per-thread exception handling structure */ +void *__get_eh_globals(void) +{ + return *(void **)__ghs_GetThreadLocalStorageItem(__ghs_TLS___eh_globals); +} +#endif diff --git a/ports/cortex_m3/ghs/src/tx_thread_context_restore.arm b/ports/cortex_m3/ghs/src/tx_thread_context_restore.arm new file mode 100644 index 00000000..c79616b5 --- /dev/null +++ b/ports/cortex_m3/ghs/src/tx_thread_context_restore.arm @@ -0,0 +1,87 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + .text + .align 4 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-M3/GHS */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* [_tx_execution_isr_exit] Execution profiling ISR exit */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + .globl _tx_thread_context_restore +_tx_thread_context_restore: + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + PUSH {r0, lr} ; Save return address + BL _tx_execution_isr_exit ; Call the ISR exit function + POP {r0, lr} ; Save return address +#endif +; + POP {lr} + BX lr +; +;} + .type _tx_thread_context_restore,$function + .size _tx_thread_context_restore,.-_tx_thread_context_restore diff --git a/ports/cortex_m3/ghs/src/tx_thread_context_save.arm b/ports/cortex_m3/ghs/src/tx_thread_context_save.arm new file mode 100644 index 00000000..6b5fd6e0 --- /dev/null +++ b/ports/cortex_m3/ghs/src/tx_thread_context_save.arm @@ -0,0 +1,85 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + .text + .align 4 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-M3/GHS */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + .globl _tx_thread_context_save +_tx_thread_context_save: +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is starting. */ +; + PUSH {r0, lr} ; Save return address + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {r0, lr} ; Recover return address +#endif +; +; /* Context is already saved - just return! */ +; + BX lr +;} + .type _tx_thread_context_save,$function + .size _tx_thread_context_save,.-_tx_thread_context_save diff --git a/ports/cortex_m3/ghs/src/tx_thread_interrupt_control.arm b/ports/cortex_m3/ghs/src/tx_thread_interrupt_control.arm new file mode 100644 index 00000000..ba145a69 --- /dev/null +++ b/ports/cortex_m3/ghs/src/tx_thread_interrupt_control.arm @@ -0,0 +1,75 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + .text + .align 4 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-M3/GHS */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + .globl _tx_thread_interrupt_control +_tx_thread_interrupt_control: + MRS r1, PRIMASK ; Pickup current interrupt lockout + MSR PRIMASK, r0 ; Apply the new interrupt lockout + MOV r0, r1 ; Transfer old to return register + BX lr ; Return to caller +; +;} + .type _tx_thread_interrupt_control,$function + .size _tx_thread_interrupt_control,.-_tx_thread_interrupt_control diff --git a/ports/cortex_m3/ghs/src/tx_thread_interrupt_disable.arm b/ports/cortex_m3/ghs/src/tx_thread_interrupt_disable.arm new file mode 100644 index 00000000..2782be91 --- /dev/null +++ b/ports/cortex_m3/ghs/src/tx_thread_interrupt_disable.arm @@ -0,0 +1,85 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + .text + .align 4 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-M3/GHS */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts and returning */ +;/* the previous interrupt lockout posture. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_disable(UINT new_posture) +;{ + .globl _tx_thread_interrupt_disable +_tx_thread_interrupt_disable: +; +; /* Return current interrupt lockout posture. */ +; + MRS r0, PRIMASK + CPSID i + BX lr +; +;} + .type _tx_thread_interrupt_disable,$function + .size _tx_thread_interrupt_disable,.-_tx_thread_interrupt_disable diff --git a/ports/cortex_m3/ghs/src/tx_thread_interrupt_restore.arm b/ports/cortex_m3/ghs/src/tx_thread_interrupt_restore.arm new file mode 100644 index 00000000..ad957f9c --- /dev/null +++ b/ports/cortex_m3/ghs/src/tx_thread_interrupt_restore.arm @@ -0,0 +1,76 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + .text + .align 4 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-M3/GHS */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for restoring the previous */ +;/* interrupt lockout posture. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* previous_posture Previous interrupt posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_interrupt_restore(UINT new_posture) +;{ + .globl _tx_thread_interrupt_restore +_tx_thread_interrupt_restore: +; +; /* Restore previous interrupt lockout posture. */ +; + MSR PRIMASK, r0 + BX lr +; +;} + .type _tx_thread_interrupt_restore,$function + .size _tx_thread_interrupt_restore,.-_tx_thread_interrupt_restore diff --git a/ports/cortex_m3/ghs/src/tx_thread_schedule.arm b/ports/cortex_m3/ghs/src/tx_thread_schedule.arm new file mode 100644 index 00000000..61546f63 --- /dev/null +++ b/ports/cortex_m3/ghs/src/tx_thread_schedule.arm @@ -0,0 +1,236 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + .text + .align 4 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-M3/GHS */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + .globl _tx_thread_schedule +_tx_thread_schedule: +; +; /* This function should only ever be called on Cortex-M +; from the first schedule request. Subsequent scheduling occurs +; from the PendSV handling routines below. */ +; +; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ +; + MOV r0, #0 ; Build value for TX_FALSE + LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag + STR r0, [r2, #0] ; Clear preempt disable flag +; +; /* Enable interrupts */ +; + CPSIE i +; +; /* Enter the scheduler for the first time. */ +; + MOV r0, #0x10000000 ; Load PENDSVSET bit + MOV r1, #0xE000E000 ; Load NVIC base + STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR + DSB ; Complete all memory accesses + ISB ; Flush pipeline +; +; /* Wait here for the PendSV to take place. */ +; +__tx_wait_here: + B __tx_wait_here ; Wait for the PendSV to happen + + .type _tx_thread_schedule,$function + .size _tx_thread_schedule,.-_tx_thread_schedule +;} +; +; /* Generic context PendSV handler. */ +; + .globl PendSV_Handler + .globl __tx_PendSVHandler +PendSV_Handler: +__tx_PendSVHandler: +; +; /* Get current thread value and new thread pointer. */ +; +__tx_ts_handler: + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + CPSID i ; Disable interrupts + PUSH {r0, lr} ; Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit ; Call the thread exit function + POP {r0, lr} ; Recover LR + CPSIE i ; Enable interrupts +#endif + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r2, =_tx_thread_execute_ptr ; Build execute thread pointer address + MOV r3, #0 ; Build NULL value + LDR r1, [r0] ; Pickup current thread pointer +; +; /* Determine if there is a current thread to finish preserving. */ +; + CBZ r1, __tx_ts_new ; If NULL, skip preservation +; +; /* Recover PSP and preserve current thread context. */ +; + STR r3, [r0] ; Set _tx_thread_current_ptr to NULL + MRS r12, PSP ; Pickup PSP pointer (thread's stack pointer) + STMDB r12!, {r4-r11} ; Save its remaining registers + LDR r4, =_tx_timer_time_slice ; Build address of time-slice variable + STR.W LR, [r12, #-0x4]! ; Save LR on the stack +; +; /* Determine if time-slice is active. If it isn't, skip time handling processing. */ +; + LDR r5, [r4] ; Pickup current time-slice + STR r12, [r1, #8] ; Save the thread stack pointer + CBZ r5, __tx_ts_new ; If not active, skip processing +; +; /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ +; + STR r5, [r1, #24] ; Save current time-slice +; +; /* Clear the global time-slice. */ +; + STR r3, [r4] ; Clear time-slice +; +; +; /* Executing thread is now completely preserved!!! */ +; +__tx_ts_new: +; +; /* Now we are looking for a new thread to execute! */ +; + CPSID i ; Disable interrupts + LDR r1, [r2] ; Is there another thread ready to execute? + CBZ r1, __tx_ts_wait ; No, skip to the wait processing +; +; /* Yes, another thread is ready for else, make the current thread the new thread. */ +; + STR r1, [r0] ; Setup the current thread pointer to the new thread + CPSIE i ; Enable interrupts +; +; /* Increment the thread run count. */ +; +__tx_ts_restore: + LDR r7, [r1, #4] ; Pickup the current thread run count + LDR r4, =_tx_timer_time_slice ; Build address of time-slice variable + LDR r5, [r1, #24] ; Pickup thread's current time-slice + ADD r7, r7, #1 ; Increment the thread run count + STR r7, [r1, #4] ; Store the new run count +; +; /* Setup global time-slice with thread's current time-slice. */ +; + STR r5, [r4] ; Setup global time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + PUSH {r0, r1} ; Save r0/r1 + BL _tx_execution_thread_enter ; Call the thread execution enter function + POP {r0, r1} ; Recover r3 +#endif +; +; /* Restore the thread context and PSP. */ +; + LDR r12, [r1, #8] ; Pickup thread's stack pointer + LDR.W LR, [r12], #4 ; Pickup LR + LDMIA r12!, {r4-r11} ; Recover thread's registers + MSR PSP, r12 ; Setup the thread's stack pointer +; +; /* Return to thread. */ +; + BX lr ; Return to thread! +; +; /* The following is the idle wait processing... in this case, no threads are ready for execution and the +; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +; are disabled to allow use of WFI for waiting for a thread to arrive. */ +; +__tx_ts_wait: + CPSID i ; Disable interrupts + LDR r1, [r2] ; Pickup the next thread to execute pointer + STR r1, [r0] ; Store it in the current pointer + CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready! +#ifdef TX_ENABLE_WFI + DSB ; Ensure no outstanding memory transactions + WFI ; Wait for interrupt + ISB ; Ensure pipeline is flushed +#endif + CPSIE i ; Enable interrupts + B __tx_ts_wait ; Loop to continue waiting +; +; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +; already in the handler! */ +; +__tx_ts_ready: + MOV r7, #0x08000000 ; Build clear PendSV value + MOV r8, #0xE000E000 ; Build base NVIC address + STR r7, [r8, #0xD04] ; Clear any PendSV +; +; /* Re-enable interrupts and restore new thread. */ +; + CPSIE i ; Enable interrupts + B __tx_ts_restore ; Restore the thread +;} +; + .type __tx_PendSVHandler,$function + .size __tx_PendSVHandler,.-__tx_PendSVHandler diff --git a/ports/cortex_m3/ghs/src/tx_thread_stack_build.arm b/ports/cortex_m3/ghs/src/tx_thread_stack_build.arm new file mode 100644 index 00000000..0ccbb5de --- /dev/null +++ b/ports/cortex_m3/ghs/src/tx_thread_stack_build.arm @@ -0,0 +1,135 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + .text + .align 4 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-M3/GHS */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + .globl _tx_thread_stack_build +_tx_thread_stack_build: +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-M should look like the following after it is built: +; +; Stack Top: +; LR Interrupted LR (LR at time of PENDSV) +; r4 Initial value for r4 +; r5 Initial value for r5 +; r6 Initial value for r6 +; r7 Initial value for r7 +; r8 Initial value for r8 +; r9 Initial value for r9 +; r10 Initial value for r10 +; r11 Initial value for r11 +; r0 Initial value for r0 (Hardware stack starts here!!) +; r1 Initial value for r1 +; r2 Initial value for r2 +; r3 Initial value for r3 +; r12 Initial value for r12 +; lr Initial value for lr +; pc Initial value for pc +; xPSR Initial value for xPSR +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #0x7 ; Align frame for 8-byte alignment + SUB r2, r2, #68 ; Subtract frame size + LDR r3, =0xFFFFFFFD ; Build initial LR value + STR r3, [r2, #0] ; Save on the stack +; +; /* Actually build the stack frame. */ +; + MOV r3, #0 ; Build initial register value + STR r3, [r2, #4] ; Store initial r4 + STR r3, [r2, #8] ; Store initial r5 + STR r3, [r2, #12] ; Store initial r6 + STR r3, [r2, #16] ; Store initial r7 + STR r3, [r2, #20] ; Store initial r8 + STR r3, [r2, #24] ; Store initial r9 + STR r3, [r2, #28] ; Store initial r10 + STR r3, [r2, #32] ; Store initial r11 +; +; /* Hardware stack follows. */ +; + STR r3, [r2, #36] ; Store initial r0 + STR r3, [r2, #40] ; Store initial r1 + STR r3, [r2, #44] ; Store initial r2 + STR r3, [r2, #48] ; Store initial r3 + STR r3, [r2, #52] ; Store initial r12 + MOV r3, #0xFFFFFFFF ; Poison EXC_RETURN value + STR r3, [r2, #56] ; Store initial lr + STR r1, [r2, #60] ; Store initial pc + MOV r3, #0x01000000 ; Only T-bit need be set + STR r3, [r2, #64] ; Store initial xPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block + BX lr ; Return to caller +;} + .type _tx_thread_stack_build,$function + .size _tx_thread_stack_build,.-_tx_thread_stack_build diff --git a/ports/cortex_m3/ghs/src/tx_thread_system_return.arm b/ports/cortex_m3/ghs/src/tx_thread_system_return.arm new file mode 100644 index 00000000..64258d3f --- /dev/null +++ b/ports/cortex_m3/ghs/src/tx_thread_system_return.arm @@ -0,0 +1,87 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + .text + .align 4 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-M3/GHS */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + .globl _tx_thread_system_return +_tx_thread_system_return: +; +; /* Return to real scheduler via PendSV. Note that this routine is often +; replaced with in-line assembly in tx_port.h to improved performance. */ +; + MOV r0, #0x10000000 ; Load PENDSVSET bit + MOV r1, #0xE000E000 ; Load NVIC base + STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR + MRS r0, IPSR ; Pickup IPSR + CMP r0, #0 ; Is it a thread returning? + BNE _isr_context ; If ISR, skip interrupt enable + MRS r1, PRIMASK ; Thread context returning, pickup PRIMASK + CPSIE i ; Enable interrupts + MSR PRIMASK, r1 ; Restore original interrupt posture +_isr_context: + BX lr ; Return to caller +;} + .type _tx_thread_system_return,$function + .size _tx_thread_system_return,.-_tx_thread_system_return diff --git a/ports/cortex_m3/ghs/src/tx_timer_interrupt.arm b/ports/cortex_m3/ghs/src/tx_timer_interrupt.arm new file mode 100644 index 00000000..519a63cc --- /dev/null +++ b/ports/cortex_m3/ghs/src/tx_timer_interrupt.arm @@ -0,0 +1,243 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + .text + .align 4 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-M3/GHS */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* expiration functions are called. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + .globl _tx_timer_interrupt +_tx_timer_interrupt: +; +; /* Upon entry to this routine, it is assumed that the compiler scratch registers are available +; for use. */ +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + LDR r1, =_tx_timer_system_clock ; Pickup address of system clock + LDR r0, [r1, #0] ; Pickup system clock + ADD r0, r0, #1 ; Increment system clock + STR r0, [r1, #0] ; Store new system clock +; +; /* Test for time-slice expiration. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r2, [r3, #0] ; Pickup time-slice + CBZ r2, __tx_timer_no_time_slice ; Is it non-active? + ; Yes, skip time-slice processing +; +; /* Decrement the time_slice. */ +; _tx_timer_time_slice--; +; + SUB r2, r2, #1 ; Decrement the time-slice + STR r2, [r3, #0] ; Store new time-slice value +; +; /* Check for expiration. */ +; if (__tx_timer_time_slice == 0) +; + CBNZ r2, __tx_timer_no_time_slice ; Has it expired? +; +; /* Set the time-slice expired flag. */ +; _tx_timer_expired_time_slice = TX_TRUE; +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup address of expired flag + MOV r0, #1 ; Build expired value + STR r0, [r3, #0] ; Set time-slice expiration flag +; +; } +; +__tx_timer_no_time_slice: +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + LDR r1, =_tx_timer_current_ptr ; Pickup current timer pointer addr + LDR r0, [r1, #0] ; Pickup current timer + LDR r2, [r0, #0] ; Pickup timer list entry + CBZ r2, __tx_timer_no_timer ; Is there anything in the list? + ; No, just increment the timer +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + LDR r3, =_tx_timer_expired ; Pickup expiration flag address + MOV r2, #1 ; Build expired value + STR r2, [r3, #0] ; Set expired flag + B __tx_timer_done ; Finished timer processing +; +; } +; else +; { +__tx_timer_no_timer: +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ADD r0, r0, #4 ; Move to next timer +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + LDR r3, =_tx_timer_list_end ; Pickup addr of timer list end + LDR r2, [r3, #0] ; Pickup list end + CMP r0, r2 ; Are we at list end? + BNE __tx_timer_skip_wrap ; No, skip wrap-around logic +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + LDR r3, =_tx_timer_list_start ; Pickup addr of timer list start + LDR r0, [r3, #0] ; Set current pointer to list start +; +__tx_timer_skip_wrap: +; + STR r0, [r1, #0] ; Store new current timer pointer +; } +; +__tx_timer_done: +; +; +; /* See if anything has expired. */ +; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of expired flag + LDR r2, [r3, #0] ; Pickup time-slice expired flag + CBNZ r2, __tx_something_expired ; Did a time-slice expire? + ; If non-zero, time-slice expired + LDR r1, =_tx_timer_expired ; Pickup addr of other expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CBZ r0, __tx_timer_nothing_expired ; Did a timer expire? + ; No, nothing expired +; +__tx_something_expired: +; +; + STMDB sp!, {r0, lr} ; Save the lr register on the stack + ; and save r0 just to keep 8-byte alignment +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + LDR r1, =_tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CBZ r0, __tx_timer_dont_activate ; Check for timer expiration + ; If not set, skip timer activation +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + BL _tx_timer_expiration_process ; Call the timer expiration handling routine +; +; } +__tx_timer_dont_activate: +; +; /* Did time slice expire? */ +; if (_tx_timer_expired_time_slice) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r2, [r3, #0] ; Pickup the actual flag + CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set + ; No, skip time-slice processing +; +; /* Time slice interrupted thread. */ +; _tx_thread_time_slice(); + + BL _tx_thread_time_slice ; Call time-slice processing + LDR r0, =_tx_thread_preempt_disable ; Build address of preempt disable flag + LDR r1, [r0] ; Is the preempt disable flag set? + CBNZ r1, __tx_timer_skip_time_slice ; Yes, skip the PendSV logic + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup the current thread pointer + LDR r2, =_tx_thread_execute_ptr ; Build execute thread pointer address + LDR r3, [r2] ; Pickup the execute thread pointer + LDR r0, =0xE000ED04 ; Build address of control register + LDR r2, =0x10000000 ; Build value for PendSV bit + CMP r1, r3 ; Are they the same? + BEQ __tx_timer_skip_time_slice ; If the same, there was no time-slice performed + STR r2, [r0] ; Not the same, issue the PendSV for preemption +__tx_timer_skip_time_slice: +; +; } +; +__tx_timer_not_ts_expiration: +; + LDMIA sp!, {r0, lr} ; Recover lr register (r0 is just there for + ; the 8-byte stack alignment +; +; } +; +__tx_timer_nothing_expired: + + DSB ; Complete all memory access + BX lr ; Return to caller +; +;} + .type _tx_timer_interrupt,$function + .size _tx_timer_interrupt,.-_tx_timer_interrupt diff --git a/ports/cortex_m3/ghs/src/txr_ghs.c b/ports/cortex_m3/ghs/src/txr_ghs.c new file mode 100644 index 00000000..19572e2b --- /dev/null +++ b/ports/cortex_m3/ghs/src/txr_ghs.c @@ -0,0 +1,84 @@ +/* + * ThreadX API Runtime Error Support + * + * Copyright 1983-2019 Green Hills Software LLC. + * + * This program is the property of Green Hills Software LLC., + * its contents are proprietary information and no part of it + * is to be disclosed to anyone except employees of Green Hills + * Software LLC., or as agreed in writing signed by the President + * of Green Hills Software LLC. + */ + +/* #include "tx_ghs.h" */ +#ifndef TX_DISABLE_ERROR_CHECKING +#define TX_DISABLE_ERROR_CHECKING +#endif +#include "tx_api.h" + +/* Customized ThreadX API runtime error support routine. */ + +void _rnerr(int num, int linenum, const char*str, void*ptr, ...); + +/* __ghs_rnerr() + This is the custom runtime error checking routine. + This implementation uses the existing __rnerr() routine. + Another implementation could use the .syscall mechanism, + provided MULTI was modified to understand that. + */ +void __ghs_rnerr(char *errMsg, int stackLevels, int stackTraceDisplay, void *hexVal) { + TX_INTERRUPT_SAVE_AREA + int num; + /* + Initialize the stack levels value. + + Add 3 to account for the calls to _rnerr, __rnerr, and + __ghs_rnerr. + + If the implementation changes, calls to __ghs_rnerr + will not need to be changed. + + Zero is not permitted, so substitute 3 in that case. + */ + num = (stackLevels+3) & 0xf; + if (!num) { + num = 3; + } + /* + Shift the stack levels value to bits 12..15 and + insert the stack trace display value in bit 11. + Bits 0..10 are unused. + */ + num = (num << 12) | (stackTraceDisplay ? 0x800 : 0); + + /* This will mask all interrupts in the RTEC code, which is probably + unacceptable for many targets. */ + TX_DISABLE + _rnerr(num, -1, (const char *)hexVal, (void *)errMsg); + TX_RESTORE +} + + +/* ThreadX thread stack checking runtime support routine. */ + +extern char __ghsbegin_stack[]; +extern TX_THREAD *_tx_thread_current_ptr; + +void __stkchk(void) { + int i; + if(_tx_thread_current_ptr) + { + if((unsigned)(&i) <= + (unsigned)(_tx_thread_current_ptr -> tx_thread_stack_start)) + { + _rnerr(21, -1, 0, 0); + } + } + else + { + if((unsigned)(&i) <= (unsigned)__ghsbegin_stack) + { + _rnerr(21, -1, 0, 0); + } + } +} diff --git a/ports/cortex_m3/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_m3/gnu/example_build/tx_initialize_low_level.S index dd788e9d..e9e90aca 100644 --- a/ports/cortex_m3/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_m3/gnu/example_build/tx_initialize_low_level.S @@ -49,7 +49,7 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* FUNCTION RELEASE */ @/* */ @/* _tx_initialize_low_level Cortex-M3/GNU */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -83,12 +83,10 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 06-30-2020 William E. Lamie Modified Comment(s), fixed */ -@/* GNU assembly comment, */ -@/* resulting in version 6.0.1 */ -@/* 08-14-2020 William E. Lamie Modified Comment(s), clean */ +@/* 09-30-2020 William E. Lamie Modified Comment(s), fixed */ +@/* GNU assembly comment, clean */ @/* up whitespace, resulting */ -@/* in version 6.0.2 */ +@/* in version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_m3/gnu/inc/tx_port.h b/ports/cortex_m3/gnu/inc/tx_port.h index 76f9aea1..b5a75fd3 100644 --- a/ports/cortex_m3/gnu/inc/tx_port.h +++ b/ports/cortex_m3/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M3/GNU */ -/* 6.0 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ @@ -343,7 +345,7 @@ unsigned int interrupt_save; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/GNU Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/GNU Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_m3/gnu/readme_threadx.txt b/ports/cortex_m3/gnu/readme_threadx.txt index d1ccef31..bb4d396b 100644 --- a/ports/cortex_m3/gnu/readme_threadx.txt +++ b/ports/cortex_m3/gnu/readme_threadx.txt @@ -143,8 +143,8 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -08-14-2020 ThreadX update of Cortex-M3/GNU port. The following files were - changed/added for port specific version 6.0.2: +09-30-2020 ThreadX update of Cortex-M3/GNU port. The following files were + changed/added for port specific version 6.1: *.S Modified comments and whitespace. diff --git a/ports/cortex_m3/gnu/src/tx_thread_context_restore.S b/ports/cortex_m3/gnu/src/tx_thread_context_restore.S index eef563f8..8b99ed12 100644 --- a/ports/cortex_m3/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_m3/gnu/src/tx_thread_context_restore.S @@ -39,7 +39,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_restore Cortex-M3/GNU */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -74,9 +74,8 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Modified comment(s), */ +@/* resulting in version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m3/gnu/src/tx_thread_context_save.S b/ports/cortex_m3/gnu/src/tx_thread_context_save.S index fb7a3845..08c41b49 100644 --- a/ports/cortex_m3/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_m3/gnu/src/tx_thread_context_save.S @@ -34,7 +34,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_save Cortex-M3/GNU */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -68,9 +68,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 Scott Larson Modified comment(s), and */ +@/* cleaned up whitespace, */ +@/* resulting in version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m3/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_m3/gnu/src/tx_thread_interrupt_control.S index 731d4bc1..9fa37ca2 100644 --- a/ports/cortex_m3/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m3/gnu/src/tx_thread_interrupt_control.S @@ -29,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_control Cortex-M3/GNU */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -60,9 +60,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 Scott Larson Modified comment(s), and */ +@/* cleaned up whitespace, */ +@/* resulting in version 6.1 */ @/* */ @/**************************************************************************/ @/* UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_m3/gnu/src/tx_thread_schedule.S b/ports/cortex_m3/gnu/src/tx_thread_schedule.S index f244081e..b2689609 100644 --- a/ports/cortex_m3/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_m3/gnu/src/tx_thread_schedule.S @@ -37,7 +37,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule Cortex-M3/GNU */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -71,9 +71,8 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Modified comment(s), */ +@/* resulting in version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_m3/gnu/src/tx_thread_stack_build.S b/ports/cortex_m3/gnu/src/tx_thread_stack_build.S index cf8dbb50..37871fc3 100644 --- a/ports/cortex_m3/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_m3/gnu/src/tx_thread_stack_build.S @@ -29,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_stack_build Cortex-M3/GNU */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -62,14 +62,12 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 06-30-2020 William E. Lamie Modified Comment(s), setting */ -@/* R10 to top of stack is not */ -@/* needed. Removed references */ -@/* to stack frame, resulting */ -@/* in version 6.0.1 */ -@/* 08-14-2020 William E. Lamie Modified Comment(s), clean up */ +@/* 09-30-2020 William E. Lamie Modified Comment(s), setting */ +@/* R10 to top of stack is not */ +@/* needed. Removed references */ +@/* to stack frame, clean up */ @/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* in version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_m3/gnu/src/tx_thread_system_return.S b/ports/cortex_m3/gnu/src/tx_thread_system_return.S index f16b757f..3b26437a 100644 --- a/ports/cortex_m3/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_m3/gnu/src/tx_thread_system_return.S @@ -29,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_system_return Cortex-M3/GNU */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -62,9 +62,8 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Modified comment(s), */ +@/* resulting in version 6.1 */ @/* */ @/**************************************************************************/ @/* VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_m3/gnu/src/tx_timer_interrupt.S b/ports/cortex_m3/gnu/src/tx_timer_interrupt.S index 26b52acb..e2c0a33c 100644 --- a/ports/cortex_m3/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_m3/gnu/src/tx_timer_interrupt.S @@ -40,7 +40,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_timer_interrupt Cortex-M3/GNU */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -75,9 +75,8 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Modified comment(s), */ +@/* resulting in version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_m3/iar/example_build/tx_initialize_low_level.s b/ports/cortex_m3/iar/example_build/tx_initialize_low_level.s index 1e867c41..6e0dfdd3 100644 --- a/ports/cortex_m3/iar/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m3/iar/example_build/tx_initialize_low_level.s @@ -45,7 +45,7 @@ __tx_free_memory_start ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level Cortex-M3/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -78,10 +78,7 @@ __tx_free_memory_start ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_m3/iar/inc/tx_port.h b/ports/cortex_m3/iar/inc/tx_port.h index 538187c6..6c18fab3 100644 --- a/ports/cortex_m3/iar/inc/tx_port.h +++ b/ports/cortex_m3/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M3/IAR */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -357,7 +357,7 @@ __istate_t interrupt_save; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/IAR Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/IAR Version 6.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m3/iar/readme_threadx.txt b/ports/cortex_m3/iar/readme_threadx.txt index 427cc94e..c4b4af32 100644 --- a/ports/cortex_m3/iar/readme_threadx.txt +++ b/ports/cortex_m3/iar/readme_threadx.txt @@ -148,12 +148,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -08-14-2020 ThreadX update of Cortex-M3/IAR port. The following files were - changed/added for port specific version 6.0.2: - - *.s Modified comments and whitespace. - -06/30/2020 Initial ThreadX version 6.0.1 for Cortex-M3 using IAR's ARM tools. +09-30-2020 Initial ThreadX version 6.1 for Cortex-M3 using IAR's ARM tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_m3/iar/src/tx_misra.s b/ports/cortex_m3/iar/src/tx_misra.s index 62559a05..2531f6ee 100644 --- a/ports/cortex_m3/iar/src/tx_misra.s +++ b/ports/cortex_m3/iar/src/tx_misra.s @@ -101,7 +101,7 @@ SECTION `.data`:DATA:REORDER:NOROOT(2) DATA -// 51 CHAR _tx_version_id[100] = "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX 6.0 MISRA C Compliant *"; +// 51 CHAR _tx_version_id[100] = "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX 6.1 MISRA C Compliant *"; _tx_version_id: DC8 43H, 6FH, 70H, 79H, 72H, 69H, 67H, 68H DC8 74H, 20H, 28H, 63H, 29H, 20H, 31H, 39H diff --git a/ports/cortex_m3/iar/src/tx_thread_context_restore.s b/ports/cortex_m3/iar/src/tx_thread_context_restore.s index 977ac88d..9842f8ce 100644 --- a/ports/cortex_m3/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_m3/iar/src/tx_thread_context_restore.s @@ -31,7 +31,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore Cortex-M3/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -65,10 +65,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m3/iar/src/tx_thread_context_save.s b/ports/cortex_m3/iar/src/tx_thread_context_save.s index 977c2208..23462fdc 100644 --- a/ports/cortex_m3/iar/src/tx_thread_context_save.s +++ b/ports/cortex_m3/iar/src/tx_thread_context_save.s @@ -31,7 +31,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save Cortex-M3/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -64,10 +64,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m3/iar/src/tx_thread_interrupt_control.s b/ports/cortex_m3/iar/src/tx_thread_interrupt_control.s index b9685cbd..2c8bf932 100644 --- a/ports/cortex_m3/iar/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m3/iar/src/tx_thread_interrupt_control.s @@ -28,7 +28,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control Cortex-M3/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -58,10 +58,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_m3/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_m3/iar/src/tx_thread_interrupt_disable.s index cad6eb3c..af919f6f 100644 --- a/ports/cortex_m3/iar/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m3/iar/src/tx_thread_interrupt_disable.s @@ -28,7 +28,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-M3/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -58,10 +58,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(UINT new_posture) diff --git a/ports/cortex_m3/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_m3/iar/src/tx_thread_interrupt_restore.s index 1b895380..a10b571f 100644 --- a/ports/cortex_m3/iar/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m3/iar/src/tx_thread_interrupt_restore.s @@ -28,7 +28,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-M3/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -58,10 +58,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_interrupt_restore(UINT new_posture) diff --git a/ports/cortex_m3/iar/src/tx_thread_schedule.s b/ports/cortex_m3/iar/src/tx_thread_schedule.s index d4f30b62..e8a3c13d 100644 --- a/ports/cortex_m3/iar/src/tx_thread_schedule.s +++ b/ports/cortex_m3/iar/src/tx_thread_schedule.s @@ -37,7 +37,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M3/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -70,10 +70,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_m3/iar/src/tx_thread_stack_build.s b/ports/cortex_m3/iar/src/tx_thread_stack_build.s index 92a5c821..e5f23bc5 100644 --- a/ports/cortex_m3/iar/src/tx_thread_stack_build.s +++ b/ports/cortex_m3/iar/src/tx_thread_stack_build.s @@ -28,7 +28,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build Cortex-M3/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -60,10 +60,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -114,7 +111,7 @@ _tx_thread_stack_build: STR r3, [r2, #28] ; Store initial r10 STR r3, [r2, #32] ; Store initial r11 ; -; /* Hardware stack follows. / +; /* Hardware stack follows. */ ; STR r3, [r2, #36] ; Store initial r0 STR r3, [r2, #40] ; Store initial r1 diff --git a/ports/cortex_m3/iar/src/tx_thread_system_return.s b/ports/cortex_m3/iar/src/tx_thread_system_return.s index 1f440cc4..38fb892b 100644 --- a/ports/cortex_m3/iar/src/tx_thread_system_return.s +++ b/ports/cortex_m3/iar/src/tx_thread_system_return.s @@ -28,7 +28,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return Cortex-M3/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -60,10 +60,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_m3/iar/src/tx_timer_interrupt.s b/ports/cortex_m3/iar/src/tx_timer_interrupt.s index 1d1dc79a..58303af0 100644 --- a/ports/cortex_m3/iar/src/tx_timer_interrupt.s +++ b/ports/cortex_m3/iar/src/tx_timer_interrupt.s @@ -42,7 +42,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt Cortex-M3/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -75,10 +75,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_m3/keil/example_build/tx_initialize_low_level.s b/ports/cortex_m3/keil/example_build/tx_initialize_low_level.s index a82c22c2..8a2ecb64 100644 --- a/ports/cortex_m3/keil/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m3/keil/example_build/tx_initialize_low_level.s @@ -92,8 +92,8 @@ Reset_Handler ;/* */ ;/* FUNCTION RELEASE */ ;/* */ -;/* _tx_initialize_low_level Cortex-M3/RVDS */ -;/* 6.0.2 */ +;/* _tx_initialize_low_level Cortex-M3/AC5 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -126,10 +126,7 @@ Reset_Handler ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_m3/keil/inc/tx_port.h b/ports/cortex_m3/keil/inc/tx_port.h index 6b0adb0d..39ed4e53 100644 --- a/ports/cortex_m3/keil/inc/tx_port.h +++ b/ports/cortex_m3/keil/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M3/Keil */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -329,7 +329,7 @@ unsigned int was_masked; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/Keil Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/Keil Version 6.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m3/keil/readme_threadx.txt b/ports/cortex_m3/keil/readme_threadx.txt index a88ac72e..90f7f70a 100644 --- a/ports/cortex_m3/keil/readme_threadx.txt +++ b/ports/cortex_m3/keil/readme_threadx.txt @@ -142,12 +142,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -08-14-2020 ThreadX update of Cortex-M3/Keil port. The following files were - changed/added for port specific version 6.0.2: - - *.s Modified comments and whitespace. - -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M3 using Keil tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-M3 using Keil tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_m3/keil/src/tx_thread_context_restore.s b/ports/cortex_m3/keil/src/tx_thread_context_restore.s index 67731bce..14b1da0e 100644 --- a/ports/cortex_m3/keil/src/tx_thread_context_restore.s +++ b/ports/cortex_m3/keil/src/tx_thread_context_restore.s @@ -33,7 +33,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore Cortex-M3/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -67,10 +67,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m3/keil/src/tx_thread_context_save.s b/ports/cortex_m3/keil/src/tx_thread_context_save.s index f11b9a70..ae21c768 100644 --- a/ports/cortex_m3/keil/src/tx_thread_context_save.s +++ b/ports/cortex_m3/keil/src/tx_thread_context_save.s @@ -33,7 +33,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save Cortex-M3/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -66,10 +66,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m3/keil/src/tx_thread_interrupt_control.s b/ports/cortex_m3/keil/src/tx_thread_interrupt_control.s index 22ad0fb7..3c0f1768 100644 --- a/ports/cortex_m3/keil/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m3/keil/src/tx_thread_interrupt_control.s @@ -27,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control Cortex-M3/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -57,10 +57,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_m3/keil/src/tx_thread_interrupt_disable.s b/ports/cortex_m3/keil/src/tx_thread_interrupt_disable.s index 6fe29368..d66a11f0 100644 --- a/ports/cortex_m3/keil/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m3/keil/src/tx_thread_interrupt_disable.s @@ -27,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_disable Cortex-M3/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -57,10 +57,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(UINT new_posture) diff --git a/ports/cortex_m3/keil/src/tx_thread_interrupt_restore.s b/ports/cortex_m3/keil/src/tx_thread_interrupt_restore.s index 8123da28..df65a539 100644 --- a/ports/cortex_m3/keil/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m3/keil/src/tx_thread_interrupt_restore.s @@ -27,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-M3/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -57,10 +57,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_interrupt_restore(UINT new_posture) diff --git a/ports/cortex_m3/keil/src/tx_thread_schedule.s b/ports/cortex_m3/keil/src/tx_thread_schedule.s index c002e1f3..beae1e0f 100644 --- a/ports/cortex_m3/keil/src/tx_thread_schedule.s +++ b/ports/cortex_m3/keil/src/tx_thread_schedule.s @@ -39,7 +39,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M3/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -72,10 +72,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_m3/keil/src/tx_thread_stack_build.s b/ports/cortex_m3/keil/src/tx_thread_stack_build.s index 9dbcd8aa..1382a9ba 100644 --- a/ports/cortex_m3/keil/src/tx_thread_stack_build.s +++ b/ports/cortex_m3/keil/src/tx_thread_stack_build.s @@ -20,15 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; ; AREA ||.text||, CODE, READONLY ;/**************************************************************************/ @@ -36,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build Cortex-M3/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -68,10 +59,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -122,7 +110,7 @@ _tx_thread_stack_build STR r3, [r2, #28] ; Store initial r10 STR r3, [r2, #32] ; Store initial r11 ; -; /* Hardware stack follows. / +; /* Hardware stack follows. */ ; STR r3, [r2, #36] ; Store initial r0 STR r3, [r2, #40] ; Store initial r1 diff --git a/ports/cortex_m3/keil/src/tx_thread_system_return.s b/ports/cortex_m3/keil/src/tx_thread_system_return.s index 8443a09a..c15ef851 100644 --- a/ports/cortex_m3/keil/src/tx_thread_system_return.s +++ b/ports/cortex_m3/keil/src/tx_thread_system_return.s @@ -27,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return Cortex-M3/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -59,10 +59,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_m3/keil/src/tx_timer_interrupt.s b/ports/cortex_m3/keil/src/tx_timer_interrupt.s index 6e877312..e80da8e2 100644 --- a/ports/cortex_m3/keil/src/tx_timer_interrupt.s +++ b/ports/cortex_m3/keil/src/tx_timer_interrupt.s @@ -42,7 +42,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt Cortex-M3/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -76,10 +76,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_m33/ac5/example_build/ARMCM33_DSP_FP_TZ_config.txt b/ports/cortex_m33/ac5/example_build/ARMCM33_DSP_FP_TZ_config.txt new file mode 100644 index 00000000..04e32d1f --- /dev/null +++ b/ports/cortex_m33/ac5/example_build/ARMCM33_DSP_FP_TZ_config.txt @@ -0,0 +1,24 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] +cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] +cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included +cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] +cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode +cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] +cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] +cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] +cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset +cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set +idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write +cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write +cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write +cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included +cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +#---------------------------------------------------------------------------------------------- diff --git a/ports/cortex_m33/ac5/example_build/AzureRTOS.uvmpw b/ports/cortex_m33/ac5/example_build/AzureRTOS.uvmpw new file mode 100644 index 00000000..c50658f7 --- /dev/null +++ b/ports/cortex_m33/ac5/example_build/AzureRTOS.uvmpw @@ -0,0 +1,23 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + WorkSpace + + + .\demo_secure_zone\demo_secure_zone.uvprojx + 1 + + + + .\demo_threadx_non-secure_zone\demo_threadx_non-secure_zone.uvprojx + + + + .\ThreadX_Library.uvprojx + + + diff --git a/ports/cortex_m33/ac5/example_build/Debug.ini b/ports/cortex_m33/ac5/example_build/Debug.ini new file mode 100644 index 00000000..2a9dfba0 --- /dev/null +++ b/ports/cortex_m33/ac5/example_build/Debug.ini @@ -0,0 +1,4 @@ +LOAD "..\\demo_threadx_non-secure_zone\\Objects\\demo_threadx_non-secure_zone.axf" incremental +LOAD "..\\demo_secure_zone\\Objects\\demo_secure_zone.axf" incremental +RESET +g, \\demo_secure_zone\main_s\main \ No newline at end of file diff --git a/ports/cortex_m33/ac5/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h b/ports/cortex_m33/ac5/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h new file mode 100644 index 00000000..1eb74752 --- /dev/null +++ b/ports/cortex_m33/ac5/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'ThreadX_Library' + * Target: 'ThreadX_Library_Project' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/ports/cortex_m33/ac5/example_build/RTOS.uvmpw.uvgui b/ports/cortex_m33/ac5/example_build/RTOS.uvmpw.uvgui new file mode 100644 index 00000000..5c23c31f --- /dev/null +++ b/ports/cortex_m33/ac5/example_build/RTOS.uvmpw.uvgui @@ -0,0 +1,1777 @@ + + + + -6.1 + +
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..\..\..\..\common\src\tx_timer_performance_info_get.c + + + tx_timer_performance_system_info_get.c + 1 + ..\..\..\..\common\src\tx_timer_performance_system_info_get.c + + + tx_timer_system_activate.c + 1 + ..\..\..\..\common\src\tx_timer_system_activate.c + + + tx_timer_system_deactivate.c + 1 + ..\..\..\..\common\src\tx_timer_system_deactivate.c + + + tx_timer_thread_entry.c + 1 + ..\..\..\..\common\src\tx_timer_thread_entry.c + + + tx_trace_disable.c + 1 + ..\..\..\..\common\src\tx_trace_disable.c + + + tx_trace_enable.c + 1 + ..\..\..\..\common\src\tx_trace_enable.c + + + tx_trace_initialize.c + 1 + ..\..\..\..\common\src\tx_trace_initialize.c + + + tx_trace_interrupt_control.c + 1 + ..\..\..\..\common\src\tx_trace_interrupt_control.c + + + tx_trace_isr_enter_insert.c + 1 + ..\..\..\..\common\src\tx_trace_isr_enter_insert.c + + + tx_trace_isr_exit_insert.c + 1 + ..\..\..\..\common\src\tx_trace_isr_exit_insert.c + + + tx_trace_object_register.c + 1 + ..\..\..\..\common\src\tx_trace_object_register.c + + + tx_trace_object_unregister.c + 1 + ..\..\..\..\common\src\tx_trace_object_unregister.c + + + tx_trace_user_event_insert.c + 1 + ..\..\..\..\common\src\tx_trace_user_event_insert.c + + + txe_block_allocate.c + 1 + ..\..\..\..\common\src\txe_block_allocate.c + + + txe_block_pool_create.c + 1 + ..\..\..\..\common\src\txe_block_pool_create.c + + + txe_block_pool_delete.c + 1 + ..\..\..\..\common\src\txe_block_pool_delete.c + + + txe_block_pool_info_get.c + 1 + ..\..\..\..\common\src\txe_block_pool_info_get.c + + + txe_block_pool_prioritize.c + 1 + ..\..\..\..\common\src\txe_block_pool_prioritize.c + + + txe_block_release.c + 1 + ..\..\..\..\common\src\txe_block_release.c + + + txe_byte_allocate.c + 1 + ..\..\..\..\common\src\txe_byte_allocate.c + + + txe_byte_pool_create.c + 1 + ..\..\..\..\common\src\txe_byte_pool_create.c + + + txe_byte_pool_delete.c + 1 + ..\..\..\..\common\src\txe_byte_pool_delete.c + + + txe_byte_pool_info_get.c + 1 + ..\..\..\..\common\src\txe_byte_pool_info_get.c + + + txe_byte_pool_prioritize.c + 1 + ..\..\..\..\common\src\txe_byte_pool_prioritize.c + + + txe_byte_release.c + 1 + ..\..\..\..\common\src\txe_byte_release.c + + + txe_event_flags_create.c + 1 + ..\..\..\..\common\src\txe_event_flags_create.c + + + txe_event_flags_delete.c + 1 + ..\..\..\..\common\src\txe_event_flags_delete.c + + + txe_event_flags_get.c + 1 + ..\..\..\..\common\src\txe_event_flags_get.c + + + txe_event_flags_info_get.c + 1 + ..\..\..\..\common\src\txe_event_flags_info_get.c + + + txe_event_flags_set.c + 1 + ..\..\..\..\common\src\txe_event_flags_set.c + + + txe_event_flags_set_notify.c + 1 + ..\..\..\..\common\src\txe_event_flags_set_notify.c + + + txe_mutex_create.c + 1 + ..\..\..\..\common\src\txe_mutex_create.c + + + txe_mutex_delete.c + 1 + ..\..\..\..\common\src\txe_mutex_delete.c + + + txe_mutex_get.c + 1 + ..\..\..\..\common\src\txe_mutex_get.c + + + txe_mutex_info_get.c + 1 + ..\..\..\..\common\src\txe_mutex_info_get.c + + + txe_mutex_prioritize.c + 1 + ..\..\..\..\common\src\txe_mutex_prioritize.c + + + txe_mutex_put.c + 1 + ..\..\..\..\common\src\txe_mutex_put.c + + + txe_queue_create.c + 1 + ..\..\..\..\common\src\txe_queue_create.c + + + txe_queue_delete.c + 1 + ..\..\..\..\common\src\txe_queue_delete.c + + + txe_queue_flush.c + 1 + ..\..\..\..\common\src\txe_queue_flush.c + + + txe_queue_front_send.c + 1 + ..\..\..\..\common\src\txe_queue_front_send.c + + + txe_queue_info_get.c + 1 + ..\..\..\..\common\src\txe_queue_info_get.c + + + txe_queue_prioritize.c + 1 + ..\..\..\..\common\src\txe_queue_prioritize.c + + + txe_queue_receive.c + 1 + ..\..\..\..\common\src\txe_queue_receive.c + + + txe_queue_send.c + 1 + ..\..\..\..\common\src\txe_queue_send.c + + + txe_queue_send_notify.c + 1 + ..\..\..\..\common\src\txe_queue_send_notify.c + + + txe_semaphore_ceiling_put.c + 1 + ..\..\..\..\common\src\txe_semaphore_ceiling_put.c + + + txe_semaphore_create.c + 1 + ..\..\..\..\common\src\txe_semaphore_create.c + + + txe_semaphore_delete.c + 1 + ..\..\..\..\common\src\txe_semaphore_delete.c + + + txe_semaphore_get.c + 1 + ..\..\..\..\common\src\txe_semaphore_get.c + + + txe_semaphore_info_get.c + 1 + ..\..\..\..\common\src\txe_semaphore_info_get.c + + + txe_semaphore_prioritize.c + 1 + ..\..\..\..\common\src\txe_semaphore_prioritize.c + + + txe_semaphore_put.c + 1 + ..\..\..\..\common\src\txe_semaphore_put.c + + + txe_semaphore_put_notify.c + 1 + ..\..\..\..\common\src\txe_semaphore_put_notify.c + + + txe_thread_create.c + 1 + ..\..\..\..\common\src\txe_thread_create.c + + + txe_thread_delete.c + 1 + ..\..\..\..\common\src\txe_thread_delete.c + + + txe_thread_entry_exit_notify.c + 1 + ..\..\..\..\common\src\txe_thread_entry_exit_notify.c + + + txe_thread_info_get.c + 1 + ..\..\..\..\common\src\txe_thread_info_get.c + + + txe_thread_preemption_change.c + 1 + ..\..\..\..\common\src\txe_thread_preemption_change.c + + + txe_thread_priority_change.c + 1 + ..\..\..\..\common\src\txe_thread_priority_change.c + + + txe_thread_relinquish.c + 1 + ..\..\..\..\common\src\txe_thread_relinquish.c + + + txe_thread_reset.c + 1 + ..\..\..\..\common\src\txe_thread_reset.c + + + txe_thread_resume.c + 1 + ..\..\..\..\common\src\txe_thread_resume.c + + + txe_thread_suspend.c + 1 + ..\..\..\..\common\src\txe_thread_suspend.c + + + txe_thread_terminate.c + 1 + ..\..\..\..\common\src\txe_thread_terminate.c + + + txe_thread_time_slice_change.c + 1 + ..\..\..\..\common\src\txe_thread_time_slice_change.c + + + txe_thread_wait_abort.c + 1 + ..\..\..\..\common\src\txe_thread_wait_abort.c + + + txe_timer_activate.c + 1 + ..\..\..\..\common\src\txe_timer_activate.c + + + txe_timer_change.c + 1 + ..\..\..\..\common\src\txe_timer_change.c + + + txe_timer_create.c + 1 + ..\..\..\..\common\src\txe_timer_create.c + + + txe_timer_deactivate.c + 1 + ..\..\..\..\common\src\txe_timer_deactivate.c + + + txe_timer_delete.c + 1 + ..\..\..\..\common\src\txe_timer_delete.c + + + txe_timer_info_get.c + 1 + ..\..\..\..\common\src\txe_timer_info_get.c + + + tx_timer_interrupt.s + 2 + ..\src\tx_timer_interrupt.s + + + tx_thread_context_restore.s + 2 + ..\src\tx_thread_context_restore.s + + + tx_thread_context_save.s + 2 + ..\src\tx_thread_context_save.s + + + tx_thread_interrupt_control.s + 2 + ..\src\tx_thread_interrupt_control.s + + + tx_thread_schedule.s + 2 + ..\src\tx_thread_schedule.s + + + tx_thread_stack_build.s + 2 + ..\src\tx_thread_stack_build.s + + + tx_thread_system_return.s + 2 + ..\src\tx_thread_system_return.s + + + tx_trace_buffer_full_notify.c + 1 + ..\..\..\..\common\src\tx_trace_buffer_full_notify.c + + + tx_trace_event_filter.c + 1 + ..\..\..\..\common\src\tx_trace_event_filter.c + + + tx_trace_event_unfilter.c + 1 + ..\..\..\..\common\src\tx_trace_event_unfilter.c + + + tx_thread_interrupt_disable.s + 2 + ..\src\tx_thread_interrupt_disable.s + + + tx_thread_interrupt_restore.s + 2 + ..\src\tx_thread_interrupt_restore.s + + + txe_thread_secure_stack_allocate.c + 1 + ..\src\txe_thread_secure_stack_allocate.c + + + txe_thread_secure_stack_free.c + 1 + ..\src\txe_thread_secure_stack_free.c + + + tx_thread_secure_stack_allocate.s + 2 + ..\src\tx_thread_secure_stack_allocate.s + + + tx_thread_secure_stack_free.s + 2 + ..\src\tx_thread_secure_stack_free.s + + + tx_initialize_low_level.S + 2 + .\tx_initialize_low_level.S + + + tx_thread_stack_error_handler.c + 1 + ..\src\tx_thread_stack_error_handler.c + + + tx_thread_stack_error_notify.c + 1 + ..\src\tx_thread_stack_error_notify.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/ports/cortex_m33/ac5/example_build/demo_secure_zone/Abstract.txt b/ports/cortex_m33/ac5/example_build/demo_secure_zone/Abstract.txt new file mode 100644 index 00000000..0d1d8c52 --- /dev/null +++ b/ports/cortex_m33/ac5/example_build/demo_secure_zone/Abstract.txt @@ -0,0 +1,19 @@ +This ARM Cortex-M33 secure/non-secure example project that +shows the setup of the CMSIS-RTOS2 RTX for TrustZone for +ARMv8-M applications. + +The application uses CMSIS and can be executed on a Fixed +Virtual Platform (FVP) simulation model. The application +demonstrates three RTOS threads. + + +Secure application: + - Setup code and start non-secure application. + +Non-secure application: + - Calls a secure function from non-secure state. + - Calls a secure function that call back to a non-secure function. + +Output: +Variables used in this application can be viewed in the Debugger +Watch window. \ No newline at end of file diff --git a/ports/cortex_m33/ac5/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_AC6.sct b/ports/cortex_m33/ac5/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_AC6.sct new file mode 100644 index 00000000..3baa3455 --- /dev/null +++ b/ports/cortex_m33/ac5/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_AC6.sct @@ -0,0 +1,74 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc +; command above MUST be in first line (no comment above!) + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x00000000 +#define __ROM_SIZE 0x00200000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00020000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000400 +#define __HEAP_SIZE 0x00000C00 + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundery definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ +#define __RO_BASE __ROM_BASE +#define __RO_SIZE __ROM_SIZE + +#define __RW_BASE (__RAM_BASE ) +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) + + + +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) +; *(Veneer$$CMSE) ; uncomment for secure applications + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } +} diff --git a/ports/cortex_m33/ac5/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h b/ports/cortex_m33/ac5/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h new file mode 100644 index 00000000..a7cb0d73 --- /dev/null +++ b/ports/cortex_m33/ac5/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h @@ -0,0 +1,1260 @@ +/**************************************************************************//** + * @file partition_ARMCM33.h + * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33 + * @version V1.1.1 + * @date 12. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PARTITION_ARMCM33_H +#define PARTITION_ARMCM33_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 1 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x00200000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x003FFFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x20200000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x203FFFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x40040000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 1 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 1 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 1 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x80-0xFF +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 1 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// Interrupt 0 <0=> Secure state <1=> Non-Secure state +// Interrupt 1 <0=> Secure state <1=> Non-Secure state +// Interrupt 2 <0=> Secure state <1=> Non-Secure state +// Interrupt 3 <0=> Secure state <1=> Non-Secure state +// Interrupt 4 <0=> Secure state <1=> Non-Secure state +// Interrupt 5 <0=> Secure state <1=> Non-Secure state +// Interrupt 6 <0=> Secure state <1=> Non-Secure state +// Interrupt 7 <0=> Secure state <1=> Non-Secure state +// Interrupt 8 <0=> Secure state <1=> Non-Secure state +// Interrupt 9 <0=> Secure state <1=> Non-Secure state +// Interrupt 10 <0=> Secure state <1=> Non-Secure state +// Interrupt 11 <0=> Secure state <1=> Non-Secure state +// Interrupt 12 <0=> Secure state <1=> Non-Secure state +// Interrupt 13 <0=> Secure state <1=> Non-Secure state +// Interrupt 14 <0=> Secure state <1=> Non-Secure state +// Interrupt 15 <0=> Secure state <1=> Non-Secure state +// Interrupt 16 <0=> Secure state <1=> Non-Secure state +// Interrupt 17 <0=> Secure state <1=> Non-Secure state +// Interrupt 18 <0=> Secure state <1=> Non-Secure state +// Interrupt 19 <0=> Secure state <1=> Non-Secure state +// Interrupt 20 <0=> Secure state <1=> Non-Secure state +// Interrupt 21 <0=> Secure state <1=> Non-Secure state +// Interrupt 22 <0=> Secure state <1=> Non-Secure state +// Interrupt 23 <0=> Secure state <1=> Non-Secure state +// Interrupt 24 <0=> Secure state <1=> Non-Secure state +// Interrupt 25 <0=> Secure state <1=> Non-Secure state +// Interrupt 26 <0=> Secure state <1=> Non-Secure state +// Interrupt 27 <0=> Secure state <1=> Non-Secure state +// Interrupt 28 <0=> Secure state <1=> Non-Secure state +// Interrupt 29 <0=> Secure state <1=> Non-Secure state +// Interrupt 30 <0=> Secure state <1=> Non-Secure state +// Interrupt 31 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// Interrupt 32 <0=> Secure state <1=> Non-Secure state +// Interrupt 33 <0=> Secure state <1=> Non-Secure state +// Interrupt 34 <0=> Secure state <1=> Non-Secure state +// Interrupt 35 <0=> Secure state <1=> Non-Secure state +// Interrupt 36 <0=> Secure state <1=> Non-Secure state +// Interrupt 37 <0=> Secure state <1=> Non-Secure state +// Interrupt 38 <0=> Secure state <1=> Non-Secure state +// Interrupt 39 <0=> Secure state <1=> Non-Secure state +// Interrupt 40 <0=> Secure state <1=> Non-Secure state +// Interrupt 41 <0=> Secure state <1=> Non-Secure state +// Interrupt 42 <0=> Secure state <1=> Non-Secure state +// Interrupt 43 <0=> Secure state <1=> Non-Secure state +// Interrupt 44 <0=> Secure state <1=> Non-Secure state +// Interrupt 45 <0=> Secure state <1=> Non-Secure state +// Interrupt 46 <0=> Secure state <1=> Non-Secure state +// Interrupt 47 <0=> Secure state <1=> Non-Secure state +// Interrupt 48 <0=> Secure state <1=> Non-Secure state +// Interrupt 49 <0=> Secure state <1=> Non-Secure state +// Interrupt 50 <0=> Secure state <1=> Non-Secure state +// Interrupt 51 <0=> Secure state <1=> Non-Secure state +// Interrupt 52 <0=> Secure state <1=> Non-Secure state +// Interrupt 53 <0=> Secure state <1=> Non-Secure state +// Interrupt 54 <0=> Secure state <1=> Non-Secure state +// Interrupt 55 <0=> Secure state <1=> Non-Secure state +// Interrupt 56 <0=> Secure state <1=> Non-Secure state +// Interrupt 57 <0=> Secure state <1=> Non-Secure state +// Interrupt 58 <0=> Secure state <1=> Non-Secure state +// Interrupt 59 <0=> Secure state <1=> Non-Secure state +// Interrupt 60 <0=> Secure state <1=> Non-Secure state +// Interrupt 61 <0=> Secure state <1=> Non-Secure state +// Interrupt 62 <0=> Secure state <1=> Non-Secure state +// Interrupt 63 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 0 + +/* +// Interrupts 64..95 +// Interrupt 64 <0=> Secure state <1=> Non-Secure state +// Interrupt 65 <0=> Secure state <1=> Non-Secure state +// Interrupt 66 <0=> Secure state <1=> Non-Secure state +// Interrupt 67 <0=> Secure state <1=> Non-Secure state +// Interrupt 68 <0=> Secure state <1=> Non-Secure state +// Interrupt 69 <0=> Secure state <1=> Non-Secure state +// Interrupt 70 <0=> Secure state <1=> Non-Secure state +// Interrupt 71 <0=> Secure state <1=> Non-Secure state +// Interrupt 72 <0=> Secure state <1=> Non-Secure state +// Interrupt 73 <0=> Secure state <1=> Non-Secure state +// Interrupt 74 <0=> Secure state <1=> Non-Secure state +// Interrupt 75 <0=> Secure state <1=> Non-Secure state +// Interrupt 76 <0=> Secure state <1=> Non-Secure state +// Interrupt 77 <0=> Secure state <1=> Non-Secure state +// Interrupt 78 <0=> Secure state <1=> Non-Secure state +// Interrupt 79 <0=> Secure state <1=> Non-Secure state +// Interrupt 80 <0=> Secure state <1=> Non-Secure state +// Interrupt 81 <0=> Secure state <1=> Non-Secure state +// Interrupt 82 <0=> Secure state <1=> Non-Secure state +// Interrupt 83 <0=> Secure state <1=> Non-Secure state +// Interrupt 84 <0=> Secure state <1=> Non-Secure state +// Interrupt 85 <0=> Secure state <1=> Non-Secure state +// Interrupt 86 <0=> Secure state <1=> Non-Secure state +// Interrupt 87 <0=> Secure state <1=> Non-Secure state +// Interrupt 88 <0=> Secure state <1=> Non-Secure state +// Interrupt 89 <0=> Secure state <1=> Non-Secure state +// Interrupt 90 <0=> Secure state <1=> Non-Secure state +// Interrupt 91 <0=> Secure state <1=> Non-Secure state +// Interrupt 92 <0=> Secure state <1=> Non-Secure state +// Interrupt 93 <0=> Secure state <1=> Non-Secure state +// Interrupt 94 <0=> Secure state <1=> Non-Secure state +// Interrupt 95 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 0 + +/* +// Interrupts 96..127 +// Interrupt 96 <0=> Secure state <1=> Non-Secure state +// Interrupt 97 <0=> Secure state <1=> Non-Secure state +// Interrupt 98 <0=> Secure state <1=> Non-Secure state +// Interrupt 99 <0=> Secure state <1=> Non-Secure state +// Interrupt 100 <0=> Secure state <1=> Non-Secure state +// Interrupt 101 <0=> Secure state <1=> Non-Secure state +// Interrupt 102 <0=> Secure state <1=> Non-Secure state +// Interrupt 103 <0=> Secure state <1=> Non-Secure state +// Interrupt 104 <0=> Secure state <1=> Non-Secure state +// Interrupt 105 <0=> Secure state <1=> Non-Secure state +// Interrupt 106 <0=> Secure state <1=> Non-Secure state +// Interrupt 107 <0=> Secure state <1=> Non-Secure state +// Interrupt 108 <0=> Secure state <1=> Non-Secure state +// Interrupt 109 <0=> Secure state <1=> Non-Secure state +// Interrupt 110 <0=> Secure state <1=> Non-Secure state +// Interrupt 111 <0=> Secure state <1=> Non-Secure state +// Interrupt 112 <0=> Secure state <1=> Non-Secure state +// Interrupt 113 <0=> Secure state <1=> Non-Secure state +// Interrupt 114 <0=> Secure state <1=> Non-Secure state +// Interrupt 115 <0=> Secure state <1=> Non-Secure state +// Interrupt 116 <0=> Secure state <1=> Non-Secure state +// Interrupt 117 <0=> Secure state <1=> Non-Secure state +// Interrupt 118 <0=> Secure state <1=> Non-Secure state +// Interrupt 119 <0=> Secure state <1=> Non-Secure state +// Interrupt 120 <0=> Secure state <1=> Non-Secure state +// Interrupt 121 <0=> Secure state <1=> Non-Secure state +// Interrupt 122 <0=> Secure state <1=> Non-Secure state +// Interrupt 123 <0=> Secure state <1=> Non-Secure state +// Interrupt 124 <0=> Secure state <1=> Non-Secure state +// Interrupt 125 <0=> Secure state <1=> Non-Secure state +// Interrupt 126 <0=> Secure state <1=> Non-Secure state +// Interrupt 127 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 128..159) +*/ +#define NVIC_INIT_ITNS4 0 + +/* +// Interrupts 128..159 +// Interrupt 128 <0=> Secure state <1=> Non-Secure state +// Interrupt 129 <0=> Secure state <1=> Non-Secure state +// Interrupt 130 <0=> Secure state <1=> Non-Secure state +// Interrupt 131 <0=> Secure state <1=> Non-Secure state +// Interrupt 132 <0=> Secure state <1=> Non-Secure state +// Interrupt 133 <0=> Secure state <1=> Non-Secure state +// Interrupt 134 <0=> Secure state <1=> Non-Secure state +// Interrupt 135 <0=> Secure state <1=> Non-Secure state +// Interrupt 136 <0=> Secure state <1=> Non-Secure state +// Interrupt 137 <0=> Secure state <1=> Non-Secure state +// Interrupt 138 <0=> Secure state <1=> Non-Secure state +// Interrupt 139 <0=> Secure state <1=> Non-Secure state +// Interrupt 140 <0=> Secure state <1=> Non-Secure state +// Interrupt 141 <0=> Secure state <1=> Non-Secure state +// Interrupt 142 <0=> Secure state <1=> Non-Secure state +// Interrupt 143 <0=> Secure state <1=> Non-Secure state +// Interrupt 144 <0=> Secure state <1=> Non-Secure state +// Interrupt 145 <0=> Secure state <1=> Non-Secure state +// Interrupt 146 <0=> Secure state <1=> Non-Secure state +// Interrupt 147 <0=> Secure state <1=> Non-Secure state +// Interrupt 148 <0=> Secure state <1=> Non-Secure state +// Interrupt 149 <0=> Secure state <1=> Non-Secure state +// Interrupt 150 <0=> Secure state <1=> Non-Secure state +// Interrupt 151 <0=> Secure state <1=> Non-Secure state +// Interrupt 152 <0=> Secure state <1=> Non-Secure state +// Interrupt 153 <0=> Secure state <1=> Non-Secure state +// Interrupt 154 <0=> Secure state <1=> Non-Secure state +// Interrupt 155 <0=> Secure state <1=> Non-Secure state +// Interrupt 156 <0=> Secure state <1=> Non-Secure state +// Interrupt 157 <0=> Secure state <1=> Non-Secure state +// Interrupt 158 <0=> Secure state <1=> Non-Secure state +// Interrupt 159 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 5 (Interrupts 160..191) +*/ +#define NVIC_INIT_ITNS5 0 + +/* +// Interrupts 160..191 +// Interrupt 160 <0=> Secure state <1=> Non-Secure state +// Interrupt 161 <0=> Secure state <1=> Non-Secure state +// Interrupt 162 <0=> Secure state <1=> Non-Secure state +// Interrupt 163 <0=> Secure state <1=> Non-Secure state +// Interrupt 164 <0=> Secure state <1=> Non-Secure state +// Interrupt 165 <0=> Secure state <1=> Non-Secure state +// Interrupt 166 <0=> Secure state <1=> Non-Secure state +// Interrupt 167 <0=> Secure state <1=> Non-Secure state +// Interrupt 168 <0=> Secure state <1=> Non-Secure state +// Interrupt 169 <0=> Secure state <1=> Non-Secure state +// Interrupt 170 <0=> Secure state <1=> Non-Secure state +// Interrupt 171 <0=> Secure state <1=> Non-Secure state +// Interrupt 172 <0=> Secure state <1=> Non-Secure state +// Interrupt 173 <0=> Secure state <1=> Non-Secure state +// Interrupt 174 <0=> Secure state <1=> Non-Secure state +// Interrupt 175 <0=> Secure state <1=> Non-Secure state +// Interrupt 176 <0=> Secure state <1=> Non-Secure state +// Interrupt 177 <0=> Secure state <1=> Non-Secure state +// Interrupt 178 <0=> Secure state <1=> Non-Secure state +// Interrupt 179 <0=> Secure state <1=> Non-Secure state +// Interrupt 180 <0=> Secure state <1=> Non-Secure state +// Interrupt 181 <0=> Secure state <1=> Non-Secure state +// Interrupt 182 <0=> Secure state <1=> Non-Secure state +// Interrupt 183 <0=> Secure state <1=> Non-Secure state +// Interrupt 184 <0=> Secure state <1=> Non-Secure state +// Interrupt 185 <0=> Secure state <1=> Non-Secure state +// Interrupt 186 <0=> Secure state <1=> Non-Secure state +// Interrupt 187 <0=> Secure state <1=> Non-Secure state +// Interrupt 188 <0=> Secure state <1=> Non-Secure state +// Interrupt 189 <0=> Secure state <1=> Non-Secure state +// Interrupt 190 <0=> Secure state <1=> Non-Secure state +// Interrupt 191 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS5_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 6 (Interrupts 192..223) +*/ +#define NVIC_INIT_ITNS6 0 + +/* +// Interrupts 192..223 +// Interrupt 192 <0=> Secure state <1=> Non-Secure state +// Interrupt 193 <0=> Secure state <1=> Non-Secure state +// Interrupt 194 <0=> Secure state <1=> Non-Secure state +// Interrupt 195 <0=> Secure state <1=> Non-Secure state +// Interrupt 196 <0=> Secure state <1=> Non-Secure state +// Interrupt 197 <0=> Secure state <1=> Non-Secure state +// Interrupt 198 <0=> Secure state <1=> Non-Secure state +// Interrupt 199 <0=> Secure state <1=> Non-Secure state +// Interrupt 200 <0=> Secure state <1=> Non-Secure state +// Interrupt 201 <0=> Secure state <1=> Non-Secure state +// Interrupt 202 <0=> Secure state <1=> Non-Secure state +// Interrupt 203 <0=> Secure state <1=> Non-Secure state +// Interrupt 204 <0=> Secure state <1=> Non-Secure state +// Interrupt 205 <0=> Secure state <1=> Non-Secure state +// Interrupt 206 <0=> Secure state <1=> Non-Secure state +// Interrupt 207 <0=> Secure state <1=> Non-Secure state +// Interrupt 208 <0=> Secure state <1=> Non-Secure state +// Interrupt 209 <0=> Secure state <1=> Non-Secure state +// Interrupt 210 <0=> Secure state <1=> Non-Secure state +// Interrupt 211 <0=> Secure state <1=> Non-Secure state +// Interrupt 212 <0=> Secure state <1=> Non-Secure state +// Interrupt 213 <0=> Secure state <1=> Non-Secure state +// Interrupt 214 <0=> Secure state <1=> Non-Secure state +// Interrupt 215 <0=> Secure state <1=> Non-Secure state +// Interrupt 216 <0=> Secure state <1=> Non-Secure state +// Interrupt 217 <0=> Secure state <1=> Non-Secure state +// Interrupt 218 <0=> Secure state <1=> Non-Secure state +// Interrupt 219 <0=> Secure state <1=> Non-Secure state +// Interrupt 220 <0=> Secure state <1=> Non-Secure state +// Interrupt 221 <0=> Secure state <1=> Non-Secure state +// Interrupt 222 <0=> Secure state <1=> Non-Secure state +// Interrupt 223 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS6_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 7 (Interrupts 224..255) +*/ +#define NVIC_INIT_ITNS7 0 + +/* +// Interrupts 224..255 +// Interrupt 224 <0=> Secure state <1=> Non-Secure state +// Interrupt 225 <0=> Secure state <1=> Non-Secure state +// Interrupt 226 <0=> Secure state <1=> Non-Secure state +// Interrupt 227 <0=> Secure state <1=> Non-Secure state +// Interrupt 228 <0=> Secure state <1=> Non-Secure state +// Interrupt 229 <0=> Secure state <1=> Non-Secure state +// Interrupt 230 <0=> Secure state <1=> Non-Secure state +// Interrupt 231 <0=> Secure state <1=> Non-Secure state +// Interrupt 232 <0=> Secure state <1=> Non-Secure state +// Interrupt 233 <0=> Secure state <1=> Non-Secure state +// Interrupt 234 <0=> Secure state <1=> Non-Secure state +// Interrupt 235 <0=> Secure state <1=> Non-Secure state +// Interrupt 236 <0=> Secure state <1=> Non-Secure state +// Interrupt 237 <0=> Secure state <1=> Non-Secure state +// Interrupt 238 <0=> Secure state <1=> Non-Secure state +// Interrupt 239 <0=> Secure state <1=> Non-Secure state +// Interrupt 240 <0=> Secure state <1=> Non-Secure state +// Interrupt 241 <0=> Secure state <1=> Non-Secure state +// Interrupt 242 <0=> Secure state <1=> Non-Secure state +// Interrupt 243 <0=> Secure state <1=> Non-Secure state +// Interrupt 244 <0=> Secure state <1=> Non-Secure state +// Interrupt 245 <0=> Secure state <1=> Non-Secure state +// Interrupt 246 <0=> Secure state <1=> Non-Secure state +// Interrupt 247 <0=> Secure state <1=> Non-Secure state +// Interrupt 248 <0=> Secure state <1=> Non-Secure state +// Interrupt 249 <0=> Secure state <1=> Non-Secure state +// Interrupt 250 <0=> Secure state <1=> Non-Secure state +// Interrupt 251 <0=> Secure state <1=> Non-Secure state +// Interrupt 252 <0=> Secure state <1=> Non-Secure state +// Interrupt 253 <0=> Secure state <1=> Non-Secure state +// Interrupt 254 <0=> Secure state <1=> Non-Secure state +// Interrupt 255 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS7_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 8 (Interrupts 256..287) +*/ +#define NVIC_INIT_ITNS8 0 + +/* +// Interrupts 256..287 +// Interrupt 256 <0=> Secure state <1=> Non-Secure state +// Interrupt 257 <0=> Secure state <1=> Non-Secure state +// Interrupt 258 <0=> Secure state <1=> Non-Secure state +// Interrupt 259 <0=> Secure state <1=> Non-Secure state +// Interrupt 260 <0=> Secure state <1=> Non-Secure state +// Interrupt 261 <0=> Secure state <1=> Non-Secure state +// Interrupt 262 <0=> Secure state <1=> Non-Secure state +// Interrupt 263 <0=> Secure state <1=> Non-Secure state +// Interrupt 264 <0=> Secure state <1=> Non-Secure state +// Interrupt 265 <0=> Secure state <1=> Non-Secure state +// Interrupt 266 <0=> Secure state <1=> Non-Secure state +// Interrupt 267 <0=> Secure state <1=> Non-Secure state +// Interrupt 268 <0=> Secure state <1=> Non-Secure state +// Interrupt 269 <0=> Secure state <1=> Non-Secure state +// Interrupt 270 <0=> Secure state <1=> Non-Secure state +// Interrupt 271 <0=> Secure state <1=> Non-Secure state +// Interrupt 272 <0=> Secure state <1=> Non-Secure state +// Interrupt 273 <0=> Secure state <1=> Non-Secure state +// Interrupt 274 <0=> Secure state <1=> Non-Secure state +// Interrupt 275 <0=> Secure state <1=> Non-Secure state +// Interrupt 276 <0=> Secure state <1=> Non-Secure state +// Interrupt 277 <0=> Secure state <1=> Non-Secure state +// Interrupt 278 <0=> Secure state <1=> Non-Secure state +// Interrupt 279 <0=> Secure state <1=> Non-Secure state +// Interrupt 280 <0=> Secure state <1=> Non-Secure state +// Interrupt 281 <0=> Secure state <1=> Non-Secure state +// Interrupt 282 <0=> Secure state <1=> Non-Secure state +// Interrupt 283 <0=> Secure state <1=> Non-Secure state +// Interrupt 284 <0=> Secure state <1=> Non-Secure state +// Interrupt 285 <0=> Secure state <1=> Non-Secure state +// Interrupt 286 <0=> Secure state <1=> Non-Secure state +// Interrupt 287 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS8_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 9 (Interrupts 288..319) +*/ +#define NVIC_INIT_ITNS9 0 + +/* +// Interrupts 288..319 +// Interrupt 288 <0=> Secure state <1=> Non-Secure state +// Interrupt 289 <0=> Secure state <1=> Non-Secure state +// Interrupt 290 <0=> Secure state <1=> Non-Secure state +// Interrupt 291 <0=> Secure state <1=> Non-Secure state +// Interrupt 292 <0=> Secure state <1=> Non-Secure state +// Interrupt 293 <0=> Secure state <1=> Non-Secure state +// Interrupt 294 <0=> Secure state <1=> Non-Secure state +// Interrupt 295 <0=> Secure state <1=> Non-Secure state +// Interrupt 296 <0=> Secure state <1=> Non-Secure state +// Interrupt 297 <0=> Secure state <1=> Non-Secure state +// Interrupt 298 <0=> Secure state <1=> Non-Secure state +// Interrupt 299 <0=> Secure state <1=> Non-Secure state +// Interrupt 300 <0=> Secure state <1=> Non-Secure state +// Interrupt 301 <0=> Secure state <1=> Non-Secure state +// Interrupt 302 <0=> Secure state <1=> Non-Secure state +// Interrupt 303 <0=> Secure state <1=> Non-Secure state +// Interrupt 304 <0=> Secure state <1=> Non-Secure state +// Interrupt 305 <0=> Secure state <1=> Non-Secure state +// Interrupt 306 <0=> Secure state <1=> Non-Secure state +// Interrupt 307 <0=> Secure state <1=> Non-Secure state +// Interrupt 308 <0=> Secure state <1=> Non-Secure state +// Interrupt 309 <0=> Secure state <1=> Non-Secure state +// Interrupt 310 <0=> Secure state <1=> Non-Secure state +// Interrupt 311 <0=> Secure state <1=> Non-Secure state +// Interrupt 312 <0=> Secure state <1=> Non-Secure state +// Interrupt 313 <0=> Secure state <1=> Non-Secure state +// Interrupt 314 <0=> Secure state <1=> Non-Secure state +// Interrupt 315 <0=> Secure state <1=> Non-Secure state +// Interrupt 316 <0=> Secure state <1=> Non-Secure state +// Interrupt 317 <0=> Secure state <1=> Non-Secure state +// Interrupt 318 <0=> Secure state <1=> Non-Secure state +// Interrupt 319 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS9_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 10 (Interrupts 320..351) +*/ +#define NVIC_INIT_ITNS10 0 + +/* +// Interrupts 320..351 +// Interrupt 320 <0=> Secure state <1=> Non-Secure state +// Interrupt 321 <0=> Secure state <1=> Non-Secure state +// Interrupt 322 <0=> Secure state <1=> Non-Secure state +// Interrupt 323 <0=> Secure state <1=> Non-Secure state +// Interrupt 324 <0=> Secure state <1=> Non-Secure state +// Interrupt 325 <0=> Secure state <1=> Non-Secure state +// Interrupt 326 <0=> Secure state <1=> Non-Secure state +// Interrupt 327 <0=> Secure state <1=> Non-Secure state +// Interrupt 328 <0=> Secure state <1=> Non-Secure state +// Interrupt 329 <0=> Secure state <1=> Non-Secure state +// Interrupt 330 <0=> Secure state <1=> Non-Secure state +// Interrupt 331 <0=> Secure state <1=> Non-Secure state +// Interrupt 332 <0=> Secure state <1=> Non-Secure state +// Interrupt 333 <0=> Secure state <1=> Non-Secure state +// Interrupt 334 <0=> Secure state <1=> Non-Secure state +// Interrupt 335 <0=> Secure state <1=> Non-Secure state +// Interrupt 336 <0=> Secure state <1=> Non-Secure state +// Interrupt 337 <0=> Secure state <1=> Non-Secure state +// Interrupt 338 <0=> Secure state <1=> Non-Secure state +// Interrupt 339 <0=> Secure state <1=> Non-Secure state +// Interrupt 340 <0=> Secure state <1=> Non-Secure state +// Interrupt 341 <0=> Secure state <1=> Non-Secure state +// Interrupt 342 <0=> Secure state <1=> Non-Secure state +// Interrupt 343 <0=> Secure state <1=> Non-Secure state +// Interrupt 344 <0=> Secure state <1=> Non-Secure state +// Interrupt 345 <0=> Secure state <1=> Non-Secure state +// Interrupt 346 <0=> Secure state <1=> Non-Secure state +// Interrupt 347 <0=> Secure state <1=> Non-Secure state +// Interrupt 348 <0=> Secure state <1=> Non-Secure state +// Interrupt 349 <0=> Secure state <1=> Non-Secure state +// Interrupt 350 <0=> Secure state <1=> Non-Secure state +// Interrupt 351 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS10_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 11 (Interrupts 352..383) +*/ +#define NVIC_INIT_ITNS11 0 + +/* +// Interrupts 352..383 +// Interrupt 352 <0=> Secure state <1=> Non-Secure state +// Interrupt 353 <0=> Secure state <1=> Non-Secure state +// Interrupt 354 <0=> Secure state <1=> Non-Secure state +// Interrupt 355 <0=> Secure state <1=> Non-Secure state +// Interrupt 356 <0=> Secure state <1=> Non-Secure state +// Interrupt 357 <0=> Secure state <1=> Non-Secure state +// Interrupt 358 <0=> Secure state <1=> Non-Secure state +// Interrupt 359 <0=> Secure state <1=> Non-Secure state +// Interrupt 360 <0=> Secure state <1=> Non-Secure state +// Interrupt 361 <0=> Secure state <1=> Non-Secure state +// Interrupt 362 <0=> Secure state <1=> Non-Secure state +// Interrupt 363 <0=> Secure state <1=> Non-Secure state +// Interrupt 364 <0=> Secure state <1=> Non-Secure state +// Interrupt 365 <0=> Secure state <1=> Non-Secure state +// Interrupt 366 <0=> Secure state <1=> Non-Secure state +// Interrupt 367 <0=> Secure state <1=> Non-Secure state +// Interrupt 368 <0=> Secure state <1=> Non-Secure state +// Interrupt 369 <0=> Secure state <1=> Non-Secure state +// Interrupt 370 <0=> Secure state <1=> Non-Secure state +// Interrupt 371 <0=> Secure state <1=> Non-Secure state +// Interrupt 372 <0=> Secure state <1=> Non-Secure state +// Interrupt 373 <0=> Secure state <1=> Non-Secure state +// Interrupt 374 <0=> Secure state <1=> Non-Secure state +// Interrupt 375 <0=> Secure state <1=> Non-Secure state +// Interrupt 376 <0=> Secure state <1=> Non-Secure state +// Interrupt 377 <0=> Secure state <1=> Non-Secure state +// Interrupt 378 <0=> Secure state <1=> Non-Secure state +// Interrupt 379 <0=> Secure state <1=> Non-Secure state +// Interrupt 380 <0=> Secure state <1=> Non-Secure state +// Interrupt 381 <0=> Secure state <1=> Non-Secure state +// Interrupt 382 <0=> Secure state <1=> Non-Secure state +// Interrupt 383 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS11_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 12 (Interrupts 384..415) +*/ +#define NVIC_INIT_ITNS12 0 + +/* +// Interrupts 384..415 +// Interrupt 384 <0=> Secure state <1=> Non-Secure state +// Interrupt 385 <0=> Secure state <1=> Non-Secure state +// Interrupt 386 <0=> Secure state <1=> Non-Secure state +// Interrupt 387 <0=> Secure state <1=> Non-Secure state +// Interrupt 388 <0=> Secure state <1=> Non-Secure state +// Interrupt 389 <0=> Secure state <1=> Non-Secure state +// Interrupt 390 <0=> Secure state <1=> Non-Secure state +// Interrupt 391 <0=> Secure state <1=> Non-Secure state +// Interrupt 392 <0=> Secure state <1=> Non-Secure state +// Interrupt 393 <0=> Secure state <1=> Non-Secure state +// Interrupt 394 <0=> Secure state <1=> Non-Secure state +// Interrupt 395 <0=> Secure state <1=> Non-Secure state +// Interrupt 396 <0=> Secure state <1=> Non-Secure state +// Interrupt 397 <0=> Secure state <1=> Non-Secure state +// Interrupt 398 <0=> Secure state <1=> Non-Secure state +// Interrupt 399 <0=> Secure state <1=> Non-Secure state +// Interrupt 400 <0=> Secure state <1=> Non-Secure state +// Interrupt 401 <0=> Secure state <1=> Non-Secure state +// Interrupt 402 <0=> Secure state <1=> Non-Secure state +// Interrupt 403 <0=> Secure state <1=> Non-Secure state +// Interrupt 404 <0=> Secure state <1=> Non-Secure state +// Interrupt 405 <0=> Secure state <1=> Non-Secure state +// Interrupt 406 <0=> Secure state <1=> Non-Secure state +// Interrupt 407 <0=> Secure state <1=> Non-Secure state +// Interrupt 408 <0=> Secure state <1=> Non-Secure state +// Interrupt 409 <0=> Secure state <1=> Non-Secure state +// Interrupt 410 <0=> Secure state <1=> Non-Secure state +// Interrupt 411 <0=> Secure state <1=> Non-Secure state +// Interrupt 412 <0=> Secure state <1=> Non-Secure state +// Interrupt 413 <0=> Secure state <1=> Non-Secure state +// Interrupt 414 <0=> Secure state <1=> Non-Secure state +// Interrupt 415 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS12_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 13 (Interrupts 416..447) +*/ +#define NVIC_INIT_ITNS13 0 + +/* +// Interrupts 416..447 +// Interrupt 416 <0=> Secure state <1=> Non-Secure state +// Interrupt 417 <0=> Secure state <1=> Non-Secure state +// Interrupt 418 <0=> Secure state <1=> Non-Secure state +// Interrupt 419 <0=> Secure state <1=> Non-Secure state +// Interrupt 420 <0=> Secure state <1=> Non-Secure state +// Interrupt 421 <0=> Secure state <1=> Non-Secure state +// Interrupt 422 <0=> Secure state <1=> Non-Secure state +// Interrupt 423 <0=> Secure state <1=> Non-Secure state +// Interrupt 424 <0=> Secure state <1=> Non-Secure state +// Interrupt 425 <0=> Secure state <1=> Non-Secure state +// Interrupt 426 <0=> Secure state <1=> Non-Secure state +// Interrupt 427 <0=> Secure state <1=> Non-Secure state +// Interrupt 428 <0=> Secure state <1=> Non-Secure state +// Interrupt 429 <0=> Secure state <1=> Non-Secure state +// Interrupt 430 <0=> Secure state <1=> Non-Secure state +// Interrupt 431 <0=> Secure state <1=> Non-Secure state +// Interrupt 432 <0=> Secure state <1=> Non-Secure state +// Interrupt 433 <0=> Secure state <1=> Non-Secure state +// Interrupt 434 <0=> Secure state <1=> Non-Secure state +// Interrupt 435 <0=> Secure state <1=> Non-Secure state +// Interrupt 436 <0=> Secure state <1=> Non-Secure state +// Interrupt 437 <0=> Secure state <1=> Non-Secure state +// Interrupt 438 <0=> Secure state <1=> Non-Secure state +// Interrupt 439 <0=> Secure state <1=> Non-Secure state +// Interrupt 440 <0=> Secure state <1=> Non-Secure state +// Interrupt 441 <0=> Secure state <1=> Non-Secure state +// Interrupt 442 <0=> Secure state <1=> Non-Secure state +// Interrupt 443 <0=> Secure state <1=> Non-Secure state +// Interrupt 444 <0=> Secure state <1=> Non-Secure state +// Interrupt 445 <0=> Secure state <1=> Non-Secure state +// Interrupt 446 <0=> Secure state <1=> Non-Secure state +// Interrupt 447 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS13_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 14 (Interrupts 448..479) +*/ +#define NVIC_INIT_ITNS14 0 + +/* +// Interrupts 448..479 +// Interrupt 448 <0=> Secure state <1=> Non-Secure state +// Interrupt 449 <0=> Secure state <1=> Non-Secure state +// Interrupt 450 <0=> Secure state <1=> Non-Secure state +// Interrupt 451 <0=> Secure state <1=> Non-Secure state +// Interrupt 452 <0=> Secure state <1=> Non-Secure state +// Interrupt 453 <0=> Secure state <1=> Non-Secure state +// Interrupt 454 <0=> Secure state <1=> Non-Secure state +// Interrupt 455 <0=> Secure state <1=> Non-Secure state +// Interrupt 456 <0=> Secure state <1=> Non-Secure state +// Interrupt 457 <0=> Secure state <1=> Non-Secure state +// Interrupt 458 <0=> Secure state <1=> Non-Secure state +// Interrupt 459 <0=> Secure state <1=> Non-Secure state +// Interrupt 460 <0=> Secure state <1=> Non-Secure state +// Interrupt 461 <0=> Secure state <1=> Non-Secure state +// Interrupt 462 <0=> Secure state <1=> Non-Secure state +// Interrupt 463 <0=> Secure state <1=> Non-Secure state +// Interrupt 464 <0=> Secure state <1=> Non-Secure state +// Interrupt 465 <0=> Secure state <1=> Non-Secure state +// Interrupt 466 <0=> Secure state <1=> Non-Secure state +// Interrupt 467 <0=> Secure state <1=> Non-Secure state +// Interrupt 468 <0=> Secure state <1=> Non-Secure state +// Interrupt 469 <0=> Secure state <1=> Non-Secure state +// Interrupt 470 <0=> Secure state <1=> Non-Secure state +// Interrupt 471 <0=> Secure state <1=> Non-Secure state +// Interrupt 472 <0=> Secure state <1=> Non-Secure state +// Interrupt 473 <0=> Secure state <1=> Non-Secure state +// Interrupt 474 <0=> Secure state <1=> Non-Secure state +// Interrupt 475 <0=> Secure state <1=> Non-Secure state +// Interrupt 476 <0=> Secure state <1=> Non-Secure state +// Interrupt 477 <0=> Secure state <1=> Non-Secure state +// Interrupt 478 <0=> Secure state <1=> Non-Secure state +// Interrupt 479 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS14_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 15 (Interrupts 480..511) +*/ +#define NVIC_INIT_ITNS15 0 + +/* +// Interrupts 480..511 +// Interrupt 480 <0=> Secure state <1=> Non-Secure state +// Interrupt 481 <0=> Secure state <1=> Non-Secure state +// Interrupt 482 <0=> Secure state <1=> Non-Secure state +// Interrupt 483 <0=> Secure state <1=> Non-Secure state +// Interrupt 484 <0=> Secure state <1=> Non-Secure state +// Interrupt 485 <0=> Secure state <1=> Non-Secure state +// Interrupt 486 <0=> Secure state <1=> Non-Secure state +// Interrupt 487 <0=> Secure state <1=> Non-Secure state +// Interrupt 488 <0=> Secure state <1=> Non-Secure state +// Interrupt 489 <0=> Secure state <1=> Non-Secure state +// Interrupt 490 <0=> Secure state <1=> Non-Secure state +// Interrupt 491 <0=> Secure state <1=> Non-Secure state +// Interrupt 492 <0=> Secure state <1=> Non-Secure state +// Interrupt 493 <0=> Secure state <1=> Non-Secure state +// Interrupt 494 <0=> Secure state <1=> Non-Secure state +// Interrupt 495 <0=> Secure state <1=> Non-Secure state +// Interrupt 496 <0=> Secure state <1=> Non-Secure state +// Interrupt 497 <0=> Secure state <1=> Non-Secure state +// Interrupt 498 <0=> Secure state <1=> Non-Secure state +// Interrupt 499 <0=> Secure state <1=> Non-Secure state +// Interrupt 500 <0=> Secure state <1=> Non-Secure state +// Interrupt 501 <0=> Secure state <1=> Non-Secure state +// Interrupt 502 <0=> Secure state <1=> Non-Secure state +// Interrupt 503 <0=> Secure state <1=> Non-Secure state +// Interrupt 504 <0=> Secure state <1=> Non-Secure state +// Interrupt 505 <0=> Secure state <1=> Non-Secure state +// Interrupt 506 <0=> Secure state <1=> Non-Secure state +// Interrupt 507 <0=> Secure state <1=> Non-Secure state +// Interrupt 508 <0=> Secure state <1=> Non-Secure state +// Interrupt 509 <0=> Secure state <1=> Non-Secure state +// Interrupt 510 <0=> Secure state <1=> Non-Secure state +// Interrupt 511 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS15_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + + + +/* + max 128 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + + #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) + NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; + #endif + + #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) + NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; + #endif + + #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) + NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; + #endif + + #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) + NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; + #endif + + #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) + NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; + #endif + + #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) + NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; + #endif + + #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) + NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; + #endif + + #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) + NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; + #endif + + #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) + NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; + #endif + + #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) + NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; + #endif + + #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) + NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; + #endif + + /* repeat this for all possible ITNS elements */ + +} + +#endif /* PARTITION_ARMCM33_H */ diff --git a/ports/cortex_m33/ac5/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c b/ports/cortex_m33/ac5/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c new file mode 100644 index 00000000..50dbd45f --- /dev/null +++ b/ports/cortex_m33/ac5/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c @@ -0,0 +1,137 @@ +/****************************************************************************** + * @file startup_ARMCM33.c + * @brief CMSIS Core Device Startup File for Cortex-M33 Device + * @version V2.0.0 + * @date 20. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM33) + #include "ARMCM33.h" +#elif defined (ARMCM33_TZ) + #include "ARMCM33_TZ.h" +#elif defined (ARMCM33_DSP_FP) + #include "ARMCM33_DSP_FP.h" +#elif defined (ARMCM33_DSP_FP_TZ) + #include "ARMCM33_DSP_FP_TZ.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler Function Prototype + *----------------------------------------------------------------------------*/ +typedef void( *pFunc )( void ); + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern void __PROGRAM_START(void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Default_Handler(void) __NO_RETURN; +void Reset_Handler (void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const pFunc __VECTOR_TABLE[496]; + const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/ports/cortex_m33/ac5/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c b/ports/cortex_m33/ac5/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c new file mode 100644 index 00000000..36cb0c63 --- /dev/null +++ b/ports/cortex_m33/ac5/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c @@ -0,0 +1,115 @@ +/**************************************************************************//** + * @file system_ARMCM33.c + * @brief CMSIS Device System Source File for + * ARMCM33 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM33) + #include "ARMCM33.h" +#elif defined (ARMCM33_TZ) + #include "ARMCM33_TZ.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM33.h" + #endif +#elif defined (ARMCM33_DSP_FP) + #include "ARMCM33_DSP_FP.h" +#elif defined (ARMCM33_DSP_FP_TZ) + #include "ARMCM33_DSP_FP_TZ.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM33.h" + #endif +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; + + *(uint32_t *)0xE000ED24 = 0x000F0000; /* S: enable secure, usage, bus, mem faults */ + *(uint32_t *)0xE002ED24 = 0x000F0000; /* NS: enable secure, usage, bus, mem faults */ +} + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +void HardFault_Handler(void) +{ + while(1); + +} + +void UsageFault_Handler(void) +{ + while(1); +} +#endif diff --git a/ports/cortex_m33/ac5/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h b/ports/cortex_m33/ac5/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h new file mode 100644 index 00000000..65bfdcd7 --- /dev/null +++ b/ports/cortex_m33/ac5/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'demo_secure_zone' + * Target: 'FVP Simulation Model' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/ports/cortex_m33/ac5/example_build/demo_secure_zone/demo_secure_zone.uvoptx b/ports/cortex_m33/ac5/example_build/demo_secure_zone/demo_secure_zone.uvoptx new file mode 100644 index 00000000..ec235687 --- /dev/null +++ b/ports/cortex_m33/ac5/example_build/demo_secure_zone/demo_secure_zone.uvoptx @@ -0,0 +1,318 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + FVP Simulation Model + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 15 + + + + + + + + + + ..\Debug.ini + BIN\DbgFMv8M.DLL + + + + 0 + DLGTARM + (6010=245,200,722,796,0)(6018=306,263,495,612,0)(6019=488,279,677,615,0)(6008=-1,-1,-1,-1,0)(6009=-1,-1,-1,-1,0)(6014=724,129,982,860,0)(6015=-1,-1,-1,-1,0)(6003=-1,-1,-1,-1,0)(6000=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0) + + + 0 + DbgFMv8M + -I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMCM33_DSP_FP_TZ_config.txt" -PF -MA + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + + 0 + 1 + thread_0_counter + + + 1 + 1 + thread_1_counter + + + 2 + 1 + thread_2_counter + + + 3 + 1 + thread_3_counter + + + 4 + 1 + thread_4_counter + + + 5 + 1 + thread_5_counter + + + 6 + 1 + thread_6_counter + + + 7 + 1 + thread_7_counter + + + + + 1 + 2 + 0x2001ffd8 + 0 + + + + + 2 + 2 + 0xE000ED28 + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Secure Code + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + .\main_s.c + main_s.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\src\tx_thread_secure_stack.c + tx_thread_secure_stack.c + 0 + 0 + + + + + Interface + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + .\interface.c + interface.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 1 + 0 + 0 + 1 + + + diff --git a/ports/cortex_m33/ac5/example_build/demo_secure_zone/demo_secure_zone.uvprojx b/ports/cortex_m33/ac5/example_build/demo_secure_zone/demo_secure_zone.uvprojx new file mode 100644 index 00000000..c2fac3e4 --- /dev/null +++ b/ports/cortex_m33/ac5/example_build/demo_secure_zone/demo_secure_zone.uvprojx @@ -0,0 +1,497 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + FVP Simulation Model + 0x4 + ARM-ADS + 6140000::V6.14::ARMCLANG + 1 + + + ARMCM33_DSP_FP_TZ + ARM + ARM.CMSIS.5.7.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ESEL ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM33_DSP_FP_TZ$Device\ARM\ARMCM33\Include\ARMCM33_DSP_FP_TZ.h + + + + + + + + + + $$Device:ARMCM33_DSP_FP_TZ$Device\ARM\SVD\ARMCM33.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + demo_secure_zone + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + -MPU + TCM.DLL + -pCM33 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 0 + -1 + + 1 + BIN\UL2V8M.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M33" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 1 + 1 + 8 + 1 + 1 + 0 + 1 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x200000 + + + 1 + 0x200000 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x20200000 + 0x20000 + + + + + + 1 + 7 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 0 + 0 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\..\common\inc, ..\..\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\RTE\Device\ARMCM33_DSP_FP_TZ\ARMCM33_AC6.sct + + + + + + + + + + + Secure Code + + + main_s.c + 1 + .\main_s.c + + + tx_thread_secure_stack.c + 1 + ..\..\src\tx_thread_secure_stack.c + + + + + Interface + + + interface.c + 1 + .\interface.c + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\ARMCM33_ac6.sct + + + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\partition_ARMCM33.h + + + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.c + + + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.s + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\system_ARMCM33.c + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/ports/cortex_m33/ac5/example_build/demo_secure_zone/interface.c b/ports/cortex_m33/ac5/example_build/demo_secure_zone/interface.c new file mode 100644 index 00000000..4e6e8eee --- /dev/null +++ b/ports/cortex_m33/ac5/example_build/demo_secure_zone/interface.c @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * interface.c Secure/non-secure callable application code + * + * Version 1.0 + * Initial Release + *---------------------------------------------------------------------------*/ + + +#include // CMSE definitions +#include "interface.h" // Header file with secure interface API + +/* typedef for non-secure callback functions */ +typedef funcptr funcptr_NS __attribute__((cmse_nonsecure_call)); + +/* Non-secure callable (entry) function */ +int func1(int x) __attribute__((cmse_nonsecure_entry)) { + return x+3; +} + +/* Non-secure callable (entry) function, calling a non-secure callback function */ +int func2(funcptr callback, int x) __attribute__((cmse_nonsecure_entry)) { + funcptr_NS callback_NS; // non-secure callback function pointer + int y; + + /* return function pointer with cleared LSB */ + callback_NS = (funcptr_NS)cmse_nsfptr_create(callback); + + y = callback_NS (x+1); + + return (y+2); +} diff --git a/ports/cortex_m33/ac5/example_build/demo_secure_zone/interface.h b/ports/cortex_m33/ac5/example_build/demo_secure_zone/interface.h new file mode 100644 index 00000000..8215d5a3 --- /dev/null +++ b/ports/cortex_m33/ac5/example_build/demo_secure_zone/interface.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * interface.h API definition for the non-secure state + * + * Version 1.0 + * Initial Release + *---------------------------------------------------------------------------*/ + +/* Function pointer declaration */ +typedef int (*funcptr)(int); + +/* Non-secure callable functions */ +extern int func1(int x); +extern int func2(funcptr callback, int x); diff --git a/ports/cortex_m33/ac5/example_build/demo_secure_zone/main_ns.c b/ports/cortex_m33/ac5/example_build/demo_secure_zone/main_ns.c new file mode 100644 index 00000000..5d16e1bb --- /dev/null +++ b/ports/cortex_m33/ac5/example_build/demo_secure_zone/main_ns.c @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * main_ns.c Non-secure main function - RTOS demo + * + * Version 1.0 + * Initial Release + *---------------------------------------------------------------------------*/ + +#include "interface.h" // Interface API +//#include "cmsis_os2.h" // ARM::CMSIS:RTOS2:Keil RTX5 + +//static osStatus_t Status; + +//static osThreadId_t ThreadA_Id; +//static osThreadId_t ThreadB_Id; +//static osThreadId_t ThreadC_Id; + +void ThreadA (void *argument); +void ThreadB (void *argument); +void ThreadC (void *argument); + + +extern volatile int counterA; +extern volatile int counterB; +extern volatile int counterC; + +volatile int counterA; +volatile int counterB; +volatile int counterC; + +/* +static int callbackA (int val) { + return (val); +} + +__attribute__((noreturn)) +void ThreadA (void *argument) { + (void)argument; + + for (;;) { + counterA = func1 (counterA); + counterA = func2 (callbackA, counterA); + osDelay(2U); + } +} + +static int callbackB (int val) { + uint32_t flags; + + flags = osThreadFlagsWait (1U, osFlagsWaitAny, osWaitForever); + if (flags == 1U) { + return (val+1); + } else { + return (0); + } +} + + +__attribute__((noreturn)) +void ThreadB (void *argument) { + (void)argument; + + for (;;) { + counterB = func1 (counterB); + counterB = func2 (callbackB, counterB); + } +} + +__attribute__((noreturn)) +void ThreadC (void *argument) { + (void)argument; + + for (;;) { + counterC = counterC + 1; + if ((counterC % 0x10) == 0) { + osThreadFlagsSet (ThreadB_Id, 1); + } + osDelay(1U); + } +} + +static const osThreadAttr_t ThreadAttr = { + .tz_module = 1U, // indicate calls to secure mode +}; +*/ +#if 1 +int main (void) { + + for (;;); +} +#endif diff --git a/ports/cortex_m33/ac5/example_build/demo_secure_zone/main_s.c b/ports/cortex_m33/ac5/example_build/demo_secure_zone/main_s.c new file mode 100644 index 00000000..2c667821 --- /dev/null +++ b/ports/cortex_m33/ac5/example_build/demo_secure_zone/main_s.c @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 15. October 2016 + * $Revision: 1.1.0 + * + * Project: TrustZone for ARMv8-M + * Title: Code template for secure main function + * + *---------------------------------------------------------------------------*/ + +/* Use CMSE intrinsics */ +#include + #include +#include "RTE_Components.h" +#include CMSIS_device_header + +/* TZ_START_NS: Start address of non-secure application */ +#ifndef TZ_START_NS +#define TZ_START_NS (0x200000U) +#endif + +/* typedef for non-secure callback functions */ +typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call)); + +/* Secure main() */ +int main(void) { + funcptr_void NonSecure_ResetHandler; + + /* Add user setup code for secure part here*/ + + /* Set non-secure main stack (MSP_NS) */ + __TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS))); + + /* Get non-secure reset handler */ + NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U))); + + /* Start non-secure state software application */ + NonSecure_ResetHandler(); + + /* Non-secure software does not return, this code is not executed */ + while (1) { + __NOP(); + } +} diff --git a/ports/cortex_m33/ac5/example_build/demo_secure_zone/tz_context.c b/ports/cortex_m33/ac5/example_build/demo_secure_zone/tz_context.c new file mode 100644 index 00000000..f3152890 --- /dev/null +++ b/ports/cortex_m33/ac5/example_build/demo_secure_zone/tz_context.c @@ -0,0 +1,203 @@ +/* + * Copyright (c) 2015-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------------- + * + * $Date: 15. October 2016 + * $Revision: 1.1.0 + * + * Project: TrustZone for ARMv8-M + * Title: Context Management for ARMv8-M TrustZone - Sample implementation + * + *---------------------------------------------------------------------------*/ + +#include "RTE_Components.h" +#include CMSIS_device_header +#include "tz_context.h" + +/// Number of process slots (threads may call secure library code) +#ifndef TZ_PROCESS_STACK_SLOTS +#define TZ_PROCESS_STACK_SLOTS 8U +#endif + +/// Stack size of the secure library code +#ifndef TZ_PROCESS_STACK_SIZE +#define TZ_PROCESS_STACK_SIZE 256U +#endif + +typedef struct { + uint32_t sp_top; // stack space top + uint32_t sp_limit; // stack space limit + uint32_t sp; // current stack pointer +} stack_info_t; + +static stack_info_t ProcessStackInfo [TZ_PROCESS_STACK_SLOTS]; +static uint64_t ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/8U]; +static uint32_t ProcessStackFreeSlot = 0xFFFFFFFFU; + + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_InitContextSystem_S (void) { + uint32_t n; + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) { + ProcessStackInfo[n].sp = 0U; + ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n]; + ProcessStackInfo[n].sp_top = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE; + *((uint32_t *)ProcessStackMemory[n]) = n + 1U; + } + *((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU; + + ProcessStackFreeSlot = 0U; + + // Default process stack pointer and stack limit + __set_PSPLIM((uint32_t)ProcessStackMemory); + __set_PSP ((uint32_t)ProcessStackMemory); + + // Privileged Thread Mode using PSP + __set_CONTROL(0x02U); + + return 1U; // Success +} + + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +__attribute__((cmse_nonsecure_entry)) +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) { + uint32_t slot; + + (void)module; // Ignore (fixed Stack size) + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + if (ProcessStackFreeSlot == 0xFFFFFFFFU) { + return 0U; // No slot available + } + + slot = ProcessStackFreeSlot; + ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]); + + ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top; + + return (slot + 1U); +} + + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) { + uint32_t slot; + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + ProcessStackInfo[slot].sp = 0U; + + *((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot; + ProcessStackFreeSlot = slot; + + return 1U; // Success +} + + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id) { + uint32_t slot; + + if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { + return 0U; // Thread Mode or using Main Stack for threads + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + + // Setup process stack pointer and stack limit + __set_PSPLIM(ProcessStackInfo[slot].sp_limit); + __set_PSP (ProcessStackInfo[slot].sp); + + return 1U; // Success +} + + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id) { + uint32_t slot; + uint32_t sp; + + if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { + return 0U; // Thread Mode or using Main Stack for threads + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + + sp = __get_PSP(); + if ((sp < ProcessStackInfo[slot].sp_limit) || + (sp > ProcessStackInfo[slot].sp_top)) { + return 0U; // SP out of range + } + ProcessStackInfo[slot].sp = sp; + + // Default process stack pointer and stack limit + __set_PSPLIM((uint32_t)ProcessStackMemory); + __set_PSP ((uint32_t)ProcessStackMemory); + + return 1U; // Success +} diff --git a/ports/cortex_m33/ac5/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c b/ports/cortex_m33/ac5/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c new file mode 100644 index 00000000..e4871014 --- /dev/null +++ b/ports/cortex_m33/ac5/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + + for (;;) {} +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; + + switch (code) { + case osRtxErrorStackUnderflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +} diff --git a/ports/cortex_m33/ac5/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h b/ports/cortex_m33/ac5/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h new file mode 100644 index 00000000..3021efbc --- /dev/null +++ b/ports/cortex_m33/ac5/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,578 @@ +/* + * Copyright (c) 2013-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.5.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 4096 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 4096 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 0 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 1 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 0 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 256 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 256 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 256 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 256 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch. +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 256 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 256 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial recording level applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Recording levels for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Recording level for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_LEVEL +#define OS_EVR_MEMORY_LEVEL 0x01U +#endif + +// Kernel +// Recording level for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_LEVEL +#define OS_EVR_KERNEL_LEVEL 0x01U +#endif + +// Thread +// Recording level for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_LEVEL +#define OS_EVR_THREAD_LEVEL 0x05U +#endif + +// Generic Wait +// Recording level for Generic Wait events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_WAIT_LEVEL +#define OS_EVR_WAIT_LEVEL 0x01U +#endif + +// Thread Flags +// Recording level for Thread Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THFLAGS_LEVEL +#define OS_EVR_THFLAGS_LEVEL 0x01U +#endif + +// Event Flags +// Recording level for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_LEVEL +#define OS_EVR_EVFLAGS_LEVEL 0x01U +#endif + +// Timer +// Recording level for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_LEVEL +#define OS_EVR_TIMER_LEVEL 0x01U +#endif + +// Mutex +// Recording level for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_LEVEL +#define OS_EVR_MUTEX_LEVEL 0x01U +#endif + +// Semaphore +// Recording level for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_LEVEL +#define OS_EVR_SEMAPHORE_LEVEL 0x01U +#endif + +// Memory Pool +// Recording level for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_LEVEL +#define OS_EVR_MEMPOOL_LEVEL 0x01U +#endif + +// Message Queue +// Recording level for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_LEVEL +#define OS_EVR_MSGQUEUE_LEVEL 0x01U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Generic Wait +// Enables Generic Wait event generation. +#ifndef OS_EVR_WAIT +#define OS_EVR_WAIT 1 +#endif + +// Thread Flags +// Enables Thread Flags event generation. +#ifndef OS_EVR_THFLAGS +#define OS_EVR_THFLAGS 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#define OS_THREAD_LIBSPACE_NUM 4 +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/ports/cortex_m33/ac5/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_AC6.sct b/ports/cortex_m33/ac5/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_AC6.sct new file mode 100644 index 00000000..3480c921 --- /dev/null +++ b/ports/cortex_m33/ac5/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_AC6.sct @@ -0,0 +1,74 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc +; command above MUST be in first line (no comment above!) + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x00200000 +#define __ROM_SIZE 0x00200000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x20200000 +#define __RAM_SIZE 0x00020000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000400 +#define __HEAP_SIZE 0x00000C00 + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundery definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ +#define __RO_BASE __ROM_BASE +#define __RO_SIZE __ROM_SIZE + +#define __RW_BASE (__RAM_BASE ) +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) + + + +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) +; *(Veneer$$CMSE) ; uncomment for secure applications + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } +} diff --git a/ports/cortex_m33/ac5/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h b/ports/cortex_m33/ac5/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h new file mode 100644 index 00000000..a7cb0d73 --- /dev/null +++ b/ports/cortex_m33/ac5/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h @@ -0,0 +1,1260 @@ +/**************************************************************************//** + * @file partition_ARMCM33.h + * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33 + * @version V1.1.1 + * @date 12. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PARTITION_ARMCM33_H +#define PARTITION_ARMCM33_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 1 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x00200000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x003FFFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x20200000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x203FFFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x40040000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 1 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 1 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 1 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x80-0xFF +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 1 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// Interrupt 0 <0=> Secure state <1=> Non-Secure state +// Interrupt 1 <0=> Secure state <1=> Non-Secure state +// Interrupt 2 <0=> Secure state <1=> Non-Secure state +// Interrupt 3 <0=> Secure state <1=> Non-Secure state +// Interrupt 4 <0=> Secure state <1=> Non-Secure state +// Interrupt 5 <0=> Secure state <1=> Non-Secure state +// Interrupt 6 <0=> Secure state <1=> Non-Secure state +// Interrupt 7 <0=> Secure state <1=> Non-Secure state +// Interrupt 8 <0=> Secure state <1=> Non-Secure state +// Interrupt 9 <0=> Secure state <1=> Non-Secure state +// Interrupt 10 <0=> Secure state <1=> Non-Secure state +// Interrupt 11 <0=> Secure state <1=> Non-Secure state +// Interrupt 12 <0=> Secure state <1=> Non-Secure state +// Interrupt 13 <0=> Secure state <1=> Non-Secure state +// Interrupt 14 <0=> Secure state <1=> Non-Secure state +// Interrupt 15 <0=> Secure state <1=> Non-Secure state +// Interrupt 16 <0=> Secure state <1=> Non-Secure state +// Interrupt 17 <0=> Secure state <1=> Non-Secure state +// Interrupt 18 <0=> Secure state <1=> Non-Secure state +// Interrupt 19 <0=> Secure state <1=> Non-Secure state +// Interrupt 20 <0=> Secure state <1=> Non-Secure state +// Interrupt 21 <0=> Secure state <1=> Non-Secure state +// Interrupt 22 <0=> Secure state <1=> Non-Secure state +// Interrupt 23 <0=> Secure state <1=> Non-Secure state +// Interrupt 24 <0=> Secure state <1=> Non-Secure state +// Interrupt 25 <0=> Secure state <1=> Non-Secure state +// Interrupt 26 <0=> Secure state <1=> Non-Secure state +// Interrupt 27 <0=> Secure state <1=> Non-Secure state +// Interrupt 28 <0=> Secure state <1=> Non-Secure state +// Interrupt 29 <0=> Secure state <1=> Non-Secure state +// Interrupt 30 <0=> Secure state <1=> Non-Secure state +// Interrupt 31 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// Interrupt 32 <0=> Secure state <1=> Non-Secure state +// Interrupt 33 <0=> Secure state <1=> Non-Secure state +// Interrupt 34 <0=> Secure state <1=> Non-Secure state +// Interrupt 35 <0=> Secure state <1=> Non-Secure state +// Interrupt 36 <0=> Secure state <1=> Non-Secure state +// Interrupt 37 <0=> Secure state <1=> Non-Secure state +// Interrupt 38 <0=> Secure state <1=> Non-Secure state +// Interrupt 39 <0=> Secure state <1=> Non-Secure state +// Interrupt 40 <0=> Secure state <1=> Non-Secure state +// Interrupt 41 <0=> Secure state <1=> Non-Secure state +// Interrupt 42 <0=> Secure state <1=> Non-Secure state +// Interrupt 43 <0=> Secure state <1=> Non-Secure state +// Interrupt 44 <0=> Secure state <1=> Non-Secure state +// Interrupt 45 <0=> Secure state <1=> Non-Secure state +// Interrupt 46 <0=> Secure state <1=> Non-Secure state +// Interrupt 47 <0=> Secure state <1=> Non-Secure state +// Interrupt 48 <0=> Secure state <1=> Non-Secure state +// Interrupt 49 <0=> Secure state <1=> Non-Secure state +// Interrupt 50 <0=> Secure state <1=> Non-Secure state +// Interrupt 51 <0=> Secure state <1=> Non-Secure state +// Interrupt 52 <0=> Secure state <1=> Non-Secure state +// Interrupt 53 <0=> Secure state <1=> Non-Secure state +// Interrupt 54 <0=> Secure state <1=> Non-Secure state +// Interrupt 55 <0=> Secure state <1=> Non-Secure state +// Interrupt 56 <0=> Secure state <1=> Non-Secure state +// Interrupt 57 <0=> Secure state <1=> Non-Secure state +// Interrupt 58 <0=> Secure state <1=> Non-Secure state +// Interrupt 59 <0=> Secure state <1=> Non-Secure state +// Interrupt 60 <0=> Secure state <1=> Non-Secure state +// Interrupt 61 <0=> Secure state <1=> Non-Secure state +// Interrupt 62 <0=> Secure state <1=> Non-Secure state +// Interrupt 63 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 0 + +/* +// Interrupts 64..95 +// Interrupt 64 <0=> Secure state <1=> Non-Secure state +// Interrupt 65 <0=> Secure state <1=> Non-Secure state +// Interrupt 66 <0=> Secure state <1=> Non-Secure state +// Interrupt 67 <0=> Secure state <1=> Non-Secure state +// Interrupt 68 <0=> Secure state <1=> Non-Secure state +// Interrupt 69 <0=> Secure state <1=> Non-Secure state +// Interrupt 70 <0=> Secure state <1=> Non-Secure state +// Interrupt 71 <0=> Secure state <1=> Non-Secure state +// Interrupt 72 <0=> Secure state <1=> Non-Secure state +// Interrupt 73 <0=> Secure state <1=> Non-Secure state +// Interrupt 74 <0=> Secure state <1=> Non-Secure state +// Interrupt 75 <0=> Secure state <1=> Non-Secure state +// Interrupt 76 <0=> Secure state <1=> Non-Secure state +// Interrupt 77 <0=> Secure state <1=> Non-Secure state +// Interrupt 78 <0=> Secure state <1=> Non-Secure state +// Interrupt 79 <0=> Secure state <1=> Non-Secure state +// Interrupt 80 <0=> Secure state <1=> Non-Secure state +// Interrupt 81 <0=> Secure state <1=> Non-Secure state +// Interrupt 82 <0=> Secure state <1=> Non-Secure state +// Interrupt 83 <0=> Secure state <1=> Non-Secure state +// Interrupt 84 <0=> Secure state <1=> Non-Secure state +// Interrupt 85 <0=> Secure state <1=> Non-Secure state +// Interrupt 86 <0=> Secure state <1=> Non-Secure state +// Interrupt 87 <0=> Secure state <1=> Non-Secure state +// Interrupt 88 <0=> Secure state <1=> Non-Secure state +// Interrupt 89 <0=> Secure state <1=> Non-Secure state +// Interrupt 90 <0=> Secure state <1=> Non-Secure state +// Interrupt 91 <0=> Secure state <1=> Non-Secure state +// Interrupt 92 <0=> Secure state <1=> Non-Secure state +// Interrupt 93 <0=> Secure state <1=> Non-Secure state +// Interrupt 94 <0=> Secure state <1=> Non-Secure state +// Interrupt 95 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 0 + +/* +// Interrupts 96..127 +// Interrupt 96 <0=> Secure state <1=> Non-Secure state +// Interrupt 97 <0=> Secure state <1=> Non-Secure state +// Interrupt 98 <0=> Secure state <1=> Non-Secure state +// Interrupt 99 <0=> Secure state <1=> Non-Secure state +// Interrupt 100 <0=> Secure state <1=> Non-Secure state +// Interrupt 101 <0=> Secure state <1=> Non-Secure state +// Interrupt 102 <0=> Secure state <1=> Non-Secure state +// Interrupt 103 <0=> Secure state <1=> Non-Secure state +// Interrupt 104 <0=> Secure state <1=> Non-Secure state +// Interrupt 105 <0=> Secure state <1=> Non-Secure state +// Interrupt 106 <0=> Secure state <1=> Non-Secure state +// Interrupt 107 <0=> Secure state <1=> Non-Secure state +// Interrupt 108 <0=> Secure state <1=> Non-Secure state +// Interrupt 109 <0=> Secure state <1=> Non-Secure state +// Interrupt 110 <0=> Secure state <1=> Non-Secure state +// Interrupt 111 <0=> Secure state <1=> Non-Secure state +// Interrupt 112 <0=> Secure state <1=> Non-Secure state +// Interrupt 113 <0=> Secure state <1=> Non-Secure state +// Interrupt 114 <0=> Secure state <1=> Non-Secure state +// Interrupt 115 <0=> Secure state <1=> Non-Secure state +// Interrupt 116 <0=> Secure state <1=> Non-Secure state +// Interrupt 117 <0=> Secure state <1=> Non-Secure state +// Interrupt 118 <0=> Secure state <1=> Non-Secure state +// Interrupt 119 <0=> Secure state <1=> Non-Secure state +// Interrupt 120 <0=> Secure state <1=> Non-Secure state +// Interrupt 121 <0=> Secure state <1=> Non-Secure state +// Interrupt 122 <0=> Secure state <1=> Non-Secure state +// Interrupt 123 <0=> Secure state <1=> Non-Secure state +// Interrupt 124 <0=> Secure state <1=> Non-Secure state +// Interrupt 125 <0=> Secure state <1=> Non-Secure state +// Interrupt 126 <0=> Secure state <1=> Non-Secure state +// Interrupt 127 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 128..159) +*/ +#define NVIC_INIT_ITNS4 0 + +/* +// Interrupts 128..159 +// Interrupt 128 <0=> Secure state <1=> Non-Secure state +// Interrupt 129 <0=> Secure state <1=> Non-Secure state +// Interrupt 130 <0=> Secure state <1=> Non-Secure state +// Interrupt 131 <0=> Secure state <1=> Non-Secure state +// Interrupt 132 <0=> Secure state <1=> Non-Secure state +// Interrupt 133 <0=> Secure state <1=> Non-Secure state +// Interrupt 134 <0=> Secure state <1=> Non-Secure state +// Interrupt 135 <0=> Secure state <1=> Non-Secure state +// Interrupt 136 <0=> Secure state <1=> Non-Secure state +// Interrupt 137 <0=> Secure state <1=> Non-Secure state +// Interrupt 138 <0=> Secure state <1=> Non-Secure state +// Interrupt 139 <0=> Secure state <1=> Non-Secure state +// Interrupt 140 <0=> Secure state <1=> Non-Secure state +// Interrupt 141 <0=> Secure state <1=> Non-Secure state +// Interrupt 142 <0=> Secure state <1=> Non-Secure state +// Interrupt 143 <0=> Secure state <1=> Non-Secure state +// Interrupt 144 <0=> Secure state <1=> Non-Secure state +// Interrupt 145 <0=> Secure state <1=> Non-Secure state +// Interrupt 146 <0=> Secure state <1=> Non-Secure state +// Interrupt 147 <0=> Secure state <1=> Non-Secure state +// Interrupt 148 <0=> Secure state <1=> Non-Secure state +// Interrupt 149 <0=> Secure state <1=> Non-Secure state +// Interrupt 150 <0=> Secure state <1=> Non-Secure state +// Interrupt 151 <0=> Secure state <1=> Non-Secure state +// Interrupt 152 <0=> Secure state <1=> Non-Secure state +// Interrupt 153 <0=> Secure state <1=> Non-Secure state +// Interrupt 154 <0=> Secure state <1=> Non-Secure state +// Interrupt 155 <0=> Secure state <1=> Non-Secure state +// Interrupt 156 <0=> Secure state <1=> Non-Secure state +// Interrupt 157 <0=> Secure state <1=> Non-Secure state +// Interrupt 158 <0=> Secure state <1=> Non-Secure state +// Interrupt 159 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 5 (Interrupts 160..191) +*/ +#define NVIC_INIT_ITNS5 0 + +/* +// Interrupts 160..191 +// Interrupt 160 <0=> Secure state <1=> Non-Secure state +// Interrupt 161 <0=> Secure state <1=> Non-Secure state +// Interrupt 162 <0=> Secure state <1=> Non-Secure state +// Interrupt 163 <0=> Secure state <1=> Non-Secure state +// Interrupt 164 <0=> Secure state <1=> Non-Secure state +// Interrupt 165 <0=> Secure state <1=> Non-Secure state +// Interrupt 166 <0=> Secure state <1=> Non-Secure state +// Interrupt 167 <0=> Secure state <1=> Non-Secure state +// Interrupt 168 <0=> Secure state <1=> Non-Secure state +// Interrupt 169 <0=> Secure state <1=> Non-Secure state +// Interrupt 170 <0=> Secure state <1=> Non-Secure state +// Interrupt 171 <0=> Secure state <1=> Non-Secure state +// Interrupt 172 <0=> Secure state <1=> Non-Secure state +// Interrupt 173 <0=> Secure state <1=> Non-Secure state +// Interrupt 174 <0=> Secure state <1=> Non-Secure state +// Interrupt 175 <0=> Secure state <1=> Non-Secure state +// Interrupt 176 <0=> Secure state <1=> Non-Secure state +// Interrupt 177 <0=> Secure state <1=> Non-Secure state +// Interrupt 178 <0=> Secure state <1=> Non-Secure state +// Interrupt 179 <0=> Secure state <1=> Non-Secure state +// Interrupt 180 <0=> Secure state <1=> Non-Secure state +// Interrupt 181 <0=> Secure state <1=> Non-Secure state +// Interrupt 182 <0=> Secure state <1=> Non-Secure state +// Interrupt 183 <0=> Secure state <1=> Non-Secure state +// Interrupt 184 <0=> Secure state <1=> Non-Secure state +// Interrupt 185 <0=> Secure state <1=> Non-Secure state +// Interrupt 186 <0=> Secure state <1=> Non-Secure state +// Interrupt 187 <0=> Secure state <1=> Non-Secure state +// Interrupt 188 <0=> Secure state <1=> Non-Secure state +// Interrupt 189 <0=> Secure state <1=> Non-Secure state +// Interrupt 190 <0=> Secure state <1=> Non-Secure state +// Interrupt 191 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS5_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 6 (Interrupts 192..223) +*/ +#define NVIC_INIT_ITNS6 0 + +/* +// Interrupts 192..223 +// Interrupt 192 <0=> Secure state <1=> Non-Secure state +// Interrupt 193 <0=> Secure state <1=> Non-Secure state +// Interrupt 194 <0=> Secure state <1=> Non-Secure state +// Interrupt 195 <0=> Secure state <1=> Non-Secure state +// Interrupt 196 <0=> Secure state <1=> Non-Secure state +// Interrupt 197 <0=> Secure state <1=> Non-Secure state +// Interrupt 198 <0=> Secure state <1=> Non-Secure state +// Interrupt 199 <0=> Secure state <1=> Non-Secure state +// Interrupt 200 <0=> Secure state <1=> Non-Secure state +// Interrupt 201 <0=> Secure state <1=> Non-Secure state +// Interrupt 202 <0=> Secure state <1=> Non-Secure state +// Interrupt 203 <0=> Secure state <1=> Non-Secure state +// Interrupt 204 <0=> Secure state <1=> Non-Secure state +// Interrupt 205 <0=> Secure state <1=> Non-Secure state +// Interrupt 206 <0=> Secure state <1=> Non-Secure state +// Interrupt 207 <0=> Secure state <1=> Non-Secure state +// Interrupt 208 <0=> Secure state <1=> Non-Secure state +// Interrupt 209 <0=> Secure state <1=> Non-Secure state +// Interrupt 210 <0=> Secure state <1=> Non-Secure state +// Interrupt 211 <0=> Secure state <1=> Non-Secure state +// Interrupt 212 <0=> Secure state <1=> Non-Secure state +// Interrupt 213 <0=> Secure state <1=> Non-Secure state +// Interrupt 214 <0=> Secure state <1=> Non-Secure state +// Interrupt 215 <0=> Secure state <1=> Non-Secure state +// Interrupt 216 <0=> Secure state <1=> Non-Secure state +// Interrupt 217 <0=> Secure state <1=> Non-Secure state +// Interrupt 218 <0=> Secure state <1=> Non-Secure state +// Interrupt 219 <0=> Secure state <1=> Non-Secure state +// Interrupt 220 <0=> Secure state <1=> Non-Secure state +// Interrupt 221 <0=> Secure state <1=> Non-Secure state +// Interrupt 222 <0=> Secure state <1=> Non-Secure state +// Interrupt 223 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS6_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 7 (Interrupts 224..255) +*/ +#define NVIC_INIT_ITNS7 0 + +/* +// Interrupts 224..255 +// Interrupt 224 <0=> Secure state <1=> Non-Secure state +// Interrupt 225 <0=> Secure state <1=> Non-Secure state +// Interrupt 226 <0=> Secure state <1=> Non-Secure state +// Interrupt 227 <0=> Secure state <1=> Non-Secure state +// Interrupt 228 <0=> Secure state <1=> Non-Secure state +// Interrupt 229 <0=> Secure state <1=> Non-Secure state +// Interrupt 230 <0=> Secure state <1=> Non-Secure state +// Interrupt 231 <0=> Secure state <1=> Non-Secure state +// Interrupt 232 <0=> Secure state <1=> Non-Secure state +// Interrupt 233 <0=> Secure state <1=> Non-Secure state +// Interrupt 234 <0=> Secure state <1=> Non-Secure state +// Interrupt 235 <0=> Secure state <1=> Non-Secure state +// Interrupt 236 <0=> Secure state <1=> Non-Secure state +// Interrupt 237 <0=> Secure state <1=> Non-Secure state +// Interrupt 238 <0=> Secure state <1=> Non-Secure state +// Interrupt 239 <0=> Secure state <1=> Non-Secure state +// Interrupt 240 <0=> Secure state <1=> Non-Secure state +// Interrupt 241 <0=> Secure state <1=> Non-Secure state +// Interrupt 242 <0=> Secure state <1=> Non-Secure state +// Interrupt 243 <0=> Secure state <1=> Non-Secure state +// Interrupt 244 <0=> Secure state <1=> Non-Secure state +// Interrupt 245 <0=> Secure state <1=> Non-Secure state +// Interrupt 246 <0=> Secure state <1=> Non-Secure state +// Interrupt 247 <0=> Secure state <1=> Non-Secure state +// Interrupt 248 <0=> Secure state <1=> Non-Secure state +// Interrupt 249 <0=> Secure state <1=> Non-Secure state +// Interrupt 250 <0=> Secure state <1=> Non-Secure state +// Interrupt 251 <0=> Secure state <1=> Non-Secure state +// Interrupt 252 <0=> Secure state <1=> Non-Secure state +// Interrupt 253 <0=> Secure state <1=> Non-Secure state +// Interrupt 254 <0=> Secure state <1=> Non-Secure state +// Interrupt 255 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS7_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 8 (Interrupts 256..287) +*/ +#define NVIC_INIT_ITNS8 0 + +/* +// Interrupts 256..287 +// Interrupt 256 <0=> Secure state <1=> Non-Secure state +// Interrupt 257 <0=> Secure state <1=> Non-Secure state +// Interrupt 258 <0=> Secure state <1=> Non-Secure state +// Interrupt 259 <0=> Secure state <1=> Non-Secure state +// Interrupt 260 <0=> Secure state <1=> Non-Secure state +// Interrupt 261 <0=> Secure state <1=> Non-Secure state +// Interrupt 262 <0=> Secure state <1=> Non-Secure state +// Interrupt 263 <0=> Secure state <1=> Non-Secure state +// Interrupt 264 <0=> Secure state <1=> Non-Secure state +// Interrupt 265 <0=> Secure state <1=> Non-Secure state +// Interrupt 266 <0=> Secure state <1=> Non-Secure state +// Interrupt 267 <0=> Secure state <1=> Non-Secure state +// Interrupt 268 <0=> Secure state <1=> Non-Secure state +// Interrupt 269 <0=> Secure state <1=> Non-Secure state +// Interrupt 270 <0=> Secure state <1=> Non-Secure state +// Interrupt 271 <0=> Secure state <1=> Non-Secure state +// Interrupt 272 <0=> Secure state <1=> Non-Secure state +// Interrupt 273 <0=> Secure state <1=> Non-Secure state +// Interrupt 274 <0=> Secure state <1=> Non-Secure state +// Interrupt 275 <0=> Secure state <1=> Non-Secure state +// Interrupt 276 <0=> Secure state <1=> Non-Secure state +// Interrupt 277 <0=> Secure state <1=> Non-Secure state +// Interrupt 278 <0=> Secure state <1=> Non-Secure state +// Interrupt 279 <0=> Secure state <1=> Non-Secure state +// Interrupt 280 <0=> Secure state <1=> Non-Secure state +// Interrupt 281 <0=> Secure state <1=> Non-Secure state +// Interrupt 282 <0=> Secure state <1=> Non-Secure state +// Interrupt 283 <0=> Secure state <1=> Non-Secure state +// Interrupt 284 <0=> Secure state <1=> Non-Secure state +// Interrupt 285 <0=> Secure state <1=> Non-Secure state +// Interrupt 286 <0=> Secure state <1=> Non-Secure state +// Interrupt 287 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS8_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 9 (Interrupts 288..319) +*/ +#define NVIC_INIT_ITNS9 0 + +/* +// Interrupts 288..319 +// Interrupt 288 <0=> Secure state <1=> Non-Secure state +// Interrupt 289 <0=> Secure state <1=> Non-Secure state +// Interrupt 290 <0=> Secure state <1=> Non-Secure state +// Interrupt 291 <0=> Secure state <1=> Non-Secure state +// Interrupt 292 <0=> Secure state <1=> Non-Secure state +// Interrupt 293 <0=> Secure state <1=> Non-Secure state +// Interrupt 294 <0=> Secure state <1=> Non-Secure state +// Interrupt 295 <0=> Secure state <1=> Non-Secure state +// Interrupt 296 <0=> Secure state <1=> Non-Secure state +// Interrupt 297 <0=> Secure state <1=> Non-Secure state +// Interrupt 298 <0=> Secure state <1=> Non-Secure state +// Interrupt 299 <0=> Secure state <1=> Non-Secure state +// Interrupt 300 <0=> Secure state <1=> Non-Secure state +// Interrupt 301 <0=> Secure state <1=> Non-Secure state +// Interrupt 302 <0=> Secure state <1=> Non-Secure state +// Interrupt 303 <0=> Secure state <1=> Non-Secure state +// Interrupt 304 <0=> Secure state <1=> Non-Secure state +// Interrupt 305 <0=> Secure state <1=> Non-Secure state +// Interrupt 306 <0=> Secure state <1=> Non-Secure state +// Interrupt 307 <0=> Secure state <1=> Non-Secure state +// Interrupt 308 <0=> Secure state <1=> Non-Secure state +// Interrupt 309 <0=> Secure state <1=> Non-Secure state +// Interrupt 310 <0=> Secure state <1=> Non-Secure state +// Interrupt 311 <0=> Secure state <1=> Non-Secure state +// Interrupt 312 <0=> Secure state <1=> Non-Secure state +// Interrupt 313 <0=> Secure state <1=> Non-Secure state +// Interrupt 314 <0=> Secure state <1=> Non-Secure state +// Interrupt 315 <0=> Secure state <1=> Non-Secure state +// Interrupt 316 <0=> Secure state <1=> Non-Secure state +// Interrupt 317 <0=> Secure state <1=> Non-Secure state +// Interrupt 318 <0=> Secure state <1=> Non-Secure state +// Interrupt 319 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS9_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 10 (Interrupts 320..351) +*/ +#define NVIC_INIT_ITNS10 0 + +/* +// Interrupts 320..351 +// Interrupt 320 <0=> Secure state <1=> Non-Secure state +// Interrupt 321 <0=> Secure state <1=> Non-Secure state +// Interrupt 322 <0=> Secure state <1=> Non-Secure state +// Interrupt 323 <0=> Secure state <1=> Non-Secure state +// Interrupt 324 <0=> Secure state <1=> Non-Secure state +// Interrupt 325 <0=> Secure state <1=> Non-Secure state +// Interrupt 326 <0=> Secure state <1=> Non-Secure state +// Interrupt 327 <0=> Secure state <1=> Non-Secure state +// Interrupt 328 <0=> Secure state <1=> Non-Secure state +// Interrupt 329 <0=> Secure state <1=> Non-Secure state +// Interrupt 330 <0=> Secure state <1=> Non-Secure state +// Interrupt 331 <0=> Secure state <1=> Non-Secure state +// Interrupt 332 <0=> Secure state <1=> Non-Secure state +// Interrupt 333 <0=> Secure state <1=> Non-Secure state +// Interrupt 334 <0=> Secure state <1=> Non-Secure state +// Interrupt 335 <0=> Secure state <1=> Non-Secure state +// Interrupt 336 <0=> Secure state <1=> Non-Secure state +// Interrupt 337 <0=> Secure state <1=> Non-Secure state +// Interrupt 338 <0=> Secure state <1=> Non-Secure state +// Interrupt 339 <0=> Secure state <1=> Non-Secure state +// Interrupt 340 <0=> Secure state <1=> Non-Secure state +// Interrupt 341 <0=> Secure state <1=> Non-Secure state +// Interrupt 342 <0=> Secure state <1=> Non-Secure state +// Interrupt 343 <0=> Secure state <1=> Non-Secure state +// Interrupt 344 <0=> Secure state <1=> Non-Secure state +// Interrupt 345 <0=> Secure state <1=> Non-Secure state +// Interrupt 346 <0=> Secure state <1=> Non-Secure state +// Interrupt 347 <0=> Secure state <1=> Non-Secure state +// Interrupt 348 <0=> Secure state <1=> Non-Secure state +// Interrupt 349 <0=> Secure state <1=> Non-Secure state +// Interrupt 350 <0=> Secure state <1=> Non-Secure state +// Interrupt 351 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS10_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 11 (Interrupts 352..383) +*/ +#define NVIC_INIT_ITNS11 0 + +/* +// Interrupts 352..383 +// Interrupt 352 <0=> Secure state <1=> Non-Secure state +// Interrupt 353 <0=> Secure state <1=> Non-Secure state +// Interrupt 354 <0=> Secure state <1=> Non-Secure state +// Interrupt 355 <0=> Secure state <1=> Non-Secure state +// Interrupt 356 <0=> Secure state <1=> Non-Secure state +// Interrupt 357 <0=> Secure state <1=> Non-Secure state +// Interrupt 358 <0=> Secure state <1=> Non-Secure state +// Interrupt 359 <0=> Secure state <1=> Non-Secure state +// Interrupt 360 <0=> Secure state <1=> Non-Secure state +// Interrupt 361 <0=> Secure state <1=> Non-Secure state +// Interrupt 362 <0=> Secure state <1=> Non-Secure state +// Interrupt 363 <0=> Secure state <1=> Non-Secure state +// Interrupt 364 <0=> Secure state <1=> Non-Secure state +// Interrupt 365 <0=> Secure state <1=> Non-Secure state +// Interrupt 366 <0=> Secure state <1=> Non-Secure state +// Interrupt 367 <0=> Secure state <1=> Non-Secure state +// Interrupt 368 <0=> Secure state <1=> Non-Secure state +// Interrupt 369 <0=> Secure state <1=> Non-Secure state +// Interrupt 370 <0=> Secure state <1=> Non-Secure state +// Interrupt 371 <0=> Secure state <1=> Non-Secure state +// Interrupt 372 <0=> Secure state <1=> Non-Secure state +// Interrupt 373 <0=> Secure state <1=> Non-Secure state +// Interrupt 374 <0=> Secure state <1=> Non-Secure state +// Interrupt 375 <0=> Secure state <1=> Non-Secure state +// Interrupt 376 <0=> Secure state <1=> Non-Secure state +// Interrupt 377 <0=> Secure state <1=> Non-Secure state +// Interrupt 378 <0=> Secure state <1=> Non-Secure state +// Interrupt 379 <0=> Secure state <1=> Non-Secure state +// Interrupt 380 <0=> Secure state <1=> Non-Secure state +// Interrupt 381 <0=> Secure state <1=> Non-Secure state +// Interrupt 382 <0=> Secure state <1=> Non-Secure state +// Interrupt 383 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS11_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 12 (Interrupts 384..415) +*/ +#define NVIC_INIT_ITNS12 0 + +/* +// Interrupts 384..415 +// Interrupt 384 <0=> Secure state <1=> Non-Secure state +// Interrupt 385 <0=> Secure state <1=> Non-Secure state +// Interrupt 386 <0=> Secure state <1=> Non-Secure state +// Interrupt 387 <0=> Secure state <1=> Non-Secure state +// Interrupt 388 <0=> Secure state <1=> Non-Secure state +// Interrupt 389 <0=> Secure state <1=> Non-Secure state +// Interrupt 390 <0=> Secure state <1=> Non-Secure state +// Interrupt 391 <0=> Secure state <1=> Non-Secure state +// Interrupt 392 <0=> Secure state <1=> Non-Secure state +// Interrupt 393 <0=> Secure state <1=> Non-Secure state +// Interrupt 394 <0=> Secure state <1=> Non-Secure state +// Interrupt 395 <0=> Secure state <1=> Non-Secure state +// Interrupt 396 <0=> Secure state <1=> Non-Secure state +// Interrupt 397 <0=> Secure state <1=> Non-Secure state +// Interrupt 398 <0=> Secure state <1=> Non-Secure state +// Interrupt 399 <0=> Secure state <1=> Non-Secure state +// Interrupt 400 <0=> Secure state <1=> Non-Secure state +// Interrupt 401 <0=> Secure state <1=> Non-Secure state +// Interrupt 402 <0=> Secure state <1=> Non-Secure state +// Interrupt 403 <0=> Secure state <1=> Non-Secure state +// Interrupt 404 <0=> Secure state <1=> Non-Secure state +// Interrupt 405 <0=> Secure state <1=> Non-Secure state +// Interrupt 406 <0=> Secure state <1=> Non-Secure state +// Interrupt 407 <0=> Secure state <1=> Non-Secure state +// Interrupt 408 <0=> Secure state <1=> Non-Secure state +// Interrupt 409 <0=> Secure state <1=> Non-Secure state +// Interrupt 410 <0=> Secure state <1=> Non-Secure state +// Interrupt 411 <0=> Secure state <1=> Non-Secure state +// Interrupt 412 <0=> Secure state <1=> Non-Secure state +// Interrupt 413 <0=> Secure state <1=> Non-Secure state +// Interrupt 414 <0=> Secure state <1=> Non-Secure state +// Interrupt 415 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS12_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 13 (Interrupts 416..447) +*/ +#define NVIC_INIT_ITNS13 0 + +/* +// Interrupts 416..447 +// Interrupt 416 <0=> Secure state <1=> Non-Secure state +// Interrupt 417 <0=> Secure state <1=> Non-Secure state +// Interrupt 418 <0=> Secure state <1=> Non-Secure state +// Interrupt 419 <0=> Secure state <1=> Non-Secure state +// Interrupt 420 <0=> Secure state <1=> Non-Secure state +// Interrupt 421 <0=> Secure state <1=> Non-Secure state +// Interrupt 422 <0=> Secure state <1=> Non-Secure state +// Interrupt 423 <0=> Secure state <1=> Non-Secure state +// Interrupt 424 <0=> Secure state <1=> Non-Secure state +// Interrupt 425 <0=> Secure state <1=> Non-Secure state +// Interrupt 426 <0=> Secure state <1=> Non-Secure state +// Interrupt 427 <0=> Secure state <1=> Non-Secure state +// Interrupt 428 <0=> Secure state <1=> Non-Secure state +// Interrupt 429 <0=> Secure state <1=> Non-Secure state +// Interrupt 430 <0=> Secure state <1=> Non-Secure state +// Interrupt 431 <0=> Secure state <1=> Non-Secure state +// Interrupt 432 <0=> Secure state <1=> Non-Secure state +// Interrupt 433 <0=> Secure state <1=> Non-Secure state +// Interrupt 434 <0=> Secure state <1=> Non-Secure state +// Interrupt 435 <0=> Secure state <1=> Non-Secure state +// Interrupt 436 <0=> Secure state <1=> Non-Secure state +// Interrupt 437 <0=> Secure state <1=> Non-Secure state +// Interrupt 438 <0=> Secure state <1=> Non-Secure state +// Interrupt 439 <0=> Secure state <1=> Non-Secure state +// Interrupt 440 <0=> Secure state <1=> Non-Secure state +// Interrupt 441 <0=> Secure state <1=> Non-Secure state +// Interrupt 442 <0=> Secure state <1=> Non-Secure state +// Interrupt 443 <0=> Secure state <1=> Non-Secure state +// Interrupt 444 <0=> Secure state <1=> Non-Secure state +// Interrupt 445 <0=> Secure state <1=> Non-Secure state +// Interrupt 446 <0=> Secure state <1=> Non-Secure state +// Interrupt 447 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS13_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 14 (Interrupts 448..479) +*/ +#define NVIC_INIT_ITNS14 0 + +/* +// Interrupts 448..479 +// Interrupt 448 <0=> Secure state <1=> Non-Secure state +// Interrupt 449 <0=> Secure state <1=> Non-Secure state +// Interrupt 450 <0=> Secure state <1=> Non-Secure state +// Interrupt 451 <0=> Secure state <1=> Non-Secure state +// Interrupt 452 <0=> Secure state <1=> Non-Secure state +// Interrupt 453 <0=> Secure state <1=> Non-Secure state +// Interrupt 454 <0=> Secure state <1=> Non-Secure state +// Interrupt 455 <0=> Secure state <1=> Non-Secure state +// Interrupt 456 <0=> Secure state <1=> Non-Secure state +// Interrupt 457 <0=> Secure state <1=> Non-Secure state +// Interrupt 458 <0=> Secure state <1=> Non-Secure state +// Interrupt 459 <0=> Secure state <1=> Non-Secure state +// Interrupt 460 <0=> Secure state <1=> Non-Secure state +// Interrupt 461 <0=> Secure state <1=> Non-Secure state +// Interrupt 462 <0=> Secure state <1=> Non-Secure state +// Interrupt 463 <0=> Secure state <1=> Non-Secure state +// Interrupt 464 <0=> Secure state <1=> Non-Secure state +// Interrupt 465 <0=> Secure state <1=> Non-Secure state +// Interrupt 466 <0=> Secure state <1=> Non-Secure state +// Interrupt 467 <0=> Secure state <1=> Non-Secure state +// Interrupt 468 <0=> Secure state <1=> Non-Secure state +// Interrupt 469 <0=> Secure state <1=> Non-Secure state +// Interrupt 470 <0=> Secure state <1=> Non-Secure state +// Interrupt 471 <0=> Secure state <1=> Non-Secure state +// Interrupt 472 <0=> Secure state <1=> Non-Secure state +// Interrupt 473 <0=> Secure state <1=> Non-Secure state +// Interrupt 474 <0=> Secure state <1=> Non-Secure state +// Interrupt 475 <0=> Secure state <1=> Non-Secure state +// Interrupt 476 <0=> Secure state <1=> Non-Secure state +// Interrupt 477 <0=> Secure state <1=> Non-Secure state +// Interrupt 478 <0=> Secure state <1=> Non-Secure state +// Interrupt 479 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS14_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 15 (Interrupts 480..511) +*/ +#define NVIC_INIT_ITNS15 0 + +/* +// Interrupts 480..511 +// Interrupt 480 <0=> Secure state <1=> Non-Secure state +// Interrupt 481 <0=> Secure state <1=> Non-Secure state +// Interrupt 482 <0=> Secure state <1=> Non-Secure state +// Interrupt 483 <0=> Secure state <1=> Non-Secure state +// Interrupt 484 <0=> Secure state <1=> Non-Secure state +// Interrupt 485 <0=> Secure state <1=> Non-Secure state +// Interrupt 486 <0=> Secure state <1=> Non-Secure state +// Interrupt 487 <0=> Secure state <1=> Non-Secure state +// Interrupt 488 <0=> Secure state <1=> Non-Secure state +// Interrupt 489 <0=> Secure state <1=> Non-Secure state +// Interrupt 490 <0=> Secure state <1=> Non-Secure state +// Interrupt 491 <0=> Secure state <1=> Non-Secure state +// Interrupt 492 <0=> Secure state <1=> Non-Secure state +// Interrupt 493 <0=> Secure state <1=> Non-Secure state +// Interrupt 494 <0=> Secure state <1=> Non-Secure state +// Interrupt 495 <0=> Secure state <1=> Non-Secure state +// Interrupt 496 <0=> Secure state <1=> Non-Secure state +// Interrupt 497 <0=> Secure state <1=> Non-Secure state +// Interrupt 498 <0=> Secure state <1=> Non-Secure state +// Interrupt 499 <0=> Secure state <1=> Non-Secure state +// Interrupt 500 <0=> Secure state <1=> Non-Secure state +// Interrupt 501 <0=> Secure state <1=> Non-Secure state +// Interrupt 502 <0=> Secure state <1=> Non-Secure state +// Interrupt 503 <0=> Secure state <1=> Non-Secure state +// Interrupt 504 <0=> Secure state <1=> Non-Secure state +// Interrupt 505 <0=> Secure state <1=> Non-Secure state +// Interrupt 506 <0=> Secure state <1=> Non-Secure state +// Interrupt 507 <0=> Secure state <1=> Non-Secure state +// Interrupt 508 <0=> Secure state <1=> Non-Secure state +// Interrupt 509 <0=> Secure state <1=> Non-Secure state +// Interrupt 510 <0=> Secure state <1=> Non-Secure state +// Interrupt 511 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS15_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + + + +/* + max 128 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + + #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) + NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; + #endif + + #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) + NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; + #endif + + #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) + NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; + #endif + + #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) + NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; + #endif + + #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) + NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; + #endif + + #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) + NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; + #endif + + #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) + NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; + #endif + + #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) + NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; + #endif + + #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) + NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; + #endif + + #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) + NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; + #endif + + #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) + NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; + #endif + + /* repeat this for all possible ITNS elements */ + +} + +#endif /* PARTITION_ARMCM33_H */ diff --git a/ports/cortex_m33/ac5/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c b/ports/cortex_m33/ac5/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c new file mode 100644 index 00000000..5ee4322c --- /dev/null +++ b/ports/cortex_m33/ac5/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c @@ -0,0 +1,138 @@ +/****************************************************************************** + * @file startup_ARMCM33.c + * @brief CMSIS Core Device Startup File for Cortex-M33 Device + * @version V2.0.0 + * @date 20. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM33) + #include "ARMCM33.h" +#elif defined (ARMCM33_TZ) + #include "ARMCM33_TZ.h" +#elif defined (ARMCM33_DSP_FP) + #include "ARMCM33_DSP_FP.h" +#elif defined (ARMCM33_DSP_FP_TZ) + #include "ARMCM33_DSP_FP_TZ.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler Function Prototype + *----------------------------------------------------------------------------*/ +typedef void( *pFunc )( void ); + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern void __PROGRAM_START(void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Default_Handler(void) __NO_RETURN; +void Reset_Handler (void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const pFunc __VECTOR_TABLE[496]; + const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/ports/cortex_m33/ac5/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c b/ports/cortex_m33/ac5/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c new file mode 100644 index 00000000..17679234 --- /dev/null +++ b/ports/cortex_m33/ac5/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c @@ -0,0 +1,99 @@ +/**************************************************************************//** + * @file system_ARMCM33.c + * @brief CMSIS Device System Source File for + * ARMCM33 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM33) + #include "ARMCM33.h" +#elif defined (ARMCM33_TZ) + #include "ARMCM33_TZ.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM33.h" + #endif +#elif defined (ARMCM33_DSP_FP) + #include "ARMCM33_DSP_FP.h" +#elif defined (ARMCM33_DSP_FP_TZ) + #include "ARMCM33_DSP_FP_TZ.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM33.h" + #endif +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/ports/cortex_m33/ac5/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h b/ports/cortex_m33/ac5/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h new file mode 100644 index 00000000..78d1b429 --- /dev/null +++ b/ports/cortex_m33/ac5/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'demo_threadx_non-secure_zone' + * Target: 'FVP Simulation Model' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/ports/cortex_m33/ac5/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h b/ports/cortex_m33/ac5/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h new file mode 100644 index 00000000..1eb74752 --- /dev/null +++ b/ports/cortex_m33/ac5/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'ThreadX_Library' + * Target: 'ThreadX_Library_Project' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/ports/cortex_m33/ac5/example_build/demo_threadx_non-secure_zone/ThreadX_Demo.uvopt b/ports/cortex_m33/ac5/example_build/demo_threadx_non-secure_zone/ThreadX_Demo.uvopt new file mode 100644 index 00000000..7ec4b36b --- /dev/null +++ b/ports/cortex_m33/ac5/example_build/demo_threadx_non-secure_zone/ThreadX_Demo.uvopt @@ -0,0 +1,305 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + ThreadX_Demo + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 1 + 0 + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + -1 + + + + + + + + + + + + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0) + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(102=-1,-1,-1,-1,0)(103=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(163=-1,-1,-1,-1,0)(164=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)(152=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)(1013=-1,-1,-1,-1,0)(171=-1,-1,-1,-1,0)(172=-1,-1,-1,-1,0)(173=-1,-1,-1,-1,0)(1014=-1,-1,-1,-1,0)(1016=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T5F + + + 0 + UL2CM3 + -UV0289BJE -O14 -S0 -C0 -N00("ARM CoreSight JTAG-DP") -D00(3BA00477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_16 -FS00 -FL04000 + + + + + + 0 + 1 + thread_0_counter + + + 1 + 1 + thread_1_counter + + + 2 + 1 + thread_2_counter + + + 3 + 1 + thread_3_counter + + + 4 + 1 + thread_4_counter + + + 5 + 1 + thread_5_counter + + + 6 + 1 + _tx_thread_current_ptr + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Source Group + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + .\tx_initialize_low_level.s + tx_initialize_low_level.s + 0 + 0 + + + 1 + 2 + 1 + 1 + 0 + 0 + .\demo_threadx.c + demo_threadx.c + 0 + 0 + + 44 + 0 + 1 + + -1 + -1 + + + -1 + -1 + + + 56 + 12 + 1633 + 671 + + + + + + + Library_Group + 1 + 0 + 0 + 0 + + 2 + 3 + 4 + 0 + 0 + 0 + .\ThreadX_Library.lib + ThreadX_Library.lib + 0 + 0 + + + + diff --git a/ports/cortex_m33/ac5/example_build/demo_threadx_non-secure_zone/ThreadX_Demo.uvproj b/ports/cortex_m33/ac5/example_build/demo_threadx_non-secure_zone/ThreadX_Demo.uvproj new file mode 100644 index 00000000..5f5dcbdb --- /dev/null +++ b/ports/cortex_m33/ac5/example_build/demo_threadx_non-secure_zone/ThreadX_Demo.uvproj @@ -0,0 +1,556 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + ThreadX_Demo + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + Cortex-M4 FPU + ARM + CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 + + + + 5237 + + + + + + + + + + + + 0 + 0 + + + + Luminary\ + Luminary\ + + 0 + 0 + 0 + 0 + 1 + + .\ + threadx_demo + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DCM.DLL + -pCM4F + SARMCM3.DLL + + TCM.DLL + -pCM4F + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + + 0 + -1 + + + + + + + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 4096 + + 0 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + --first __tx_vectors --entry=__main + + + + + + + + Source Group + + + 0 + 1 + 1 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 0 + + + + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + tx_initialize_low_level.s + 2 + .\tx_initialize_low_level.s + + + 2 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 2 + 2 + 1 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + demo_threadx.c + 1 + .\demo_threadx.c + + + + + Library_Group + + + ThreadX_Library.lib + 4 + .\ThreadX_Library.lib + + + + + + + + diff --git a/ports/cortex_m33/ac5/example_build/demo_threadx_non-secure_zone/demo_threadx.c b/ports/cortex_m33/ac5/example_build/demo_threadx_non-secure_zone/demo_threadx.c new file mode 100644 index 00000000..3d4032a4 --- /dev/null +++ b/ports/cortex_m33/ac5/example_build/demo_threadx_non-secure_zone/demo_threadx.c @@ -0,0 +1,400 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. Please refer to Chapter 6 of the ThreadX User Guide for a complete + description of this demonstration. */ + +#include "tx_api.h" +#include "..\demo_secure_zone\interface.h" /* Interface to sample secure functions. */ + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +static TX_THREAD thread_0; +static TX_THREAD thread_1; +static TX_THREAD thread_2; +static TX_THREAD thread_3; +static TX_THREAD thread_4; +static TX_THREAD thread_5; +static TX_THREAD thread_6; +static TX_THREAD thread_7; +static TX_QUEUE queue_0; +static TX_SEMAPHORE semaphore_0; +static TX_MUTEX mutex_0; +static TX_EVENT_FLAGS_GROUP event_flags_0; +static TX_BYTE_POOL byte_pool_0; +static TX_BLOCK_POOL block_pool_0; + +/* Define byte pool memory. */ + +static UCHAR byte_pool_memory[DEMO_BYTE_POOL_SIZE]; + + +/* Define event buffer. */ + +#ifdef TX_ENABLE_EVENT_TRACE +UCHAR trace_buffer[0x10000]; +#endif + + +/* Define the counters used in the demo application... */ + +static ULONG thread_0_counter; +static ULONG thread_1_counter; +static ULONG thread_1_messages_sent; +static ULONG thread_2_counter; +static ULONG thread_2_messages_received; +static ULONG thread_3_counter; +static ULONG thread_4_counter; +static ULONG thread_5_counter; +static ULONG thread_6_counter; +static ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + +/* Define main entry point. */ + +int main() +{ + + /* Please refer to Chapter 6 of the ThreadX User Guide for a complete + description of this demonstration. */ + + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer; + + (VOID)first_unused_memory; /* unused parameter. */ + +#ifdef TX_ENABLE_EVENT_TRACE + tx_trace_enable(trace_buffer, sizeof(trace_buffer), 32); +#endif + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", byte_pool_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); + + tx_thread_secure_stack_allocate(&thread_0,256); + tx_thread_secure_stack_allocate(&thread_1,256); + tx_thread_secure_stack_allocate(&thread_2,256); + tx_thread_secure_stack_allocate(&thread_3,256); + tx_thread_secure_stack_allocate(&thread_4,256); + tx_thread_secure_stack_allocate(&thread_5,256); + tx_thread_secure_stack_allocate(&thread_6,256); + tx_thread_secure_stack_allocate(&thread_7,256); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ +UINT status; + + (VOID)thread_input; /* unused parameter. */ + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + (VOID)thread_input; /* unused parameter. */ + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + (VOID)thread_input; /* unused parameter. */ + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + (VOID)thread_input; /* unused parameter. */ + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_m33/ac5/example_build/demo_threadx_non-secure_zone/demo_threadx_non-secure_zone.uvoptx b/ports/cortex_m33/ac5/example_build/demo_threadx_non-secure_zone/demo_threadx_non-secure_zone.uvoptx new file mode 100644 index 00000000..c6f15929 --- /dev/null +++ b/ports/cortex_m33/ac5/example_build/demo_threadx_non-secure_zone/demo_threadx_non-secure_zone.uvoptx @@ -0,0 +1,359 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + FVP Simulation Model + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 15 + + + + + + + + + + ..\Debug.ini + BIN\DbgFMv8M.DLL + + + + 0 + PWSTATINFO + 200,50,700 + + + 0 + DLGTARM + (6010=636,564,1113,1160,0)(6018=1284,352,1473,701,0)(6019=1328,34,1517,370,0)(6008=-1,-1,-1,-1,0)(6009=1290,960,1584,1146,0)(6014=1111,129,1369,860,0)(6015=872,146,1130,768,0)(6003=-1,-1,-1,-1,0)(6000=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=150,186,829,544,0)(106=511,345,1277,659,0)(107=-1,-1,-1,-1,0) + + + 0 + DbgFMv8M + -I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMCM33_DSP_FP_TZ_config.txt" -MA + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FC1000 -FD20000000 + + + + + 0 + 0 + 251 + 1 +
2111470
+ 0 + 0 + 0 + 0 + 0 + 1 + <3>.\tx_initialize_low_level.S + + \\demo_threadx_non_secure_zone\tx_initialize_low_level.S\251 + + + + + 0 + 1 + thread_0_counter + + + 1 + 1 + thread_1_counter + + + 2 + 1 + thread_2_counter + + + 3 + 1 + thread_3_counter + + + 4 + 1 + thread_4_counter + + + 5 + 1 + thread_5_counter + + + 6 + 1 + thread_6_counter + + + 7 + 1 + thread_7_counter + + + + + 1 + 2 + 0x2001ffd8 + 0 + + + + + 2 + 2 + 0xE000ED28 + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 1 + 10000000 + + + + + + Non-secure Code + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + .\demo_threadx.c + demo_threadx.c + 0 + 0 + + + 1 + 2 + 4 + 0 + 0 + 0 + ..\ThreadX_Library.lib + ThreadX_Library.lib + 0 + 0 + + + + + CMSE Library + 1 + 0 + 0 + 0 + + 2 + 3 + 5 + 0 + 0 + 0 + ..\demo_secure_zone\interface.h + interface.h + 0 + 0 + + + 2 + 4 + 3 + 0 + 0 + 0 + ..\demo_secure_zone\Objects\demo_secure_zone_CMSE_Lib.o + demo_secure_zone_CMSE_Lib.o + 0 + 0 + + + + + ::CMSIS + 1 + 0 + 0 + 1 + + + + ::Device + 1 + 0 + 0 + 1 + + + diff --git a/ports/cortex_m33/ac5/example_build/demo_threadx_non-secure_zone/demo_threadx_non-secure_zone.uvprojx b/ports/cortex_m33/ac5/example_build/demo_threadx_non-secure_zone/demo_threadx_non-secure_zone.uvprojx new file mode 100644 index 00000000..f6bb1598 --- /dev/null +++ b/ports/cortex_m33/ac5/example_build/demo_threadx_non-secure_zone/demo_threadx_non-secure_zone.uvprojx @@ -0,0 +1,585 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + FVP Simulation Model + 0x4 + ARM-ADS + 6140000::V6.14::ARMCLANG + 1 + + + ARMCM33_DSP_FP_TZ + ARM + ARM.CMSIS.5.7.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ESEL ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM33_DSP_FP_TZ$Device\ARM\ARMCM33\Include\ARMCM33_DSP_FP_TZ.h + + + + + + + + + + $$Device:ARMCM33_DSP_FP_TZ$Device\ARM\SVD\ARMCM33.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + demo_threadx_non-secure_zone + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + -MPU + TCM.DLL + -pCM33 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 0 + -1 + + 1 + BIN\UL2V8M.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M33" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 1 + 1 + 16 + 1 + 1 + 0 + 0 + 4 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x200000 + + + 1 + 0x200000 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x20200000 + 0x20000 + + + + + + 1 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 3 + 1 + 1 + 1 + 0 + 0 + 0 + + -Wno-unused-function -Wno-visibility + + + ..\..\..\..\..\common\inc, ..\..\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 13 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\RTE\Device\ARMCM33_DSP_FP_TZ\ARMCM33_AC6.sct + + + + + + + + + + + Non-secure Code + + + demo_threadx.c + 1 + .\demo_threadx.c + + + ThreadX_Library.lib + 4 + ..\ThreadX_Library.lib + + + + + CMSE Library + + + interface.h + 5 + ..\demo_secure_zone\interface.h + + + demo_secure_zone_CMSE_Lib.o + 3 + ..\demo_secure_zone\Objects\demo_secure_zone_CMSE_Lib.o + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + RTE\Device\ARMCM33_DSP_FP\startup_ARMCM33.s + + + + + + RTE\Device\ARMCM33_DSP_FP\system_ARMCM33.c + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\ARMCM33_ac6.sct + + + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\partition_ARMCM33.h + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.c + + + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.s + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\system_ARMCM33.c + + + + + + + + RTE\Device\ARMCM33_TZ\partition_ARMCM33.h + + + + + + RTE\Device\ARMCM33_TZ\startup_ARMCM33.s + + + + + + RTE\Device\ARMCM33_TZ\system_ARMCM33.c + + + + + + RTE\Device\ARMv8MBL\partition_ARMv8MBL.h + + + + + + RTE\Device\ARMv8MBL\startup_ARMv8MBL.s + + + + + + RTE\Device\ARMv8MBL\system_ARMv8MBL.c + + + + + + RTE\Device\CMSDK_ARMv8MBL\RTE_Device.h + + + + + + RTE\Device\CMSDK_ARMv8MBL\partition_CMSDK_ARMv8MBL.h + + + + + + RTE\Device\CMSDK_ARMv8MBL\startup_CMSDK_ARMv8MBL.s + + + + + + RTE\Device\CMSDK_ARMv8MBL\system_CMSDK_ARMv8MBL.c + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/ports/cortex_m33/ac5/example_build/tx_initialize_low_level.S b/ports/cortex_m33/ac5/example_build/tx_initialize_low_level.S new file mode 100644 index 00000000..6ea775c6 --- /dev/null +++ b/ports/cortex_m33/ac5/example_build/tx_initialize_low_level.S @@ -0,0 +1,284 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + IMPORT _tx_thread_system_stack_ptr + IMPORT _tx_initialize_unused_memory + IMPORT _tx_thread_context_save + IMPORT _tx_thread_context_restore + IMPORT _tx_timer_interrupt + IMPORT __main + IMPORT |Image$$RW_RAM$$ZI$$Limit| + IMPORT __Vectors + IMPORT SystemInit + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_stack_error_handler +; +; +SYSTEM_CLOCK EQU 6000000 +SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1) +; +; +;/* Setup the stack and heap areas. */ +; +STACK_SIZE EQU 0x00000400 +HEAP_SIZE EQU 0x00000000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +StackMem + SPACE STACK_SIZE +__initial_sp + + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +HeapMem + SPACE HEAP_SIZE +__heap_limit + + + AREA ||.text||, CODE, READONLY + PRESERVE8 + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-M33/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + EXPORT _tx_initialize_low_level +_tx_initialize_low_level FUNCTION +; +; /* Disable interrupts during ThreadX initialization. */ +; + CPSID i +; +; /* Set base of available memory to end of non-initialised RAM area. */ +; + LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer + LDR r1, =|Image$$RW_RAM$$ZI$$Limit| ; Build first free address + ADD r1, r1, #4 ; + STR r1, [r0] ; Setup first unused memory pointer +; +; /* Setup Vector Table Offset Register. */ +; + MOV r0, #0xE000E000 ; Build address of NVIC registers + LDR r1, =__Vectors ; Pickup address of vector table + STR r1, [r0, #0xD08] ; Set vector table address +; +; /* Enable the cycle count register. */ +; +; LDR r0, =0xE0001000 ; Build address of DWT register +; LDR r1, [r0] ; Pickup the current value +; ORR r1, r1, #1 ; Set the CYCCNTENA bit +; STR r1, [r0] ; Enable the cycle count register +; +; /* Set system stack pointer from vector value. */ +; + LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer + LDR r1, =__Vectors ; Pickup address of vector table + LDR r1, [r1] ; Pickup reset stack pointer + STR r1, [r0] ; Save system stack pointer +; +; /* Configure SysTick. */ +; + MOV r0, #0xE000E000 ; Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] ; Setup SysTick Reload Value + MOV r1, #0x7 ; Build SysTick Control Enable Value + STR r1, [r0, #0x10] ; Setup SysTick Control +; +; /* Configure handler priorities. */ +; + LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] ; Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] ; Setup System Handlers 8-11 Priority Registers + ; Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] ; Setup System Handlers 12-15 Priority Registers + ; Note: PnSV must be lowest priority, which is 0xFF +; +; /* Return to caller. */ +; + BX lr + ENDFUNC +;} +; +; +;/* Define initial heap/stack routine for the ARM startup code. +; This routine will set the initial stack and heap locations. */ +; + EXPORT __user_initial_stackheap +__user_initial_stackheap FUNCTION + LDR r0, =HeapMem + LDR r1, =(StackMem + STACK_SIZE) + LDR r2, =(HeapMem + HEAP_SIZE) + LDR r3, =StackMem + BX lr + ENDFUNC +; +; +;/* Define shells for each of the unused vectors. */ +; + EXPORT __tx_BadHandler +__tx_BadHandler FUNCTION + B __tx_BadHandler + ENDFUNC + + EXPORT __tx_IntHandler +__tx_IntHandler FUNCTION +; VOID InterruptHandler (VOID) +; { + PUSH {r0, lr} ; Save LR (and dummy r0 to maintain stack alignment) + +; /* Do interrupt handler work here */ +; /* .... */ + + POP {r0, lr} + BX lr +; } + ENDFUNC + + + EXPORT __tx_SysTickHandler + EXPORT SysTick_Handler +SysTick_Handler FUNCTION +__tx_SysTickHandler +; VOID TimerInterruptHandler (VOID) +; { +; + PUSH {r0, lr} ; Save LR (and dummy r0 to maintain stack alignment) + BL _tx_timer_interrupt + POP {r0, lr} + BX lr +; } + ENDFUNC + + + EXPORT HardFault_Handler +HardFault_Handler FUNCTION + B HardFault_Handler + ENDFUNC + + + EXPORT UsageFault_Handler +UsageFault_Handler FUNCTION + CPSID i ; Disable interrupts + ; Check for stack limit fault + LDR r0, =0xE000ED28 ; CFSR address + LDR r1,[r0] ; Pick up CFSR + TST r1, #0x00100000 ; Check for Stack Overflow +_unhandled_usage_loop + BEQ _unhandled_usage_loop ; If not stack overflow then loop + + ; Handle stack overflow + STR r1, [r0] ; Clear CFSR flag(s) + + IF {TARGET_FPU_VFP} = {TRUE} + LDR r0, =0xE000EF34 ; Cleanup FPU context: Load FPCCR address + LDR r1, [r0] ; Load FPCCR + BIC r1, r1, #1 ; Clear the lazy preservation active bit + STR r1, [r0] ; Store the value + ENDIF + + MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address + LDR r0,[r0] ; Pick up current thread pointer + PUSH {r0,lr} ; Save LR (and r0 to maintain stack alignment) + BL _tx_thread_stack_error_handler ; Call ThreadX/user handler + POP {r0,lr} ; Restore LR and dummy reg + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + ; Call the thread exit function to indicate the thread is no longer executing. + PUSH {r0, lr} ; Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit ; Call the thread exit function + POP {r0, lr} ; Recover LR + ENDIF + + MOV r1, #0 ; Build NULL value + LDR r0, =_tx_thread_current_ptr ; Pickup address of current thread pointer + STR r1, [r0] ; Clear current thread pointer + + ; Return from UsageFault_Handler exception + LDR r0, =0xE000ED04 ; Load ICSR + LDR r1, =0x10000000 ; Set PENDSVSET bit + STR r1, [r0] ; Store ICSR + DSB ; Wait for memory access to complete + CPSIE i ; Enable interrupts + BX lr ; Return from exception + ENDFUNC + + + + EXPORT __tx_NMIHandler +__tx_NMIHandler FUNCTION + B __tx_NMIHandler + ENDFUNC + + + EXPORT __tx_DBGHandler +__tx_DBGHandler FUNCTION + B __tx_DBGHandler + ENDFUNC + + ALIGN + LTORG + END diff --git a/ports/cortex_m33/ac5/inc/tx_port.h b/ports/cortex_m33/ac5/inc/tx_port.h new file mode 100644 index 00000000..855e0491 --- /dev/null +++ b/ports/cortex_m33/ac5/inc/tx_port.h @@ -0,0 +1,547 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-M33/AC5 */ +/* 6.1 */ +/* */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + +/* Determine if the optional ThreadX user define file should be used. */ +#ifdef TX_INCLUDE_USER_DEFINE_FILE + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + +/* Define compiler library include files. */ + +#include +#include +#include +#include "ARMCM33_DSP_FP_TZ.h" /* For intrinsic functions. */ + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef unsigned long long ULONG64; +typedef short SHORT; +typedef unsigned short USHORT; + +/* Function prototypes for this port. */ +struct TX_THREAD_STRUCT; +UINT _txe_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *thread_ptr, ULONG stack_size); +UINT _txe_thread_secure_stack_free(struct TX_THREAD_STRUCT *thread_ptr); +UINT _tx_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *tx_thread, ULONG stack_size); +UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); + +/* This hardware has stack checking that we take advantage of - do NOT define. */ +#ifdef TX_ENABLE_STACK_CHECKING + #error "Do not define TX_ENABLE_STACK_CHECKING" +#endif + +/* If user does not want to terminate thread on stack overflow, + #define the TX_THREAD_NO_TERMINATE_STACK_ERROR symbol. + The thread will be rescheduled and continue to cause the exception. + It is suggested user code handle this by registering a notification with the + tx_thread_stack_error_notify function. */ +/*#define TX_THREAD_NO_TERMINATE_STACK_ERROR */ + +/* Define the system API mappings based on the error checking + selected by the user. Note: this section is only applicable to + application source code, hence the conditional that turns off this + stuff when the include file is processed by the ThreadX source. */ + +#ifndef TX_SOURCE_CODE + + +/* Determine if error checking is desired. If so, map API functions + to the appropriate error checking front-ends. Otherwise, map API + functions to the core functions that actually perform the work. + Note: error checking is enabled by default. */ + +#ifdef TX_DISABLE_ERROR_CHECKING + +/* Services without error checking. */ + +#define tx_thread_secure_stack_allocate _tx_thread_secure_stack_allocate +#define tx_thread_secure_stack_free _tx_thread_secure_stack_free + +#else + +/* Services with error checking. */ + +#define tx_thread_secure_stack_allocate _txe_thread_secure_stack_allocate +#define tx_thread_secure_stack_free _txe_thread_secure_stack_free + +#endif +#endif + + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX Cortex-M33 port. */ + +#define TX_INT_DISABLE 1 /* Disable interrupts */ +#define TX_INT_ENABLE 0 /* Enable interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) +#endif +#else +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif + +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_secure_stack_context; +#else +#define TX_THREAD_EXTENSION_2 +#endif +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) if(thread_ptr -> tx_thread_secure_stack_context){_tx_thread_secure_stack_free(thread_ptr);} +#else +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +/* Define the size of the secure stack for the timer thread and use the extension to allocate the secure stack. */ +#define TX_TIMER_THREAD_SECURE_STACK_SIZE 256 +#define TX_TIMER_INITIALIZE_EXTENSION(status) _tx_thread_secure_stack_allocate(&_tx_timer_thread, TX_TIMER_THREAD_SECURE_STACK_SIZE); +#endif + + +#ifndef TX_MISRA_ENABLE + +//register unsigned int _ipsr __asm ("MRS %[result], ipsr" : [result] "=r" (_ipsr) : ); +inline static unsigned int _get_ipsr(void); +inline static unsigned int _get_ipsr(void) +{ + unsigned int _ipsr; + __asm("MRS %[result], ipsr" : [result] "=r" (_ipsr) : ); + return _ipsr; +} + +#endif + + +#ifdef __ARM_PCS_VFP + +#ifdef TX_MISRA_ENABLE + +ULONG _tx_misra_control_get(void); +void _tx_misra_control_set(ULONG value); +ULONG _tx_misra_fpccr_get(void); +void _tx_misra_vfp_touch(void); + +#else + +#ifdef TX_SOURCE_CODE + +static unsigned int _get_control(void); +static unsigned int _get_control(void) +{ + unsigned int _control; + __asm("MRS %[result], control" : [result] "=r" (_control) : ); + return _control; +} + +static void _set_control(unsigned int _control); +static void _set_control(unsigned int _control) +{ + __asm("MSR control, %[input]" : : [input] "r" (_control)); +} + +#endif +#endif + +/* A completed thread falls into _thread_shell_entry and we can simply deactivate the FPU via CONTROL.FPCA + in order to ensure no lazy stacking will occur. */ + +#ifndef TX_MISRA_ENABLE + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _get_control(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _set_control(_tx_vfp_state);; \ + } +#else + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } + +#endif + +/* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. + If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + the lazy FPU save, then restore the CONTROL.FPCA state. */ + +#ifndef TX_MISRA_ENABLE + +void _tx_vfp_access(void); + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _get_control(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _set_control(_tx_vfp_state); \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = *((ULONG *) 0xE000EF34); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _get_control(); \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + _tx_vfp_access(); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = _get_control(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _set_control(_tx_vfp_state); \ + } \ + } \ + } \ + } +#else + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = _tx_misra_fpccr_get(); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + _tx_misra_vfp_touch(); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + } \ + } \ + } +#endif + +#else + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + +#endif + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define the get system state macro. */ + +#ifndef TX_THREAD_GET_SYSTEM_STATE +#ifndef TX_MISRA_ENABLE +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _get_ipsr()) +#else +ULONG _tx_misra_ipsr_get(VOID); +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get()) +#endif +#endif + + +/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value + indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h + for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always + zero after initialization for Cortex-M ports. */ + +#ifndef TX_THREAD_SYSTEM_RETURN_CHECK +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#endif + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +/* Initialize secure stacks for threads calling secure functions. */ +extern void _tx_thread_secure_stack_initialize(void); +#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION _tx_thread_secure_stack_initialize(); +#endif + +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to + prevent early scheduling on Cortex-M parts. */ + +#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); + +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifdef TX_DISABLE_INLINE + +UINT _tx_thread_interrupt_disable(VOID); +VOID _tx_thread_interrupt_restore(UINT previous_posture); + +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); + +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA unsigned int was_masked; +#define TX_DISABLE was_masked = __disable_irq(); +#define TX_RESTORE if (was_masked == 0) __enable_irq(); + +#define _tx_thread_system_return _tx_thread_system_return_inline + + +static void _tx_thread_system_return_inline(void) +{ +unsigned int was_masked; + + + /* Set PendSV to invoke ThreadX scheduler. */ + *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + if (_get_ipsr() == 0) + { + was_masked = __disable_irq(); + __enable_irq(); + if (was_masked != 0) + __disable_irq(); + } +} +#endif + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33/AC5 Version 6.1 *"; +#else +#ifdef TX_MISRA_ENABLE +extern CHAR _tx_version_id[100]; +#else +extern CHAR _tx_version_id[]; +#endif +#endif + +#endif diff --git a/ports/cortex_m33/ac5/inc/tx_secure_interface.h b/ports/cortex_m33/ac5/inc/tx_secure_interface.h new file mode 100644 index 00000000..6fa51319 --- /dev/null +++ b/ports/cortex_m33/ac5/inc/tx_secure_interface.h @@ -0,0 +1,60 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* tx_secure_interface.h Cortex-M33 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the ThreadX secure thread stack components, */ +/* including data types and external references. */ +/* It is assumed that tx_api.h and tx_port.h have already been */ +/* included. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_SECURE_INTERFACE_H +#define TX_SECURE_INTERFACE_H + +/* Define internal secure thread stack function prototypes. */ + +extern void _tx_thread_secure_stack_initialize(void); +extern UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size); +extern UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr); +extern void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr); +extern void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr); + +#endif diff --git a/ports/cortex_m33/ac5/readme_threadx.txt b/ports/cortex_m33/ac5/readme_threadx.txt new file mode 100644 index 00000000..291d070e --- /dev/null +++ b/ports/cortex_m33/ac5/readme_threadx.txt @@ -0,0 +1,214 @@ + Microsoft's Azure RTOS ThreadX for Cortex-M33 + + Using the AC5 Tools in Keil uVision + +1. Import the ThreadX Projects + +In order to build the ThreadX library and the ThreadX demonstration, first open +the AzureRTOS.uvmpw workspace (located in the "example_build" directory) +into Keil. + + +2. Building the ThreadX run-time Library + +Building the ThreadX library is easy; simply set the ThreadX_Library project +as active, then then build the library. You should now observe the compilation +and assembly of the ThreadX library. This project build produces the ThreadX +library file ThreadX_Library.lib. + + +3. Demonstration System + +The ThreadX demonstration is designed to execute under the Keil debugger on the +FVP_MPS2_Cortex-M33_MDK simulator. + +Building the demonstration is easy; simply select the "Batch Build" button. +You should now observe the compilation and assembly of the ThreadX demonstration of +both the demo_secure_zone and demo_threadx_non-secure_zone projects. +Then click the Start/Stop Debug Session button to start the simulator and begin debugging. +You are now ready to execute the ThreadX demonstration. + + +4. System Initialization + +The entry point in ThreadX for the Cortex-M33 using AC5 tools uses the standard AC5 +Cortex-M33 reset sequence. From the reset vector the C runtime will be initialized. + +The ThreadX tx_initialize_low_level.S file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. + +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input +parameter to your application definition function, tx_application_define. + + +5. Register Usage and Stack Frames + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have the same stack frame in the Cortex-M33 version of +ThreadX. The top of the suspended thread's stack is pointed to by +tx_thread_stack_ptr in the associated thread control block TX_THREAD. + +Non-FPU Stack Frame: + + Stack Offset Stack Contents + + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 r4 + 0x08 r5 + 0x0C r6 + 0x10 r7 + 0x14 r8 + 0x18 r9 + 0x1C r10 + 0x20 r11 + 0x24 r0 (Hardware stack starts here!!) + 0x28 r1 + 0x2C r2 + 0x30 r3 + 0x34 r12 + 0x38 lr + 0x3C pc + 0x40 xPSR + +FPU Stack Frame (only interrupted thread with FPU enabled): + + Stack Offset Stack Contents + + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 s0 + 0x08 s1 + 0x0C s2 + 0x10 s3 + 0x14 s4 + 0x18 s5 + 0x1C s6 + 0x20 s7 + 0x24 s8 + 0x28 s9 + 0x2C s10 + 0x30 s11 + 0x34 s12 + 0x38 s13 + 0x3C s14 + 0x40 s15 + 0x44 s16 + 0x48 s17 + 0x4C s18 + 0x50 s19 + 0x54 s20 + 0x58 s21 + 0x5C s22 + 0x60 s23 + 0x64 s24 + 0x68 s25 + 0x6C s26 + 0x70 s27 + 0x74 s28 + 0x78 s29 + 0x7C s30 + 0x80 s31 + 0x84 fpscr + 0x88 r4 + 0x8C r5 + 0x90 r6 + 0x94 r7 + 0x98 r8 + 0x9C r9 + 0xA0 r10 + 0xA4 r11 + 0xA8 r0 (Hardware stack starts here!!) + 0xAC r1 + 0xB0 r2 + 0xB4 r3 + 0xB8 r12 + 0xBC lr + 0xC0 pc + 0xC4 xPSR + + +6. Improving Performance + +To make ThreadX and the application(s) run faster, you can enable +all compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-M33 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +7.1 Vector Area + +The Cortex-M33 vectors start at the label __Vectors or similar. The application may modify +the vector area according to its needs. There is code in tx_initialize_low_level() that will +configure the vector base register. + + +7.2 Managed Interrupts + +ISRs can be written completely in C (or assembly language) without any calls to +_tx_thread_context_save or _tx_thread_context_restore. These ISRs are allowed access to the +ThreadX API that is available to ISRs. + +ISRs written in C will take the form (where "your_C_isr" is an entry in the vector table): + +void your_C_isr(void) +{ + + /* ISR processing goes here, including any needed function calls. */ +} + +ISRs written in assembly language will take the form: + + + .global your_assembly_isr + .thumb_func +your_assembly_isr: +; VOID your_assembly_isr(VOID) +; { + PUSH {r0, lr} +; +; /* Do interrupt handler work here */ +; /* BL */ + + POP {r0, lr} + BX lr +; } + +Note: the Cortex-M33 requires exception handlers to be thumb labels, this implies bit 0 set. +To accomplish this, the declaration of the label has to be preceded by the assembler directive +.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to +be inserted in the correct location in the interrupt vector table. This table is typically +located in either your runtime startup file or in the tx_initialize_low_level.S file. + + +8. FPU Support + +ThreadX for Cortex-M33 supports automatic ("lazy") VFP support, which means that applications threads +can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread +context. + + +9. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +09-30-2020 Initial ThreadX 6.1 version for Cortex-M33 using AC5 tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_m33/ac5/src/tx_thread_context_restore.s b/ports/cortex_m33/ac5/src/tx_thread_context_restore.s new file mode 100644 index 00000000..87b18f05 --- /dev/null +++ b/ports/cortex_m33/ac5/src/tx_thread_context_restore.s @@ -0,0 +1,92 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_exit + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-M33/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + EXPORT _tx_thread_context_restore +_tx_thread_context_restore FUNCTION + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + PUSH {r0, lr} ; Save return address + BL _tx_execution_isr_exit ; Call the ISR exit function + POP {r0, lr} ; Recover Save return address + ENDIF +; +; /* Return to interrupt processing. */ +; + BX lr +;} + ENDFUNC + ALIGN + LTORG + END + diff --git a/ports/cortex_m33/ac5/src/tx_thread_context_save.s b/ports/cortex_m33/ac5/src/tx_thread_context_save.s new file mode 100644 index 00000000..b90e611b --- /dev/null +++ b/ports/cortex_m33/ac5/src/tx_thread_context_save.s @@ -0,0 +1,91 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_enter + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-M33/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + EXPORT _tx_thread_context_save +_tx_thread_context_save FUNCTION + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {r0, lr} ; Save return address + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {r0, lr} ; Recover return address + ENDIF +; +; /* Return to interrupt processing. */ +; + BX lr +;} + ENDFUNC + ALIGN + LTORG + END + diff --git a/ports/cortex_m33/ac5/src/tx_thread_interrupt_control.s b/ports/cortex_m33/ac5/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..93fa6d05 --- /dev/null +++ b/ports/cortex_m33/ac5/src/tx_thread_interrupt_control.s @@ -0,0 +1,78 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-M33/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + EXPORT _tx_thread_interrupt_control +_tx_thread_interrupt_control FUNCTION +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r1, PRIMASK + MSR PRIMASK, r0 + MOV r0, r1 + BX lr +; +;} + ENDFUNC + END diff --git a/ports/cortex_m33/ac5/src/tx_thread_interrupt_disable.s b/ports/cortex_m33/ac5/src/tx_thread_interrupt_disable.s new file mode 100644 index 00000000..e5e8ec40 --- /dev/null +++ b/ports/cortex_m33/ac5/src/tx_thread_interrupt_disable.s @@ -0,0 +1,77 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-M33/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts and returning */ +;/* the previous interrupt lockout posture. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_disable(UINT new_posture) +;{ + EXPORT _tx_thread_interrupt_disable +_tx_thread_interrupt_disable FUNCTION +; +; /* Return current interrupt lockout posture. */ +; + MRS r0, PRIMASK + CPSID i + BX lr +; +;} + ENDFUNC + END diff --git a/ports/cortex_m33/ac5/src/tx_thread_interrupt_restore.s b/ports/cortex_m33/ac5/src/tx_thread_interrupt_restore.s new file mode 100644 index 00000000..9b83987c --- /dev/null +++ b/ports/cortex_m33/ac5/src/tx_thread_interrupt_restore.s @@ -0,0 +1,76 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-M33/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for restoring the previous */ +;/* interrupt lockout posture. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* previous_posture Previous interrupt posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_interrupt_restore(UINT new_posture) +;{ + EXPORT _tx_thread_interrupt_restore +_tx_thread_interrupt_restore FUNCTION +; +; /* Restore previous interrupt lockout posture. */ +; + MSR PRIMASK, r0 + BX lr +; +;} + ENDFUNC + END diff --git a/ports/cortex_m33/ac5/src/tx_thread_schedule.s b/ports/cortex_m33/ac5/src/tx_thread_schedule.s new file mode 100644 index 00000000..55393cab --- /dev/null +++ b/ports/cortex_m33/ac5/src/tx_thread_schedule.s @@ -0,0 +1,341 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_execute_ptr + IMPORT _tx_timer_time_slice + IMPORT _tx_thread_system_stack_ptr + IMPORT _tx_thread_preempt_disable + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_thread_enter + IMPORT _tx_execution_thread_exit + ENDIF + + IF :LNOT::DEF: TX_SINGLE_MODE_SECURE :LAND: :LNOT::DEF: TX_SINGLE_MODE_NON_SECURE + IMPORT _tx_thread_secure_stack_context_restore + IMPORT _tx_thread_secure_stack_context_save + IMPORT _tx_thread_secure_mode_stack_allocate + IMPORT _tx_thread_secure_mode_stack_free + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-M33/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + EXPORT _tx_thread_schedule +_tx_thread_schedule FUNCTION +; +; /* This function should only ever be called on Cortex-M +; from the first schedule request. Subsequent scheduling occurs +; from the PendSV handling routines below. */ +; +; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ +; + MOV r0, #0 ; Build value for TX_FALSE + LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag + STR r0, [r2, #0] ; Clear preempt disable flag +; +; /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */ +; + IF {TARGET_FPU_VFP} = {TRUE} + MRS r0, CONTROL ; Pickup current CONTROL register + BIC r0, r0, #4 ; Clear the FPCA bit + MSR CONTROL, r0 ; Setup new CONTROL register + ENDIF +; +; /* Enable the interrupts */ +; + CPSIE i +; +; /* Enter the scheduler for the first time. */ +; + MOV r0, #0x10000000 ; Load PENDSVSET bit + MOV r1, #0xE000E000 ; Load NVIC base + STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR + DSB ; Complete all memory accesses + ISB ; Flush pipeline +; +; /* Wait here for the PendSV to take place. */ +; +__tx_wait_here + B __tx_wait_here ; Wait for the PendSV to happen + ENDFUNC +;} +; +; /* Generic context switching PendSV handler. */ +; + EXPORT PendSV_Handler +PendSV_Handler FUNCTION +; +; /* Get current thread value and new thread pointer. */ +; +__tx_ts_handler + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + CPSID i ; Disable interrupts + PUSH {r0, lr} ; Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit ; Call the thread exit function + POP {r0, lr} ; Recover LR + CPSIE i ; Enable interrupts + ENDIF + MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address + MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address + MOV r3, #0 ; Build NULL value + LDR r1, [r0] ; Pickup current thread pointer +; +; /* Determine if there is a current thread to finish preserving. */ +; + CBZ r1, __tx_ts_new ; If NULL, skip preservation +; +; /* Recover PSP and preserve current thread context. */ +; + STR r3, [r0] ; Set _tx_thread_current_ptr to NULL + MRS r12, PSP ; Pickup PSP pointer (thread's stack pointer) + STMDB r12!, {r4-r11} ; Save its remaining registers + IF {TARGET_FPU_VFP} = {TRUE} + TST LR, #0x10 ; Determine if the VFP extended frame is present + BNE _skip_vfp_save + VSTMDB r12!,{s16-s31} ; Yes, save additional VFP registers +_skip_vfp_save + ENDIF + MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable + STMDB r12!, {LR} ; Save LR on the stack + STR r12, [r1, #8] ; Save the thread stack pointer + + IF :LNOT::DEF: TX_SINGLE_MODE_SECURE :LAND: :LNOT::DEF: TX_SINGLE_MODE_NON_SECURE + ; Save secure context + LDR r5, [r1,#0x90] ; Load secure stack index + CBZ r5, _skip_secure_save ; Skip save if there is no secure context + PUSH {r0,r1,r2,r3} ; Save scratch registers + MOV r0, r1 ; Move thread ptr to r0 + BL _tx_thread_secure_stack_context_save ; Save secure stack + POP {r0,r1,r2,r3} ; Restore secure registers +_skip_secure_save + ENDIF +; +; /* Determine if time-slice is active. If it isn't, skip time handling processing. */ +; + LDR r5, [r4] ; Pickup current time-slice + CBZ r5, __tx_ts_new ; If not active, skip processing +; +; /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ +; + STR r5, [r1, #24] ; Save current time-slice +; +; /* Clear the global time-slice. */ +; + STR r3, [r4] ; Clear time-slice +; +; /* Executing thread is now completely preserved!!! */ +; +__tx_ts_new +; +; /* Now we are looking for a new thread to execute! */ +; + CPSID i ; Disable interrupts + LDR r1, [r2] ; Is there another thread ready to execute? + CBZ r1, __tx_ts_wait ; No, skip to the wait processing +; +; /* Yes, another thread is ready for else, make the current thread the new thread. */ +; + STR r1, [r0] ; Setup the current thread pointer to the new thread + CPSIE i ; Enable interrupts +; +; /* Increment the thread run count. */ +; +__tx_ts_restore + LDR r7, [r1, #4] ; Pickup the current thread run count + MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable + LDR r5, [r1, #24] ; Pickup thread's current time-slice + ADD r7, r7, #1 ; Increment the thread run count + STR r7, [r1, #4] ; Store the new run count +; +; /* Setup global time-slice with thread's current time-slice. */ +; + STR r5, [r4] ; Setup global time-slice + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + PUSH {r0, r1} ; Save r0/r1 + BL _tx_execution_thread_enter ; Call the thread execution enter function + POP {r0, r1} ; Recover r0/r1 + ENDIF + + IF :LNOT::DEF: TX_SINGLE_MODE_SECURE :LAND: :LNOT::DEF: TX_SINGLE_MODE_NON_SECURE + ; Restore secure context + LDR r0, [r1,#0x90] ; Load secure stack index + CBZ r0, _skip_secure_restore ; Skip restore if there is no secure context + PUSH {r0,r1} ; Save r1 (and dummy r0) + MOV r0, r1 ; Move thread ptr to r0 + BL _tx_thread_secure_stack_context_restore ; Restore secure stack + POP {r0,r1} ; Restore r1 (and dummy r0) +_skip_secure_restore + ENDIF + +; +; /* Restore the thread context and PSP. */ +; + LDR r12, [r1, #12] ; Get stack start + MSR PSPLIM, r12 ; Set stack limit + LDR r12, [r1, #8] ; Pickup thread's stack pointer + LDMIA r12!, {LR} ; Pickup LR + IF {TARGET_FPU_VFP} = {TRUE} + TST LR, #0x10 ; Determine if the VFP extended frame is present + BNE _skip_vfp_restore ; If not, skip VFP restore + VLDMIA r12!, {s16-s31} ; Yes, restore additional VFP registers +_skip_vfp_restore + ENDIF + LDMIA r12!, {r4-r11} ; Recover thread's registers + MSR PSP, r12 ; Setup the thread's stack pointer +; +; /* Return to thread. */ +; + BX lr ; Return to thread! +; +; /* The following is the idle wait processing... in this case, no threads are ready for execution and the +; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +; are disabled to allow use of WFI for waiting for a thread to arrive. */ +; +__tx_ts_wait + CPSID i ; Disable interrupts + LDR r1, [r2] ; Pickup the next thread to execute pointer + STR r1, [r0] ; Store it in the current pointer + CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready! + IF :DEF:TX_ENABLE_WFI + DSB ; Ensure no outstanding memory transactions + WFI ; Wait for interrupt + ISB ; Ensure pipeline is flushed + ENDIF + CPSIE i ; Enable interrupts + B __tx_ts_wait ; Loop to continue waiting +; +; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +; already in the handler! */ +; +__tx_ts_ready + MOV r7, #0x08000000 ; Build clear PendSV value + MOV r8, #0xE000E000 ; Build base NVIC address + STR r7, [r8, #0xD04] ; Clear any PendSV +; +; /* Re-enable interrupts and restore new thread. */ +; + CPSIE i ; Enable interrupts + B __tx_ts_restore ; Restore the thread + ENDFUNC + + + + IF :LNOT::DEF: TX_SINGLE_MODE_SECURE :LAND: :LNOT::DEF: TX_SINGLE_MODE_NON_SECURE + ; SVC_Handler is not needed when ThreadX is running in single mode. + EXPORT SVC_Handler +SVC_Handler FUNCTION + TST lr, #0x04 ; Determine return stack from EXC_RETURN bit 2 + ITE EQ + MRSEQ r0, MSP ; Get MSP if return stack is MSP + MRSNE r0, PSP ; Get PSP if return stack is PSP + + LDR r1, [r0,#24] ; Load saved PC from stack + LDRB r1, [r1,#-2] ; Load SVC number + + CMP r1, #1 ; Is it a secure stack allocate request? + BEQ _tx_svc_secure_alloc ; Yes, go there + + CMP r1, #2 ; Is it a secure stack free request? + BEQ _tx_svc_secure_free ; Yes, go there + + ; Unknown SVC argument - just return + BX lr + +_tx_svc_secure_alloc + PUSH {r0,lr} ; Save SP and EXC_RETURN + LDM r0, {r0-r3} ; Load function parameters from stack + BL _tx_thread_secure_mode_stack_allocate + POP {r12,lr} ; Restore SP and EXC_RETURN + STR r0,[r12] ; Store function return value + BX lr +_tx_svc_secure_free + PUSH {r0,lr} ; Save SP and EXC_RETURN + LDM r0, {r0-r3} ; Load function parameters from stack + BL _tx_thread_secure_mode_stack_free + POP {r12,lr} ; Restore SP and EXC_RETURN + STR r0,[r12] ; Store function return value + BX lr + ENDFUNC + ENDIF ; End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE + + + EXPORT _tx_vfp_access +_tx_vfp_access FUNCTION + VMOV.F32 s0, s0 ; Simply access the VFP + BX lr ; Return to caller + ENDFUNC + + ALIGN + LTORG + END diff --git a/ports/cortex_m33/ac5/src/tx_thread_secure_stack.c b/ports/cortex_m33/ac5/src/tx_thread_secure_stack.c new file mode 100644 index 00000000..bcd204f1 --- /dev/null +++ b/ports/cortex_m33/ac5/src/tx_thread_secure_stack.c @@ -0,0 +1,464 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +#include "tx_api.h" + +/* If TX_SINGLE_MODE_SECURE or TX_SINGLE_MODE_NON_SECURE is defined, + no secure stack functionality is needed. */ +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + +#define TX_SOURCE_CODE + +#include "ARMCM33_DSP_FP_TZ.h" /* For intrinsic functions. */ +#include "tx_secure_interface.h" /* Interface for NS code. */ + +/* Minimum size of secure stack. */ +#ifndef TX_THREAD_SECURE_STACK_MINIMUM +#define TX_THREAD_SECURE_STACK_MINIMUM 256 +#endif +/* Maximum size of secure stack. */ +#ifndef TX_THREAD_SECURE_STACK_MAXIMUM +#define TX_THREAD_SECURE_STACK_MAXIMUM 1024 +#endif + +/* Secure stack info struct to hold stack start, stack limit, + current stack pointer, and pointer to owning thread. + This will be allocated for each thread with a secure stack. */ +typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT +{ + VOID *tx_thread_secure_stack_ptr; /* Thread's secure stack current pointer */ + VOID *tx_thread_secure_stack_start; /* Thread's secure stack start address */ + VOID *tx_thread_secure_stack_limit; /* Thread's secure stack limit */ + TX_THREAD *tx_thread_ptr; /* Keep track of thread for error handling */ +} TX_THREAD_SECURE_STACK_INFO; + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_initialize Cortex-M33/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes secure mode to use PSP stack. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __get_CONTROL Intrinsic to get CONTROL */ +/* __set_CONTROL Intrinsic to set CONTROL */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +void _tx_thread_secure_stack_initialize(void) +{ + + /* Set secure mode to use PSP. */ + __set_CONTROL(__get_CONTROL() | 2); + + /* Set process stack pointer and stack limit to 0 to throw exception when a thread + without a secure stack calls a secure function that tries to use secure stack. */ + __set_PSPLIM(0); + __set_PSP(0); + + return; +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_mode_stack_allocate Cortex-M33/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function allocates a thread's secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* stack_size Size of stack to allocates */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_SIZE_ERROR Invalid stack size */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* calloc Compiler's calloc function */ +/* malloc Compiler's malloc function */ +/* free Compiler's free() function */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* __TZ_get_PSPLIM_NS Intrinsic to get NS PSP */ +/* */ +/* CALLED BY */ +/* */ +/* SVC Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +{ +UINT status; +TX_THREAD_SECURE_STACK_INFO *info_ptr; +UCHAR *stack_mem; + + status = TX_SUCCESS; + + /* Make sure function is called from interrupt (threads should not call). */ + if (__get_IPSR() == 0) + { + status = TX_CALLER_ERROR; + } + else if (stack_size < TX_THREAD_SECURE_STACK_MINIMUM || stack_size > TX_THREAD_SECURE_STACK_MAXIMUM) + { + status = TX_SIZE_ERROR; + } + + /* Check if thread already has secure stack allocated. */ + else if (thread_ptr -> tx_thread_secure_stack_context != 0) + { + status = TX_THREAD_ERROR; + } + + else + { + /* Allocate space for secure stack info. */ + info_ptr = calloc(1, sizeof(TX_THREAD_SECURE_STACK_INFO)); + + if(info_ptr != TX_NULL) + { + /* If stack info allocated, allocate a stack. */ + stack_mem = malloc(stack_size); + + if(stack_mem != TX_NULL) + { + /* Secure stack has been allocated, save in the stack info struct. */ + info_ptr -> tx_thread_secure_stack_limit = stack_mem; + info_ptr -> tx_thread_secure_stack_start = stack_mem + stack_size; + info_ptr -> tx_thread_secure_stack_ptr = info_ptr -> tx_thread_secure_stack_start; + info_ptr -> tx_thread_ptr = thread_ptr; + + /* Save info pointer in thread. */ + thread_ptr -> tx_thread_secure_stack_context = info_ptr; + + /* Check if this thread is running by looking at its stack start and PSPLIM_NS */ + if(((ULONG) thread_ptr -> tx_thread_stack_start & 0xFFFFFFF8) == __TZ_get_PSPLIM_NS()) + { + /* If this thread is running, set Secure PSP and PSPLIM. */ + __set_PSPLIM((ULONG)(info_ptr -> tx_thread_secure_stack_limit)); + __set_PSP((ULONG)(info_ptr -> tx_thread_secure_stack_ptr)); + } + } + + else + { + /* Stack not allocated, free the info struct. */ + free(info_ptr); + status = TX_NO_MEMORY; + } + } + + else + { + status = TX_NO_MEMORY; + } + } + + return(status); +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_mode_stack_free Cortex-M33/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function frees a thread's secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* free Compiler's free() function */ +/* */ +/* CALLED BY */ +/* */ +/* SVC Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr) +{ +UINT status; +TX_THREAD_SECURE_STACK_INFO *info_ptr; + + status = TX_SUCCESS; + + /* Pickup stack info from thread. */ + info_ptr = thread_ptr -> tx_thread_secure_stack_context; + + /* Make sure function is called from interrupt (threads should not call). */ + if (__get_IPSR() == 0) + { + status = TX_CALLER_ERROR; + } + + /* Check that this secure context is for this thread. */ + else if (info_ptr -> tx_thread_ptr != thread_ptr) + { + status = TX_THREAD_ERROR; + } + + else + { + + /* Free secure stack. */ + free(info_ptr -> tx_thread_secure_stack_limit); + + /* Free info struct. */ + free(info_ptr); + + /* Clear secure context from thread. */ + thread_ptr -> tx_thread_secure_stack_context = 0; + } + + return(status); +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_context_save Cortex-M33/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves context of the secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* __get_PSP Intrinsic to get PSP */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* */ +/* CALLED BY */ +/* */ +/* PendSV Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr) +{ +TX_THREAD_SECURE_STACK_INFO *info_ptr; +ULONG sp; + + /* This function should be called from scheduler only. */ + if (__get_IPSR() == 0) + { + return; + } + + /* Pickup the secure context pointer. */ + info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); + + /* Check that this secure context is for this thread. */ + if (info_ptr -> tx_thread_ptr != thread_ptr) + { + return; + } + + /* Check that stack pointer is in range */ + sp = __get_PSP(); + if ((sp < (ULONG)info_ptr -> tx_thread_secure_stack_limit) || + (sp > (ULONG)info_ptr -> tx_thread_secure_stack_start)) + { + return; + } + + /* Save stack pointer. */ + *(ULONG *) info_ptr -> tx_thread_secure_stack_ptr = sp; + + /* Set process stack pointer and stack limit to 0 to throw exception when a thread + without a secure stack calls a secure function that tries to use secure stack. */ + __set_PSPLIM(0); + __set_PSP(0); + + return; +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_context_restore Cortex-M33/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores context of the secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* */ +/* CALLED BY */ +/* */ +/* PendSV Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr) +{ +TX_THREAD_SECURE_STACK_INFO *info_ptr; + + /* This function should be called from scheduler only. */ + if (__get_IPSR() == 0) + { + return; + } + + /* Pickup the secure context pointer. */ + info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); + + /* Check that this secure context is for this thread. */ + if (info_ptr -> tx_thread_ptr != thread_ptr) + { + return; + } + + /* Set stack pointer and limit. */ + __set_PSPLIM((ULONG)info_ptr -> tx_thread_secure_stack_limit); + __set_PSP ((ULONG)info_ptr -> tx_thread_secure_stack_ptr); + + return; +} + +#endif diff --git a/ports/cortex_m33/ac5/src/tx_thread_secure_stack_allocate.s b/ports/cortex_m33/ac5/src/tx_thread_secure_stack_allocate.s new file mode 100644 index 00000000..f516bcd4 --- /dev/null +++ b/ports/cortex_m33/ac5/src/tx_thread_secure_stack_allocate.s @@ -0,0 +1,83 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_secure_stack_allocate Cortex-M33/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function enters the SVC handler to allocate a secure stack. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Thread control block pointer */ +;/* stack_size Size of secure stack to */ +;/* allocate */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* status Actual completion status */ +;/* */ +;/* CALLS */ +;/* */ +;/* SVC 1 */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +;{ + EXPORT _tx_thread_secure_stack_allocate +_tx_thread_secure_stack_allocate FUNCTION + IF :LNOT::DEF: TX_SINGLE_MODE_SECURE :LAND: :LNOT::DEF: TX_SINGLE_MODE_NON_SECURE + MRS r3, PRIMASK ; Save interrupt mask + CPSIE i ; Enable interrupts for SVC call + SVC 1 + CMP r3, #0 ; If interrupts enabled, just return + BEQ _alloc_return_interrupt_enabled + CPSID i ; Otherwise, disable interrupts + ELSE + MOV32 r0, #0xFF ; Feature not enabled + ENDIF +_alloc_return_interrupt_enabled + BX lr + ENDFUNC + + END diff --git a/ports/cortex_m33/ac5/src/tx_thread_secure_stack_free.s b/ports/cortex_m33/ac5/src/tx_thread_secure_stack_free.s new file mode 100644 index 00000000..b0dc2312 --- /dev/null +++ b/ports/cortex_m33/ac5/src/tx_thread_secure_stack_free.s @@ -0,0 +1,81 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_secure_stack_free Cortex-M33/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function enters the SVC handler to free a secure stack. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Thread control block pointer */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* status Actual completion status */ +;/* */ +;/* CALLS */ +;/* */ +;/* SVC 2 */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) +;{ + EXPORT _tx_thread_secure_stack_free +_tx_thread_secure_stack_free FUNCTION + IF :LNOT::DEF: TX_SINGLE_MODE_SECURE :LAND: :LNOT::DEF: TX_SINGLE_MODE_NON_SECURE + MRS r3, PRIMASK ; Save interrupt mask + CPSIE i ; Enable interrupts for SVC call + SVC 2 + CMP r3, #0 ; If interrupts enabled, just return + BEQ _free_return_interrupt_enabled + CPSID i ; Otherwise, disable interrupts + ELSE + MOV32 r0, #0xFF ; Feature not enabled + ENDIF +_free_return_interrupt_enabled + BX lr + ENDFUNC + END + \ No newline at end of file diff --git a/ports/cortex_m33/ac5/src/tx_thread_stack_build.s b/ports/cortex_m33/ac5/src/tx_thread_stack_build.s new file mode 100644 index 00000000..15eee502 --- /dev/null +++ b/ports/cortex_m33/ac5/src/tx_thread_stack_build.s @@ -0,0 +1,139 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-M33/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + EXPORT _tx_thread_stack_build +_tx_thread_stack_build FUNCTION +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-M33 should look like the following after it is built: +; +; Stack Top: +; LR Interrupted LR (LR at time of PENDSV) +; r4 Initial value for r4 +; r5 Initial value for r5 +; r6 Initial value for r6 +; r7 Initial value for r7 +; r8 Initial value for r8 +; r9 Initial value for r9 +; r10 Initial value for r10 +; r11 Initial value for r11 +; r0 Initial value for r0 (Hardware stack starts here!!) +; r1 Initial value for r1 +; r2 Initial value for r2 +; r3 Initial value for r3 +; r12 Initial value for r12 +; lr Initial value for lr +; pc Initial value for pc +; xPSR Initial value for xPSR +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #0x7 ; Align frame for 8-byte alignment + SUB r2, r2, #68 ; Subtract frame size + IF :DEF: TX_SINGLE_MODE_SECURE + LDR r3, =0xFFFFFFFD ; Build initial LR value for secure mode + ELSE + LDR r3, =0xFFFFFFBC ; Build initial LR value to return to non-secure PSP + ENDIF + STR r3, [r2, #0] ; Save on the stack +; +; /* Actually build the stack frame. */ +; + MOV r3, #0 ; Build initial register value + STR r3, [r2, #4] ; Store initial r4 + STR r3, [r2, #8] ; Store initial r5 + STR r3, [r2, #12] ; Store initial r6 + STR r3, [r2, #16] ; Store initial r7 + STR r3, [r2, #20] ; Store initial r8 + STR r3, [r2, #24] ; Store initial r9 + STR r3, [r2, #28] ; Store initial r10 + STR r3, [r2, #32] ; Store initial r11 +; +; /* Hardware stack follows. */ +; + STR r3, [r2, #36] ; Store initial r0 + STR r3, [r2, #40] ; Store initial r1 + STR r3, [r2, #44] ; Store initial r2 + STR r3, [r2, #48] ; Store initial r3 + STR r3, [r2, #52] ; Store initial r12 + MOV r3, #0xFFFFFFFF ; Poison EXC_RETURN value + STR r3, [r2, #56] ; Store initial lr + STR r1, [r2, #60] ; Store initial pc + MOV r3, #0x01000000 ; Only T-bit need be set + STR r3, [r2, #64] ; Store initial xPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block + BX lr ; Return to caller +;} + ENDFUNC + END + diff --git a/ports/cortex_m33/ac5/src/tx_thread_stack_error_handler.c b/ports/cortex_m33/ac5/src/tx_thread_stack_error_handler.c new file mode 100644 index 00000000..5c643784 --- /dev/null +++ b/ports/cortex_m33/ac5/src/tx_thread_stack_error_handler.c @@ -0,0 +1,93 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + +/* Define the global function pointer for stack error handling. If a stack error is + detected and the application has registered a stack error handler, it will be + called via this function pointer. */ + +VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_error_handler Cortex-M33 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes stack errors detected during run-time. */ +/* */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_terminate */ +/* _tx_thread_application_stack_error_handler */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX internal code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) +{ + #ifndef TX_THREAD_NO_TERMINATE_STACK_ERROR + /* Is there a thread? */ + if (thread_ptr) + { + /* Terminate the current thread. */ + _tx_thread_terminate(_tx_thread_current_ptr); + } + #endif + + /* Determine if the application has registered an error handler. */ + if (_tx_thread_application_stack_error_handler != TX_NULL) + { + /* Yes, an error handler is present, simply call the application error handler. */ + (_tx_thread_application_stack_error_handler)(thread_ptr); + } +} diff --git a/ports/cortex_m33/ac5/src/tx_thread_stack_error_notify.c b/ports/cortex_m33/ac5/src/tx_thread_stack_error_notify.c new file mode 100644 index 00000000..0ad24a46 --- /dev/null +++ b/ports/cortex_m33/ac5/src/tx_thread_stack_error_notify.c @@ -0,0 +1,96 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_trace.h" + +extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_error_notify Cortex-M33 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application stack error handler. If */ +/* ThreadX detects a stack error, this application handler is called. */ +/* */ +/* */ +/* INPUT */ +/* */ +/* stack_error_handler Pointer to stack error */ +/* handler, TX_NULL to disable */ +/* */ +/* OUTPUT */ +/* */ +/* status Service return status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr)) +{ + +TX_INTERRUPT_SAVE_AREA + + /* Disable interrupts. */ + TX_DISABLE + + /* Make entry in event log. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_STACK_ERROR_NOTIFY, 0, 0, 0, 0, TX_TRACE_THREAD_EVENTS) + + /* Make entry in event log. */ + TX_EL_THREAD_STACK_ERROR_NOTIFY_INSERT + + /* Setup global thread stack error handler. */ + _tx_thread_application_stack_error_handler = stack_error_handler; + + /* Restore interrupts. */ + TX_RESTORE + + /* Return success to caller. */ + return(TX_SUCCESS); +} diff --git a/ports/cortex_m33/ac5/src/tx_thread_system_return.s b/ports/cortex_m33/ac5/src/tx_thread_system_return.s new file mode 100644 index 00000000..b29de463 --- /dev/null +++ b/ports/cortex_m33/ac5/src/tx_thread_system_return.s @@ -0,0 +1,87 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-M33/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + EXPORT _tx_thread_system_return +_tx_thread_system_return FUNCTION +; +; /* Return to real scheduler via PendSV. Note that this routine is often +; replaced with in-line assembly in tx_port.h to improved performance. */ +; + MOV r0, #0x10000000 ; Load PENDSVSET bit + MOV r1, #0xE000E000 ; Load NVIC base + STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR + MRS r0, IPSR ; Pickup IPSR + CMP r0, #0 ; Is it a thread returning? + BNE _isr_context ; If ISR, skip interrupt enable + MRS r1, PRIMASK ; Thread context returning, pickup PRIMASK + CPSIE i ; Enable interrupts + MSR PRIMASK, r1 ; Restore original interrupt posture +_isr_context + BX lr ; Return to caller +;} + ENDFUNC + END diff --git a/ports/cortex_m33/ac5/src/tx_timer_interrupt.s b/ports/cortex_m33/ac5/src/tx_timer_interrupt.s new file mode 100644 index 00000000..7e2ce1a7 --- /dev/null +++ b/ports/cortex_m33/ac5/src/tx_timer_interrupt.s @@ -0,0 +1,260 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + IMPORT _tx_timer_time_slice + IMPORT _tx_timer_system_clock + IMPORT _tx_timer_current_ptr + IMPORT _tx_timer_list_start + IMPORT _tx_timer_list_end + IMPORT _tx_timer_expired_time_slice + IMPORT _tx_timer_expired + IMPORT _tx_thread_time_slice + IMPORT _tx_timer_expiration_process + IMPORT _tx_thread_preempt_disable + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_execute_ptr +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-M33/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* the expiration functions are called. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + EXPORT _tx_timer_interrupt +_tx_timer_interrupt FUNCTION +; +; /* Upon entry to this routine, it is assumed that the compiler scratch registers are available +; for use. */ +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + MOV32 r1, _tx_timer_system_clock ; Pickup address of system clock + LDR r0, [r1, #0] ; Pickup system clock + ADD r0, r0, #1 ; Increment system clock + STR r0, [r1, #0] ; Store new system clock +; +; /* Test for time-slice expiration. */ +; if (_tx_timer_time_slice) +; { +; + MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice + LDR r2, [r3, #0] ; Pickup time-slice + CBZ r2, __tx_timer_no_time_slice ; Is it non-active? + ; Yes, skip time-slice processing +; +; /* Decrement the time_slice. */ +; _tx_timer_time_slice--; +; + SUB r2, r2, #1 ; Decrement the time-slice + STR r2, [r3, #0] ; Store new time-slice value +; +; /* Check for expiration. */ +; if (__tx_timer_time_slice == 0) +; + CBNZ r2, __tx_timer_no_time_slice ; Has it expired? +; +; /* Set the time-slice expired flag. */ +; _tx_timer_expired_time_slice = TX_TRUE; +; + MOV32 r3, _tx_timer_expired_time_slice ; Pickup address of expired flag + MOV r0, #1 ; Build expired value + STR r0, [r3, #0] ; Set time-slice expiration flag +; +; } +; +__tx_timer_no_time_slice +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + MOV32 r1, _tx_timer_current_ptr ; Pickup current timer pointer address + LDR r0, [r1, #0] ; Pickup current timer + LDR r2, [r0, #0] ; Pickup timer list entry + CBZ r2, __tx_timer_no_timer ; Is there anything in the list? + ; No, just increment the timer +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + MOV32 r3, _tx_timer_expired ; Pickup expiration flag address + MOV r2, #1 ; Build expired value + STR r2, [r3, #0] ; Set expired flag + B __tx_timer_done ; Finished timer processing +; +; } +; else +; { +__tx_timer_no_timer +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ADD r0, r0, #4 ; Move to next timer +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + MOV32 r3, _tx_timer_list_end ; Pickup addr of timer list end + LDR r2, [r3, #0] ; Pickup list end + CMP r0, r2 ; Are we at list end? + BNE __tx_timer_skip_wrap ; No, skip wrap-around logic +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + MOV32 r3, _tx_timer_list_start ; Pickup addr of timer list start + LDR r0, [r3, #0] ; Set current pointer to list start +; +__tx_timer_skip_wrap +; + STR r0, [r1, #0] ; Store new current timer pointer +; } +; +__tx_timer_done +; +; +; /* See if anything has expired. */ +; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +; { +; + MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of expired flag + LDR r2, [r3, #0] ; Pickup time-slice expired flag + CBNZ r2, __tx_something_expired ; Did a time-slice expire? + ; If non-zero, time-slice expired + MOV32 r1, _tx_timer_expired ; Pickup addr of other expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CBZ r0, __tx_timer_nothing_expired ; Did a timer expire? + ; No, nothing expired +; +__tx_something_expired +; +; + STMDB sp!, {r0, lr} ; Save the lr register on the stack + ; and save r0 just to keep 8-byte alignment +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + MOV32 r1, _tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CBZ r0, __tx_timer_dont_activate ; Check for timer expiration + ; If not set, skip timer activation +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + BL _tx_timer_expiration_process ; Call the timer expiration handling routine +; +; } +__tx_timer_dont_activate +; +; /* Did time slice expire? */ +; if (_tx_timer_expired_time_slice) +; { +; + MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r2, [r3, #0] ; Pickup the actual flag + CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set + ; No, skip time-slice processing +; +; /* Time slice interrupted thread. */ +; _tx_thread_time_slice(); + + BL _tx_thread_time_slice ; Call time-slice processing + MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag + LDR r1, [r0] ; Is the preempt disable flag set? + CBNZ r1, __tx_timer_skip_time_slice ; Yes, skip the PendSV logic + MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup the current thread pointer + MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address + LDR r3, [r2] ; Pickup the execute thread pointer + MOV32 r0, 0xE000ED04 ; Build address of control register + MOV32 r2, 0x10000000 ; Build value for PendSV bit + CMP r1, r3 ; Are they the same? + BEQ __tx_timer_skip_time_slice ; If the same, there was no time-slice performed + STR r2, [r0] ; Not the same, issue the PendSV for preemption +__tx_timer_skip_time_slice +; +; } +; +__tx_timer_not_ts_expiration +; + LDMIA sp!, {r0, lr} ; Recover lr register (r0 is just there for + ; the 8-byte stack alignment +; +; } +; +__tx_timer_nothing_expired + + DSB ; Complete all memory access + BX lr ; Return to caller +; +;} + ENDFUNC + ALIGN + LTORG + END + diff --git a/ports/cortex_m33/ac5/src/txe_thread_secure_stack_allocate.c b/ports/cortex_m33/ac5/src/txe_thread_secure_stack_allocate.c new file mode 100644 index 00000000..dc99f538 --- /dev/null +++ b/ports/cortex_m33/ac5/src/txe_thread_secure_stack_allocate.c @@ -0,0 +1,119 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_secure_stack_allocate Cortex-M33 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the secure stack allocate */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* stack_size Size of secure stack to */ +/* allocate */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_secure_stack_allocate Actual stack alloc function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +{ +#if defined(TX_SINGLE_MODE_SECURE) || defined(TX_SINGLE_MODE_NON_SECURE) + return(TX_FEATURE_NOT_ENABLED); +#else +UINT status; + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid thread pointer. */ + if (thread_ptr == TX_NULL) + { + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Now check for invalid thread ID. */ + else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) + { + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Check for interrupt call. */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + /* Is call from an interrupt and not initialization? */ + if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS) + { + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + /* Call actual secure stack allocate function. */ + status = _tx_thread_secure_stack_allocate(thread_ptr, stack_size); + } + + /* Return completion status. */ + return(status); +#endif +} diff --git a/ports/cortex_m33/ac5/src/txe_thread_secure_stack_free.c b/ports/cortex_m33/ac5/src/txe_thread_secure_stack_free.c new file mode 100644 index 00000000..9f6ed6b9 --- /dev/null +++ b/ports/cortex_m33/ac5/src/txe_thread_secure_stack_free.c @@ -0,0 +1,120 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_secure_stack_free Cortex-M33 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the secure stack free */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_secure_stack_free Actual stack free function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) +{ +#if defined(TX_SINGLE_MODE_SECURE) || defined(TX_SINGLE_MODE_NON_SECURE) + return(TX_FEATURE_NOT_ENABLED); +#else +UINT status; + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid thread pointer. */ + if (thread_ptr == TX_NULL) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Now check for invalid thread ID. */ + else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Check for interrupt call. */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + /* Is call from an interrupt and not initialization? */ + if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS) + { + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + + /* Call actual secure stack allocate function. */ + status = _tx_thread_secure_stack_free(thread_ptr); + } + + /* Return completion status. */ + return(status); +#endif +} diff --git a/ports/cortex_m33/ac6/example_build/tx_initialize_low_level.S b/ports/cortex_m33/ac6/example_build/tx_initialize_low_level.S index 094a575d..95ceb7a1 100644 --- a/ports/cortex_m33/ac6/example_build/tx_initialize_low_level.S +++ b/ports/cortex_m33/ac6/example_build/tx_initialize_low_level.S @@ -34,7 +34,7 @@ HEAP_SIZE = 0x00000000 /* FUNCTION RELEASE */ /* */ /* _tx_initialize_low_level Cortex-M33/AC6 */ -/* 6.0.2 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -67,10 +67,7 @@ HEAP_SIZE = 0x00000000 /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ -/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -/* whitespace, resulting */ -/* in version 6.0.2 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_m33/ac6/inc/tx_port.h b/ports/cortex_m33/ac6/inc/tx_port.h index bee06e96..dc9aa58f 100644 --- a/ports/cortex_m33/ac6/inc/tx_port.h +++ b/ports/cortex_m33/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M33/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -535,7 +535,7 @@ unsigned int was_masked; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33/AC6 Version 6.0.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33/AC6 Version 6.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m33/ac6/inc/tx_secure_interface.h b/ports/cortex_m33/ac6/inc/tx_secure_interface.h index e2133c88..c2779f40 100644 --- a/ports/cortex_m33/ac6/inc/tx_secure_interface.h +++ b/ports/cortex_m33/ac6/inc/tx_secure_interface.h @@ -26,7 +26,7 @@ /* COMPONENT DEFINITION RELEASE */ /* */ /* tx_secure_interface.h PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -42,7 +42,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ diff --git a/ports/cortex_m33/ac6/readme_threadx.txt b/ports/cortex_m33/ac6/readme_threadx.txt index cdbbb7a5..fbc3451f 100644 --- a/ports/cortex_m33/ac6/readme_threadx.txt +++ b/ports/cortex_m33/ac6/readme_threadx.txt @@ -204,15 +204,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -08-14-2020 ThreadX update of Cortex-M33/AC6 port. The following files were - changed/added for port specific version 6.0.2: - - tx_thread_context_restore.S Remove execution profile kit call. - tx_thread_context_save.S Remove execution profile kit call. - tx_timer_interrupt.S Add DSB instruction before returning. - *.S Modified comments and whitespace. - -06-30-2020 Initial ThreadX 6.0.1 version for Cortex-M33 using AC6 tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-M33 using AC6 tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_m33/ac6/src/tx_thread_context_restore.S b/ports/cortex_m33/ac6/src/tx_thread_context_restore.S index 951d526a..26e64ab4 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_m33/ac6/src/tx_thread_context_restore.S @@ -26,7 +26,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore Cortex-M33/AC6 */ -/* 6.0.2 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -55,10 +55,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ -/* 08-14-2020 Scott Larson Modified comment(s), remove */ -/* EPK, clean up whitespace */ -/* resulting in version 6.0.2 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m33/ac6/src/tx_thread_context_save.S b/ports/cortex_m33/ac6/src/tx_thread_context_save.S index 36e115f9..2d2314fb 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_m33/ac6/src/tx_thread_context_save.S @@ -26,7 +26,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save Cortex-M33/AC6 */ -/* 6.0.2 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -55,10 +55,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ -/* 08-14-2020 Scott Larson Modified comment(s), remove */ -/* EPK, clean up whitespace */ -/* resulting in version 6.0.2 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m33/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_m33/ac6/src/tx_thread_interrupt_control.S index bf00b31e..bbb3da9a 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m33/ac6/src/tx_thread_interrupt_control.S @@ -26,7 +26,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control Cortex-M33/AC6 */ -/* 6.0.2 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -56,10 +56,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ -/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -/* whitespace, resulting */ -/* in version 6.0.2 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_m33/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_m33/ac6/src/tx_thread_interrupt_disable.S index b603c19e..e3a95f5c 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_m33/ac6/src/tx_thread_interrupt_disable.S @@ -26,7 +26,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable Cortex-M33/AC6 */ -/* 6.0.2 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -56,10 +56,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ -/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -/* whitespace, resulting */ -/* in version 6.0.2 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_interrupt_disable(UINT new_posture) diff --git a/ports/cortex_m33/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_m33/ac6/src/tx_thread_interrupt_restore.S index 7da57ee0..2e29b3cb 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_m33/ac6/src/tx_thread_interrupt_restore.S @@ -26,7 +26,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore Cortex-M33/AC6 */ -/* 6.0.2 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -56,10 +56,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ -/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -/* whitespace, resulting */ -/* in version 6.0.2 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_interrupt_restore(UINT new_posture) diff --git a/ports/cortex_m33/ac6/src/tx_thread_schedule.S b/ports/cortex_m33/ac6/src/tx_thread_schedule.S index 4171213a..cd6b3e67 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_m33/ac6/src/tx_thread_schedule.S @@ -26,7 +26,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M33/AC6 */ -/* 6.0.2 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,10 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ -/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -/* whitespace, resulting */ -/* in version 6.0.2 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_m33/ac6/src/tx_thread_secure_stack.c b/ports/cortex_m33/ac6/src/tx_thread_secure_stack.c index b563ba7c..d53cb715 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_secure_stack.c +++ b/ports/cortex_m33/ac6/src/tx_thread_secure_stack.c @@ -59,7 +59,7 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_initialize Cortex-M33/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -91,7 +91,7 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) @@ -116,7 +116,7 @@ void _tx_thread_secure_stack_initialize(void) /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_mode_stack_allocate PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -155,7 +155,7 @@ void _tx_thread_secure_stack_initialize(void) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) @@ -238,7 +238,7 @@ UCHAR *stack_mem; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_mode_stack_free PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -270,7 +270,7 @@ UCHAR *stack_mem; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) @@ -319,7 +319,7 @@ TX_THREAD_SECURE_STACK_INFO *info_ptr; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_context_save PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -351,7 +351,7 @@ TX_THREAD_SECURE_STACK_INFO *info_ptr; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) @@ -401,7 +401,7 @@ ULONG sp; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_context_restore PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -432,7 +432,7 @@ ULONG sp; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) diff --git a/ports/cortex_m33/ac6/src/tx_thread_secure_stack_allocate.S b/ports/cortex_m33/ac6/src/tx_thread_secure_stack_allocate.S index 6e4ec1b6..3e3870b0 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_secure_stack_allocate.S +++ b/ports/cortex_m33/ac6/src/tx_thread_secure_stack_allocate.S @@ -26,7 +26,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_allocate Cortex-M33/AC6 */ -/* 6.0.2 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -57,10 +57,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ -/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -/* whitespace, resulting */ -/* in version 6.0.2 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) diff --git a/ports/cortex_m33/ac6/src/tx_thread_secure_stack_free.S b/ports/cortex_m33/ac6/src/tx_thread_secure_stack_free.S index 53aada3b..1511d779 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_secure_stack_free.S +++ b/ports/cortex_m33/ac6/src/tx_thread_secure_stack_free.S @@ -26,7 +26,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_free Cortex-M33/AC6 */ -/* 6.0.2 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -55,10 +55,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ -/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -/* whitespace, resulting */ -/* in version 6.0.2 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) diff --git a/ports/cortex_m33/ac6/src/tx_thread_stack_build.S b/ports/cortex_m33/ac6/src/tx_thread_stack_build.S index f31d35c7..16f98ef2 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_m33/ac6/src/tx_thread_stack_build.S @@ -26,7 +26,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build Cortex-M33/AC6 */ -/* 6.0.2 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,10 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ -/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -/* whitespace, resulting */ -/* in version 6.0.2 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_m33/ac6/src/tx_thread_stack_error_handler.c b/ports/cortex_m33/ac6/src/tx_thread_stack_error_handler.c index 133497b4..98e86a2e 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_stack_error_handler.c +++ b/ports/cortex_m33/ac6/src/tx_thread_stack_error_handler.c @@ -39,7 +39,7 @@ VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_error_handler Cortex-M33/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -70,7 +70,7 @@ VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) diff --git a/ports/cortex_m33/ac6/src/tx_thread_stack_error_notify.c b/ports/cortex_m33/ac6/src/tx_thread_stack_error_notify.c index c9e70eb6..afa5b98f 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_stack_error_notify.c +++ b/ports/cortex_m33/ac6/src/tx_thread_stack_error_notify.c @@ -36,7 +36,7 @@ extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr) /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_error_notify Cortex-M33/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -68,7 +68,7 @@ extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr)) diff --git a/ports/cortex_m33/ac6/src/tx_thread_system_return.S b/ports/cortex_m33/ac6/src/tx_thread_system_return.S index 7651e708..7094adfd 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_m33/ac6/src/tx_thread_system_return.S @@ -26,7 +26,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return Cortex-M33/AC6 */ -/* 6.0.2 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -58,10 +58,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ -/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -/* whitespace, resulting */ -/* in version 6.0.2 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ // VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_m33/ac6/src/tx_timer_interrupt.S b/ports/cortex_m33/ac6/src/tx_timer_interrupt.S index 6e49112e..b1599312 100644 --- a/ports/cortex_m33/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_m33/ac6/src/tx_timer_interrupt.S @@ -26,7 +26,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt Cortex-M33/AC6 */ -/* 6.0.2 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,11 +60,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ -/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -/* whitespace, add DSB before */ -/* returning, resulting */ -/* in version 6.0.2 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_m33/ac6/src/txe_thread_secure_stack_allocate.c b/ports/cortex_m33/ac6/src/txe_thread_secure_stack_allocate.c index ded0507d..3ff6fa68 100644 --- a/ports/cortex_m33/ac6/src/txe_thread_secure_stack_allocate.c +++ b/ports/cortex_m33/ac6/src/txe_thread_secure_stack_allocate.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_allocate PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) diff --git a/ports/cortex_m33/ac6/src/txe_thread_secure_stack_free.c b/ports/cortex_m33/ac6/src/txe_thread_secure_stack_free.c index af49c7df..f8207c68 100644 --- a/ports/cortex_m33/ac6/src/txe_thread_secure_stack_free.c +++ b/ports/cortex_m33/ac6/src/txe_thread_secure_stack_free.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_secure_stack_free PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -66,7 +66,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) diff --git a/ports/cortex_m33/gnu/inc/tx_port.h b/ports/cortex_m33/gnu/inc/tx_port.h new file mode 100644 index 00000000..5ded9c99 --- /dev/null +++ b/ports/cortex_m33/gnu/inc/tx_port.h @@ -0,0 +1,578 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-M33/GNU */ +/* 6.1 */ +/* */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + +/* Determine if the optional ThreadX user define file should be used. */ +#ifdef TX_INCLUDE_USER_DEFINE_FILE + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + +/* Define compiler library include files. */ + +#include +#include + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef unsigned long long ULONG64; +typedef short SHORT; +typedef unsigned short USHORT; + +/* Function prototypes for this port. */ +struct TX_THREAD_STRUCT; +UINT _txe_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *thread_ptr, ULONG stack_size); +UINT _txe_thread_secure_stack_free(struct TX_THREAD_STRUCT *thread_ptr); +UINT _tx_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *tx_thread, ULONG stack_size); +UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); + +/* This hardware has stack checking that we take advantage of - do NOT define. */ +#ifdef TX_ENABLE_STACK_CHECKING + #error "Do not define TX_ENABLE_STACK_CHECKING" +#endif + +/* If user does not want to terminate thread on stack overflow, + #define the TX_THREAD_NO_TERMINATE_STACK_ERROR symbol. + The thread will be rescheduled and continue to cause the exception. + It is suggested user code handle this by registering a notification with the + tx_thread_stack_error_notify function. */ +/*#define TX_THREAD_NO_TERMINATE_STACK_ERROR */ + +/* Define the system API mappings based on the error checking + selected by the user. Note: this section is only applicable to + application source code, hence the conditional that turns off this + stuff when the include file is processed by the ThreadX source. */ + +#ifndef TX_SOURCE_CODE + + +/* Determine if error checking is desired. If so, map API functions + to the appropriate error checking front-ends. Otherwise, map API + functions to the core functions that actually perform the work. + Note: error checking is enabled by default. */ + +#ifdef TX_DISABLE_ERROR_CHECKING + +/* Services without error checking. */ + +#define tx_thread_secure_stack_allocate _tx_thread_secure_stack_allocate +#define tx_thread_secure_stack_free _tx_thread_secure_stack_free + +#else + +/* Services with error checking. */ + +#define tx_thread_secure_stack_allocate _txe_thread_secure_stack_allocate +#define tx_thread_secure_stack_free _txe_thread_secure_stack_free + +#endif +#endif + + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX Cortex-M33 port. */ + +#define TX_INT_DISABLE 1 /* Disable interrupts */ +#define TX_INT_ENABLE 0 /* Enable interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) +#endif +#else +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif + +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_secure_stack_context; +#else +#define TX_THREAD_EXTENSION_2 +#endif +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) if(thread_ptr -> tx_thread_secure_stack_context){_tx_thread_secure_stack_free(thread_ptr);} +#else +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +/* Define the size of the secure stack for the timer thread and use the extension to allocate the secure stack. */ +#define TX_TIMER_THREAD_SECURE_STACK_SIZE 256 +#define TX_TIMER_INITIALIZE_EXTENSION(status) _tx_thread_secure_stack_allocate(&_tx_timer_thread, TX_TIMER_THREAD_SECURE_STACK_SIZE); +#endif + + +#ifndef TX_MISRA_ENABLE + +//register unsigned int _ipsr __asm ("MRS %[result], ipsr" : [result] "=r" (_ipsr) : ); +inline static unsigned int _get_ipsr(void); +inline static unsigned int _get_ipsr(void) +{ + unsigned int _ipsr; + __asm("MRS %[result], ipsr" : [result] "=r" (_ipsr) : ); + return _ipsr; +} + +#endif + + +#ifdef __ARM_PCS_VFP + +#ifdef TX_MISRA_ENABLE + +ULONG _tx_misra_control_get(void); +void _tx_misra_control_set(ULONG value); +ULONG _tx_misra_fpccr_get(void); +void _tx_misra_vfp_touch(void); + +#else + +#ifdef TX_SOURCE_CODE + +static unsigned int _get_control(void); +static unsigned int _get_control(void) +{ + unsigned int _control; + __asm("MRS %[result], control" : [result] "=r" (_control) : ); + return _control; +} + +static void _set_control(unsigned int _control); +static void _set_control(unsigned int _control) +{ + __asm("MSR control, %[input]" : : [input] "r" (_control)); +} + +#endif +#endif + +/* A completed thread falls into _thread_shell_entry and we can simply deactivate the FPU via CONTROL.FPCA + in order to ensure no lazy stacking will occur. */ + +#ifndef TX_MISRA_ENABLE + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _get_control(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _set_control(_tx_vfp_state);; \ + } +#else + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } + +#endif + +/* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. + If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + the lazy FPU save, then restore the CONTROL.FPCA state. */ + +#ifndef TX_MISRA_ENABLE + +void _tx_vfp_access(void); + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _get_control(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _set_control(_tx_vfp_state); \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = *((ULONG *) 0xE000EF34); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _get_control(); \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + _tx_vfp_access(); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = _get_control(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _set_control(_tx_vfp_state); \ + } \ + } \ + } \ + } +#else + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = _tx_misra_fpccr_get(); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + _tx_misra_vfp_touch(); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + } \ + } \ + } +#endif + +#else + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + +#endif + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define the get system state macro. */ + +#ifndef TX_THREAD_GET_SYSTEM_STATE +#ifndef TX_MISRA_ENABLE +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _get_ipsr()) +#else +ULONG _tx_misra_ipsr_get(VOID); +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get()) +#endif +#endif + + +/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value + indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h + for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always + zero after initialization for Cortex-M ports. */ + +#ifndef TX_THREAD_SYSTEM_RETURN_CHECK +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#endif + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +/* Initialize secure stacks for threads calling secure functions. */ +extern void _tx_thread_secure_stack_initialize(void); +#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION _tx_thread_secure_stack_initialize(); +#endif + +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to + prevent early scheduling on Cortex-M parts. */ + +#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifndef TX_DISABLE_INLINE + +/* Define GNU specific macros, with in-line assembly for performance. */ + +__attribute__( ( always_inline ) ) static inline unsigned int __disable_interrupts(void) +{ + +unsigned int primask_value; + + __asm__ volatile (" MRS %0,PRIMASK ": "=r" (primask_value) ); + __asm__ volatile (" CPSID i" : : : "memory" ); + return(primask_value); +} + +__attribute__( ( always_inline ) ) static inline void __restore_interrupts(unsigned int primask_value) +{ + + __asm__ volatile (" MSR PRIMASK,%0": : "r" (primask_value): "memory" ); +} + +__attribute__( ( always_inline ) ) static inline unsigned int __get_primask_value(void) +{ + +unsigned int primask_value; + + __asm__ volatile (" MRS %0,PRIMASK ": "=r" (primask_value) ); + return(primask_value); +} + +__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void) +{ + + __asm__ volatile (" CPSIE i": : : "memory" ); +} + + +__attribute__( ( always_inline ) ) static inline void _tx_thread_system_return_inline(void) +{ +unsigned int interrupt_save; + + *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + if (_get_ipsr() == 0) + { + interrupt_save = __get_primask_value(); + __enable_interrupts(); + __restore_interrupts(interrupt_save); + } +} + + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = __disable_interrupts(); +#define TX_RESTORE __restore_interrupts(interrupt_save); + + +/* Redefine _tx_thread_system_return for improved performance. */ + +#define _tx_thread_system_return _tx_thread_system_return_inline + + +#else + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); +#define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); +#endif + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33/GNU Version 6.1 *"; +#else +#ifdef TX_MISRA_ENABLE +extern CHAR _tx_version_id[100]; +#else +extern CHAR _tx_version_id[]; +#endif +#endif + +#endif diff --git a/ports/cortex_m33/gnu/inc/tx_secure_interface.h b/ports/cortex_m33/gnu/inc/tx_secure_interface.h new file mode 100644 index 00000000..6fa51319 --- /dev/null +++ b/ports/cortex_m33/gnu/inc/tx_secure_interface.h @@ -0,0 +1,60 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* tx_secure_interface.h Cortex-M33 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the ThreadX secure thread stack components, */ +/* including data types and external references. */ +/* It is assumed that tx_api.h and tx_port.h have already been */ +/* included. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_SECURE_INTERFACE_H +#define TX_SECURE_INTERFACE_H + +/* Define internal secure thread stack function prototypes. */ + +extern void _tx_thread_secure_stack_initialize(void); +extern UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size); +extern UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr); +extern void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr); +extern void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr); + +#endif diff --git a/ports/cortex_m33/gnu/readme_threadx.txt b/ports/cortex_m33/gnu/readme_threadx.txt new file mode 100644 index 00000000..822b73ec --- /dev/null +++ b/ports/cortex_m33/gnu/readme_threadx.txt @@ -0,0 +1,197 @@ + Microsoft's Azure RTOS ThreadX for Cortex-M33 + + Using the GNU Tools + +1. Building the ThreadX run-time Library + +Import all ThreadX common and port-specific source files into a GNU project. +Configure the project to build a library rather than an executable. This +results in the ThreadX run-time library file tx.a, which is needed by +the application. + + +2. Demonstration System + +No demonstration project is provided. + + +3. System Initialization + +The entry point in ThreadX for the Cortex-M33 using gnu tools uses the standard GNU +Cortex-M33 reset sequence. From the reset vector the C runtime will be initialized. + +The ThreadX tx_initialize_low_level.S file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. + +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input +parameter to your application definition function, tx_application_define. + + +4. Register Usage and Stack Frames + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have the same stack frame in the Cortex-M33 version of +ThreadX. The top of the suspended thread's stack is pointed to by +tx_thread_stack_ptr in the associated thread control block TX_THREAD. + +Non-FPU Stack Frame: + + Stack Offset Stack Contents + + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 r4 + 0x08 r5 + 0x0C r6 + 0x10 r7 + 0x14 r8 + 0x18 r9 + 0x1C r10 + 0x20 r11 + 0x24 r0 (Hardware stack starts here!!) + 0x28 r1 + 0x2C r2 + 0x30 r3 + 0x34 r12 + 0x38 lr + 0x3C pc + 0x40 xPSR + +FPU Stack Frame (only interrupted thread with FPU enabled): + + Stack Offset Stack Contents + + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 s0 + 0x08 s1 + 0x0C s2 + 0x10 s3 + 0x14 s4 + 0x18 s5 + 0x1C s6 + 0x20 s7 + 0x24 s8 + 0x28 s9 + 0x2C s10 + 0x30 s11 + 0x34 s12 + 0x38 s13 + 0x3C s14 + 0x40 s15 + 0x44 s16 + 0x48 s17 + 0x4C s18 + 0x50 s19 + 0x54 s20 + 0x58 s21 + 0x5C s22 + 0x60 s23 + 0x64 s24 + 0x68 s25 + 0x6C s26 + 0x70 s27 + 0x74 s28 + 0x78 s29 + 0x7C s30 + 0x80 s31 + 0x84 fpscr + 0x88 r4 + 0x8C r5 + 0x90 r6 + 0x94 r7 + 0x98 r8 + 0x9C r9 + 0xA0 r10 + 0xA4 r11 + 0xA8 r0 (Hardware stack starts here!!) + 0xAC r1 + 0xB0 r2 + 0xB4 r3 + 0xB8 r12 + 0xBC lr + 0xC0 pc + 0xC4 xPSR + + +5. Improving Performance + +To make ThreadX and the application(s) run faster, you can enable +all compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +6. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-M33 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +6.1 Vector Area + +The Cortex-M33 vectors start at the label __tx_vectors or similar. The application may modify +the vector area according to its needs. There is code in tx_initialize_low_level() that will +configure the vector base register. + + +6.2 Managed Interrupts + +ISRs can be written completely in C (or assembly language) without any calls to +_tx_thread_context_save or _tx_thread_context_restore. These ISRs are allowed access to the +ThreadX API that is available to ISRs. + +ISRs written in C will take the form (where "your_C_isr" is an entry in the vector table): + +void your_C_isr(void) +{ + + /* ISR processing goes here, including any needed function calls. */ +} + +ISRs written in assembly language will take the form: + + + .global your_assembly_isr + .thumb_func +your_assembly_isr: + PUSH {r0, lr} +; +; /* Do interrupt handler work here */ +; /* BL */ + + POP {r0, lr} + BX lr + +Note: the Cortex-M33 requires exception handlers to be thumb labels, this implies bit 0 set. +To accomplish this, the declaration of the label has to be preceded by the assembler directive +.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to +be inserted in the correct location in the interrupt vector table. This table is typically +located in either your runtime startup file or in the tx_initialize_low_level.S file. + + +7. FPU Support + +ThreadX for Cortex-M33 supports automatic ("lazy") VFP support, which means that applications threads +can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread +context. + + +8. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +09-30-2020 Initial ThreadX 6.1 version for Cortex-M33 using GNU tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_m33/gnu/src/tx_initialize_low_level.S b/ports/cortex_m33/gnu/src/tx_initialize_low_level.S new file mode 100644 index 00000000..3f7cc108 --- /dev/null +++ b/ports/cortex_m33/gnu/src/tx_initialize_low_level.S @@ -0,0 +1,268 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +SYSTEM_CLOCK = 6000000 +SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) + +/* Setup the stack and heap areas. */ + +STACK_SIZE = 0x00000400 +HEAP_SIZE = 0x00000000 + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-M33/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_initialize_low_level(VOID) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_initialize_low_level + .thumb_func +.type _tx_initialize_low_level, function +_tx_initialize_low_level: + + /* Disable interrupts during ThreadX initialization. */ + CPSID i + + /* Set base of available memory to end of non-initialised RAM area. */ + LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer + LDR r1, =__RAM_segment_used_end__ // Build first free address + ADD r1, r1, #4 // + STR r1, [r0] // Setup first unused memory pointer + + /* Setup Vector Table Offset Register. */ + MOV r0, #0xE000E000 // Build address of NVIC registers + LDR r1, =_vectors // Pickup address of vector table + STR r1, [r0, #0xD08] // Set vector table address + + /* Enable the cycle count register. */ + LDR r0, =0xE0001000 // Build address of DWT register + LDR r1, [r0] // Pickup the current value + ORR r1, r1, #1 // Set the CYCCNTENA bit + STR r1, [r0] // Enable the cycle count register + + /* Set system stack pointer from vector value. */ + LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer + LDR r1, =_vectors // Pickup address of vector table + LDR r1, [r1] // Pickup reset stack pointer + STR r1, [r0] // Save system stack pointer + + /* Configure SysTick. */ + MOV r0, #0xE000E000 // Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] // Setup SysTick Reload Value + MOV r1, #0x7 // Build SysTick Control Enable Value + STR r1, [r0, #0x10] // Setup SysTick Control + + /* Configure handler priorities. */ + LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] // Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] // Setup System Handlers 8-11 Priority Registers + // Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] // Setup System Handlers 12-15 Priority Registers + // Note: PnSV must be lowest priority, which is 0xFF + + /* Return to caller. */ + BX lr +// } + + +/* Define shells for each of the unused vectors. */ + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global __tx_BadHandler + .thumb_func +.type __tx_BadHandler, function +__tx_BadHandler: + B __tx_BadHandler + + + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global __tx_IntHandler + .thumb_func +.type __tx_IntHandler, function +__tx_IntHandler: +// VOID InterruptHandler (VOID) +// { + PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) + + /* Do interrupt handler work here */ + /* .... */ + + POP {r0,lr} + BX LR +// } + + + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global SysTick_Handler + .thumb_func +.type SysTick_Handler, function +SysTick_Handler: +// VOID TimerInterruptHandler (VOID) +// { + PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) + BL _tx_timer_interrupt + POP {r0,lr} + BX LR +// } + + + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global HardFault_Handler + .thumb_func +.type HardFault_Handler, function +HardFault_Handler: + B HardFault_Handler + + + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global UsageFault_Handler + .thumb_func +.type UsageFault_Handler, function +UsageFault_Handler: + CPSID i // Disable interrupts + // Check for stack limit fault + LDR r0, =0xE000ED28 // CFSR address + LDR r1,[r0] // Pick up CFSR + TST r1, #0x00100000 // Check for Stack Overflow +_unhandled_usage_loop: + BEQ _unhandled_usage_loop // If not stack overflow then loop + + // Handle stack overflow + STR r1, [r0] // Clear CFSR flag(s) + +#ifdef __ARM_PCS_VFP + LDR r0, =0xE000EF34 // Cleanup FPU context: Load FPCCR address + LDR r1, [r0] // Load FPCCR + BIC r1, r1, #1 // Clear the lazy preservation active bit + STR r1, [r0] // Store the value +#endif + + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r0,[r0] // Pick up current thread pointer + PUSH {r0,lr} // Save LR (and r0 to maintain stack alignment) + BL _tx_thread_stack_error_handler // Call ThreadX/user handler + POP {r0,lr} // Restore LR and dummy reg + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + // Call the thread exit function to indicate the thread is no longer executing. + PUSH {r0, lr} // Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit // Call the thread exit function + POP {r0, lr} // Recover LR +#endif + + MOV r1, #0 // Build NULL value + LDR r0, =_tx_thread_current_ptr // Pickup address of current thread pointer + STR r1, [r0] // Clear current thread pointer + + // Return from UsageFault_Handler exception + LDR r0, =0xE000ED04 // Load ICSR + LDR r1, =0x10000000 // Set PENDSVSET bit + STR r1, [r0] // Store ICSR + DSB // Wait for memory access to complete + CPSIE i // Enable interrupts + BX lr // Return from exception + + + + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global __tx_NMIHandler + .thumb_func +.type __tx_NMIHandler, function +__tx_NMIHandler: + B __tx_NMIHandler + + + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global __tx_DBGHandler + .thumb_func +.type __tx_DBGHandler, function +__tx_DBGHandler: + B __tx_DBGHandler + + .end diff --git a/ports/cortex_m33/gnu/src/tx_thread_context_restore.S b/ports/cortex_m33/gnu/src/tx_thread_context_restore.S new file mode 100644 index 00000000..0cf97109 --- /dev/null +++ b/ports/cortex_m33/gnu/src/tx_thread_context_restore.S @@ -0,0 +1,74 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore Cortex-M33/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is not needed for Cortex-M. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_context_restore(VOID) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_context_restore + .thumb_func +.type _tx_thread_context_restore, function +_tx_thread_context_restore: + /* Just return! */ + BX lr +// } + .end diff --git a/ports/cortex_m33/gnu/src/tx_thread_context_save.S b/ports/cortex_m33/gnu/src/tx_thread_context_save.S new file mode 100644 index 00000000..29c21b85 --- /dev/null +++ b/ports/cortex_m33/gnu/src/tx_thread_context_save.S @@ -0,0 +1,74 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save Cortex-M33/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is not needed for Cortex-M. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_context_save(VOID) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_context_save + .thumb_func +.type _tx_thread_context_save, function +_tx_thread_context_save: + /* Return to interrupt processing. */ + BX lr +// } + .end diff --git a/ports/cortex_m33/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_m33/gnu/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..bbe60f44 --- /dev/null +++ b/ports/cortex_m33/gnu/src/tx_thread_interrupt_control.S @@ -0,0 +1,78 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control Cortex-M33/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_interrupt_control(UINT new_posture) +// { + .section .text + .balign 4 + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_interrupt_control + .thumb_func +.type _tx_thread_interrupt_control, function +_tx_thread_interrupt_control: + + /* Pickup current interrupt lockout posture. */ + MRS r1, PRIMASK + MSR PRIMASK, r0 + MOV r0, r1 + BX lr +// } + .end diff --git a/ports/cortex_m33/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_m33/gnu/src/tx_thread_interrupt_disable.S new file mode 100644 index 00000000..62ed1d07 --- /dev/null +++ b/ports/cortex_m33/gnu/src/tx_thread_interrupt_disable.S @@ -0,0 +1,77 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_disable Cortex-M33/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for disabling interrupts and returning */ +/* the previous interrupt lockout posture. */ +/* */ +/* INPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_interrupt_disable(UINT new_posture) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_interrupt_disable + .thumb_func +.type _tx_thread_interrupt_disable, function +_tx_thread_interrupt_disable: + /* Return current interrupt lockout posture. */ + MRS r0, PRIMASK + CPSID i + BX lr +// } + .end diff --git a/ports/cortex_m33/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_m33/gnu/src/tx_thread_interrupt_restore.S new file mode 100644 index 00000000..e33ce2b0 --- /dev/null +++ b/ports/cortex_m33/gnu/src/tx_thread_interrupt_restore.S @@ -0,0 +1,76 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_restore Cortex-M33/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for restoring the previous */ +/* interrupt lockout posture. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* previous_posture Previous interrupt posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_interrupt_restore(UINT new_posture) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_interrupt_restore + .thumb_func +.type _tx_thread_interrupt_restore, function +_tx_thread_interrupt_restore: + /* Restore previous interrupt lockout posture. */ + MSR PRIMASK, r0 + BX lr +// } + .end diff --git a/ports/cortex_m33/gnu/src/tx_thread_schedule.S b/ports/cortex_m33/gnu/src/tx_thread_schedule.S new file mode 100644 index 00000000..59717066 --- /dev/null +++ b/ports/cortex_m33/gnu/src/tx_thread_schedule.S @@ -0,0 +1,325 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule Cortex-M33/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_schedule(VOID) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_schedule + .thumb_func +.type _tx_thread_schedule, function +_tx_thread_schedule: + /* This function should only ever be called on Cortex-M + from the first schedule request. Subsequent scheduling occurs + from the PendSV handling routine below. */ + + /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ + MOV r0, #0 // Build value for TX_FALSE + LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag + STR r0, [r2, #0] // Clear preempt disable flag + + /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */ + +#ifdef __ARM_PCS_VFP + MRS r0, CONTROL // Pickup current CONTROL register + BIC r0, r0, #4 // Clear the FPCA bit + MSR CONTROL, r0 // Setup new CONTROL register +#endif + + /* Enable interrupts */ + CPSIE i + + /* Enter the scheduler for the first time. */ + + MOV r0, #0x10000000 // Load PENDSVSET bit + MOV r1, #0xE000E000 // Load NVIC base + STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + DSB // Complete all memory accesses + ISB // Flush pipeline + + /* Wait here for the PendSV to take place. */ + +__tx_wait_here: + B __tx_wait_here // Wait for the PendSV to happen +// } + + /* Generic context switching PendSV handler. */ + + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global PendSV_Handler + .thumb_func +.type PendSV_Handler, function + /* Get current thread value and new thread pointer. */ +PendSV_Handler: +__tx_ts_handler: + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread exit function to indicate the thread is no longer executing. */ + + CPSID i // Disable interrupts + PUSH {r0, lr} // Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit // Call the thread exit function + POP {r0, lr} // Recover LR + CPSIE i // Enable interrupts +#endif + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address + MOV r3, #0 // Build NULL value + LDR r1, [r0] // Pickup current thread pointer + + /* Determine if there is a current thread to finish preserving. */ + + CBZ r1, __tx_ts_new // If NULL, skip preservation + + /* Recover PSP and preserve current thread context. */ + + STR r3, [r0] // Set _tx_thread_current_ptr to NULL + MRS r12, PSP // Pickup PSP pointer (thread's stack pointer) + STMDB r12!, {r4-r11} // Save its remaining registers +#ifdef __ARM_PCS_VFP + TST LR, #0x10 // Determine if the VFP extended frame is present + BNE _skip_vfp_save + VSTMDB r12!,{s16-s31} // Yes, save additional VFP registers +_skip_vfp_save: +#endif + LDR r4, =_tx_timer_time_slice // Build address of time-slice variable + STMDB r12!, {LR} // Save LR on the stack + STR r12, [r1, #8] // Save the thread stack pointer + +#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) + // Save secure context + LDR r5, [r1,#0x90] // Load secure stack index + CBZ r5, _skip_secure_save // Skip save if there is no secure context + PUSH {r0,r1,r2,r3} // Save scratch registers + MOV r0, r1 // Move thread ptr to r0 + BL _tx_thread_secure_stack_context_save // Save secure stack + POP {r0,r1,r2,r3} // Restore secure registers +_skip_secure_save: +#endif + + /* Determine if time-slice is active. If it isn't, skip time handling processing. */ + + LDR r5, [r4] // Pickup current time-slice + CBZ r5, __tx_ts_new // If not active, skip processing + + /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ + + STR r5, [r1, #24] // Save current time-slice + + /* Clear the global time-slice. */ + + STR r3, [r4] // Clear time-slice + + /* Executing thread is now completely preserved!!! */ + +__tx_ts_new: + + /* Now we are looking for a new thread to execute! */ + + CPSID i // Disable interrupts + LDR r1, [r2] // Is there another thread ready to execute? + CBZ r1, __tx_ts_wait // No, skip to the wait processing + + /* Yes, another thread is ready for else, make the current thread the new thread. */ + + STR r1, [r0] // Setup the current thread pointer to the new thread + CPSIE i // Enable interrupts + + /* Increment the thread run count. */ + +__tx_ts_restore: + LDR r7, [r1, #4] // Pickup the current thread run count + LDR r4, =_tx_timer_time_slice // Build address of time-slice variable + LDR r5, [r1, #24] // Pickup thread's current time-slice + ADD r7, r7, #1 // Increment the thread run count + STR r7, [r1, #4] // Store the new run count + + /* Setup global time-slice with thread's current time-slice. */ + + STR r5, [r4] // Setup global time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + /* Call the thread entry function to indicate the thread is executing. */ + PUSH {r0, r1} // Save r0/r1 + BL _tx_execution_thread_enter // Call the thread execution enter function + POP {r0, r1} // Recover r0/r1 +#endif + +#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) + // Restore secure context + LDR r0, [r1,#0x90] // Load secure stack index + CBZ r0, _skip_secure_restore // Skip restore if there is no secure context + PUSH {r0,r1} // Save r1 (and dummy r0) + MOV r0, r1 // Move thread ptr to r0 + BL _tx_thread_secure_stack_context_restore // Restore secure stack + POP {r0,r1} // Restore r1 (and dummy r0) +_skip_secure_restore: +#endif + + /* Restore the thread context and PSP. */ + LDR r12, [r1, #12] // Get stack start + MSR PSPLIM, r12 // Set stack limit + LDR r12, [r1, #8] // Pickup thread's stack pointer + LDMIA r12!, {LR} // Pickup LR +#ifdef __ARM_PCS_VFP + TST LR, #0x10 // Determine if the VFP extended frame is present + BNE _skip_vfp_restore // If not, skip VFP restore + VLDMIA r12!, {s16-s31} // Yes, restore additional VFP registers +_skip_vfp_restore: +#endif + LDMIA r12!, {r4-r11} // Recover thread's registers + MSR PSP, r12 // Setup the thread's stack pointer + + /* Return to thread. */ + BX lr // Return to thread! + + /* The following is the idle wait processing... in this case, no threads are ready for execution and the + system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts + are disabled to allow use of WFI for waiting for a thread to arrive. */ + +__tx_ts_wait: + CPSID i // Disable interrupts + LDR r1, [r2] // Pickup the next thread to execute pointer + STR r1, [r0] // Store it in the current pointer + CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! +#ifdef TX_ENABLE_WFI + DSB // Ensure no outstanding memory transactions + WFI // Wait for interrupt + ISB // Ensure pipeline is flushed +#endif + CPSIE i // Enable interrupts + B __tx_ts_wait // Loop to continue waiting + + /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are + already in the handler! */ +__tx_ts_ready: + MOV r7, #0x08000000 // Build clear PendSV value + MOV r8, #0xE000E000 // Build base NVIC address + STR r7, [r8, #0xD04] // Clear any PendSV + + /* Re-enable interrupts and restore new thread. */ + CPSIE i // Enable interrupts + B __tx_ts_restore // Restore the thread + + +#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) + // SVC_Handler is not needed when ThreadX is running in single mode. + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global SVC_Handler + .thumb_func +.type SVC_Handler, function +SVC_Handler: + TST lr, #0x04 // Determine return stack from EXC_RETURN bit 2 + ITE EQ + MRSEQ r0, MSP // Get MSP if return stack is MSP + MRSNE r0, PSP // Get PSP if return stack is PSP + + LDR r1, [r0,#24] // Load saved PC from stack + LDRB r1, [r1,#-2] // Load SVC number + + CMP r1, #1 // Is it a secure stack allocate request? + BEQ _tx_svc_secure_alloc // Yes, go there + + CMP r1, #2 // Is it a secure stack free request? + BEQ _tx_svc_secure_free // Yes, go there + + // Unknown SVC argument - just return + BX lr + +_tx_svc_secure_alloc: + PUSH {r0,lr} // Save SP and EXC_RETURN + LDM r0, {r0-r3} // Load function parameters from stack + BL _tx_thread_secure_mode_stack_allocate + POP {r12,lr} // Restore SP and EXC_RETURN + STR r0,[r12] // Store function return value + BX lr +_tx_svc_secure_free: + PUSH {r0,lr} // Save SP and EXC_RETURN + LDM r0, {r0-r3} // Load function parameters from stack + BL _tx_thread_secure_mode_stack_free + POP {r12,lr} // Restore SP and EXC_RETURN + STR r0,[r12] // Store function return value + BX lr +#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE + + + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_vfp_access + .thumb_func +.type _tx_vfp_access, function +_tx_vfp_access: + VMOV.F32 s0, s0 // Simply access the VFP + BX lr // Return to caller +.end diff --git a/ports/cortex_m33/gnu/src/tx_thread_secure_stack.c b/ports/cortex_m33/gnu/src/tx_thread_secure_stack.c new file mode 100644 index 00000000..79d8e9e0 --- /dev/null +++ b/ports/cortex_m33/gnu/src/tx_thread_secure_stack.c @@ -0,0 +1,475 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +#include "tx_api.h" + +/* If TX_SINGLE_MODE_SECURE or TX_SINGLE_MODE_NON_SECURE is defined, + no secure stack functionality is needed. */ +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + +#define TX_SOURCE_CODE + +#include "tx_secure_interface.h" /* Interface for NS code. */ + +/* Minimum size of secure stack. */ +#ifndef TX_THREAD_SECURE_STACK_MINIMUM +#define TX_THREAD_SECURE_STACK_MINIMUM 256 +#endif +/* Maximum size of secure stack. */ +#ifndef TX_THREAD_SECURE_STACK_MAXIMUM +#define TX_THREAD_SECURE_STACK_MAXIMUM 1024 +#endif + +/* Secure stack info struct to hold stack start, stack limit, + current stack pointer, and pointer to owning thread. + This will be allocated for each thread with a secure stack. */ +typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT +{ + VOID *tx_thread_secure_stack_ptr; /* Thread's secure stack current pointer */ + VOID *tx_thread_secure_stack_start; /* Thread's secure stack start address */ + VOID *tx_thread_secure_stack_limit; /* Thread's secure stack limit */ + TX_THREAD *tx_thread_ptr; /* Keep track of thread for error handling */ +} TX_THREAD_SECURE_STACK_INFO; + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_initialize Cortex-M33/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes secure mode to use PSP stack. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __get_CONTROL Intrinsic to get CONTROL */ +/* __set_CONTROL Intrinsic to set CONTROL */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +void _tx_thread_secure_stack_initialize(void) +{ + ULONG control; + + /* Set secure mode to use PSP. */ + asm volatile("MRS %0, CONTROL" : "=r" (control)); /* Get CONTROL register. */ + control |= 2; /* Use PSP. */ + asm volatile("MSR CONTROL, %0" :: "r" (control)); /* Set CONTROL register. */ + + /* Set process stack pointer and stack limit to 0 to throw exception when a thread + without a secure stack calls a secure function that tries to use secure stack. */ + asm volatile("MSR PSPLIM, %0" :: "r" (0)); + asm volatile("MSR PSP, %0" :: "r" (0)); + + return; +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_mode_stack_allocate Cortex-M33/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function allocates a thread's secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* stack_size Size of stack to allocates */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_SIZE_ERROR Invalid stack size */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* calloc Compiler's calloc function */ +/* malloc Compiler's malloc function */ +/* free Compiler's free() function */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* */ +/* CALLED BY */ +/* */ +/* SVC Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +{ +UINT status; +TX_THREAD_SECURE_STACK_INFO *info_ptr; +UCHAR *stack_mem; +ULONG ipsr; +ULONG psplim_ns; + + status = TX_SUCCESS; + + /* Make sure function is called from interrupt (threads should not call). */ + asm volatile("MRS %0, IPSR" : "=r" (ipsr)); /* Get IPSR register. */ + if (ipsr == 0) + { + status = TX_CALLER_ERROR; + } + else if (stack_size < TX_THREAD_SECURE_STACK_MINIMUM || stack_size > TX_THREAD_SECURE_STACK_MAXIMUM) + { + status = TX_SIZE_ERROR; + } + + /* Check if thread already has secure stack allocated. */ + else if (thread_ptr -> tx_thread_secure_stack_context != 0) + { + status = TX_THREAD_ERROR; + } + + else + { + /* Allocate space for secure stack info. */ + info_ptr = calloc(1, sizeof(TX_THREAD_SECURE_STACK_INFO)); + + if(info_ptr != TX_NULL) + { + /* If stack info allocated, allocate a stack. */ + stack_mem = malloc(stack_size); + + if(stack_mem != TX_NULL) + { + /* Secure stack has been allocated, save in the stack info struct. */ + info_ptr -> tx_thread_secure_stack_limit = stack_mem; + info_ptr -> tx_thread_secure_stack_start = stack_mem + stack_size; + info_ptr -> tx_thread_secure_stack_ptr = info_ptr -> tx_thread_secure_stack_start; + info_ptr -> tx_thread_ptr = thread_ptr; + + /* Save info pointer in thread. */ + thread_ptr -> tx_thread_secure_stack_context = info_ptr; + + /* Check if this thread is running by looking at its stack start and PSPLIM_NS */ + asm volatile("MRS %0, PSPLIM_NS" : "=r" (psplim_ns)); /* Get PSPLIM_NS register. */ + if(((ULONG) thread_ptr -> tx_thread_stack_start & 0xFFFFFFF8) == psplim_ns) + { + /* If this thread is running, set Secure PSP and PSPLIM. */ + asm volatile("MSR PSPLIM, %0" :: "r" ((ULONG)(info_ptr -> tx_thread_secure_stack_limit))); + asm volatile("MSR PSP, %0" :: "r" ((ULONG)(info_ptr -> tx_thread_secure_stack_ptr))); + } + } + + else + { + /* Stack not allocated, free the info struct. */ + free(info_ptr); + status = TX_NO_MEMORY; + } + } + + else + { + status = TX_NO_MEMORY; + } + } + + return(status); +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_mode_stack_free Cortex-M33/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function frees a thread's secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* free Compiler's free() function */ +/* */ +/* CALLED BY */ +/* */ +/* SVC Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr) +{ +UINT status; +TX_THREAD_SECURE_STACK_INFO *info_ptr; +ULONG ipsr; + + status = TX_SUCCESS; + + /* Pickup stack info from thread. */ + info_ptr = thread_ptr -> tx_thread_secure_stack_context; + + /* Make sure function is called from interrupt (threads should not call). */ + asm volatile("MRS %0, IPSR" : "=r" (ipsr)); /* Get IPSR register. */ + if (ipsr == 0) + { + status = TX_CALLER_ERROR; + } + + /* Check that this secure context is for this thread. */ + else if (info_ptr -> tx_thread_ptr != thread_ptr) + { + status = TX_THREAD_ERROR; + } + + else + { + + /* Free secure stack. */ + free(info_ptr -> tx_thread_secure_stack_limit); + + /* Free info struct. */ + free(info_ptr); + + /* Clear secure context from thread. */ + thread_ptr -> tx_thread_secure_stack_context = 0; + } + + return(status); +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_context_save Cortex-M33/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves context of the secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* __get_PSP Intrinsic to get PSP */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* */ +/* CALLED BY */ +/* */ +/* PendSV Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr) +{ +TX_THREAD_SECURE_STACK_INFO *info_ptr; +ULONG sp; +ULONG ipsr; + + /* This function should be called from scheduler only. */ + asm volatile("MRS %0, IPSR" : "=r" (ipsr)); /* Get IPSR register. */ + if (ipsr == 0) + { + return; + } + + /* Pickup the secure context pointer. */ + info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); + + /* Check that this secure context is for this thread. */ + if (info_ptr -> tx_thread_ptr != thread_ptr) + { + return; + } + + /* Check that stack pointer is in range */ + asm volatile("MRS %0, PSP" : "=r" (sp)); /* Get PSP register. */ + if ((sp < (ULONG)info_ptr -> tx_thread_secure_stack_limit) || + (sp > (ULONG)info_ptr -> tx_thread_secure_stack_start)) + { + return; + } + + /* Save stack pointer. */ + *(ULONG *) info_ptr -> tx_thread_secure_stack_ptr = sp; + + /* Set process stack pointer and stack limit to 0 to throw exception when a thread + without a secure stack calls a secure function that tries to use secure stack. */ + asm volatile("MSR PSPLIM, %0" :: "r" (0)); + asm volatile("MSR PSP, %0" :: "r" (0)); + + return; +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_context_restore Cortex-M33/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores context of the secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* */ +/* CALLED BY */ +/* */ +/* PendSV Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr) +{ +TX_THREAD_SECURE_STACK_INFO *info_ptr; +ULONG ipsr; + + /* This function should be called from scheduler only. */ + asm volatile("MRS %0, IPSR" : "=r" (ipsr)); /* Get IPSR register. */ + if (ipsr == 0) + { + return; + } + + /* Pickup the secure context pointer. */ + info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); + + /* Check that this secure context is for this thread. */ + if (info_ptr -> tx_thread_ptr != thread_ptr) + { + return; + } + + /* Set stack pointer and limit. */ + asm volatile("MSR PSPLIM, %0" :: "r" ((ULONG)info_ptr -> tx_thread_secure_stack_limit)); + asm volatile("MSR PSP, %0" :: "r" ((ULONG)info_ptr -> tx_thread_secure_stack_ptr)); + + return; +} + +#endif diff --git a/ports/cortex_m33/gnu/src/tx_thread_secure_stack_allocate.S b/ports/cortex_m33/gnu/src/tx_thread_secure_stack_allocate.S new file mode 100644 index 00000000..333a95a3 --- /dev/null +++ b/ports/cortex_m33/gnu/src/tx_thread_secure_stack_allocate.S @@ -0,0 +1,85 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_allocate Cortex-M33/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function enters the SVC handler to allocate a secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* stack_size Size of secure stack to */ +/* allocate */ +/* */ +/* OUTPUT */ +/* */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* SVC 1 */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_secure_stack_allocate + .thumb_func +.type _tx_thread_secure_stack_allocate, function +_tx_thread_secure_stack_allocate: +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + MRS r3, PRIMASK // Save interrupt mask + CPSIE i // Enable interrupts for SVC call + SVC 1 + CMP r3, #0 // If interrupts enabled, just return + BEQ _alloc_return_interrupt_enabled + CPSID i // Otherwise, disable interrupts +#else + MOV r0, #0xFF // Feature not enabled +#endif +_alloc_return_interrupt_enabled: + BX lr + .end diff --git a/ports/cortex_m33/gnu/src/tx_thread_secure_stack_free.S b/ports/cortex_m33/gnu/src/tx_thread_secure_stack_free.S new file mode 100644 index 00000000..5152414b --- /dev/null +++ b/ports/cortex_m33/gnu/src/tx_thread_secure_stack_free.S @@ -0,0 +1,83 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_free Cortex-M33/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function enters the SVC handler to free a secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* SVC 2 */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_secure_stack_free + .thumb_func +.type _tx_thread_secure_stack_free, function +_tx_thread_secure_stack_free: +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + MRS r3, PRIMASK // Save interrupt mask + CPSIE i // Enable interrupts for SVC call + SVC 2 + CMP r3, #0 // If interrupts enabled, just return + BEQ _free_return_interrupt_enabled + CPSID i // Otherwise, disable interrupts +#else + MOV r0, #0xFF // Feature not enabled +#endif +_free_return_interrupt_enabled: + BX lr + .end diff --git a/ports/cortex_m33/gnu/src/tx_thread_stack_build.S b/ports/cortex_m33/gnu/src/tx_thread_stack_build.S new file mode 100644 index 00000000..5bda6d11 --- /dev/null +++ b/ports/cortex_m33/gnu/src/tx_thread_stack_build.S @@ -0,0 +1,140 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build Cortex-M33/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_stack_build + .thumb_func +.type _tx_thread_stack_build, function +_tx_thread_stack_build: + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-M33 should look like the following after it is built: + + Stack Top: + LR Interrupted LR (LR at time of PENDSV) + r4 Initial value for r4 + r5 Initial value for r5 + r6 Initial value for r6 + r7 Initial value for r7 + r8 Initial value for r8 + r9 Initial value for r9 + r10 Initial value for r10 + r11 Initial value for r11 + r0 Initial value for r0 (Hardware stack starts here!!) + r1 Initial value for r1 + r2 Initial value for r2 + r3 Initial value for r3 + r12 Initial value for r12 + lr Initial value for lr + pc Initial value for pc + xPSR Initial value for xPSR + + Stack Bottom: (higher memory address) */ + + LDR r2, [r0, #16] // Pickup end of stack area + BIC r2, r2, #0x7 // Align frame for 8-byte alignment + SUB r2, r2, #68 // Subtract frame size +#ifdef TX_SINGLE_MODE_SECURE + LDR r3, =0xFFFFFFFD // Build initial LR value for secure mode +#else + LDR r3, =0xFFFFFFBC // Build initial LR value to return to non-secure PSP +#endif + STR r3, [r2, #0] // Save on the stack + + /* Actually build the stack frame. */ + + MOV r3, #0 // Build initial register value + STR r3, [r2, #4] // Store initial r4 + STR r3, [r2, #8] // Store initial r5 + STR r3, [r2, #12] // Store initial r6 + STR r3, [r2, #16] // Store initial r7 + STR r3, [r2, #20] // Store initial r8 + STR r3, [r2, #24] // Store initial r9 + STR r3, [r2, #28] // Store initial r10 + STR r3, [r2, #32] // Store initial r11 + + /* Hardware stack follows. */ + + STR r3, [r2, #36] // Store initial r0 + STR r3, [r2, #40] // Store initial r1 + STR r3, [r2, #44] // Store initial r2 + STR r3, [r2, #48] // Store initial r3 + STR r3, [r2, #52] // Store initial r12 + MOV r3, #0xFFFFFFFF // Poison EXC_RETURN value + STR r3, [r2, #56] // Store initial lr + STR r1, [r2, #60] // Store initial pc + MOV r3, #0x01000000 // Only T-bit need be set + STR r3, [r2, #64] // Store initial xPSR + + /* Setup stack pointer. */ + // thread_ptr -> tx_thread_stack_ptr = r2; + + STR r2, [r0, #8] // Save stack pointer in thread's + // control block + BX lr // Return to caller +// } + .end diff --git a/ports/cortex_m33/gnu/src/tx_thread_stack_error_handler.c b/ports/cortex_m33/gnu/src/tx_thread_stack_error_handler.c new file mode 100644 index 00000000..8d892e6c --- /dev/null +++ b/ports/cortex_m33/gnu/src/tx_thread_stack_error_handler.c @@ -0,0 +1,93 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + +/* Define the global function pointer for stack error handling. If a stack error is + detected and the application has registered a stack error handler, it will be + called via this function pointer. */ + +VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_error_handler Cortex-M33/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes stack errors detected during run-time. */ +/* */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_terminate */ +/* _tx_thread_application_stack_error_handler */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX internal code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) +{ + #ifndef TX_THREAD_NO_TERMINATE_STACK_ERROR + /* Is there a thread? */ + if (thread_ptr) + { + /* Terminate the current thread. */ + _tx_thread_terminate(_tx_thread_current_ptr); + } + #endif + + /* Determine if the application has registered an error handler. */ + if (_tx_thread_application_stack_error_handler != TX_NULL) + { + /* Yes, an error handler is present, simply call the application error handler. */ + (_tx_thread_application_stack_error_handler)(thread_ptr); + } +} diff --git a/ports/cortex_m33/gnu/src/tx_thread_stack_error_notify.c b/ports/cortex_m33/gnu/src/tx_thread_stack_error_notify.c new file mode 100644 index 00000000..6c2006ad --- /dev/null +++ b/ports/cortex_m33/gnu/src/tx_thread_stack_error_notify.c @@ -0,0 +1,96 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_trace.h" + +extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_error_notify Cortex-M33/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application stack error handler. If */ +/* ThreadX detects a stack error, this application handler is called. */ +/* */ +/* */ +/* INPUT */ +/* */ +/* stack_error_handler Pointer to stack error */ +/* handler, TX_NULL to disable */ +/* */ +/* OUTPUT */ +/* */ +/* status Service return status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr)) +{ + +TX_INTERRUPT_SAVE_AREA + + /* Disable interrupts. */ + TX_DISABLE + + /* Make entry in event log. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_STACK_ERROR_NOTIFY, 0, 0, 0, 0, TX_TRACE_THREAD_EVENTS) + + /* Make entry in event log. */ + TX_EL_THREAD_STACK_ERROR_NOTIFY_INSERT + + /* Setup global thread stack error handler. */ + _tx_thread_application_stack_error_handler = stack_error_handler; + + /* Restore interrupts. */ + TX_RESTORE + + /* Return success to caller. */ + return(TX_SUCCESS); +} diff --git a/ports/cortex_m33/gnu/src/tx_thread_system_return.S b/ports/cortex_m33/gnu/src/tx_thread_system_return.S new file mode 100644 index 00000000..a053e85f --- /dev/null +++ b/ports/cortex_m33/gnu/src/tx_thread_system_return.S @@ -0,0 +1,89 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return Cortex-M33/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the ThreadX system. Only a */ +/* minimal context is saved since the compiler assumes temp registers */ +/* are going to get slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_system_return(VOID) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_system_return + .thumb_func +.type _tx_thread_system_return, function +_tx_thread_system_return: + /* Return to real scheduler via PendSV. Note that this routine is often + replaced with in-line assembly in tx_port.h to improved performance. */ + + MOV r0, #0x10000000 // Load PENDSVSET bit + LDR r1, =0xE000E000 // Load NVIC base + STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + MRS r0, IPSR // Pickup IPSR + CMP r0, #0 // Is it a thread returning? + BNE _isr_context // If ISR, skip interrupt enable + MRS r1, PRIMASK // Thread context returning, pickup PRIMASK + CPSIE i // Enable interrupts + MSR PRIMASK, r1 // Restore original interrupt posture +_isr_context: + BX lr // Return to caller +// } + .end diff --git a/ports/cortex_m33/gnu/src/tx_timer_interrupt.S b/ports/cortex_m33/gnu/src/tx_timer_interrupt.S new file mode 100644 index 00000000..5e5311a3 --- /dev/null +++ b/ports/cortex_m33/gnu/src/tx_timer_interrupt.S @@ -0,0 +1,246 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt Cortex-M33/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_timer_interrupt(VOID) +{ */ + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_timer_interrupt + .thumb_func +.type _tx_timer_interrupt, function +_tx_timer_interrupt: + + /* Upon entry to this routine, it is assumed that context save has already + been called, and therefore the compiler scratch registers are available + for use. */ + + /* Increment the system clock. */ + // _tx_timer_system_clock++; + + LDR r1, =_tx_timer_system_clock // Pickup address of system clock + LDR r0, [r1, #0] // Pickup system clock + ADD r0, r0, #1 // Increment system clock + STR r0, [r1, #0] // Store new system clock + + /* Test for time-slice expiration. */ + // if (_tx_timer_time_slice) + // { + + LDR r3, =_tx_timer_time_slice // Pickup address of time-slice + LDR r2, [r3, #0] // Pickup time-slice + CBZ r2, __tx_timer_no_time_slice // Is it non-active? + // Yes, skip time-slice processing + + /* Decrement the time_slice. */ + // _tx_timer_time_slice--; + + SUB r2, r2, #1 // Decrement the time-slice + STR r2, [r3, #0] // Store new time-slice value + + /* Check for expiration. */ + // if (__tx_timer_time_slice == 0) + + CBNZ r2, __tx_timer_no_time_slice // Has it expired? + + /* Set the time-slice expired flag. */ + // _tx_timer_expired_time_slice = TX_TRUE; + + LDR r3, =_tx_timer_expired_time_slice // Pickup address of expired flag + MOV r0, #1 // Build expired value + STR r0, [r3, #0] // Set time-slice expiration flag + + // } + +__tx_timer_no_time_slice: + + /* Test for timer expiration. */ + // if (*_tx_timer_current_ptr) + // { + + LDR r1, =_tx_timer_current_ptr // Pickup current timer pointer address + LDR r0, [r1, #0] // Pickup current timer + LDR r2, [r0, #0] // Pickup timer list entry + CBZ r2, __tx_timer_no_timer // Is there anything in the list? + // No, just increment the timer + + /* Set expiration flag. */ + // _tx_timer_expired = TX_TRUE; + + LDR r3, =_tx_timer_expired // Pickup expiration flag address + MOV r2, #1 // Build expired value + STR r2, [r3, #0] // Set expired flag + B __tx_timer_done // Finished timer processing + + // } + // else + // { +__tx_timer_no_timer: + + /* No timer expired, increment the timer pointer. */ + // _tx_timer_current_ptr++; + + ADD r0, r0, #4 // Move to next timer + + /* Check for wrap-around. */ + // if (_tx_timer_current_ptr == _tx_timer_list_end) + + LDR r3, =_tx_timer_list_end // Pickup addr of timer list end + LDR r2, [r3, #0] // Pickup list end + CMP r0, r2 // Are we at list end? + BNE __tx_timer_skip_wrap // No, skip wrap-around logic + + /* Wrap to beginning of list. */ + // _tx_timer_current_ptr = _tx_timer_list_start; + + LDR r3, =_tx_timer_list_start // Pickup addr of timer list start + LDR r0, [r3, #0] // Set current pointer to list start + +__tx_timer_skip_wrap: + + STR r0, [r1, #0] // Store new current timer pointer + // } + +__tx_timer_done: + + + /* See if anything has expired. */ + // if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) + // { + + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of expired flag + LDR r2, [r3, #0] // Pickup time-slice expired flag + CBNZ r2, __tx_something_expired // Did a time-slice expire? + // If non-zero, time-slice expired + LDR r1, =_tx_timer_expired // Pickup addr of other expired flag + LDR r0, [r1, #0] // Pickup timer expired flag + CBZ r0, __tx_timer_nothing_expired // Did a timer expire? + // No, nothing expired + +__tx_something_expired: + + STMDB sp!, {r0, lr} // Save the lr register on the stack + // and save r0 just to keep 8-byte alignment + + /* Did a timer expire? */ + // if (_tx_timer_expired) + // { + + LDR r1, =_tx_timer_expired // Pickup addr of expired flag + LDR r0, [r1, #0] // Pickup timer expired flag + CBZ r0, __tx_timer_dont_activate // Check for timer expiration + // If not set, skip timer activation + + /* Process timer expiration. */ + // _tx_timer_expiration_process(); + + BL _tx_timer_expiration_process // Call the timer expiration handling routine + + // } +__tx_timer_dont_activate: + + /* Did time slice expire? */ + // if (_tx_timer_expired_time_slice) + // { + + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of time-slice expired + LDR r2, [r3, #0] // Pickup the actual flag + CBZ r2, __tx_timer_not_ts_expiration // See if the flag is set + // No, skip time-slice processing + + /* Time slice interrupted thread. */ + // _tx_thread_time_slice(); + + BL _tx_thread_time_slice // Call time-slice processing + LDR r0, =_tx_thread_preempt_disable // Build address of preempt disable flag + LDR r1, [r0] // Is the preempt disable flag set? + CBNZ r1, __tx_timer_skip_time_slice // Yes, skip the PendSV logic + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r0] // Pickup the current thread pointer + LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address + LDR r3, [r2] // Pickup the execute thread pointer + LDR r0, =0xE000ED04 // Build address of control register + MOV r2, 0x10000000 // Build value for PendSV bit + CMP r1, r3 // Are they the same? + BEQ __tx_timer_skip_time_slice // If the same, there was no time-slice performed + STR r2, [r0] // Not the same, issue the PendSV for preemption +__tx_timer_skip_time_slice: + + // } + +__tx_timer_not_ts_expiration: + + LDMIA sp!, {r0, lr} // Recover lr register (r0 is just there for + + // } + +__tx_timer_nothing_expired: + + DSB // Complete all memory access + BX lr // Return to caller + +// } + .end diff --git a/ports/cortex_m33/gnu/src/txe_thread_secure_stack_allocate.c b/ports/cortex_m33/gnu/src/txe_thread_secure_stack_allocate.c new file mode 100644 index 00000000..9ad9b439 --- /dev/null +++ b/ports/cortex_m33/gnu/src/txe_thread_secure_stack_allocate.c @@ -0,0 +1,119 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_secure_stack_allocate Cortex-M33/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the secure stack allocate */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* stack_size Size of secure stack to */ +/* allocate */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_secure_stack_allocate Actual stack alloc function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +{ +#if defined(TX_SINGLE_MODE_SECURE) || defined(TX_SINGLE_MODE_NON_SECURE) + return(TX_FEATURE_NOT_ENABLED); +#else +UINT status; + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid thread pointer. */ + if (thread_ptr == TX_NULL) + { + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Now check for invalid thread ID. */ + else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) + { + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Check for interrupt call. */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + /* Is call from an interrupt and not initialization? */ + if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS) + { + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + /* Call actual secure stack allocate function. */ + status = _tx_thread_secure_stack_allocate(thread_ptr, stack_size); + } + + /* Return completion status. */ + return(status); +#endif +} diff --git a/ports/cortex_m33/gnu/src/txe_thread_secure_stack_free.c b/ports/cortex_m33/gnu/src/txe_thread_secure_stack_free.c new file mode 100644 index 00000000..3b9f2f2f --- /dev/null +++ b/ports/cortex_m33/gnu/src/txe_thread_secure_stack_free.c @@ -0,0 +1,120 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_secure_stack_free Cortex-M33/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the secure stack free */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_secure_stack_free Actual stack free function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) +{ +#if defined(TX_SINGLE_MODE_SECURE) || defined(TX_SINGLE_MODE_NON_SECURE) + return(TX_FEATURE_NOT_ENABLED); +#else +UINT status; + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid thread pointer. */ + if (thread_ptr == TX_NULL) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Now check for invalid thread ID. */ + else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Check for interrupt call. */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + /* Is call from an interrupt and not initialization? */ + if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS) + { + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + + /* Call actual secure stack allocate function. */ + status = _tx_thread_secure_stack_free(thread_ptr); + } + + /* Return completion status. */ + return(status); +#endif +} diff --git a/ports/cortex_m33/iar/inc/tx_port.h b/ports/cortex_m33/iar/inc/tx_port.h index fceae6ec..5661f114 100644 --- a/ports/cortex_m33/iar/inc/tx_port.h +++ b/ports/cortex_m33/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M33/IAR */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -556,7 +556,7 @@ __istate_t interrupt_save; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33/IAR Version 6.0.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33/IAR Version 6.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m33/iar/inc/tx_secure_interface.h b/ports/cortex_m33/iar/inc/tx_secure_interface.h index e2133c88..c2779f40 100644 --- a/ports/cortex_m33/iar/inc/tx_secure_interface.h +++ b/ports/cortex_m33/iar/inc/tx_secure_interface.h @@ -26,7 +26,7 @@ /* COMPONENT DEFINITION RELEASE */ /* */ /* tx_secure_interface.h PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -42,7 +42,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ diff --git a/ports/cortex_m33/iar/readme_threadx.txt b/ports/cortex_m33/iar/readme_threadx.txt index b804225c..c808670d 100644 --- a/ports/cortex_m33/iar/readme_threadx.txt +++ b/ports/cortex_m33/iar/readme_threadx.txt @@ -198,14 +198,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -08-14-2020 ThreadX update of Cortex-M33/IAR port. The following files were - changed/added for port specific version 6.0.2: - - tx_thread_context_restore.s Remove execution profile kit call. - tx_thread_context_save.s Remove execution profile kit call. - *.s Modified comments and whitespace. - -06-30-2020 Initial ThreadX 6.0.1 version for Cortex-M33 using IAR's ARM tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-M33 using IAR's ARM tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_m33/iar/src/tx_initialize_low_level.s b/ports/cortex_m33/iar/src/tx_initialize_low_level.s index 96ddc643..27922ca2 100644 --- a/ports/cortex_m33/iar/src/tx_initialize_low_level.s +++ b/ports/cortex_m33/iar/src/tx_initialize_low_level.s @@ -48,7 +48,7 @@ __tx_free_memory_start ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level Cortex-M33/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ @@ -81,10 +81,7 @@ __tx_free_memory_start ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_m33/iar/src/tx_misra.s b/ports/cortex_m33/iar/src/tx_misra.s index 0edc32a1..acb85cc9 100644 --- a/ports/cortex_m33/iar/src/tx_misra.s +++ b/ports/cortex_m33/iar/src/tx_misra.s @@ -101,7 +101,7 @@ SECTION `.data`:DATA:REORDER:NOROOT(2) DATA -// 51 CHAR _tx_version_id[100] = "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX 6.0 MISRA C Compliant *"; +// 51 CHAR _tx_version_id[100] = "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX 6.1 MISRA C Compliant *"; _tx_version_id: DC8 43H, 6FH, 70H, 79H, 72H, 69H, 67H, 68H DC8 74H, 20H, 28H, 63H, 29H, 20H, 31H, 39H diff --git a/ports/cortex_m33/iar/src/tx_thread_context_restore.s b/ports/cortex_m33/iar/src/tx_thread_context_restore.s index 690652d9..3217ef18 100644 --- a/ports/cortex_m33/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_m33/iar/src/tx_thread_context_restore.s @@ -28,7 +28,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore Cortex-M33/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ @@ -57,10 +57,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), remove */ -;/* EPK, clean up whitespace */ -;/* resulting in version 6.0.2 */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m33/iar/src/tx_thread_context_save.s b/ports/cortex_m33/iar/src/tx_thread_context_save.s index df77906f..49f55f4f 100644 --- a/ports/cortex_m33/iar/src/tx_thread_context_save.s +++ b/ports/cortex_m33/iar/src/tx_thread_context_save.s @@ -28,7 +28,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save Cortex-M33/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ @@ -57,10 +57,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), remove */ -;/* EPK, clean up whitespace */ -;/* resulting in version 6.0.2 */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -73,4 +70,3 @@ _tx_thread_context_save: BX lr ;} END - diff --git a/ports/cortex_m33/iar/src/tx_thread_interrupt_control.s b/ports/cortex_m33/iar/src/tx_thread_interrupt_control.s index d1308939..faa06ed3 100644 --- a/ports/cortex_m33/iar/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m33/iar/src/tx_thread_interrupt_control.s @@ -28,7 +28,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control Cortex-M33/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ @@ -58,10 +58,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_m33/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_m33/iar/src/tx_thread_interrupt_disable.s index f1148371..fb01c9d1 100644 --- a/ports/cortex_m33/iar/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m33/iar/src/tx_thread_interrupt_disable.s @@ -28,7 +28,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_disable Cortex-M33/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ @@ -58,10 +58,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(UINT new_posture) diff --git a/ports/cortex_m33/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_m33/iar/src/tx_thread_interrupt_restore.s index e5cbbaf8..ce4da3c3 100644 --- a/ports/cortex_m33/iar/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m33/iar/src/tx_thread_interrupt_restore.s @@ -28,7 +28,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-M33/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ @@ -58,10 +58,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_interrupt_restore(UINT new_posture) diff --git a/ports/cortex_m33/iar/src/tx_thread_schedule.s b/ports/cortex_m33/iar/src/tx_thread_schedule.s index 37c0397a..e8962618 100644 --- a/ports/cortex_m33/iar/src/tx_thread_schedule.s +++ b/ports/cortex_m33/iar/src/tx_thread_schedule.s @@ -41,7 +41,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M33/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ @@ -73,10 +73,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_m33/iar/src/tx_thread_secure_stack.c b/ports/cortex_m33/iar/src/tx_thread_secure_stack.c index 7d4a4b2e..d1a9d182 100644 --- a/ports/cortex_m33/iar/src/tx_thread_secure_stack.c +++ b/ports/cortex_m33/iar/src/tx_thread_secure_stack.c @@ -58,7 +58,7 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_initialize Cortex-M33/IAR */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -90,7 +90,7 @@ typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) @@ -115,7 +115,7 @@ void _tx_thread_secure_stack_initialize(void) /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_mode_stack_allocate PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -154,7 +154,7 @@ void _tx_thread_secure_stack_initialize(void) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) @@ -237,7 +237,7 @@ UCHAR *stack_mem; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_mode_stack_free PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -269,7 +269,7 @@ UCHAR *stack_mem; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) @@ -318,7 +318,7 @@ TX_THREAD_SECURE_STACK_INFO *info_ptr; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_context_save PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -350,7 +350,7 @@ TX_THREAD_SECURE_STACK_INFO *info_ptr; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) @@ -400,7 +400,7 @@ ULONG sp; /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_context_restore PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -431,7 +431,7 @@ ULONG sp; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ __attribute__((cmse_nonsecure_entry)) diff --git a/ports/cortex_m33/iar/src/tx_thread_secure_stack_allocate.s b/ports/cortex_m33/iar/src/tx_thread_secure_stack_allocate.s index 650c25db..817746bb 100644 --- a/ports/cortex_m33/iar/src/tx_thread_secure_stack_allocate.s +++ b/ports/cortex_m33/iar/src/tx_thread_secure_stack_allocate.s @@ -28,7 +28,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_secure_stack_allocate Cortex-M33/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ @@ -59,10 +59,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) diff --git a/ports/cortex_m33/iar/src/tx_thread_secure_stack_free.s b/ports/cortex_m33/iar/src/tx_thread_secure_stack_free.s index 5b939bb5..204b40c2 100644 --- a/ports/cortex_m33/iar/src/tx_thread_secure_stack_free.s +++ b/ports/cortex_m33/iar/src/tx_thread_secure_stack_free.s @@ -28,7 +28,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_secure_stack_free Cortex-M33/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ @@ -57,10 +57,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) diff --git a/ports/cortex_m33/iar/src/tx_thread_stack_build.s b/ports/cortex_m33/iar/src/tx_thread_stack_build.s index 25c38cfd..e891b8ff 100644 --- a/ports/cortex_m33/iar/src/tx_thread_stack_build.s +++ b/ports/cortex_m33/iar/src/tx_thread_stack_build.s @@ -28,7 +28,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build Cortex-M33/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ @@ -60,10 +60,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_m33/iar/src/tx_thread_stack_error_handler.c b/ports/cortex_m33/iar/src/tx_thread_stack_error_handler.c index 03fe6fdb..27ac5c42 100644 --- a/ports/cortex_m33/iar/src/tx_thread_stack_error_handler.c +++ b/ports/cortex_m33/iar/src/tx_thread_stack_error_handler.c @@ -39,7 +39,7 @@ VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_error_handler Cortex-M33/IAR */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -70,7 +70,7 @@ VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) diff --git a/ports/cortex_m33/iar/src/tx_thread_stack_error_notify.c b/ports/cortex_m33/iar/src/tx_thread_stack_error_notify.c index eb9b3928..328103b2 100644 --- a/ports/cortex_m33/iar/src/tx_thread_stack_error_notify.c +++ b/ports/cortex_m33/iar/src/tx_thread_stack_error_notify.c @@ -36,7 +36,7 @@ extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr) /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_error_notify Cortex-M33/IAR */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -68,7 +68,7 @@ extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr)) diff --git a/ports/cortex_m33/iar/src/tx_thread_system_return.s b/ports/cortex_m33/iar/src/tx_thread_system_return.s index 083dfefe..2f0c2c4e 100644 --- a/ports/cortex_m33/iar/src/tx_thread_system_return.s +++ b/ports/cortex_m33/iar/src/tx_thread_system_return.s @@ -28,7 +28,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return Cortex-M33/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ @@ -60,10 +60,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_m33/iar/src/tx_timer_interrupt.s b/ports/cortex_m33/iar/src/tx_timer_interrupt.s index 202bc4aa..bed202d4 100644 --- a/ports/cortex_m33/iar/src/tx_timer_interrupt.s +++ b/ports/cortex_m33/iar/src/tx_timer_interrupt.s @@ -42,7 +42,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt Cortex-M33/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ @@ -75,10 +75,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_m33/iar/src/txe_thread_secure_stack_allocate.c b/ports/cortex_m33/iar/src/txe_thread_secure_stack_allocate.c index ded0507d..3ff6fa68 100644 --- a/ports/cortex_m33/iar/src/txe_thread_secure_stack_allocate.c +++ b/ports/cortex_m33/iar/src/txe_thread_secure_stack_allocate.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_secure_stack_allocate PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -68,7 +68,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) diff --git a/ports/cortex_m33/iar/src/txe_thread_secure_stack_free.c b/ports/cortex_m33/iar/src/txe_thread_secure_stack_free.c index af49c7df..f8207c68 100644 --- a/ports/cortex_m33/iar/src/txe_thread_secure_stack_free.c +++ b/ports/cortex_m33/iar/src/txe_thread_secure_stack_free.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _txe_thread_secure_stack_free PORTABLE C */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -66,7 +66,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) diff --git a/ports/cortex_m4/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_m4/ac5/example_build/tx_initialize_low_level.s index 3ca267be..56a46f71 100644 --- a/ports/cortex_m4/ac5/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m4/ac5/example_build/tx_initialize_low_level.s @@ -97,7 +97,7 @@ Reset_Handler ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level Cortex-M4/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation. */ @@ -130,10 +130,7 @@ Reset_Handler ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_m4/ac5/inc/tx_port.h b/ports/cortex_m4/ac5/inc/tx_port.h index 76bccfa6..c220665b 100644 --- a/ports/cortex_m4/ac5/inc/tx_port.h +++ b/ports/cortex_m4/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M4/AC5 */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -454,7 +454,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/AC5 Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/AC5 Version 6.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m4/ac5/readme_threadx.txt b/ports/cortex_m4/ac5/readme_threadx.txt index 6664f394..9cf1f019 100644 --- a/ports/cortex_m4/ac5/readme_threadx.txt +++ b/ports/cortex_m4/ac5/readme_threadx.txt @@ -197,12 +197,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -08-14-2020 ThreadX update of Cortex-M4/AC5 port. The following files were - changed/added for port specific version 6.0.2: - tx_thread_context_save.s Fixed register names. - *.s Modified comments and whitespace. - -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M4 using AC5 tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-M4 using AC5 tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_m4/ac5/src/tx_thread_context_restore.s b/ports/cortex_m4/ac5/src/tx_thread_context_restore.s index 9f65cc8c..0ed36142 100644 --- a/ports/cortex_m4/ac5/src/tx_thread_context_restore.s +++ b/ports/cortex_m4/ac5/src/tx_thread_context_restore.s @@ -33,7 +33,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore Cortex-M4/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -67,10 +67,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m4/ac5/src/tx_thread_context_save.s b/ports/cortex_m4/ac5/src/tx_thread_context_save.s index aa86e10d..03ec67e6 100644 --- a/ports/cortex_m4/ac5/src/tx_thread_context_save.s +++ b/ports/cortex_m4/ac5/src/tx_thread_context_save.s @@ -33,7 +33,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save Cortex-M4/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -66,10 +66,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m4/ac5/src/tx_thread_interrupt_control.s b/ports/cortex_m4/ac5/src/tx_thread_interrupt_control.s index 9ca90dd7..ef983f17 100644 --- a/ports/cortex_m4/ac5/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m4/ac5/src/tx_thread_interrupt_control.s @@ -27,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control Cortex-M4/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -57,10 +57,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_m4/ac5/src/tx_thread_interrupt_disable.s b/ports/cortex_m4/ac5/src/tx_thread_interrupt_disable.s index 861fbbe8..b0b31cb0 100644 --- a/ports/cortex_m4/ac5/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m4/ac5/src/tx_thread_interrupt_disable.s @@ -27,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_disable Cortex-M4/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation. */ @@ -57,10 +57,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(UINT new_posture) diff --git a/ports/cortex_m4/ac5/src/tx_thread_interrupt_restore.s b/ports/cortex_m4/ac5/src/tx_thread_interrupt_restore.s index 1ef06c78..c7350e36 100644 --- a/ports/cortex_m4/ac5/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m4/ac5/src/tx_thread_interrupt_restore.s @@ -27,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-M4/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation. */ @@ -57,10 +57,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_interrupt_restore(UINT new_posture) diff --git a/ports/cortex_m4/ac5/src/tx_thread_schedule.s b/ports/cortex_m4/ac5/src/tx_thread_schedule.s index 158783fa..184477ff 100644 --- a/ports/cortex_m4/ac5/src/tx_thread_schedule.s +++ b/ports/cortex_m4/ac5/src/tx_thread_schedule.s @@ -39,7 +39,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M4/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -72,10 +72,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_m4/ac5/src/tx_thread_stack_build.s b/ports/cortex_m4/ac5/src/tx_thread_stack_build.s index 2b3b76f8..f548938b 100644 --- a/ports/cortex_m4/ac5/src/tx_thread_stack_build.s +++ b/ports/cortex_m4/ac5/src/tx_thread_stack_build.s @@ -20,15 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; ; AREA ||.text||, CODE, READONLY ;/**************************************************************************/ @@ -36,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build Cortex-M4/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -68,10 +59,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -122,7 +110,7 @@ _tx_thread_stack_build STR r3, [r2, #28] ; Store initial r10 STR r3, [r2, #32] ; Store initial r11 ; -; /* Hardware stack follows. / +; /* Hardware stack follows. */ ; STR r3, [r2, #36] ; Store initial r0 STR r3, [r2, #40] ; Store initial r1 diff --git a/ports/cortex_m4/ac5/src/tx_thread_system_return.s b/ports/cortex_m4/ac5/src/tx_thread_system_return.s index ece0b1cf..9c453e61 100644 --- a/ports/cortex_m4/ac5/src/tx_thread_system_return.s +++ b/ports/cortex_m4/ac5/src/tx_thread_system_return.s @@ -27,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return Cortex-M4/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -59,10 +59,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_m4/ac5/src/tx_timer_interrupt.s b/ports/cortex_m4/ac5/src/tx_timer_interrupt.s index 33793ad0..f5160174 100644 --- a/ports/cortex_m4/ac5/src/tx_timer_interrupt.s +++ b/ports/cortex_m4/ac5/src/tx_timer_interrupt.s @@ -42,7 +42,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt Cortex-M4/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -76,10 +76,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_m4/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_m4/ac6/example_build/sample_threadx/tx_initialize_low_level.S index 272484cc..29cedd0e 100644 --- a/ports/cortex_m4/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports/cortex_m4/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -47,7 +47,7 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* FUNCTION RELEASE */ @/* */ @/* _tx_initialize_low_level Cortex-M4/AC6 */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -80,10 +80,7 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_m4/ac6/inc/tx_port.h b/ports/cortex_m4/ac6/inc/tx_port.h index 98b2adea..b6eb3929 100644 --- a/ports/cortex_m4/ac6/inc/tx_port.h +++ b/ports/cortex_m4/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M4/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -485,7 +485,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/AC6 Version 6.0.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/AC6 Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_m4/ac6/readme_threadx.txt b/ports/cortex_m4/ac6/readme_threadx.txt index 928be3df..dfd53faf 100644 --- a/ports/cortex_m4/ac6/readme_threadx.txt +++ b/ports/cortex_m4/ac6/readme_threadx.txt @@ -211,12 +211,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -08-14-2020 ThreadX update of Cortex-M4/AC6 port. The following files were - changed/added for port specific version 6.0.2: - - *.S Modified comments and whitespace. - -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M4 using AC6 tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-M4 using AC6 tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_m4/ac6/src/tx_thread_context_restore.S b/ports/cortex_m4/ac6/src/tx_thread_context_restore.S index 49baa253..daa78a7a 100644 --- a/ports/cortex_m4/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_m4/ac6/src/tx_thread_context_restore.S @@ -38,7 +38,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_restore Cortex-M4/AC6 */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -72,10 +72,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m4/ac6/src/tx_thread_context_save.S b/ports/cortex_m4/ac6/src/tx_thread_context_save.S index ed1831f2..43f2e4c9 100644 --- a/ports/cortex_m4/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_m4/ac6/src/tx_thread_context_save.S @@ -33,7 +33,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_save Cortex-M4/AC6 */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -66,10 +66,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m4/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_m4/ac6/src/tx_thread_interrupt_control.S index c6facbc6..892509bc 100644 --- a/ports/cortex_m4/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m4/ac6/src/tx_thread_interrupt_control.S @@ -29,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_control Cortex-M4/AC6 */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -59,10 +59,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @/* UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_m4/ac6/src/tx_thread_schedule.S b/ports/cortex_m4/ac6/src/tx_thread_schedule.S index 614bf3c1..9edd6a99 100644 --- a/ports/cortex_m4/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_m4/ac6/src/tx_thread_schedule.S @@ -35,7 +35,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule Cortex-M4/AC6 */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -68,10 +68,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_m4/ac6/src/tx_thread_stack_build.S b/ports/cortex_m4/ac6/src/tx_thread_stack_build.S index 2dd6acd2..f2639031 100644 --- a/ports/cortex_m4/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_m4/ac6/src/tx_thread_stack_build.S @@ -29,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_stack_build Cortex-M4/AC6 */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -61,10 +61,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_m4/ac6/src/tx_thread_system_return.S b/ports/cortex_m4/ac6/src/tx_thread_system_return.S index e163c9dd..3fa421c3 100644 --- a/ports/cortex_m4/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_m4/ac6/src/tx_thread_system_return.S @@ -29,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_system_return Cortex-M4/AC6 */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -61,10 +61,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @/* VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_m4/ac6/src/tx_timer_interrupt.S b/ports/cortex_m4/ac6/src/tx_timer_interrupt.S index 72085640..4f1175da 100644 --- a/ports/cortex_m4/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_m4/ac6/src/tx_timer_interrupt.S @@ -40,7 +40,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_timer_interrupt Cortex-M4/AC6 */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -74,10 +74,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_m4/ghs/example_build/azure_rtos_workspace.gpj b/ports/cortex_m4/ghs/example_build/azure_rtos_workspace.gpj new file mode 100644 index 00000000..16d5ad2c --- /dev/null +++ b/ports/cortex_m4/ghs/example_build/azure_rtos_workspace.gpj @@ -0,0 +1,13 @@ +#!gbuild +primaryTarget=arm_standalone.tgt +[Project] + -bsp generic + -G + -littleendian + -cpu=cortexm4 + -fsingle +sample_threadx.gpj [Program] +sample_threadx_el.gpj [Program] +tx.gpj [Library] +txe.gpj [Library] +..\readme_threadx.txt diff --git a/ports/cortex_m4/ghs/example_build/reset.arm b/ports/cortex_m4/ghs/example_build/reset.arm new file mode 100644 index 00000000..29194564 --- /dev/null +++ b/ports/cortex_m4/ghs/example_build/reset.arm @@ -0,0 +1,40 @@ +# +# +#/* Define the Cortex-M4 vector area. */ +# + + .section ".reset", .text + .globl __vectors +__vectors: + .data.w __ghsend_stack # Reset and system stack ptr + .data.w __Reset_Handler # Reset goes to Reset Handler + .data.w __tx_NMIHandler # NMI + .data.w __tx_BadHandler # HardFault + .data.w 0 # MemManage + .data.w 0 # BusFault + .data.w 0 # UsageFault + .data.w 0 # 7 + .data.w 0 # 8 + .data.w 0 # 9 + .data.w 0 # 10 + .data.w __tx_SVCallHandler # SVCall + .data.w __tx_DBGHandler # Monitor + .data.w 0 # 13 + .data.w __tx_PendSVHandler # PendSV + .data.w __tx_SysTickHandler # SysTick + .data.w __tx_IntHandler # Int 0 + .data.w __tx_IntHandler # Int 1 + .data.w __tx_IntHandler # Int 2 + .data.w __tx_IntHandler # Int 3 + .type __vectors,$object + .size __vectors,.-__vectors +# +# + .globl __Reset_Handler +__Reset_Handler: + CPSID i # Disable interrupts + LDR r0,=_start # Build address of GHS startup code + BX r0 # Enter GHS startup + + .type __Reset_Handler,$function + .size __Reset_Handler,.-__Reset_Handler diff --git a/ports/cortex_m4/ghs/example_build/sample_threadx.c b/ports/cortex_m4/ghs/example_build/sample_threadx.c new file mode 100644 index 00000000..418ec634 --- /dev/null +++ b/ports/cortex_m4/ghs/example_build/sample_threadx.c @@ -0,0 +1,369 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_m4/ghs/example_build/sample_threadx.con b/ports/cortex_m4/ghs/example_build/sample_threadx.con new file mode 100644 index 00000000..477ffe12 --- /dev/null +++ b/ports/cortex_m4/ghs/example_build/sample_threadx.con @@ -0,0 +1,17 @@ +target_connection { + { + title = "Simulator" + type = "Custom" + short_type = "Custom" + args = "simarm -cpu=cortexm4 -fpu -rom_use_entry" + command = "simarm -cpu=cortexm4 -fpu -rom_use_entry" + logfile = "" + mode = "download" + setup_script = "" + run_mode_partner = "" + run_mode_policy = "" + sane = "yes" + log = "no" + timestamp = "0" + } +} diff --git a/ports/cortex_m4/ghs/example_build/sample_threadx.gpj b/ports/cortex_m4/ghs/example_build/sample_threadx.gpj new file mode 100644 index 00000000..b9b2c04c --- /dev/null +++ b/ports/cortex_m4/ghs/example_build/sample_threadx.gpj @@ -0,0 +1,11 @@ +#!gbuild +[Program] + -I../../../../common/inc + -I../../../../ports_common_green/inc + -I../inc +reset.arm +tx_initialize_low_level.arm +sample_threadx.c +tx.a +sample_threadx.ld +sample_threadx.con diff --git a/ports/cortex_m4/ghs/example_build/sample_threadx.ld b/ports/cortex_m4/ghs/example_build/sample_threadx.ld new file mode 100644 index 00000000..a5cfce73 --- /dev/null +++ b/ports/cortex_m4/ghs/example_build/sample_threadx.ld @@ -0,0 +1,45 @@ +# The following explains what the default Green Hills sections are for: +# +# picbase - base of the text sections, relocatable in -pic mode +# text - text section +# syscall - syscall section, for host I/O under Multi +# fixaddr/fixtype - for PIC/PID fixups +# rodata - read only data +# romdata - the ROM image of .data +# romsdata - the ROM image of .sdata +# secinfo - section information section, used by the start-up code +# pidbase - base of the data sections, relocatable in -pid mode +# sdabase - base of the small data area section pointer +# sbss - small BSS (zeroed data) section +# sdata - small data section +# data - non-zeroed writeable data section +# bss - zeroed data section +# heap - the heap, grows upward +# stack - the stack, grows downward + +-sec +{ + .reset 0x000000 : + .picbase 0x1000 : + .text : + .comment : + .intercall : + .interfunc : + .syscall : + .fixaddr : + .fixtype : + .rodata : + .romdata ROM(.data) : + .romsdata ROM(.sdata) : + .secinfo : + .pidbase align(16) : + .sdabase : + .sbss : + .sdata : + .data : + .bss : + .heap align(16) pad(0x10000) : + .stack align(16) pad(0x1000) : + .free_mem align(16) pad(0x10000) : + .sys_regs 0xE0000000 pad(0xe000) : +} diff --git a/ports/cortex_m4/ghs/example_build/sample_threadx_el.gpj b/ports/cortex_m4/ghs/example_build/sample_threadx_el.gpj new file mode 100644 index 00000000..a51049ca --- /dev/null +++ b/ports/cortex_m4/ghs/example_build/sample_threadx_el.gpj @@ -0,0 +1,13 @@ +#!gbuild +[Program] + -DTX_ENABLE_EVENT_LOGGING + -I../../../../common/inc + -I../../../../ports_common_green/inc + -I../inc +reset.arm +tx_initialize_low_level.arm +sample_threadx.c +txe.a +sample_threadx_el.ld +sample_threadx.con +readme_threadx.txt diff --git a/ports/cortex_m4/ghs/example_build/sample_threadx_el.ld b/ports/cortex_m4/ghs/example_build/sample_threadx_el.ld new file mode 100644 index 00000000..753374c7 --- /dev/null +++ b/ports/cortex_m4/ghs/example_build/sample_threadx_el.ld @@ -0,0 +1,46 @@ +# The following explains what the default Green Hills sections are for: +# +# picbase - base of the text sections, relocatable in -pic mode +# text - text section +# syscall - syscall section, for host I/O under Multi +# fixaddr/fixtype - for PIC/PID fixups +# rodata - read only data +# romdata - the ROM image of .data +# romsdata - the ROM image of .sdata +# secinfo - section information section, used by the start-up code +# pidbase - base of the data sections, relocatable in -pid mode +# sdabase - base of the small data area section pointer +# sbss - small BSS (zeroed data) section +# sdata - small data section +# data - non-zeroed writeable data section +# bss - zeroed data section +# heap - the heap, grows upward +# stack - the stack, grows downward + +-sec +{ + .reset 0x000000 : + .picbase 0x1000 : + .text : + .comment : + .intercall : + .interfunc : + .syscall : + .fixaddr : + .fixtype : + .rodata : + .romdata ROM(.data) : + .romsdata ROM(.sdata) : + .secinfo : + .pidbase align(16) : + .sdabase : + .sbss : + .sdata : + .data : + .bss : + .heap align(16) pad(0x1000) : + .stack align(16) pad(0x1000) : + .eventlog align(16) pad(0x10000) : + .free_mem align(16) pad(0x10000) : + .sys_regs 0xE0000000 pad(0xe000) : +} diff --git a/ports/cortex_m4/ghs/example_build/tx.gpj b/ports/cortex_m4/ghs/example_build/tx.gpj new file mode 100644 index 00000000..ca9baa41 --- /dev/null +++ b/ports/cortex_m4/ghs/example_build/tx.gpj @@ -0,0 +1,215 @@ +#!gbuild +[Library] + -I../../../../common/inc + -I../inc +..\..\..\..\common\inc\tx_api.h +..\..\..\..\common\inc\tx_block_pool.h +..\..\..\..\common\inc\tx_byte_pool.h +..\..\..\..\common\inc\tx_event_flags.h +..\..\..\..\common\inc\tx_initialize.h +..\..\..\..\common\inc\tx_mutex.h +..\..\..\..\common\inc\tx_queue.h +..\..\..\..\common\inc\tx_semaphore.h +..\..\..\..\common\inc\tx_thread.h +..\..\..\..\common\inc\tx_timer.h +..\..\..\..\common\inc\tx_trace.h +..\..\..\..\common\inc\tx_user_sample.h +..\inc\tx_port.h +..\inc\tx_el.h +..\inc\tx_ghs.h +..\src\tx_el.c +..\src\tx_ghs.c +..\src\tx_ghse.c +..\src\tx_thread_context_restore.arm +..\src\tx_thread_context_save.arm +..\src\tx_thread_interrupt_control.arm +..\src\tx_thread_interrupt_disable.arm +..\src\tx_thread_interrupt_restore.arm +..\src\tx_thread_schedule.arm +..\src\tx_thread_stack_build.arm +..\src\tx_thread_system_return.arm +..\src\tx_timer_interrupt.arm +..\..\..\..\common\src\tx_block_allocate.c +..\..\..\..\common\src\tx_block_pool_cleanup.c +..\..\..\..\common\src\tx_block_pool_create.c +..\..\..\..\common\src\tx_block_pool_delete.c +..\..\..\..\common\src\tx_block_pool_info_get.c +..\..\..\..\common\src\tx_block_pool_initialize.c +..\..\..\..\common\src\tx_block_pool_performance_info_get.c +..\..\..\..\common\src\tx_block_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_block_pool_prioritize.c +..\..\..\..\common\src\tx_block_release.c +..\..\..\..\common\src\tx_byte_allocate.c +..\..\..\..\common\src\tx_byte_pool_cleanup.c +..\..\..\..\common\src\tx_byte_pool_create.c +..\..\..\..\common\src\tx_byte_pool_delete.c +..\..\..\..\common\src\tx_byte_pool_info_get.c +..\..\..\..\common\src\tx_byte_pool_initialize.c +..\..\..\..\common\src\tx_byte_pool_performance_info_get.c +..\..\..\..\common\src\tx_byte_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_byte_pool_prioritize.c +..\..\..\..\common\src\tx_byte_pool_search.c +..\..\..\..\common\src\tx_byte_release.c +..\..\..\..\common\src\tx_event_flags_cleanup.c +..\..\..\..\common\src\tx_event_flags_create.c +..\..\..\..\common\src\tx_event_flags_delete.c +..\..\..\..\common\src\tx_event_flags_get.c +..\..\..\..\common\src\tx_event_flags_info_get.c +..\..\..\..\common\src\tx_event_flags_initialize.c +..\..\..\..\common\src\tx_event_flags_performance_info_get.c +..\..\..\..\common\src\tx_event_flags_performance_system_info_get.c +..\..\..\..\common\src\tx_event_flags_set.c +..\..\..\..\common\src\tx_event_flags_set_notify.c +..\..\..\..\common\src\tx_initialize_high_level.c +..\..\..\..\common\src\tx_initialize_kernel_enter.c +..\..\..\..\common\src\tx_initialize_kernel_setup.c +..\..\..\..\common\src\tx_mutex_cleanup.c +..\..\..\..\common\src\tx_mutex_create.c +..\..\..\..\common\src\tx_mutex_delete.c +..\..\..\..\common\src\tx_mutex_get.c +..\..\..\..\common\src\tx_mutex_info_get.c +..\..\..\..\common\src\tx_mutex_initialize.c +..\..\..\..\common\src\tx_mutex_performance_info_get.c +..\..\..\..\common\src\tx_mutex_performance_system_info_get.c +..\..\..\..\common\src\tx_mutex_prioritize.c +..\..\..\..\common\src\tx_mutex_priority_change.c +..\..\..\..\common\src\tx_mutex_put.c +..\..\..\..\common\src\tx_queue_cleanup.c +..\..\..\..\common\src\tx_queue_create.c +..\..\..\..\common\src\tx_queue_delete.c +..\..\..\..\common\src\tx_queue_flush.c +..\..\..\..\common\src\tx_queue_front_send.c +..\..\..\..\common\src\tx_queue_info_get.c +..\..\..\..\common\src\tx_queue_initialize.c +..\..\..\..\common\src\tx_queue_performance_info_get.c +..\..\..\..\common\src\tx_queue_performance_system_info_get.c +..\..\..\..\common\src\tx_queue_prioritize.c +..\..\..\..\common\src\tx_queue_receive.c +..\..\..\..\common\src\tx_queue_send.c +..\..\..\..\common\src\tx_queue_send_notify.c +..\..\..\..\common\src\tx_semaphore_ceiling_put.c +..\..\..\..\common\src\tx_semaphore_cleanup.c +..\..\..\..\common\src\tx_semaphore_create.c +..\..\..\..\common\src\tx_semaphore_delete.c +..\..\..\..\common\src\tx_semaphore_get.c +..\..\..\..\common\src\tx_semaphore_info_get.c +..\..\..\..\common\src\tx_semaphore_initialize.c +..\..\..\..\common\src\tx_semaphore_performance_info_get.c +..\..\..\..\common\src\tx_semaphore_performance_system_info_get.c +..\..\..\..\common\src\tx_semaphore_prioritize.c +..\..\..\..\common\src\tx_semaphore_put.c +..\..\..\..\common\src\tx_semaphore_put_notify.c +..\..\..\..\common\src\tx_thread_create.c +..\..\..\..\common\src\tx_thread_delete.c +..\..\..\..\common\src\tx_thread_entry_exit_notify.c +..\..\..\..\common\src\tx_thread_identify.c +..\..\..\..\common\src\tx_thread_info_get.c +..\..\..\..\common\src\tx_thread_initialize.c +..\..\..\..\common\src\tx_thread_performance_info_get.c +..\..\..\..\common\src\tx_thread_performance_system_info_get.c +..\..\..\..\common\src\tx_thread_preemption_change.c +..\..\..\..\common\src\tx_thread_priority_change.c +..\..\..\..\common\src\tx_thread_relinquish.c +..\..\..\..\common\src\tx_thread_reset.c +..\..\..\..\common\src\tx_thread_resume.c +..\..\..\..\common\src\tx_thread_shell_entry.c +..\..\..\..\common\src\tx_thread_sleep.c +..\..\..\..\common\src\tx_thread_stack_analyze.c +..\..\..\..\common\src\tx_thread_stack_error_handler.c +..\..\..\..\common\src\tx_thread_stack_error_notify.c +..\..\..\..\common\src\tx_thread_suspend.c +..\..\..\..\common\src\tx_thread_system_preempt_check.c +..\..\..\..\common\src\tx_thread_system_resume.c +..\..\..\..\common\src\tx_thread_system_suspend.c +..\..\..\..\common\src\tx_thread_terminate.c +..\..\..\..\common\src\tx_thread_time_slice.c +..\..\..\..\common\src\tx_thread_time_slice_change.c +..\..\..\..\common\src\tx_thread_timeout.c +..\..\..\..\common\src\tx_thread_wait_abort.c +..\..\..\..\common\src\tx_time_get.c +..\..\..\..\common\src\tx_time_set.c +..\..\..\..\common\src\tx_timer_activate.c +..\..\..\..\common\src\tx_timer_change.c +..\..\..\..\common\src\tx_timer_create.c +..\..\..\..\common\src\tx_timer_deactivate.c +..\..\..\..\common\src\tx_timer_delete.c +..\..\..\..\common\src\tx_timer_expiration_process.c +..\..\..\..\common\src\tx_timer_info_get.c +..\..\..\..\common\src\tx_timer_initialize.c +..\..\..\..\common\src\tx_timer_performance_info_get.c +..\..\..\..\common\src\tx_timer_performance_system_info_get.c +..\..\..\..\common\src\tx_timer_system_activate.c +..\..\..\..\common\src\tx_timer_system_deactivate.c +..\..\..\..\common\src\tx_timer_thread_entry.c +..\..\..\..\common\src\tx_trace_buffer_full_notify.c +..\..\..\..\common\src\tx_trace_disable.c +..\..\..\..\common\src\tx_trace_enable.c +..\..\..\..\common\src\tx_trace_event_filter.c +..\..\..\..\common\src\tx_trace_event_unfilter.c +..\..\..\..\common\src\tx_trace_initialize.c +..\..\..\..\common\src\tx_trace_interrupt_control.c +..\..\..\..\common\src\tx_trace_isr_enter_insert.c +..\..\..\..\common\src\tx_trace_isr_exit_insert.c +..\..\..\..\common\src\tx_trace_object_register.c +..\..\..\..\common\src\tx_trace_object_unregister.c +..\..\..\..\common\src\tx_trace_user_event_insert.c +..\..\..\..\common\src\txe_block_allocate.c +..\..\..\..\common\src\txe_block_pool_create.c +..\..\..\..\common\src\txe_block_pool_delete.c +..\..\..\..\common\src\txe_block_pool_info_get.c +..\..\..\..\common\src\txe_block_pool_prioritize.c +..\..\..\..\common\src\txe_block_release.c +..\..\..\..\common\src\txe_byte_allocate.c +..\..\..\..\common\src\txe_byte_pool_create.c +..\..\..\..\common\src\txe_byte_pool_delete.c +..\..\..\..\common\src\txe_byte_pool_info_get.c +..\..\..\..\common\src\txe_byte_pool_prioritize.c +..\..\..\..\common\src\txe_byte_release.c +..\..\..\..\common\src\txe_event_flags_create.c +..\..\..\..\common\src\txe_event_flags_delete.c +..\..\..\..\common\src\txe_event_flags_get.c +..\..\..\..\common\src\txe_event_flags_info_get.c +..\..\..\..\common\src\txe_event_flags_set.c +..\..\..\..\common\src\txe_event_flags_set_notify.c +..\..\..\..\common\src\txe_mutex_create.c +..\..\..\..\common\src\txe_mutex_delete.c +..\..\..\..\common\src\txe_mutex_get.c +..\..\..\..\common\src\txe_mutex_info_get.c +..\..\..\..\common\src\txe_mutex_prioritize.c +..\..\..\..\common\src\txe_mutex_put.c +..\..\..\..\common\src\txe_queue_create.c +..\..\..\..\common\src\txe_queue_delete.c +..\..\..\..\common\src\txe_queue_flush.c +..\..\..\..\common\src\txe_queue_front_send.c +..\..\..\..\common\src\txe_queue_info_get.c +..\..\..\..\common\src\txe_queue_prioritize.c +..\..\..\..\common\src\txe_queue_receive.c +..\..\..\..\common\src\txe_queue_send.c +..\..\..\..\common\src\txe_queue_send_notify.c +..\..\..\..\common\src\txe_semaphore_ceiling_put.c +..\..\..\..\common\src\txe_semaphore_create.c +..\..\..\..\common\src\txe_semaphore_delete.c +..\..\..\..\common\src\txe_semaphore_get.c +..\..\..\..\common\src\txe_semaphore_info_get.c +..\..\..\..\common\src\txe_semaphore_prioritize.c +..\..\..\..\common\src\txe_semaphore_put.c +..\..\..\..\common\src\txe_semaphore_put_notify.c +..\..\..\..\common\src\txe_thread_create.c +..\..\..\..\common\src\txe_thread_delete.c +..\..\..\..\common\src\txe_thread_entry_exit_notify.c +..\..\..\..\common\src\txe_thread_info_get.c +..\..\..\..\common\src\txe_thread_preemption_change.c +..\..\..\..\common\src\txe_thread_priority_change.c +..\..\..\..\common\src\txe_thread_relinquish.c +..\..\..\..\common\src\txe_thread_reset.c +..\..\..\..\common\src\txe_thread_resume.c +..\..\..\..\common\src\txe_thread_suspend.c +..\..\..\..\common\src\txe_thread_terminate.c +..\..\..\..\common\src\txe_thread_time_slice_change.c +..\..\..\..\common\src\txe_thread_wait_abort.c +..\..\..\..\common\src\txe_timer_activate.c +..\..\..\..\common\src\txe_timer_change.c +..\..\..\..\common\src\txe_timer_create.c +..\..\..\..\common\src\txe_timer_deactivate.c +..\..\..\..\common\src\txe_timer_delete.c +..\..\..\..\common\src\txe_timer_info_get.c diff --git a/ports/cortex_m4/ghs/example_build/tx_initialize_low_level.arm b/ports/cortex_m4/ghs/example_build/tx_initialize_low_level.arm new file mode 100644 index 00000000..fca0e30b --- /dev/null +++ b/ports/cortex_m4/ghs/example_build/tx_initialize_low_level.arm @@ -0,0 +1,232 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SYSTEM_CLOCK = 6000000 + SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-M4/GHS */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_initialize_low_level(VOID) +{ */ + .globl _tx_initialize_low_level +_tx_initialize_low_level: + + /* Disable interrupts. */ + + CPSID i ; Disable interrupts + + + /* Save the system stack pointer. */ + /* _tx_thread_system_stack_ptr = (VOID_PTR) (sp); */ + + LDR r1,=_tx_thread_system_stack_ptr ; Pickup address of system stack ptr + STR sp, [r1] ; Save system stack + + + /* Save the first available memory address. */ + /* _tx_initialize_unused_memory = (VOID_PTR) __ghsbegin_free_mem; */ + + LDR r0,=__ghsbegin_free_mem ; Pickup free memory address + LDR r2,=_tx_initialize_unused_memory ; Pickup unused memory ptr address + STR r0, [r2] ; Save first free memory address + + + /* Enable the cycle count register. */ + + LDR r0, =0xE0001000 ; Build address of DWT register + LDR r1, [r0] ; Pickup the current value + ORR r1, r1, 1 ; Set the CYCCNTENA bit + STR r1, [r0] ; Enable the cycle count register + + + /* Setup Vector Table Offset Register. */ + + MOV r0, 0xE000E000 ; Build address of NVIC registers + LDR r1, =__vectors ; Pickup address of vector table + STR r1, [r0, 0xD08] ; Set vector table address + + + /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ + + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, 0x14] ; Setup SysTick Reload Value + MOV r1, 0x7 ; Build SysTick Control Enable Value + STR r1, [r0, 0x10] ; Setup SysTick Control + + /* Configure handler priorities. */ + + LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM + STR r1, [r0, 0xD18] ; Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, 0xD1C] ; Setup System Handlers 8-11 Priority Registers + ; Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM + STR r1, [r0, 0xD20] ; Setup System Handlers 12-15 Priority Registers + ; Note: PnSV must be lowest priority, which is 0xFF + +#ifdef __VFP__ + LDR r0, =0xE000EF34 ; Pickup FPCCR + LDR r1, [r0] ; + LDR r2, =0x3FFFFFFF ; Build mask to clear ASPEN and LSPEN + AND r1, r1, r2 ; Clear the ASPEN and LSPEN bits + STR r1, [r0] ; Update FPCCR +#endif + + /* Return to caller. */ + + BX lr ; Return to caller + + .type _tx_initialize_low_level,$function + .size _tx_initialize_low_level,.-_tx_initialize_low_level +/* } */ + + +/* Define shells for each of the interrupt vectors. */ + + .globl __tx_BadHandler +__tx_BadHandler: + B __tx_BadHandler + + .type __tx_BadHandler,$function + .size __tx_BadHandler,.-__tx_BadHandler + + + .globl __tx_IntHandler +__tx_IntHandler: + PUSH {lr} + BL _tx_thread_context_save + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 0 ; Build interrupt code + BL _tx_el_interrupt ; Call interrupt event logging +#endif + +; /* Do interrupt handler work here */ +; /* .... */ + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 0 ; Build interrupt code + BL _tx_el_interrupt_end ; Call interrupt event logging +#endif + + B _tx_thread_context_restore + + .type __tx_IntHandler,$function + .size __tx_IntHandler,.-__tx_IntHandler + + + .globl __tx_SysTickHandler +__tx_SysTickHandler: + PUSH {lr} + BL _tx_thread_context_save + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 15 ; Build interrupt code + BL _tx_el_interrupt ; Call interrupt event logging +#endif + + BL _tx_timer_interrupt + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 15 ; Build interrupt code + BL _tx_el_interrupt_end ; Call interrupt event logging +#endif + + B _tx_thread_context_restore + + .type __tx_SysTickHandler,$function + .size __tx_SysTickHandler,.-__tx_SysTickHandler + + + .globl __tx_NMIHandler +__tx_NMIHandler: + B __tx_NMIHandler + + .type __tx_NMIHandler,$function + .size __tx_NMIHandler,.-__tx_NMIHandler + + + .globl __tx_DBGHandler +__tx_DBGHandler: + B __tx_DBGHandler + + .type __tx_DBGHandler,$function + .size __tx_DBGHandler,.-__tx_DBGHandler + + + .globl __tx_SVCallHandler +__tx_SVCallHandler: + B __tx_SVCallHandler + + .type __tx_SVCallHandler,$function + .size __tx_SVCallHandler,.-__tx_SVCallHandler + + + /* Reference build options and version ID to ensure they come in. */ + +BUILD_OPTIONS: + .data.w _tx_build_options +VERSION_ID: + .data.w _tx_version_id diff --git a/ports/cortex_m4/ghs/example_build/txe.gpj b/ports/cortex_m4/ghs/example_build/txe.gpj new file mode 100644 index 00000000..c7825b04 --- /dev/null +++ b/ports/cortex_m4/ghs/example_build/txe.gpj @@ -0,0 +1,216 @@ +#!gbuild +[Library] + -DTX_ENABLE_EVENT_LOGGING + -I../../../../common/inc + -I../inc +..\..\..\..\common\inc\tx_api.h +..\..\..\..\common\inc\tx_block_pool.h +..\..\..\..\common\inc\tx_byte_pool.h +..\..\..\..\common\inc\tx_event_flags.h +..\..\..\..\common\inc\tx_initialize.h +..\..\..\..\common\inc\tx_mutex.h +..\..\..\..\common\inc\tx_queue.h +..\..\..\..\common\inc\tx_semaphore.h +..\..\..\..\common\inc\tx_thread.h +..\..\..\..\common\inc\tx_timer.h +..\..\..\..\common\inc\tx_trace.h +..\..\..\..\common\inc\tx_user_sample.h +..\inc\tx_port.h +..\inc\tx_el.h +..\inc\tx_ghs.h +..\src\tx_el.c +..\src\tx_ghs.c +..\src\tx_ghse.c +..\src\tx_thread_context_restore.arm +..\src\tx_thread_context_save.arm +..\src\tx_thread_interrupt_control.arm +..\src\tx_thread_interrupt_disable.arm +..\src\tx_thread_interrupt_restore.arm +..\src\tx_thread_schedule.arm +..\src\tx_thread_stack_build.arm +..\src\tx_thread_system_return.arm +..\src\tx_timer_interrupt.arm +..\..\..\..\common\src\tx_block_allocate.c +..\..\..\..\common\src\tx_block_pool_cleanup.c +..\..\..\..\common\src\tx_block_pool_create.c +..\..\..\..\common\src\tx_block_pool_delete.c +..\..\..\..\common\src\tx_block_pool_info_get.c +..\..\..\..\common\src\tx_block_pool_initialize.c +..\..\..\..\common\src\tx_block_pool_performance_info_get.c +..\..\..\..\common\src\tx_block_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_block_pool_prioritize.c +..\..\..\..\common\src\tx_block_release.c +..\..\..\..\common\src\tx_byte_allocate.c +..\..\..\..\common\src\tx_byte_pool_cleanup.c +..\..\..\..\common\src\tx_byte_pool_create.c +..\..\..\..\common\src\tx_byte_pool_delete.c +..\..\..\..\common\src\tx_byte_pool_info_get.c +..\..\..\..\common\src\tx_byte_pool_initialize.c +..\..\..\..\common\src\tx_byte_pool_performance_info_get.c +..\..\..\..\common\src\tx_byte_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_byte_pool_prioritize.c +..\..\..\..\common\src\tx_byte_pool_search.c +..\..\..\..\common\src\tx_byte_release.c +..\..\..\..\common\src\tx_event_flags_cleanup.c +..\..\..\..\common\src\tx_event_flags_create.c +..\..\..\..\common\src\tx_event_flags_delete.c +..\..\..\..\common\src\tx_event_flags_get.c +..\..\..\..\common\src\tx_event_flags_info_get.c +..\..\..\..\common\src\tx_event_flags_initialize.c +..\..\..\..\common\src\tx_event_flags_performance_info_get.c +..\..\..\..\common\src\tx_event_flags_performance_system_info_get.c +..\..\..\..\common\src\tx_event_flags_set.c +..\..\..\..\common\src\tx_event_flags_set_notify.c +..\..\..\..\common\src\tx_initialize_high_level.c +..\..\..\..\common\src\tx_initialize_kernel_enter.c +..\..\..\..\common\src\tx_initialize_kernel_setup.c +..\..\..\..\common\src\tx_mutex_cleanup.c +..\..\..\..\common\src\tx_mutex_create.c +..\..\..\..\common\src\tx_mutex_delete.c +..\..\..\..\common\src\tx_mutex_get.c +..\..\..\..\common\src\tx_mutex_info_get.c +..\..\..\..\common\src\tx_mutex_initialize.c +..\..\..\..\common\src\tx_mutex_performance_info_get.c +..\..\..\..\common\src\tx_mutex_performance_system_info_get.c +..\..\..\..\common\src\tx_mutex_prioritize.c +..\..\..\..\common\src\tx_mutex_priority_change.c +..\..\..\..\common\src\tx_mutex_put.c +..\..\..\..\common\src\tx_queue_cleanup.c +..\..\..\..\common\src\tx_queue_create.c +..\..\..\..\common\src\tx_queue_delete.c +..\..\..\..\common\src\tx_queue_flush.c +..\..\..\..\common\src\tx_queue_front_send.c +..\..\..\..\common\src\tx_queue_info_get.c +..\..\..\..\common\src\tx_queue_initialize.c +..\..\..\..\common\src\tx_queue_performance_info_get.c +..\..\..\..\common\src\tx_queue_performance_system_info_get.c +..\..\..\..\common\src\tx_queue_prioritize.c +..\..\..\..\common\src\tx_queue_receive.c +..\..\..\..\common\src\tx_queue_send.c +..\..\..\..\common\src\tx_queue_send_notify.c +..\..\..\..\common\src\tx_semaphore_ceiling_put.c +..\..\..\..\common\src\tx_semaphore_cleanup.c +..\..\..\..\common\src\tx_semaphore_create.c +..\..\..\..\common\src\tx_semaphore_delete.c +..\..\..\..\common\src\tx_semaphore_get.c +..\..\..\..\common\src\tx_semaphore_info_get.c +..\..\..\..\common\src\tx_semaphore_initialize.c +..\..\..\..\common\src\tx_semaphore_performance_info_get.c +..\..\..\..\common\src\tx_semaphore_performance_system_info_get.c +..\..\..\..\common\src\tx_semaphore_prioritize.c +..\..\..\..\common\src\tx_semaphore_put.c +..\..\..\..\common\src\tx_semaphore_put_notify.c +..\..\..\..\common\src\tx_thread_create.c +..\..\..\..\common\src\tx_thread_delete.c +..\..\..\..\common\src\tx_thread_entry_exit_notify.c +..\..\..\..\common\src\tx_thread_identify.c +..\..\..\..\common\src\tx_thread_info_get.c +..\..\..\..\common\src\tx_thread_initialize.c +..\..\..\..\common\src\tx_thread_performance_info_get.c +..\..\..\..\common\src\tx_thread_performance_system_info_get.c +..\..\..\..\common\src\tx_thread_preemption_change.c +..\..\..\..\common\src\tx_thread_priority_change.c +..\..\..\..\common\src\tx_thread_relinquish.c +..\..\..\..\common\src\tx_thread_reset.c +..\..\..\..\common\src\tx_thread_resume.c +..\..\..\..\common\src\tx_thread_shell_entry.c +..\..\..\..\common\src\tx_thread_sleep.c +..\..\..\..\common\src\tx_thread_stack_analyze.c +..\..\..\..\common\src\tx_thread_stack_error_handler.c +..\..\..\..\common\src\tx_thread_stack_error_notify.c +..\..\..\..\common\src\tx_thread_suspend.c +..\..\..\..\common\src\tx_thread_system_preempt_check.c +..\..\..\..\common\src\tx_thread_system_resume.c +..\..\..\..\common\src\tx_thread_system_suspend.c +..\..\..\..\common\src\tx_thread_terminate.c +..\..\..\..\common\src\tx_thread_time_slice.c +..\..\..\..\common\src\tx_thread_time_slice_change.c +..\..\..\..\common\src\tx_thread_timeout.c +..\..\..\..\common\src\tx_thread_wait_abort.c +..\..\..\..\common\src\tx_time_get.c +..\..\..\..\common\src\tx_time_set.c +..\..\..\..\common\src\tx_timer_activate.c +..\..\..\..\common\src\tx_timer_change.c +..\..\..\..\common\src\tx_timer_create.c +..\..\..\..\common\src\tx_timer_deactivate.c +..\..\..\..\common\src\tx_timer_delete.c +..\..\..\..\common\src\tx_timer_expiration_process.c +..\..\..\..\common\src\tx_timer_info_get.c +..\..\..\..\common\src\tx_timer_initialize.c +..\..\..\..\common\src\tx_timer_performance_info_get.c +..\..\..\..\common\src\tx_timer_performance_system_info_get.c +..\..\..\..\common\src\tx_timer_system_activate.c +..\..\..\..\common\src\tx_timer_system_deactivate.c +..\..\..\..\common\src\tx_timer_thread_entry.c +..\..\..\..\common\src\tx_trace_buffer_full_notify.c +..\..\..\..\common\src\tx_trace_disable.c +..\..\..\..\common\src\tx_trace_enable.c +..\..\..\..\common\src\tx_trace_event_filter.c +..\..\..\..\common\src\tx_trace_event_unfilter.c +..\..\..\..\common\src\tx_trace_initialize.c +..\..\..\..\common\src\tx_trace_interrupt_control.c +..\..\..\..\common\src\tx_trace_isr_enter_insert.c +..\..\..\..\common\src\tx_trace_isr_exit_insert.c +..\..\..\..\common\src\tx_trace_object_register.c +..\..\..\..\common\src\tx_trace_object_unregister.c +..\..\..\..\common\src\tx_trace_user_event_insert.c +..\..\..\..\common\src\txe_block_allocate.c +..\..\..\..\common\src\txe_block_pool_create.c +..\..\..\..\common\src\txe_block_pool_delete.c +..\..\..\..\common\src\txe_block_pool_info_get.c +..\..\..\..\common\src\txe_block_pool_prioritize.c +..\..\..\..\common\src\txe_block_release.c +..\..\..\..\common\src\txe_byte_allocate.c +..\..\..\..\common\src\txe_byte_pool_create.c +..\..\..\..\common\src\txe_byte_pool_delete.c +..\..\..\..\common\src\txe_byte_pool_info_get.c +..\..\..\..\common\src\txe_byte_pool_prioritize.c +..\..\..\..\common\src\txe_byte_release.c +..\..\..\..\common\src\txe_event_flags_create.c +..\..\..\..\common\src\txe_event_flags_delete.c +..\..\..\..\common\src\txe_event_flags_get.c +..\..\..\..\common\src\txe_event_flags_info_get.c +..\..\..\..\common\src\txe_event_flags_set.c +..\..\..\..\common\src\txe_event_flags_set_notify.c +..\..\..\..\common\src\txe_mutex_create.c +..\..\..\..\common\src\txe_mutex_delete.c +..\..\..\..\common\src\txe_mutex_get.c +..\..\..\..\common\src\txe_mutex_info_get.c +..\..\..\..\common\src\txe_mutex_prioritize.c +..\..\..\..\common\src\txe_mutex_put.c +..\..\..\..\common\src\txe_queue_create.c +..\..\..\..\common\src\txe_queue_delete.c +..\..\..\..\common\src\txe_queue_flush.c +..\..\..\..\common\src\txe_queue_front_send.c +..\..\..\..\common\src\txe_queue_info_get.c +..\..\..\..\common\src\txe_queue_prioritize.c +..\..\..\..\common\src\txe_queue_receive.c +..\..\..\..\common\src\txe_queue_send.c +..\..\..\..\common\src\txe_queue_send_notify.c +..\..\..\..\common\src\txe_semaphore_ceiling_put.c +..\..\..\..\common\src\txe_semaphore_create.c +..\..\..\..\common\src\txe_semaphore_delete.c +..\..\..\..\common\src\txe_semaphore_get.c +..\..\..\..\common\src\txe_semaphore_info_get.c +..\..\..\..\common\src\txe_semaphore_prioritize.c +..\..\..\..\common\src\txe_semaphore_put.c +..\..\..\..\common\src\txe_semaphore_put_notify.c +..\..\..\..\common\src\txe_thread_create.c +..\..\..\..\common\src\txe_thread_delete.c +..\..\..\..\common\src\txe_thread_entry_exit_notify.c +..\..\..\..\common\src\txe_thread_info_get.c +..\..\..\..\common\src\txe_thread_preemption_change.c +..\..\..\..\common\src\txe_thread_priority_change.c +..\..\..\..\common\src\txe_thread_relinquish.c +..\..\..\..\common\src\txe_thread_reset.c +..\..\..\..\common\src\txe_thread_resume.c +..\..\..\..\common\src\txe_thread_suspend.c +..\..\..\..\common\src\txe_thread_terminate.c +..\..\..\..\common\src\txe_thread_time_slice_change.c +..\..\..\..\common\src\txe_thread_wait_abort.c +..\..\..\..\common\src\txe_timer_activate.c +..\..\..\..\common\src\txe_timer_change.c +..\..\..\..\common\src\txe_timer_create.c +..\..\..\..\common\src\txe_timer_deactivate.c +..\..\..\..\common\src\txe_timer_delete.c +..\..\..\..\common\src\txe_timer_info_get.c diff --git a/ports/cortex_m4/ghs/inc/tx_el.h b/ports/cortex_m4/ghs/inc/tx_el.h new file mode 100644 index 00000000..29c72370 --- /dev/null +++ b/ports/cortex_m4/ghs/inc/tx_el.h @@ -0,0 +1,765 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** ThreadX/GHS Event Log (EL) */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* tx_el.h PORTABLE C/GHS */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the ThreadX event log functions for the GHS MULTI */ +/* EventAnalyzer. It is assumed that tx_api.h and tx_port.h have */ +/* already been included. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_EL_H +#define TX_EL_H + + +/* Define Event Log specific data definitions. */ + +#define TX_EL_VERSION_ID 2 /* Event log version ID */ +#define TX_EL_HEADER_SIZE 24 /* Event log header size */ +#define TX_EL_TNIS 16 /* Number of thread names supported */ + /* If the application needs to */ + /* track more thread names, just */ + /* increase this number and re- */ + /* build the ThreadX library. */ +#define TX_EL_TNI_ENTRY_SIZE 44 /* Thread name entries are 44 bytes */ +#define TX_EL_TNI_NAME_SIZE 34 /* Thread name size in TNI */ +#define TX_EL_NO_MORE_TNI_ROOM 1 /* Error return from thread register*/ +#define TX_EL_NAME_NOT_FOUND 2 /* Error return from un-register */ +#define TX_EL_EVENT_SIZE 32 /* Number of bytes in each event */ +#define TX_EL_VALID_ENTRY 1 /* Valid log entry */ +#define TX_EL_INVALID_ENTRY 0 /* Invalid log entry */ + + +/* Define necessary offsets. */ + +#define TX_EL_TNI_VALID_OFFSET 34 +#define TX_EL_TNI_THREAD_ID_OFFSET 36 +#define TX_EL_TNI_THREAD_PRIORITY_OFF 40 +#define TX_EL_EVENT_TYPE_OFFSET 0 +#define TX_EL_EVENT_SUBTYPE_OFFSET 2 +#define TX_EL_EVENT_TIME_UPPER_OFFSET 4 +#define TX_EL_EVENT_TIME_LOWER_OFFSET 8 +#define TX_EL_EVENT_THREAD_OFFSET 12 +#define TX_EL_EVENT_INFO_1_OFFSET 16 +#define TX_EL_EVENT_INFO_2_OFFSET 20 +#define TX_EL_EVENT_INFO_3_OFFSET 24 +#define TX_EL_EVENT_INFO_4_OFFSET 28 + + +/* Undefine constants that might be been defined previously by tx_api.h. */ + +#undef TX_EL_INITIALIZE +#undef TX_EL_THREAD_REGISTER +#undef TX_EL_THREAD_UNREGISTER +#undef TX_EL_THREAD_STATUS_CHANGE_INSERT +#undef TX_EL_BYTE_ALLOCATE_INSERT +#undef TX_EL_BYTE_POOL_CREATE_INSERT +#undef TX_EL_BYTE_POOL_DELETE_INSERT +#undef TX_EL_BYTE_RELEASE_INSERT +#undef TX_EL_BLOCK_ALLOCATE_INSERT +#undef TX_EL_BLOCK_POOL_CREATE_INSERT +#undef TX_EL_BLOCK_POOL_DELETE_INSERT +#undef TX_EL_BLOCK_RELEASE_INSERT +#undef TX_EL_EVENT_FLAGS_CREATE_INSERT +#undef TX_EL_EVENT_FLAGS_DELETE_INSERT +#undef TX_EL_EVENT_FLAGS_GET_INSERT +#undef TX_EL_EVENT_FLAGS_SET_INSERT +#undef TX_EL_INTERRUPT_CONTROL_INSERT +#undef TX_EL_QUEUE_CREATE_INSERT +#undef TX_EL_QUEUE_DELETE_INSERT +#undef TX_EL_QUEUE_FLUSH_INSERT +#undef TX_EL_QUEUE_RECEIVE_INSERT +#undef TX_EL_QUEUE_SEND_INSERT +#undef TX_EL_SEMAPHORE_CREATE_INSERT +#undef TX_EL_SEMAPHORE_DELETE_INSERT +#undef TX_EL_SEMAPHORE_GET_INSERT +#undef TX_EL_SEMAPHORE_PUT_INSERT +#undef TX_EL_THREAD_CREATE_INSERT +#undef TX_EL_THREAD_DELETE_INSERT +#undef TX_EL_THREAD_IDENTIFY_INSERT +#undef TX_EL_THREAD_PREEMPTION_CHANGE_INSERT +#undef TX_EL_THREAD_PRIORITY_CHANGE_INSERT +#undef TX_EL_THREAD_RELINQUISH_INSERT +#undef TX_EL_THREAD_RESUME_INSERT +#undef TX_EL_THREAD_SLEEP_INSERT +#undef TX_EL_THREAD_SUSPEND_INSERT +#undef TX_EL_THREAD_TERMINATE_INSERT +#undef TX_EL_THREAD_TIME_SLICE_CHANGE_INSERT +#undef TX_EL_TIME_GET_INSERT +#undef TX_EL_TIME_SET_INSERT +#undef TX_EL_TIMER_ACTIVATE_INSERT +#undef TX_EL_TIMER_CHANGE_INSERT +#undef TX_EL_TIMER_CREATE_INSERT +#undef TX_EL_TIMER_DEACTIVATE_INSERT +#undef TX_EL_TIMER_DELETE_INSERT +#undef TX_EL_BLOCK_POOL_INFO_GET_INSERT +#undef TX_EL_BLOCK_POOL_PRIORITIZE_INSERT +#undef TX_EL_BYTE_POOL_INFO_GET_INSERT +#undef TX_EL_BYTE_POOL_PRIORITIZE_INSERT +#undef TX_EL_EVENT_FLAGS_INFO_GET_INSERT +#undef TX_EL_MUTEX_CREATE_INSERT +#undef TX_EL_MUTEX_DELETE_INSERT +#undef TX_EL_MUTEX_GET_INSERT +#undef TX_EL_MUTEX_INFO_GET_INSERT +#undef TX_EL_MUTEX_PRIORITIZE_INSERT +#undef TX_EL_MUTEX_PUT_INSERT +#undef TX_EL_QUEUE_INFO_GET_INSERT +#undef TX_EL_QUEUE_FRONT_SEND_INSERT +#undef TX_EL_QUEUE_PRIORITIZE_INSERT +#undef TX_EL_SEMAPHORE_INFO_GET_INSERT +#undef TX_EL_SEMAPHORE_PRIORITIZE_INSERT +#undef TX_EL_THREAD_INFO_GET_INSERT +#undef TX_EL_THREAD_WAIT_ABORT_INSERT +#undef TX_EL_TIMER_INFO_GET_INSERT +#undef TX_EL_BLOCK_POOL_PERFORMANCE_INFO_GET_INSERT +#undef TX_EL_BLOCK_POOL_PERFORMANCE_SYSTEM_INFO_GET_INSERT +#undef TX_EL_BYTE_POOL_PERFORMANCE_INFO_GET_INSERT +#undef TX_EL_BYTE_POOL_PERFORMANCE_SYSTEM_INFO_GET_INSERT +#undef TX_EL_EVENT_FLAGS_PERFORMANCE_INFO_GET_INSERT +#undef TX_EL_EVENT_FLAGS_PERFORMANCE_SYSTEM_INFO_GET_INSERT +#undef TX_EL_EVENT_FLAGS_SET_NOTIFY_INSERT +#undef TX_EL_MUTEX_PERFORMANCE_INFO_GET_INSERT +#undef TX_EL_MUTEX_PERFORMANCE_SYSTEM_INFO_GET_INSERT +#undef TX_EL_QUEUE_PERFORMANCE_INFO_GET_INSERT +#undef TX_EL_QUEUE_PERFORMANCE_SYSTEM_INFO_GET_INSERT +#undef TX_EL_QUEUE_SEND_NOTIFY_INSERT +#undef TX_EL_SEMAPHORE_CEILING_PUT_INSERT +#undef TX_EL_SEMAPHORE_PERFORMANCE_INFO_GET_INSERT +#undef TX_EL_SEMAPHORE_PERFORMANCE_SYSTEM_INFO_GET_INSERT +#undef TX_EL_SEMAPHORE_PUT_NOTIFY_INSERT +#undef TX_EL_THREAD_ENTRY_EXIT_NOTIFY_INSERT +#undef TX_EL_THREAD_RESET_INSERT +#undef TX_EL_THREAD_PERFORMANCE_INFO_GET_INSERT +#undef TX_EL_THREAD_PERFORMANCE_SYSTEM_INFO_GET_INSERT +#undef TX_EL_THREAD_STACK_ERROR_NOTIFY_INSERT +#undef TX_EL_TIMER_PERFORMANCE_INFO_GET_INSERT +#undef TX_EL_TIMER_PERFORMANCE_SYSTEM_INFO_GET_INSERT + + +/* Define Event Types. */ + +#define TX_EL_THREAD_CHANGE 1 +#define TX_EL_INTERRUPT 2 +#define TX_EL_THREADX_CALL 3 +#define TX_EL_USER_EVENT 4 +#define TX_EL_THREAD_STATUS_CHANGE 5 +#define TX_EL_REFRESH 6 /* Not implemented */ +#define TX_EL_TIMER 7 /* Not implemented */ +#define TX_EL_TIMESOURCE_DELTA 8 /* Not implemented */ + + +/* Define TX_EL_THREADX_CALL event sub-types. */ + +#define TX_EL_BYTE_ALLOCATE 0 +#define TX_EL_BYTE_POOL_CREATE 1 +#define TX_EL_BYTE_POOL_DELETE 2 +#define TX_EL_BYTE_RELEASE 3 +#define TX_EL_BLOCK_ALLOCATE 4 +#define TX_EL_BLOCK_POOL_CREATE 5 +#define TX_EL_BLOCK_POOL_DELETE 6 +#define TX_EL_BLOCK_RELEASE 7 +#define TX_EL_EVENT_FLAGS_CREATE 8 +#define TX_EL_EVENT_FLAGS_DELETE 9 +#define TX_EL_EVENT_FLAGS_GET 10 +#define TX_EL_EVENT_FLAGS_SET 11 +#define TX_EL_INTERRUPT_CONTROL 12 +#define TX_EL_QUEUE_CREATE 13 +#define TX_EL_QUEUE_DELETE 14 +#define TX_EL_QUEUE_FLUSH 15 +#define TX_EL_QUEUE_RECEIVE 16 +#define TX_EL_QUEUE_SEND 17 +#define TX_EL_SEMAPHORE_CREATE 18 +#define TX_EL_SEMAPHORE_DELETE 19 +#define TX_EL_SEMAPHORE_GET 20 +#define TX_EL_SEMAPHORE_PUT 21 +#define TX_EL_THREAD_CREATE 22 +#define TX_EL_THREAD_DELETE 23 +#define TX_EL_THREAD_IDENTIFY 24 +#define TX_EL_THREAD_PREEMPTION_CHANGE 25 +#define TX_EL_THREAD_PRIORITY_CHANGE 26 +#define TX_EL_THREAD_RELINQUISH 27 +#define TX_EL_THREAD_RESUME 28 +#define TX_EL_THREAD_SLEEP 29 +#define TX_EL_THREAD_SUSPEND 30 +#define TX_EL_THREAD_TERMINATE 31 +#define TX_EL_THREAD_TIME_SLICE_CHANGE 32 +#define TX_EL_TIME_GET 33 +#define TX_EL_TIME_SET 34 +#define TX_EL_TIMER_ACTIVATE 35 +#define TX_EL_TIMER_CHANGE 36 +#define TX_EL_TIMER_CREATE 37 +#define TX_EL_TIMER_DEACTIVATE 38 +#define TX_EL_TIMER_DELETE 39 +#define TX_EL_BLOCK_POOL_INFO_GET 40 +#define TX_EL_BLOCK_POOL_PRIORITIZE 41 +#define TX_EL_BYTE_POOL_INFO_GET 42 +#define TX_EL_BYTE_POOL_PRIORITIZE 43 +#define TX_EL_EVENT_FLAGS_INFO_GET 44 +#define TX_EL_MUTEX_CREATE 45 +#define TX_EL_MUTEX_DELETE 46 +#define TX_EL_MUTEX_GET 47 +#define TX_EL_MUTEX_INFO_GET 48 +#define TX_EL_MUTEX_PRIORITIZE 49 +#define TX_EL_MUTEX_PUT 50 +#define TX_EL_QUEUE_INFO_GET 51 +#define TX_EL_QUEUE_FRONT_SEND 52 +#define TX_EL_QUEUE_PRIORITIZE 53 +#define TX_EL_SEMAPHORE_INFO_GET 54 +#define TX_EL_SEMAPHORE_PRIORITIZE 55 +#define TX_EL_THREAD_INFO_GET 56 +#define TX_EL_THREAD_WAIT_ABORT 57 +#define TX_EL_TIMER_INFO_GET 58 +#define TX_EL_BLOCK_POOL_PERFORMANCE_INFO_GET 59 +#define TX_EL_BLOCK_POOL_PERFORMANCE_SYSTEM_INFO_GET 60 +#define TX_EL_BYTE_POOL_PERFORMANCE_INFO_GET 61 +#define TX_EL_BYTE_POOL_PERFORMANCE_SYSTEM_INFO_GET 62 +#define TX_EL_EVENT_FLAGS_PERFORMANCE_INFO_GET 63 +#define TX_EL_EVENT_FLAGS_PERFORMANCE_SYSTEM_INFO_GET 64 +#define TX_EL_EVENT_FLAGS_SET_NOTIFY 65 +#define TX_EL_MUTEX_PERFORMANCE_INFO_GET 66 +#define TX_EL_MUTEX_PERFORMANCE_SYSTEM_INFO_GET 67 +#define TX_EL_QUEUE_PERFORMANCE_INFO_GET 68 +#define TX_EL_QUEUE_PERFORMANCE_SYSTEM_INFO_GET 69 +#define TX_EL_QUEUE_SEND_NOTIFY 70 +#define TX_EL_SEMAPHORE_CEILING_PUT 71 +#define TX_EL_SEMAPHORE_PERFORMANCE_INFO_GET 72 +#define TX_EL_SEMAPHORE_PERFORMANCE_SYSTEM_INFO_GET 73 +#define TX_EL_SEMAPHORE_PUT_NOTIFY 74 +#define TX_EL_THREAD_ENTRY_EXIT_NOTIFY 75 +#define TX_EL_THREAD_RESET 76 +#define TX_EL_THREAD_PERFORMANCE_INFO_GET 77 +#define TX_EL_THREAD_PERFORMANCE_SYSTEM_INFO_GET 78 +#define TX_EL_THREAD_STACK_ERROR_NOTIFY 79 +#define TX_EL_TIMER_PERFORMANCE_INFO_GET 80 +#define TX_EL_TIMER_PERFORMANCE_SYSTEM_INFO_GET 81 + + +/* Define ThreadX sub-types. */ + +#define TX_EL_INTERRUPT_SUB_TYPE 1 +#define TX_EL_END_OF_INTERRUPT 3 + + +/* Define event logging filters, which may be used by the application program to + dynamically enable/disable events in run-time. */ + +#define TX_EL_FILTER_STATUS_CHANGE 0x0001 +#define TX_EL_FILTER_INTERRUPTS 0x0002 +#define TX_EL_FILTER_THREAD_CALLS 0x0004 +#define TX_EL_FILTER_TIMER_CALLS 0x0008 +#define TX_EL_FILTER_EVENT_FLAG_CALLS 0x0010 +#define TX_EL_FILTER_SEMAPHORE_CALLS 0x0020 +#define TX_EL_FILTER_QUEUE_CALLS 0x0040 +#define TX_EL_FILTER_BLOCK_CALLS 0x0080 +#define TX_EL_FILTER_BYTE_CALLS 0x0100 +#define TX_EL_FILTER_MUTEX_CALLS 0x0200 +#define TX_EL_FILTER_ALL_EVENTS 0xFFFF +#define TX_EL_ENABLE_ALL_EVENTS 0x0000 + + +/* Define filter macros that are inserted in-line with the other macros below. */ + +#ifdef TX_ENABLE_EVENT_FILTERS +#define TX_EL_NO_STATUS_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_STATUS_CHANGE)) { +#define TX_EL_NO_INTERRUPT_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_INTERRUPTS)) { +#define TX_EL_NO_THREAD_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_THREAD_CALLS)) { +#define TX_EL_NO_TIMER_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_TIMER_CALLS)) { +#define TX_EL_NO_EVENT_FLAG_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_EVENT_FLAG_CALLS)) { +#define TX_EL_NO_SEMAPHORE_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_SEMAPHORE_CALLS)) { +#define TX_EL_NO_QUEUE_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_QUEUE_CALLS)) { +#define TX_EL_NO_BLOCK_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_BLOCK_CALLS)) { +#define TX_EL_NO_BYTE_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_BYTE_CALLS)) { +#define TX_EL_NO_MUTEX_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_MUTEX_CALLS)) { +#define TX_EL_END_FILTER } +#else +#define TX_EL_NO_STATUS_EVENTS +#define TX_EL_NO_INTERRUPT_EVENTS +#define TX_EL_NO_THREAD_EVENTS +#define TX_EL_NO_TIMER_EVENTS +#define TX_EL_NO_EVENT_FLAG_EVENTS +#define TX_EL_NO_SEMAPHORE_EVENTS +#define TX_EL_NO_QUEUE_EVENTS +#define TX_EL_NO_BLOCK_EVENTS +#define TX_EL_NO_BYTE_EVENTS +#define TX_EL_NO_MUTEX_EVENTS +#define TX_EL_END_FILTER +#endif + +/* Define externs and constants for non-event log source modules. This is for + the in-line macros below. */ + +#ifndef TX_EL_SOURCE_CODE +extern UCHAR *_tx_el_tni_start; +extern UCHAR **_tx_el_current_event; +extern UCHAR *_tx_el_event_area_start; +extern UCHAR *_tx_el_event_area_end; +extern UINT _tx_el_maximum_events; +extern ULONG _tx_el_total_events; +extern TX_THREAD *_tx_thread_current_ptr; +extern UINT _tx_el_event_filter; +extern ULONG _tx_el_time_base_upper; +extern ULONG _tx_el_time_base_lower; + + +/* Define macros for event logging functions. */ + +#define TX_EL_THREAD_CREATE_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO4(TX_EL_THREAD_CREATE, thread_ptr, stack_start, stack_size, priority); TX_EL_END_FILTER +#define TX_EL_EVENT_FLAGS_SET_INSERT TX_EL_NO_EVENT_FLAG_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_EVENT_FLAGS_SET, group_ptr, flags_to_set, set_option); TX_EL_END_FILTER +#define TX_EL_THREAD_DELETE_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_DELETE, thread_ptr); TX_EL_END_FILTER +#define TX_EL_THREAD_INFO_GET_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_INFO_GET, thread_ptr); TX_EL_END_FILTER +#define TX_EL_THREAD_TIME_SLICE_CHANGE_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_THREAD_TIME_SLICE_CHANGE, thread_ptr, thread_ptr -> tx_thread_new_time_slice, new_time_slice); TX_EL_END_FILTER +#define TX_EL_THREAD_TERMINATE_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_TERMINATE, thread_ptr); TX_EL_END_FILTER +#define TX_EL_THREAD_SLEEP_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_SLEEP, timer_ticks); TX_EL_END_FILTER +#define TX_EL_THREAD_SUSPEND_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_SUSPEND, thread_ptr); TX_EL_END_FILTER +#define TX_EL_THREAD_RELINQUISH_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_THREAD_RELINQUISH); TX_EL_END_FILTER +#define TX_EL_THREAD_RESUME_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_RESUME, thread_ptr); TX_EL_END_FILTER +#define TX_EL_THREAD_PRIORITY_CHANGE_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_THREAD_PRIORITY_CHANGE, thread_ptr, thread_ptr -> tx_thread_priority, new_priority); TX_EL_END_FILTER +#define TX_EL_THREAD_PREEMPTION_CHANGE_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_THREAD_PREEMPTION_CHANGE, thread_ptr, thread_ptr -> tx_thread_preempt_threshold, new_threshold); TX_EL_END_FILTER +#define TX_EL_THREAD_WAIT_ABORT_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_WAIT_ABORT, thread_ptr); TX_EL_END_FILTER +#define TX_EL_THREAD_ENTRY_EXIT_NOTIFY_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_THREAD_ENTRY_EXIT_NOTIFY, thread_ptr, thread_entry_exit_notify); TX_EL_END_FILTER +#define TX_EL_THREAD_RESET_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_RESET, thread_ptr); TX_EL_END_FILTER +#define TX_EL_THREAD_PERFORMANCE_INFO_GET_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_PERFORMANCE_INFO_GET, thread_ptr); TX_EL_END_FILTER +#define TX_EL_THREAD_PERFORMANCE_SYSTEM_INFO_GET_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_THREAD_PERFORMANCE_SYSTEM_INFO_GET); TX_EL_END_FILTER +#define TX_EL_THREAD_STACK_ERROR_NOTIFY_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_STACK_ERROR_NOTIFY, stack_error_handler); TX_EL_END_FILTER +#define TX_EL_TIME_SET_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_TIME_SET, new_time); TX_EL_END_FILTER +#define TX_EL_TIME_GET_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_TIME_GET, _tx_timer_system_clock); TX_EL_END_FILTER +#define TX_EL_TIMER_DELETE_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_TIMER_DELETE, timer_ptr); TX_EL_END_FILTER +#define TX_EL_TIMER_CREATE_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO4(TX_EL_TIMER_CREATE, timer_ptr, initial_ticks, reschedule_ticks, auto_activate); TX_EL_END_FILTER +#define TX_EL_TIMER_CHANGE_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_TIMER_CHANGE, timer_ptr, initial_ticks, reschedule_ticks); TX_EL_END_FILTER +#define TX_EL_THREAD_IDENTIFY_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_THREAD_IDENTIFY); TX_EL_END_FILTER +#define TX_EL_TIMER_DEACTIVATE_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_TIMER_DEACTIVATE, timer_ptr); TX_EL_END_FILTER +#define TX_EL_TIMER_ACTIVATE_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_TIMER_ACTIVATE, timer_ptr); TX_EL_END_FILTER +#define TX_EL_TIMER_INFO_GET_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_TIMER_INFO_GET, timer_ptr); TX_EL_END_FILTER +#define TX_EL_TIMER_PERFORMANCE_INFO_GET_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_TIMER_PERFORMANCE_INFO_GET, timer_ptr); TX_EL_END_FILTER +#define TX_EL_TIMER_PERFORMANCE_SYSTEM_INFO_GET_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_TIMER_PERFORMANCE_SYSTEM_INFO_GET); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_PUT_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_SEMAPHORE_PUT, semaphore_ptr, semaphore_ptr -> tx_semaphore_count); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_GET_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_SEMAPHORE_GET, semaphore_ptr, semaphore_ptr -> tx_semaphore_count); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_DELETE_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_SEMAPHORE_DELETE, semaphore_ptr); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_CREATE_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_SEMAPHORE_CREATE, semaphore_ptr, initial_count); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_INFO_GET_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_SEMAPHORE_INFO_GET, semaphore_ptr); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_PRIORITIZE_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_SEMAPHORE_PRIORITIZE, semaphore_ptr); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_CEILING_PUT_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_SEMAPHORE_CEILING_PUT, semaphore_ptr, semaphore_ptr -> tx_semaphore_count, ceiling); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_PERFORMANCE_INFO_GET_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_SEMAPHORE_PERFORMANCE_INFO_GET, semaphore_ptr); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_PERFORMANCE_SYSTEM_INFO_GET_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_SEMAPHORE_PERFORMANCE_SYSTEM_INFO_GET); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_PUT_NOTIFY_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_SEMAPHORE_PUT_NOTIFY, semaphore_ptr, semaphore_put_notify); TX_EL_END_FILTER +#define TX_EL_QUEUE_FRONT_SEND_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_QUEUE_FRONT_SEND, queue_ptr, source_ptr); TX_EL_END_FILTER +#define TX_EL_QUEUE_SEND_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_QUEUE_SEND, queue_ptr, source_ptr); TX_EL_END_FILTER +#define TX_EL_QUEUE_RECEIVE_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_QUEUE_RECEIVE, queue_ptr, destination_ptr); TX_EL_END_FILTER +#define TX_EL_QUEUE_FLUSH_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_QUEUE_FLUSH, queue_ptr); TX_EL_END_FILTER +#define TX_EL_QUEUE_DELETE_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_QUEUE_DELETE, queue_ptr); TX_EL_END_FILTER +#define TX_EL_QUEUE_CREATE_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO4(TX_EL_QUEUE_CREATE, queue_ptr, queue_start, queue_size, message_size); TX_EL_END_FILTER +#define TX_EL_QUEUE_INFO_GET_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_QUEUE_INFO_GET, queue_ptr); TX_EL_END_FILTER +#define TX_EL_QUEUE_PRIORITIZE_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_QUEUE_PRIORITIZE, queue_ptr); TX_EL_END_FILTER +#define TX_EL_QUEUE_PERFORMANCE_INFO_GET_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_QUEUE_PERFORMANCE_INFO_GET, queue_ptr); TX_EL_END_FILTER +#define TX_EL_QUEUE_PERFORMANCE_SYSTEM_INFO_GET_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_QUEUE_PERFORMANCE_SYSTEM_INFO_GET); TX_EL_END_FILTER +#define TX_EL_QUEUE_SEND_NOTIFY_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_QUEUE_SEND_NOTIFY, queue_ptr, queue_send_notify); TX_EL_END_FILTER +#define TX_EL_EVENT_FLAGS_GET_INSERT TX_EL_NO_EVENT_FLAG_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_EVENT_FLAGS_GET, group_ptr, requested_flags, get_option); TX_EL_END_FILTER +#define TX_EL_EVENT_FLAGS_DELETE_INSERT TX_EL_NO_EVENT_FLAG_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_EVENT_FLAGS_DELETE, group_ptr); TX_EL_END_FILTER +#define TX_EL_EVENT_FLAGS_CREATE_INSERT TX_EL_NO_EVENT_FLAG_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_EVENT_FLAGS_CREATE, group_ptr); TX_EL_END_FILTER +#define TX_EL_EVENT_FLAGS_INFO_GET_INSERT TX_EL_NO_EVENT_FLAG_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_EVENT_FLAGS_INFO_GET, group_ptr); TX_EL_END_FILTER +#define TX_EL_EVENT_FLAGS_PERFORMANCE_INFO_GET_INSERT TX_EL_NO_EVENT_FLAG_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_EVENT_FLAGS_PERFORMANCE_INFO_GET, group_ptr); TX_EL_END_FILTER +#define TX_EL_EVENT_FLAGS_PERFORMANCE_SYSTEM_INFO_GET_INSERT TX_EL_NO_EVENT_FLAG_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_EVENT_FLAGS_PERFORMANCE_SYSTEM_INFO_GET); TX_EL_END_FILTER +#define TX_EL_EVENT_FLAGS_SET_NOTIFY_INSERT TX_EL_NO_EVENT_FLAG_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_EVENT_FLAGS_SET_NOTIFY, group_ptr, events_set_notify); TX_EL_END_FILTER +#define TX_EL_BYTE_RELEASE_INSERT TX_EL_NO_BYTE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_BYTE_RELEASE, pool_ptr, memory_ptr); TX_EL_END_FILTER +#define TX_EL_BYTE_POOL_DELETE_INSERT TX_EL_NO_BYTE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_BYTE_POOL_DELETE, pool_ptr); TX_EL_END_FILTER +#define TX_EL_BYTE_POOL_CREATE_INSERT TX_EL_NO_BYTE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_BYTE_POOL_CREATE, pool_ptr, pool_start, pool_size); TX_EL_END_FILTER +#define TX_EL_BYTE_POOL_INFO_GET_INSERT TX_EL_NO_BYTE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_BYTE_POOL_INFO_GET, pool_ptr); TX_EL_END_FILTER +#define TX_EL_BYTE_POOL_PRIORITIZE_INSERT TX_EL_NO_BYTE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_BYTE_POOL_PRIORITIZE, pool_ptr); TX_EL_END_FILTER +#define TX_EL_BYTE_ALLOCATE_INSERT TX_EL_NO_BYTE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_BYTE_ALLOCATE, pool_ptr, memory_ptr, memory_size); TX_EL_END_FILTER +#define TX_EL_BYTE_POOL_PERFORMANCE_INFO_GET_INSERT TX_EL_NO_BYTE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_BYTE_POOL_PERFORMANCE_INFO_GET, pool_ptr); TX_EL_END_FILTER +#define TX_EL_BYTE_POOL_PERFORMANCE_SYSTEM_INFO_GET_INSERT TX_EL_NO_BYTE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_BYTE_POOL_PERFORMANCE_SYSTEM_INFO_GET); TX_EL_END_FILTER +#define TX_EL_BLOCK_RELEASE_INSERT TX_EL_NO_BLOCK_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_BLOCK_RELEASE, pool_ptr, block_ptr); TX_EL_END_FILTER +#define TX_EL_BLOCK_POOL_DELETE_INSERT TX_EL_NO_BLOCK_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_BLOCK_POOL_DELETE, pool_ptr); TX_EL_END_FILTER +#define TX_EL_BLOCK_POOL_CREATE_INSERT TX_EL_NO_BLOCK_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO4(TX_EL_BLOCK_POOL_CREATE, pool_ptr, pool_start, pool_size, block_size); TX_EL_END_FILTER +#define TX_EL_BLOCK_POOL_INFO_GET_INSERT TX_EL_NO_BLOCK_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_BLOCK_POOL_INFO_GET, pool_ptr); TX_EL_END_FILTER +#define TX_EL_BLOCK_POOL_PRIORITIZE_INSERT TX_EL_NO_BLOCK_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_BLOCK_POOL_PRIORITIZE, pool_ptr); TX_EL_END_FILTER +#define TX_EL_BLOCK_ALLOCATE_INSERT TX_EL_NO_BLOCK_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_BLOCK_ALLOCATE, pool_ptr, block_ptr); TX_EL_END_FILTER +#define TX_EL_BLOCK_POOL_PERFORMANCE_INFO_GET_INSERT TX_EL_NO_BLOCK_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_BLOCK_POOL_PERFORMANCE_INFO_GET, pool_ptr); TX_EL_END_FILTER +#define TX_EL_BLOCK_POOL_PERFORMANCE_SYSTEM_INFO_GET_INSERT TX_EL_NO_BLOCK_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_BLOCK_POOL_PERFORMANCE_SYSTEM_INFO_GET); TX_EL_END_FILTER +#define TX_EL_MUTEX_CREATE_INSERT TX_EL_NO_MUTEX_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_MUTEX_CREATE, mutex_ptr, inherit); TX_EL_END_FILTER +#define TX_EL_MUTEX_DELETE_INSERT TX_EL_NO_MUTEX_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_MUTEX_DELETE, mutex_ptr); TX_EL_END_FILTER +#define TX_EL_MUTEX_GET_INSERT TX_EL_NO_MUTEX_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_MUTEX_GET, mutex_ptr, mutex_ptr -> tx_mutex_owner, mutex_ptr -> tx_mutex_ownership_count); TX_EL_END_FILTER +#define TX_EL_MUTEX_INFO_GET_INSERT TX_EL_NO_MUTEX_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_MUTEX_INFO_GET, mutex_ptr); TX_EL_END_FILTER +#define TX_EL_MUTEX_PRIORITIZE_INSERT TX_EL_NO_MUTEX_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_MUTEX_PRIORITIZE, mutex_ptr); TX_EL_END_FILTER +#define TX_EL_MUTEX_PUT_INSERT TX_EL_NO_MUTEX_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_MUTEX_PUT, mutex_ptr, mutex_ptr -> tx_mutex_owner, mutex_ptr -> tx_mutex_ownership_count); TX_EL_END_FILTER +#define TX_EL_MUTEX_PERFORMANCE_INFO_GET_INSERT TX_EL_NO_MUTEX_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_MUTEX_PERFORMANCE_INFO_GET, mutex_ptr); TX_EL_END_FILTER +#define TX_EL_MUTEX_PERFORMANCE_SYSTEM_INFO_GET_INSERT TX_EL_NO_MUTEX_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_MUTEX_PERFORMANCE_SYSTEM_INFO_GET); TX_EL_END_FILTER + + +#endif + + +/* Define Event Log function prototypes. */ + +VOID _tx_el_initialize(VOID); +UINT _tx_el_thread_register(TX_THREAD *thread_ptr); +UINT _tx_el_thread_unregister(TX_THREAD *thread_ptr); +VOID _tx_el_user_event_insert(UINT sub_type, ULONG info_1, ULONG info_2, + ULONG info_3, ULONG info_4); +VOID _tx_el_thread_running(TX_THREAD *thread_ptr); +VOID _tx_el_thread_preempted(TX_THREAD *thread_ptr); +VOID _tx_el_interrupt(UINT interrupt_number); +VOID _tx_el_interrupt_end(UINT interrupt_number); +VOID _tx_el_interrupt_control_call(void); +VOID _tx_el_event_log_on(void); +VOID _tx_el_event_log_off(void); +VOID _tx_el_event_filter_set(UINT filter); + + +/* Define macros that are used inside the ThreadX source code. + If event logging is disabled, these macros will be defined + as white space. */ + +#ifdef TX_ENABLE_EVENT_LOGGING +#ifndef TX_NO_EVENT_INFO +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO4(a, b, c, d, e) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_current_ptr;\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_1_OFFSET)) =\ + (ULONG) b;\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_2_OFFSET)) =\ + (ULONG) c;\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_3_OFFSET)) =\ + (ULONG) d;\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_4_OFFSET)) =\ + (ULONG) e;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(a, b, c, d) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_current_ptr;\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_1_OFFSET)) =\ + (ULONG) b;\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_2_OFFSET)) =\ + (ULONG) c;\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_3_OFFSET)) =\ + (ULONG) d;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(a, b, c) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_current_ptr;\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_1_OFFSET)) =\ + (ULONG) b;\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_2_OFFSET)) =\ + (ULONG) c;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(a, b) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_current_ptr;\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_1_OFFSET)) =\ + (ULONG) b;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(a) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_current_ptr;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_THREAD_STATUS_CHANGE_INSERT(a, b) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + TX_EL_NO_STATUS_EVENTS \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREAD_STATUS_CHANGE; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) b; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) a;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + TX_EL_END_FILTER \ + } +#define TX_EL_THREAD_REGISTER(a) \ + _tx_el_thread_register(a); +#define TX_EL_THREAD_UNREGISTER(a) \ + _tx_el_thread_unregister(a); +#define TX_EL_INITIALIZE _tx_el_initialize(); +#else +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO4(a, b, c, d, e) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_current_ptr;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(a, b, c, d) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_current_ptr;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(a, b, c) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_current_ptr;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(a, b) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_current_ptr;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(a) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_current_ptr;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_THREAD_STATUS_CHANGE_INSERT(a, b) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + TX_EL_NO_STATUS_EVENTS \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREAD_STATUS_CHANGE; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) b; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) a;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + TX_EL_END_FILTER \ + } +#define TX_EL_THREAD_REGISTER(a) \ + _tx_el_thread_register(a); +#define TX_EL_THREAD_UNREGISTER(a) \ + _tx_el_thread_unregister(a); +#define TX_EL_INITIALIZE _tx_el_initialize(); +#endif +#else +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO4(a, b, c, d, e) +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(a, b, c, d) +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(a, b, c) +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(a, b) +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(a) +#define TX_EL_THREAD_STATUS_CHANGE_INSERT(a, b) +#define TX_EL_THREAD_REGISTER(a) +#define TX_EL_THREAD_UNREGISTER(a) +#define TX_EL_INITIALIZE +#endif + +#endif + diff --git a/ports/cortex_m4/ghs/inc/tx_ghs.h b/ports/cortex_m4/ghs/inc/tx_ghs.h new file mode 100644 index 00000000..ca976916 --- /dev/null +++ b/ports/cortex_m4/ghs/inc/tx_ghs.h @@ -0,0 +1,77 @@ +/* + * ThreadX C/C++ Library Support + * + * Copyright 1983-2019 Green Hills Software LLC. + * + * This program is the property of Green Hills Software LLC., + * its contents are proprietary information and no part of it + * is to be disclosed to anyone except employees of Green Hills + * Software LLC., or as agreed in writing signed by the President + * of Green Hills Software LLC. + */ + +#ifndef _TX_GHS_H_ +#define _TX_GHS_H_ + +#include +#include +#include +#include + +#if defined(__ghs) && (__GHS_VERSION_NUMBER >= 500) +extern void *__ghs_GetThreadLocalStorageItem(int specifier); + +/* Thread-local storage routines for Green Hills releases 5.x and beyond. + The following specifiers are used when calling + __ghs_GetThreadLocalStorageItem. + + If __ghs_GetThreadLocalStorageItem is customized to + return a per-thread errno value, define the preprocessor symbol + USE_THREAD_LOCAL_ERRNO in ind_errn.c. + */ + +enum __ghs_ThreadLocalStorage_specifier { + __ghs_TLS_asctime_buff, + __ghs_TLS_tmpnam_space, + __ghs_TLS_strtok_saved_pos, + __ghs_TLS_Errno, + __ghs_TLS_gmtime_temp, + __ghs_TLS___eh_globals, + __ghs_TLS_SignalHandlers +}; +#else +/* Thread-local storage routines for Green Hills releases 4.x and 3.x . */ +typedef void (*SignalHandler)(int); + +typedef struct +{ + int Errno; /* errno. */ + SignalHandler SignalHandlers[_SIGMAX]; /* signal() buffer. */ + char tmpnam_space[L_tmpnam]; /* tmpnam(NULL) buffer. */ + char asctime_buff[30]; /* . */ + char *strtok_saved_pos; /* strtok() position. */ + struct tm gmtime_temp; /* gmtime() and localtime() buffer. */ + void *__eh_globals; /* Pointer for C++ exception handling. */ +} ThreadLocalStorage; + +ThreadLocalStorage *GetThreadLocalStorage(void); +#endif + + +void __ghsLock(void); +void __ghsUnlock(void); + +int __ghs_SaveSignalContext(jmp_buf); +void __ghs_RestoreSignalContext(jmp_buf); + +/* prototypes for FILE lock routines. */ +void __ghs_flock_file(void *); +void __ghs_funlock_file(void *); +int __ghs_ftrylock_file(void *); +void __ghs_flock_create(void **); +void __ghs_flock_destroy(void *); + +/* prototype for GHS/ThreadX error shell checking. */ +void __ghs_rnerr(char *errMsg, int stackLevels, int stackTraceDisplay, void *hexVal); + +#endif /* _TX_GHS_H_ */ diff --git a/ports/cortex_m4/ghs/inc/tx_port.h b/ports/cortex_m4/ghs/inc/tx_port.h new file mode 100644 index 00000000..3370092a --- /dev/null +++ b/ports/cortex_m4/ghs/inc/tx_port.h @@ -0,0 +1,396 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-M4/GHS */ +/* 6.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include +#include +#include "tx_ghs.h" + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM Cortex-M port. */ + +#define TX_INT_DISABLE 1 /* Disable interrupts */ +#define TX_INT_ENABLE 0 /* Enable interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define constants for Green Hills EventAnalyzer. */ + +/* Define the number of ticks per second. This informs the EventAnalyzer what the timestamps + represent. By default, this is set to 1,000,000 i.e., one tick every microsecond. */ + +#define TX_EL_TICKS_PER_SECOND 1000000 + +/* Define the method of how to get the upper and lower 32-bits of the time stamp. By default, simply + simulate the time-stamp source with a counter. */ + +#define read_tbu() _tx_el_time_base_upper +#define read_tbl() ++_tx_el_time_base_lower + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 VOID * tx_thread_eh_globals; \ + int Errno; /* errno. */ \ + char * strtok_saved_pos; /* strtok() position. */ +#ifndef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#define TX_THREAD_EXTENSION_3 +#else +#define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ + unsigned long long tx_thread_execution_time_last_start; +#endif + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + +#if (__GHS_VERSION_NUMBER >= 500) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) \ + { \ + extern void __tx_cpp_exception_init(TX_THREAD *thread_ptr); \ + __tx_cpp_exception_init(thread_ptr); \ + } +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) \ + { \ + #pragma weak __cpp_exception_init \ + extern void __cpp_exception_init(void **); \ + static void (*const cpp_init_funcp)(void **) = __cpp_exception_init; \ + if (cpp_init_funcp) \ + __cpp_exception_init(&(thread_ptr -> tx_thread_eh_globals)); \ + } +#endif + +#if (__GHS_VERSION_NUMBER >= 500) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) \ + { \ + extern void __tx_cpp_exception_cleanup(TX_THREAD *thread_ptr); \ + __tx_cpp_exception_cleanup(thread_ptr); \ + } +#else +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) \ + { \ + #pragma weak __cpp_exception_cleanup \ + extern void __cpp_exception_cleanup(void **); \ + static void (*const cpp_cleanup_funcp)(void **) = \ + __cpp_exception_cleanup; \ + if (cpp_cleanup_funcp) \ + __cpp_exception_cleanup(&(thread_ptr -> tx_thread_eh_globals)); \ + } +#endif + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define the get system state macro. */ + +#ifndef TX_THREAD_GET_SYSTEM_STATE +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | __MRS(__IPSR)) +#endif + + +/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value + indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h + for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always + zero after initialization for Cortex-M ports. */ + +#ifndef TX_THREAD_SYSTEM_RETURN_CHECK +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#endif + + +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to + prevent early scheduling on Cortex-M parts. */ + +#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + b = __CLZ32(m); \ + b = 31 - b; + +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifdef TX_DISABLE_INLINE + +UINT _tx_thread_interrupt_disable(VOID); +VOID _tx_thread_interrupt_restore(UINT previous_posture); + +#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); + +#define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; + +/* Define ThreadX interrupt lockout and restore macros using + asm macros. */ + +asm int disable_ints(void) +{ +% + MRS r0,PRIMASK + MOV r1,1 + MSR PRIMASK,r1 +%error +} + +asm void restore_ints(int a) +{ +%reg a + MSR PRIMASK,a +%mem a + LDR r0,a + MSR PRIMASK,r0 +%error +} + +#define TX_DISABLE interrupt_save = disable_ints(); + +#define TX_RESTORE restore_ints(interrupt_save); + +#endif + + +/* Define FPU extension for the Cortex-M4. Each is assumed to be called in the context of the executing + thread. These are no longer needed, but are preserved for backward compatibility only. */ + +void tx_thread_fpu_enable(void); +void tx_thread_fpu_disable(void); + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/GHS Version 6.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + + + diff --git a/ports/cortex_m4/ghs/readme_threadx.txt b/ports/cortex_m4/ghs/readme_threadx.txt new file mode 100644 index 00000000..ad268020 --- /dev/null +++ b/ports/cortex_m4/ghs/readme_threadx.txt @@ -0,0 +1,233 @@ + Microsoft's Azure RTOS ThreadX for Cortex-M4 + + Using the Green Hills Software Tools + +1. Open the ThreadX Project Workspace + +In order to build the ThreadX library and the ThreadX demonstration first load +the Azure RTOS Workspace azure_rtos_workspace.gpj, which is located inside the +"example_build" directory. + + +2. Building the ThreadX run-time Library + +Building the ThreadX library is easy; simply select the MULTI project file +tx.gpj and then select the build button. You should now observe the +compilation and assembly of the ThreadX library. This project build produces +the ThreadX library file tx.a. + + +3. Demonstration System + +The ThreadX demonstration is designed to execute under the MULTI environment +on the Green Hills Cortex-M4 simulator. The instructions that follow describe +how to get the ThreadX evaluation running under the MULTI Cortex-M4 simulation +environment. + +Building the demonstration is easy; simply select the MULTI project file +sample_threadx.gpj. At this point, select the "Project Build" button and observe +the compilation, assembly, and linkage of the ThreadX demonstration application. + +After the demonstration is built, invoke the MULTI ARM simulator by selecting +the simulator connection from within the sample_threadx.con connection file. +Once connected to the simulator, select the "Debug" button. You should now +observe the main function of sample_threadx.c. + +You are now ready to execute the ThreadX demonstration system. Select +breakpoints and data watches to observe the execution of the sample_threadx.c +application. + + +4. EventAnalyzer Demonstration + +To build a demonstration system that also logs events for the MULTI EventAnalyzer, +perform the same steps as the regular demo, except build the ThreadX library with +txe.gpj file and use the sample_threadx_el.gpj build file to build the demonstration. +The resulting image will log all system events, which can then be displayed by the +MULTI EventAnalyzer. + + +5. System Initialization + +The system entry point using the Green Hills tools is at the label _start. +This is defined within the crt0.arm file supplied by Green Hills. In addition, +this is where all static and global preset C variable initialization +processing is called from. + +After the Green Hills startup function returns, ThreadX initialization is +called. The main initialization function is _tx_initialize_low_level and +is located in the file tx_initialize_low_level.arm. This function is responsible +for setting up various system data structures, interrupt vectors, and the +periodic timer interrupt source of ThreadX. + +In addition, _tx_initialize_low_level determines where the first available +RAM memory address is located. This address is supplied to tx_application_define. + +By default, the first available RAM memory address is assumed to start at the +beginning of the ThreadX section .free_mem. If changes are made to the +sample_threadx.ld file, the .free_mem section should remain the last allocated +section in the main RAM area. The starting address of this section is passed +to tx_application_define. + + +6. Register Usage and Stack Frames + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have the same stack frame in the Cortex-M4 version of +ThreadX. The top of the suspended thread's stack is pointed to by +tx_thread_stack_ptr in the associated thread control block TX_THREAD. + + +Non-FPU Stack Frame: + + Stack Offset Stack Contents + + 0x00 r4 + 0x04 r5 + 0x08 r6 + 0x0C r7 + 0x10 r8 + 0x14 r9 + 0x18 r10 + 0x1C r11 + 0x20 r0 (Hardware stack starts here!!) + 0x24 r1 + 0x28 r2 + 0x2C r3 + 0x30 r12 + 0x34 lr + 0x38 pc + 0x3C xPSR + +FPU Stack Frame (only interrupted thread with FPU enabled): + + Stack Offset Stack Contents + + 0x00 s0 + 0x04 s1 + 0x08 s2 + 0x0C s3 + 0x10 s4 + 0x14 s5 + 0x18 s6 + 0x1C s7 + 0x20 s8 + 0x24 s9 + 0x28 s10 + 0x2C s11 + 0x30 s12 + 0x34 s13 + 0x38 s14 + 0x3C s15 + 0x40 s16 + 0x44 s17 + 0x48 s18 + 0x4C s19 + 0x50 s20 + 0x54 s21 + 0x58 s22 + 0x5C s23 + 0x60 s24 + 0x64 s25 + 0x68 s26 + 0x6C s27 + 0x70 s28 + 0x74 s29 + 0x78 s30 + 0x7C s31 + 0x80 fpscr + 0x84 r4 + 0x88 r5 + 0x8C r6 + 0x90 r7 + 0x94 r8 + 0x98 r9 + 0x9C r10 (sl) + 0xA0 r11 + 0xA4 r0 (Hardware stack starts here!!) + 0xA8 r1 + 0xAC r2 + 0xB0 r3 + 0xB4 r12 + 0xB8 lr + 0xBC pc + 0xC0 xPSR + + +7. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make ThreadX run faster, you can change the tx.gpj project +to disable debug information and enable the desired optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined before tx_api.h is included. + + +8. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-M4 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +8.1 Vector Area + +The Cortex-M4 vectors start at the label __tx_vectors. The application may modify +the vector area according to its needs. + + +8.2 Managed Interrupts + +A ThreadX managed interrupt is defined below. By following these conventions, the +application ISR is then allowed access to various ThreadX services from the ISR. +Here is the standard template for managed ISRs in ThreadX: + + + .globl __tx_IntHandler +__tx_IntHandler: + PUSH {lr} + BL _tx_thread_context_save + + /* Do interrupt handler work here */ + + B _tx_thread_context_restore + + +9. FPU Support + +By default, FPU support is disabled for each thread. If saving the context of the FPU registers +is needed, the ThreadX library should be re-built with TX_ENABLE_FPU_SUPPORT defined. In addition, +the following API call must be made from the context of the application thread - before +the FPU usage: + +void tx_thread_fpu_enable(void); + +After this API is called in the application, FPU registers will be saved/restored for this thread if it +is preempted via an interrupt. All other suspension of the this thread will not require the FPU registers +to be saved/restored. + +To disable FPU register context saving, simply call the following API: + +void tx_thread_fpu_disable(void); + + + +10. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +05/19/2020 Initial ThreadX version of Cortex-M4/Green Hills port. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_m4/ghs/src/tx_el.c b/ports/cortex_m4/ghs/src/tx_el.c new file mode 100644 index 00000000..e2c39a1d --- /dev/null +++ b/ports/cortex_m4/ghs/src/tx_el.c @@ -0,0 +1,1165 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** ThreadX/GHS Event Log (EL) */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_EL_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_el.h" +#include "string.h" + + +/* Define global variables used to manage the event pool. */ + +UCHAR *_tx_el_tni_start; +UCHAR **_tx_el_current_event; +UCHAR *_tx_el_event_area_start; +UCHAR *_tx_el_event_area_end; +UINT _tx_el_maximum_events; +ULONG _tx_el_total_events; +UINT _tx_el_event_filter; +ULONG _tx_el_time_base_upper; +ULONG _tx_el_time_base_lower; + +extern char __ghsbegin_eventlog[]; +extern char __ghsend_eventlog[]; + +extern TX_THREAD *_tx_thread_current_ptr; +UINT _tx_thread_interrupt_control(UINT new_posture); + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_initialize PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates the Event Log (in the format dictated by the */ +/* GHS Event Analyzer) and sets up various information for subsequent */ +/* operation. The start and end of the Event Log is determined by the */ +/* .eventlog section in the linker control file. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_el_initialize(VOID) +{ + +UCHAR *work_ptr; +UCHAR *read_ptr; +ULONG event_log_size; +UCHAR *end_ptr; +UINT i; + + + /* Clear total event counter. */ + _tx_el_total_events = 0; + + /* Clear event filter. */ + _tx_el_event_filter = 0; + + /* First, pickup the starting and ending address of the Event Log memory. */ + work_ptr = (unsigned char *) __ghsbegin_eventlog; + end_ptr = (unsigned char *) __ghsend_eventlog; + + /* Calculate the event log size. */ + event_log_size = end_ptr - work_ptr; + + /* Subtract off the number of bytes in the header and the TNI area. */ + event_log_size = event_log_size - (TX_EL_HEADER_SIZE + + (TX_EL_TNI_ENTRY_SIZE * TX_EL_TNIS)); + + /* Make sure the event log is evenly divisible by the event size. */ + event_log_size = (event_log_size/TX_EL_EVENT_SIZE) * TX_EL_EVENT_SIZE; + + /* Build the Event Log header. */ + + /* Setup the Event Log Version ID. */ + *((unsigned short *) work_ptr) = (unsigned short) TX_EL_VERSION_ID; + work_ptr = work_ptr + sizeof(unsigned short); + + /* Setup the TNIS (number of thread names) field. */ + *((unsigned short *) work_ptr) = (unsigned short) TX_EL_TNIS; + work_ptr = work_ptr + sizeof(unsigned short); + + /* Setup the EVPS (event pool size) field. */ + *((ULONG *) work_ptr) = event_log_size; + work_ptr = work_ptr + sizeof(ULONG); + + /* Remember the maximum number of events. */ + _tx_el_maximum_events = event_log_size/TX_EL_EVENT_SIZE; + + /* Setup max_events field. */ + *((ULONG *) work_ptr) = _tx_el_maximum_events; + work_ptr = work_ptr + sizeof(ULONG); + + /* Setup the evploc (location of event pool). */ + *((ULONG *) work_ptr) = (ULONG) (((ULONG) __ghsbegin_eventlog) + TX_EL_HEADER_SIZE + + (TX_EL_TNIS * TX_EL_TNI_ENTRY_SIZE)); + work_ptr = work_ptr + sizeof(ULONG); + + /* Save the current event pointer. */ + _tx_el_current_event = (UCHAR **) work_ptr; + + /* Setup event_ptr (pointer to oldest event) field to the start + of the event pool. */ + *_tx_el_current_event = (UCHAR *) (((ULONG) __ghsbegin_eventlog) + TX_EL_HEADER_SIZE + + (TX_EL_TNIS * TX_EL_TNI_ENTRY_SIZE)); + work_ptr = work_ptr + sizeof(ULONG); + + /* Setup tbfreq (the number of ticks in a second) field. */ + *((ULONG *) work_ptr) = TX_EL_TICKS_PER_SECOND; + work_ptr = work_ptr + sizeof(ULONG); + + /* At this point we are pointing at the Thread Name Information (TNI) array. */ + + /* Remember the start of this for future updates. */ + _tx_el_tni_start = work_ptr; + + /* Clear the entire TNI array, this is the initial setting. */ + end_ptr = work_ptr + (TX_EL_TNIS * TX_EL_TNI_ENTRY_SIZE); + memset((void *)work_ptr, 0, (TX_EL_TNIS * TX_EL_TNI_ENTRY_SIZE)); + work_ptr = end_ptr; + + /* At this point, we are pointing at the actual Event Entry area. */ + + /* Remember the start of the actual event log area. */ + _tx_el_event_area_start = work_ptr; + + /* Clear the entire Event area. */ + end_ptr = work_ptr + event_log_size; + memset((void *)work_ptr, 0, event_log_size); + work_ptr = end_ptr; + + /* Save the end pointer for later use. */ + _tx_el_event_area_end = work_ptr; + + /* Setup an entry to resolve all activities from initialization and from + an idle system. */ + work_ptr = _tx_el_tni_start; + read_ptr = (UCHAR *) "Initialization/System Idle"; + i = 0; + while ((i < TX_EL_TNI_NAME_SIZE) && (*read_ptr)) + { + + /* Copy a character of thread's name into TNI area of log. */ + *work_ptr++ = *read_ptr++; + + /* Increment the character count. */ + i++; + } + + /* Determine if a NULL needs to be inserted. */ + if (i < TX_EL_TNI_NAME_SIZE) + { + + /* Yes, insert a NULL into the event log string. */ + *work_ptr = (unsigned char) 0; + } + + /* Setup the thread ID to NULL. */ + *((ULONG *) (_tx_el_tni_start + TX_EL_TNI_THREAD_ID_OFFSET)) = (ULONG) TX_NULL; + + /* Set the valid field to indicate the entry is complete. */ + *((UCHAR *) (_tx_el_tni_start + TX_EL_TNI_VALID_OFFSET)) = (ULONG) TX_EL_VALID_ENTRY; + + /* Clear the time base global variables. */ + _tx_el_time_base_upper = 0; + _tx_el_time_base_lower = 0; +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_thread_register PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers a thread in the event log for future */ +/* display purposes. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SUCCESS Thread was placed in TNI area */ +/* TX_ERROR No more room in the TNI area */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create ThreadX thread create function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _tx_el_thread_register(TX_THREAD *thread_ptr) +{ + +UCHAR *entry_ptr; +UCHAR *work_ptr; +UCHAR *read_ptr; +UINT i; + + + /* First of all, search for a free slot in the TNI area. */ + entry_ptr = _tx_el_tni_start; + i = 0; + while (i < TX_EL_TNIS) + { + + /* Determine if this entry is available. */ + if (*(entry_ptr + TX_EL_TNI_VALID_OFFSET) == TX_EL_INVALID_ENTRY) + break; + + /* Otherwise, increment the associated pointers and indices. */ + i++; + entry_ptr = entry_ptr + TX_EL_TNI_ENTRY_SIZE; + } + + /* Check to see if there were no more valid entries. */ + if (i >= TX_EL_TNIS) + return(TX_EL_NO_MORE_TNI_ROOM); + + /* Otherwise, we have room in the TNI and a valid record. */ + + /* Setup the thread's name. */ + work_ptr = entry_ptr; + read_ptr = (UCHAR *) thread_ptr -> tx_thread_name; + i = 0; + while ((i < TX_EL_TNI_NAME_SIZE) && (*read_ptr)) + { + + /* Copy a character of thread's name into TNI area of log. */ + *work_ptr++ = *read_ptr++; + + /* Increment the character count. */ + i++; + } + + /* Determine if a NULL needs to be inserted. */ + if (i < TX_EL_TNI_NAME_SIZE) + { + + /* Yes, insert a NULL into the event log string. */ + *work_ptr = (unsigned char) 0; + } + + /* Setup the thread ID. */ + *((ULONG *) (entry_ptr + TX_EL_TNI_THREAD_ID_OFFSET)) = (ULONG) thread_ptr; + + /* Setup the thread priority. */ + *((ULONG *) (entry_ptr + TX_EL_TNI_THREAD_PRIORITY_OFF)) = (ULONG) thread_ptr -> tx_thread_priority; + + /* Set the valid field to indicate the entry is complete. */ + *((UCHAR *) (entry_ptr + TX_EL_TNI_VALID_OFFSET)) = (ULONG) TX_EL_VALID_ENTRY; + + /* Thread name has been registered. */ + return(TX_SUCCESS); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_thread_unregister PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function unregisters a thread in the event log for future */ +/* display purposes. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SUCCESS Thread was placed in TNI area */ +/* TX_ERROR No more room in the TNI area */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create ThreadX thread create function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _tx_el_thread_unregister(TX_THREAD *thread_ptr) +{ + +UCHAR *entry_ptr; +UCHAR *work_ptr; +UCHAR *read_ptr; +UINT found; +UINT i, j; + + + /* First of all, search for a match in the TNI area. */ + entry_ptr = _tx_el_tni_start; + i = 0; + while (i < TX_EL_TNIS) + { + + /* Determine if this entry is a match. */ + work_ptr = entry_ptr; + read_ptr = (UCHAR *) thread_ptr -> tx_thread_name; + found = TX_TRUE; + j = 0; + do + { + + /* Determine if this character is the same. */ + if (*work_ptr != *read_ptr) + { + + /* Set found to false and fall out of the loop. */ + found = TX_FALSE; + break; + } + else if (*work_ptr == 0) + { + + /* Null terminated, just break the loop. */ + break; + } + else + { + + /* Copy a character of thread's name into TNI area of log. */ + *work_ptr++ = *read_ptr++; + } + + /* Increment the character count. */ + j++; + + } while(j < TX_EL_TNIS); + + + /* Was a match found? */ + if (found) + { + + /* Yes, mark the entry as available now. */ + *(entry_ptr + TX_EL_TNI_VALID_OFFSET) = TX_EL_INVALID_ENTRY; + + /* Get out of the loop! */ + break; + } + + /* Otherwise, increment the associated pointers and indices. */ + i++; + entry_ptr = entry_ptr + TX_EL_TNI_ENTRY_SIZE; + } + + /* Determine status to return. */ + if (found) + return(TX_SUCCESS); + else + return(TX_EL_NAME_NOT_FOUND); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_user_event_insert PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function inserts a user event into the event log. */ +/* If the event log is full, the oldest event is overwritten. */ +/* */ +/* INPUT */ +/* */ +/* sub_type Event subtype for kernel call */ +/* info_1 First information field */ +/* info_2 Second information field */ +/* info_3 Third information field */ +/* info_4 Fourth information field */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX services */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_el_user_event_insert(UINT sub_type, ULONG info_1, ULONG info_2, + ULONG info_3, ULONG info_4) +{ + +TX_INTERRUPT_SAVE_AREA + +UINT upper_tb; +UCHAR *entry_ptr; + + /* Disable interrupts. */ + TX_DISABLE + + /* Increment total event counter. */ + _tx_el_total_events++; + + /* Setup working entry pointer first. */ + entry_ptr = *_tx_el_current_event; + + /* Store the event type. */ + *((unsigned short *) entry_ptr) = (unsigned short) TX_EL_USER_EVENT; + + /* Store the event subtype. */ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = + (unsigned short) sub_type; + + /* Get time stamp. */ + do + { + + /* Pickup the upper tb. */ + upper_tb = (ULONG) read_tbu(); + + /* Store the upper time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = + (ULONG) upper_tb; + + /* Store the lower time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) = + (ULONG) read_tbl(); + } while (upper_tb != (ULONG) read_tbu()); + + /* Store the current thread. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) = + (ULONG) _tx_thread_current_ptr; + + /* Store the first info field. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_1_OFFSET)) = + (ULONG) info_1; + + /* Store the second info field. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_2_OFFSET)) = + (ULONG) info_2; + + /* Store the third info field. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_3_OFFSET)) = + (ULONG) info_3; + + /* Store the fourth info field. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_4_OFFSET)) = + (ULONG) info_4; + + /* Now move the current event log pointer. */ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE; + + /* Check for a wraparound condition. */ + if (entry_ptr >= _tx_el_event_area_end) + { + + /* Yes, we have wrapped around to the end of the event area. + Start back at the top! */ + entry_ptr = _tx_el_event_area_start; + } + + /* Write the entry pointer back into the header. */ + *_tx_el_current_event = entry_ptr; + + /* Restore interrupts. */ + TX_RESTORE +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_thread_running PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function inserts a thread change event into the event */ +/* log, which indicates that a context switch is taking place. */ +/* If the event log is full, the oldest event is overwritten. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread being */ +/* scheduled */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_schedule ThreadX scheduler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_el_thread_running(TX_THREAD *thread_ptr) +{ + +UINT upper_tb; +UCHAR *entry_ptr; + + TX_EL_NO_STATUS_EVENTS + + /* Increment total event counter. */ + _tx_el_total_events++; + + /* Setup working entry pointer first. */ + entry_ptr = *_tx_el_current_event; + + /* Store the event type. */ + *((unsigned short *) entry_ptr) = (unsigned short) TX_EL_THREAD_CHANGE; + + /* Store the event subtype. */ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = + (unsigned short) 0; + + /* Get time stamp. */ + do + { + + /* Pickup the upper tb. */ + upper_tb = (ULONG) read_tbu(); + + /* Store the upper time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = + (ULONG) upper_tb; + + /* Store the lower time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) = + (ULONG) read_tbl(); + } while (upper_tb != (ULONG) read_tbu()); + + /* Store the current thread. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) = + (ULONG) thread_ptr; + + /* Now move the current event log pointer. */ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE; + + /* Check for a wraparound condition. */ + if (entry_ptr >= _tx_el_event_area_end) + { + + /* Yes, we have wrapped around to the end of the event area. + Start back at the top! */ + entry_ptr = _tx_el_event_area_start; + } + + /* Write the entry pointer back into the header. */ + *_tx_el_current_event = entry_ptr; + + TX_EL_END_FILTER +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_thread_preempted PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function inserts a thread preempted event into the event */ +/* log, which indicates that an interrupt occurred that made a higher */ +/* priority thread ready for execution. In this case, the previously */ +/* executing thread has an event entered to indicate it is no longer */ +/* running. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread being */ +/* scheduled */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_context_restore ThreadX context restore */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_el_thread_preempted(TX_THREAD *thread_ptr) +{ + +UINT upper_tb; +UCHAR *entry_ptr; + + + TX_EL_NO_STATUS_EVENTS + + /* Increment total event counter. */ + _tx_el_total_events++; + + /* Setup working entry pointer first. */ + entry_ptr = *_tx_el_current_event; + + /* Store the event type. */ + *((unsigned short *) entry_ptr) = (unsigned short) TX_EL_THREAD_STATUS_CHANGE; + + /* Store the event subtype. */ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = + (unsigned short) TX_READY; + + /* Get time stamp. */ + do + { + + /* Pickup the upper tb. */ + upper_tb = (ULONG) read_tbu(); + + /* Store the upper time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = + (ULONG) upper_tb; + + /* Store the lower time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) = + (ULONG) read_tbl(); + } while (upper_tb != (ULONG) read_tbu()); + + /* Store the current thread. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) = + (ULONG) _tx_thread_current_ptr; + + /* Now move the current event log pointer. */ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE; + + /* Check for a wraparound condition. */ + if (entry_ptr >= _tx_el_event_area_end) + { + + /* Yes, we have wrapped around to the end of the event area. + Start back at the top! */ + entry_ptr = _tx_el_event_area_start; + } + + /* Write the entry pointer back into the header. */ + *_tx_el_current_event = entry_ptr; + + TX_EL_END_FILTER +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_interrupt PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function inserts an interrupt event into the log, which */ +/* indicates the start of interrupt processing for the specific */ +/* */ +/* INPUT */ +/* */ +/* interrupt_number Interrupt number supplied by */ +/* ISR */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISR processing */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_el_interrupt(UINT interrupt_number) +{ + +UINT upper_tb; +UCHAR *entry_ptr; + + + TX_EL_NO_INTERRUPT_EVENTS + + /* Increment total event counter. */ + _tx_el_total_events++; + + /* Setup working entry pointer first. */ + entry_ptr = *_tx_el_current_event; + + /* Store the event type. */ + *((unsigned short *) entry_ptr) = (unsigned short) TX_EL_INTERRUPT; + + /* Store the event subtype. */ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = + (unsigned short) TX_EL_INTERRUPT_SUB_TYPE; + + /* Get time stamp. */ + do + { + + /* Pickup the upper tb. */ + upper_tb = (ULONG) read_tbu(); + + /* Store the upper time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = + (ULONG) upper_tb; + + /* Store the lower time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) = + (ULONG) read_tbl(); + } while (upper_tb != (ULONG) read_tbu()); + + /* Store the current thread. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) = + (ULONG) _tx_thread_current_ptr; + + /* Store the first info word. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_1_OFFSET)) = + (ULONG) interrupt_number; + + /* Now move the current event log pointer. */ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE; + + /* Check for a wraparound condition. */ + if (entry_ptr >= _tx_el_event_area_end) + { + + /* Yes, we have wrapped around to the end of the event area. + Start back at the top! */ + entry_ptr = _tx_el_event_area_start; + } + + /* Write the entry pointer back into the header. */ + *_tx_el_current_event = entry_ptr; + + TX_EL_END_FILTER +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_interrupt_end PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function inserts an interrupt end event into the log, which */ +/* indicates the end of interrupt processing for the specific */ +/* */ +/* INPUT */ +/* */ +/* interrupt_number Interrupt number supplied by */ +/* ISR */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISR processing */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_el_interrupt_end(UINT interrupt_number) +{ + +UINT upper_tb; +UCHAR *entry_ptr; + + + TX_EL_NO_INTERRUPT_EVENTS + + /* Increment total event counter. */ + _tx_el_total_events++; + + /* Setup working entry pointer first. */ + entry_ptr = *_tx_el_current_event; + + /* Store the event type. */ + *((unsigned short *) entry_ptr) = (unsigned short) TX_EL_INTERRUPT; + + /* Store the event subtype. */ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = + (unsigned short) TX_EL_END_OF_INTERRUPT; + + /* Get time stamp. */ + do + { + + /* Pickup the upper tb. */ + upper_tb = (ULONG) read_tbu(); + + /* Store the upper time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = + (ULONG) upper_tb; + + /* Store the lower time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) = + (ULONG) read_tbl(); + } while (upper_tb != (ULONG) read_tbu()); + + /* Store the current thread. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) = + (ULONG) _tx_thread_current_ptr; + + /* Store the first info word. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_1_OFFSET)) = + (ULONG) interrupt_number; + + /* Now move the current event log pointer. */ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE; + + /* Check for a wraparound condition. */ + if (entry_ptr >= _tx_el_event_area_end) + { + + /* Yes, we have wrapped around to the end of the event area. + Start back at the top! */ + entry_ptr = _tx_el_event_area_start; + } + + /* Write the entry pointer back into the header. */ + *_tx_el_current_event = entry_ptr; + + TX_EL_END_FILTER +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_interrupt_control PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function remaps the tx_interrupt_control service call so that */ +/* it can be tracked in the event log. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt posture */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_interrupt_control Interrupt control service */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX services */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _tx_el_interrupt_control(UINT new_posture) +{ + +TX_INTERRUPT_SAVE_AREA +UINT old_posture; + + + TX_EL_NO_INTERRUPT_EVENTS + + TX_DISABLE + TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_INTERRUPT_CONTROL, _tx_thread_current_ptr, new_posture) + TX_RESTORE + + TX_EL_END_FILTER + + old_posture = _tx_thread_interrupt_control(new_posture); + return(old_posture); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_event_log_on PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function disables all event filters. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_el_event_log_on(void) +{ + + /* Disable all event filters. */ + _tx_el_event_filter = TX_EL_ENABLE_ALL_EVENTS; +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_event_log_off PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets all event filters, thereby turning event */ +/* logging off. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_el_event_log_off(void) +{ + + /* Set all event filters. */ + _tx_el_event_filter = TX_EL_FILTER_ALL_EVENTS; +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_event_log_set PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets the events filters specified by the user. */ +/* */ +/* INPUT */ +/* */ +/* filter Events to filter */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_el_event_filter_set(UINT filter) +{ + + /* Apply the user event filter. */ + _tx_el_event_filter = filter; +} + diff --git a/ports/cortex_m4/ghs/src/tx_ghs.c b/ports/cortex_m4/ghs/src/tx_ghs.c new file mode 100644 index 00000000..0be9d715 --- /dev/null +++ b/ports/cortex_m4/ghs/src/tx_ghs.c @@ -0,0 +1,485 @@ +/* + * ThreadX C/C++ Library Support + * + * Copyright 1983-2019 Green Hills Software LLC. + * + * This program is the property of Green Hills Software LLC., + * its contents are proprietary information and no part of it + * is to be disclosed to anyone except employees of Green Hills + * Software LLC., or as agreed in writing signed by the President + * of Green Hills Software LLC. + */ + +#include "tx_ghs.h" +#ifndef TX_DISABLE_ERROR_CHECKING +#define TX_DISABLE_ERROR_CHECKING +#endif +#include "tx_api.h" +#include +#include + +/* Allow these routines to access the following ThreadX global variables. */ +extern ULONG _tx_thread_created_count; +extern TX_THREAD *_tx_thread_created_ptr; +extern TX_THREAD *_tx_thread_current_ptr; + +#if defined(__ghs) && (__GHS_VERSION_NUMBER >= 500) +/* Thread-local storage routines for Green Hills releases 5.x and above. */ +/* + Thread-Local (Per-Thread) Library Data Retrieval + ================================================ + + __ghs_ThreadLocalStorage_specifier defines all library data items + that the Green Hills libraries allow to be allocated per-thread. + + An implementation can choose which of these data items to allocate + for each thread. For example, an implementation may choose to + allocate an errno value for each thread, but not the strtok_saved_pos + pointer. The application could then use strtok_r instead of strtok for + correct operation. + + To add per-thread library data, define one of the + TX_THREAD_EXTENSION_* macros in tx_port.h to include the data item + or items in each thread control block TX_THREAD. + + If C++ with exceptions is being used, the __eh_globals entry must be + allocated for each thread. This is typically done by default using + TX_THREAD_EXTENSION_1 in tx_port.h. + + If __ghs_GetThreadLocalStorageItem is customized to return a + per-thread errno value, you should also: + + * Customize the System Library for your project + * Define the preprocessor symbol USE_THREAD_LOCAL_ERRNO in + src/libsys/ind_errn.c + + If you customize the System Library, you should remove ind_thrd.c + from the libsys.gpj subproject. + + */ + +/* Provide global __eh_globals value to support C++ exception handling + outside a thread context. This name also forces this module to be + included in the linked program instead of the ind_thrd.o module from + the System Library libsys.a. + */ +static void *__eh_globals; + +#pragma ghs startnomisra +void *__ghs_GetThreadLocalStorageItem(int specifier) +{ + void *ptlsitem = (void *)0; + switch (specifier) { + case (int)__ghs_TLS_Errno: + /* Set ptslsitem to the address of the per-thread errno value. + The per-thread errno value should have the type int. + + If returning a per-thread errno value, follow the steps + above. + + This item is used by numerous library functions. + */ + break; + case (int)__ghs_TLS_SignalHandlers: + /* Set ptslsitem to the address of the per-thread SignalHandlers + array. The per-thread SignalHandlers array should have the + array type as in the following declaration: + SignalHandler SignalHandlers[_SIGMAX]; + The SignalHandler type and _SIGMAX constant are defined in + ind_thrd.h. + + This item is used by the library functions signal() and + raise(). + */ + break; + case (int)__ghs_TLS_asctime_buff: + /* Set ptslsitem to the address of the per-thread asctime_buff + array. The per-thread asctime_buff array should have the + array type as in the following declaration: + char asctime_buff[30]; + + This item is used by the library functions asctime() and + ctime(). The library provides asctime_r() and ctime_r(), + inherently thread-safe versions of these functions. + */ + break; + case (int)__ghs_TLS_tmpnam_space: + /* Set ptslsitem to the address of the per-thread tmpnam_space + array. The per-thread tmpnam_space array should have the + array type as in the following declaration: + char tmpnam_space[L_tmpnam]; + The constant is defined in + + This item is used by the library function tmpnam() when + passed NULL. The library provides tmpnam_r(), an + inherently thread-safe version of tmpnam(). + */ + break; + case (int)__ghs_TLS_strtok_saved_pos: + /* Set ptslsitem to the address of the per-thread + strtok_saved_pos pointer. The per-thread strtok_saved_pos + pointer should have the type "char *". + + This item is used by the library function strtok(). + The library provides strtok_r(), an inherently thread-safe + version of strtok(). + */ + break; + case (int)__ghs_TLS_gmtime_temp: + /* Set ptslsitem to the address of the per-thread gmtime_temp + value. The per-thread gmtime_temp value should have the + type "struct tm" defined in time.h, included by indos.h. + + This item is used by the library functions gmtime() and + localtime(). The library provides gmtime_r() and + localtime_r(), inherently thread-safe versions of these + functions. + */ + break; + case (int)__ghs_TLS___eh_globals: + /* Set ptslsitem to the address of the per-thread __eh_globals + value. The per-thread __eh_globals value should have the + type "void *". + + This item is used by C++ exception handling. + */ + if (_tx_thread_current_ptr) + ptlsitem = (void *)&(_tx_thread_current_ptr->tx_thread_eh_globals); + else + /* Use the global __eh_globals pointer. */ + ptlsitem = (void *)&__eh_globals; + break; + } + return ptlsitem; +} +#pragma ghs endnomisra +#else +/* Thread-local storage routines for Green Hills releases 4.x and 3.x . */ + +/* + * ThreadX C and C++ thread-safe library support routines. + * + * This implementation merely tries to guarantee thread safety within + * individual C library calls such as malloc() and free(), but it does + * not attempt to solve the problems associated with the following + * multithreaded issues: + * + * 1. Use of errno. This can be made thread-safe by adding errno + * to TX_THREAD_PORT_EXTENSION and using that within a modified + * version of libsys/ind_errno.c. + * + * 2. Thread safety ACROSS library calls. Certain C library calls either + * return pointers to statically-allocated data structures or maintain + * state across calls. These include strtok(), asctime(), gmtime(), + * tmpnam(NULL), signal(). To make such C library routines thread-safe + * would require adding a ThreadLocalStorage struct to the thread control + * block TX_THREAD. Since relatively few applications make use of these + * library routines, the implementation provided here uses a single, global + * ThreadLocalStorage data structure rather than greatly increasing the size + * of the thread control block TX_THREAD. + * + * The ThreadX global variable _tx_thread_current_ptr points to the + * current thread's control block TX_THREAD. If a ThreadLocalStorage struct + * called tx_tls is placed in TX_THREAD, the function GetThreadLocalStorage + * should be modified to return &(_tx_thread_current_ptr->tx_tls). + */ + +static ThreadLocalStorage GlobalTLS; + +ThreadLocalStorage *GetThreadLocalStorage() +{ + return &GlobalTLS; +} +#endif + +/* + * Use a global ThreadX mutex to implement thread safety within C and C++ + * library routines. + * + */ +TX_MUTEX __ghLockMutex; + +/* + * Acquire general lock. Blocks until the lock becomes available. + * Use tx_mutex_get to implement __ghsLock + */ +void __ghsLock(void) +{ + tx_mutex_get(&__ghLockMutex, TX_WAIT_FOREVER); +} + +/* + * Release general lock + * Use tx_mutex_put to implement __ghsUnlock + */ +void __ghsUnlock(void) +{ + tx_mutex_put(&__ghLockMutex); +} + +/* ThreadX Initialization function prototype. */ +void _tx_initialize_kernel_setup(void); + +void __gh_lock_init(void) +{ + /* Initialize the low-level portions of ThreadX. */ + _tx_initialize_kernel_setup(); + + /* Create the global thread lock mutex. */ + tx_mutex_create(&__ghLockMutex, "__ghLockMutex", TX_NO_INHERIT); +} + +/* + Saving State Across setjmp() Calls + ================================== + + These routines can be used to save and restore arbitrary state + across calls to setjmp() and longjmp(). +*/ +int __ghs_SaveSignalContext(jmp_buf jmpbuf) +{ + return 0; +} + +/* Restore arbitrary state across a longjmp() */ +void __ghs_RestoreSignalContext(jmp_buf jmpbuf) +{ +} + +#if defined(__GHS_VERSION_NUMBER) && (__GHS_VERSION_NUMBER < 560) +/* + C++ Exception Handling + ====================== + + These routines allow C++ exceptions to be used in multiple threads. + The default implementation uses __ghs_GetThreadLocalStorageItem + to return a thread-specific __eh_globals pointer. + +*/ + +/* Must be called after __cpp_exception_init() is called to allocate + * and initialize the per-thread exception handling structure */ +void *__get_eh_globals(void) +{ +#if defined(__ghs) && (__GHS_VERSION_NUMBER >= 500) + return *(void **)__ghs_GetThreadLocalStorageItem(__ghs_TLS___eh_globals); +#else + if (_tx_thread_current_ptr) + + /* Return thread-specific __eh_globals pointer. */ + return _tx_thread_current_ptr->tx_thread_eh_globals; + else + /* Return the global __eh_globals pointer. */ + return GlobalTLS.__eh_globals; +#endif +} +#endif + +#if defined(__ghs) && (__GHS_VERSION_NUMBER >= 500) +#pragma weak __cpp_exception_init +extern void __cpp_exception_init(void **); +#pragma weak __cpp_exception_cleanup +extern void __cpp_exception_cleanup(void **); + +/* __tx_cpp_exception_init retrieves the eh_globals field from + thread-local storage and calls __cpp_exception_init. + */ +void __tx_cpp_exception_init(TX_THREAD *thread_ptr) { + void **peh_globals; + if(__cpp_exception_init) { + if (thread_ptr) + peh_globals = &(thread_ptr->tx_thread_eh_globals); + else + /* Use the global __eh_globals pointer. */ + peh_globals = &__eh_globals; + __cpp_exception_init(peh_globals); + } +} + +/* __tx_cpp_exception_cleanup retrieves the eh_globals field from + thread-local storage and calls __cpp_exception_cleanup. + */ +void __tx_cpp_exception_cleanup(TX_THREAD *thread_ptr) { + void **peh_globals; + if(__cpp_exception_cleanup) { + if (thread_ptr) + peh_globals = &(thread_ptr->tx_thread_eh_globals); + else + /* Use the global __eh_globals pointer. */ + peh_globals = &__eh_globals; + __cpp_exception_cleanup(peh_globals); + } +} + +/* __ghs_cpp_exception_init is called from ind_crt1.o to initialize + exceptions for the global context. + */ +void __ghs_cpp_exception_init() { + __tx_cpp_exception_init((void *)0); +} + +/* __ghs_cpp_exception_cleanup is called from ind_exit.o to clean up + exceptions for the global context. + */ +void __ghs_cpp_exception_cleanup(TX_THREAD *thread_ptr) { + __tx_cpp_exception_cleanup((void *)0); +} +#endif + + +/* + File Locks + ====================== + + These routines can be customized to implement per-file locks to allow + thread-safe I/O. + +*/ + +/* Acquire lock for FILE *addr */ +void __ghs_flock_file(void *addr) +{ + tx_mutex_get((TX_MUTEX *)addr, TX_WAIT_FOREVER); +} + +/* Release lock for FILE *addr */ +void __ghs_funlock_file(void *addr) +{ + tx_mutex_put((TX_MUTEX *)addr); +} + +/* Non blocking acquire lock for FILE *addr. May return -1 if */ +/* not implemented. Returns 0 on success and nonzero otherwise. */ +int __ghs_ftrylock_file(void *addr) +{ + return -1; +} + +/* Calls to initialize local lock data structures before they */ +/* are used. */ +void __ghs_flock_create(void **addr) +{ + *addr = (void *)(&__ghLockMutex); +} +void __ghs_flock_destroy(void *addr) {} + + +/* + * ThreadX Peak Stack Checking support routines. + * + * All of these routines are called by MULTI's ThreadX-aware debugging + * package to determine the peak stack use for one thread or for all threads. + * + * These routines are included in this file in order to guarantee that they will + * be available while debugging with MULTI. These routines are not referenced by + * any other part of the ThreadX system. + * + * _txs_thread_stack_check: return the peak stack usage for a thread. + * + * _txs_thread_stack_check_2: store the peak stack usage for all threads + * in the tx_thread_stack_size field of each thread + * control block, TX_THREAD. This routine takes + * advantage of the redundancy within the TX_THREAD + * structure since tx_thread_stack_size can be computed + * from the tx_thread_stack_start and tx_thread_stack_end + * fields of TX_THREAD. + * + * _txs_thread_stack_check_2_fixup: clean up from the _txs_thread_stack_check_2 + * call by computing the stack size for each + * thread and storing the result in the + * tx_thread_stack_size field of each thread control + * block TX_THREAD. + * + * These three routines do not support architectures such as i960 or StarCore + * where the stack grows up instead of down. + * + */ +#ifndef TX_DISABLE_STACK_CHECKING + +ULONG _txs_thread_stack_check(TX_THREAD *thread_ptr) +{ + CHAR *cp; /* Pointer inside thread's stack. */ + + /* Search through the thread's stack to find the highest address modified. */ + for ( cp = (CHAR *)thread_ptr->tx_thread_stack_start; + cp <= (CHAR *)thread_ptr->tx_thread_stack_end; ++cp ) { + + /* Check if this byte in the stack contains something other than TX_STACK_FILL. */ + if (*cp != (char)TX_STACK_FILL) { + + /* Assume cp points to the locating marking the peak stack use. + Return the number of bytes from cp up to and including the + end of the stack. */ + return (((ULONG)thread_ptr->tx_thread_stack_end) - (ULONG)cp + 1); + } + } + return thread_ptr->tx_thread_stack_size; +} + + +int _txs_thread_stack_check_2(void) { + CHAR * cp; /* Pointer inside thread's stack. */ + TX_THREAD * tp; /* Pointer to each thread. */ + + /* If no threads are created, return immediately. */ + if (!_tx_thread_created_count) + return 0; + + /* Start iterating through the threads in the system. Assume that we always + have at least one thread (the system timer thread) in the system. */ + tp = _tx_thread_created_ptr; + + do { + + /* Search through the thread's stack to find the highest address modified. */ + for ( cp = (CHAR *)tp->tx_thread_stack_start; cp <= (CHAR *)tp->tx_thread_stack_end; + ++cp ) { + + /* Check if this byte in the stack contains something other than TX_STACK_FILL. */ + if (*cp != (char)TX_STACK_FILL) { + + /* Assume cp points to the locating marking the peak stack use. + Store the number of bytes from cp up to and including the + end of the stack in the tx_thread_stack_size field. */ + tp->tx_thread_stack_size = ((ULONG)tp->tx_thread_stack_end) - (ULONG)cp + 1; + break; + } + + } + + /* Continue with the next thread. */ + tp = tp->tx_thread_created_next; + + /* Loop until we point to the first thread again. */ + } while ( tp != _tx_thread_created_ptr ); + + return 0; +} + +int _txs_thread_stack_check_2_fixup(void) { + TX_THREAD * tp; /* Pointer to each thread. */ + + /* If no threads are created, return immediately. */ + if (!_tx_thread_created_count) + return 0; + + /* Start iterating through the threads in the system. Assume that we always + have at least one thread (the system timer thread) in the system. */ + tp = _tx_thread_created_ptr; + + do { + + /* Compute the tx_thread_stack_size field by using the tx_thread_stack_end and + tx_thread_stack_start fields. */ + tp->tx_thread_stack_size = (ULONG)tp->tx_thread_stack_end-(ULONG)tp->tx_thread_stack_start+1; + + /* Continue with the next thread. */ + tp = tp->tx_thread_created_next; + + /* Loop until we point to the first thread again. */ + } while ( tp != _tx_thread_created_ptr ); + + return 0; +} + +#endif /* TX_DISABLE_STACK_CHECKING */ diff --git a/ports/cortex_m4/ghs/src/tx_ghse.c b/ports/cortex_m4/ghs/src/tx_ghse.c new file mode 100644 index 00000000..6369df77 --- /dev/null +++ b/ports/cortex_m4/ghs/src/tx_ghse.c @@ -0,0 +1,49 @@ +/* + * ThreadX C++ Library Support + * + * Copyright 1983-2019 Green Hills Software LLC. + * + * This program is the property of Green Hills Software LLC., + * its contents are proprietary information and no part of it + * is to be disclosed to anyone except employees of Green Hills + * Software LLC., or as agreed in writing signed by the President + * of Green Hills Software LLC. + */ +#include "tx_ghs.h" +#ifndef TX_DISABLE_ERROR_CHECKING +#define TX_DISABLE_ERROR_CHECKING +#endif +#include "tx_api.h" + +/* + C++ Exception Handling + ====================== + + These routines allow C++ exceptions to be used in multiple threads. + The default implementation uses __ghs_GetThreadLocalStorageItem + to return a thread-specific __eh_globals pointer. + +*/ + +#if defined(__ghs) && (__GHS_VERSION_NUMBER >= 560) +#ifdef _WIN32 +/* Windows uses a different linker, so include a stub routine, never called, + to pull in __cpp_exception_init and __cpp_exception_cleanup */ +extern void __cpp_exception_init(void **); +extern void __cpp_exception_cleanup(void **); +void __tx_win32_pull_in_exceptions(void) { + __cpp_exception_init(0); + __cpp_exception_cleanup(0); +} +#else +#pragma ghs reference __cpp_exception_init +#pragma ghs reference __cpp_exception_cleanup +#endif + +/* Must be called after __cpp_exception_init() is called to allocate + * and initialize the per-thread exception handling structure */ +void *__get_eh_globals(void) +{ + return *(void **)__ghs_GetThreadLocalStorageItem(__ghs_TLS___eh_globals); +} +#endif diff --git a/ports/cortex_m4/ghs/src/tx_thread_context_restore.arm b/ports/cortex_m4/ghs/src/tx_thread_context_restore.arm new file mode 100644 index 00000000..2b3e2826 --- /dev/null +++ b/ports/cortex_m4/ghs/src/tx_thread_context_restore.arm @@ -0,0 +1,87 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + .text + .align 4 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-M4/GHS */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* [_tx_execution_isr_exit] Execution profiling ISR exit */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + .globl _tx_thread_context_restore +_tx_thread_context_restore: + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + PUSH {r0, lr} ; Save return address + BL _tx_execution_isr_exit ; Call the ISR exit function + POP {r0, lr} ; Save return address +#endif +; + POP {lr} + BX lr +; +;} + .type _tx_thread_context_restore,$function + .size _tx_thread_context_restore,.-_tx_thread_context_restore diff --git a/ports/cortex_m4/ghs/src/tx_thread_context_save.arm b/ports/cortex_m4/ghs/src/tx_thread_context_save.arm new file mode 100644 index 00000000..059208ee --- /dev/null +++ b/ports/cortex_m4/ghs/src/tx_thread_context_save.arm @@ -0,0 +1,85 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + .text + .align 4 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-M4/GHS */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + .globl _tx_thread_context_save +_tx_thread_context_save: +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is starting. */ +; + PUSH {r0, lr} ; Save return address + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {r0, lr} ; Recover return address +#endif +; +; /* Context is already saved - just return! */ +; + BX lr +;} + .type _tx_thread_context_save,$function + .size _tx_thread_context_save,.-_tx_thread_context_save diff --git a/ports/cortex_m4/ghs/src/tx_thread_interrupt_control.arm b/ports/cortex_m4/ghs/src/tx_thread_interrupt_control.arm new file mode 100644 index 00000000..8eecf381 --- /dev/null +++ b/ports/cortex_m4/ghs/src/tx_thread_interrupt_control.arm @@ -0,0 +1,75 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + .text + .align 4 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-M4/GHS */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + .globl _tx_thread_interrupt_control +_tx_thread_interrupt_control: + MRS r1, PRIMASK ; Pickup current interrupt lockout + MSR PRIMASK, r0 ; Apply the new interrupt lockout + MOV r0, r1 ; Transfer old to return register + BX lr ; Return to caller +; +;} + .type _tx_thread_interrupt_control,$function + .size _tx_thread_interrupt_control,.-_tx_thread_interrupt_control diff --git a/ports/cortex_m4/ghs/src/tx_thread_interrupt_disable.arm b/ports/cortex_m4/ghs/src/tx_thread_interrupt_disable.arm new file mode 100644 index 00000000..0a2d1f98 --- /dev/null +++ b/ports/cortex_m4/ghs/src/tx_thread_interrupt_disable.arm @@ -0,0 +1,85 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + .text + .align 4 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-M4/GHS */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts and returning */ +;/* the previous interrupt lockout posture. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_disable(UINT new_posture) +;{ + .globl _tx_thread_interrupt_disable +_tx_thread_interrupt_disable: +; +; /* Return current interrupt lockout posture. */ +; + MRS r0, PRIMASK + CPSID i + BX lr +; +;} + .type _tx_thread_interrupt_disable,$function + .size _tx_thread_interrupt_disable,.-_tx_thread_interrupt_disable diff --git a/ports/cortex_m4/ghs/src/tx_thread_interrupt_restore.arm b/ports/cortex_m4/ghs/src/tx_thread_interrupt_restore.arm new file mode 100644 index 00000000..45a7ef25 --- /dev/null +++ b/ports/cortex_m4/ghs/src/tx_thread_interrupt_restore.arm @@ -0,0 +1,76 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + .text + .align 4 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-M4/GHS */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for restoring the previous */ +;/* interrupt lockout posture. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* previous_posture Previous interrupt posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_interrupt_restore(UINT new_posture) +;{ + .globl _tx_thread_interrupt_restore +_tx_thread_interrupt_restore: +; +; /* Restore previous interrupt lockout posture. */ +; + MSR PRIMASK, r0 + BX lr +; +;} + .type _tx_thread_interrupt_restore,$function + .size _tx_thread_interrupt_restore,.-_tx_thread_interrupt_restore diff --git a/ports/cortex_m4/ghs/src/tx_thread_schedule.arm b/ports/cortex_m4/ghs/src/tx_thread_schedule.arm new file mode 100644 index 00000000..bac40b7d --- /dev/null +++ b/ports/cortex_m4/ghs/src/tx_thread_schedule.arm @@ -0,0 +1,282 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + .text + .align 4 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-M4/GHS */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + .globl _tx_thread_schedule +_tx_thread_schedule: +; +; /* This function should only ever be called on Cortex-M +; from the first schedule request. Subsequent scheduling occurs +; from the PendSV handling routines below. */ +; +; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ +; + MOV r0, #0 ; Build value for TX_FALSE + LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag + STR r0, [r2, #0] ; Clear preempt disable flag +; +; /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */ +; +#ifdef __VFP__ + MRS r0, CONTROL ; Pickup current CONTROL register + BIC r0, r0, #4 ; Clear the FPCA bit + MSR CONTROL, r0 ; Setup new CONTROL register +#endif +; +; /* Enable interrupts */ +; + CPSIE i +; +; /* Enter the scheduler for the first time. */ +; + MOV r0, #0x10000000 ; Load PENDSVSET bit + MOV r1, #0xE000E000 ; Load NVIC base + STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR + DSB ; Complete all memory accesses + ISB ; Flush pipeline +; +; /* Wait here for the PendSV to take place. */ +; +__tx_wait_here: + B __tx_wait_here ; Wait for the PendSV to happen + + .type _tx_thread_schedule,$function + .size _tx_thread_schedule,.-_tx_thread_schedule +;} +; +; /* Generic context PendSV handler. */ +; + .globl PendSV_Handler + .globl __tx_PendSVHandler +PendSV_Handler: +__tx_PendSVHandler: +; +; /* Get current thread value and new thread pointer. */ +; +__tx_ts_handler: + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + CPSID i ; Disable interrupts + PUSH {r0, lr} ; Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit ; Call the thread exit function + POP {r0, lr} ; Recover LR + CPSIE i ; Enable interrupts +#endif + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r2, =_tx_thread_execute_ptr ; Build execute thread pointer address + MOV r3, #0 ; Build NULL value + LDR r1, [r0] ; Pickup current thread pointer +; +; /* Determine if there is a current thread to finish preserving. */ +; + CBZ r1, __tx_ts_new ; If NULL, skip preservation +; +; /* Recover PSP and preserve current thread context. */ +; + STR r3, [r0] ; Set _tx_thread_current_ptr to NULL + MRS r12, PSP ; Pickup PSP pointer (thread's stack pointer) + STMDB r12!, {r4-r11} ; Save its remaining registers +#ifdef __VFP__ + TST LR, #0x10 ; Determine if the VFP extended frame is present + BNE _skip_vfp_save + VSTMDB r12!,{s16-s31} ; Yes, save additional VFP registers +_skip_vfp_save: +#endif + LDR r4, =_tx_timer_time_slice ; Build address of time-slice variable + STR.W LR, [r12, #-0x4]! ; Save LR on the stack +; +; /* Determine if time-slice is active. If it isn't, skip time handling processing. */ +; + LDR r5, [r4] ; Pickup current time-slice + STR r12, [r1, #8] ; Save the thread stack pointer + CBZ r5, __tx_ts_new ; If not active, skip processing +; +; /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ +; + STR r5, [r1, #24] ; Save current time-slice +; +; /* Clear the global time-slice. */ +; + STR r3, [r4] ; Clear time-slice +; +; +; /* Executing thread is now completely preserved!!! */ +; +__tx_ts_new: +; +; /* Now we are looking for a new thread to execute! */ +; + CPSID i ; Disable interrupts + LDR r1, [r2] ; Is there another thread ready to execute? + CBZ r1, __tx_ts_wait ; No, skip to the wait processing +; +; /* Yes, another thread is ready for else, make the current thread the new thread. */ +; + STR r1, [r0] ; Setup the current thread pointer to the new thread + CPSIE i ; Enable interrupts +; +; /* Increment the thread run count. */ +; +__tx_ts_restore: + LDR r7, [r1, #4] ; Pickup the current thread run count + LDR r4, =_tx_timer_time_slice ; Build address of time-slice variable + LDR r5, [r1, #24] ; Pickup thread's current time-slice + ADD r7, r7, #1 ; Increment the thread run count + STR r7, [r1, #4] ; Store the new run count +; +; /* Setup global time-slice with thread's current time-slice. */ +; + STR r5, [r4] ; Setup global time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + PUSH {r0, r1} ; Save r0/r1 + BL _tx_execution_thread_enter ; Call the thread execution enter function + POP {r0, r1} ; Recover r3 +#endif +; +; /* Restore the thread context and PSP. */ +; + LDR r12, [r1, #8] ; Pickup thread's stack pointer + LDR.W LR, [r12], #4 ; Pickup LR +#ifdef __VFP__ + TST LR, #0x10 ; Determine if the VFP extended frame is present + BNE _skip_vfp_restore ; If not, skip VFP restore + VLDMIA r12!, {s16-s31} ; Yes, restore additional VFP registers +_skip_vfp_restore: +#endif + LDMIA r12!, {r4-r11} ; Recover thread's registers + MSR PSP, r12 ; Setup the thread's stack pointer +; +; /* Return to thread. */ +; + BX lr ; Return to thread! +; +; /* The following is the idle wait processing... in this case, no threads are ready for execution and the +; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +; are disabled to allow use of WFI for waiting for a thread to arrive. */ +; +__tx_ts_wait: + CPSID i ; Disable interrupts + LDR r1, [r2] ; Pickup the next thread to execute pointer + STR r1, [r0] ; Store it in the current pointer + CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready! +#ifdef TX_ENABLE_WFI + DSB ; Ensure no outstanding memory transactions + WFI ; Wait for interrupt + ISB ; Ensure pipeline is flushed +#endif + CPSIE i ; Enable interrupts + B __tx_ts_wait ; Loop to continue waiting +; +; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +; already in the handler! */ +; +__tx_ts_ready: + MOV r7, #0x08000000 ; Build clear PendSV value + MOV r8, #0xE000E000 ; Build base NVIC address + STR r7, [r8, #0xD04] ; Clear any PendSV +; +; /* Re-enable interrupts and restore new thread. */ +; + CPSIE i ; Enable interrupts + B __tx_ts_restore ; Restore the thread +;} +; + .type __tx_PendSVHandler,$function + .size __tx_PendSVHandler,.-__tx_PendSVHandler + +#ifdef __VFP__ + + .globl tx_thread_fpu_enable +tx_thread_fpu_enable: +; +; /* Automatic VPF logic is supported, this function is present only for +; backward compatibility purposes and therefore simply returns. */ +; + BX LR ; Return to caller + + .type tx_thread_fpu_enable,$function + .size tx_thread_fpu_enable,.-tx_thread_fpu_enable + + .global tx_thread_fpu_disable +tx_thread_fpu_disable: +; +; /* Automatic VPF logic is supported, this function is present only for +; backward compatibility purposes and therefore simply returns. */ +; + BX LR ; Return to caller + + .type tx_thread_fpu_disable,$function + .size tx_thread_fpu_disable,.-tx_thread_fpu_disable + +#endif diff --git a/ports/cortex_m4/ghs/src/tx_thread_stack_build.arm b/ports/cortex_m4/ghs/src/tx_thread_stack_build.arm new file mode 100644 index 00000000..db78217a --- /dev/null +++ b/ports/cortex_m4/ghs/src/tx_thread_stack_build.arm @@ -0,0 +1,135 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + .text + .align 4 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-M4/GHS */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + .globl _tx_thread_stack_build +_tx_thread_stack_build: +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-M should look like the following after it is built: +; +; Stack Top: +; LR Interrupted LR (LR at time of PENDSV) +; r4 Initial value for r4 +; r5 Initial value for r5 +; r6 Initial value for r6 +; r7 Initial value for r7 +; r8 Initial value for r8 +; r9 Initial value for r9 +; r10 Initial value for r10 +; r11 Initial value for r11 +; r0 Initial value for r0 (Hardware stack starts here!!) +; r1 Initial value for r1 +; r2 Initial value for r2 +; r3 Initial value for r3 +; r12 Initial value for r12 +; lr Initial value for lr +; pc Initial value for pc +; xPSR Initial value for xPSR +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #0x7 ; Align frame for 8-byte alignment + SUB r2, r2, #68 ; Subtract frame size + LDR r3, =0xFFFFFFFD ; Build initial LR value + STR r3, [r2, #0] ; Save on the stack +; +; /* Actually build the stack frame. */ +; + MOV r3, #0 ; Build initial register value + STR r3, [r2, #4] ; Store initial r4 + STR r3, [r2, #8] ; Store initial r5 + STR r3, [r2, #12] ; Store initial r6 + STR r3, [r2, #16] ; Store initial r7 + STR r3, [r2, #20] ; Store initial r8 + STR r3, [r2, #24] ; Store initial r9 + STR r3, [r2, #28] ; Store initial r10 + STR r3, [r2, #32] ; Store initial r11 +; +; /* Hardware stack follows. */ +; + STR r3, [r2, #36] ; Store initial r0 + STR r3, [r2, #40] ; Store initial r1 + STR r3, [r2, #44] ; Store initial r2 + STR r3, [r2, #48] ; Store initial r3 + STR r3, [r2, #52] ; Store initial r12 + MOV r3, #0xFFFFFFFF ; Poison EXC_RETURN value + STR r3, [r2, #56] ; Store initial lr + STR r1, [r2, #60] ; Store initial pc + MOV r3, #0x01000000 ; Only T-bit need be set + STR r3, [r2, #64] ; Store initial xPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block + BX lr ; Return to caller +;} + .type _tx_thread_stack_build,$function + .size _tx_thread_stack_build,.-_tx_thread_stack_build diff --git a/ports/cortex_m4/ghs/src/tx_thread_system_return.arm b/ports/cortex_m4/ghs/src/tx_thread_system_return.arm new file mode 100644 index 00000000..d3be1746 --- /dev/null +++ b/ports/cortex_m4/ghs/src/tx_thread_system_return.arm @@ -0,0 +1,87 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + .text + .align 4 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-M4/GHS */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + .globl _tx_thread_system_return +_tx_thread_system_return: +; +; /* Return to real scheduler via PendSV. Note that this routine is often +; replaced with in-line assembly in tx_port.h to improved performance. */ +; + MOV r0, #0x10000000 ; Load PENDSVSET bit + MOV r1, #0xE000E000 ; Load NVIC base + STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR + MRS r0, IPSR ; Pickup IPSR + CMP r0, #0 ; Is it a thread returning? + BNE _isr_context ; If ISR, skip interrupt enable + MRS r1, PRIMASK ; Thread context returning, pickup PRIMASK + CPSIE i ; Enable interrupts + MSR PRIMASK, r1 ; Restore original interrupt posture +_isr_context: + BX lr ; Return to caller +;} + .type _tx_thread_system_return,$function + .size _tx_thread_system_return,.-_tx_thread_system_return diff --git a/ports/cortex_m4/ghs/src/tx_timer_interrupt.arm b/ports/cortex_m4/ghs/src/tx_timer_interrupt.arm new file mode 100644 index 00000000..ed5bf5aa --- /dev/null +++ b/ports/cortex_m4/ghs/src/tx_timer_interrupt.arm @@ -0,0 +1,243 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + .text + .align 4 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-M4/GHS */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* expiration functions are called. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + .globl _tx_timer_interrupt +_tx_timer_interrupt: +; +; /* Upon entry to this routine, it is assumed that the compiler scratch registers are available +; for use. */ +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + LDR r1, =_tx_timer_system_clock ; Pickup address of system clock + LDR r0, [r1, #0] ; Pickup system clock + ADD r0, r0, #1 ; Increment system clock + STR r0, [r1, #0] ; Store new system clock +; +; /* Test for time-slice expiration. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r2, [r3, #0] ; Pickup time-slice + CBZ r2, __tx_timer_no_time_slice ; Is it non-active? + ; Yes, skip time-slice processing +; +; /* Decrement the time_slice. */ +; _tx_timer_time_slice--; +; + SUB r2, r2, #1 ; Decrement the time-slice + STR r2, [r3, #0] ; Store new time-slice value +; +; /* Check for expiration. */ +; if (__tx_timer_time_slice == 0) +; + CBNZ r2, __tx_timer_no_time_slice ; Has it expired? +; +; /* Set the time-slice expired flag. */ +; _tx_timer_expired_time_slice = TX_TRUE; +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup address of expired flag + MOV r0, #1 ; Build expired value + STR r0, [r3, #0] ; Set time-slice expiration flag +; +; } +; +__tx_timer_no_time_slice: +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + LDR r1, =_tx_timer_current_ptr ; Pickup current timer pointer addr + LDR r0, [r1, #0] ; Pickup current timer + LDR r2, [r0, #0] ; Pickup timer list entry + CBZ r2, __tx_timer_no_timer ; Is there anything in the list? + ; No, just increment the timer +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + LDR r3, =_tx_timer_expired ; Pickup expiration flag address + MOV r2, #1 ; Build expired value + STR r2, [r3, #0] ; Set expired flag + B __tx_timer_done ; Finished timer processing +; +; } +; else +; { +__tx_timer_no_timer: +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ADD r0, r0, #4 ; Move to next timer +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + LDR r3, =_tx_timer_list_end ; Pickup addr of timer list end + LDR r2, [r3, #0] ; Pickup list end + CMP r0, r2 ; Are we at list end? + BNE __tx_timer_skip_wrap ; No, skip wrap-around logic +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + LDR r3, =_tx_timer_list_start ; Pickup addr of timer list start + LDR r0, [r3, #0] ; Set current pointer to list start +; +__tx_timer_skip_wrap: +; + STR r0, [r1, #0] ; Store new current timer pointer +; } +; +__tx_timer_done: +; +; +; /* See if anything has expired. */ +; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of expired flag + LDR r2, [r3, #0] ; Pickup time-slice expired flag + CBNZ r2, __tx_something_expired ; Did a time-slice expire? + ; If non-zero, time-slice expired + LDR r1, =_tx_timer_expired ; Pickup addr of other expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CBZ r0, __tx_timer_nothing_expired ; Did a timer expire? + ; No, nothing expired +; +__tx_something_expired: +; +; + STMDB sp!, {r0, lr} ; Save the lr register on the stack + ; and save r0 just to keep 8-byte alignment +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + LDR r1, =_tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CBZ r0, __tx_timer_dont_activate ; Check for timer expiration + ; If not set, skip timer activation +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + BL _tx_timer_expiration_process ; Call the timer expiration handling routine +; +; } +__tx_timer_dont_activate: +; +; /* Did time slice expire? */ +; if (_tx_timer_expired_time_slice) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r2, [r3, #0] ; Pickup the actual flag + CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set + ; No, skip time-slice processing +; +; /* Time slice interrupted thread. */ +; _tx_thread_time_slice(); + + BL _tx_thread_time_slice ; Call time-slice processing + LDR r0, =_tx_thread_preempt_disable ; Build address of preempt disable flag + LDR r1, [r0] ; Is the preempt disable flag set? + CBNZ r1, __tx_timer_skip_time_slice ; Yes, skip the PendSV logic + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup the current thread pointer + LDR r2, =_tx_thread_execute_ptr ; Build execute thread pointer address + LDR r3, [r2] ; Pickup the execute thread pointer + LDR r0, =0xE000ED04 ; Build address of control register + LDR r2, =0x10000000 ; Build value for PendSV bit + CMP r1, r3 ; Are they the same? + BEQ __tx_timer_skip_time_slice ; If the same, there was no time-slice performed + STR r2, [r0] ; Not the same, issue the PendSV for preemption +__tx_timer_skip_time_slice: +; +; } +; +__tx_timer_not_ts_expiration: +; + LDMIA sp!, {r0, lr} ; Recover lr register (r0 is just there for + ; the 8-byte stack alignment +; +; } +; +__tx_timer_nothing_expired: + + DSB ; Complete all memory access + BX lr ; Return to caller +; +;} + .type _tx_timer_interrupt,$function + .size _tx_timer_interrupt,.-_tx_timer_interrupt diff --git a/ports/cortex_m4/ghs/src/txr_ghs.c b/ports/cortex_m4/ghs/src/txr_ghs.c new file mode 100644 index 00000000..19572e2b --- /dev/null +++ b/ports/cortex_m4/ghs/src/txr_ghs.c @@ -0,0 +1,84 @@ +/* + * ThreadX API Runtime Error Support + * + * Copyright 1983-2019 Green Hills Software LLC. + * + * This program is the property of Green Hills Software LLC., + * its contents are proprietary information and no part of it + * is to be disclosed to anyone except employees of Green Hills + * Software LLC., or as agreed in writing signed by the President + * of Green Hills Software LLC. + */ + +/* #include "tx_ghs.h" */ +#ifndef TX_DISABLE_ERROR_CHECKING +#define TX_DISABLE_ERROR_CHECKING +#endif +#include "tx_api.h" + +/* Customized ThreadX API runtime error support routine. */ + +void _rnerr(int num, int linenum, const char*str, void*ptr, ...); + +/* __ghs_rnerr() + This is the custom runtime error checking routine. + This implementation uses the existing __rnerr() routine. + Another implementation could use the .syscall mechanism, + provided MULTI was modified to understand that. + */ +void __ghs_rnerr(char *errMsg, int stackLevels, int stackTraceDisplay, void *hexVal) { + TX_INTERRUPT_SAVE_AREA + int num; + /* + Initialize the stack levels value. + + Add 3 to account for the calls to _rnerr, __rnerr, and + __ghs_rnerr. + + If the implementation changes, calls to __ghs_rnerr + will not need to be changed. + + Zero is not permitted, so substitute 3 in that case. + */ + num = (stackLevels+3) & 0xf; + if (!num) { + num = 3; + } + /* + Shift the stack levels value to bits 12..15 and + insert the stack trace display value in bit 11. + Bits 0..10 are unused. + */ + num = (num << 12) | (stackTraceDisplay ? 0x800 : 0); + + /* This will mask all interrupts in the RTEC code, which is probably + unacceptable for many targets. */ + TX_DISABLE + _rnerr(num, -1, (const char *)hexVal, (void *)errMsg); + TX_RESTORE +} + + +/* ThreadX thread stack checking runtime support routine. */ + +extern char __ghsbegin_stack[]; +extern TX_THREAD *_tx_thread_current_ptr; + +void __stkchk(void) { + int i; + if(_tx_thread_current_ptr) + { + if((unsigned)(&i) <= + (unsigned)(_tx_thread_current_ptr -> tx_thread_stack_start)) + { + _rnerr(21, -1, 0, 0); + } + } + else + { + if((unsigned)(&i) <= (unsigned)__ghsbegin_stack) + { + _rnerr(21, -1, 0, 0); + } + } +} diff --git a/ports/cortex_m4/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_m4/gnu/example_build/tx_initialize_low_level.S index 16d055d3..3569f0c7 100644 --- a/ports/cortex_m4/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_m4/gnu/example_build/tx_initialize_low_level.S @@ -49,7 +49,7 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* FUNCTION RELEASE */ @/* */ @/* _tx_initialize_low_level Cortex-M4/GNU */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -83,12 +83,10 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 06-30-2020 William E. Lamie Modified Comment(s), fixed */ +@/* 09-30-2020 William E. Lamie Modified Comment(s), fixed */ @/* GNU assembly comment, */ -@/* resulting in version 6.0.1 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* cleaned up whitespace, */ +@/* resulting in version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_m4/gnu/inc/tx_port.h b/ports/cortex_m4/gnu/inc/tx_port.h index bca31b3d..604e27ba 100644 --- a/ports/cortex_m4/gnu/inc/tx_port.h +++ b/ports/cortex_m4/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M4/GNU */ -/* 6.0 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ @@ -485,7 +487,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/GNU Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/GNU Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_m4/gnu/readme_threadx.txt b/ports/cortex_m4/gnu/readme_threadx.txt index ebc6f2af..3d6f02a0 100644 --- a/ports/cortex_m4/gnu/readme_threadx.txt +++ b/ports/cortex_m4/gnu/readme_threadx.txt @@ -208,8 +208,8 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -08-14-2020 ThreadX update of Cortex-M4/GNU port. The following files were - changed/added for port specific version 6.0.2: +09-30-2020 ThreadX update of Cortex-M4/GNU port. The following files were + changed/added for port specific version 6.1: *.S Modified comments and whitespace. diff --git a/ports/cortex_m4/gnu/src/tx_thread_context_restore.S b/ports/cortex_m4/gnu/src/tx_thread_context_restore.S index 29a1c0ce..6dfd19df 100644 --- a/ports/cortex_m4/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_m4/gnu/src/tx_thread_context_restore.S @@ -39,7 +39,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_restore Cortex-M4/GNU */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -74,9 +74,8 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Modified comment(s), */ +@/* resulting in version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m4/gnu/src/tx_thread_context_save.S b/ports/cortex_m4/gnu/src/tx_thread_context_save.S index 8cef0b96..e086d467 100644 --- a/ports/cortex_m4/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_m4/gnu/src/tx_thread_context_save.S @@ -34,7 +34,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_save Cortex-M4/GNU */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -68,9 +68,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 Scott Larson Modified comment(s), and */ +@/* cleaned up whitespace, */ +@/* resulting in version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m4/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_m4/gnu/src/tx_thread_interrupt_control.S index 9c990ca0..4e6ec582 100644 --- a/ports/cortex_m4/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m4/gnu/src/tx_thread_interrupt_control.S @@ -29,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_control Cortex-M4/GNU */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -60,9 +60,8 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Modified comment(s), */ +@/* resulting in version 6.1 */ @/* */ @/**************************************************************************/ @/* UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_m4/gnu/src/tx_thread_schedule.S b/ports/cortex_m4/gnu/src/tx_thread_schedule.S index 8b0ecb16..f6cb7af7 100644 --- a/ports/cortex_m4/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_m4/gnu/src/tx_thread_schedule.S @@ -37,7 +37,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule Cortex-M4/GNU */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -71,9 +71,8 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Modified comment(s), */ +@/* resulting in version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_m4/gnu/src/tx_thread_stack_build.S b/ports/cortex_m4/gnu/src/tx_thread_stack_build.S index 5c0e0377..c0e8bca9 100644 --- a/ports/cortex_m4/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_m4/gnu/src/tx_thread_stack_build.S @@ -29,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_stack_build Cortex-M4/GNU */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -62,14 +62,12 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 06-30-2020 William E. Lamie Modified Comment(s), setting */ -@/* R10 to top of stack is not */ -@/* needed. Removed references */ -@/* to stack frame, resulting */ -@/* in version 6.0.1 */ -@/* 08-14-2020 William E. Lamie Modified Comment(s), clean up */ +@/* 09-30-2020 William E. Lamie Modified Comment(s), setting */ +@/* R10 to top of stack is not */ +@/* needed. Removed references */ +@/* to stack frame, clean up */ @/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* in version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_m4/gnu/src/tx_thread_system_return.S b/ports/cortex_m4/gnu/src/tx_thread_system_return.S index 65907ae7..1a799fd4 100644 --- a/ports/cortex_m4/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_m4/gnu/src/tx_thread_system_return.S @@ -29,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_system_return Cortex-M4/GNU */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -62,9 +62,8 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Modified comment(s), */ +@/* resulting in version 6.1 */ @/* */ @/**************************************************************************/ @/* VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_m4/gnu/src/tx_timer_interrupt.S b/ports/cortex_m4/gnu/src/tx_timer_interrupt.S index bbb5c08b..35923a33 100644 --- a/ports/cortex_m4/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_m4/gnu/src/tx_timer_interrupt.S @@ -40,7 +40,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_timer_interrupt Cortex-M4/GNU */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -75,9 +75,8 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Modified comment(s), */ +@/* resulting in version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_m4/iar/example_build/tx_initialize_low_level.s b/ports/cortex_m4/iar/example_build/tx_initialize_low_level.s index 50eb54dc..4f107ea6 100644 --- a/ports/cortex_m4/iar/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m4/iar/example_build/tx_initialize_low_level.s @@ -45,7 +45,7 @@ __tx_free_memory_start ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level Cortex-M4/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -78,10 +78,7 @@ __tx_free_memory_start ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_m4/iar/inc/tx_port.h b/ports/cortex_m4/iar/inc/tx_port.h index 2aa60ea8..81656f62 100644 --- a/ports/cortex_m4/iar/inc/tx_port.h +++ b/ports/cortex_m4/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M4/IAR */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -117,7 +117,7 @@ typedef unsigned short USHORT; #endif -/* Define various constants for the ThreadX Cortex-M3 port. */ +/* Define various constants for the ThreadX ARM Cortex-M port. */ #define TX_INT_DISABLE 1 /* Disable interrupts */ #define TX_INT_ENABLE 0 /* Enable interrupts */ @@ -347,7 +347,7 @@ void _tx_misra_vfp_touch(void); #else #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) -#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) #endif @@ -477,7 +477,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/IAR Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/IAR Version 6.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m4/iar/readme_threadx.txt b/ports/cortex_m4/iar/readme_threadx.txt index 22a5dc7f..3dfa5c42 100644 --- a/ports/cortex_m4/iar/readme_threadx.txt +++ b/ports/cortex_m4/iar/readme_threadx.txt @@ -214,12 +214,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -08-14-2020 ThreadX update of Cortex-M4/IAR port. The following files were - changed/added for port specific version 6.0.2: - - *.s Modified comments and whitespace. - -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M4 using IAR's ARM tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-M4 using IAR's ARM tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_m4/iar/src/tx_misra.s b/ports/cortex_m4/iar/src/tx_misra.s index 60ab3549..2add69b3 100644 --- a/ports/cortex_m4/iar/src/tx_misra.s +++ b/ports/cortex_m4/iar/src/tx_misra.s @@ -107,7 +107,7 @@ SECTION `.data`:DATA:REORDER:NOROOT(2) DATA -// 51 CHAR _tx_version_id[100] = "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX 6.0 MISRA C Compliant *"; +// 51 CHAR _tx_version_id[100] = "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX 6.1 MISRA C Compliant *"; _tx_version_id: DC8 43H, 6FH, 70H, 79H, 72H, 69H, 67H, 68H DC8 74H, 20H, 28H, 63H, 29H, 20H, 31H, 39H diff --git a/ports/cortex_m4/iar/src/tx_thread_context_restore.s b/ports/cortex_m4/iar/src/tx_thread_context_restore.s index a3d4d7a3..850fefa9 100644 --- a/ports/cortex_m4/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_m4/iar/src/tx_thread_context_restore.s @@ -31,7 +31,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore Cortex-M4/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -65,10 +65,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m4/iar/src/tx_thread_context_save.s b/ports/cortex_m4/iar/src/tx_thread_context_save.s index 5ce75e63..46cc01d0 100644 --- a/ports/cortex_m4/iar/src/tx_thread_context_save.s +++ b/ports/cortex_m4/iar/src/tx_thread_context_save.s @@ -31,7 +31,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save Cortex-M4/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -64,10 +64,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m4/iar/src/tx_thread_interrupt_control.s b/ports/cortex_m4/iar/src/tx_thread_interrupt_control.s index c036b06f..c903f17b 100644 --- a/ports/cortex_m4/iar/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m4/iar/src/tx_thread_interrupt_control.s @@ -28,7 +28,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control Cortex-M4/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -58,23 +58,17 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) ;{ PUBLIC _tx_thread_interrupt_control _tx_thread_interrupt_control: -; -; /* Pickup current interrupt lockout posture. */ -; - MRS r1, PRIMASK - MSR PRIMASK, r0 - MOV r0, r1 - BX lr + MRS r1, PRIMASK ; Pickup current interrupt lockout + MSR PRIMASK, r0 ; Apply the new interrupt lockout + MOV r0, r1 ; Transfer old to return register + BX lr ; Return to caller ; ;} END diff --git a/ports/cortex_m4/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_m4/iar/src/tx_thread_interrupt_disable.s index 3a6557bc..5577555c 100644 --- a/ports/cortex_m4/iar/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m4/iar/src/tx_thread_interrupt_disable.s @@ -28,7 +28,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-M4/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -58,10 +58,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(UINT new_posture) diff --git a/ports/cortex_m4/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_m4/iar/src/tx_thread_interrupt_restore.s index d57b60d9..10baa764 100644 --- a/ports/cortex_m4/iar/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m4/iar/src/tx_thread_interrupt_restore.s @@ -28,7 +28,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-M4/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -58,10 +58,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_interrupt_restore(UINT new_posture) diff --git a/ports/cortex_m4/iar/src/tx_thread_schedule.s b/ports/cortex_m4/iar/src/tx_thread_schedule.s index 62785071..d4356990 100644 --- a/ports/cortex_m4/iar/src/tx_thread_schedule.s +++ b/ports/cortex_m4/iar/src/tx_thread_schedule.s @@ -37,7 +37,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M4/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -70,10 +70,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_m4/iar/src/tx_thread_stack_build.s b/ports/cortex_m4/iar/src/tx_thread_stack_build.s index 5f28b814..493ee69d 100644 --- a/ports/cortex_m4/iar/src/tx_thread_stack_build.s +++ b/ports/cortex_m4/iar/src/tx_thread_stack_build.s @@ -28,7 +28,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build Cortex-M4/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -60,10 +60,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -114,7 +111,7 @@ _tx_thread_stack_build: STR r3, [r2, #28] ; Store initial r10 STR r3, [r2, #32] ; Store initial r11 ; -; /* Hardware stack follows. / +; /* Hardware stack follows. */ ; STR r3, [r2, #36] ; Store initial r0 STR r3, [r2, #40] ; Store initial r1 diff --git a/ports/cortex_m4/iar/src/tx_thread_system_return.s b/ports/cortex_m4/iar/src/tx_thread_system_return.s index 72b588dd..4ea6aa72 100644 --- a/ports/cortex_m4/iar/src/tx_thread_system_return.s +++ b/ports/cortex_m4/iar/src/tx_thread_system_return.s @@ -28,7 +28,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return Cortex-M4/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -60,10 +60,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_m4/iar/src/tx_timer_interrupt.s b/ports/cortex_m4/iar/src/tx_timer_interrupt.s index 5921443e..dabf7e1c 100644 --- a/ports/cortex_m4/iar/src/tx_timer_interrupt.s +++ b/ports/cortex_m4/iar/src/tx_timer_interrupt.s @@ -42,7 +42,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt Cortex-M4/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -75,10 +75,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_m4/keil/example_build/tx_initialize_low_level.s b/ports/cortex_m4/keil/example_build/tx_initialize_low_level.s index 64b690c4..a16879b9 100644 --- a/ports/cortex_m4/keil/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m4/keil/example_build/tx_initialize_low_level.s @@ -112,8 +112,8 @@ Reset_Handler ;/* */ ;/* FUNCTION RELEASE */ ;/* */ -;/* _tx_initialize_low_level Cortex-M4/RVDS */ -;/* 6.0.2 */ +;/* _tx_initialize_low_level Cortex-M4/AC5 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -146,10 +146,7 @@ Reset_Handler ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_m4/keil/inc/tx_port.h b/ports/cortex_m4/keil/inc/tx_port.h index 7474585b..85489c1a 100644 --- a/ports/cortex_m4/keil/inc/tx_port.h +++ b/ports/cortex_m4/keil/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M4/Keil */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -454,7 +454,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/Keil Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/Keil Version 6.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m4/keil/readme_threadx.txt b/ports/cortex_m4/keil/readme_threadx.txt index a265efd9..0557e507 100644 --- a/ports/cortex_m4/keil/readme_threadx.txt +++ b/ports/cortex_m4/keil/readme_threadx.txt @@ -198,12 +198,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -08-14-2020 ThreadX update of Cortex-M4/Keil port. The following files were - changed/added for port specific version 6.0.2: - - *.s Modified comments and whitespace. - -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M4 using Keil tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-M4 using Keil tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_m4/keil/src/tx_thread_context_restore.s b/ports/cortex_m4/keil/src/tx_thread_context_restore.s index 603a73e3..0ed36142 100644 --- a/ports/cortex_m4/keil/src/tx_thread_context_restore.s +++ b/ports/cortex_m4/keil/src/tx_thread_context_restore.s @@ -32,8 +32,8 @@ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ -;/* _tx_thread_context_restore Cortex-M4/AC5 */ -;/* 6.0.2 */ +;/* _tx_thread_context_restore Cortex-M4/AC5 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -67,10 +67,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m4/keil/src/tx_thread_context_save.s b/ports/cortex_m4/keil/src/tx_thread_context_save.s index fbadbcb3..a6827883 100644 --- a/ports/cortex_m4/keil/src/tx_thread_context_save.s +++ b/ports/cortex_m4/keil/src/tx_thread_context_save.s @@ -32,8 +32,8 @@ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ -;/* _tx_thread_context_save Cortex-M4/AC5 */ -;/* 6.0.2 */ +;/* _tx_thread_context_save Cortex-M4/AC5 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -66,10 +66,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m4/keil/src/tx_thread_interrupt_control.s b/ports/cortex_m4/keil/src/tx_thread_interrupt_control.s index 910322d9..ef983f17 100644 --- a/ports/cortex_m4/keil/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m4/keil/src/tx_thread_interrupt_control.s @@ -26,8 +26,8 @@ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ -;/* _tx_thread_interrupt_control Cortex-M4/AC5 */ -;/* 6.0.2 */ +;/* _tx_thread_interrupt_control Cortex-M4/AC5 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -57,10 +57,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_m4/keil/src/tx_thread_interrupt_disable.s b/ports/cortex_m4/keil/src/tx_thread_interrupt_disable.s index 2504a54d..6d11e5b8 100644 --- a/ports/cortex_m4/keil/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m4/keil/src/tx_thread_interrupt_disable.s @@ -26,8 +26,8 @@ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ -;/* _tx_thread_interrupt_disable Cortex-M4/AC5 */ -;/* 6.0.2 */ +;/* _tx_thread_interrupt_disable Cortex-M4/AC5 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -57,10 +57,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(UINT new_posture) diff --git a/ports/cortex_m4/keil/src/tx_thread_interrupt_restore.s b/ports/cortex_m4/keil/src/tx_thread_interrupt_restore.s index 8cb20abc..0f52527b 100644 --- a/ports/cortex_m4/keil/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m4/keil/src/tx_thread_interrupt_restore.s @@ -26,8 +26,8 @@ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ -;/* _tx_thread_interrupt_restore Cortex-M4/AC5 */ -;/* 6.0.2 */ +;/* _tx_thread_interrupt_restore Cortex-M4/AC5 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -57,10 +57,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_interrupt_restore(UINT new_posture) diff --git a/ports/cortex_m4/keil/src/tx_thread_schedule.s b/ports/cortex_m4/keil/src/tx_thread_schedule.s index 56159f35..347681c8 100644 --- a/ports/cortex_m4/keil/src/tx_thread_schedule.s +++ b/ports/cortex_m4/keil/src/tx_thread_schedule.s @@ -38,8 +38,8 @@ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ -;/* _tx_thread_schedule Cortex-M4/AC5 */ -;/* 6.0.2 */ +;/* _tx_thread_schedule Cortex-M4/AC5 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -72,10 +72,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_m4/keil/src/tx_thread_stack_build.s b/ports/cortex_m4/keil/src/tx_thread_stack_build.s index 2b3b76f8..f548938b 100644 --- a/ports/cortex_m4/keil/src/tx_thread_stack_build.s +++ b/ports/cortex_m4/keil/src/tx_thread_stack_build.s @@ -20,15 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; ; AREA ||.text||, CODE, READONLY ;/**************************************************************************/ @@ -36,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build Cortex-M4/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -68,10 +59,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -122,7 +110,7 @@ _tx_thread_stack_build STR r3, [r2, #28] ; Store initial r10 STR r3, [r2, #32] ; Store initial r11 ; -; /* Hardware stack follows. / +; /* Hardware stack follows. */ ; STR r3, [r2, #36] ; Store initial r0 STR r3, [r2, #40] ; Store initial r1 diff --git a/ports/cortex_m4/keil/src/tx_thread_system_return.s b/ports/cortex_m4/keil/src/tx_thread_system_return.s index 1918450c..9c453e61 100644 --- a/ports/cortex_m4/keil/src/tx_thread_system_return.s +++ b/ports/cortex_m4/keil/src/tx_thread_system_return.s @@ -26,8 +26,8 @@ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ -;/* _tx_thread_system_return Cortex-M4/AC5 */ -;/* 6.0.2 */ +;/* _tx_thread_system_return Cortex-M4/AC5 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -59,10 +59,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_m4/keil/src/tx_timer_interrupt.s b/ports/cortex_m4/keil/src/tx_timer_interrupt.s index 3e23d43a..f5160174 100644 --- a/ports/cortex_m4/keil/src/tx_timer_interrupt.s +++ b/ports/cortex_m4/keil/src/tx_timer_interrupt.s @@ -41,8 +41,8 @@ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ -;/* _tx_timer_interrupt Cortex-M4/AC5 */ -;/* 6.0.2 */ +;/* _tx_timer_interrupt Cortex-M4/AC5 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -76,10 +76,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_m7/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_m7/ac5/example_build/tx_initialize_low_level.s index 0b7db8c2..2dad8fb4 100644 --- a/ports/cortex_m7/ac5/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m7/ac5/example_build/tx_initialize_low_level.s @@ -103,7 +103,7 @@ Reset_Handler ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level Cortex-M7/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -136,10 +136,7 @@ Reset_Handler ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_m7/ac5/inc/tx_port.h b/ports/cortex_m7/ac5/inc/tx_port.h index 57480ebb..e621a41a 100644 --- a/ports/cortex_m7/ac5/inc/tx_port.h +++ b/ports/cortex_m7/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M7/AC5 */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -454,7 +454,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/AC5 Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/AC5 Version 6.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m7/ac5/readme_threadx.txt b/ports/cortex_m7/ac5/readme_threadx.txt index 57e21b28..648b030d 100644 --- a/ports/cortex_m7/ac5/readme_threadx.txt +++ b/ports/cortex_m7/ac5/readme_threadx.txt @@ -197,12 +197,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -08-14-2020 ThreadX update of Cortex-M7/AC5 port. The following files were - changed/added for port specific version 6.0.2: - - *.s Modified comments and whitespace. - -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M7 using AC5 tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-M7 using AC5 tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_m7/ac5/src/tx_thread_context_restore.s b/ports/cortex_m7/ac5/src/tx_thread_context_restore.s index 92f481f9..d63c29c8 100644 --- a/ports/cortex_m7/ac5/src/tx_thread_context_restore.s +++ b/ports/cortex_m7/ac5/src/tx_thread_context_restore.s @@ -33,7 +33,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore Cortex-M7/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -67,10 +67,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m7/ac5/src/tx_thread_context_save.s b/ports/cortex_m7/ac5/src/tx_thread_context_save.s index 4626a8ee..55747b13 100644 --- a/ports/cortex_m7/ac5/src/tx_thread_context_save.s +++ b/ports/cortex_m7/ac5/src/tx_thread_context_save.s @@ -33,7 +33,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save Cortex-M7/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -66,10 +66,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m7/ac5/src/tx_thread_interrupt_control.s b/ports/cortex_m7/ac5/src/tx_thread_interrupt_control.s index 090cc3c1..059053b5 100644 --- a/ports/cortex_m7/ac5/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m7/ac5/src/tx_thread_interrupt_control.s @@ -27,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control Cortex-M7/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -57,10 +57,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_m7/ac5/src/tx_thread_interrupt_disable.s b/ports/cortex_m7/ac5/src/tx_thread_interrupt_disable.s index 79ca1e67..0030e9a4 100644 --- a/ports/cortex_m7/ac5/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m7/ac5/src/tx_thread_interrupt_disable.s @@ -27,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_disable Cortex-M7/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -57,10 +57,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(UINT new_posture) diff --git a/ports/cortex_m7/ac5/src/tx_thread_interrupt_restore.s b/ports/cortex_m7/ac5/src/tx_thread_interrupt_restore.s index 7fc8fb4b..8bb8fea2 100644 --- a/ports/cortex_m7/ac5/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m7/ac5/src/tx_thread_interrupt_restore.s @@ -27,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-M7/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -57,10 +57,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_interrupt_restore(UINT new_posture) diff --git a/ports/cortex_m7/ac5/src/tx_thread_schedule.s b/ports/cortex_m7/ac5/src/tx_thread_schedule.s index fbdd7a2b..6f5e9daa 100644 --- a/ports/cortex_m7/ac5/src/tx_thread_schedule.s +++ b/ports/cortex_m7/ac5/src/tx_thread_schedule.s @@ -39,7 +39,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M7/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -72,10 +72,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_m7/ac5/src/tx_thread_stack_build.s b/ports/cortex_m7/ac5/src/tx_thread_stack_build.s index ce4b928d..73fcccf2 100644 --- a/ports/cortex_m7/ac5/src/tx_thread_stack_build.s +++ b/ports/cortex_m7/ac5/src/tx_thread_stack_build.s @@ -27,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build Cortex-M7/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -59,10 +59,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_m7/ac5/src/tx_thread_system_return.s b/ports/cortex_m7/ac5/src/tx_thread_system_return.s index 12b14b7e..917abbc8 100644 --- a/ports/cortex_m7/ac5/src/tx_thread_system_return.s +++ b/ports/cortex_m7/ac5/src/tx_thread_system_return.s @@ -27,7 +27,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return Cortex-M7/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -59,10 +59,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_m7/ac5/src/tx_timer_interrupt.s b/ports/cortex_m7/ac5/src/tx_timer_interrupt.s index 491f99b0..d18bbd08 100644 --- a/ports/cortex_m7/ac5/src/tx_timer_interrupt.s +++ b/ports/cortex_m7/ac5/src/tx_timer_interrupt.s @@ -42,7 +42,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt Cortex-M7/AC5 */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -76,10 +76,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S index e3a08654..32c96cf4 100644 --- a/ports/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -47,7 +47,7 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* FUNCTION RELEASE */ @/* */ @/* _tx_initialize_low_level Cortex-M7/AC6 */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -80,10 +80,7 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_m7/ac6/inc/tx_port.h b/ports/cortex_m7/ac6/inc/tx_port.h index 129c26fe..f73dc482 100644 --- a/ports/cortex_m7/ac6/inc/tx_port.h +++ b/ports/cortex_m7/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M7/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -482,7 +482,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/AC6 Version 6.0.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/AC6 Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_m7/ac6/readme_threadx.txt b/ports/cortex_m7/ac6/readme_threadx.txt index fd7a1025..a7f9aaae 100644 --- a/ports/cortex_m7/ac6/readme_threadx.txt +++ b/ports/cortex_m7/ac6/readme_threadx.txt @@ -144,12 +144,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -08-14-2020 ThreadX update of Cortex-M7/AC6 port. The following files were - changed/added for port specific version 6.0.2: - - *.s Modified comments and whitespace. - -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M7 using AC6 tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-M7 using AC6 tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_m7/ac6/src/tx_thread_context_restore.S b/ports/cortex_m7/ac6/src/tx_thread_context_restore.S index 529c47f8..e512d16f 100644 --- a/ports/cortex_m7/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_m7/ac6/src/tx_thread_context_restore.S @@ -38,7 +38,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_restore Cortex-M7/AC6 */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -72,10 +72,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m7/ac6/src/tx_thread_context_save.S b/ports/cortex_m7/ac6/src/tx_thread_context_save.S index 90ba4b8b..00f1f550 100644 --- a/ports/cortex_m7/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_m7/ac6/src/tx_thread_context_save.S @@ -33,7 +33,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_save Cortex-M7/AC6 */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -66,10 +66,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m7/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_m7/ac6/src/tx_thread_interrupt_control.S index 5c463ac1..d146da48 100644 --- a/ports/cortex_m7/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m7/ac6/src/tx_thread_interrupt_control.S @@ -28,7 +28,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_control Cortex-M7/AC6 */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -58,10 +58,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @/* UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_m7/ac6/src/tx_thread_schedule.S b/ports/cortex_m7/ac6/src/tx_thread_schedule.S index 2fc270f7..be98698a 100644 --- a/ports/cortex_m7/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_m7/ac6/src/tx_thread_schedule.S @@ -35,7 +35,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule Cortex-M7/AC6 */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -68,10 +68,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_m7/ac6/src/tx_thread_stack_build.S b/ports/cortex_m7/ac6/src/tx_thread_stack_build.S index 6adc81ac..c218041e 100644 --- a/ports/cortex_m7/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_m7/ac6/src/tx_thread_stack_build.S @@ -29,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_stack_build Cortex-M7/AC6 */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -61,10 +61,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_m7/ac6/src/tx_thread_system_return.S b/ports/cortex_m7/ac6/src/tx_thread_system_return.S index 6ba17aab..27b67633 100644 --- a/ports/cortex_m7/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_m7/ac6/src/tx_thread_system_return.S @@ -29,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_system_return Cortex-M7/AC6 */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -61,10 +61,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @/* VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_m7/ac6/src/tx_timer_interrupt.S b/ports/cortex_m7/ac6/src/tx_timer_interrupt.S index 597fbfa5..7f34283d 100644 --- a/ports/cortex_m7/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_m7/ac6/src/tx_timer_interrupt.S @@ -40,7 +40,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_timer_interrupt Cortex-M7/AC6 */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -74,10 +74,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_m7/ghs/example_build/azure_rtos_workspace.gpj b/ports/cortex_m7/ghs/example_build/azure_rtos_workspace.gpj new file mode 100644 index 00000000..16f753b0 --- /dev/null +++ b/ports/cortex_m7/ghs/example_build/azure_rtos_workspace.gpj @@ -0,0 +1,13 @@ +#!gbuild +primaryTarget=arm_standalone.tgt +[Project] + -bsp generic + -G + -littleendian + -cpu=cortexm7 + -fsingle +sample_threadx.gpj [Program] +sample_threadx_el.gpj [Program] +tx.gpj [Library] +txe.gpj [Library] +..\readme_threadx.txt diff --git a/ports/cortex_m7/ghs/example_build/reset.arm b/ports/cortex_m7/ghs/example_build/reset.arm new file mode 100644 index 00000000..32a123fa --- /dev/null +++ b/ports/cortex_m7/ghs/example_build/reset.arm @@ -0,0 +1,40 @@ +# +# +#/* Define the Cortex-M7 vector area. */ +# + + .section ".reset", .text + .globl __vectors +__vectors: + .data.w __ghsend_stack # Reset and system stack ptr + .data.w __Reset_Handler # Reset goes to Reset Handler + .data.w __tx_NMIHandler # NMI + .data.w __tx_BadHandler # HardFault + .data.w 0 # MemManage + .data.w 0 # BusFault + .data.w 0 # UsageFault + .data.w 0 # 7 + .data.w 0 # 8 + .data.w 0 # 9 + .data.w 0 # 10 + .data.w __tx_SVCallHandler # SVCall + .data.w __tx_DBGHandler # Monitor + .data.w 0 # 13 + .data.w __tx_PendSVHandler # PendSV + .data.w __tx_SysTickHandler # SysTick + .data.w __tx_IntHandler # Int 0 + .data.w __tx_IntHandler # Int 1 + .data.w __tx_IntHandler # Int 2 + .data.w __tx_IntHandler # Int 3 + .type __vectors,$object + .size __vectors,.-__vectors +# +# + .globl __Reset_Handler +__Reset_Handler: + CPSID i # Disable interrupts + LDR r0,=_start # Build address of GHS startup code + BX r0 # Enter GHS startup + + .type __Reset_Handler,$function + .size __Reset_Handler,.-__Reset_Handler diff --git a/ports/cortex_m7/ghs/example_build/sample_threadx.c b/ports/cortex_m7/ghs/example_build/sample_threadx.c new file mode 100644 index 00000000..418ec634 --- /dev/null +++ b/ports/cortex_m7/ghs/example_build/sample_threadx.c @@ -0,0 +1,369 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_m7/ghs/example_build/sample_threadx.con b/ports/cortex_m7/ghs/example_build/sample_threadx.con new file mode 100644 index 00000000..3f474f0a --- /dev/null +++ b/ports/cortex_m7/ghs/example_build/sample_threadx.con @@ -0,0 +1,17 @@ +target_connection { + { + title = "Simulator" + type = "Custom" + short_type = "Custom" + args = "simarm -cpu=cortexm7 -fpu -rom_use_entry" + command = "simarm -cpu=cortexm7 -fpu -rom_use_entry" + logfile = "" + mode = "download" + setup_script = "" + run_mode_partner = "" + run_mode_policy = "" + sane = "yes" + log = "no" + timestamp = "0" + } +} diff --git a/ports/cortex_m7/ghs/example_build/sample_threadx.gpj b/ports/cortex_m7/ghs/example_build/sample_threadx.gpj new file mode 100644 index 00000000..b9b2c04c --- /dev/null +++ b/ports/cortex_m7/ghs/example_build/sample_threadx.gpj @@ -0,0 +1,11 @@ +#!gbuild +[Program] + -I../../../../common/inc + -I../../../../ports_common_green/inc + -I../inc +reset.arm +tx_initialize_low_level.arm +sample_threadx.c +tx.a +sample_threadx.ld +sample_threadx.con diff --git a/ports/cortex_m7/ghs/example_build/sample_threadx.ld b/ports/cortex_m7/ghs/example_build/sample_threadx.ld new file mode 100644 index 00000000..a5cfce73 --- /dev/null +++ b/ports/cortex_m7/ghs/example_build/sample_threadx.ld @@ -0,0 +1,45 @@ +# The following explains what the default Green Hills sections are for: +# +# picbase - base of the text sections, relocatable in -pic mode +# text - text section +# syscall - syscall section, for host I/O under Multi +# fixaddr/fixtype - for PIC/PID fixups +# rodata - read only data +# romdata - the ROM image of .data +# romsdata - the ROM image of .sdata +# secinfo - section information section, used by the start-up code +# pidbase - base of the data sections, relocatable in -pid mode +# sdabase - base of the small data area section pointer +# sbss - small BSS (zeroed data) section +# sdata - small data section +# data - non-zeroed writeable data section +# bss - zeroed data section +# heap - the heap, grows upward +# stack - the stack, grows downward + +-sec +{ + .reset 0x000000 : + .picbase 0x1000 : + .text : + .comment : + .intercall : + .interfunc : + .syscall : + .fixaddr : + .fixtype : + .rodata : + .romdata ROM(.data) : + .romsdata ROM(.sdata) : + .secinfo : + .pidbase align(16) : + .sdabase : + .sbss : + .sdata : + .data : + .bss : + .heap align(16) pad(0x10000) : + .stack align(16) pad(0x1000) : + .free_mem align(16) pad(0x10000) : + .sys_regs 0xE0000000 pad(0xe000) : +} diff --git a/ports/cortex_m7/ghs/example_build/sample_threadx_el.gpj b/ports/cortex_m7/ghs/example_build/sample_threadx_el.gpj new file mode 100644 index 00000000..a51049ca --- /dev/null +++ b/ports/cortex_m7/ghs/example_build/sample_threadx_el.gpj @@ -0,0 +1,13 @@ +#!gbuild +[Program] + -DTX_ENABLE_EVENT_LOGGING + -I../../../../common/inc + -I../../../../ports_common_green/inc + -I../inc +reset.arm +tx_initialize_low_level.arm +sample_threadx.c +txe.a +sample_threadx_el.ld +sample_threadx.con +readme_threadx.txt diff --git a/ports/cortex_m7/ghs/example_build/sample_threadx_el.ld b/ports/cortex_m7/ghs/example_build/sample_threadx_el.ld new file mode 100644 index 00000000..753374c7 --- /dev/null +++ b/ports/cortex_m7/ghs/example_build/sample_threadx_el.ld @@ -0,0 +1,46 @@ +# The following explains what the default Green Hills sections are for: +# +# picbase - base of the text sections, relocatable in -pic mode +# text - text section +# syscall - syscall section, for host I/O under Multi +# fixaddr/fixtype - for PIC/PID fixups +# rodata - read only data +# romdata - the ROM image of .data +# romsdata - the ROM image of .sdata +# secinfo - section information section, used by the start-up code +# pidbase - base of the data sections, relocatable in -pid mode +# sdabase - base of the small data area section pointer +# sbss - small BSS (zeroed data) section +# sdata - small data section +# data - non-zeroed writeable data section +# bss - zeroed data section +# heap - the heap, grows upward +# stack - the stack, grows downward + +-sec +{ + .reset 0x000000 : + .picbase 0x1000 : + .text : + .comment : + .intercall : + .interfunc : + .syscall : + .fixaddr : + .fixtype : + .rodata : + .romdata ROM(.data) : + .romsdata ROM(.sdata) : + .secinfo : + .pidbase align(16) : + .sdabase : + .sbss : + .sdata : + .data : + .bss : + .heap align(16) pad(0x1000) : + .stack align(16) pad(0x1000) : + .eventlog align(16) pad(0x10000) : + .free_mem align(16) pad(0x10000) : + .sys_regs 0xE0000000 pad(0xe000) : +} diff --git a/ports/cortex_m7/ghs/example_build/tx.gpj b/ports/cortex_m7/ghs/example_build/tx.gpj new file mode 100644 index 00000000..ca9baa41 --- /dev/null +++ b/ports/cortex_m7/ghs/example_build/tx.gpj @@ -0,0 +1,215 @@ +#!gbuild +[Library] + -I../../../../common/inc + -I../inc +..\..\..\..\common\inc\tx_api.h +..\..\..\..\common\inc\tx_block_pool.h +..\..\..\..\common\inc\tx_byte_pool.h +..\..\..\..\common\inc\tx_event_flags.h +..\..\..\..\common\inc\tx_initialize.h +..\..\..\..\common\inc\tx_mutex.h +..\..\..\..\common\inc\tx_queue.h +..\..\..\..\common\inc\tx_semaphore.h +..\..\..\..\common\inc\tx_thread.h +..\..\..\..\common\inc\tx_timer.h +..\..\..\..\common\inc\tx_trace.h +..\..\..\..\common\inc\tx_user_sample.h +..\inc\tx_port.h +..\inc\tx_el.h +..\inc\tx_ghs.h +..\src\tx_el.c +..\src\tx_ghs.c +..\src\tx_ghse.c +..\src\tx_thread_context_restore.arm +..\src\tx_thread_context_save.arm +..\src\tx_thread_interrupt_control.arm +..\src\tx_thread_interrupt_disable.arm +..\src\tx_thread_interrupt_restore.arm +..\src\tx_thread_schedule.arm +..\src\tx_thread_stack_build.arm +..\src\tx_thread_system_return.arm +..\src\tx_timer_interrupt.arm +..\..\..\..\common\src\tx_block_allocate.c +..\..\..\..\common\src\tx_block_pool_cleanup.c +..\..\..\..\common\src\tx_block_pool_create.c +..\..\..\..\common\src\tx_block_pool_delete.c +..\..\..\..\common\src\tx_block_pool_info_get.c +..\..\..\..\common\src\tx_block_pool_initialize.c +..\..\..\..\common\src\tx_block_pool_performance_info_get.c +..\..\..\..\common\src\tx_block_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_block_pool_prioritize.c +..\..\..\..\common\src\tx_block_release.c +..\..\..\..\common\src\tx_byte_allocate.c +..\..\..\..\common\src\tx_byte_pool_cleanup.c +..\..\..\..\common\src\tx_byte_pool_create.c +..\..\..\..\common\src\tx_byte_pool_delete.c +..\..\..\..\common\src\tx_byte_pool_info_get.c +..\..\..\..\common\src\tx_byte_pool_initialize.c +..\..\..\..\common\src\tx_byte_pool_performance_info_get.c +..\..\..\..\common\src\tx_byte_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_byte_pool_prioritize.c +..\..\..\..\common\src\tx_byte_pool_search.c +..\..\..\..\common\src\tx_byte_release.c +..\..\..\..\common\src\tx_event_flags_cleanup.c +..\..\..\..\common\src\tx_event_flags_create.c +..\..\..\..\common\src\tx_event_flags_delete.c +..\..\..\..\common\src\tx_event_flags_get.c +..\..\..\..\common\src\tx_event_flags_info_get.c +..\..\..\..\common\src\tx_event_flags_initialize.c +..\..\..\..\common\src\tx_event_flags_performance_info_get.c +..\..\..\..\common\src\tx_event_flags_performance_system_info_get.c +..\..\..\..\common\src\tx_event_flags_set.c +..\..\..\..\common\src\tx_event_flags_set_notify.c +..\..\..\..\common\src\tx_initialize_high_level.c +..\..\..\..\common\src\tx_initialize_kernel_enter.c +..\..\..\..\common\src\tx_initialize_kernel_setup.c +..\..\..\..\common\src\tx_mutex_cleanup.c +..\..\..\..\common\src\tx_mutex_create.c +..\..\..\..\common\src\tx_mutex_delete.c +..\..\..\..\common\src\tx_mutex_get.c +..\..\..\..\common\src\tx_mutex_info_get.c +..\..\..\..\common\src\tx_mutex_initialize.c +..\..\..\..\common\src\tx_mutex_performance_info_get.c +..\..\..\..\common\src\tx_mutex_performance_system_info_get.c +..\..\..\..\common\src\tx_mutex_prioritize.c +..\..\..\..\common\src\tx_mutex_priority_change.c +..\..\..\..\common\src\tx_mutex_put.c +..\..\..\..\common\src\tx_queue_cleanup.c +..\..\..\..\common\src\tx_queue_create.c +..\..\..\..\common\src\tx_queue_delete.c +..\..\..\..\common\src\tx_queue_flush.c +..\..\..\..\common\src\tx_queue_front_send.c +..\..\..\..\common\src\tx_queue_info_get.c +..\..\..\..\common\src\tx_queue_initialize.c +..\..\..\..\common\src\tx_queue_performance_info_get.c +..\..\..\..\common\src\tx_queue_performance_system_info_get.c +..\..\..\..\common\src\tx_queue_prioritize.c +..\..\..\..\common\src\tx_queue_receive.c +..\..\..\..\common\src\tx_queue_send.c +..\..\..\..\common\src\tx_queue_send_notify.c +..\..\..\..\common\src\tx_semaphore_ceiling_put.c +..\..\..\..\common\src\tx_semaphore_cleanup.c +..\..\..\..\common\src\tx_semaphore_create.c +..\..\..\..\common\src\tx_semaphore_delete.c +..\..\..\..\common\src\tx_semaphore_get.c +..\..\..\..\common\src\tx_semaphore_info_get.c +..\..\..\..\common\src\tx_semaphore_initialize.c +..\..\..\..\common\src\tx_semaphore_performance_info_get.c +..\..\..\..\common\src\tx_semaphore_performance_system_info_get.c +..\..\..\..\common\src\tx_semaphore_prioritize.c +..\..\..\..\common\src\tx_semaphore_put.c +..\..\..\..\common\src\tx_semaphore_put_notify.c +..\..\..\..\common\src\tx_thread_create.c +..\..\..\..\common\src\tx_thread_delete.c +..\..\..\..\common\src\tx_thread_entry_exit_notify.c +..\..\..\..\common\src\tx_thread_identify.c +..\..\..\..\common\src\tx_thread_info_get.c +..\..\..\..\common\src\tx_thread_initialize.c +..\..\..\..\common\src\tx_thread_performance_info_get.c +..\..\..\..\common\src\tx_thread_performance_system_info_get.c +..\..\..\..\common\src\tx_thread_preemption_change.c +..\..\..\..\common\src\tx_thread_priority_change.c +..\..\..\..\common\src\tx_thread_relinquish.c +..\..\..\..\common\src\tx_thread_reset.c +..\..\..\..\common\src\tx_thread_resume.c +..\..\..\..\common\src\tx_thread_shell_entry.c +..\..\..\..\common\src\tx_thread_sleep.c +..\..\..\..\common\src\tx_thread_stack_analyze.c +..\..\..\..\common\src\tx_thread_stack_error_handler.c +..\..\..\..\common\src\tx_thread_stack_error_notify.c +..\..\..\..\common\src\tx_thread_suspend.c +..\..\..\..\common\src\tx_thread_system_preempt_check.c +..\..\..\..\common\src\tx_thread_system_resume.c +..\..\..\..\common\src\tx_thread_system_suspend.c +..\..\..\..\common\src\tx_thread_terminate.c +..\..\..\..\common\src\tx_thread_time_slice.c +..\..\..\..\common\src\tx_thread_time_slice_change.c +..\..\..\..\common\src\tx_thread_timeout.c +..\..\..\..\common\src\tx_thread_wait_abort.c +..\..\..\..\common\src\tx_time_get.c +..\..\..\..\common\src\tx_time_set.c +..\..\..\..\common\src\tx_timer_activate.c +..\..\..\..\common\src\tx_timer_change.c +..\..\..\..\common\src\tx_timer_create.c +..\..\..\..\common\src\tx_timer_deactivate.c +..\..\..\..\common\src\tx_timer_delete.c +..\..\..\..\common\src\tx_timer_expiration_process.c +..\..\..\..\common\src\tx_timer_info_get.c +..\..\..\..\common\src\tx_timer_initialize.c +..\..\..\..\common\src\tx_timer_performance_info_get.c +..\..\..\..\common\src\tx_timer_performance_system_info_get.c +..\..\..\..\common\src\tx_timer_system_activate.c +..\..\..\..\common\src\tx_timer_system_deactivate.c +..\..\..\..\common\src\tx_timer_thread_entry.c +..\..\..\..\common\src\tx_trace_buffer_full_notify.c +..\..\..\..\common\src\tx_trace_disable.c +..\..\..\..\common\src\tx_trace_enable.c +..\..\..\..\common\src\tx_trace_event_filter.c +..\..\..\..\common\src\tx_trace_event_unfilter.c +..\..\..\..\common\src\tx_trace_initialize.c +..\..\..\..\common\src\tx_trace_interrupt_control.c +..\..\..\..\common\src\tx_trace_isr_enter_insert.c +..\..\..\..\common\src\tx_trace_isr_exit_insert.c +..\..\..\..\common\src\tx_trace_object_register.c +..\..\..\..\common\src\tx_trace_object_unregister.c +..\..\..\..\common\src\tx_trace_user_event_insert.c +..\..\..\..\common\src\txe_block_allocate.c +..\..\..\..\common\src\txe_block_pool_create.c +..\..\..\..\common\src\txe_block_pool_delete.c +..\..\..\..\common\src\txe_block_pool_info_get.c +..\..\..\..\common\src\txe_block_pool_prioritize.c +..\..\..\..\common\src\txe_block_release.c +..\..\..\..\common\src\txe_byte_allocate.c +..\..\..\..\common\src\txe_byte_pool_create.c +..\..\..\..\common\src\txe_byte_pool_delete.c +..\..\..\..\common\src\txe_byte_pool_info_get.c +..\..\..\..\common\src\txe_byte_pool_prioritize.c +..\..\..\..\common\src\txe_byte_release.c +..\..\..\..\common\src\txe_event_flags_create.c +..\..\..\..\common\src\txe_event_flags_delete.c +..\..\..\..\common\src\txe_event_flags_get.c +..\..\..\..\common\src\txe_event_flags_info_get.c +..\..\..\..\common\src\txe_event_flags_set.c +..\..\..\..\common\src\txe_event_flags_set_notify.c +..\..\..\..\common\src\txe_mutex_create.c +..\..\..\..\common\src\txe_mutex_delete.c +..\..\..\..\common\src\txe_mutex_get.c +..\..\..\..\common\src\txe_mutex_info_get.c +..\..\..\..\common\src\txe_mutex_prioritize.c +..\..\..\..\common\src\txe_mutex_put.c +..\..\..\..\common\src\txe_queue_create.c +..\..\..\..\common\src\txe_queue_delete.c +..\..\..\..\common\src\txe_queue_flush.c +..\..\..\..\common\src\txe_queue_front_send.c +..\..\..\..\common\src\txe_queue_info_get.c +..\..\..\..\common\src\txe_queue_prioritize.c +..\..\..\..\common\src\txe_queue_receive.c +..\..\..\..\common\src\txe_queue_send.c +..\..\..\..\common\src\txe_queue_send_notify.c +..\..\..\..\common\src\txe_semaphore_ceiling_put.c +..\..\..\..\common\src\txe_semaphore_create.c +..\..\..\..\common\src\txe_semaphore_delete.c +..\..\..\..\common\src\txe_semaphore_get.c +..\..\..\..\common\src\txe_semaphore_info_get.c +..\..\..\..\common\src\txe_semaphore_prioritize.c +..\..\..\..\common\src\txe_semaphore_put.c +..\..\..\..\common\src\txe_semaphore_put_notify.c +..\..\..\..\common\src\txe_thread_create.c +..\..\..\..\common\src\txe_thread_delete.c +..\..\..\..\common\src\txe_thread_entry_exit_notify.c +..\..\..\..\common\src\txe_thread_info_get.c +..\..\..\..\common\src\txe_thread_preemption_change.c +..\..\..\..\common\src\txe_thread_priority_change.c +..\..\..\..\common\src\txe_thread_relinquish.c +..\..\..\..\common\src\txe_thread_reset.c +..\..\..\..\common\src\txe_thread_resume.c +..\..\..\..\common\src\txe_thread_suspend.c +..\..\..\..\common\src\txe_thread_terminate.c +..\..\..\..\common\src\txe_thread_time_slice_change.c +..\..\..\..\common\src\txe_thread_wait_abort.c +..\..\..\..\common\src\txe_timer_activate.c +..\..\..\..\common\src\txe_timer_change.c +..\..\..\..\common\src\txe_timer_create.c +..\..\..\..\common\src\txe_timer_deactivate.c +..\..\..\..\common\src\txe_timer_delete.c +..\..\..\..\common\src\txe_timer_info_get.c diff --git a/ports/cortex_m7/ghs/example_build/tx_initialize_low_level.arm b/ports/cortex_m7/ghs/example_build/tx_initialize_low_level.arm new file mode 100644 index 00000000..7c05080a --- /dev/null +++ b/ports/cortex_m7/ghs/example_build/tx_initialize_low_level.arm @@ -0,0 +1,232 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SYSTEM_CLOCK = 6000000 + SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-M7/GHS */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_initialize_low_level(VOID) +{ */ + .globl _tx_initialize_low_level +_tx_initialize_low_level: + + /* Disable interrupts. */ + + CPSID i ; Disable interrupts + + + /* Save the system stack pointer. */ + /* _tx_thread_system_stack_ptr = (VOID_PTR) (sp); */ + + LDR r1,=_tx_thread_system_stack_ptr ; Pickup address of system stack ptr + STR sp, [r1] ; Save system stack + + + /* Save the first available memory address. */ + /* _tx_initialize_unused_memory = (VOID_PTR) __ghsbegin_free_mem; */ + + LDR r0,=__ghsbegin_free_mem ; Pickup free memory address + LDR r2,=_tx_initialize_unused_memory ; Pickup unused memory ptr address + STR r0, [r2] ; Save first free memory address + + + /* Enable the cycle count register. */ + + LDR r0, =0xE0001000 ; Build address of DWT register + LDR r1, [r0] ; Pickup the current value + ORR r1, r1, 1 ; Set the CYCCNTENA bit + STR r1, [r0] ; Enable the cycle count register + + + /* Setup Vector Table Offset Register. */ + + MOV r0, 0xE000E000 ; Build address of NVIC registers + LDR r1, =__vectors ; Pickup address of vector table + STR r1, [r0, 0xD08] ; Set vector table address + + + /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ + + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, 0x14] ; Setup SysTick Reload Value + MOV r1, 0x7 ; Build SysTick Control Enable Value + STR r1, [r0, 0x10] ; Setup SysTick Control + + /* Configure handler priorities. */ + + LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM + STR r1, [r0, 0xD18] ; Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, 0xD1C] ; Setup System Handlers 8-11 Priority Registers + ; Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM + STR r1, [r0, 0xD20] ; Setup System Handlers 12-15 Priority Registers + ; Note: PnSV must be lowest priority, which is 0xFF + +#ifdef __VFP__ + LDR r0, =0xE000EF34 ; Pickup FPCCR + LDR r1, [r0] ; + LDR r2, =0x3FFFFFFF ; Build mask to clear ASPEN and LSPEN + AND r1, r1, r2 ; Clear the ASPEN and LSPEN bits + STR r1, [r0] ; Update FPCCR +#endif + + /* Return to caller. */ + + BX lr ; Return to caller + + .type _tx_initialize_low_level,$function + .size _tx_initialize_low_level,.-_tx_initialize_low_level +/* } */ + + +/* Define shells for each of the interrupt vectors. */ + + .globl __tx_BadHandler +__tx_BadHandler: + B __tx_BadHandler + + .type __tx_BadHandler,$function + .size __tx_BadHandler,.-__tx_BadHandler + + + .globl __tx_IntHandler +__tx_IntHandler: + PUSH {lr} + BL _tx_thread_context_save + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 0 ; Build interrupt code + BL _tx_el_interrupt ; Call interrupt event logging +#endif + +; /* Do interrupt handler work here */ +; /* .... */ + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 0 ; Build interrupt code + BL _tx_el_interrupt_end ; Call interrupt event logging +#endif + + B _tx_thread_context_restore + + .type __tx_IntHandler,$function + .size __tx_IntHandler,.-__tx_IntHandler + + + .globl __tx_SysTickHandler +__tx_SysTickHandler: + PUSH {lr} + BL _tx_thread_context_save + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 15 ; Build interrupt code + BL _tx_el_interrupt ; Call interrupt event logging +#endif + + BL _tx_timer_interrupt + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 15 ; Build interrupt code + BL _tx_el_interrupt_end ; Call interrupt event logging +#endif + + B _tx_thread_context_restore + + .type __tx_SysTickHandler,$function + .size __tx_SysTickHandler,.-__tx_SysTickHandler + + + .globl __tx_NMIHandler +__tx_NMIHandler: + B __tx_NMIHandler + + .type __tx_NMIHandler,$function + .size __tx_NMIHandler,.-__tx_NMIHandler + + + .globl __tx_DBGHandler +__tx_DBGHandler: + B __tx_DBGHandler + + .type __tx_DBGHandler,$function + .size __tx_DBGHandler,.-__tx_DBGHandler + + + .globl __tx_SVCallHandler +__tx_SVCallHandler: + B __tx_SVCallHandler + + .type __tx_SVCallHandler,$function + .size __tx_SVCallHandler,.-__tx_SVCallHandler + + + /* Reference build options and version ID to ensure they come in. */ + +BUILD_OPTIONS: + .data.w _tx_build_options +VERSION_ID: + .data.w _tx_version_id diff --git a/ports/cortex_m7/ghs/example_build/txe.gpj b/ports/cortex_m7/ghs/example_build/txe.gpj new file mode 100644 index 00000000..c7825b04 --- /dev/null +++ b/ports/cortex_m7/ghs/example_build/txe.gpj @@ -0,0 +1,216 @@ +#!gbuild +[Library] + -DTX_ENABLE_EVENT_LOGGING + -I../../../../common/inc + -I../inc +..\..\..\..\common\inc\tx_api.h +..\..\..\..\common\inc\tx_block_pool.h +..\..\..\..\common\inc\tx_byte_pool.h +..\..\..\..\common\inc\tx_event_flags.h +..\..\..\..\common\inc\tx_initialize.h +..\..\..\..\common\inc\tx_mutex.h +..\..\..\..\common\inc\tx_queue.h +..\..\..\..\common\inc\tx_semaphore.h +..\..\..\..\common\inc\tx_thread.h +..\..\..\..\common\inc\tx_timer.h +..\..\..\..\common\inc\tx_trace.h +..\..\..\..\common\inc\tx_user_sample.h +..\inc\tx_port.h +..\inc\tx_el.h +..\inc\tx_ghs.h +..\src\tx_el.c +..\src\tx_ghs.c +..\src\tx_ghse.c +..\src\tx_thread_context_restore.arm +..\src\tx_thread_context_save.arm +..\src\tx_thread_interrupt_control.arm +..\src\tx_thread_interrupt_disable.arm +..\src\tx_thread_interrupt_restore.arm +..\src\tx_thread_schedule.arm +..\src\tx_thread_stack_build.arm +..\src\tx_thread_system_return.arm +..\src\tx_timer_interrupt.arm +..\..\..\..\common\src\tx_block_allocate.c +..\..\..\..\common\src\tx_block_pool_cleanup.c +..\..\..\..\common\src\tx_block_pool_create.c +..\..\..\..\common\src\tx_block_pool_delete.c +..\..\..\..\common\src\tx_block_pool_info_get.c +..\..\..\..\common\src\tx_block_pool_initialize.c +..\..\..\..\common\src\tx_block_pool_performance_info_get.c +..\..\..\..\common\src\tx_block_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_block_pool_prioritize.c +..\..\..\..\common\src\tx_block_release.c +..\..\..\..\common\src\tx_byte_allocate.c +..\..\..\..\common\src\tx_byte_pool_cleanup.c +..\..\..\..\common\src\tx_byte_pool_create.c +..\..\..\..\common\src\tx_byte_pool_delete.c +..\..\..\..\common\src\tx_byte_pool_info_get.c +..\..\..\..\common\src\tx_byte_pool_initialize.c +..\..\..\..\common\src\tx_byte_pool_performance_info_get.c +..\..\..\..\common\src\tx_byte_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_byte_pool_prioritize.c +..\..\..\..\common\src\tx_byte_pool_search.c +..\..\..\..\common\src\tx_byte_release.c +..\..\..\..\common\src\tx_event_flags_cleanup.c +..\..\..\..\common\src\tx_event_flags_create.c +..\..\..\..\common\src\tx_event_flags_delete.c +..\..\..\..\common\src\tx_event_flags_get.c +..\..\..\..\common\src\tx_event_flags_info_get.c +..\..\..\..\common\src\tx_event_flags_initialize.c +..\..\..\..\common\src\tx_event_flags_performance_info_get.c +..\..\..\..\common\src\tx_event_flags_performance_system_info_get.c +..\..\..\..\common\src\tx_event_flags_set.c +..\..\..\..\common\src\tx_event_flags_set_notify.c +..\..\..\..\common\src\tx_initialize_high_level.c +..\..\..\..\common\src\tx_initialize_kernel_enter.c +..\..\..\..\common\src\tx_initialize_kernel_setup.c +..\..\..\..\common\src\tx_mutex_cleanup.c +..\..\..\..\common\src\tx_mutex_create.c +..\..\..\..\common\src\tx_mutex_delete.c +..\..\..\..\common\src\tx_mutex_get.c +..\..\..\..\common\src\tx_mutex_info_get.c +..\..\..\..\common\src\tx_mutex_initialize.c +..\..\..\..\common\src\tx_mutex_performance_info_get.c +..\..\..\..\common\src\tx_mutex_performance_system_info_get.c +..\..\..\..\common\src\tx_mutex_prioritize.c +..\..\..\..\common\src\tx_mutex_priority_change.c +..\..\..\..\common\src\tx_mutex_put.c +..\..\..\..\common\src\tx_queue_cleanup.c +..\..\..\..\common\src\tx_queue_create.c +..\..\..\..\common\src\tx_queue_delete.c +..\..\..\..\common\src\tx_queue_flush.c +..\..\..\..\common\src\tx_queue_front_send.c +..\..\..\..\common\src\tx_queue_info_get.c +..\..\..\..\common\src\tx_queue_initialize.c +..\..\..\..\common\src\tx_queue_performance_info_get.c +..\..\..\..\common\src\tx_queue_performance_system_info_get.c +..\..\..\..\common\src\tx_queue_prioritize.c +..\..\..\..\common\src\tx_queue_receive.c +..\..\..\..\common\src\tx_queue_send.c +..\..\..\..\common\src\tx_queue_send_notify.c +..\..\..\..\common\src\tx_semaphore_ceiling_put.c +..\..\..\..\common\src\tx_semaphore_cleanup.c +..\..\..\..\common\src\tx_semaphore_create.c +..\..\..\..\common\src\tx_semaphore_delete.c +..\..\..\..\common\src\tx_semaphore_get.c +..\..\..\..\common\src\tx_semaphore_info_get.c +..\..\..\..\common\src\tx_semaphore_initialize.c +..\..\..\..\common\src\tx_semaphore_performance_info_get.c +..\..\..\..\common\src\tx_semaphore_performance_system_info_get.c +..\..\..\..\common\src\tx_semaphore_prioritize.c +..\..\..\..\common\src\tx_semaphore_put.c +..\..\..\..\common\src\tx_semaphore_put_notify.c +..\..\..\..\common\src\tx_thread_create.c +..\..\..\..\common\src\tx_thread_delete.c +..\..\..\..\common\src\tx_thread_entry_exit_notify.c +..\..\..\..\common\src\tx_thread_identify.c +..\..\..\..\common\src\tx_thread_info_get.c +..\..\..\..\common\src\tx_thread_initialize.c +..\..\..\..\common\src\tx_thread_performance_info_get.c +..\..\..\..\common\src\tx_thread_performance_system_info_get.c +..\..\..\..\common\src\tx_thread_preemption_change.c +..\..\..\..\common\src\tx_thread_priority_change.c +..\..\..\..\common\src\tx_thread_relinquish.c +..\..\..\..\common\src\tx_thread_reset.c +..\..\..\..\common\src\tx_thread_resume.c +..\..\..\..\common\src\tx_thread_shell_entry.c +..\..\..\..\common\src\tx_thread_sleep.c +..\..\..\..\common\src\tx_thread_stack_analyze.c +..\..\..\..\common\src\tx_thread_stack_error_handler.c +..\..\..\..\common\src\tx_thread_stack_error_notify.c +..\..\..\..\common\src\tx_thread_suspend.c +..\..\..\..\common\src\tx_thread_system_preempt_check.c +..\..\..\..\common\src\tx_thread_system_resume.c +..\..\..\..\common\src\tx_thread_system_suspend.c +..\..\..\..\common\src\tx_thread_terminate.c +..\..\..\..\common\src\tx_thread_time_slice.c +..\..\..\..\common\src\tx_thread_time_slice_change.c +..\..\..\..\common\src\tx_thread_timeout.c +..\..\..\..\common\src\tx_thread_wait_abort.c +..\..\..\..\common\src\tx_time_get.c +..\..\..\..\common\src\tx_time_set.c +..\..\..\..\common\src\tx_timer_activate.c +..\..\..\..\common\src\tx_timer_change.c +..\..\..\..\common\src\tx_timer_create.c +..\..\..\..\common\src\tx_timer_deactivate.c +..\..\..\..\common\src\tx_timer_delete.c +..\..\..\..\common\src\tx_timer_expiration_process.c +..\..\..\..\common\src\tx_timer_info_get.c +..\..\..\..\common\src\tx_timer_initialize.c +..\..\..\..\common\src\tx_timer_performance_info_get.c +..\..\..\..\common\src\tx_timer_performance_system_info_get.c +..\..\..\..\common\src\tx_timer_system_activate.c +..\..\..\..\common\src\tx_timer_system_deactivate.c +..\..\..\..\common\src\tx_timer_thread_entry.c +..\..\..\..\common\src\tx_trace_buffer_full_notify.c +..\..\..\..\common\src\tx_trace_disable.c +..\..\..\..\common\src\tx_trace_enable.c +..\..\..\..\common\src\tx_trace_event_filter.c +..\..\..\..\common\src\tx_trace_event_unfilter.c +..\..\..\..\common\src\tx_trace_initialize.c +..\..\..\..\common\src\tx_trace_interrupt_control.c +..\..\..\..\common\src\tx_trace_isr_enter_insert.c +..\..\..\..\common\src\tx_trace_isr_exit_insert.c +..\..\..\..\common\src\tx_trace_object_register.c +..\..\..\..\common\src\tx_trace_object_unregister.c +..\..\..\..\common\src\tx_trace_user_event_insert.c +..\..\..\..\common\src\txe_block_allocate.c +..\..\..\..\common\src\txe_block_pool_create.c +..\..\..\..\common\src\txe_block_pool_delete.c +..\..\..\..\common\src\txe_block_pool_info_get.c +..\..\..\..\common\src\txe_block_pool_prioritize.c +..\..\..\..\common\src\txe_block_release.c +..\..\..\..\common\src\txe_byte_allocate.c +..\..\..\..\common\src\txe_byte_pool_create.c +..\..\..\..\common\src\txe_byte_pool_delete.c +..\..\..\..\common\src\txe_byte_pool_info_get.c +..\..\..\..\common\src\txe_byte_pool_prioritize.c +..\..\..\..\common\src\txe_byte_release.c +..\..\..\..\common\src\txe_event_flags_create.c +..\..\..\..\common\src\txe_event_flags_delete.c +..\..\..\..\common\src\txe_event_flags_get.c +..\..\..\..\common\src\txe_event_flags_info_get.c +..\..\..\..\common\src\txe_event_flags_set.c +..\..\..\..\common\src\txe_event_flags_set_notify.c +..\..\..\..\common\src\txe_mutex_create.c +..\..\..\..\common\src\txe_mutex_delete.c +..\..\..\..\common\src\txe_mutex_get.c +..\..\..\..\common\src\txe_mutex_info_get.c +..\..\..\..\common\src\txe_mutex_prioritize.c +..\..\..\..\common\src\txe_mutex_put.c +..\..\..\..\common\src\txe_queue_create.c +..\..\..\..\common\src\txe_queue_delete.c +..\..\..\..\common\src\txe_queue_flush.c +..\..\..\..\common\src\txe_queue_front_send.c +..\..\..\..\common\src\txe_queue_info_get.c +..\..\..\..\common\src\txe_queue_prioritize.c +..\..\..\..\common\src\txe_queue_receive.c +..\..\..\..\common\src\txe_queue_send.c +..\..\..\..\common\src\txe_queue_send_notify.c +..\..\..\..\common\src\txe_semaphore_ceiling_put.c +..\..\..\..\common\src\txe_semaphore_create.c +..\..\..\..\common\src\txe_semaphore_delete.c +..\..\..\..\common\src\txe_semaphore_get.c +..\..\..\..\common\src\txe_semaphore_info_get.c +..\..\..\..\common\src\txe_semaphore_prioritize.c +..\..\..\..\common\src\txe_semaphore_put.c +..\..\..\..\common\src\txe_semaphore_put_notify.c +..\..\..\..\common\src\txe_thread_create.c +..\..\..\..\common\src\txe_thread_delete.c +..\..\..\..\common\src\txe_thread_entry_exit_notify.c +..\..\..\..\common\src\txe_thread_info_get.c +..\..\..\..\common\src\txe_thread_preemption_change.c +..\..\..\..\common\src\txe_thread_priority_change.c +..\..\..\..\common\src\txe_thread_relinquish.c +..\..\..\..\common\src\txe_thread_reset.c +..\..\..\..\common\src\txe_thread_resume.c +..\..\..\..\common\src\txe_thread_suspend.c +..\..\..\..\common\src\txe_thread_terminate.c +..\..\..\..\common\src\txe_thread_time_slice_change.c +..\..\..\..\common\src\txe_thread_wait_abort.c +..\..\..\..\common\src\txe_timer_activate.c +..\..\..\..\common\src\txe_timer_change.c +..\..\..\..\common\src\txe_timer_create.c +..\..\..\..\common\src\txe_timer_deactivate.c +..\..\..\..\common\src\txe_timer_delete.c +..\..\..\..\common\src\txe_timer_info_get.c diff --git a/ports/cortex_m7/ghs/inc/tx_el.h b/ports/cortex_m7/ghs/inc/tx_el.h new file mode 100644 index 00000000..29c72370 --- /dev/null +++ b/ports/cortex_m7/ghs/inc/tx_el.h @@ -0,0 +1,765 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** ThreadX/GHS Event Log (EL) */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* tx_el.h PORTABLE C/GHS */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the ThreadX event log functions for the GHS MULTI */ +/* EventAnalyzer. It is assumed that tx_api.h and tx_port.h have */ +/* already been included. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_EL_H +#define TX_EL_H + + +/* Define Event Log specific data definitions. */ + +#define TX_EL_VERSION_ID 2 /* Event log version ID */ +#define TX_EL_HEADER_SIZE 24 /* Event log header size */ +#define TX_EL_TNIS 16 /* Number of thread names supported */ + /* If the application needs to */ + /* track more thread names, just */ + /* increase this number and re- */ + /* build the ThreadX library. */ +#define TX_EL_TNI_ENTRY_SIZE 44 /* Thread name entries are 44 bytes */ +#define TX_EL_TNI_NAME_SIZE 34 /* Thread name size in TNI */ +#define TX_EL_NO_MORE_TNI_ROOM 1 /* Error return from thread register*/ +#define TX_EL_NAME_NOT_FOUND 2 /* Error return from un-register */ +#define TX_EL_EVENT_SIZE 32 /* Number of bytes in each event */ +#define TX_EL_VALID_ENTRY 1 /* Valid log entry */ +#define TX_EL_INVALID_ENTRY 0 /* Invalid log entry */ + + +/* Define necessary offsets. */ + +#define TX_EL_TNI_VALID_OFFSET 34 +#define TX_EL_TNI_THREAD_ID_OFFSET 36 +#define TX_EL_TNI_THREAD_PRIORITY_OFF 40 +#define TX_EL_EVENT_TYPE_OFFSET 0 +#define TX_EL_EVENT_SUBTYPE_OFFSET 2 +#define TX_EL_EVENT_TIME_UPPER_OFFSET 4 +#define TX_EL_EVENT_TIME_LOWER_OFFSET 8 +#define TX_EL_EVENT_THREAD_OFFSET 12 +#define TX_EL_EVENT_INFO_1_OFFSET 16 +#define TX_EL_EVENT_INFO_2_OFFSET 20 +#define TX_EL_EVENT_INFO_3_OFFSET 24 +#define TX_EL_EVENT_INFO_4_OFFSET 28 + + +/* Undefine constants that might be been defined previously by tx_api.h. */ + +#undef TX_EL_INITIALIZE +#undef TX_EL_THREAD_REGISTER +#undef TX_EL_THREAD_UNREGISTER +#undef TX_EL_THREAD_STATUS_CHANGE_INSERT +#undef TX_EL_BYTE_ALLOCATE_INSERT +#undef TX_EL_BYTE_POOL_CREATE_INSERT +#undef TX_EL_BYTE_POOL_DELETE_INSERT +#undef TX_EL_BYTE_RELEASE_INSERT +#undef TX_EL_BLOCK_ALLOCATE_INSERT +#undef TX_EL_BLOCK_POOL_CREATE_INSERT +#undef TX_EL_BLOCK_POOL_DELETE_INSERT +#undef TX_EL_BLOCK_RELEASE_INSERT +#undef TX_EL_EVENT_FLAGS_CREATE_INSERT +#undef TX_EL_EVENT_FLAGS_DELETE_INSERT +#undef TX_EL_EVENT_FLAGS_GET_INSERT +#undef TX_EL_EVENT_FLAGS_SET_INSERT +#undef TX_EL_INTERRUPT_CONTROL_INSERT +#undef TX_EL_QUEUE_CREATE_INSERT +#undef TX_EL_QUEUE_DELETE_INSERT +#undef TX_EL_QUEUE_FLUSH_INSERT +#undef TX_EL_QUEUE_RECEIVE_INSERT +#undef TX_EL_QUEUE_SEND_INSERT +#undef TX_EL_SEMAPHORE_CREATE_INSERT +#undef TX_EL_SEMAPHORE_DELETE_INSERT +#undef TX_EL_SEMAPHORE_GET_INSERT +#undef TX_EL_SEMAPHORE_PUT_INSERT +#undef TX_EL_THREAD_CREATE_INSERT +#undef TX_EL_THREAD_DELETE_INSERT +#undef TX_EL_THREAD_IDENTIFY_INSERT +#undef TX_EL_THREAD_PREEMPTION_CHANGE_INSERT +#undef TX_EL_THREAD_PRIORITY_CHANGE_INSERT +#undef TX_EL_THREAD_RELINQUISH_INSERT +#undef TX_EL_THREAD_RESUME_INSERT +#undef TX_EL_THREAD_SLEEP_INSERT +#undef TX_EL_THREAD_SUSPEND_INSERT +#undef TX_EL_THREAD_TERMINATE_INSERT +#undef TX_EL_THREAD_TIME_SLICE_CHANGE_INSERT +#undef TX_EL_TIME_GET_INSERT +#undef TX_EL_TIME_SET_INSERT +#undef TX_EL_TIMER_ACTIVATE_INSERT +#undef TX_EL_TIMER_CHANGE_INSERT +#undef TX_EL_TIMER_CREATE_INSERT +#undef TX_EL_TIMER_DEACTIVATE_INSERT +#undef TX_EL_TIMER_DELETE_INSERT +#undef TX_EL_BLOCK_POOL_INFO_GET_INSERT +#undef TX_EL_BLOCK_POOL_PRIORITIZE_INSERT +#undef TX_EL_BYTE_POOL_INFO_GET_INSERT +#undef TX_EL_BYTE_POOL_PRIORITIZE_INSERT +#undef TX_EL_EVENT_FLAGS_INFO_GET_INSERT +#undef TX_EL_MUTEX_CREATE_INSERT +#undef TX_EL_MUTEX_DELETE_INSERT +#undef TX_EL_MUTEX_GET_INSERT +#undef TX_EL_MUTEX_INFO_GET_INSERT +#undef TX_EL_MUTEX_PRIORITIZE_INSERT +#undef TX_EL_MUTEX_PUT_INSERT +#undef TX_EL_QUEUE_INFO_GET_INSERT +#undef TX_EL_QUEUE_FRONT_SEND_INSERT +#undef TX_EL_QUEUE_PRIORITIZE_INSERT +#undef TX_EL_SEMAPHORE_INFO_GET_INSERT +#undef TX_EL_SEMAPHORE_PRIORITIZE_INSERT +#undef TX_EL_THREAD_INFO_GET_INSERT +#undef TX_EL_THREAD_WAIT_ABORT_INSERT +#undef TX_EL_TIMER_INFO_GET_INSERT +#undef TX_EL_BLOCK_POOL_PERFORMANCE_INFO_GET_INSERT +#undef TX_EL_BLOCK_POOL_PERFORMANCE_SYSTEM_INFO_GET_INSERT +#undef TX_EL_BYTE_POOL_PERFORMANCE_INFO_GET_INSERT +#undef TX_EL_BYTE_POOL_PERFORMANCE_SYSTEM_INFO_GET_INSERT +#undef TX_EL_EVENT_FLAGS_PERFORMANCE_INFO_GET_INSERT +#undef TX_EL_EVENT_FLAGS_PERFORMANCE_SYSTEM_INFO_GET_INSERT +#undef TX_EL_EVENT_FLAGS_SET_NOTIFY_INSERT +#undef TX_EL_MUTEX_PERFORMANCE_INFO_GET_INSERT +#undef TX_EL_MUTEX_PERFORMANCE_SYSTEM_INFO_GET_INSERT +#undef TX_EL_QUEUE_PERFORMANCE_INFO_GET_INSERT +#undef TX_EL_QUEUE_PERFORMANCE_SYSTEM_INFO_GET_INSERT +#undef TX_EL_QUEUE_SEND_NOTIFY_INSERT +#undef TX_EL_SEMAPHORE_CEILING_PUT_INSERT +#undef TX_EL_SEMAPHORE_PERFORMANCE_INFO_GET_INSERT +#undef TX_EL_SEMAPHORE_PERFORMANCE_SYSTEM_INFO_GET_INSERT +#undef TX_EL_SEMAPHORE_PUT_NOTIFY_INSERT +#undef TX_EL_THREAD_ENTRY_EXIT_NOTIFY_INSERT +#undef TX_EL_THREAD_RESET_INSERT +#undef TX_EL_THREAD_PERFORMANCE_INFO_GET_INSERT +#undef TX_EL_THREAD_PERFORMANCE_SYSTEM_INFO_GET_INSERT +#undef TX_EL_THREAD_STACK_ERROR_NOTIFY_INSERT +#undef TX_EL_TIMER_PERFORMANCE_INFO_GET_INSERT +#undef TX_EL_TIMER_PERFORMANCE_SYSTEM_INFO_GET_INSERT + + +/* Define Event Types. */ + +#define TX_EL_THREAD_CHANGE 1 +#define TX_EL_INTERRUPT 2 +#define TX_EL_THREADX_CALL 3 +#define TX_EL_USER_EVENT 4 +#define TX_EL_THREAD_STATUS_CHANGE 5 +#define TX_EL_REFRESH 6 /* Not implemented */ +#define TX_EL_TIMER 7 /* Not implemented */ +#define TX_EL_TIMESOURCE_DELTA 8 /* Not implemented */ + + +/* Define TX_EL_THREADX_CALL event sub-types. */ + +#define TX_EL_BYTE_ALLOCATE 0 +#define TX_EL_BYTE_POOL_CREATE 1 +#define TX_EL_BYTE_POOL_DELETE 2 +#define TX_EL_BYTE_RELEASE 3 +#define TX_EL_BLOCK_ALLOCATE 4 +#define TX_EL_BLOCK_POOL_CREATE 5 +#define TX_EL_BLOCK_POOL_DELETE 6 +#define TX_EL_BLOCK_RELEASE 7 +#define TX_EL_EVENT_FLAGS_CREATE 8 +#define TX_EL_EVENT_FLAGS_DELETE 9 +#define TX_EL_EVENT_FLAGS_GET 10 +#define TX_EL_EVENT_FLAGS_SET 11 +#define TX_EL_INTERRUPT_CONTROL 12 +#define TX_EL_QUEUE_CREATE 13 +#define TX_EL_QUEUE_DELETE 14 +#define TX_EL_QUEUE_FLUSH 15 +#define TX_EL_QUEUE_RECEIVE 16 +#define TX_EL_QUEUE_SEND 17 +#define TX_EL_SEMAPHORE_CREATE 18 +#define TX_EL_SEMAPHORE_DELETE 19 +#define TX_EL_SEMAPHORE_GET 20 +#define TX_EL_SEMAPHORE_PUT 21 +#define TX_EL_THREAD_CREATE 22 +#define TX_EL_THREAD_DELETE 23 +#define TX_EL_THREAD_IDENTIFY 24 +#define TX_EL_THREAD_PREEMPTION_CHANGE 25 +#define TX_EL_THREAD_PRIORITY_CHANGE 26 +#define TX_EL_THREAD_RELINQUISH 27 +#define TX_EL_THREAD_RESUME 28 +#define TX_EL_THREAD_SLEEP 29 +#define TX_EL_THREAD_SUSPEND 30 +#define TX_EL_THREAD_TERMINATE 31 +#define TX_EL_THREAD_TIME_SLICE_CHANGE 32 +#define TX_EL_TIME_GET 33 +#define TX_EL_TIME_SET 34 +#define TX_EL_TIMER_ACTIVATE 35 +#define TX_EL_TIMER_CHANGE 36 +#define TX_EL_TIMER_CREATE 37 +#define TX_EL_TIMER_DEACTIVATE 38 +#define TX_EL_TIMER_DELETE 39 +#define TX_EL_BLOCK_POOL_INFO_GET 40 +#define TX_EL_BLOCK_POOL_PRIORITIZE 41 +#define TX_EL_BYTE_POOL_INFO_GET 42 +#define TX_EL_BYTE_POOL_PRIORITIZE 43 +#define TX_EL_EVENT_FLAGS_INFO_GET 44 +#define TX_EL_MUTEX_CREATE 45 +#define TX_EL_MUTEX_DELETE 46 +#define TX_EL_MUTEX_GET 47 +#define TX_EL_MUTEX_INFO_GET 48 +#define TX_EL_MUTEX_PRIORITIZE 49 +#define TX_EL_MUTEX_PUT 50 +#define TX_EL_QUEUE_INFO_GET 51 +#define TX_EL_QUEUE_FRONT_SEND 52 +#define TX_EL_QUEUE_PRIORITIZE 53 +#define TX_EL_SEMAPHORE_INFO_GET 54 +#define TX_EL_SEMAPHORE_PRIORITIZE 55 +#define TX_EL_THREAD_INFO_GET 56 +#define TX_EL_THREAD_WAIT_ABORT 57 +#define TX_EL_TIMER_INFO_GET 58 +#define TX_EL_BLOCK_POOL_PERFORMANCE_INFO_GET 59 +#define TX_EL_BLOCK_POOL_PERFORMANCE_SYSTEM_INFO_GET 60 +#define TX_EL_BYTE_POOL_PERFORMANCE_INFO_GET 61 +#define TX_EL_BYTE_POOL_PERFORMANCE_SYSTEM_INFO_GET 62 +#define TX_EL_EVENT_FLAGS_PERFORMANCE_INFO_GET 63 +#define TX_EL_EVENT_FLAGS_PERFORMANCE_SYSTEM_INFO_GET 64 +#define TX_EL_EVENT_FLAGS_SET_NOTIFY 65 +#define TX_EL_MUTEX_PERFORMANCE_INFO_GET 66 +#define TX_EL_MUTEX_PERFORMANCE_SYSTEM_INFO_GET 67 +#define TX_EL_QUEUE_PERFORMANCE_INFO_GET 68 +#define TX_EL_QUEUE_PERFORMANCE_SYSTEM_INFO_GET 69 +#define TX_EL_QUEUE_SEND_NOTIFY 70 +#define TX_EL_SEMAPHORE_CEILING_PUT 71 +#define TX_EL_SEMAPHORE_PERFORMANCE_INFO_GET 72 +#define TX_EL_SEMAPHORE_PERFORMANCE_SYSTEM_INFO_GET 73 +#define TX_EL_SEMAPHORE_PUT_NOTIFY 74 +#define TX_EL_THREAD_ENTRY_EXIT_NOTIFY 75 +#define TX_EL_THREAD_RESET 76 +#define TX_EL_THREAD_PERFORMANCE_INFO_GET 77 +#define TX_EL_THREAD_PERFORMANCE_SYSTEM_INFO_GET 78 +#define TX_EL_THREAD_STACK_ERROR_NOTIFY 79 +#define TX_EL_TIMER_PERFORMANCE_INFO_GET 80 +#define TX_EL_TIMER_PERFORMANCE_SYSTEM_INFO_GET 81 + + +/* Define ThreadX sub-types. */ + +#define TX_EL_INTERRUPT_SUB_TYPE 1 +#define TX_EL_END_OF_INTERRUPT 3 + + +/* Define event logging filters, which may be used by the application program to + dynamically enable/disable events in run-time. */ + +#define TX_EL_FILTER_STATUS_CHANGE 0x0001 +#define TX_EL_FILTER_INTERRUPTS 0x0002 +#define TX_EL_FILTER_THREAD_CALLS 0x0004 +#define TX_EL_FILTER_TIMER_CALLS 0x0008 +#define TX_EL_FILTER_EVENT_FLAG_CALLS 0x0010 +#define TX_EL_FILTER_SEMAPHORE_CALLS 0x0020 +#define TX_EL_FILTER_QUEUE_CALLS 0x0040 +#define TX_EL_FILTER_BLOCK_CALLS 0x0080 +#define TX_EL_FILTER_BYTE_CALLS 0x0100 +#define TX_EL_FILTER_MUTEX_CALLS 0x0200 +#define TX_EL_FILTER_ALL_EVENTS 0xFFFF +#define TX_EL_ENABLE_ALL_EVENTS 0x0000 + + +/* Define filter macros that are inserted in-line with the other macros below. */ + +#ifdef TX_ENABLE_EVENT_FILTERS +#define TX_EL_NO_STATUS_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_STATUS_CHANGE)) { +#define TX_EL_NO_INTERRUPT_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_INTERRUPTS)) { +#define TX_EL_NO_THREAD_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_THREAD_CALLS)) { +#define TX_EL_NO_TIMER_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_TIMER_CALLS)) { +#define TX_EL_NO_EVENT_FLAG_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_EVENT_FLAG_CALLS)) { +#define TX_EL_NO_SEMAPHORE_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_SEMAPHORE_CALLS)) { +#define TX_EL_NO_QUEUE_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_QUEUE_CALLS)) { +#define TX_EL_NO_BLOCK_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_BLOCK_CALLS)) { +#define TX_EL_NO_BYTE_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_BYTE_CALLS)) { +#define TX_EL_NO_MUTEX_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_MUTEX_CALLS)) { +#define TX_EL_END_FILTER } +#else +#define TX_EL_NO_STATUS_EVENTS +#define TX_EL_NO_INTERRUPT_EVENTS +#define TX_EL_NO_THREAD_EVENTS +#define TX_EL_NO_TIMER_EVENTS +#define TX_EL_NO_EVENT_FLAG_EVENTS +#define TX_EL_NO_SEMAPHORE_EVENTS +#define TX_EL_NO_QUEUE_EVENTS +#define TX_EL_NO_BLOCK_EVENTS +#define TX_EL_NO_BYTE_EVENTS +#define TX_EL_NO_MUTEX_EVENTS +#define TX_EL_END_FILTER +#endif + +/* Define externs and constants for non-event log source modules. This is for + the in-line macros below. */ + +#ifndef TX_EL_SOURCE_CODE +extern UCHAR *_tx_el_tni_start; +extern UCHAR **_tx_el_current_event; +extern UCHAR *_tx_el_event_area_start; +extern UCHAR *_tx_el_event_area_end; +extern UINT _tx_el_maximum_events; +extern ULONG _tx_el_total_events; +extern TX_THREAD *_tx_thread_current_ptr; +extern UINT _tx_el_event_filter; +extern ULONG _tx_el_time_base_upper; +extern ULONG _tx_el_time_base_lower; + + +/* Define macros for event logging functions. */ + +#define TX_EL_THREAD_CREATE_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO4(TX_EL_THREAD_CREATE, thread_ptr, stack_start, stack_size, priority); TX_EL_END_FILTER +#define TX_EL_EVENT_FLAGS_SET_INSERT TX_EL_NO_EVENT_FLAG_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_EVENT_FLAGS_SET, group_ptr, flags_to_set, set_option); TX_EL_END_FILTER +#define TX_EL_THREAD_DELETE_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_DELETE, thread_ptr); TX_EL_END_FILTER +#define TX_EL_THREAD_INFO_GET_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_INFO_GET, thread_ptr); TX_EL_END_FILTER +#define TX_EL_THREAD_TIME_SLICE_CHANGE_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_THREAD_TIME_SLICE_CHANGE, thread_ptr, thread_ptr -> tx_thread_new_time_slice, new_time_slice); TX_EL_END_FILTER +#define TX_EL_THREAD_TERMINATE_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_TERMINATE, thread_ptr); TX_EL_END_FILTER +#define TX_EL_THREAD_SLEEP_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_SLEEP, timer_ticks); TX_EL_END_FILTER +#define TX_EL_THREAD_SUSPEND_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_SUSPEND, thread_ptr); TX_EL_END_FILTER +#define TX_EL_THREAD_RELINQUISH_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_THREAD_RELINQUISH); TX_EL_END_FILTER +#define TX_EL_THREAD_RESUME_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_RESUME, thread_ptr); TX_EL_END_FILTER +#define TX_EL_THREAD_PRIORITY_CHANGE_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_THREAD_PRIORITY_CHANGE, thread_ptr, thread_ptr -> tx_thread_priority, new_priority); TX_EL_END_FILTER +#define TX_EL_THREAD_PREEMPTION_CHANGE_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_THREAD_PREEMPTION_CHANGE, thread_ptr, thread_ptr -> tx_thread_preempt_threshold, new_threshold); TX_EL_END_FILTER +#define TX_EL_THREAD_WAIT_ABORT_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_WAIT_ABORT, thread_ptr); TX_EL_END_FILTER +#define TX_EL_THREAD_ENTRY_EXIT_NOTIFY_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_THREAD_ENTRY_EXIT_NOTIFY, thread_ptr, thread_entry_exit_notify); TX_EL_END_FILTER +#define TX_EL_THREAD_RESET_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_RESET, thread_ptr); TX_EL_END_FILTER +#define TX_EL_THREAD_PERFORMANCE_INFO_GET_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_PERFORMANCE_INFO_GET, thread_ptr); TX_EL_END_FILTER +#define TX_EL_THREAD_PERFORMANCE_SYSTEM_INFO_GET_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_THREAD_PERFORMANCE_SYSTEM_INFO_GET); TX_EL_END_FILTER +#define TX_EL_THREAD_STACK_ERROR_NOTIFY_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_STACK_ERROR_NOTIFY, stack_error_handler); TX_EL_END_FILTER +#define TX_EL_TIME_SET_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_TIME_SET, new_time); TX_EL_END_FILTER +#define TX_EL_TIME_GET_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_TIME_GET, _tx_timer_system_clock); TX_EL_END_FILTER +#define TX_EL_TIMER_DELETE_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_TIMER_DELETE, timer_ptr); TX_EL_END_FILTER +#define TX_EL_TIMER_CREATE_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO4(TX_EL_TIMER_CREATE, timer_ptr, initial_ticks, reschedule_ticks, auto_activate); TX_EL_END_FILTER +#define TX_EL_TIMER_CHANGE_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_TIMER_CHANGE, timer_ptr, initial_ticks, reschedule_ticks); TX_EL_END_FILTER +#define TX_EL_THREAD_IDENTIFY_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_THREAD_IDENTIFY); TX_EL_END_FILTER +#define TX_EL_TIMER_DEACTIVATE_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_TIMER_DEACTIVATE, timer_ptr); TX_EL_END_FILTER +#define TX_EL_TIMER_ACTIVATE_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_TIMER_ACTIVATE, timer_ptr); TX_EL_END_FILTER +#define TX_EL_TIMER_INFO_GET_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_TIMER_INFO_GET, timer_ptr); TX_EL_END_FILTER +#define TX_EL_TIMER_PERFORMANCE_INFO_GET_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_TIMER_PERFORMANCE_INFO_GET, timer_ptr); TX_EL_END_FILTER +#define TX_EL_TIMER_PERFORMANCE_SYSTEM_INFO_GET_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_TIMER_PERFORMANCE_SYSTEM_INFO_GET); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_PUT_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_SEMAPHORE_PUT, semaphore_ptr, semaphore_ptr -> tx_semaphore_count); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_GET_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_SEMAPHORE_GET, semaphore_ptr, semaphore_ptr -> tx_semaphore_count); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_DELETE_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_SEMAPHORE_DELETE, semaphore_ptr); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_CREATE_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_SEMAPHORE_CREATE, semaphore_ptr, initial_count); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_INFO_GET_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_SEMAPHORE_INFO_GET, semaphore_ptr); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_PRIORITIZE_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_SEMAPHORE_PRIORITIZE, semaphore_ptr); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_CEILING_PUT_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_SEMAPHORE_CEILING_PUT, semaphore_ptr, semaphore_ptr -> tx_semaphore_count, ceiling); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_PERFORMANCE_INFO_GET_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_SEMAPHORE_PERFORMANCE_INFO_GET, semaphore_ptr); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_PERFORMANCE_SYSTEM_INFO_GET_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_SEMAPHORE_PERFORMANCE_SYSTEM_INFO_GET); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_PUT_NOTIFY_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_SEMAPHORE_PUT_NOTIFY, semaphore_ptr, semaphore_put_notify); TX_EL_END_FILTER +#define TX_EL_QUEUE_FRONT_SEND_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_QUEUE_FRONT_SEND, queue_ptr, source_ptr); TX_EL_END_FILTER +#define TX_EL_QUEUE_SEND_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_QUEUE_SEND, queue_ptr, source_ptr); TX_EL_END_FILTER +#define TX_EL_QUEUE_RECEIVE_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_QUEUE_RECEIVE, queue_ptr, destination_ptr); TX_EL_END_FILTER +#define TX_EL_QUEUE_FLUSH_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_QUEUE_FLUSH, queue_ptr); TX_EL_END_FILTER +#define TX_EL_QUEUE_DELETE_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_QUEUE_DELETE, queue_ptr); TX_EL_END_FILTER +#define TX_EL_QUEUE_CREATE_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO4(TX_EL_QUEUE_CREATE, queue_ptr, queue_start, queue_size, message_size); TX_EL_END_FILTER +#define TX_EL_QUEUE_INFO_GET_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_QUEUE_INFO_GET, queue_ptr); TX_EL_END_FILTER +#define TX_EL_QUEUE_PRIORITIZE_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_QUEUE_PRIORITIZE, queue_ptr); TX_EL_END_FILTER +#define TX_EL_QUEUE_PERFORMANCE_INFO_GET_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_QUEUE_PERFORMANCE_INFO_GET, queue_ptr); TX_EL_END_FILTER +#define TX_EL_QUEUE_PERFORMANCE_SYSTEM_INFO_GET_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_QUEUE_PERFORMANCE_SYSTEM_INFO_GET); TX_EL_END_FILTER +#define TX_EL_QUEUE_SEND_NOTIFY_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_QUEUE_SEND_NOTIFY, queue_ptr, queue_send_notify); TX_EL_END_FILTER +#define TX_EL_EVENT_FLAGS_GET_INSERT TX_EL_NO_EVENT_FLAG_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_EVENT_FLAGS_GET, group_ptr, requested_flags, get_option); TX_EL_END_FILTER +#define TX_EL_EVENT_FLAGS_DELETE_INSERT TX_EL_NO_EVENT_FLAG_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_EVENT_FLAGS_DELETE, group_ptr); TX_EL_END_FILTER +#define TX_EL_EVENT_FLAGS_CREATE_INSERT TX_EL_NO_EVENT_FLAG_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_EVENT_FLAGS_CREATE, group_ptr); TX_EL_END_FILTER +#define TX_EL_EVENT_FLAGS_INFO_GET_INSERT TX_EL_NO_EVENT_FLAG_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_EVENT_FLAGS_INFO_GET, group_ptr); TX_EL_END_FILTER +#define TX_EL_EVENT_FLAGS_PERFORMANCE_INFO_GET_INSERT TX_EL_NO_EVENT_FLAG_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_EVENT_FLAGS_PERFORMANCE_INFO_GET, group_ptr); TX_EL_END_FILTER +#define TX_EL_EVENT_FLAGS_PERFORMANCE_SYSTEM_INFO_GET_INSERT TX_EL_NO_EVENT_FLAG_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_EVENT_FLAGS_PERFORMANCE_SYSTEM_INFO_GET); TX_EL_END_FILTER +#define TX_EL_EVENT_FLAGS_SET_NOTIFY_INSERT TX_EL_NO_EVENT_FLAG_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_EVENT_FLAGS_SET_NOTIFY, group_ptr, events_set_notify); TX_EL_END_FILTER +#define TX_EL_BYTE_RELEASE_INSERT TX_EL_NO_BYTE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_BYTE_RELEASE, pool_ptr, memory_ptr); TX_EL_END_FILTER +#define TX_EL_BYTE_POOL_DELETE_INSERT TX_EL_NO_BYTE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_BYTE_POOL_DELETE, pool_ptr); TX_EL_END_FILTER +#define TX_EL_BYTE_POOL_CREATE_INSERT TX_EL_NO_BYTE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_BYTE_POOL_CREATE, pool_ptr, pool_start, pool_size); TX_EL_END_FILTER +#define TX_EL_BYTE_POOL_INFO_GET_INSERT TX_EL_NO_BYTE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_BYTE_POOL_INFO_GET, pool_ptr); TX_EL_END_FILTER +#define TX_EL_BYTE_POOL_PRIORITIZE_INSERT TX_EL_NO_BYTE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_BYTE_POOL_PRIORITIZE, pool_ptr); TX_EL_END_FILTER +#define TX_EL_BYTE_ALLOCATE_INSERT TX_EL_NO_BYTE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_BYTE_ALLOCATE, pool_ptr, memory_ptr, memory_size); TX_EL_END_FILTER +#define TX_EL_BYTE_POOL_PERFORMANCE_INFO_GET_INSERT TX_EL_NO_BYTE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_BYTE_POOL_PERFORMANCE_INFO_GET, pool_ptr); TX_EL_END_FILTER +#define TX_EL_BYTE_POOL_PERFORMANCE_SYSTEM_INFO_GET_INSERT TX_EL_NO_BYTE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_BYTE_POOL_PERFORMANCE_SYSTEM_INFO_GET); TX_EL_END_FILTER +#define TX_EL_BLOCK_RELEASE_INSERT TX_EL_NO_BLOCK_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_BLOCK_RELEASE, pool_ptr, block_ptr); TX_EL_END_FILTER +#define TX_EL_BLOCK_POOL_DELETE_INSERT TX_EL_NO_BLOCK_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_BLOCK_POOL_DELETE, pool_ptr); TX_EL_END_FILTER +#define TX_EL_BLOCK_POOL_CREATE_INSERT TX_EL_NO_BLOCK_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO4(TX_EL_BLOCK_POOL_CREATE, pool_ptr, pool_start, pool_size, block_size); TX_EL_END_FILTER +#define TX_EL_BLOCK_POOL_INFO_GET_INSERT TX_EL_NO_BLOCK_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_BLOCK_POOL_INFO_GET, pool_ptr); TX_EL_END_FILTER +#define TX_EL_BLOCK_POOL_PRIORITIZE_INSERT TX_EL_NO_BLOCK_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_BLOCK_POOL_PRIORITIZE, pool_ptr); TX_EL_END_FILTER +#define TX_EL_BLOCK_ALLOCATE_INSERT TX_EL_NO_BLOCK_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_BLOCK_ALLOCATE, pool_ptr, block_ptr); TX_EL_END_FILTER +#define TX_EL_BLOCK_POOL_PERFORMANCE_INFO_GET_INSERT TX_EL_NO_BLOCK_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_BLOCK_POOL_PERFORMANCE_INFO_GET, pool_ptr); TX_EL_END_FILTER +#define TX_EL_BLOCK_POOL_PERFORMANCE_SYSTEM_INFO_GET_INSERT TX_EL_NO_BLOCK_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_BLOCK_POOL_PERFORMANCE_SYSTEM_INFO_GET); TX_EL_END_FILTER +#define TX_EL_MUTEX_CREATE_INSERT TX_EL_NO_MUTEX_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_MUTEX_CREATE, mutex_ptr, inherit); TX_EL_END_FILTER +#define TX_EL_MUTEX_DELETE_INSERT TX_EL_NO_MUTEX_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_MUTEX_DELETE, mutex_ptr); TX_EL_END_FILTER +#define TX_EL_MUTEX_GET_INSERT TX_EL_NO_MUTEX_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_MUTEX_GET, mutex_ptr, mutex_ptr -> tx_mutex_owner, mutex_ptr -> tx_mutex_ownership_count); TX_EL_END_FILTER +#define TX_EL_MUTEX_INFO_GET_INSERT TX_EL_NO_MUTEX_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_MUTEX_INFO_GET, mutex_ptr); TX_EL_END_FILTER +#define TX_EL_MUTEX_PRIORITIZE_INSERT TX_EL_NO_MUTEX_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_MUTEX_PRIORITIZE, mutex_ptr); TX_EL_END_FILTER +#define TX_EL_MUTEX_PUT_INSERT TX_EL_NO_MUTEX_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_MUTEX_PUT, mutex_ptr, mutex_ptr -> tx_mutex_owner, mutex_ptr -> tx_mutex_ownership_count); TX_EL_END_FILTER +#define TX_EL_MUTEX_PERFORMANCE_INFO_GET_INSERT TX_EL_NO_MUTEX_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_MUTEX_PERFORMANCE_INFO_GET, mutex_ptr); TX_EL_END_FILTER +#define TX_EL_MUTEX_PERFORMANCE_SYSTEM_INFO_GET_INSERT TX_EL_NO_MUTEX_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_MUTEX_PERFORMANCE_SYSTEM_INFO_GET); TX_EL_END_FILTER + + +#endif + + +/* Define Event Log function prototypes. */ + +VOID _tx_el_initialize(VOID); +UINT _tx_el_thread_register(TX_THREAD *thread_ptr); +UINT _tx_el_thread_unregister(TX_THREAD *thread_ptr); +VOID _tx_el_user_event_insert(UINT sub_type, ULONG info_1, ULONG info_2, + ULONG info_3, ULONG info_4); +VOID _tx_el_thread_running(TX_THREAD *thread_ptr); +VOID _tx_el_thread_preempted(TX_THREAD *thread_ptr); +VOID _tx_el_interrupt(UINT interrupt_number); +VOID _tx_el_interrupt_end(UINT interrupt_number); +VOID _tx_el_interrupt_control_call(void); +VOID _tx_el_event_log_on(void); +VOID _tx_el_event_log_off(void); +VOID _tx_el_event_filter_set(UINT filter); + + +/* Define macros that are used inside the ThreadX source code. + If event logging is disabled, these macros will be defined + as white space. */ + +#ifdef TX_ENABLE_EVENT_LOGGING +#ifndef TX_NO_EVENT_INFO +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO4(a, b, c, d, e) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_current_ptr;\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_1_OFFSET)) =\ + (ULONG) b;\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_2_OFFSET)) =\ + (ULONG) c;\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_3_OFFSET)) =\ + (ULONG) d;\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_4_OFFSET)) =\ + (ULONG) e;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(a, b, c, d) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_current_ptr;\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_1_OFFSET)) =\ + (ULONG) b;\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_2_OFFSET)) =\ + (ULONG) c;\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_3_OFFSET)) =\ + (ULONG) d;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(a, b, c) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_current_ptr;\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_1_OFFSET)) =\ + (ULONG) b;\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_2_OFFSET)) =\ + (ULONG) c;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(a, b) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_current_ptr;\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_1_OFFSET)) =\ + (ULONG) b;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(a) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_current_ptr;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_THREAD_STATUS_CHANGE_INSERT(a, b) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + TX_EL_NO_STATUS_EVENTS \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREAD_STATUS_CHANGE; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) b; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) a;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + TX_EL_END_FILTER \ + } +#define TX_EL_THREAD_REGISTER(a) \ + _tx_el_thread_register(a); +#define TX_EL_THREAD_UNREGISTER(a) \ + _tx_el_thread_unregister(a); +#define TX_EL_INITIALIZE _tx_el_initialize(); +#else +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO4(a, b, c, d, e) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_current_ptr;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(a, b, c, d) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_current_ptr;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(a, b, c) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_current_ptr;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(a, b) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_current_ptr;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(a) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_current_ptr;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_THREAD_STATUS_CHANGE_INSERT(a, b) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + TX_EL_NO_STATUS_EVENTS \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREAD_STATUS_CHANGE; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) b; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) a;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + TX_EL_END_FILTER \ + } +#define TX_EL_THREAD_REGISTER(a) \ + _tx_el_thread_register(a); +#define TX_EL_THREAD_UNREGISTER(a) \ + _tx_el_thread_unregister(a); +#define TX_EL_INITIALIZE _tx_el_initialize(); +#endif +#else +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO4(a, b, c, d, e) +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(a, b, c, d) +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(a, b, c) +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(a, b) +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(a) +#define TX_EL_THREAD_STATUS_CHANGE_INSERT(a, b) +#define TX_EL_THREAD_REGISTER(a) +#define TX_EL_THREAD_UNREGISTER(a) +#define TX_EL_INITIALIZE +#endif + +#endif + diff --git a/ports/cortex_m7/ghs/inc/tx_ghs.h b/ports/cortex_m7/ghs/inc/tx_ghs.h new file mode 100644 index 00000000..ca976916 --- /dev/null +++ b/ports/cortex_m7/ghs/inc/tx_ghs.h @@ -0,0 +1,77 @@ +/* + * ThreadX C/C++ Library Support + * + * Copyright 1983-2019 Green Hills Software LLC. + * + * This program is the property of Green Hills Software LLC., + * its contents are proprietary information and no part of it + * is to be disclosed to anyone except employees of Green Hills + * Software LLC., or as agreed in writing signed by the President + * of Green Hills Software LLC. + */ + +#ifndef _TX_GHS_H_ +#define _TX_GHS_H_ + +#include +#include +#include +#include + +#if defined(__ghs) && (__GHS_VERSION_NUMBER >= 500) +extern void *__ghs_GetThreadLocalStorageItem(int specifier); + +/* Thread-local storage routines for Green Hills releases 5.x and beyond. + The following specifiers are used when calling + __ghs_GetThreadLocalStorageItem. + + If __ghs_GetThreadLocalStorageItem is customized to + return a per-thread errno value, define the preprocessor symbol + USE_THREAD_LOCAL_ERRNO in ind_errn.c. + */ + +enum __ghs_ThreadLocalStorage_specifier { + __ghs_TLS_asctime_buff, + __ghs_TLS_tmpnam_space, + __ghs_TLS_strtok_saved_pos, + __ghs_TLS_Errno, + __ghs_TLS_gmtime_temp, + __ghs_TLS___eh_globals, + __ghs_TLS_SignalHandlers +}; +#else +/* Thread-local storage routines for Green Hills releases 4.x and 3.x . */ +typedef void (*SignalHandler)(int); + +typedef struct +{ + int Errno; /* errno. */ + SignalHandler SignalHandlers[_SIGMAX]; /* signal() buffer. */ + char tmpnam_space[L_tmpnam]; /* tmpnam(NULL) buffer. */ + char asctime_buff[30]; /* . */ + char *strtok_saved_pos; /* strtok() position. */ + struct tm gmtime_temp; /* gmtime() and localtime() buffer. */ + void *__eh_globals; /* Pointer for C++ exception handling. */ +} ThreadLocalStorage; + +ThreadLocalStorage *GetThreadLocalStorage(void); +#endif + + +void __ghsLock(void); +void __ghsUnlock(void); + +int __ghs_SaveSignalContext(jmp_buf); +void __ghs_RestoreSignalContext(jmp_buf); + +/* prototypes for FILE lock routines. */ +void __ghs_flock_file(void *); +void __ghs_funlock_file(void *); +int __ghs_ftrylock_file(void *); +void __ghs_flock_create(void **); +void __ghs_flock_destroy(void *); + +/* prototype for GHS/ThreadX error shell checking. */ +void __ghs_rnerr(char *errMsg, int stackLevels, int stackTraceDisplay, void *hexVal); + +#endif /* _TX_GHS_H_ */ diff --git a/ports/cortex_m7/ghs/inc/tx_port.h b/ports/cortex_m7/ghs/inc/tx_port.h new file mode 100644 index 00000000..acab31b7 --- /dev/null +++ b/ports/cortex_m7/ghs/inc/tx_port.h @@ -0,0 +1,396 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-M7/GHS */ +/* 6.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include +#include +#include "tx_ghs.h" + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM Cortex-M port. */ + +#define TX_INT_DISABLE 1 /* Disable interrupts */ +#define TX_INT_ENABLE 0 /* Enable interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define constants for Green Hills EventAnalyzer. */ + +/* Define the number of ticks per second. This informs the EventAnalyzer what the timestamps + represent. By default, this is set to 1,000,000 i.e., one tick every microsecond. */ + +#define TX_EL_TICKS_PER_SECOND 1000000 + +/* Define the method of how to get the upper and lower 32-bits of the time stamp. By default, simply + simulate the time-stamp source with a counter. */ + +#define read_tbu() _tx_el_time_base_upper +#define read_tbl() ++_tx_el_time_base_lower + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 VOID * tx_thread_eh_globals; \ + int Errno; /* errno. */ \ + char * strtok_saved_pos; /* strtok() position. */ +#ifndef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#define TX_THREAD_EXTENSION_3 +#else +#define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ + unsigned long long tx_thread_execution_time_last_start; +#endif + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + +#if (__GHS_VERSION_NUMBER >= 500) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) \ + { \ + extern void __tx_cpp_exception_init(TX_THREAD *thread_ptr); \ + __tx_cpp_exception_init(thread_ptr); \ + } +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) \ + { \ + #pragma weak __cpp_exception_init \ + extern void __cpp_exception_init(void **); \ + static void (*const cpp_init_funcp)(void **) = __cpp_exception_init; \ + if (cpp_init_funcp) \ + __cpp_exception_init(&(thread_ptr -> tx_thread_eh_globals)); \ + } +#endif + +#if (__GHS_VERSION_NUMBER >= 500) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) \ + { \ + extern void __tx_cpp_exception_cleanup(TX_THREAD *thread_ptr); \ + __tx_cpp_exception_cleanup(thread_ptr); \ + } +#else +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) \ + { \ + #pragma weak __cpp_exception_cleanup \ + extern void __cpp_exception_cleanup(void **); \ + static void (*const cpp_cleanup_funcp)(void **) = \ + __cpp_exception_cleanup; \ + if (cpp_cleanup_funcp) \ + __cpp_exception_cleanup(&(thread_ptr -> tx_thread_eh_globals)); \ + } +#endif + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define the get system state macro. */ + +#ifndef TX_THREAD_GET_SYSTEM_STATE +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | __MRS(__IPSR)) +#endif + + +/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value + indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h + for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always + zero after initialization for Cortex-M ports. */ + +#ifndef TX_THREAD_SYSTEM_RETURN_CHECK +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#endif + + +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to + prevent early scheduling on Cortex-M parts. */ + +#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + b = __CLZ32(m); \ + b = 31 - b; + +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifdef TX_DISABLE_INLINE + +UINT _tx_thread_interrupt_disable(VOID); +VOID _tx_thread_interrupt_restore(UINT previous_posture); + +#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); + +#define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; + +/* Define ThreadX interrupt lockout and restore macros using + asm macros. */ + +asm int disable_ints(void) +{ +% + MRS r0,PRIMASK + MOV r1,1 + MSR PRIMASK,r1 +%error +} + +asm void restore_ints(int a) +{ +%reg a + MSR PRIMASK,a +%mem a + LDR r0,a + MSR PRIMASK,r0 +%error +} + +#define TX_DISABLE interrupt_save = disable_ints(); + +#define TX_RESTORE restore_ints(interrupt_save); + +#endif + + +/* Define FPU extension for the Cortex-M7. Each is assumed to be called in the context of the executing + thread. These are no longer needed, but are preserved for backward compatibility only. */ + +void tx_thread_fpu_enable(void); +void tx_thread_fpu_disable(void); + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/GHS Version 6.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + + + diff --git a/ports/cortex_m7/ghs/readme_threadx.txt b/ports/cortex_m7/ghs/readme_threadx.txt new file mode 100644 index 00000000..2f0cc0ea --- /dev/null +++ b/ports/cortex_m7/ghs/readme_threadx.txt @@ -0,0 +1,233 @@ + Microsoft's Azure RTOS ThreadX for Cortex-M7 + + Using the Green Hills Software Tools + +1. Open the ThreadX Project Workspace + +In order to build the ThreadX library and the ThreadX demonstration first load +the Azure RTOS Workspace azure_rtos_workspace.gpj, which is located inside the +"example_build" directory. + + +2. Building the ThreadX run-time Library + +Building the ThreadX library is easy; simply select the MULTI project file +tx.gpj and then select the build button. You should now observe the +compilation and assembly of the ThreadX library. This project build produces +the ThreadX library file tx.a. + + +3. Demonstration System + +The ThreadX demonstration is designed to execute under the MULTI environment +on the Green Hills Cortex-M7 simulator. The instructions that follow describe +how to get the ThreadX evaluation running under the MULTI Cortex-M7 simulation +environment. + +Building the demonstration is easy; simply select the MULTI project file +sample_threadx.gpj. At this point, select the "Project Build" button and observe +the compilation, assembly, and linkage of the ThreadX demonstration application. + +After the demonstration is built, invoke the MULTI ARM simulator by selecting +the simulator connection from within the sample_threadx.con connection file. +Once connected to the simulator, select the "Debug" button. You should now +observe the main function of sample_threadx.c. + +You are now ready to execute the ThreadX demonstration system. Select +breakpoints and data watches to observe the execution of the sample_threadx.c +application. + + +4. EventAnalyzer Demonstration + +To build a demonstration system that also logs events for the MULTI EventAnalyzer, +perform the same steps as the regular demo, except build the ThreadX library with +txe.gpj file and use the sample_threadx_el.gpj build file to build the demonstration. +The resulting image will log all system events, which can then be displayed by the +MULTI EventAnalyzer. + + +5. System Initialization + +The system entry point using the Green Hills tools is at the label _start. +This is defined within the crt0.arm file supplied by Green Hills. In addition, +this is where all static and global preset C variable initialization +processing is called from. + +After the Green Hills startup function returns, ThreadX initialization is +called. The main initialization function is _tx_initialize_low_level and +is located in the file tx_initialize_low_level.arm. This function is responsible +for setting up various system data structures, interrupt vectors, and the +periodic timer interrupt source of ThreadX. + +In addition, _tx_initialize_low_level determines where the first available +RAM memory address is located. This address is supplied to tx_application_define. + +By default, the first available RAM memory address is assumed to start at the +beginning of the ThreadX section .free_mem. If changes are made to the +sample_threadx.ld file, the .free_mem section should remain the last allocated +section in the main RAM area. The starting address of this section is passed +to tx_application_define. + + +6. Register Usage and Stack Frames + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have the same stack frame in the Cortex-M7 version of +ThreadX. The top of the suspended thread's stack is pointed to by +tx_thread_stack_ptr in the associated thread control block TX_THREAD. + + +Non-FPU Stack Frame: + + Stack Offset Stack Contents + + 0x00 r4 + 0x04 r5 + 0x08 r6 + 0x0C r7 + 0x10 r8 + 0x14 r9 + 0x18 r10 + 0x1C r11 + 0x20 r0 (Hardware stack starts here!!) + 0x24 r1 + 0x28 r2 + 0x2C r3 + 0x30 r12 + 0x34 lr + 0x38 pc + 0x3C xPSR + +FPU Stack Frame (only interrupted thread with FPU enabled): + + Stack Offset Stack Contents + + 0x00 s0 + 0x04 s1 + 0x08 s2 + 0x0C s3 + 0x10 s4 + 0x14 s5 + 0x18 s6 + 0x1C s7 + 0x20 s8 + 0x24 s9 + 0x28 s10 + 0x2C s11 + 0x30 s12 + 0x34 s13 + 0x38 s14 + 0x3C s15 + 0x40 s16 + 0x44 s17 + 0x48 s18 + 0x4C s19 + 0x50 s20 + 0x54 s21 + 0x58 s22 + 0x5C s23 + 0x60 s24 + 0x64 s25 + 0x68 s26 + 0x6C s27 + 0x70 s28 + 0x74 s29 + 0x78 s30 + 0x7C s31 + 0x80 fpscr + 0x84 r4 + 0x88 r5 + 0x8C r6 + 0x90 r7 + 0x94 r8 + 0x98 r9 + 0x9C r10 (sl) + 0xA0 r11 + 0xA4 r0 (Hardware stack starts here!!) + 0xA8 r1 + 0xAC r2 + 0xB0 r3 + 0xB4 r12 + 0xB8 lr + 0xBC pc + 0xC0 xPSR + + +7. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make ThreadX run faster, you can change the tx.gpj project +to disable debug information and enable the desired optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined before tx_api.h is included. + + +8. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-M7 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +8.1 Vector Area + +The Cortex-M7 vectors start at the label __tx_vectors. The application may modify +the vector area according to its needs. + + +8.2 Managed Interrupts + +A ThreadX managed interrupt is defined below. By following these conventions, the +application ISR is then allowed access to various ThreadX services from the ISR. +Here is the standard template for managed ISRs in ThreadX: + + + .globl __tx_IntHandler +__tx_IntHandler: + PUSH {lr} + BL _tx_thread_context_save + + /* Do interrupt handler work here */ + + B _tx_thread_context_restore + + +9. FPU Support + +By default, FPU support is disabled for each thread. If saving the context of the FPU registers +is needed, the ThreadX library should be re-built with TX_ENABLE_FPU_SUPPORT defined. In addition, +the following API call must be made from the context of the application thread - before +the FPU usage: + +void tx_thread_fpu_enable(void); + +After this API is called in the application, FPU registers will be saved/restored for this thread if it +is preempted via an interrupt. All other suspension of the this thread will not require the FPU registers +to be saved/restored. + +To disable FPU register context saving, simply call the following API: + +void tx_thread_fpu_disable(void); + + + +10. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +05/19/2020 Initial ThreadX version of Cortex-M7/Green Hills port. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_m7/ghs/src/tx_el.c b/ports/cortex_m7/ghs/src/tx_el.c new file mode 100644 index 00000000..e2c39a1d --- /dev/null +++ b/ports/cortex_m7/ghs/src/tx_el.c @@ -0,0 +1,1165 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** ThreadX/GHS Event Log (EL) */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_EL_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_el.h" +#include "string.h" + + +/* Define global variables used to manage the event pool. */ + +UCHAR *_tx_el_tni_start; +UCHAR **_tx_el_current_event; +UCHAR *_tx_el_event_area_start; +UCHAR *_tx_el_event_area_end; +UINT _tx_el_maximum_events; +ULONG _tx_el_total_events; +UINT _tx_el_event_filter; +ULONG _tx_el_time_base_upper; +ULONG _tx_el_time_base_lower; + +extern char __ghsbegin_eventlog[]; +extern char __ghsend_eventlog[]; + +extern TX_THREAD *_tx_thread_current_ptr; +UINT _tx_thread_interrupt_control(UINT new_posture); + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_initialize PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates the Event Log (in the format dictated by the */ +/* GHS Event Analyzer) and sets up various information for subsequent */ +/* operation. The start and end of the Event Log is determined by the */ +/* .eventlog section in the linker control file. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_el_initialize(VOID) +{ + +UCHAR *work_ptr; +UCHAR *read_ptr; +ULONG event_log_size; +UCHAR *end_ptr; +UINT i; + + + /* Clear total event counter. */ + _tx_el_total_events = 0; + + /* Clear event filter. */ + _tx_el_event_filter = 0; + + /* First, pickup the starting and ending address of the Event Log memory. */ + work_ptr = (unsigned char *) __ghsbegin_eventlog; + end_ptr = (unsigned char *) __ghsend_eventlog; + + /* Calculate the event log size. */ + event_log_size = end_ptr - work_ptr; + + /* Subtract off the number of bytes in the header and the TNI area. */ + event_log_size = event_log_size - (TX_EL_HEADER_SIZE + + (TX_EL_TNI_ENTRY_SIZE * TX_EL_TNIS)); + + /* Make sure the event log is evenly divisible by the event size. */ + event_log_size = (event_log_size/TX_EL_EVENT_SIZE) * TX_EL_EVENT_SIZE; + + /* Build the Event Log header. */ + + /* Setup the Event Log Version ID. */ + *((unsigned short *) work_ptr) = (unsigned short) TX_EL_VERSION_ID; + work_ptr = work_ptr + sizeof(unsigned short); + + /* Setup the TNIS (number of thread names) field. */ + *((unsigned short *) work_ptr) = (unsigned short) TX_EL_TNIS; + work_ptr = work_ptr + sizeof(unsigned short); + + /* Setup the EVPS (event pool size) field. */ + *((ULONG *) work_ptr) = event_log_size; + work_ptr = work_ptr + sizeof(ULONG); + + /* Remember the maximum number of events. */ + _tx_el_maximum_events = event_log_size/TX_EL_EVENT_SIZE; + + /* Setup max_events field. */ + *((ULONG *) work_ptr) = _tx_el_maximum_events; + work_ptr = work_ptr + sizeof(ULONG); + + /* Setup the evploc (location of event pool). */ + *((ULONG *) work_ptr) = (ULONG) (((ULONG) __ghsbegin_eventlog) + TX_EL_HEADER_SIZE + + (TX_EL_TNIS * TX_EL_TNI_ENTRY_SIZE)); + work_ptr = work_ptr + sizeof(ULONG); + + /* Save the current event pointer. */ + _tx_el_current_event = (UCHAR **) work_ptr; + + /* Setup event_ptr (pointer to oldest event) field to the start + of the event pool. */ + *_tx_el_current_event = (UCHAR *) (((ULONG) __ghsbegin_eventlog) + TX_EL_HEADER_SIZE + + (TX_EL_TNIS * TX_EL_TNI_ENTRY_SIZE)); + work_ptr = work_ptr + sizeof(ULONG); + + /* Setup tbfreq (the number of ticks in a second) field. */ + *((ULONG *) work_ptr) = TX_EL_TICKS_PER_SECOND; + work_ptr = work_ptr + sizeof(ULONG); + + /* At this point we are pointing at the Thread Name Information (TNI) array. */ + + /* Remember the start of this for future updates. */ + _tx_el_tni_start = work_ptr; + + /* Clear the entire TNI array, this is the initial setting. */ + end_ptr = work_ptr + (TX_EL_TNIS * TX_EL_TNI_ENTRY_SIZE); + memset((void *)work_ptr, 0, (TX_EL_TNIS * TX_EL_TNI_ENTRY_SIZE)); + work_ptr = end_ptr; + + /* At this point, we are pointing at the actual Event Entry area. */ + + /* Remember the start of the actual event log area. */ + _tx_el_event_area_start = work_ptr; + + /* Clear the entire Event area. */ + end_ptr = work_ptr + event_log_size; + memset((void *)work_ptr, 0, event_log_size); + work_ptr = end_ptr; + + /* Save the end pointer for later use. */ + _tx_el_event_area_end = work_ptr; + + /* Setup an entry to resolve all activities from initialization and from + an idle system. */ + work_ptr = _tx_el_tni_start; + read_ptr = (UCHAR *) "Initialization/System Idle"; + i = 0; + while ((i < TX_EL_TNI_NAME_SIZE) && (*read_ptr)) + { + + /* Copy a character of thread's name into TNI area of log. */ + *work_ptr++ = *read_ptr++; + + /* Increment the character count. */ + i++; + } + + /* Determine if a NULL needs to be inserted. */ + if (i < TX_EL_TNI_NAME_SIZE) + { + + /* Yes, insert a NULL into the event log string. */ + *work_ptr = (unsigned char) 0; + } + + /* Setup the thread ID to NULL. */ + *((ULONG *) (_tx_el_tni_start + TX_EL_TNI_THREAD_ID_OFFSET)) = (ULONG) TX_NULL; + + /* Set the valid field to indicate the entry is complete. */ + *((UCHAR *) (_tx_el_tni_start + TX_EL_TNI_VALID_OFFSET)) = (ULONG) TX_EL_VALID_ENTRY; + + /* Clear the time base global variables. */ + _tx_el_time_base_upper = 0; + _tx_el_time_base_lower = 0; +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_thread_register PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers a thread in the event log for future */ +/* display purposes. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SUCCESS Thread was placed in TNI area */ +/* TX_ERROR No more room in the TNI area */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create ThreadX thread create function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _tx_el_thread_register(TX_THREAD *thread_ptr) +{ + +UCHAR *entry_ptr; +UCHAR *work_ptr; +UCHAR *read_ptr; +UINT i; + + + /* First of all, search for a free slot in the TNI area. */ + entry_ptr = _tx_el_tni_start; + i = 0; + while (i < TX_EL_TNIS) + { + + /* Determine if this entry is available. */ + if (*(entry_ptr + TX_EL_TNI_VALID_OFFSET) == TX_EL_INVALID_ENTRY) + break; + + /* Otherwise, increment the associated pointers and indices. */ + i++; + entry_ptr = entry_ptr + TX_EL_TNI_ENTRY_SIZE; + } + + /* Check to see if there were no more valid entries. */ + if (i >= TX_EL_TNIS) + return(TX_EL_NO_MORE_TNI_ROOM); + + /* Otherwise, we have room in the TNI and a valid record. */ + + /* Setup the thread's name. */ + work_ptr = entry_ptr; + read_ptr = (UCHAR *) thread_ptr -> tx_thread_name; + i = 0; + while ((i < TX_EL_TNI_NAME_SIZE) && (*read_ptr)) + { + + /* Copy a character of thread's name into TNI area of log. */ + *work_ptr++ = *read_ptr++; + + /* Increment the character count. */ + i++; + } + + /* Determine if a NULL needs to be inserted. */ + if (i < TX_EL_TNI_NAME_SIZE) + { + + /* Yes, insert a NULL into the event log string. */ + *work_ptr = (unsigned char) 0; + } + + /* Setup the thread ID. */ + *((ULONG *) (entry_ptr + TX_EL_TNI_THREAD_ID_OFFSET)) = (ULONG) thread_ptr; + + /* Setup the thread priority. */ + *((ULONG *) (entry_ptr + TX_EL_TNI_THREAD_PRIORITY_OFF)) = (ULONG) thread_ptr -> tx_thread_priority; + + /* Set the valid field to indicate the entry is complete. */ + *((UCHAR *) (entry_ptr + TX_EL_TNI_VALID_OFFSET)) = (ULONG) TX_EL_VALID_ENTRY; + + /* Thread name has been registered. */ + return(TX_SUCCESS); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_thread_unregister PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function unregisters a thread in the event log for future */ +/* display purposes. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SUCCESS Thread was placed in TNI area */ +/* TX_ERROR No more room in the TNI area */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create ThreadX thread create function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _tx_el_thread_unregister(TX_THREAD *thread_ptr) +{ + +UCHAR *entry_ptr; +UCHAR *work_ptr; +UCHAR *read_ptr; +UINT found; +UINT i, j; + + + /* First of all, search for a match in the TNI area. */ + entry_ptr = _tx_el_tni_start; + i = 0; + while (i < TX_EL_TNIS) + { + + /* Determine if this entry is a match. */ + work_ptr = entry_ptr; + read_ptr = (UCHAR *) thread_ptr -> tx_thread_name; + found = TX_TRUE; + j = 0; + do + { + + /* Determine if this character is the same. */ + if (*work_ptr != *read_ptr) + { + + /* Set found to false and fall out of the loop. */ + found = TX_FALSE; + break; + } + else if (*work_ptr == 0) + { + + /* Null terminated, just break the loop. */ + break; + } + else + { + + /* Copy a character of thread's name into TNI area of log. */ + *work_ptr++ = *read_ptr++; + } + + /* Increment the character count. */ + j++; + + } while(j < TX_EL_TNIS); + + + /* Was a match found? */ + if (found) + { + + /* Yes, mark the entry as available now. */ + *(entry_ptr + TX_EL_TNI_VALID_OFFSET) = TX_EL_INVALID_ENTRY; + + /* Get out of the loop! */ + break; + } + + /* Otherwise, increment the associated pointers and indices. */ + i++; + entry_ptr = entry_ptr + TX_EL_TNI_ENTRY_SIZE; + } + + /* Determine status to return. */ + if (found) + return(TX_SUCCESS); + else + return(TX_EL_NAME_NOT_FOUND); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_user_event_insert PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function inserts a user event into the event log. */ +/* If the event log is full, the oldest event is overwritten. */ +/* */ +/* INPUT */ +/* */ +/* sub_type Event subtype for kernel call */ +/* info_1 First information field */ +/* info_2 Second information field */ +/* info_3 Third information field */ +/* info_4 Fourth information field */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX services */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_el_user_event_insert(UINT sub_type, ULONG info_1, ULONG info_2, + ULONG info_3, ULONG info_4) +{ + +TX_INTERRUPT_SAVE_AREA + +UINT upper_tb; +UCHAR *entry_ptr; + + /* Disable interrupts. */ + TX_DISABLE + + /* Increment total event counter. */ + _tx_el_total_events++; + + /* Setup working entry pointer first. */ + entry_ptr = *_tx_el_current_event; + + /* Store the event type. */ + *((unsigned short *) entry_ptr) = (unsigned short) TX_EL_USER_EVENT; + + /* Store the event subtype. */ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = + (unsigned short) sub_type; + + /* Get time stamp. */ + do + { + + /* Pickup the upper tb. */ + upper_tb = (ULONG) read_tbu(); + + /* Store the upper time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = + (ULONG) upper_tb; + + /* Store the lower time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) = + (ULONG) read_tbl(); + } while (upper_tb != (ULONG) read_tbu()); + + /* Store the current thread. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) = + (ULONG) _tx_thread_current_ptr; + + /* Store the first info field. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_1_OFFSET)) = + (ULONG) info_1; + + /* Store the second info field. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_2_OFFSET)) = + (ULONG) info_2; + + /* Store the third info field. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_3_OFFSET)) = + (ULONG) info_3; + + /* Store the fourth info field. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_4_OFFSET)) = + (ULONG) info_4; + + /* Now move the current event log pointer. */ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE; + + /* Check for a wraparound condition. */ + if (entry_ptr >= _tx_el_event_area_end) + { + + /* Yes, we have wrapped around to the end of the event area. + Start back at the top! */ + entry_ptr = _tx_el_event_area_start; + } + + /* Write the entry pointer back into the header. */ + *_tx_el_current_event = entry_ptr; + + /* Restore interrupts. */ + TX_RESTORE +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_thread_running PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function inserts a thread change event into the event */ +/* log, which indicates that a context switch is taking place. */ +/* If the event log is full, the oldest event is overwritten. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread being */ +/* scheduled */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_schedule ThreadX scheduler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_el_thread_running(TX_THREAD *thread_ptr) +{ + +UINT upper_tb; +UCHAR *entry_ptr; + + TX_EL_NO_STATUS_EVENTS + + /* Increment total event counter. */ + _tx_el_total_events++; + + /* Setup working entry pointer first. */ + entry_ptr = *_tx_el_current_event; + + /* Store the event type. */ + *((unsigned short *) entry_ptr) = (unsigned short) TX_EL_THREAD_CHANGE; + + /* Store the event subtype. */ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = + (unsigned short) 0; + + /* Get time stamp. */ + do + { + + /* Pickup the upper tb. */ + upper_tb = (ULONG) read_tbu(); + + /* Store the upper time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = + (ULONG) upper_tb; + + /* Store the lower time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) = + (ULONG) read_tbl(); + } while (upper_tb != (ULONG) read_tbu()); + + /* Store the current thread. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) = + (ULONG) thread_ptr; + + /* Now move the current event log pointer. */ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE; + + /* Check for a wraparound condition. */ + if (entry_ptr >= _tx_el_event_area_end) + { + + /* Yes, we have wrapped around to the end of the event area. + Start back at the top! */ + entry_ptr = _tx_el_event_area_start; + } + + /* Write the entry pointer back into the header. */ + *_tx_el_current_event = entry_ptr; + + TX_EL_END_FILTER +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_thread_preempted PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function inserts a thread preempted event into the event */ +/* log, which indicates that an interrupt occurred that made a higher */ +/* priority thread ready for execution. In this case, the previously */ +/* executing thread has an event entered to indicate it is no longer */ +/* running. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread being */ +/* scheduled */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_context_restore ThreadX context restore */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_el_thread_preempted(TX_THREAD *thread_ptr) +{ + +UINT upper_tb; +UCHAR *entry_ptr; + + + TX_EL_NO_STATUS_EVENTS + + /* Increment total event counter. */ + _tx_el_total_events++; + + /* Setup working entry pointer first. */ + entry_ptr = *_tx_el_current_event; + + /* Store the event type. */ + *((unsigned short *) entry_ptr) = (unsigned short) TX_EL_THREAD_STATUS_CHANGE; + + /* Store the event subtype. */ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = + (unsigned short) TX_READY; + + /* Get time stamp. */ + do + { + + /* Pickup the upper tb. */ + upper_tb = (ULONG) read_tbu(); + + /* Store the upper time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = + (ULONG) upper_tb; + + /* Store the lower time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) = + (ULONG) read_tbl(); + } while (upper_tb != (ULONG) read_tbu()); + + /* Store the current thread. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) = + (ULONG) _tx_thread_current_ptr; + + /* Now move the current event log pointer. */ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE; + + /* Check for a wraparound condition. */ + if (entry_ptr >= _tx_el_event_area_end) + { + + /* Yes, we have wrapped around to the end of the event area. + Start back at the top! */ + entry_ptr = _tx_el_event_area_start; + } + + /* Write the entry pointer back into the header. */ + *_tx_el_current_event = entry_ptr; + + TX_EL_END_FILTER +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_interrupt PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function inserts an interrupt event into the log, which */ +/* indicates the start of interrupt processing for the specific */ +/* */ +/* INPUT */ +/* */ +/* interrupt_number Interrupt number supplied by */ +/* ISR */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISR processing */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_el_interrupt(UINT interrupt_number) +{ + +UINT upper_tb; +UCHAR *entry_ptr; + + + TX_EL_NO_INTERRUPT_EVENTS + + /* Increment total event counter. */ + _tx_el_total_events++; + + /* Setup working entry pointer first. */ + entry_ptr = *_tx_el_current_event; + + /* Store the event type. */ + *((unsigned short *) entry_ptr) = (unsigned short) TX_EL_INTERRUPT; + + /* Store the event subtype. */ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = + (unsigned short) TX_EL_INTERRUPT_SUB_TYPE; + + /* Get time stamp. */ + do + { + + /* Pickup the upper tb. */ + upper_tb = (ULONG) read_tbu(); + + /* Store the upper time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = + (ULONG) upper_tb; + + /* Store the lower time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) = + (ULONG) read_tbl(); + } while (upper_tb != (ULONG) read_tbu()); + + /* Store the current thread. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) = + (ULONG) _tx_thread_current_ptr; + + /* Store the first info word. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_1_OFFSET)) = + (ULONG) interrupt_number; + + /* Now move the current event log pointer. */ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE; + + /* Check for a wraparound condition. */ + if (entry_ptr >= _tx_el_event_area_end) + { + + /* Yes, we have wrapped around to the end of the event area. + Start back at the top! */ + entry_ptr = _tx_el_event_area_start; + } + + /* Write the entry pointer back into the header. */ + *_tx_el_current_event = entry_ptr; + + TX_EL_END_FILTER +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_interrupt_end PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function inserts an interrupt end event into the log, which */ +/* indicates the end of interrupt processing for the specific */ +/* */ +/* INPUT */ +/* */ +/* interrupt_number Interrupt number supplied by */ +/* ISR */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISR processing */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_el_interrupt_end(UINT interrupt_number) +{ + +UINT upper_tb; +UCHAR *entry_ptr; + + + TX_EL_NO_INTERRUPT_EVENTS + + /* Increment total event counter. */ + _tx_el_total_events++; + + /* Setup working entry pointer first. */ + entry_ptr = *_tx_el_current_event; + + /* Store the event type. */ + *((unsigned short *) entry_ptr) = (unsigned short) TX_EL_INTERRUPT; + + /* Store the event subtype. */ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = + (unsigned short) TX_EL_END_OF_INTERRUPT; + + /* Get time stamp. */ + do + { + + /* Pickup the upper tb. */ + upper_tb = (ULONG) read_tbu(); + + /* Store the upper time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = + (ULONG) upper_tb; + + /* Store the lower time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) = + (ULONG) read_tbl(); + } while (upper_tb != (ULONG) read_tbu()); + + /* Store the current thread. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) = + (ULONG) _tx_thread_current_ptr; + + /* Store the first info word. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_1_OFFSET)) = + (ULONG) interrupt_number; + + /* Now move the current event log pointer. */ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE; + + /* Check for a wraparound condition. */ + if (entry_ptr >= _tx_el_event_area_end) + { + + /* Yes, we have wrapped around to the end of the event area. + Start back at the top! */ + entry_ptr = _tx_el_event_area_start; + } + + /* Write the entry pointer back into the header. */ + *_tx_el_current_event = entry_ptr; + + TX_EL_END_FILTER +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_interrupt_control PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function remaps the tx_interrupt_control service call so that */ +/* it can be tracked in the event log. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt posture */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_interrupt_control Interrupt control service */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX services */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _tx_el_interrupt_control(UINT new_posture) +{ + +TX_INTERRUPT_SAVE_AREA +UINT old_posture; + + + TX_EL_NO_INTERRUPT_EVENTS + + TX_DISABLE + TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_INTERRUPT_CONTROL, _tx_thread_current_ptr, new_posture) + TX_RESTORE + + TX_EL_END_FILTER + + old_posture = _tx_thread_interrupt_control(new_posture); + return(old_posture); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_event_log_on PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function disables all event filters. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_el_event_log_on(void) +{ + + /* Disable all event filters. */ + _tx_el_event_filter = TX_EL_ENABLE_ALL_EVENTS; +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_event_log_off PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets all event filters, thereby turning event */ +/* logging off. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_el_event_log_off(void) +{ + + /* Set all event filters. */ + _tx_el_event_filter = TX_EL_FILTER_ALL_EVENTS; +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_event_log_set PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets the events filters specified by the user. */ +/* */ +/* INPUT */ +/* */ +/* filter Events to filter */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_el_event_filter_set(UINT filter) +{ + + /* Apply the user event filter. */ + _tx_el_event_filter = filter; +} + diff --git a/ports/cortex_m7/ghs/src/tx_ghs.c b/ports/cortex_m7/ghs/src/tx_ghs.c new file mode 100644 index 00000000..0be9d715 --- /dev/null +++ b/ports/cortex_m7/ghs/src/tx_ghs.c @@ -0,0 +1,485 @@ +/* + * ThreadX C/C++ Library Support + * + * Copyright 1983-2019 Green Hills Software LLC. + * + * This program is the property of Green Hills Software LLC., + * its contents are proprietary information and no part of it + * is to be disclosed to anyone except employees of Green Hills + * Software LLC., or as agreed in writing signed by the President + * of Green Hills Software LLC. + */ + +#include "tx_ghs.h" +#ifndef TX_DISABLE_ERROR_CHECKING +#define TX_DISABLE_ERROR_CHECKING +#endif +#include "tx_api.h" +#include +#include + +/* Allow these routines to access the following ThreadX global variables. */ +extern ULONG _tx_thread_created_count; +extern TX_THREAD *_tx_thread_created_ptr; +extern TX_THREAD *_tx_thread_current_ptr; + +#if defined(__ghs) && (__GHS_VERSION_NUMBER >= 500) +/* Thread-local storage routines for Green Hills releases 5.x and above. */ +/* + Thread-Local (Per-Thread) Library Data Retrieval + ================================================ + + __ghs_ThreadLocalStorage_specifier defines all library data items + that the Green Hills libraries allow to be allocated per-thread. + + An implementation can choose which of these data items to allocate + for each thread. For example, an implementation may choose to + allocate an errno value for each thread, but not the strtok_saved_pos + pointer. The application could then use strtok_r instead of strtok for + correct operation. + + To add per-thread library data, define one of the + TX_THREAD_EXTENSION_* macros in tx_port.h to include the data item + or items in each thread control block TX_THREAD. + + If C++ with exceptions is being used, the __eh_globals entry must be + allocated for each thread. This is typically done by default using + TX_THREAD_EXTENSION_1 in tx_port.h. + + If __ghs_GetThreadLocalStorageItem is customized to return a + per-thread errno value, you should also: + + * Customize the System Library for your project + * Define the preprocessor symbol USE_THREAD_LOCAL_ERRNO in + src/libsys/ind_errn.c + + If you customize the System Library, you should remove ind_thrd.c + from the libsys.gpj subproject. + + */ + +/* Provide global __eh_globals value to support C++ exception handling + outside a thread context. This name also forces this module to be + included in the linked program instead of the ind_thrd.o module from + the System Library libsys.a. + */ +static void *__eh_globals; + +#pragma ghs startnomisra +void *__ghs_GetThreadLocalStorageItem(int specifier) +{ + void *ptlsitem = (void *)0; + switch (specifier) { + case (int)__ghs_TLS_Errno: + /* Set ptslsitem to the address of the per-thread errno value. + The per-thread errno value should have the type int. + + If returning a per-thread errno value, follow the steps + above. + + This item is used by numerous library functions. + */ + break; + case (int)__ghs_TLS_SignalHandlers: + /* Set ptslsitem to the address of the per-thread SignalHandlers + array. The per-thread SignalHandlers array should have the + array type as in the following declaration: + SignalHandler SignalHandlers[_SIGMAX]; + The SignalHandler type and _SIGMAX constant are defined in + ind_thrd.h. + + This item is used by the library functions signal() and + raise(). + */ + break; + case (int)__ghs_TLS_asctime_buff: + /* Set ptslsitem to the address of the per-thread asctime_buff + array. The per-thread asctime_buff array should have the + array type as in the following declaration: + char asctime_buff[30]; + + This item is used by the library functions asctime() and + ctime(). The library provides asctime_r() and ctime_r(), + inherently thread-safe versions of these functions. + */ + break; + case (int)__ghs_TLS_tmpnam_space: + /* Set ptslsitem to the address of the per-thread tmpnam_space + array. The per-thread tmpnam_space array should have the + array type as in the following declaration: + char tmpnam_space[L_tmpnam]; + The constant is defined in + + This item is used by the library function tmpnam() when + passed NULL. The library provides tmpnam_r(), an + inherently thread-safe version of tmpnam(). + */ + break; + case (int)__ghs_TLS_strtok_saved_pos: + /* Set ptslsitem to the address of the per-thread + strtok_saved_pos pointer. The per-thread strtok_saved_pos + pointer should have the type "char *". + + This item is used by the library function strtok(). + The library provides strtok_r(), an inherently thread-safe + version of strtok(). + */ + break; + case (int)__ghs_TLS_gmtime_temp: + /* Set ptslsitem to the address of the per-thread gmtime_temp + value. The per-thread gmtime_temp value should have the + type "struct tm" defined in time.h, included by indos.h. + + This item is used by the library functions gmtime() and + localtime(). The library provides gmtime_r() and + localtime_r(), inherently thread-safe versions of these + functions. + */ + break; + case (int)__ghs_TLS___eh_globals: + /* Set ptslsitem to the address of the per-thread __eh_globals + value. The per-thread __eh_globals value should have the + type "void *". + + This item is used by C++ exception handling. + */ + if (_tx_thread_current_ptr) + ptlsitem = (void *)&(_tx_thread_current_ptr->tx_thread_eh_globals); + else + /* Use the global __eh_globals pointer. */ + ptlsitem = (void *)&__eh_globals; + break; + } + return ptlsitem; +} +#pragma ghs endnomisra +#else +/* Thread-local storage routines for Green Hills releases 4.x and 3.x . */ + +/* + * ThreadX C and C++ thread-safe library support routines. + * + * This implementation merely tries to guarantee thread safety within + * individual C library calls such as malloc() and free(), but it does + * not attempt to solve the problems associated with the following + * multithreaded issues: + * + * 1. Use of errno. This can be made thread-safe by adding errno + * to TX_THREAD_PORT_EXTENSION and using that within a modified + * version of libsys/ind_errno.c. + * + * 2. Thread safety ACROSS library calls. Certain C library calls either + * return pointers to statically-allocated data structures or maintain + * state across calls. These include strtok(), asctime(), gmtime(), + * tmpnam(NULL), signal(). To make such C library routines thread-safe + * would require adding a ThreadLocalStorage struct to the thread control + * block TX_THREAD. Since relatively few applications make use of these + * library routines, the implementation provided here uses a single, global + * ThreadLocalStorage data structure rather than greatly increasing the size + * of the thread control block TX_THREAD. + * + * The ThreadX global variable _tx_thread_current_ptr points to the + * current thread's control block TX_THREAD. If a ThreadLocalStorage struct + * called tx_tls is placed in TX_THREAD, the function GetThreadLocalStorage + * should be modified to return &(_tx_thread_current_ptr->tx_tls). + */ + +static ThreadLocalStorage GlobalTLS; + +ThreadLocalStorage *GetThreadLocalStorage() +{ + return &GlobalTLS; +} +#endif + +/* + * Use a global ThreadX mutex to implement thread safety within C and C++ + * library routines. + * + */ +TX_MUTEX __ghLockMutex; + +/* + * Acquire general lock. Blocks until the lock becomes available. + * Use tx_mutex_get to implement __ghsLock + */ +void __ghsLock(void) +{ + tx_mutex_get(&__ghLockMutex, TX_WAIT_FOREVER); +} + +/* + * Release general lock + * Use tx_mutex_put to implement __ghsUnlock + */ +void __ghsUnlock(void) +{ + tx_mutex_put(&__ghLockMutex); +} + +/* ThreadX Initialization function prototype. */ +void _tx_initialize_kernel_setup(void); + +void __gh_lock_init(void) +{ + /* Initialize the low-level portions of ThreadX. */ + _tx_initialize_kernel_setup(); + + /* Create the global thread lock mutex. */ + tx_mutex_create(&__ghLockMutex, "__ghLockMutex", TX_NO_INHERIT); +} + +/* + Saving State Across setjmp() Calls + ================================== + + These routines can be used to save and restore arbitrary state + across calls to setjmp() and longjmp(). +*/ +int __ghs_SaveSignalContext(jmp_buf jmpbuf) +{ + return 0; +} + +/* Restore arbitrary state across a longjmp() */ +void __ghs_RestoreSignalContext(jmp_buf jmpbuf) +{ +} + +#if defined(__GHS_VERSION_NUMBER) && (__GHS_VERSION_NUMBER < 560) +/* + C++ Exception Handling + ====================== + + These routines allow C++ exceptions to be used in multiple threads. + The default implementation uses __ghs_GetThreadLocalStorageItem + to return a thread-specific __eh_globals pointer. + +*/ + +/* Must be called after __cpp_exception_init() is called to allocate + * and initialize the per-thread exception handling structure */ +void *__get_eh_globals(void) +{ +#if defined(__ghs) && (__GHS_VERSION_NUMBER >= 500) + return *(void **)__ghs_GetThreadLocalStorageItem(__ghs_TLS___eh_globals); +#else + if (_tx_thread_current_ptr) + + /* Return thread-specific __eh_globals pointer. */ + return _tx_thread_current_ptr->tx_thread_eh_globals; + else + /* Return the global __eh_globals pointer. */ + return GlobalTLS.__eh_globals; +#endif +} +#endif + +#if defined(__ghs) && (__GHS_VERSION_NUMBER >= 500) +#pragma weak __cpp_exception_init +extern void __cpp_exception_init(void **); +#pragma weak __cpp_exception_cleanup +extern void __cpp_exception_cleanup(void **); + +/* __tx_cpp_exception_init retrieves the eh_globals field from + thread-local storage and calls __cpp_exception_init. + */ +void __tx_cpp_exception_init(TX_THREAD *thread_ptr) { + void **peh_globals; + if(__cpp_exception_init) { + if (thread_ptr) + peh_globals = &(thread_ptr->tx_thread_eh_globals); + else + /* Use the global __eh_globals pointer. */ + peh_globals = &__eh_globals; + __cpp_exception_init(peh_globals); + } +} + +/* __tx_cpp_exception_cleanup retrieves the eh_globals field from + thread-local storage and calls __cpp_exception_cleanup. + */ +void __tx_cpp_exception_cleanup(TX_THREAD *thread_ptr) { + void **peh_globals; + if(__cpp_exception_cleanup) { + if (thread_ptr) + peh_globals = &(thread_ptr->tx_thread_eh_globals); + else + /* Use the global __eh_globals pointer. */ + peh_globals = &__eh_globals; + __cpp_exception_cleanup(peh_globals); + } +} + +/* __ghs_cpp_exception_init is called from ind_crt1.o to initialize + exceptions for the global context. + */ +void __ghs_cpp_exception_init() { + __tx_cpp_exception_init((void *)0); +} + +/* __ghs_cpp_exception_cleanup is called from ind_exit.o to clean up + exceptions for the global context. + */ +void __ghs_cpp_exception_cleanup(TX_THREAD *thread_ptr) { + __tx_cpp_exception_cleanup((void *)0); +} +#endif + + +/* + File Locks + ====================== + + These routines can be customized to implement per-file locks to allow + thread-safe I/O. + +*/ + +/* Acquire lock for FILE *addr */ +void __ghs_flock_file(void *addr) +{ + tx_mutex_get((TX_MUTEX *)addr, TX_WAIT_FOREVER); +} + +/* Release lock for FILE *addr */ +void __ghs_funlock_file(void *addr) +{ + tx_mutex_put((TX_MUTEX *)addr); +} + +/* Non blocking acquire lock for FILE *addr. May return -1 if */ +/* not implemented. Returns 0 on success and nonzero otherwise. */ +int __ghs_ftrylock_file(void *addr) +{ + return -1; +} + +/* Calls to initialize local lock data structures before they */ +/* are used. */ +void __ghs_flock_create(void **addr) +{ + *addr = (void *)(&__ghLockMutex); +} +void __ghs_flock_destroy(void *addr) {} + + +/* + * ThreadX Peak Stack Checking support routines. + * + * All of these routines are called by MULTI's ThreadX-aware debugging + * package to determine the peak stack use for one thread or for all threads. + * + * These routines are included in this file in order to guarantee that they will + * be available while debugging with MULTI. These routines are not referenced by + * any other part of the ThreadX system. + * + * _txs_thread_stack_check: return the peak stack usage for a thread. + * + * _txs_thread_stack_check_2: store the peak stack usage for all threads + * in the tx_thread_stack_size field of each thread + * control block, TX_THREAD. This routine takes + * advantage of the redundancy within the TX_THREAD + * structure since tx_thread_stack_size can be computed + * from the tx_thread_stack_start and tx_thread_stack_end + * fields of TX_THREAD. + * + * _txs_thread_stack_check_2_fixup: clean up from the _txs_thread_stack_check_2 + * call by computing the stack size for each + * thread and storing the result in the + * tx_thread_stack_size field of each thread control + * block TX_THREAD. + * + * These three routines do not support architectures such as i960 or StarCore + * where the stack grows up instead of down. + * + */ +#ifndef TX_DISABLE_STACK_CHECKING + +ULONG _txs_thread_stack_check(TX_THREAD *thread_ptr) +{ + CHAR *cp; /* Pointer inside thread's stack. */ + + /* Search through the thread's stack to find the highest address modified. */ + for ( cp = (CHAR *)thread_ptr->tx_thread_stack_start; + cp <= (CHAR *)thread_ptr->tx_thread_stack_end; ++cp ) { + + /* Check if this byte in the stack contains something other than TX_STACK_FILL. */ + if (*cp != (char)TX_STACK_FILL) { + + /* Assume cp points to the locating marking the peak stack use. + Return the number of bytes from cp up to and including the + end of the stack. */ + return (((ULONG)thread_ptr->tx_thread_stack_end) - (ULONG)cp + 1); + } + } + return thread_ptr->tx_thread_stack_size; +} + + +int _txs_thread_stack_check_2(void) { + CHAR * cp; /* Pointer inside thread's stack. */ + TX_THREAD * tp; /* Pointer to each thread. */ + + /* If no threads are created, return immediately. */ + if (!_tx_thread_created_count) + return 0; + + /* Start iterating through the threads in the system. Assume that we always + have at least one thread (the system timer thread) in the system. */ + tp = _tx_thread_created_ptr; + + do { + + /* Search through the thread's stack to find the highest address modified. */ + for ( cp = (CHAR *)tp->tx_thread_stack_start; cp <= (CHAR *)tp->tx_thread_stack_end; + ++cp ) { + + /* Check if this byte in the stack contains something other than TX_STACK_FILL. */ + if (*cp != (char)TX_STACK_FILL) { + + /* Assume cp points to the locating marking the peak stack use. + Store the number of bytes from cp up to and including the + end of the stack in the tx_thread_stack_size field. */ + tp->tx_thread_stack_size = ((ULONG)tp->tx_thread_stack_end) - (ULONG)cp + 1; + break; + } + + } + + /* Continue with the next thread. */ + tp = tp->tx_thread_created_next; + + /* Loop until we point to the first thread again. */ + } while ( tp != _tx_thread_created_ptr ); + + return 0; +} + +int _txs_thread_stack_check_2_fixup(void) { + TX_THREAD * tp; /* Pointer to each thread. */ + + /* If no threads are created, return immediately. */ + if (!_tx_thread_created_count) + return 0; + + /* Start iterating through the threads in the system. Assume that we always + have at least one thread (the system timer thread) in the system. */ + tp = _tx_thread_created_ptr; + + do { + + /* Compute the tx_thread_stack_size field by using the tx_thread_stack_end and + tx_thread_stack_start fields. */ + tp->tx_thread_stack_size = (ULONG)tp->tx_thread_stack_end-(ULONG)tp->tx_thread_stack_start+1; + + /* Continue with the next thread. */ + tp = tp->tx_thread_created_next; + + /* Loop until we point to the first thread again. */ + } while ( tp != _tx_thread_created_ptr ); + + return 0; +} + +#endif /* TX_DISABLE_STACK_CHECKING */ diff --git a/ports/cortex_m7/ghs/src/tx_ghse.c b/ports/cortex_m7/ghs/src/tx_ghse.c new file mode 100644 index 00000000..6369df77 --- /dev/null +++ b/ports/cortex_m7/ghs/src/tx_ghse.c @@ -0,0 +1,49 @@ +/* + * ThreadX C++ Library Support + * + * Copyright 1983-2019 Green Hills Software LLC. + * + * This program is the property of Green Hills Software LLC., + * its contents are proprietary information and no part of it + * is to be disclosed to anyone except employees of Green Hills + * Software LLC., or as agreed in writing signed by the President + * of Green Hills Software LLC. + */ +#include "tx_ghs.h" +#ifndef TX_DISABLE_ERROR_CHECKING +#define TX_DISABLE_ERROR_CHECKING +#endif +#include "tx_api.h" + +/* + C++ Exception Handling + ====================== + + These routines allow C++ exceptions to be used in multiple threads. + The default implementation uses __ghs_GetThreadLocalStorageItem + to return a thread-specific __eh_globals pointer. + +*/ + +#if defined(__ghs) && (__GHS_VERSION_NUMBER >= 560) +#ifdef _WIN32 +/* Windows uses a different linker, so include a stub routine, never called, + to pull in __cpp_exception_init and __cpp_exception_cleanup */ +extern void __cpp_exception_init(void **); +extern void __cpp_exception_cleanup(void **); +void __tx_win32_pull_in_exceptions(void) { + __cpp_exception_init(0); + __cpp_exception_cleanup(0); +} +#else +#pragma ghs reference __cpp_exception_init +#pragma ghs reference __cpp_exception_cleanup +#endif + +/* Must be called after __cpp_exception_init() is called to allocate + * and initialize the per-thread exception handling structure */ +void *__get_eh_globals(void) +{ + return *(void **)__ghs_GetThreadLocalStorageItem(__ghs_TLS___eh_globals); +} +#endif diff --git a/ports/cortex_m7/ghs/src/tx_thread_context_restore.arm b/ports/cortex_m7/ghs/src/tx_thread_context_restore.arm new file mode 100644 index 00000000..0c148254 --- /dev/null +++ b/ports/cortex_m7/ghs/src/tx_thread_context_restore.arm @@ -0,0 +1,87 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + .text + .align 4 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-M7/GHS */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* [_tx_execution_isr_exit] Execution profiling ISR exit */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + .globl _tx_thread_context_restore +_tx_thread_context_restore: + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + PUSH {r0, lr} ; Save return address + BL _tx_execution_isr_exit ; Call the ISR exit function + POP {r0, lr} ; Save return address +#endif +; + POP {lr} + BX lr +; +;} + .type _tx_thread_context_restore,$function + .size _tx_thread_context_restore,.-_tx_thread_context_restore diff --git a/ports/cortex_m7/ghs/src/tx_thread_context_save.arm b/ports/cortex_m7/ghs/src/tx_thread_context_save.arm new file mode 100644 index 00000000..fd9ccb70 --- /dev/null +++ b/ports/cortex_m7/ghs/src/tx_thread_context_save.arm @@ -0,0 +1,85 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + .text + .align 4 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-M7/GHS */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + .globl _tx_thread_context_save +_tx_thread_context_save: +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is starting. */ +; + PUSH {r0, lr} ; Save return address + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {r0, lr} ; Recover return address +#endif +; +; /* Context is already saved - just return! */ +; + BX lr +;} + .type _tx_thread_context_save,$function + .size _tx_thread_context_save,.-_tx_thread_context_save diff --git a/ports/cortex_m7/ghs/src/tx_thread_interrupt_control.arm b/ports/cortex_m7/ghs/src/tx_thread_interrupt_control.arm new file mode 100644 index 00000000..94680f21 --- /dev/null +++ b/ports/cortex_m7/ghs/src/tx_thread_interrupt_control.arm @@ -0,0 +1,75 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + .text + .align 4 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-M7/GHS */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + .globl _tx_thread_interrupt_control +_tx_thread_interrupt_control: + MRS r1, PRIMASK ; Pickup current interrupt lockout + MSR PRIMASK, r0 ; Apply the new interrupt lockout + MOV r0, r1 ; Transfer old to return register + BX lr ; Return to caller +; +;} + .type _tx_thread_interrupt_control,$function + .size _tx_thread_interrupt_control,.-_tx_thread_interrupt_control diff --git a/ports/cortex_m7/ghs/src/tx_thread_interrupt_disable.arm b/ports/cortex_m7/ghs/src/tx_thread_interrupt_disable.arm new file mode 100644 index 00000000..918c4e9d --- /dev/null +++ b/ports/cortex_m7/ghs/src/tx_thread_interrupt_disable.arm @@ -0,0 +1,85 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + .text + .align 4 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-M7/GHS */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts and returning */ +;/* the previous interrupt lockout posture. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_disable(UINT new_posture) +;{ + .globl _tx_thread_interrupt_disable +_tx_thread_interrupt_disable: +; +; /* Return current interrupt lockout posture. */ +; + MRS r0, PRIMASK + CPSID i + BX lr +; +;} + .type _tx_thread_interrupt_disable,$function + .size _tx_thread_interrupt_disable,.-_tx_thread_interrupt_disable diff --git a/ports/cortex_m7/ghs/src/tx_thread_interrupt_restore.arm b/ports/cortex_m7/ghs/src/tx_thread_interrupt_restore.arm new file mode 100644 index 00000000..f60f0684 --- /dev/null +++ b/ports/cortex_m7/ghs/src/tx_thread_interrupt_restore.arm @@ -0,0 +1,76 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + .text + .align 4 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-M7/GHS */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for restoring the previous */ +;/* interrupt lockout posture. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* previous_posture Previous interrupt posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_interrupt_restore(UINT new_posture) +;{ + .globl _tx_thread_interrupt_restore +_tx_thread_interrupt_restore: +; +; /* Restore previous interrupt lockout posture. */ +; + MSR PRIMASK, r0 + BX lr +; +;} + .type _tx_thread_interrupt_restore,$function + .size _tx_thread_interrupt_restore,.-_tx_thread_interrupt_restore diff --git a/ports/cortex_m7/ghs/src/tx_thread_schedule.arm b/ports/cortex_m7/ghs/src/tx_thread_schedule.arm new file mode 100644 index 00000000..0871821c --- /dev/null +++ b/ports/cortex_m7/ghs/src/tx_thread_schedule.arm @@ -0,0 +1,282 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + .text + .align 4 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-M7/GHS */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + .globl _tx_thread_schedule +_tx_thread_schedule: +; +; /* This function should only ever be called on Cortex-M +; from the first schedule request. Subsequent scheduling occurs +; from the PendSV handling routines below. */ +; +; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ +; + MOV r0, #0 ; Build value for TX_FALSE + LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag + STR r0, [r2, #0] ; Clear preempt disable flag +; +; /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */ +; +#ifdef __VFP__ + MRS r0, CONTROL ; Pickup current CONTROL register + BIC r0, r0, #4 ; Clear the FPCA bit + MSR CONTROL, r0 ; Setup new CONTROL register +#endif +; +; /* Enable interrupts */ +; + CPSIE i +; +; /* Enter the scheduler for the first time. */ +; + MOV r0, #0x10000000 ; Load PENDSVSET bit + MOV r1, #0xE000E000 ; Load NVIC base + STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR + DSB ; Complete all memory accesses + ISB ; Flush pipeline +; +; /* Wait here for the PendSV to take place. */ +; +__tx_wait_here: + B __tx_wait_here ; Wait for the PendSV to happen + + .type _tx_thread_schedule,$function + .size _tx_thread_schedule,.-_tx_thread_schedule +;} +; +; /* Generic context PendSV handler. */ +; + .globl PendSV_Handler + .globl __tx_PendSVHandler +PendSV_Handler: +__tx_PendSVHandler: +; +; /* Get current thread value and new thread pointer. */ +; +__tx_ts_handler: + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + CPSID i ; Disable interrupts + PUSH {r0, lr} ; Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit ; Call the thread exit function + POP {r0, lr} ; Recover LR + CPSIE i ; Enable interrupts +#endif + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r2, =_tx_thread_execute_ptr ; Build execute thread pointer address + MOV r3, #0 ; Build NULL value + LDR r1, [r0] ; Pickup current thread pointer +; +; /* Determine if there is a current thread to finish preserving. */ +; + CBZ r1, __tx_ts_new ; If NULL, skip preservation +; +; /* Recover PSP and preserve current thread context. */ +; + STR r3, [r0] ; Set _tx_thread_current_ptr to NULL + MRS r12, PSP ; Pickup PSP pointer (thread's stack pointer) + STMDB r12!, {r4-r11} ; Save its remaining registers +#ifdef __VFP__ + TST LR, #0x10 ; Determine if the VFP extended frame is present + BNE _skip_vfp_save + VSTMDB r12!,{s16-s31} ; Yes, save additional VFP registers +_skip_vfp_save: +#endif + LDR r4, =_tx_timer_time_slice ; Build address of time-slice variable + STR.W LR, [r12, #-0x4]! ; Save LR on the stack +; +; /* Determine if time-slice is active. If it isn't, skip time handling processing. */ +; + LDR r5, [r4] ; Pickup current time-slice + STR r12, [r1, #8] ; Save the thread stack pointer + CBZ r5, __tx_ts_new ; If not active, skip processing +; +; /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ +; + STR r5, [r1, #24] ; Save current time-slice +; +; /* Clear the global time-slice. */ +; + STR r3, [r4] ; Clear time-slice +; +; +; /* Executing thread is now completely preserved!!! */ +; +__tx_ts_new: +; +; /* Now we are looking for a new thread to execute! */ +; + CPSID i ; Disable interrupts + LDR r1, [r2] ; Is there another thread ready to execute? + CBZ r1, __tx_ts_wait ; No, skip to the wait processing +; +; /* Yes, another thread is ready for else, make the current thread the new thread. */ +; + STR r1, [r0] ; Setup the current thread pointer to the new thread + CPSIE i ; Enable interrupts +; +; /* Increment the thread run count. */ +; +__tx_ts_restore: + LDR r7, [r1, #4] ; Pickup the current thread run count + LDR r4, =_tx_timer_time_slice ; Build address of time-slice variable + LDR r5, [r1, #24] ; Pickup thread's current time-slice + ADD r7, r7, #1 ; Increment the thread run count + STR r7, [r1, #4] ; Store the new run count +; +; /* Setup global time-slice with thread's current time-slice. */ +; + STR r5, [r4] ; Setup global time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + PUSH {r0, r1} ; Save r0/r1 + BL _tx_execution_thread_enter ; Call the thread execution enter function + POP {r0, r1} ; Recover r3 +#endif +; +; /* Restore the thread context and PSP. */ +; + LDR r12, [r1, #8] ; Pickup thread's stack pointer + LDR.W LR, [r12], #4 ; Pickup LR +#ifdef __VFP__ + TST LR, #0x10 ; Determine if the VFP extended frame is present + BNE _skip_vfp_restore ; If not, skip VFP restore + VLDMIA r12!, {s16-s31} ; Yes, restore additional VFP registers +_skip_vfp_restore: +#endif + LDMIA r12!, {r4-r11} ; Recover thread's registers + MSR PSP, r12 ; Setup the thread's stack pointer +; +; /* Return to thread. */ +; + BX lr ; Return to thread! +; +; /* The following is the idle wait processing... in this case, no threads are ready for execution and the +; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +; are disabled to allow use of WFI for waiting for a thread to arrive. */ +; +__tx_ts_wait: + CPSID i ; Disable interrupts + LDR r1, [r2] ; Pickup the next thread to execute pointer + STR r1, [r0] ; Store it in the current pointer + CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready! +#ifdef TX_ENABLE_WFI + DSB ; Ensure no outstanding memory transactions + WFI ; Wait for interrupt + ISB ; Ensure pipeline is flushed +#endif + CPSIE i ; Enable interrupts + B __tx_ts_wait ; Loop to continue waiting +; +; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +; already in the handler! */ +; +__tx_ts_ready: + MOV r7, #0x08000000 ; Build clear PendSV value + MOV r8, #0xE000E000 ; Build base NVIC address + STR r7, [r8, #0xD04] ; Clear any PendSV +; +; /* Re-enable interrupts and restore new thread. */ +; + CPSIE i ; Enable interrupts + B __tx_ts_restore ; Restore the thread +;} +; + .type __tx_PendSVHandler,$function + .size __tx_PendSVHandler,.-__tx_PendSVHandler + +#ifdef __VFP__ + + .globl tx_thread_fpu_enable +tx_thread_fpu_enable: +; +; /* Automatic VPF logic is supported, this function is present only for +; backward compatibility purposes and therefore simply returns. */ +; + BX LR ; Return to caller + + .type tx_thread_fpu_enable,$function + .size tx_thread_fpu_enable,.-tx_thread_fpu_enable + + .global tx_thread_fpu_disable +tx_thread_fpu_disable: +; +; /* Automatic VPF logic is supported, this function is present only for +; backward compatibility purposes and therefore simply returns. */ +; + BX LR ; Return to caller + + .type tx_thread_fpu_disable,$function + .size tx_thread_fpu_disable,.-tx_thread_fpu_disable + +#endif diff --git a/ports/cortex_m7/ghs/src/tx_thread_stack_build.arm b/ports/cortex_m7/ghs/src/tx_thread_stack_build.arm new file mode 100644 index 00000000..159b5077 --- /dev/null +++ b/ports/cortex_m7/ghs/src/tx_thread_stack_build.arm @@ -0,0 +1,135 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + .text + .align 4 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-M7/GHS */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + .globl _tx_thread_stack_build +_tx_thread_stack_build: +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-M should look like the following after it is built: +; +; Stack Top: +; LR Interrupted LR (LR at time of PENDSV) +; r4 Initial value for r4 +; r5 Initial value for r5 +; r6 Initial value for r6 +; r7 Initial value for r7 +; r8 Initial value for r8 +; r9 Initial value for r9 +; r10 Initial value for r10 +; r11 Initial value for r11 +; r0 Initial value for r0 (Hardware stack starts here!!) +; r1 Initial value for r1 +; r2 Initial value for r2 +; r3 Initial value for r3 +; r12 Initial value for r12 +; lr Initial value for lr +; pc Initial value for pc +; xPSR Initial value for xPSR +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #0x7 ; Align frame for 8-byte alignment + SUB r2, r2, #68 ; Subtract frame size + LDR r3, =0xFFFFFFFD ; Build initial LR value + STR r3, [r2, #0] ; Save on the stack +; +; /* Actually build the stack frame. */ +; + MOV r3, #0 ; Build initial register value + STR r3, [r2, #4] ; Store initial r4 + STR r3, [r2, #8] ; Store initial r5 + STR r3, [r2, #12] ; Store initial r6 + STR r3, [r2, #16] ; Store initial r7 + STR r3, [r2, #20] ; Store initial r8 + STR r3, [r2, #24] ; Store initial r9 + STR r3, [r2, #28] ; Store initial r10 + STR r3, [r2, #32] ; Store initial r11 +; +; /* Hardware stack follows. */ +; + STR r3, [r2, #36] ; Store initial r0 + STR r3, [r2, #40] ; Store initial r1 + STR r3, [r2, #44] ; Store initial r2 + STR r3, [r2, #48] ; Store initial r3 + STR r3, [r2, #52] ; Store initial r12 + MOV r3, #0xFFFFFFFF ; Poison EXC_RETURN value + STR r3, [r2, #56] ; Store initial lr + STR r1, [r2, #60] ; Store initial pc + MOV r3, #0x01000000 ; Only T-bit need be set + STR r3, [r2, #64] ; Store initial xPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block + BX lr ; Return to caller +;} + .type _tx_thread_stack_build,$function + .size _tx_thread_stack_build,.-_tx_thread_stack_build diff --git a/ports/cortex_m7/ghs/src/tx_thread_system_return.arm b/ports/cortex_m7/ghs/src/tx_thread_system_return.arm new file mode 100644 index 00000000..d30d1443 --- /dev/null +++ b/ports/cortex_m7/ghs/src/tx_thread_system_return.arm @@ -0,0 +1,87 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + .text + .align 4 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-M7/GHS */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + .globl _tx_thread_system_return +_tx_thread_system_return: +; +; /* Return to real scheduler via PendSV. Note that this routine is often +; replaced with in-line assembly in tx_port.h to improved performance. */ +; + MOV r0, #0x10000000 ; Load PENDSVSET bit + MOV r1, #0xE000E000 ; Load NVIC base + STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR + MRS r0, IPSR ; Pickup IPSR + CMP r0, #0 ; Is it a thread returning? + BNE _isr_context ; If ISR, skip interrupt enable + MRS r1, PRIMASK ; Thread context returning, pickup PRIMASK + CPSIE i ; Enable interrupts + MSR PRIMASK, r1 ; Restore original interrupt posture +_isr_context: + BX lr ; Return to caller +;} + .type _tx_thread_system_return,$function + .size _tx_thread_system_return,.-_tx_thread_system_return diff --git a/ports/cortex_m7/ghs/src/tx_timer_interrupt.arm b/ports/cortex_m7/ghs/src/tx_timer_interrupt.arm new file mode 100644 index 00000000..32e08c29 --- /dev/null +++ b/ports/cortex_m7/ghs/src/tx_timer_interrupt.arm @@ -0,0 +1,243 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + .text + .align 4 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-M7/GHS */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* expiration functions are called. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + .globl _tx_timer_interrupt +_tx_timer_interrupt: +; +; /* Upon entry to this routine, it is assumed that the compiler scratch registers are available +; for use. */ +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + LDR r1, =_tx_timer_system_clock ; Pickup address of system clock + LDR r0, [r1, #0] ; Pickup system clock + ADD r0, r0, #1 ; Increment system clock + STR r0, [r1, #0] ; Store new system clock +; +; /* Test for time-slice expiration. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r2, [r3, #0] ; Pickup time-slice + CBZ r2, __tx_timer_no_time_slice ; Is it non-active? + ; Yes, skip time-slice processing +; +; /* Decrement the time_slice. */ +; _tx_timer_time_slice--; +; + SUB r2, r2, #1 ; Decrement the time-slice + STR r2, [r3, #0] ; Store new time-slice value +; +; /* Check for expiration. */ +; if (__tx_timer_time_slice == 0) +; + CBNZ r2, __tx_timer_no_time_slice ; Has it expired? +; +; /* Set the time-slice expired flag. */ +; _tx_timer_expired_time_slice = TX_TRUE; +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup address of expired flag + MOV r0, #1 ; Build expired value + STR r0, [r3, #0] ; Set time-slice expiration flag +; +; } +; +__tx_timer_no_time_slice: +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + LDR r1, =_tx_timer_current_ptr ; Pickup current timer pointer addr + LDR r0, [r1, #0] ; Pickup current timer + LDR r2, [r0, #0] ; Pickup timer list entry + CBZ r2, __tx_timer_no_timer ; Is there anything in the list? + ; No, just increment the timer +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + LDR r3, =_tx_timer_expired ; Pickup expiration flag address + MOV r2, #1 ; Build expired value + STR r2, [r3, #0] ; Set expired flag + B __tx_timer_done ; Finished timer processing +; +; } +; else +; { +__tx_timer_no_timer: +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ADD r0, r0, #4 ; Move to next timer +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + LDR r3, =_tx_timer_list_end ; Pickup addr of timer list end + LDR r2, [r3, #0] ; Pickup list end + CMP r0, r2 ; Are we at list end? + BNE __tx_timer_skip_wrap ; No, skip wrap-around logic +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + LDR r3, =_tx_timer_list_start ; Pickup addr of timer list start + LDR r0, [r3, #0] ; Set current pointer to list start +; +__tx_timer_skip_wrap: +; + STR r0, [r1, #0] ; Store new current timer pointer +; } +; +__tx_timer_done: +; +; +; /* See if anything has expired. */ +; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of expired flag + LDR r2, [r3, #0] ; Pickup time-slice expired flag + CBNZ r2, __tx_something_expired ; Did a time-slice expire? + ; If non-zero, time-slice expired + LDR r1, =_tx_timer_expired ; Pickup addr of other expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CBZ r0, __tx_timer_nothing_expired ; Did a timer expire? + ; No, nothing expired +; +__tx_something_expired: +; +; + STMDB sp!, {r0, lr} ; Save the lr register on the stack + ; and save r0 just to keep 8-byte alignment +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + LDR r1, =_tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CBZ r0, __tx_timer_dont_activate ; Check for timer expiration + ; If not set, skip timer activation +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + BL _tx_timer_expiration_process ; Call the timer expiration handling routine +; +; } +__tx_timer_dont_activate: +; +; /* Did time slice expire? */ +; if (_tx_timer_expired_time_slice) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r2, [r3, #0] ; Pickup the actual flag + CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set + ; No, skip time-slice processing +; +; /* Time slice interrupted thread. */ +; _tx_thread_time_slice(); + + BL _tx_thread_time_slice ; Call time-slice processing + LDR r0, =_tx_thread_preempt_disable ; Build address of preempt disable flag + LDR r1, [r0] ; Is the preempt disable flag set? + CBNZ r1, __tx_timer_skip_time_slice ; Yes, skip the PendSV logic + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup the current thread pointer + LDR r2, =_tx_thread_execute_ptr ; Build execute thread pointer address + LDR r3, [r2] ; Pickup the execute thread pointer + LDR r0, =0xE000ED04 ; Build address of control register + LDR r2, =0x10000000 ; Build value for PendSV bit + CMP r1, r3 ; Are they the same? + BEQ __tx_timer_skip_time_slice ; If the same, there was no time-slice performed + STR r2, [r0] ; Not the same, issue the PendSV for preemption +__tx_timer_skip_time_slice: +; +; } +; +__tx_timer_not_ts_expiration: +; + LDMIA sp!, {r0, lr} ; Recover lr register (r0 is just there for + ; the 8-byte stack alignment +; +; } +; +__tx_timer_nothing_expired: + + DSB ; Complete all memory access + BX lr ; Return to caller +; +;} + .type _tx_timer_interrupt,$function + .size _tx_timer_interrupt,.-_tx_timer_interrupt diff --git a/ports/cortex_m7/ghs/src/txr_ghs.c b/ports/cortex_m7/ghs/src/txr_ghs.c new file mode 100644 index 00000000..19572e2b --- /dev/null +++ b/ports/cortex_m7/ghs/src/txr_ghs.c @@ -0,0 +1,84 @@ +/* + * ThreadX API Runtime Error Support + * + * Copyright 1983-2019 Green Hills Software LLC. + * + * This program is the property of Green Hills Software LLC., + * its contents are proprietary information and no part of it + * is to be disclosed to anyone except employees of Green Hills + * Software LLC., or as agreed in writing signed by the President + * of Green Hills Software LLC. + */ + +/* #include "tx_ghs.h" */ +#ifndef TX_DISABLE_ERROR_CHECKING +#define TX_DISABLE_ERROR_CHECKING +#endif +#include "tx_api.h" + +/* Customized ThreadX API runtime error support routine. */ + +void _rnerr(int num, int linenum, const char*str, void*ptr, ...); + +/* __ghs_rnerr() + This is the custom runtime error checking routine. + This implementation uses the existing __rnerr() routine. + Another implementation could use the .syscall mechanism, + provided MULTI was modified to understand that. + */ +void __ghs_rnerr(char *errMsg, int stackLevels, int stackTraceDisplay, void *hexVal) { + TX_INTERRUPT_SAVE_AREA + int num; + /* + Initialize the stack levels value. + + Add 3 to account for the calls to _rnerr, __rnerr, and + __ghs_rnerr. + + If the implementation changes, calls to __ghs_rnerr + will not need to be changed. + + Zero is not permitted, so substitute 3 in that case. + */ + num = (stackLevels+3) & 0xf; + if (!num) { + num = 3; + } + /* + Shift the stack levels value to bits 12..15 and + insert the stack trace display value in bit 11. + Bits 0..10 are unused. + */ + num = (num << 12) | (stackTraceDisplay ? 0x800 : 0); + + /* This will mask all interrupts in the RTEC code, which is probably + unacceptable for many targets. */ + TX_DISABLE + _rnerr(num, -1, (const char *)hexVal, (void *)errMsg); + TX_RESTORE +} + + +/* ThreadX thread stack checking runtime support routine. */ + +extern char __ghsbegin_stack[]; +extern TX_THREAD *_tx_thread_current_ptr; + +void __stkchk(void) { + int i; + if(_tx_thread_current_ptr) + { + if((unsigned)(&i) <= + (unsigned)(_tx_thread_current_ptr -> tx_thread_stack_start)) + { + _rnerr(21, -1, 0, 0); + } + } + else + { + if((unsigned)(&i) <= (unsigned)__ghsbegin_stack) + { + _rnerr(21, -1, 0, 0); + } + } +} diff --git a/ports/cortex_m7/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_m7/gnu/example_build/tx_initialize_low_level.S index 710590f5..85e612a6 100644 --- a/ports/cortex_m7/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_m7/gnu/example_build/tx_initialize_low_level.S @@ -49,7 +49,7 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* FUNCTION RELEASE */ @/* */ @/* _tx_initialize_low_level Cortex-M7/GNU */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -83,12 +83,10 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 06-30-2020 William E. Lamie Modified Comment(s), fixed */ -@/* GNU assembly comment, */ -@/* resulting in version 6.0.1 */ -@/* 08-14-2020 William E. Lamie Modified Comment(s), clean */ +@/* 09-30-2020 William E. Lamie Modified Comment(s), fixed */ +@/* GNU assembly comment, clean */ @/* up whitespace, resulting */ -@/* in version 6.0.2 */ +@/* in version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_m7/gnu/inc/tx_port.h b/ports/cortex_m7/gnu/inc/tx_port.h index 95adfab4..6fdefd0b 100644 --- a/ports/cortex_m7/gnu/inc/tx_port.h +++ b/ports/cortex_m7/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M7/GNU */ -/* 6.0 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,8 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ /* */ /**************************************************************************/ @@ -482,7 +484,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/GNU Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/GNU Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_m7/gnu/readme_threadx.txt b/ports/cortex_m7/gnu/readme_threadx.txt index c5975f3a..04a541cd 100644 --- a/ports/cortex_m7/gnu/readme_threadx.txt +++ b/ports/cortex_m7/gnu/readme_threadx.txt @@ -141,8 +141,8 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -08-14-2020 ThreadX update of Cortex-M7/GNU port. The following files were - changed/added for port specific version 6.0.2: +09-30-2020 ThreadX update of Cortex-M7/GNU port. The following files were + changed/added for port specific version 6.1: *.S Modified comments and whitespace. diff --git a/ports/cortex_m7/gnu/src/tx_thread_context_restore.S b/ports/cortex_m7/gnu/src/tx_thread_context_restore.S index dfddb849..2cc089dd 100755 --- a/ports/cortex_m7/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_m7/gnu/src/tx_thread_context_restore.S @@ -29,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_restore Cortex-M7/GNU */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -64,9 +64,8 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Modified comment(s), */ +@/* resulting in version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m7/gnu/src/tx_thread_context_save.S b/ports/cortex_m7/gnu/src/tx_thread_context_save.S index 201cccdd..98330daa 100755 --- a/ports/cortex_m7/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_m7/gnu/src/tx_thread_context_save.S @@ -29,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_save Cortex-M7/GNU */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -63,9 +63,8 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Modified comment(s), */ +@/* resulting in version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m7/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_m7/gnu/src/tx_thread_interrupt_control.S index c43b8cc9..ba269498 100755 --- a/ports/cortex_m7/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_m7/gnu/src/tx_thread_interrupt_control.S @@ -28,7 +28,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_control Cortex-M7/GNU */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -59,9 +59,9 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 Scott Larson Modified comment(s), and */ +@/* cleaned up whitespace, */ +@/* resulting in version 6.1 */ @/* */ @/**************************************************************************/ @/* UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_m7/gnu/src/tx_thread_schedule.S b/ports/cortex_m7/gnu/src/tx_thread_schedule.S index 0f0c18b7..4dd2ae83 100755 --- a/ports/cortex_m7/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_m7/gnu/src/tx_thread_schedule.S @@ -37,7 +37,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule Cortex-M7/GNU */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -71,9 +71,8 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Modified comment(s), */ +@/* resulting in version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_m7/gnu/src/tx_thread_stack_build.S b/ports/cortex_m7/gnu/src/tx_thread_stack_build.S index c8723d1d..a163ab91 100755 --- a/ports/cortex_m7/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_m7/gnu/src/tx_thread_stack_build.S @@ -29,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_stack_build Cortex-M7/GNU */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -62,14 +62,12 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 06-30-2020 William E. Lamie Modified Comment(s), setting */ -@/* R10 to top of stack is not */ -@/* needed. Removed references */ -@/* to stack frame, resulting */ -@/* in version 6.0.1 */ -@/* 08-14-2020 William E. Lamie Modified Comment(s), clean up */ +@/* 09-30-2020 William E. Lamie Modified Comment(s), setting */ +@/* R10 to top of stack is not */ +@/* needed. Removed references */ +@/* to stack frame, clean up */ @/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* in version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_m7/gnu/src/tx_thread_system_return.S b/ports/cortex_m7/gnu/src/tx_thread_system_return.S index 9ed23b63..965f4482 100755 --- a/ports/cortex_m7/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_m7/gnu/src/tx_thread_system_return.S @@ -29,7 +29,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_system_return Cortex-M7/GNU */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -62,9 +62,8 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Modified comment(s), */ +@/* resulting in version 6.1 */ @/* */ @/**************************************************************************/ @/* VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_m7/gnu/src/tx_timer_interrupt.S b/ports/cortex_m7/gnu/src/tx_timer_interrupt.S index 7bf85439..5e1a1570 100755 --- a/ports/cortex_m7/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_m7/gnu/src/tx_timer_interrupt.S @@ -40,7 +40,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_timer_interrupt Cortex-M7/GNU */ -@/* 6.0.2 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -75,9 +75,8 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -@/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -@/* whitespace, resulting */ -@/* in version 6.0.2 */ +@/* 09-30-2020 William E. Lamie Modified comment(s), */ +@/* resulting in version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_m7/iar/example_build/tx_initialize_low_level.s b/ports/cortex_m7/iar/example_build/tx_initialize_low_level.s index bb349b95..b20c2801 100644 --- a/ports/cortex_m7/iar/example_build/tx_initialize_low_level.s +++ b/ports/cortex_m7/iar/example_build/tx_initialize_low_level.s @@ -45,7 +45,7 @@ __tx_free_memory_start ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level Cortex-M7/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -78,10 +78,7 @@ __tx_free_memory_start ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_m7/iar/inc/tx_port.h b/ports/cortex_m7/iar/inc/tx_port.h index 9995e99a..d465e382 100644 --- a/ports/cortex_m7/iar/inc/tx_port.h +++ b/ports/cortex_m7/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M7/IAR */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -483,7 +483,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/IAR Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/IAR Version 6.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m7/iar/readme_threadx.txt b/ports/cortex_m7/iar/readme_threadx.txt index 41ff1b5a..1f82f580 100644 --- a/ports/cortex_m7/iar/readme_threadx.txt +++ b/ports/cortex_m7/iar/readme_threadx.txt @@ -206,12 +206,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -08-14-2020 ThreadX update of Cortex-M7/IAR port. The following files were - changed/added for port specific version 6.0.2: - - *.s Modified comments and whitespace. - -06/30/2020 Initial ThreadX version 6.0.1 for Cortex-M7 using IAR's ARM tools. +09-30-2020 Initial ThreadX version 6.1 for Cortex-M7 using IAR's ARM tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_m7/iar/src/tx_misra.s b/ports/cortex_m7/iar/src/tx_misra.s index 60ab3549..2add69b3 100644 --- a/ports/cortex_m7/iar/src/tx_misra.s +++ b/ports/cortex_m7/iar/src/tx_misra.s @@ -107,7 +107,7 @@ SECTION `.data`:DATA:REORDER:NOROOT(2) DATA -// 51 CHAR _tx_version_id[100] = "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX 6.0 MISRA C Compliant *"; +// 51 CHAR _tx_version_id[100] = "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX 6.1 MISRA C Compliant *"; _tx_version_id: DC8 43H, 6FH, 70H, 79H, 72H, 69H, 67H, 68H DC8 74H, 20H, 28H, 63H, 29H, 20H, 31H, 39H diff --git a/ports/cortex_m7/iar/src/tx_thread_context_restore.s b/ports/cortex_m7/iar/src/tx_thread_context_restore.s index fc27deeb..e269a807 100644 --- a/ports/cortex_m7/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_m7/iar/src/tx_thread_context_restore.s @@ -38,7 +38,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore Cortex-M7/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -72,10 +72,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_m7/iar/src/tx_thread_context_save.s b/ports/cortex_m7/iar/src/tx_thread_context_save.s index d1a7f71d..75a20061 100644 --- a/ports/cortex_m7/iar/src/tx_thread_context_save.s +++ b/ports/cortex_m7/iar/src/tx_thread_context_save.s @@ -33,7 +33,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save Cortex-M7/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -66,10 +66,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_m7/iar/src/tx_thread_interrupt_control.s b/ports/cortex_m7/iar/src/tx_thread_interrupt_control.s index 207ffed8..b8f727e3 100644 --- a/ports/cortex_m7/iar/src/tx_thread_interrupt_control.s +++ b/ports/cortex_m7/iar/src/tx_thread_interrupt_control.s @@ -28,7 +28,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control Cortex-M7/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -58,10 +58,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_m7/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_m7/iar/src/tx_thread_interrupt_disable.s index d706ed79..bea68745 100644 --- a/ports/cortex_m7/iar/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_m7/iar/src/tx_thread_interrupt_disable.s @@ -28,7 +28,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-M7/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -58,10 +58,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(UINT new_posture) diff --git a/ports/cortex_m7/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_m7/iar/src/tx_thread_interrupt_restore.s index addd8816..64ffcce0 100644 --- a/ports/cortex_m7/iar/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_m7/iar/src/tx_thread_interrupt_restore.s @@ -28,7 +28,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-M7/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -58,10 +58,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_interrupt_restore(UINT new_posture) diff --git a/ports/cortex_m7/iar/src/tx_thread_schedule.s b/ports/cortex_m7/iar/src/tx_thread_schedule.s index 0e26586d..409c6987 100644 --- a/ports/cortex_m7/iar/src/tx_thread_schedule.s +++ b/ports/cortex_m7/iar/src/tx_thread_schedule.s @@ -37,7 +37,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M7/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -70,10 +70,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_m7/iar/src/tx_thread_stack_build.s b/ports/cortex_m7/iar/src/tx_thread_stack_build.s index 9a94461b..919b0da7 100644 --- a/ports/cortex_m7/iar/src/tx_thread_stack_build.s +++ b/ports/cortex_m7/iar/src/tx_thread_stack_build.s @@ -28,7 +28,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build Cortex-M7/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -60,10 +60,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_m7/iar/src/tx_thread_system_return.s b/ports/cortex_m7/iar/src/tx_thread_system_return.s index 52322551..81be6e32 100644 --- a/ports/cortex_m7/iar/src/tx_thread_system_return.s +++ b/ports/cortex_m7/iar/src/tx_thread_system_return.s @@ -28,7 +28,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return Cortex-M7/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -60,10 +60,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_m7/iar/src/tx_timer_interrupt.s b/ports/cortex_m7/iar/src/tx_timer_interrupt.s index 33f13a42..2f5594d5 100644 --- a/ports/cortex_m7/iar/src/tx_timer_interrupt.s +++ b/ports/cortex_m7/iar/src/tx_timer_interrupt.s @@ -42,7 +42,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt Cortex-M7/IAR */ -;/* 6.0.2 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -75,10 +75,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ -;/* 08-14-2020 Scott Larson Modified comment(s), clean up */ -;/* whitespace, resulting */ -;/* in version 6.0.2 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_r4/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_r4/ac5/example_build/tx_initialize_low_level.s index 330e7865..03cae15c 100644 --- a/ports/cortex_r4/ac5/example_build/tx_initialize_low_level.s +++ b/ports/cortex_r4/ac5/example_build/tx_initialize_low_level.s @@ -96,7 +96,7 @@ __vectors ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level Cortex-R4/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -129,7 +129,7 @@ __vectors ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_r4/ac5/inc/tx_port.h b/ports/cortex_r4/ac5/inc/tx_port.h index 75238e40..d73a6c82 100644 --- a/ports/cortex_r4/ac5/inc/tx_port.h +++ b/ports/cortex_r4/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-R4/AC5 */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -324,7 +324,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/AC5 Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/AC5 Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r4/ac5/readme_threadx.txt b/ports/cortex_r4/ac5/readme_threadx.txt index 93ef3dbc..01b3e2da 100644 --- a/ports/cortex_r4/ac5/readme_threadx.txt +++ b/ports/cortex_r4/ac5/readme_threadx.txt @@ -539,7 +539,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-R4 using AC5 tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-R4 using AC5 tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_r4/ac5/src/tx_thread_context_restore.s b/ports/cortex_r4/ac5/src/tx_thread_context_restore.s index b1f4023c..5b42a7d3 100644 --- a/ports/cortex_r4/ac5/src/tx_thread_context_restore.s +++ b/ports/cortex_r4/ac5/src/tx_thread_context_restore.s @@ -60,7 +60,7 @@ SVC_MODE EQU 0x93 ; SVC mode ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore Cortex-R4/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -92,7 +92,7 @@ SVC_MODE EQU 0x93 ; SVC mode ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_r4/ac5/src/tx_thread_context_save.s b/ports/cortex_r4/ac5/src/tx_thread_context_save.s index f6bde687..5b329e40 100644 --- a/ports/cortex_r4/ac5/src/tx_thread_context_save.s +++ b/ports/cortex_r4/ac5/src/tx_thread_context_save.s @@ -45,7 +45,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save Cortex-R4/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -76,7 +76,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_r4/ac5/src/tx_thread_fiq_context_restore.s b/ports/cortex_r4/ac5/src/tx_thread_fiq_context_restore.s index 79ddc37e..ed350323 100644 --- a/ports/cortex_r4/ac5/src/tx_thread_fiq_context_restore.s +++ b/ports/cortex_r4/ac5/src/tx_thread_fiq_context_restore.s @@ -56,7 +56,7 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_context_restore Cortex-R4/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -88,7 +88,7 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_context_restore(VOID) diff --git a/ports/cortex_r4/ac5/src/tx_thread_fiq_context_save.s b/ports/cortex_r4/ac5/src/tx_thread_fiq_context_save.s index 75325f33..45fcfbc9 100644 --- a/ports/cortex_r4/ac5/src/tx_thread_fiq_context_save.s +++ b/ports/cortex_r4/ac5/src/tx_thread_fiq_context_save.s @@ -45,7 +45,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_context_save Cortex-R4/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -76,7 +76,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ; VOID _tx_thread_fiq_context_save(VOID) diff --git a/ports/cortex_r4/ac5/src/tx_thread_fiq_nesting_end.s b/ports/cortex_r4/ac5/src/tx_thread_fiq_nesting_end.s index e4727145..180bd776 100644 --- a/ports/cortex_r4/ac5/src/tx_thread_fiq_nesting_end.s +++ b/ports/cortex_r4/ac5/src/tx_thread_fiq_nesting_end.s @@ -45,7 +45,7 @@ FIQ_MODE_BITS EQU 0x11 ; FIQ mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_nesting_end Cortex-R4/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -84,7 +84,7 @@ FIQ_MODE_BITS EQU 0x11 ; FIQ mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_end(VOID) diff --git a/ports/cortex_r4/ac5/src/tx_thread_fiq_nesting_start.s b/ports/cortex_r4/ac5/src/tx_thread_fiq_nesting_start.s index 24f4689d..6cd0e968 100644 --- a/ports/cortex_r4/ac5/src/tx_thread_fiq_nesting_start.s +++ b/ports/cortex_r4/ac5/src/tx_thread_fiq_nesting_start.s @@ -41,7 +41,7 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_nesting_start Cortex-R4/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/cortex_r4/ac5/src/tx_thread_interrupt_control.s b/ports/cortex_r4/ac5/src/tx_thread_interrupt_control.s index 984102e0..5369776c 100644 --- a/ports/cortex_r4/ac5/src/tx_thread_interrupt_control.s +++ b/ports/cortex_r4/ac5/src/tx_thread_interrupt_control.s @@ -42,7 +42,7 @@ INT_MASK EQU 0x80 ; Interrupt bit mask ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control Cortex-R4/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ INT_MASK EQU 0x80 ; Interrupt bit mask ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_r4/ac5/src/tx_thread_interrupt_disable.s b/ports/cortex_r4/ac5/src/tx_thread_interrupt_disable.s index da0cae5c..cbcc0ac8 100644 --- a/ports/cortex_r4/ac5/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_r4/ac5/src/tx_thread_interrupt_disable.s @@ -35,7 +35,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_disable Cortex-R4/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -64,7 +64,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(void) diff --git a/ports/cortex_r4/ac5/src/tx_thread_interrupt_restore.s b/ports/cortex_r4/ac5/src/tx_thread_interrupt_restore.s index 021d8f95..6e66ef64 100644 --- a/ports/cortex_r4/ac5/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_r4/ac5/src/tx_thread_interrupt_restore.s @@ -35,7 +35,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-R4/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -65,7 +65,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_r4/ac5/src/tx_thread_irq_nesting_end.s b/ports/cortex_r4/ac5/src/tx_thread_irq_nesting_end.s index 6ad5dcf4..3459eadd 100644 --- a/ports/cortex_r4/ac5/src/tx_thread_irq_nesting_end.s +++ b/ports/cortex_r4/ac5/src/tx_thread_irq_nesting_end.s @@ -45,7 +45,7 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_irq_nesting_end Cortex-R4/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -84,7 +84,7 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports/cortex_r4/ac5/src/tx_thread_irq_nesting_start.s b/ports/cortex_r4/ac5/src/tx_thread_irq_nesting_start.s index 5fcd5382..ac978134 100644 --- a/ports/cortex_r4/ac5/src/tx_thread_irq_nesting_start.s +++ b/ports/cortex_r4/ac5/src/tx_thread_irq_nesting_start.s @@ -41,7 +41,7 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_irq_nesting_start Cortex-R4/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_r4/ac5/src/tx_thread_schedule.s b/ports/cortex_r4/ac5/src/tx_thread_schedule.s index a9f7f55a..c3290415 100644 --- a/ports/cortex_r4/ac5/src/tx_thread_schedule.s +++ b/ports/cortex_r4/ac5/src/tx_thread_schedule.s @@ -46,7 +46,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-R4/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -79,7 +79,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_r4/ac5/src/tx_thread_stack_build.s b/ports/cortex_r4/ac5/src/tx_thread_stack_build.s index 053db0e1..47f06d48 100644 --- a/ports/cortex_r4/ac5/src/tx_thread_stack_build.s +++ b/ports/cortex_r4/ac5/src/tx_thread_stack_build.s @@ -47,7 +47,7 @@ THUMB_BIT EQU 0x20 ; Thumb-bit ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build Cortex-R4/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -79,7 +79,7 @@ THUMB_BIT EQU 0x20 ; Thumb-bit ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_r4/ac5/src/tx_thread_system_return.s b/ports/cortex_r4/ac5/src/tx_thread_system_return.s index 4c5b0d28..2c7dc3e5 100644 --- a/ports/cortex_r4/ac5/src/tx_thread_system_return.s +++ b/ports/cortex_r4/ac5/src/tx_thread_system_return.s @@ -45,7 +45,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return Cortex-R4/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_r4/ac5/src/tx_thread_vectored_context_save.s b/ports/cortex_r4/ac5/src/tx_thread_vectored_context_save.s index be161ce7..30e1f701 100644 --- a/ports/cortex_r4/ac5/src/tx_thread_vectored_context_save.s +++ b/ports/cortex_r4/ac5/src/tx_thread_vectored_context_save.s @@ -44,7 +44,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_vectored_context_save Cortex-R4/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -75,7 +75,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) diff --git a/ports/cortex_r4/ac5/src/tx_timer_interrupt.s b/ports/cortex_r4/ac5/src/tx_timer_interrupt.s index f6482e30..4545d525 100644 --- a/ports/cortex_r4/ac5/src/tx_timer_interrupt.s +++ b/ports/cortex_r4/ac5/src/tx_timer_interrupt.s @@ -50,7 +50,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt Cortex-R4/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -84,7 +84,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_r4/ac6/inc/tx_port.h b/ports/cortex_r4/ac6/inc/tx_port.h index 5a38b4bf..991db05d 100644 --- a/ports/cortex_r4/ac6/inc/tx_port.h +++ b/ports/cortex_r4/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-R4/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -327,7 +327,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/AC6 Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/AC6 Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r4/ac6/readme_threadx.txt b/ports/cortex_r4/ac6/readme_threadx.txt index a5849018..ab6eebfa 100644 --- a/ports/cortex_r4/ac6/readme_threadx.txt +++ b/ports/cortex_r4/ac6/readme_threadx.txt @@ -382,7 +382,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-R4 using ARM tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-R4 using ARM tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_r4/ac6/src/tx_initialize_low_level.S b/ports/cortex_r4/ac6/src/tx_initialize_low_level.S index e1995158..ea1d88ff 100644 --- a/ports/cortex_r4/ac6/src/tx_initialize_low_level.S +++ b/ports/cortex_r4/ac6/src/tx_initialize_low_level.S @@ -72,7 +72,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_initialize_low_level Cortex-R4/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -105,7 +105,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_r4/ac6/src/tx_thread_context_restore.S b/ports/cortex_r4/ac6/src/tx_thread_context_restore.S index eefbe092..ca6f6a39 100644 --- a/ports/cortex_r4/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_r4/ac6/src/tx_thread_context_restore.S @@ -61,7 +61,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore Cortex-R4/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -93,7 +93,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_r4/ac6/src/tx_thread_context_save.S b/ports/cortex_r4/ac6/src/tx_thread_context_save.S index 9f5e23db..a935546f 100644 --- a/ports/cortex_r4/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_r4/ac6/src/tx_thread_context_save.S @@ -50,7 +50,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save Cortex-R4/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -81,7 +81,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_r4/ac6/src/tx_thread_fiq_context_restore.S b/ports/cortex_r4/ac6/src/tx_thread_fiq_context_restore.S index 8d26087f..c480e844 100644 --- a/ports/cortex_r4/ac6/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_r4/ac6/src/tx_thread_fiq_context_restore.S @@ -61,7 +61,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_context_restore Cortex-R4/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -93,7 +93,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_fiq_context_restore(VOID) */ diff --git a/ports/cortex_r4/ac6/src/tx_thread_fiq_context_save.S b/ports/cortex_r4/ac6/src/tx_thread_fiq_context_save.S index 3221a358..18d6d587 100644 --- a/ports/cortex_r4/ac6/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_r4/ac6/src/tx_thread_fiq_context_save.S @@ -50,7 +50,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_context_save Cortex-R4/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -81,7 +81,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_fiq_context_save(VOID) */ diff --git a/ports/cortex_r4/ac6/src/tx_thread_fiq_nesting_end.S b/ports/cortex_r4/ac6/src/tx_thread_fiq_nesting_end.S index 8568b961..58dad6f1 100644 --- a/ports/cortex_r4/ac6/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_r4/ac6/src/tx_thread_fiq_nesting_end.S @@ -43,7 +43,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_end Cortex-R4/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_fiq_nesting_end(VOID) */ diff --git a/ports/cortex_r4/ac6/src/tx_thread_fiq_nesting_start.S b/ports/cortex_r4/ac6/src/tx_thread_fiq_nesting_start.S index 60bd335f..a4ccd9f3 100644 --- a/ports/cortex_r4/ac6/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_r4/ac6/src/tx_thread_fiq_nesting_start.S @@ -43,7 +43,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_fiq_nesting_start Cortex-R4/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -79,7 +79,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_fiq_nesting_start(VOID) */ diff --git a/ports/cortex_r4/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_r4/ac6/src/tx_thread_interrupt_control.S index aa0215ac..e8c2259c 100644 --- a/ports/cortex_r4/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_r4/ac6/src/tx_thread_interrupt_control.S @@ -48,7 +48,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control Cortex-R4/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -78,7 +78,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* UINT _tx_thread_interrupt_control(UINT new_posture) */ diff --git a/ports/cortex_r4/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_r4/ac6/src/tx_thread_interrupt_disable.S index 079cbfdc..35e9aad5 100644 --- a/ports/cortex_r4/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_r4/ac6/src/tx_thread_interrupt_disable.S @@ -41,7 +41,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable Cortex-R4/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* UINT _tx_thread_interrupt_disable(void) */ diff --git a/ports/cortex_r4/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_r4/ac6/src/tx_thread_interrupt_restore.S index 7c374cad..24e04df0 100644 --- a/ports/cortex_r4/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_r4/ac6/src/tx_thread_interrupt_restore.S @@ -41,7 +41,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore Cortex-R4/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* UINT _tx_thread_interrupt_restore(UINT old_posture) */ diff --git a/ports/cortex_r4/ac6/src/tx_thread_irq_nesting_end.S b/ports/cortex_r4/ac6/src/tx_thread_irq_nesting_end.S index 7f81779a..5e3c5794 100644 --- a/ports/cortex_r4/ac6/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_r4/ac6/src/tx_thread_irq_nesting_end.S @@ -43,7 +43,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_end Cortex-R4/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_irq_nesting_end(VOID) */ diff --git a/ports/cortex_r4/ac6/src/tx_thread_irq_nesting_start.S b/ports/cortex_r4/ac6/src/tx_thread_irq_nesting_start.S index c8cd19a5..84f55aca 100644 --- a/ports/cortex_r4/ac6/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_r4/ac6/src/tx_thread_irq_nesting_start.S @@ -43,7 +43,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_irq_nesting_start Cortex-R4/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -79,7 +79,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_irq_nesting_start(VOID) */ diff --git a/ports/cortex_r4/ac6/src/tx_thread_schedule.S b/ports/cortex_r4/ac6/src/tx_thread_schedule.S index 75d29128..262008c1 100644 --- a/ports/cortex_r4/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_r4/ac6/src/tx_thread_schedule.S @@ -46,7 +46,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-R4/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -79,7 +79,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_schedule(VOID) */ diff --git a/ports/cortex_r4/ac6/src/tx_thread_stack_build.S b/ports/cortex_r4/ac6/src/tx_thread_stack_build.S index 57fbb637..48078eb1 100644 --- a/ports/cortex_r4/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_r4/ac6/src/tx_thread_stack_build.S @@ -52,7 +52,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build Cortex-R4/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -84,7 +84,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) */ diff --git a/ports/cortex_r4/ac6/src/tx_thread_system_return.S b/ports/cortex_r4/ac6/src/tx_thread_system_return.S index 4c025765..ecc3d388 100644 --- a/ports/cortex_r4/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_r4/ac6/src/tx_thread_system_return.S @@ -50,7 +50,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return Cortex-R4/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_system_return(VOID) */ diff --git a/ports/cortex_r4/ac6/src/tx_thread_vectored_context_save.S b/ports/cortex_r4/ac6/src/tx_thread_vectored_context_save.S index 0b7134bd..c070adae 100644 --- a/ports/cortex_r4/ac6/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_r4/ac6/src/tx_thread_vectored_context_save.S @@ -49,7 +49,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_vectored_context_save Cortex-R4/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -80,7 +80,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_vectored_context_save(VOID) */ diff --git a/ports/cortex_r4/ac6/src/tx_timer_interrupt.S b/ports/cortex_r4/ac6/src/tx_timer_interrupt.S index 1426b7f9..12bb4a5d 100644 --- a/ports/cortex_r4/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_r4/ac6/src/tx_timer_interrupt.S @@ -55,7 +55,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt Cortex-R4/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -89,7 +89,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_timer_interrupt(VOID) */ diff --git a/ports/cortex_r4/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_r4/gnu/example_build/tx_initialize_low_level.S index 69779012..aadc98b8 100644 --- a/ports/cortex_r4/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_r4/gnu/example_build/tx_initialize_low_level.S @@ -78,7 +78,7 @@ $_tx_initialize_low_level: @/* FUNCTION RELEASE */ @/* */ @/* _tx_initialize_low_level Cortex-R4/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -111,7 +111,7 @@ $_tx_initialize_low_level: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_r4/gnu/inc/tx_port.h b/ports/cortex_r4/gnu/inc/tx_port.h index b5a9bced..8ae22b85 100644 --- a/ports/cortex_r4/gnu/inc/tx_port.h +++ b/ports/cortex_r4/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-R4/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -306,7 +306,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/GNU Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/GNU Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r4/gnu/readme_threadx.txt b/ports/cortex_r4/gnu/readme_threadx.txt index c89d5940..6bd41bcc 100644 --- a/ports/cortex_r4/gnu/readme_threadx.txt +++ b/ports/cortex_r4/gnu/readme_threadx.txt @@ -486,7 +486,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-R4 using GNU tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-R4 using GNU tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_r4/gnu/src/tx_thread_context_restore.S b/ports/cortex_r4/gnu/src/tx_thread_context_restore.S index 8f37269c..1eb935e4 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_r4/gnu/src/tx_thread_context_restore.S @@ -60,7 +60,7 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_restore Cortex-R4/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -92,7 +92,7 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_r4/gnu/src/tx_thread_context_save.S b/ports/cortex_r4/gnu/src/tx_thread_context_save.S index 52447586..5b358301 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_r4/gnu/src/tx_thread_context_save.S @@ -48,7 +48,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_save Cortex-R4/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -79,7 +79,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_r4/gnu/src/tx_thread_fiq_context_restore.S b/ports/cortex_r4/gnu/src/tx_thread_fiq_context_restore.S index 5437c7af..74ffa84d 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_r4/gnu/src/tx_thread_fiq_context_restore.S @@ -59,7 +59,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_context_restore Cortex-R4/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -91,7 +91,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_context_restore(VOID) diff --git a/ports/cortex_r4/gnu/src/tx_thread_fiq_context_save.S b/ports/cortex_r4/gnu/src/tx_thread_fiq_context_save.S index 48ebb94f..c3775b36 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_r4/gnu/src/tx_thread_fiq_context_save.S @@ -47,7 +47,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_context_save Cortex-R4/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -78,7 +78,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @ VOID _tx_thread_fiq_context_save(VOID) diff --git a/ports/cortex_r4/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_r4/gnu/src/tx_thread_fiq_nesting_end.S index e30a7146..a4b9b893 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_r4/gnu/src/tx_thread_fiq_nesting_end.S @@ -50,7 +50,7 @@ FIQ_MODE_BITS = 0x11 @ FIQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_nesting_end Cortex-R4/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -89,7 +89,7 @@ FIQ_MODE_BITS = 0x11 @ FIQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_end(VOID) diff --git a/ports/cortex_r4/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_r4/gnu/src/tx_thread_fiq_nesting_start.S index 7679d8aa..da5b3930 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_r4/gnu/src/tx_thread_fiq_nesting_start.S @@ -46,7 +46,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_nesting_start Cortex-R4/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/cortex_r4/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_r4/gnu/src/tx_thread_interrupt_control.S index cbe76857..84ca0823 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_r4/gnu/src/tx_thread_interrupt_control.S @@ -56,7 +56,7 @@ $_tx_thread_interrupt_control: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_control Cortex-R4/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -86,7 +86,7 @@ $_tx_thread_interrupt_control: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_r4/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_r4/gnu/src/tx_thread_interrupt_disable.S index 9fe7a729..8b160fe5 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_r4/gnu/src/tx_thread_interrupt_disable.S @@ -53,7 +53,7 @@ $_tx_thread_interrupt_disable: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_disable Cortex-R4/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ $_tx_thread_interrupt_disable: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_disable(void) diff --git a/ports/cortex_r4/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_r4/gnu/src/tx_thread_interrupt_restore.S index e89b7999..d963c5d9 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_r4/gnu/src/tx_thread_interrupt_restore.S @@ -53,7 +53,7 @@ $_tx_thread_interrupt_restore: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_restore Cortex-R4/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -83,7 +83,7 @@ $_tx_thread_interrupt_restore: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_r4/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_r4/gnu/src/tx_thread_irq_nesting_end.S index c5800dfe..ffe7384d 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_r4/gnu/src/tx_thread_irq_nesting_end.S @@ -50,7 +50,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_irq_nesting_end Cortex-R4/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -89,7 +89,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports/cortex_r4/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_r4/gnu/src/tx_thread_irq_nesting_start.S index c7675bf2..ff5c4c64 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_r4/gnu/src/tx_thread_irq_nesting_start.S @@ -46,7 +46,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_irq_nesting_start Cortex-R4/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_r4/gnu/src/tx_thread_schedule.S b/ports/cortex_r4/gnu/src/tx_thread_schedule.S index 365e5678..8691fa87 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_r4/gnu/src/tx_thread_schedule.S @@ -62,7 +62,7 @@ $_tx_thread_schedule: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule Cortex-R4/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -95,7 +95,7 @@ $_tx_thread_schedule: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_r4/gnu/src/tx_thread_stack_build.S b/ports/cortex_r4/gnu/src/tx_thread_stack_build.S index 2b573dce..0f36b5f3 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_r4/gnu/src/tx_thread_stack_build.S @@ -64,7 +64,7 @@ $_tx_thread_stack_build: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_stack_build Cortex-R4/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -96,7 +96,7 @@ $_tx_thread_stack_build: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_r4/gnu/src/tx_thread_system_return.S b/ports/cortex_r4/gnu/src/tx_thread_system_return.S index 9d18837f..e4d2612a 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_r4/gnu/src/tx_thread_system_return.S @@ -64,7 +64,7 @@ $_tx_thread_system_return: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_system_return Cortex-R4/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -96,7 +96,7 @@ $_tx_thread_system_return: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_r4/gnu/src/tx_thread_vectored_context_save.S b/ports/cortex_r4/gnu/src/tx_thread_vectored_context_save.S index 9f69fa32..37a1ef93 100644 --- a/ports/cortex_r4/gnu/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_r4/gnu/src/tx_thread_vectored_context_save.S @@ -47,7 +47,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_vectored_context_save Cortex-R4/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -78,7 +78,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_vectored_context_save(VOID) diff --git a/ports/cortex_r4/gnu/src/tx_timer_interrupt.S b/ports/cortex_r4/gnu/src/tx_timer_interrupt.S index 629e0928..53cd6b4e 100644 --- a/ports/cortex_r4/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_r4/gnu/src/tx_timer_interrupt.S @@ -71,7 +71,7 @@ $_tx_timer_interrupt: @/* FUNCTION RELEASE */ @/* */ @/* _tx_timer_interrupt Cortex-R4/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -105,7 +105,7 @@ $_tx_timer_interrupt: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_r4/green/example_build/azure_rtos_workspace.gpj b/ports/cortex_r4/green/example_build/azure_rtos_workspace.gpj new file mode 100644 index 00000000..db8f3aeb --- /dev/null +++ b/ports/cortex_r4/green/example_build/azure_rtos_workspace.gpj @@ -0,0 +1,12 @@ +#!gbuild +primaryTarget=arm_standalone.tgt +[Project] + -bsp generic + -G + -cpu=cortexr4 + -littleendian +sample_threadx.gpj [Program] +sample_threadx_el.gpj [Program] +tx.gpj [Library] +txe.gpj [Library] +..\readme_threadx.txt diff --git a/ports/cortex_r4/green/example_build/reset.arm b/ports/cortex_r4/green/example_build/reset.arm new file mode 100644 index 00000000..a4215434 --- /dev/null +++ b/ports/cortex_r4/green/example_build/reset.arm @@ -0,0 +1,45 @@ +# +# +#/* Define the Cortex-R4 vector area. This should be located or copied to 0. */ +# + + .section ".reset", .text + .globl __vectors +__vectors: + B __entry # Reset goes to the entry function + LDR pc,UNDEFINED # Undefined handler + LDR pc,SWI # Software interrupt handler + LDR pc,PREFETCH # Prefetch exception handler + LDR pc,ABORT # Abort exception handler + LDR pc,RESERVED # Reserved exception handler + LDR pc,IRQ # IRQ interrupt handler + LDR pc,FIQ # FIQ interrupt handler +# +# +__entry: + LDR sp,STACK # Setup stack pointer + LDR pc,START # Jump to Green Hills startup +# +# +STACK: + .data.w __ghsend_stack +START: + .data.w _start # Reset goes to startup function +UNDEFINED: + .data.w __tx_undefined # Undefined handler +SWI: + .data.w __tx_swi_interrupt # Software interrupt handler +PREFETCH: + .data.w __tx_prefetch_handler # Prefetch exception handler +ABORT: + .data.w __tx_abort_handler # Abort exception handler +RESERVED: + .data.w __tx_reserved_handler # Reserved exception handler +IRQ: + .data.w __tx_irq_handler # IRQ interrupt handler +FIQ: + .data.w __tx_fiq_handler # FIQ interrupt handler +# +# + .type __vectors,$function + .size __vectors,.-__vectors diff --git a/ports/cortex_r4/green/example_build/sample_threadx.c b/ports/cortex_r4/green/example_build/sample_threadx.c new file mode 100644 index 00000000..418ec634 --- /dev/null +++ b/ports/cortex_r4/green/example_build/sample_threadx.c @@ -0,0 +1,369 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_r4/green/example_build/sample_threadx.con b/ports/cortex_r4/green/example_build/sample_threadx.con new file mode 100644 index 00000000..1fbf19f9 --- /dev/null +++ b/ports/cortex_r4/green/example_build/sample_threadx.con @@ -0,0 +1,11 @@ +target_connection.00000000.title="Simulator connection for ThreadX" +target_connection.00000000.type="Custom" +target_connection.00000000.short_type="Custom" +target_connection.00000000.args="simarm -cpu=cortexr4 -fpu -rom" +target_connection.00000000.command="simarm -cpu=cortexr4 -fpu -rom" +target_connection.00000000.logfile="" +target_connection.00000000.mode="download" +target_connection.00000000.setup_script="" +target_connection.00000000.sane="yes" +target_connection.00000000.log="no" +target_connection.00000000.timestamp="1192825758" diff --git a/ports/cortex_r4/green/example_build/sample_threadx.gpj b/ports/cortex_r4/green/example_build/sample_threadx.gpj new file mode 100644 index 00000000..b9b2c04c --- /dev/null +++ b/ports/cortex_r4/green/example_build/sample_threadx.gpj @@ -0,0 +1,11 @@ +#!gbuild +[Program] + -I../../../../common/inc + -I../../../../ports_common_green/inc + -I../inc +reset.arm +tx_initialize_low_level.arm +sample_threadx.c +tx.a +sample_threadx.ld +sample_threadx.con diff --git a/ports/cortex_r4/green/example_build/sample_threadx.ld b/ports/cortex_r4/green/example_build/sample_threadx.ld new file mode 100644 index 00000000..8d1ab4df --- /dev/null +++ b/ports/cortex_r4/green/example_build/sample_threadx.ld @@ -0,0 +1,44 @@ +# The following explains what the default Green Hills sections are for: +# +# picbase - base of the text sections, relocatable in -pic mode +# text - text section +# syscall - syscall section, for host I/O under Multi +# fixaddr/fixtype - for PIC/PID fixups +# rodata - read only data +# romdata - the ROM image of .data +# romsdata - the ROM image of .sdata +# secinfo - section information section, used by the start-up code +# pidbase - base of the data sections, relocatable in -pid mode +# sdabase - base of the small data area section pointer +# sbss - small BSS (zeroed data) section +# sdata - small data section +# data - non-zeroed writeable data section +# bss - zeroed data section +# heap - the heap, grows upward +# stack - the stack, grows downward + +-sec +{ + .reset 0x000000 : + .picbase 0x1000 : + .text : + .comment : + .intercall : + .interfunc : + .syscall : + .fixaddr : + .fixtype : + .rodata : + .romdata ROM(.data) : + .romsdata ROM(.sdata) : + .secinfo : + .pidbase align(16) : + .sdabase : + .sbss : + .sdata : + .data : + .bss : + .heap align(16) pad(0x10000) : + .stack align(16) pad(0x1000) : + .free_mem align(16) pad(0x10000) : +} diff --git a/ports/cortex_r4/green/example_build/sample_threadx_el.gpj b/ports/cortex_r4/green/example_build/sample_threadx_el.gpj new file mode 100644 index 00000000..a51049ca --- /dev/null +++ b/ports/cortex_r4/green/example_build/sample_threadx_el.gpj @@ -0,0 +1,13 @@ +#!gbuild +[Program] + -DTX_ENABLE_EVENT_LOGGING + -I../../../../common/inc + -I../../../../ports_common_green/inc + -I../inc +reset.arm +tx_initialize_low_level.arm +sample_threadx.c +txe.a +sample_threadx_el.ld +sample_threadx.con +readme_threadx.txt diff --git a/ports/cortex_r4/green/example_build/sample_threadx_el.ld b/ports/cortex_r4/green/example_build/sample_threadx_el.ld new file mode 100644 index 00000000..33c0f934 --- /dev/null +++ b/ports/cortex_r4/green/example_build/sample_threadx_el.ld @@ -0,0 +1,45 @@ +# The following explains what the default Green Hills sections are for: +# +# picbase - base of the text sections, relocatable in -pic mode +# text - text section +# syscall - syscall section, for host I/O under Multi +# fixaddr/fixtype - for PIC/PID fixups +# rodata - read only data +# romdata - the ROM image of .data +# romsdata - the ROM image of .sdata +# secinfo - section information section, used by the start-up code +# pidbase - base of the data sections, relocatable in -pid mode +# sdabase - base of the small data area section pointer +# sbss - small BSS (zeroed data) section +# sdata - small data section +# data - non-zeroed writeable data section +# bss - zeroed data section +# heap - the heap, grows upward +# stack - the stack, grows downward + +-sec +{ + .reset 0x000000 : + .picbase 0x1000 : + .text : + .comment : + .intercall : + .interfunc : + .syscall : + .fixaddr : + .fixtype : + .rodata : + .romdata ROM(.data) : + .romsdata ROM(.sdata) : + .secinfo : + .pidbase align(16) : + .sdabase : + .sbss : + .sdata : + .data : + .bss : + .heap align(16) pad(0x1000) : + .stack align(16) pad(0x1000) : + .eventlog align(16) pad(0x10000) : + .free_mem align(16) pad(0x10000) : +} diff --git a/ports/cortex_r4/green/example_build/tx.gpj b/ports/cortex_r4/green/example_build/tx.gpj new file mode 100644 index 00000000..afbd6bef --- /dev/null +++ b/ports/cortex_r4/green/example_build/tx.gpj @@ -0,0 +1,283 @@ +#!gbuild +[Library] + -I../../../../common/inc + -I../../../../ports_common_green/inc + -I../inc +..\..\..\..\common\inc\tx_api.h +..\..\..\..\common\inc\tx_block_pool.h +..\..\..\..\common\inc\tx_byte_pool.h +..\..\..\..\common\inc\tx_event_flags.h +..\..\..\..\common\inc\tx_initialize.h +..\..\..\..\common\inc\tx_mutex.h +..\..\..\..\common\inc\tx_queue.h +..\..\..\..\common\inc\tx_semaphore.h +..\..\..\..\common\inc\tx_thread.h +..\..\..\..\common\inc\tx_timer.h +..\..\..\..\common\inc\tx_trace.h +..\..\..\..\common\inc\tx_user_sample.h +..\inc\tx_port.h +..\..\..\..\ports_common_green\inc\tx_el.h +..\..\..\..\ports_common_green\inc\tx_ghs.h +..\src\tx_thread_context_restore.arm +..\src\tx_thread_context_save.arm +..\src\tx_thread_fiq_context_restore.arm +..\src\tx_thread_fiq_context_save.arm +..\src\tx_thread_fiq_nesting_end.arm +..\src\tx_thread_fiq_nesting_start.arm +..\src\tx_thread_interrupt_control.arm +..\src\tx_thread_interrupt_disable.arm +..\src\tx_thread_interrupt_restore.arm +..\src\tx_thread_irq_nesting_end.arm +..\src\tx_thread_irq_nesting_start.arm +..\src\tx_thread_schedule.arm +..\src\tx_thread_stack_build.arm +..\src\tx_thread_system_return.arm +..\src\tx_thread_vectored_context_save.arm +..\src\tx_timer_interrupt.arm +..\..\..\..\common\src\tx_block_allocate.c +..\..\..\..\common\src\tx_block_pool_cleanup.c +..\..\..\..\common\src\tx_block_pool_create.c +..\..\..\..\common\src\tx_block_pool_delete.c +..\..\..\..\common\src\tx_block_pool_info_get.c +..\..\..\..\common\src\tx_block_pool_initialize.c +..\..\..\..\common\src\tx_block_pool_performance_info_get.c +..\..\..\..\common\src\tx_block_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_block_pool_prioritize.c +..\..\..\..\common\src\tx_block_release.c +..\..\..\..\common\src\tx_byte_allocate.c +..\..\..\..\common\src\tx_byte_pool_cleanup.c +..\..\..\..\common\src\tx_byte_pool_create.c +..\..\..\..\common\src\tx_byte_pool_delete.c +..\..\..\..\common\src\tx_byte_pool_info_get.c +..\..\..\..\common\src\tx_byte_pool_initialize.c +..\..\..\..\common\src\tx_byte_pool_performance_info_get.c +..\..\..\..\common\src\tx_byte_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_byte_pool_prioritize.c +..\..\..\..\common\src\tx_byte_pool_search.c +..\..\..\..\common\src\tx_byte_release.c +..\..\..\..\common\src\tx_event_flags_cleanup.c +..\..\..\..\common\src\tx_event_flags_create.c +..\..\..\..\common\src\tx_event_flags_delete.c +..\..\..\..\common\src\tx_event_flags_get.c +..\..\..\..\common\src\tx_event_flags_info_get.c +..\..\..\..\common\src\tx_event_flags_initialize.c +..\..\..\..\common\src\tx_event_flags_performance_info_get.c +..\..\..\..\common\src\tx_event_flags_performance_system_info_get.c +..\..\..\..\common\src\tx_event_flags_set.c +..\..\..\..\common\src\tx_event_flags_set_notify.c +..\..\..\..\common\src\tx_initialize_high_level.c +..\..\..\..\common\src\tx_initialize_kernel_enter.c +..\..\..\..\common\src\tx_initialize_kernel_setup.c +..\..\..\..\common\src\tx_mutex_cleanup.c +..\..\..\..\common\src\tx_mutex_create.c +..\..\..\..\common\src\tx_mutex_delete.c +..\..\..\..\common\src\tx_mutex_get.c +..\..\..\..\common\src\tx_mutex_info_get.c +..\..\..\..\common\src\tx_mutex_initialize.c +..\..\..\..\common\src\tx_mutex_performance_info_get.c +..\..\..\..\common\src\tx_mutex_performance_system_info_get.c +..\..\..\..\common\src\tx_mutex_prioritize.c +..\..\..\..\common\src\tx_mutex_priority_change.c +..\..\..\..\common\src\tx_mutex_put.c +..\..\..\..\common\src\tx_queue_cleanup.c +..\..\..\..\common\src\tx_queue_create.c +..\..\..\..\common\src\tx_queue_delete.c +..\..\..\..\common\src\tx_queue_flush.c +..\..\..\..\common\src\tx_queue_front_send.c +..\..\..\..\common\src\tx_queue_info_get.c +..\..\..\..\common\src\tx_queue_initialize.c +..\..\..\..\common\src\tx_queue_performance_info_get.c +..\..\..\..\common\src\tx_queue_performance_system_info_get.c +..\..\..\..\common\src\tx_queue_prioritize.c +..\..\..\..\common\src\tx_queue_receive.c +..\..\..\..\common\src\tx_queue_send.c +..\..\..\..\common\src\tx_queue_send_notify.c +..\..\..\..\common\src\tx_semaphore_ceiling_put.c +..\..\..\..\common\src\tx_semaphore_cleanup.c +..\..\..\..\common\src\tx_semaphore_create.c +..\..\..\..\common\src\tx_semaphore_delete.c +..\..\..\..\common\src\tx_semaphore_get.c +..\..\..\..\common\src\tx_semaphore_info_get.c +..\..\..\..\common\src\tx_semaphore_initialize.c +..\..\..\..\common\src\tx_semaphore_performance_info_get.c +..\..\..\..\common\src\tx_semaphore_performance_system_info_get.c +..\..\..\..\common\src\tx_semaphore_prioritize.c +..\..\..\..\common\src\tx_semaphore_put.c +..\..\..\..\common\src\tx_semaphore_put_notify.c +..\..\..\..\common\src\tx_thread_create.c +..\..\..\..\common\src\tx_thread_delete.c +..\..\..\..\common\src\tx_thread_entry_exit_notify.c +..\..\..\..\common\src\tx_thread_identify.c +..\..\..\..\common\src\tx_thread_info_get.c +..\..\..\..\common\src\tx_thread_initialize.c +..\..\..\..\common\src\tx_thread_performance_info_get.c +..\..\..\..\common\src\tx_thread_performance_system_info_get.c +..\..\..\..\common\src\tx_thread_preemption_change.c +..\..\..\..\common\src\tx_thread_priority_change.c +..\..\..\..\common\src\tx_thread_relinquish.c +..\..\..\..\common\src\tx_thread_reset.c +..\..\..\..\common\src\tx_thread_resume.c +..\..\..\..\common\src\tx_thread_shell_entry.c +..\..\..\..\common\src\tx_thread_sleep.c +..\..\..\..\common\src\tx_thread_stack_analyze.c +..\..\..\..\common\src\tx_thread_stack_error_handler.c +..\..\..\..\common\src\tx_thread_stack_error_notify.c +..\..\..\..\common\src\tx_thread_suspend.c +..\..\..\..\common\src\tx_thread_system_preempt_check.c +..\..\..\..\common\src\tx_thread_system_resume.c +..\..\..\..\common\src\tx_thread_system_suspend.c +..\..\..\..\common\src\tx_thread_terminate.c +..\..\..\..\common\src\tx_thread_time_slice.c +..\..\..\..\common\src\tx_thread_time_slice_change.c +..\..\..\..\common\src\tx_thread_timeout.c +..\..\..\..\common\src\tx_thread_wait_abort.c +..\..\..\..\common\src\tx_time_get.c +..\..\..\..\common\src\tx_time_set.c +..\..\..\..\common\src\tx_timer_activate.c +..\..\..\..\common\src\tx_timer_change.c +..\..\..\..\common\src\tx_timer_create.c +..\..\..\..\common\src\tx_timer_deactivate.c +..\..\..\..\common\src\tx_timer_delete.c +..\..\..\..\common\src\tx_timer_expiration_process.c +..\..\..\..\common\src\tx_timer_info_get.c +..\..\..\..\common\src\tx_timer_initialize.c +..\..\..\..\common\src\tx_timer_performance_info_get.c +..\..\..\..\common\src\tx_timer_performance_system_info_get.c +..\..\..\..\common\src\tx_timer_system_activate.c +..\..\..\..\common\src\tx_timer_system_deactivate.c +..\..\..\..\common\src\tx_timer_thread_entry.c +..\..\..\..\common\src\tx_trace_buffer_full_notify.c +..\..\..\..\common\src\tx_trace_disable.c +..\..\..\..\common\src\tx_trace_enable.c +..\..\..\..\common\src\tx_trace_event_filter.c +..\..\..\..\common\src\tx_trace_event_unfilter.c +..\..\..\..\common\src\tx_trace_initialize.c +..\..\..\..\common\src\tx_trace_interrupt_control.c +..\..\..\..\common\src\tx_trace_isr_enter_insert.c +..\..\..\..\common\src\tx_trace_isr_exit_insert.c +..\..\..\..\common\src\tx_trace_object_register.c +..\..\..\..\common\src\tx_trace_object_unregister.c +..\..\..\..\common\src\tx_trace_user_event_insert.c +..\..\..\..\common\src\txe_block_allocate.c +..\..\..\..\common\src\txe_block_pool_create.c +..\..\..\..\common\src\txe_block_pool_delete.c +..\..\..\..\common\src\txe_block_pool_info_get.c +..\..\..\..\common\src\txe_block_pool_prioritize.c +..\..\..\..\common\src\txe_block_release.c +..\..\..\..\common\src\txe_byte_allocate.c +..\..\..\..\common\src\txe_byte_pool_create.c +..\..\..\..\common\src\txe_byte_pool_delete.c +..\..\..\..\common\src\txe_byte_pool_info_get.c +..\..\..\..\common\src\txe_byte_pool_prioritize.c +..\..\..\..\common\src\txe_byte_release.c +..\..\..\..\common\src\txe_event_flags_create.c +..\..\..\..\common\src\txe_event_flags_delete.c +..\..\..\..\common\src\txe_event_flags_get.c +..\..\..\..\common\src\txe_event_flags_info_get.c +..\..\..\..\common\src\txe_event_flags_set.c +..\..\..\..\common\src\txe_event_flags_set_notify.c +..\..\..\..\common\src\txe_mutex_create.c +..\..\..\..\common\src\txe_mutex_delete.c +..\..\..\..\common\src\txe_mutex_get.c +..\..\..\..\common\src\txe_mutex_info_get.c +..\..\..\..\common\src\txe_mutex_prioritize.c +..\..\..\..\common\src\txe_mutex_put.c +..\..\..\..\common\src\txe_queue_create.c +..\..\..\..\common\src\txe_queue_delete.c +..\..\..\..\common\src\txe_queue_flush.c +..\..\..\..\common\src\txe_queue_front_send.c +..\..\..\..\common\src\txe_queue_info_get.c +..\..\..\..\common\src\txe_queue_prioritize.c +..\..\..\..\common\src\txe_queue_receive.c +..\..\..\..\common\src\txe_queue_send.c +..\..\..\..\common\src\txe_queue_send_notify.c +..\..\..\..\common\src\txe_semaphore_ceiling_put.c +..\..\..\..\common\src\txe_semaphore_create.c +..\..\..\..\common\src\txe_semaphore_delete.c +..\..\..\..\common\src\txe_semaphore_get.c +..\..\..\..\common\src\txe_semaphore_info_get.c +..\..\..\..\common\src\txe_semaphore_prioritize.c +..\..\..\..\common\src\txe_semaphore_put.c +..\..\..\..\common\src\txe_semaphore_put_notify.c +..\..\..\..\common\src\txe_thread_create.c +..\..\..\..\common\src\txe_thread_delete.c +..\..\..\..\common\src\txe_thread_entry_exit_notify.c +..\..\..\..\common\src\txe_thread_info_get.c +..\..\..\..\common\src\txe_thread_preemption_change.c +..\..\..\..\common\src\txe_thread_priority_change.c +..\..\..\..\common\src\txe_thread_relinquish.c +..\..\..\..\common\src\txe_thread_reset.c +..\..\..\..\common\src\txe_thread_resume.c +..\..\..\..\common\src\txe_thread_suspend.c +..\..\..\..\common\src\txe_thread_terminate.c +..\..\..\..\common\src\txe_thread_time_slice_change.c +..\..\..\..\common\src\txe_thread_wait_abort.c +..\..\..\..\common\src\txe_timer_activate.c +..\..\..\..\common\src\txe_timer_change.c +..\..\..\..\common\src\txe_timer_create.c +..\..\..\..\common\src\txe_timer_deactivate.c +..\..\..\..\common\src\txe_timer_delete.c +..\..\..\..\common\src\txe_timer_info_get.c +..\..\..\..\ports_common_green\src\tx_el.c +..\..\..\..\ports_common_green\src\tx_ghs.c +..\..\..\..\ports_common_green\src\tx_ghse.c +..\..\..\..\ports_common_green\src\txr_block_allocate.c +..\..\..\..\ports_common_green\src\txr_block_pool_create.c +..\..\..\..\ports_common_green\src\txr_block_pool_delete.c +..\..\..\..\ports_common_green\src\txr_block_pool_info_get.c +..\..\..\..\ports_common_green\src\txr_block_pool_prioritize.c +..\..\..\..\ports_common_green\src\txr_block_release.c +..\..\..\..\ports_common_green\src\txr_byte_allocate.c +..\..\..\..\ports_common_green\src\txr_byte_pool_create.c +..\..\..\..\ports_common_green\src\txr_byte_pool_delete.c +..\..\..\..\ports_common_green\src\txr_byte_pool_info_get.c +..\..\..\..\ports_common_green\src\txr_byte_pool_prioritize.c +..\..\..\..\ports_common_green\src\txr_byte_release.c +..\..\..\..\ports_common_green\src\txr_event_flags_create.c +..\..\..\..\ports_common_green\src\txr_event_flags_delete.c +..\..\..\..\ports_common_green\src\txr_event_flags_get.c +..\..\..\..\ports_common_green\src\txr_event_flags_info_get.c +..\..\..\..\ports_common_green\src\txr_event_flags_set.c +..\..\..\..\ports_common_green\src\txr_event_flags_set_notify.c +..\..\..\..\ports_common_green\src\txr_ghs.c +..\..\..\..\ports_common_green\src\txr_mutex_create.c +..\..\..\..\ports_common_green\src\txr_mutex_delete.c +..\..\..\..\ports_common_green\src\txr_mutex_get.c +..\..\..\..\ports_common_green\src\txr_mutex_info_get.c +..\..\..\..\ports_common_green\src\txr_mutex_prioritize.c +..\..\..\..\ports_common_green\src\txr_mutex_put.c +..\..\..\..\ports_common_green\src\txr_queue_create.c +..\..\..\..\ports_common_green\src\txr_queue_delete.c +..\..\..\..\ports_common_green\src\txr_queue_flush.c +..\..\..\..\ports_common_green\src\txr_queue_front_send.c +..\..\..\..\ports_common_green\src\txr_queue_info_get.c +..\..\..\..\ports_common_green\src\txr_queue_prioritize.c +..\..\..\..\ports_common_green\src\txr_queue_receive.c +..\..\..\..\ports_common_green\src\txr_queue_send.c +..\..\..\..\ports_common_green\src\txr_queue_send_notify.c +..\..\..\..\ports_common_green\src\txr_semaphore_ceiling_put.c +..\..\..\..\ports_common_green\src\txr_semaphore_create.c +..\..\..\..\ports_common_green\src\txr_semaphore_delete.c +..\..\..\..\ports_common_green\src\txr_semaphore_get.c +..\..\..\..\ports_common_green\src\txr_semaphore_info_get.c +..\..\..\..\ports_common_green\src\txr_semaphore_prioritize.c +..\..\..\..\ports_common_green\src\txr_semaphore_put.c +..\..\..\..\ports_common_green\src\txr_semaphore_put_notify.c +..\..\..\..\ports_common_green\src\txr_thread_create.c +..\..\..\..\ports_common_green\src\txr_thread_delete.c +..\..\..\..\ports_common_green\src\txr_thread_entry_exit_notify.c +..\..\..\..\ports_common_green\src\txr_thread_info_get.c +..\..\..\..\ports_common_green\src\txr_thread_preemption_change.c +..\..\..\..\ports_common_green\src\txr_thread_priority_change.c +..\..\..\..\ports_common_green\src\txr_thread_reset.c +..\..\..\..\ports_common_green\src\txr_thread_resume.c +..\..\..\..\ports_common_green\src\txr_thread_suspend.c +..\..\..\..\ports_common_green\src\txr_thread_terminate.c +..\..\..\..\ports_common_green\src\txr_thread_time_slice_change.c +..\..\..\..\ports_common_green\src\txr_thread_wait_abort.c +..\..\..\..\ports_common_green\src\txr_timer_activate.c +..\..\..\..\ports_common_green\src\txr_timer_change.c +..\..\..\..\ports_common_green\src\txr_timer_create.c +..\..\..\..\ports_common_green\src\txr_timer_deactivate.c +..\..\..\..\ports_common_green\src\txr_timer_delete.c +..\..\..\..\ports_common_green\src\txr_timer_info_get.c diff --git a/ports/cortex_r4/green/example_build/tx_initialize_low_level.arm b/ports/cortex_r4/green/example_build/tx_initialize_low_level.arm new file mode 100644 index 00000000..3be4fc78 --- /dev/null +++ b/ports/cortex_r4/green/example_build/tx_initialize_low_level.arm @@ -0,0 +1,319 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_initialize.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + SVC_MODE = 0xD3 # Disable IRQ/FIQ SVC mode + IRQ_MODE = 0xD2 # Disable IRQ/FIQ IRQ mode + FIQ_MODE = 0xD1 # Disable IRQ/FIQ FIQ mode + SYS_MODE = 0xDF # Disable IRQ/FIQ SYS mode + MODE_MASK = 0x1F # Mode mask + FIQ_STACK_SIZE = 512 # FIQ stack size + IRQ_STACK_SIZE = 1024 # IRQ stack size + SYS_STACK_SIZE = 1024 # SYS stack size + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-R4/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_initialize_low_level(VOID) +{ */ + .globl _tx_initialize_low_level +_tx_initialize_low_level: + + /****** NOTE ****** We must be in SVC MODE at this point. Some monitors + enter this routine in USER mode and require a software interrupt to + change into SVC mode. */ + + /* Save the system stack pointer. */ + /* _tx_thread_system_stack_ptr = (VOID_PTR) (sp); */ + + LDR r1,=_tx_thread_system_stack_ptr # Pickup address of system stack ptr + STR sp, [r1] # Save system stack + + /* Pickup the first available memory address. */ + + LDR r0,=__ghsbegin_free_mem # Pickup free memory address + + /* Setup initial stack pointers for IRQ and FIQ modes. */ + + MRS r12, CPSR # Pickup current CPSR + MOV r1, r0 # Get first available memory +#ifdef TX_ENABLE_IRQ_NESTING + /* Setup the system mode stack for nested interrupt support */ + LDR r2, =SYS_STACK_SIZE # Pickup stack size + BIC r3, r12, MODE_MASK # Clear mode bits + ORR r3, r3, SYS_MODE # Build SYS mode CPSR + MSR CPSR_c, r3 # Enter SYS mode + ADD r1, r1, r2 # Calculate start of SYS stack + SUB r1, r1, 1 # Backup one byte + BIC r1, r1, 7 # Insure 8-byte alignment + MOV sp, r1 # Setup SYS stack pointer +#endif + LDR r2, =FIQ_STACK_SIZE # Pickup stack size + BIC r3, r12, MODE_MASK # Clear mode bits + ORR r3, r3, FIQ_MODE # Build FIQ mode CPSR + MSR CPSR_c, r3 # Enter FIQ mode + ADD r1, r1, r2 # Calculate start of FIQ stack + SUB r1, r1, 1 # Backup one byte + BIC r1, r1, 7 # Insure 8-byte alignment + MOV sp, r1 # Setup FIQ stack pointer + MOV r10, 0 # Clear sl + MOV r11, 0 # Clear fp + LDR r2, =IRQ_STACK_SIZE # Pickup IRQ (system stack size) + BIC r3, r12, MODE_MASK # Clear mode bits + ORR r3, r3, IRQ_MODE # Build IRQ mode CPSR + MSR CPSR_c, r3 # Enter IRQ mode + ADD r1, r1, r2 # Calculate start of IRQ stack + SUB r1, r1, 1 # Backup one byte + BIC r1, r1, 7 # Insure 8-byte alignment + MOV sp, r1 # Setup IRQ stack pointer + MSR CPSR_c, r12 # Restore previous mode + ADD r0, r1, 4 # Adjust the new free memory + + + /* Save the first available memory address. */ + /* _tx_initialize_unused_memory = (VOID_PTR) __ghsbegin_free_mem + [SYS_STACK] + FIQ_STACK + IRQ_STACK; */ + + LDR r2,=_tx_initialize_unused_memory # Pickup unused memory ptr address + STR r0, [r2] # Save first free memory address + + + /* Setup Timer for periodic interrupts. To generate timer interrupts with + the Green Hills simulator, enter the following command in the target + window: timer 9999 irq */ + + /* Done, return to caller. */ + + RET # Return to caller + + .type _tx_initialize_low_level,$function + .size _tx_initialize_low_level,.-_tx_initialize_low_level +/* } */ + + +/* Define shells for each of the interrupt vectors. */ + + .globl __tx_undefined +__tx_undefined: + B __tx_undefined # Undefined handler + + .type __tx_undefined,$function + .size __tx_undefined,.-__tx_undefined + + .globl __tx_swi_interrupt +__tx_swi_interrupt: + B __tx_swi_interrupt # Software interrupt handler + + .type __tx_swi_interrupt,$function + .size __tx_swi_interrupt,.-__tx_swi_interrupt + + .globl __tx_prefetch_handler +__tx_prefetch_handler: + B __tx_prefetch_handler # Prefetch exception handler + + .type __tx_prefetch_handler,$function + .size __tx_prefetch_handler,.-__tx_prefetch_handler + + .globl __tx_abort_handler +__tx_abort_handler: + B __tx_abort_handler # Abort exception handler + + .type __tx_abort_handler,$function + .size __tx_abort_handler,.-__tx_abort_handler + + .globl __tx_reserved_handler +__tx_reserved_handler: + B __tx_reserved_handler # Reserved exception handler + + .type __tx_reserved_handler,$function + .size __tx_reserved_handler,.-__tx_reserved_handler + + .globl __tx_irq_handler + .globl __tx_irq_processing_return +__tx_irq_handler: + + /* Jump to context save to save system context. */ + B _tx_thread_context_save + + .type __tx_irq_handler,$function + .size __tx_irq_handler,.-__tx_irq_handler + +__tx_irq_processing_return: + + /* At this point execution is still in the IRQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. */ + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 0 # Build interrupt code + BL _tx_el_interrupt # Call interrupt event logging +#endif + + /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start + from IRQ mode with interrupts disabled. This routine switches to the + system mode and returns with IRQ interrupts enabled. + + NOTE: It is very important to ensure all IRQ interrupts are cleared + prior to enabling nested IRQ interrupts. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_start +#endif + + + /* For debug purpose, execute the timer interrupt processing here. In + a real system, some kind of status indication would have to be checked + before the timer interrupt handler could be called. */ + BL _tx_timer_interrupt # Timer interrupt handler + + /* Application IRQ handlers can be called here! */ + + /* If interrupt nesting was started earlier, the end of interrupt nesting + service must be called before returning to _tx_thread_context_restore. + This routine returns in processing in IRQ mode with interrupts disabled. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_end +#endif + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 0 # Build interrupt code + BL _tx_el_interrupt_end # Call interrupt event logging +#endif + + /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + .type __tx_irq_processing_return,$function + .size __tx_irq_processing_return,.-__tx_irq_processing_return + +#ifdef TX_ENABLE_FIQ_SUPPORT + + .globl __tx_fiq_handler + .globl __tx_fiq_processing_return +__tx_fiq_handler: + /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save + + .type __tx_fiq_handler,$function + .size __tx_fiq_handler,.-__tx_fiq_handler + +__tx_fiq_processing_return: + + /* At this point execution is still in the FIQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. */ + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 1 # Build interrupt code + BL _tx_el_interrupt # Call interrupt event logging +#endif + + /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start + from FIQ mode with interrupts disabled. This routine switches to the + system mode and returns with FIQ interrupts enabled. + + NOTE: It is very important to ensure all FIQ interrupts are cleared + prior to enabling nested FIQ interrupts. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_start +#endif + + /* Application FIQ handlers can be called here! */ + + /* If interrupt nesting was started earlier, the end of interrupt nesting + service must be called before returning to _tx_thread_fiq_context_restore. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_end +#endif + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 1 # Build interrupt code + BL _tx_el_interrupt_end # Call interrupt event logging +#endif + + /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + .type __tx_fiq_processing_return,$function + .size __tx_fiq_processing_return,.-__tx_fiq_processing_return + +#else + .globl __tx_fiq_handler +__tx_fiq_handler: + B __tx_fiq_handler # FIQ interrupt handler + + .type __tx_fiq_handler,$function + .size __tx_fiq_handler,.-__tx_fiq_handler +#endif + + /* Reference build options and version ID to ensure they come in. */ + +BUILD_OPTIONS: + .data.w _tx_build_options +VERSION_ID: + .data.w _tx_version_id diff --git a/ports/cortex_r4/green/example_build/txe.gpj b/ports/cortex_r4/green/example_build/txe.gpj new file mode 100644 index 00000000..662bcd16 --- /dev/null +++ b/ports/cortex_r4/green/example_build/txe.gpj @@ -0,0 +1,284 @@ +#!gbuild +[Library] + -DTX_ENABLE_EVENT_LOGGING + -I../../../../common/inc + -I../../../../ports_common_green/inc + -I../inc +..\..\..\..\common\inc\tx_api.h +..\..\..\..\common\inc\tx_block_pool.h +..\..\..\..\common\inc\tx_byte_pool.h +..\..\..\..\common\inc\tx_event_flags.h +..\..\..\..\common\inc\tx_initialize.h +..\..\..\..\common\inc\tx_mutex.h +..\..\..\..\common\inc\tx_queue.h +..\..\..\..\common\inc\tx_semaphore.h +..\..\..\..\common\inc\tx_thread.h +..\..\..\..\common\inc\tx_timer.h +..\..\..\..\common\inc\tx_trace.h +..\..\..\..\common\inc\tx_user_sample.h +..\inc\tx_port.h +..\..\..\..\ports_common_green\inc\tx_el.h +..\..\..\..\ports_common_green\inc\tx_ghs.h +..\src\tx_thread_context_restore.arm +..\src\tx_thread_context_save.arm +..\src\tx_thread_fiq_context_restore.arm +..\src\tx_thread_fiq_context_save.arm +..\src\tx_thread_fiq_nesting_end.arm +..\src\tx_thread_fiq_nesting_start.arm +..\src\tx_thread_interrupt_control.arm +..\src\tx_thread_interrupt_disable.arm +..\src\tx_thread_interrupt_restore.arm +..\src\tx_thread_irq_nesting_end.arm +..\src\tx_thread_irq_nesting_start.arm +..\src\tx_thread_schedule.arm +..\src\tx_thread_stack_build.arm +..\src\tx_thread_system_return.arm +..\src\tx_thread_vectored_context_save.arm +..\src\tx_timer_interrupt.arm +..\..\..\..\common\src\tx_block_allocate.c +..\..\..\..\common\src\tx_block_pool_cleanup.c +..\..\..\..\common\src\tx_block_pool_create.c +..\..\..\..\common\src\tx_block_pool_delete.c +..\..\..\..\common\src\tx_block_pool_info_get.c +..\..\..\..\common\src\tx_block_pool_initialize.c +..\..\..\..\common\src\tx_block_pool_performance_info_get.c +..\..\..\..\common\src\tx_block_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_block_pool_prioritize.c +..\..\..\..\common\src\tx_block_release.c +..\..\..\..\common\src\tx_byte_allocate.c +..\..\..\..\common\src\tx_byte_pool_cleanup.c +..\..\..\..\common\src\tx_byte_pool_create.c +..\..\..\..\common\src\tx_byte_pool_delete.c +..\..\..\..\common\src\tx_byte_pool_info_get.c +..\..\..\..\common\src\tx_byte_pool_initialize.c +..\..\..\..\common\src\tx_byte_pool_performance_info_get.c +..\..\..\..\common\src\tx_byte_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_byte_pool_prioritize.c +..\..\..\..\common\src\tx_byte_pool_search.c +..\..\..\..\common\src\tx_byte_release.c +..\..\..\..\common\src\tx_event_flags_cleanup.c +..\..\..\..\common\src\tx_event_flags_create.c +..\..\..\..\common\src\tx_event_flags_delete.c +..\..\..\..\common\src\tx_event_flags_get.c +..\..\..\..\common\src\tx_event_flags_info_get.c +..\..\..\..\common\src\tx_event_flags_initialize.c +..\..\..\..\common\src\tx_event_flags_performance_info_get.c +..\..\..\..\common\src\tx_event_flags_performance_system_info_get.c +..\..\..\..\common\src\tx_event_flags_set.c +..\..\..\..\common\src\tx_event_flags_set_notify.c +..\..\..\..\common\src\tx_initialize_high_level.c +..\..\..\..\common\src\tx_initialize_kernel_enter.c +..\..\..\..\common\src\tx_initialize_kernel_setup.c +..\..\..\..\common\src\tx_mutex_cleanup.c +..\..\..\..\common\src\tx_mutex_create.c +..\..\..\..\common\src\tx_mutex_delete.c +..\..\..\..\common\src\tx_mutex_get.c +..\..\..\..\common\src\tx_mutex_info_get.c +..\..\..\..\common\src\tx_mutex_initialize.c +..\..\..\..\common\src\tx_mutex_performance_info_get.c +..\..\..\..\common\src\tx_mutex_performance_system_info_get.c +..\..\..\..\common\src\tx_mutex_prioritize.c +..\..\..\..\common\src\tx_mutex_priority_change.c +..\..\..\..\common\src\tx_mutex_put.c +..\..\..\..\common\src\tx_queue_cleanup.c +..\..\..\..\common\src\tx_queue_create.c +..\..\..\..\common\src\tx_queue_delete.c +..\..\..\..\common\src\tx_queue_flush.c +..\..\..\..\common\src\tx_queue_front_send.c +..\..\..\..\common\src\tx_queue_info_get.c +..\..\..\..\common\src\tx_queue_initialize.c +..\..\..\..\common\src\tx_queue_performance_info_get.c +..\..\..\..\common\src\tx_queue_performance_system_info_get.c +..\..\..\..\common\src\tx_queue_prioritize.c +..\..\..\..\common\src\tx_queue_receive.c +..\..\..\..\common\src\tx_queue_send.c +..\..\..\..\common\src\tx_queue_send_notify.c +..\..\..\..\common\src\tx_semaphore_ceiling_put.c +..\..\..\..\common\src\tx_semaphore_cleanup.c +..\..\..\..\common\src\tx_semaphore_create.c +..\..\..\..\common\src\tx_semaphore_delete.c +..\..\..\..\common\src\tx_semaphore_get.c +..\..\..\..\common\src\tx_semaphore_info_get.c +..\..\..\..\common\src\tx_semaphore_initialize.c +..\..\..\..\common\src\tx_semaphore_performance_info_get.c +..\..\..\..\common\src\tx_semaphore_performance_system_info_get.c +..\..\..\..\common\src\tx_semaphore_prioritize.c +..\..\..\..\common\src\tx_semaphore_put.c +..\..\..\..\common\src\tx_semaphore_put_notify.c +..\..\..\..\common\src\tx_thread_create.c +..\..\..\..\common\src\tx_thread_delete.c +..\..\..\..\common\src\tx_thread_entry_exit_notify.c +..\..\..\..\common\src\tx_thread_identify.c +..\..\..\..\common\src\tx_thread_info_get.c +..\..\..\..\common\src\tx_thread_initialize.c +..\..\..\..\common\src\tx_thread_performance_info_get.c +..\..\..\..\common\src\tx_thread_performance_system_info_get.c +..\..\..\..\common\src\tx_thread_preemption_change.c +..\..\..\..\common\src\tx_thread_priority_change.c +..\..\..\..\common\src\tx_thread_relinquish.c +..\..\..\..\common\src\tx_thread_reset.c +..\..\..\..\common\src\tx_thread_resume.c +..\..\..\..\common\src\tx_thread_shell_entry.c +..\..\..\..\common\src\tx_thread_sleep.c +..\..\..\..\common\src\tx_thread_stack_analyze.c +..\..\..\..\common\src\tx_thread_stack_error_handler.c +..\..\..\..\common\src\tx_thread_stack_error_notify.c +..\..\..\..\common\src\tx_thread_suspend.c +..\..\..\..\common\src\tx_thread_system_preempt_check.c +..\..\..\..\common\src\tx_thread_system_resume.c +..\..\..\..\common\src\tx_thread_system_suspend.c +..\..\..\..\common\src\tx_thread_terminate.c +..\..\..\..\common\src\tx_thread_time_slice.c +..\..\..\..\common\src\tx_thread_time_slice_change.c +..\..\..\..\common\src\tx_thread_timeout.c +..\..\..\..\common\src\tx_thread_wait_abort.c +..\..\..\..\common\src\tx_time_get.c +..\..\..\..\common\src\tx_time_set.c +..\..\..\..\common\src\tx_timer_activate.c +..\..\..\..\common\src\tx_timer_change.c +..\..\..\..\common\src\tx_timer_create.c +..\..\..\..\common\src\tx_timer_deactivate.c +..\..\..\..\common\src\tx_timer_delete.c +..\..\..\..\common\src\tx_timer_expiration_process.c +..\..\..\..\common\src\tx_timer_info_get.c +..\..\..\..\common\src\tx_timer_initialize.c +..\..\..\..\common\src\tx_timer_performance_info_get.c +..\..\..\..\common\src\tx_timer_performance_system_info_get.c +..\..\..\..\common\src\tx_timer_system_activate.c +..\..\..\..\common\src\tx_timer_system_deactivate.c +..\..\..\..\common\src\tx_timer_thread_entry.c +..\..\..\..\common\src\tx_trace_buffer_full_notify.c +..\..\..\..\common\src\tx_trace_disable.c +..\..\..\..\common\src\tx_trace_enable.c +..\..\..\..\common\src\tx_trace_event_filter.c +..\..\..\..\common\src\tx_trace_event_unfilter.c +..\..\..\..\common\src\tx_trace_initialize.c +..\..\..\..\common\src\tx_trace_interrupt_control.c +..\..\..\..\common\src\tx_trace_isr_enter_insert.c +..\..\..\..\common\src\tx_trace_isr_exit_insert.c +..\..\..\..\common\src\tx_trace_object_register.c +..\..\..\..\common\src\tx_trace_object_unregister.c +..\..\..\..\common\src\tx_trace_user_event_insert.c +..\..\..\..\common\src\txe_block_allocate.c +..\..\..\..\common\src\txe_block_pool_create.c +..\..\..\..\common\src\txe_block_pool_delete.c +..\..\..\..\common\src\txe_block_pool_info_get.c +..\..\..\..\common\src\txe_block_pool_prioritize.c +..\..\..\..\common\src\txe_block_release.c +..\..\..\..\common\src\txe_byte_allocate.c +..\..\..\..\common\src\txe_byte_pool_create.c +..\..\..\..\common\src\txe_byte_pool_delete.c +..\..\..\..\common\src\txe_byte_pool_info_get.c +..\..\..\..\common\src\txe_byte_pool_prioritize.c +..\..\..\..\common\src\txe_byte_release.c +..\..\..\..\common\src\txe_event_flags_create.c +..\..\..\..\common\src\txe_event_flags_delete.c +..\..\..\..\common\src\txe_event_flags_get.c +..\..\..\..\common\src\txe_event_flags_info_get.c +..\..\..\..\common\src\txe_event_flags_set.c +..\..\..\..\common\src\txe_event_flags_set_notify.c +..\..\..\..\common\src\txe_mutex_create.c +..\..\..\..\common\src\txe_mutex_delete.c +..\..\..\..\common\src\txe_mutex_get.c +..\..\..\..\common\src\txe_mutex_info_get.c +..\..\..\..\common\src\txe_mutex_prioritize.c +..\..\..\..\common\src\txe_mutex_put.c +..\..\..\..\common\src\txe_queue_create.c +..\..\..\..\common\src\txe_queue_delete.c +..\..\..\..\common\src\txe_queue_flush.c +..\..\..\..\common\src\txe_queue_front_send.c +..\..\..\..\common\src\txe_queue_info_get.c +..\..\..\..\common\src\txe_queue_prioritize.c +..\..\..\..\common\src\txe_queue_receive.c +..\..\..\..\common\src\txe_queue_send.c +..\..\..\..\common\src\txe_queue_send_notify.c +..\..\..\..\common\src\txe_semaphore_ceiling_put.c +..\..\..\..\common\src\txe_semaphore_create.c +..\..\..\..\common\src\txe_semaphore_delete.c +..\..\..\..\common\src\txe_semaphore_get.c +..\..\..\..\common\src\txe_semaphore_info_get.c +..\..\..\..\common\src\txe_semaphore_prioritize.c +..\..\..\..\common\src\txe_semaphore_put.c +..\..\..\..\common\src\txe_semaphore_put_notify.c +..\..\..\..\common\src\txe_thread_create.c +..\..\..\..\common\src\txe_thread_delete.c +..\..\..\..\common\src\txe_thread_entry_exit_notify.c +..\..\..\..\common\src\txe_thread_info_get.c +..\..\..\..\common\src\txe_thread_preemption_change.c +..\..\..\..\common\src\txe_thread_priority_change.c +..\..\..\..\common\src\txe_thread_relinquish.c +..\..\..\..\common\src\txe_thread_reset.c +..\..\..\..\common\src\txe_thread_resume.c +..\..\..\..\common\src\txe_thread_suspend.c +..\..\..\..\common\src\txe_thread_terminate.c +..\..\..\..\common\src\txe_thread_time_slice_change.c +..\..\..\..\common\src\txe_thread_wait_abort.c +..\..\..\..\common\src\txe_timer_activate.c +..\..\..\..\common\src\txe_timer_change.c +..\..\..\..\common\src\txe_timer_create.c +..\..\..\..\common\src\txe_timer_deactivate.c +..\..\..\..\common\src\txe_timer_delete.c +..\..\..\..\common\src\txe_timer_info_get.c +..\..\..\..\ports_common_green\src\tx_el.c +..\..\..\..\ports_common_green\src\tx_ghs.c +..\..\..\..\ports_common_green\src\tx_ghse.c +..\..\..\..\ports_common_green\src\txr_block_allocate.c +..\..\..\..\ports_common_green\src\txr_block_pool_create.c +..\..\..\..\ports_common_green\src\txr_block_pool_delete.c +..\..\..\..\ports_common_green\src\txr_block_pool_info_get.c +..\..\..\..\ports_common_green\src\txr_block_pool_prioritize.c +..\..\..\..\ports_common_green\src\txr_block_release.c +..\..\..\..\ports_common_green\src\txr_byte_allocate.c +..\..\..\..\ports_common_green\src\txr_byte_pool_create.c +..\..\..\..\ports_common_green\src\txr_byte_pool_delete.c +..\..\..\..\ports_common_green\src\txr_byte_pool_info_get.c +..\..\..\..\ports_common_green\src\txr_byte_pool_prioritize.c +..\..\..\..\ports_common_green\src\txr_byte_release.c +..\..\..\..\ports_common_green\src\txr_event_flags_create.c +..\..\..\..\ports_common_green\src\txr_event_flags_delete.c +..\..\..\..\ports_common_green\src\txr_event_flags_get.c +..\..\..\..\ports_common_green\src\txr_event_flags_info_get.c +..\..\..\..\ports_common_green\src\txr_event_flags_set.c +..\..\..\..\ports_common_green\src\txr_event_flags_set_notify.c +..\..\..\..\ports_common_green\src\txr_ghs.c +..\..\..\..\ports_common_green\src\txr_mutex_create.c +..\..\..\..\ports_common_green\src\txr_mutex_delete.c +..\..\..\..\ports_common_green\src\txr_mutex_get.c +..\..\..\..\ports_common_green\src\txr_mutex_info_get.c +..\..\..\..\ports_common_green\src\txr_mutex_prioritize.c +..\..\..\..\ports_common_green\src\txr_mutex_put.c +..\..\..\..\ports_common_green\src\txr_queue_create.c +..\..\..\..\ports_common_green\src\txr_queue_delete.c +..\..\..\..\ports_common_green\src\txr_queue_flush.c +..\..\..\..\ports_common_green\src\txr_queue_front_send.c +..\..\..\..\ports_common_green\src\txr_queue_info_get.c +..\..\..\..\ports_common_green\src\txr_queue_prioritize.c +..\..\..\..\ports_common_green\src\txr_queue_receive.c +..\..\..\..\ports_common_green\src\txr_queue_send.c +..\..\..\..\ports_common_green\src\txr_queue_send_notify.c +..\..\..\..\ports_common_green\src\txr_semaphore_ceiling_put.c +..\..\..\..\ports_common_green\src\txr_semaphore_create.c +..\..\..\..\ports_common_green\src\txr_semaphore_delete.c +..\..\..\..\ports_common_green\src\txr_semaphore_get.c +..\..\..\..\ports_common_green\src\txr_semaphore_info_get.c +..\..\..\..\ports_common_green\src\txr_semaphore_prioritize.c +..\..\..\..\ports_common_green\src\txr_semaphore_put.c +..\..\..\..\ports_common_green\src\txr_semaphore_put_notify.c +..\..\..\..\ports_common_green\src\txr_thread_create.c +..\..\..\..\ports_common_green\src\txr_thread_delete.c +..\..\..\..\ports_common_green\src\txr_thread_entry_exit_notify.c +..\..\..\..\ports_common_green\src\txr_thread_info_get.c +..\..\..\..\ports_common_green\src\txr_thread_preemption_change.c +..\..\..\..\ports_common_green\src\txr_thread_priority_change.c +..\..\..\..\ports_common_green\src\txr_thread_reset.c +..\..\..\..\ports_common_green\src\txr_thread_resume.c +..\..\..\..\ports_common_green\src\txr_thread_suspend.c +..\..\..\..\ports_common_green\src\txr_thread_terminate.c +..\..\..\..\ports_common_green\src\txr_thread_time_slice_change.c +..\..\..\..\ports_common_green\src\txr_thread_wait_abort.c +..\..\..\..\ports_common_green\src\txr_timer_activate.c +..\..\..\..\ports_common_green\src\txr_timer_change.c +..\..\..\..\ports_common_green\src\txr_timer_create.c +..\..\..\..\ports_common_green\src\txr_timer_deactivate.c +..\..\..\..\ports_common_green\src\txr_timer_delete.c +..\..\..\..\ports_common_green\src\txr_timer_info_get.c diff --git a/ports/cortex_r4/green/inc/tx_port.h b/ports/cortex_r4/green/inc/tx_port.h new file mode 100644 index 00000000..c066849d --- /dev/null +++ b/ports/cortex_r4/green/inc/tx_port.h @@ -0,0 +1,392 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-R4/Green Hills */ +/* 6.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include +#include +#include "tx_ghs.h" + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define constants for Green Hills EventAnalyzer. */ + +/* Define the number of ticks per second. This informs the EventAnalyzer what the timestamps + represent. By default, this is set to 1,000,000 i.e., one tick every microsecond. */ + +#define TX_EL_TICKS_PER_SECOND 1000000 + +/* Define the method of how to get the upper and lower 32-bits of the time stamp. By default, simply + simulate the time-stamp source with a counter. */ + +#define read_tbu() _tx_el_time_base_upper +#define read_tbl() ++_tx_el_time_base_lower + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 VOID * tx_thread_eh_globals; +#define TX_THREAD_EXTENSION_2 int Errno; /* errno. */ +#define TX_THREAD_EXTENSION_3 char * strtok_saved_pos; /* strtok() position. */ + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + +#if (__GHS_VERSION_NUMBER >= 500) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) \ + { \ + extern void __tx_cpp_exception_init(TX_THREAD *thread_ptr); \ + __tx_cpp_exception_init(thread_ptr); \ + } +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) \ + { \ + #pragma weak __cpp_exception_init \ + extern void __cpp_exception_init(void **); \ + static void (*const cpp_init_funcp)(void **) = __cpp_exception_init; \ + if (cpp_init_funcp) \ + __cpp_exception_init(&(thread_ptr -> tx_thread_eh_globals)); \ + } +#endif + +#if (__GHS_VERSION_NUMBER >= 500) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) \ + { \ + extern void __tx_cpp_exception_cleanup(TX_THREAD *thread_ptr); \ + __tx_cpp_exception_cleanup(thread_ptr); \ + } +#else +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) \ + { \ + #pragma weak __cpp_exception_cleanup \ + extern void __cpp_exception_cleanup(void **); \ + static void (*const cpp_cleanup_funcp)(void **) = \ + __cpp_exception_cleanup; \ + if (cpp_cleanup_funcp) \ + __cpp_exception_cleanup(&(thread_ptr -> tx_thread_eh_globals)); \ + } +#endif + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + b = __CLZ32(m); \ + b = 31 - b; + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#if defined(__THUMB) + +unsigned int _tx_thread_interrupt_disable(void); +void _tx_thread_interrupt_restore(unsigned int new_posture); + +#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); + +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; + +#if defined(__GHS_VERSION_NUMBER) && (__GHS_VERSION_NUMBER >= 350) + +/* Define ThreadX interrupt lockout and restore macros using + compiler built-in functions if using Green Hills ARM compiler + version 3.5 or later. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_DISABLE interrupt_save = __GETSR(); \ + __SETSR(interrupt_save | 0xC0); + +#define TX_RESTORE __SETSR(interrupt_save); +#else +#define TX_DISABLE interrupt_save = __GETSR(); \ + __SETSR(interrupt_save | 0x80); + +#define TX_RESTORE __SETSR(interrupt_save); +#endif + +#else + +/* Define ThreadX interrupt lockout and restore macros using + asm macros if using Green Hills ARM compiler earlier than + version 3.5. */ + +asm int disable_ints(void) +{ +% + MRS r0,CPSR +#ifdef TX_BEFORE_ARMV6 +#ifdef TX_ENABLE_FIQ_SUPPORT + ORR r1,r0,0xC0 +#else + ORR r1,r0,0x80 +#endif + MSR CPSR_c,r1 +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if +#else + CPSID i +#endif +#endif +%error +} + +asm void restore_ints(int a) +{ +%reg a + MSR CPSR_c,a +%mem a + LDR r0,a + MSR CPSR_c,r0 +%error +} + +#define TX_DISABLE interrupt_save = disable_ints(); + +#define TX_RESTORE restore_ints(interrupt_save); +#endif +#endif + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/Green Hills Version 6.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + diff --git a/ports/cortex_r4/green/readme_threadx.txt b/ports/cortex_r4/green/readme_threadx.txt new file mode 100644 index 00000000..7b358c23 --- /dev/null +++ b/ports/cortex_r4/green/readme_threadx.txt @@ -0,0 +1,510 @@ + Microsoft's Azure RTOS ThreadX for Cortex-R4 + + Using the Green Hills Software Tools + +1. Open the ThreadX Project Workspace + +In order to build the ThreadX library and the ThreadX demonstration first load +the Azure RTOS Workspace azure_rtos_workspace.gpj, which is located inside the +"example_build" directory. + + +2. Building the ThreadX run-time Library + +Building the ThreadX library is easy; simply select the MULTI project file +tx.gpj and then select the build button. You should now observe the +compilation and assembly of the ThreadX library. This project build produces +the ThreadX library file tx.a. + + +3. Demonstration System + +The ThreadX demonstration is designed to execute under the MULTI environment +on the Green Hills Cortex-R4 simulator. The instructions that follow describe +how to get the ThreadX evaluation running under the MULTI Cortex-R4 simulation +environment. + +Building the demonstration is easy; simply select the MULTI project file +sample_threadx.gpj. At this point, select the "Project Build" button and observe +the compilation, assembly, and linkage of the ThreadX demonstration application. + +After the demonstration is built, invoke the MULTI ARM simulator by selecting +the simulator connection from within the sample_threadx.con connection file. +Once connected to the simulator, select the "Debug" button. You should now +observe the main function of sample_threadx.c. + +At this point, you should setup a simulated timer interrupt for ThreadX +by entering "timer 9999 irq" in the "target" window of the debugger. + +You are now ready to execute the ThreadX demonstration system. Select +breakpoints and data watches to observe the execution of the sample_threadx.c +application. + + +4. EventAnalyzer Demonstration + +To build a demonstration system that also logs events for the MULTI EventAnalyzer, +perform the same steps as the regular demo, except build the ThreadX library with +txe.gpj file and use the sample_threadx_el.gpj build file to build the demonstration. +The resulting image will log all system events, which can then be displayed by the +MULTI EventAnalyzer. + + +5. System Initialization + +The system entry point using the Green Hills tools is at the label _start. +This is defined within the crt0.arm file supplied by Green Hills. In addition, +this is where all static and global preset C variable initialization +processing is called from. + +After the Green Hills startup function returns, ThreadX initialization is +called. The main initialization function is _tx_initialize_low_level and +is located in the file tx_initialize_low_level.arm. This function is responsible +for setting up various system data structures, interrupt vectors, and the +periodic timer interrupt source of ThreadX. + +In addition, _tx_initialize_low_level determines where the first available +RAM memory address is located. This address is supplied to tx_application_define. + +By default, the first available RAM memory address is assumed to start at the +beginning of the ThreadX section .free_mem. If changes are made to the +sample_threadx.ld file, the .free_mem section should remain the last allocated +section in the main RAM area. The starting address of this section is passed +to tx_application_define. + + +6. User defines + +The following defines and their associated action are as follows: + + Define Meaning + + TX_ENABLE_IRQ_NESTING If defined, this brings in special IRQ + interrupt nesting logic into the ThreadX + library. This define should be applied + to the entire ThreadX library. + + TX_ENABLE_FIQ_NESTING If defined, this brings in special FIQ + interrupt nesting logic into the ThreadX + library. This define should be applied + to the entire ThreadX library and the + define TX_ENABLE_FIQ_SUPPORT should also + be defined. + + TX_ENABLE_FIQ_SUPPORT If defined, this brings in FIQ context + save and restore logic necessary for + applications to call ThreadX services from + FIQ interrupt handlers. This define + should be applied to the entire ThreadX + library. + + + TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, + this define causes basic ThreadX error + checking to be disabled. Please see + Chapter 4 in the "ThreadX User Guide" + for more details. + + TX_ENABLE_EVENT_LOGGING This define enables event logging for any + or all of the ThreadX source code. If this + option is used anywhere, the tx_initialize_high_level.c + file must be compiled with it as well, since this + is where the event log is initialized. + + TX_NO_EVENT_INFO This is a sub-option for event logging. + If this is enabled, only basic information + is saved in the log. + + TX_ENABLE_EVENT_FILTERS This is also a sub-option for event-logging. + If this is enabled, run-time filtering logic + is added to the event logging code. + + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By + default, this value is set to 32 priority levels. + + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found + in tx_port.h. + + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default + value is port-specific and is found in tx_port.h. + + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined + in tx_port.h. + + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. + By default, this option is not defined. + + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. + By default, this option is not defined. + + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is + not defined. + + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. + By default, this option is not defined. + + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. + By default, this option is not defined. + + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. + By default, this option is not defined. + + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size + and improves performance. + + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is + not defined. + + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is + not defined. + + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option + is not defined. + + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is + not defined. + + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is + not defined. + + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is + not defined. + + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is + not defined. + + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is + not defined. + + + +7. Register Usage and Stack Frames + +The Green Hills compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) +are scratch registers for each function. All other registers used by a C +function must be preserved by the function. ThreadX takes advantage of this +in situations where a context switch happens as a result of making a ThreadX +service call (which is itself a C function). In such cases, the saved +context of a thread is only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 CPSR CPSR + 0x08 r0 (a1) r4 (v1) + 0x0C r1 (a2) r5 (v2) + 0x10 r2 (a3) r6 (v3) + 0x14 r3 (a4) r7 (v4) + 0x18 r4 (v1) r8 (v5) + 0x1C r5 (v2) r9 (v6) + 0x20 r6 (v3) r10 (v7) + 0x24 r7 (v4) r11 (fp) + 0x28 r8 (v5) r14 (lr) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) + 0x3C r14 (lr) + 0x40 PC + + +8. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make ThreadX run faster, you can change the tx.gpj project +to disable debug information and enable the desired optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined before tx_api.h is included. + + +9. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-R4 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +9.1 Vector Area + +The Cortex-R4 vectors start at address zero. The demonstration system reset.arm +file contains the reset section (which contains all the ARM vectors) and is +typically loaded at address zero. On actual hardware platforms, this section +might have to be copied to address 0. + +9.2 IRQ ISRs + +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested +IRQ interrupts. The following sub-sections define the IRQ capabilities. + + +9.2.1 Standard IRQ ISRs + +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +is the default IRQ handler defined in tx_initialize_low_level.arm: + + + .globl __tx_irq_handler + .globl __tx_irq_processing_return +__tx_irq_handler: + + /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return: + + /* At this point execution is still in the IRQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. Note + that IRQ interrupts are still disabled upon return from the context + save function. */ + + /* Application ISR call(s) go here! */ + + /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +9.2.2 Vectored IRQ ISRs + +The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified +by the particular implementation. The following is an example IRQ handler defined in +tx_initialize_low_level.arm: + + .globl __tx_irq_example_handler +__tx_irq_example_handler: + + /* Call context save to save system context. */ + + STMDB sp!, {r0-r3} # Save some scratch registers + MRS r0, SPSR # Pickup saved SPSR + SUB lr, lr, #4 # Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} # Store other scratch registers + BL _tx_thread_vectored_context_save # Call the vectored IRQ context save + + /* At this point execution is still in the IRQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. Note + that IRQ interrupts are still disabled upon return from the context + save function. */ + + /* Application ISR call goes here! */ + + /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +9.2.3 Nested IRQ Support + +By default, nested IRQ interrupt support is not enabled. To enable nested +IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING +defined. With this defined, two new IRQ interrupt management services are +available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. +These function should be called between the IRQ context save and restore +calls. + +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +by switching from IRQ mode to SYS mode and enabling IRQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.arm. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables nesting +by disabling IRQ interrupts and switching back to IRQ mode in preparation for +the IRQ context restore service. + +The following is an example of enabling IRQ nested interrupts in the +typical IRQ handler: + + .globl __tx_irq_handler + .globl __tx_irq_processing_return +__tx_irq_handler: + + /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return: + + /* Enable nested IRQ interrupts. NOTE: Since this service returns + with IRQ interrupts enabled, all IRQ interrupt sources must be + cleared prior to calling this service. */ + BL _tx_thread_irq_nesting_start + + /* Application ISR call(s) go here! */ + + /* Disable nested IRQ interrupts. The mode is switched back to + IRQ mode and IRQ interrupts are disable upon return. */ + BL _tx_thread_irq_nesting_end + + /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +9.3 FIQ Interrupts + +By default, Cortex-R4 FIQ interrupts are left completely enabled by ThreadX. +Of course, this means that the application is fully responsible for +saving/restoring any registers used in the FIQ ISR processing. In addition, +no ThreadX service calls are allowed from the default FIQ ISRs. The default +FIQ interrupt shell is located in tx_initialize_low_level.arm. + +9.3.1 Managed FIQ Interrupts + +Full ThreadX management of FIQ interrupts is provided if the ThreadX sources +are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built +this way, the FIQ interrupt handlers are very similar to the IRQ interrupt +handlers defined previously. The following is default FIQ handler +defined in tx_initialize_low_level.arm: + + + .globl __tx_fiq_handler + .globl __tx_fiq_processing_return +__tx_fiq_handler: + + /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: + + /* At this point execution is still in the FIQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. */ + + /* Application FIQ handlers can be called here! */ + + /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +9.3.1.1 Nested FIQ Support + +By default, nested FIQ interrupt support is not enabled. To enable nested +FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING +defined. With this defined, two new FIQ interrupt management services are +available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. +These function should be called between the FIQ context save and restore +calls. + +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +by switching from FIQ mode to SYS mode and enabling FIQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.arm. When nested FIQ interrupts are no longer +required, calling the _tx_thread_fiq_nesting_end service disables nesting by +disabling FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +context restore service. + +The following is an example of enabling FIQ nested interrupts in the +typical FIQ handler: + + + .globl __tx_fiq_handler + .globl __tx_fiq_processing_return +__tx_fiq_handler: + + /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: + + /* At this point execution is still in the FIQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. */ + + /* Enable nested FIQ interrupts. NOTE: Since this service returns + with FIQ interrupts enabled, all FIQ interrupt sources must be + cleared prior to calling this service. */ + BL _tx_thread_fiq_nesting_start + + /* Application FIQ handlers can be called here! */ + + /* Disable nested FIQ interrupts. The mode is switched back to + FIQ mode and FIQ interrupts are disable upon return. */ + BL _tx_thread_fiq_nesting_end + + /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + + +10. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional. However, all other +ThreadX services are operational without a periodic timer source. + +To add the timer interrupt processing, simply make a call to +_tx_timer_interrupt in the IRQ processing. An example of this can be +found in the file tx_initialize_low_level.arm. + + +11. Thumb/Cortex-R4 Mixed Mode + +By default, ThreadX is setup for running in Cortex-R4 32-bit mode. This is +also true for the demonstration system. It is possible to build any +ThreadX file and/or the application in Thumb mode. The only exception +to this is the file tx_thread_shell_entry.c. This file must always be +built in 32-bit mode. + + +12. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +05/19/2020 Initial ThreadX version of Cortex-R4/Green Hills port. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_r4/green/src/tx_thread_context_restore.arm b/ports/cortex_r4/green/src/tx_thread_context_restore.arm new file mode 100644 index 00000000..c4f3c21c --- /dev/null +++ b/ports/cortex_r4/green/src/tx_thread_context_restore.arm @@ -0,0 +1,246 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # Disable IRQ and FIQ interrupts +#else + DISABLE_INTS = 0x80 # Disable IRQ interrupts +#endif + SVC_MODE = (0x13 | DISABLE_INTS) # SVC mode + IRQ_MODE = (0x12 | DISABLE_INTS) # IRQ mode + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore Cortex-R4/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores the interrupt context if it is processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_restore(VOID) +{ */ + .globl _tx_thread_context_restore +_tx_thread_context_restore: + + /* Lockout interrupts. */ + +#ifdef TX_BEFORE_ARMV6 + MRS r3, CPSR # Pickup current CPSR + ORR r0, r3, DISABLE_INTS # Build interrupt disable value + MSR CPSR_c, r0 # Lockout interrupts +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if # Disable IRQ and FIQ interrupts +#else + CPSID i # Disable IRQ interrupts +#endif +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR exit function to indicate an ISR is complete. */ + + BL _tx_execution_isr_exit # Call the ISR exit function +#endif + + /* Determine if interrupts are nested. */ + /* if (--_tx_thread_system_state) + { */ + + LDR r3, =_tx_thread_system_state # Pickup address of system state var + LDR r2, [r3] # Pickup system state + SUB r2, r2, 1 # Decrement the counter + STR r2, [r3] # Store the counter + CMP r2, 0 # Was this the first interrupt? + BEQ __tx_thread_not_nested_restore # If so, not a nested restore + + /* Interrupts are nested. */ + + /* Just recover the saved registers and return to the point of + interrupt. */ + + LDMIA sp!, {r0, r10, r12, lr} # Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 # Put SPSR back + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOVS pc, lr # Return to point of interrupt + + /* } */ +__tx_thread_not_nested_restore: + + /* Determine if a thread was interrupted and no preemption is required. */ + /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) + || (_tx_thread_preempt_disable)) + { */ + + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup actual current thread pointer + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_idle_system_restore # Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable # Pickup preempt disable address + LDR r2, [r3] # Pickup actual preempt disable flag + CMP r2, 0 # Is it set? + BNE __tx_thread_no_preempt_restore # Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr # Pickup address of execute thread ptr + LDR r2, [r3] # Pickup actual execute thread pointer + CMP r0, r2 # Is the same thread highest priority? + BNE __tx_thread_preempt_restore # No, preemption needs to happen + + +__tx_thread_no_preempt_restore: + + /* Restore interrupted thread or ISR. */ + + /* Pickup the saved stack pointer. */ + /* tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; */ + + /* Recover the saved context and return to the point of interrupt. */ + + LDMIA sp!, {r0, r10, r12, lr} # Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 # Put SPSR back + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOVS pc, lr # Return to point of interrupt + + /* } + else + { */ +__tx_thread_preempt_restore: + + LDMIA sp!, {r3, r10, r12, lr} # Recover temporarily saved registers + MOV r1, lr # Save lr (point of interrupt) + MOV r2, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r2 # Enter SVC mode + STR r1, [sp, -4]! # Save point of interrupt + STMDB sp!, {r4-r12, lr} # Save upper half of registers + MOV r4, r3 # Save SPSR in r4 + MOV r2, IRQ_MODE # Build IRQ mode CPSR + MSR CPSR_c, r2 # Re-enter IRQ mode + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOV r5, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r5 # Enter SVC mode + STMDB sp!, {r0-r3} # Save r0-r3 on thread's stack + MOV r3, 1 # Build interrupt stack type + STMDB sp!, {r3, r4} # Save interrupt stack type and SPSR + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup current thread pointer + STR sp, [r0, 8] # Save stack pointer in thread control + /* # block */ + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r4, r0 # Save r0 + MOV r5, r1 # Save r1 + BL _tx_el_thread_preempted # Call thread preempted routine + MOV r0, r4 # Restore r0 + MOV r1, r5 # Restore r1 +#endif + + /* Save the remaining time-slice and disable it. */ + /* if (_tx_timer_time_slice) + { */ + + LDR r3, =_tx_timer_time_slice # Pickup time-slice variable address + LDR r2, [r3] # Pickup time-slice + CMP r2, 0 # Is it active? + BEQ __tx_thread_dont_save_ts # No, don't save it + + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + STR r2, [r0, 24] # Save thread's time-slice + MOV r2, 0 # Clear value + STR r2, [r3] # Disable global time-slice flag + + /* } */ +__tx_thread_dont_save_ts: + + + /* Clear the current task pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + MOV r0, 0 # NULL value + STR r0, [r1] # Clear current thread pointer + + /* Return to the scheduler. */ + /* _tx_thread_schedule(); */ + + B _tx_thread_schedule # Return to scheduler + /* } */ + +__tx_thread_idle_system_restore: + + /* Just return back to the scheduler! */ + + + MOV r3, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r3 # Lockout interrupts + B _tx_thread_schedule # Return to scheduler + + .type _tx_thread_context_restore,$function + .size _tx_thread_context_restore,.-_tx_thread_context_restore + +/* } */ + diff --git a/ports/cortex_r4/green/src/tx_thread_context_save.arm b/ports/cortex_r4/green/src/tx_thread_context_save.arm new file mode 100644 index 00000000..3b9c1484 --- /dev/null +++ b/ports/cortex_r4/green/src/tx_thread_context_save.arm @@ -0,0 +1,207 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # IRQ & FIQ interrupts disabled +#else + DISABLE_INTS = 0x80 # IRQ interrupts disabled +#endif + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save Cortex-R4/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_save(VOID) +{ */ + .globl _tx_thread_context_save +_tx_thread_context_save: + + /* Upon entry to this routine, it is assumed that IRQ interrupts are locked + out, we are in IRQ mode, and all registers are intact. */ + + /* Check for a nested interrupt condition. */ + /* if (_tx_thread_system_state++) + { */ + + STMDB sp!, {r0-r3} # Save some working registers + +#ifdef TX_ENABLE_FIQ_SUPPORT +#ifdef TX_BEFORE_ARMV6 + MRS r0, CPSR # Pickup the CPSR + ORR r0, r0, DISABLE_INTS # Build disable interrupt CPSR + MSR CPSR_c, r0 # Disable interrupts +#else + CPSID if # Disable FIQ interrupts +#endif +#endif + + LDR r3, =_tx_thread_system_state # Pickup address of system state var + LDR r2, [r3] # Pickup system state + CMP r2, 0 # Is this the first interrupt? + BEQ __tx_thread_not_nested_save # Yes, not a nested context save + + /* Nested interrupt condition. */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + + /* Save the rest of the scratch registers on the stack and return to the + calling ISR. */ + + MRS r0, SPSR # Pickup saved SPSR + SUB lr, lr, 4 # Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} # Store other registers + + /* Return to the ISR. */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + B __tx_irq_processing_return # Continue IRQ processing + +__tx_thread_not_nested_save: + /* } */ + + /* Otherwise, not nested, check to see if a thread was running. */ + /* else if (_tx_thread_current_ptr) + { */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup current thread pointer + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_idle_system_save # If so, interrupt occurred in + /* # scheduling loop - nothing needs saving! */ + + /* Save minimal context of interrupted thread. */ + + MRS r2, SPSR # Pickup saved SPSR + SUB lr, lr, 4 # Adjust point of interrupt + STMDB sp!, {r2, r10, r12, lr} # Store other registers + + /* Save the current stack pointer in the thread's control block. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ + + /* Switch to the system stack. */ + /* sp = _tx_thread_system_stack_ptr; */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + B __tx_irq_processing_return # Continue IRQ processing + + /* } + else + { */ + +__tx_thread_idle_system_save: + + /* Interrupt occurred in the scheduling loop. */ + + /* Not much to do here, just adjust the stack pointer, and return to IRQ + processing. */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + ADD sp, sp, 16 # Recover saved registers + B __tx_irq_processing_return # Continue IRQ processing + + .type _tx_thread_context_save,$function + .size _tx_thread_context_save,.-_tx_thread_context_save + + /* } +} */ + diff --git a/ports/cortex_r4/green/src/tx_thread_fiq_context_restore.arm b/ports/cortex_r4/green/src/tx_thread_fiq_context_restore.arm new file mode 100644 index 00000000..f2784a06 --- /dev/null +++ b/ports/cortex_r4/green/src/tx_thread_fiq_context_restore.arm @@ -0,0 +1,251 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + SVC_MODE = 0xD3 # SVC mode + FIQ_MODE = 0xD1 # FIQ mode +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # Disable IRQ and FIQ interrupts +#else + DISABLE_INTS = 0x80 # Disable IRQ interrupts +#endif + MODE_MASK = 0x1F # Mode mask + IRQ_MODE_BITS = 0x12 # IRQ mode bits + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_context_restore Cortex-R4/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores the fiq interrupt context when processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* FIQ ISR Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_fiq_context_restore(VOID) +{ */ + .globl _tx_thread_fiq_context_restore +_tx_thread_fiq_context_restore: + + /* Lockout interrupts. */ + +#ifdef TX_BEFORE_ARMV6 + MRS r3, CPSR # Pickup current CPSR + ORR r0, r3, DISABLE_INTS # Build interrupt disable value + MSR CPSR_c, r0 # Lockout interrupts +#else + CPSID if # Disable IRQ and FIQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR exit function to indicate an ISR is complete. */ + + BL _tx_execution_isr_exit # Call the ISR exit function +#endif + + /* Determine if interrupts are nested. */ + /* if (--_tx_thread_system_state) + { */ + + LDR r3, =_tx_thread_system_state # Pickup address of system state var + LDR r2, [r3] # Pickup system state + SUB r2, r2, 1 # Decrement the counter + STR r2, [r3] # Store the counter + CMP r2, 0 # Was this the first interrupt? + BEQ __tx_thread_fiq_not_nested_restore # If so, not a nested restore + + /* Interrupts are nested. */ + + /* Just recover the saved registers and return to the point of + interrupt. */ + + LDMIA sp!, {r0, r10, r12, lr} # Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 # Put SPSR back + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOVS pc, lr # Return to point of interrupt + + /* } */ +__tx_thread_fiq_not_nested_restore: + + /* Determine if a thread was interrupted and no preemption is required. */ + /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) + || (_tx_thread_preempt_disable)) + { */ + + LDR r1, [sp] # Pickup the saved SPSR + MOV r2, MODE_MASK # Build mask to isolate the interrupted mode + AND r1, r1, r2 # Isolate mode bits + CMP r1, IRQ_MODE_BITS # Was an interrupt taken in IRQ mode before we + /* # got to context save? */ + BEQ __tx_thread_fiq_no_preempt_restore # Yes, just go back to point of interrupt + + + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup actual current thread pointer + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_fiq_idle_system_restore # Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable # Pickup preempt disable address + LDR r2, [r3] # Pickup actual preempt disable flag + CMP r2, 0 # Is it set? + BNE __tx_thread_fiq_no_preempt_restore # Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr # Pickup address of execute thread ptr + LDR r2, [r3] # Pickup actual execute thread pointer + CMP r0, r2 # Is the same thread highest priority? + BNE __tx_thread_fiq_preempt_restore # No, preemption needs to happen + + +__tx_thread_fiq_no_preempt_restore: + + /* Restore interrupted thread or ISR. */ + + /* Pickup the saved stack pointer. */ + /* tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; */ + + /* Recover the saved context and return to the point of interrupt. */ + + LDMIA sp!, {r0, lr} # Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 # Put SPSR back + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOVS pc, lr # Return to point of interrupt + + /* } + else + { */ +__tx_thread_fiq_preempt_restore: + + LDMIA sp!, {r3, lr} # Recover temporarily saved registers + MOV r1, lr # Save lr (point of interrupt) + MOV r2, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r2 # Enter SVC mode + STR r1, [sp, -4]! # Save point of interrupt + STMDB sp!, {r4-r12, lr} # Save upper half of registers + MOV r4, r3 # Save SPSR in r4 + MOV r2, FIQ_MODE # Build FIQ mode CPSR + MSR CPSR_c, r2 # Re-enter FIQ mode + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOV r5, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r5 # Enter SVC mode + STMDB sp!, {r0-r3} # Save r0-r3 on thread's stack + MOV r3, 1 # Build interrupt stack type + STMDB sp!, {r3, r4} # Save interrupt stack type and SPSR + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup current thread pointer + STR sp, [r0, 8] # Save stack pointer in thread control + /* # block */ + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r4, r0 # Save r0 + MOV r5, r1 # Save r1 + BL _tx_el_thread_preempted # Call thread preempted routine + MOV r0, r4 # Restore r0 + MOV r1, r5 # Restore r1 +#endif + + /* Save the remaining time-slice and disable it. */ + /* if (_tx_timer_time_slice) + { */ + + LDR r3, =_tx_timer_time_slice # Pickup time-slice variable address + LDR r2, [r3] # Pickup time-slice + CMP r2, 0 # Is it active? + BEQ __tx_thread_fiq_dont_save_ts # No, don't save it + + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + STR r2, [r0, 24] # Save thread's time-slice + MOV r2, 0 # Clear value + STR r2, [r3] # Disable global time-slice flag + + /* } */ +__tx_thread_fiq_dont_save_ts: + + + /* Clear the current task pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + MOV r0, 0 # NULL value + STR r0, [r1] # Clear current thread pointer + + /* Return to the scheduler. */ + /* _tx_thread_schedule(); */ + + B _tx_thread_schedule # Return to scheduler + /* } */ + +__tx_thread_fiq_idle_system_restore: + + /* Just return back to the scheduler! */ + + ADD sp, sp, 24 # Recover FIQ stack space + MOV r3, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r3 # Lockout interrupts + B _tx_thread_schedule # Return to scheduler + + .type _tx_thread_fiq_context_restore,$function + .size _tx_thread_fiq_context_restore,.-_tx_thread_fiq_context_restore + +/* } */ + diff --git a/ports/cortex_r4/green/src/tx_thread_fiq_context_save.arm b/ports/cortex_r4/green/src/tx_thread_fiq_context_save.arm new file mode 100644 index 00000000..604c9110 --- /dev/null +++ b/ports/cortex_r4/green/src/tx_thread_fiq_context_save.arm @@ -0,0 +1,197 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_context_save Cortex-R4/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_fiq_context_save(VOID) +{ */ + .globl _tx_thread_fiq_context_save +_tx_thread_fiq_context_save: + + /* Upon entry to this routine, it is assumed that IRQ interrupts are locked + out, we are in IRQ mode, and all registers are intact. */ + + /* Check for a nested interrupt condition. */ + /* if (_tx_thread_system_state++) + { */ + + STMDB sp!, {r0-r3} # Save some working registers + LDR r3, =_tx_thread_system_state # Pickup address of system state var + LDR r2, [r3] # Pickup system state + CMP r2, 0 # Is this the first interrupt? + BEQ __tx_thread_fiq_not_nested_save # Yes, not a nested context save + + /* Nested interrupt condition. */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + + /* Save the rest of the scratch registers on the stack and return to the + calling ISR. */ + + MRS r0, SPSR # Pickup saved SPSR + SUB lr, lr, 4 # Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} # Store other registers + + /* Return to the ISR. */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + B __tx_fiq_processing_return # Continue FIQ processing + +__tx_thread_fiq_not_nested_save: + /* } */ + + /* Otherwise, not nested, check to see if a thread was running. */ + /* else if (_tx_thread_current_ptr) + { */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup current thread pointer + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_fiq_idle_system_save # If so, interrupt occurred in + /* # scheduling loop - nothing needs saving! */ + + /* Save minimal context of interrupted thread. */ + + MRS r2, SPSR # Pickup saved SPSR + SUB lr, lr, 4 # Adjust point of interrupt + STMDB sp!, {r2, lr} # Store other registers, Note that we don't + /* # need to save sl and ip since FIQ has + # copies of these registers. Nested + # interrupt processing does need to save + # these registers. */ + + /* Save the current stack pointer in the thread's control block. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ + + /* Switch to the system stack. */ + /* sp = _tx_thread_system_stack_ptr; */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + B __tx_fiq_processing_return # Continue FIQ processing + + /* } + else + { */ + +__tx_thread_fiq_idle_system_save: + + /* Interrupt occurred in the scheduling loop. */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + /* Not much to do here, save the current SPSR and LR for possible + use in IRQ interrupted in idle system conditions, and return to + FIQ interrupt processing. */ + + MRS r0, SPSR # Pickup saved SPSR + SUB lr, lr, 4 # Adjust point of interrupt + STMDB sp!, {r0, lr} # Store other registers that will get used + /* # or stripped off the stack in context + # restore */ + B __tx_fiq_processing_return # Continue FIQ processing + + .type _tx_thread_fiq_context_save,$function + .size _tx_thread_fiq_context_save,.-_tx_thread_fiq_context_save + + /* } +} */ + diff --git a/ports/cortex_r4/green/src/tx_thread_fiq_nesting_end.arm b/ports/cortex_r4/green/src/tx_thread_fiq_nesting_end.arm new file mode 100644 index 00000000..c833a268 --- /dev/null +++ b/ports/cortex_r4/green/src/tx_thread_fiq_nesting_end.arm @@ -0,0 +1,109 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # Disable IRQ and FIQ interrupts +#else + DISABLE_INTS = 0x80 # Disable IRQ interrupts +#endif + MODE_MASK = 0x1F # Mode mask + FIQ_MODE_BITS = 0x11 # FIQ mode bits + SVC_MODE_BITS = 0x13 # SVC mode value */ + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_nesting_end Cortex-R4/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from FIQ mode after */ +/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +/* processing from system mode back to FIQ mode prior to the ISR */ +/* calling _tx_thread_fiq_context_restore. Note that this function */ +/* assumes the system stack pointer is in the same position after */ +/* nesting start function was called. */ +/* */ +/* This function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.arm). */ +/* */ +/* This function returns with FIQ interrupts disabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_fiq_nesting_end(VOID) +{ */ + .globl _tx_thread_fiq_nesting_end +_tx_thread_fiq_nesting_end: + MOV r3,lr # Save ISR return address + MRS r0, CPSR # Pickup the CPSR + ORR r0, r0, DISABLE_INTS # Build disable interrupt value + MSR CPSR_c, r0 # Disable interrupts + LDR lr, [sp] # Pickup saved lr + ADD sp, sp, 4 # Adjust stack pointer + BIC r0, r0, MODE_MASK # Clear mode bits + ORR r0, r0, FIQ_MODE_BITS # Build IRQ mode CPSR + MSR CPSR_c, r0 # Re-enter IRQ mode + MOV pc, r3 # Return to ISR + + .type _tx_thread_fiq_nesting_end,$function + .size _tx_thread_fiq_nesting_end,.-_tx_thread_fiq_nesting_end +/* } */ + diff --git a/ports/cortex_r4/green/src/tx_thread_fiq_nesting_start.arm b/ports/cortex_r4/green/src/tx_thread_fiq_nesting_start.arm new file mode 100644 index 00000000..e1cc76fd --- /dev/null +++ b/ports/cortex_r4/green/src/tx_thread_fiq_nesting_start.arm @@ -0,0 +1,103 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + + FIQ_DISABLE = 0x40 # FIQ disable bit + MODE_MASK = 0x1F # Mode mask + SYS_MODE_BITS = 0x1F # System mode bits + + + .text + .align 4 + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_nesting_start Cortex-R4/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from FIQ mode after */ +/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +/* processing to the system mode so nested FIQ interrupt processing */ +/* is possible (system mode has its own "lr" register). Note that */ +/* this function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.arm). */ +/* */ +/* This function returns with FIQ interrupts enabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_fiq_nesting_start(VOID) +{ */ + .globl _tx_thread_fiq_nesting_start +_tx_thread_fiq_nesting_start: + MOV r3,lr # Save ISR return address + MRS r0, CPSR # Pickup the CPSR + BIC r0, r0, MODE_MASK # Clear the mode bits + ORR r0, r0, SYS_MODE_BITS # Build system mode CPSR + MSR CPSR_c, r0 # Enter system mode + STR lr, [sp, -4]! # Push the system mode lr on the system mode stack + BIC r0, r0, FIQ_DISABLE # Build enable FIQ CPSR + MSR CPSR_c, r0 # Enter system mode + MOV pc, r3 # Return to ISR + + .type _tx_thread_fiq_nesting_start,$function + .size _tx_thread_fiq_nesting_start,.-_tx_thread_fiq_nesting_start +/* } */ + diff --git a/ports/cortex_r4/green/src/tx_thread_interrupt_control.arm b/ports/cortex_r4/green/src/tx_thread_interrupt_control.arm new file mode 100644 index 00000000..faf3a08e --- /dev/null +++ b/ports/cortex_r4/green/src/tx_thread_interrupt_control.arm @@ -0,0 +1,101 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" */ + + +#ifdef TX_ENABLE_FIQ_SUPPORT + INT_MASK = 0xC0 # Interrupt bit mask +#else + INT_MASK = 0x80 # Interrupt bit mask +#endif + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control Cortex-R4/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_control(UINT new_posture) +{ */ + .globl _tx_thread_interrupt_control +_tx_thread_interrupt_control: + + /* Pickup current interrupt lockout posture. */ + + MRS r3, CPSR # Pickup current CPSR + BIC r1, r3, INT_MASK # Clear interrupt lockout bits + ORR r1, r1, r0 # Or-in new interrupt lockout bits + + /* Apply the new interrupt posture. */ + + MSR CPSR_c, r1 # Setup new CPSR + AND r0, r3, INT_MASK # Return previous interrupt mask + RET # Return to caller + + .type _tx_thread_interrupt_control,$function + .size _tx_thread_interrupt_control,.-_tx_thread_interrupt_control +/* } */ + + + diff --git a/ports/cortex_r4/green/src/tx_thread_interrupt_disable.arm b/ports/cortex_r4/green/src/tx_thread_interrupt_disable.arm new file mode 100644 index 00000000..4993f0b2 --- /dev/null +++ b/ports/cortex_r4/green/src/tx_thread_interrupt_disable.arm @@ -0,0 +1,105 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" */ + + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # IRQ & FIQ interrupts disabled +#else + DISABLE_INTS = 0x80 # IRQ interrupts disabled +#endif + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_disable Cortex-R4/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for disabling interrupts */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_disable(void) +{ */ + .globl _tx_thread_interrupt_disable +_tx_thread_interrupt_disable: + + /* Pickup current interrupt lockout posture. */ + + MRS r0, CPSR # Pickup current CPSR + + /* Mask interrupts. */ + +#ifdef TX_BEFORE_ARMV6 + ORR r1, r0, DISABLE_INTS # Mask interrupts + MSR CPSR_c, r1 # Setup new CPSR +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if # Disable IRQ and FIQ +#else + CPSID i # Disable IRQ +#endif +#endif + + RET # Return previous CPSR value + + .type _tx_thread_interrupt_disable,$function + .size _tx_thread_interrupt_disable,.-_tx_thread_interrupt_disable +/* } */ + diff --git a/ports/cortex_r4/green/src/tx_thread_interrupt_restore.arm b/ports/cortex_r4/green/src/tx_thread_interrupt_restore.arm new file mode 100644 index 00000000..6b09c8bf --- /dev/null +++ b/ports/cortex_r4/green/src/tx_thread_interrupt_restore.arm @@ -0,0 +1,85 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" */ + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_restore Cortex-R4/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for restoring interrupts to the state */ +/* returned by a previous _tx_thread_interrupt_disable call. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_interrupt_restore(UINT new_posture) +{ */ + .globl _tx_thread_interrupt_restore +_tx_thread_interrupt_restore: + + /* Apply the new interrupt posture. */ + + MSR CPSR_c, r0 # Setup new CPSR + RET + + .type _tx_thread_interrupt_restore,$function + .size _tx_thread_interrupt_restore,.-_tx_thread_interrupt_restore +/* } */ + diff --git a/ports/cortex_r4/green/src/tx_thread_irq_nesting_end.arm b/ports/cortex_r4/green/src/tx_thread_irq_nesting_end.arm new file mode 100644 index 00000000..7681137b --- /dev/null +++ b/ports/cortex_r4/green/src/tx_thread_irq_nesting_end.arm @@ -0,0 +1,109 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # Disable IRQ and FIQ interrupts +#else + DISABLE_INTS = 0x80 # Disable IRQ interrupts +#endif + MODE_MASK = 0x1F # Mode mask + IRQ_MODE_BITS = 0x12 # IRQ mode bits + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_irq_nesting_end Cortex-R4/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from IRQ mode after */ +/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +/* processing from system mode back to IRQ mode prior to the ISR */ +/* calling _tx_thread_context_restore. Note that this function */ +/* assumes the system stack pointer is in the same position after */ +/* nesting start function was called. */ +/* */ +/* This function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.arm). */ +/* */ +/* This function returns with IRQ interrupts disabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_irq_nesting_end(VOID) +{ */ + .globl _tx_thread_irq_nesting_end +_tx_thread_irq_nesting_end: + MOV r3,lr # Save ISR return address + MRS r0, CPSR # Pickup the CPSR + ORR r0, r0, DISABLE_INTS # Build disable interrupt value + MSR CPSR_c, r0 # Disable interrupts + LDR lr, [sp] # Pickup saved lr + ADD sp, sp, 4 # Adjust stack pointer + BIC r0, r0, MODE_MASK # Clear mode bits + ORR r0, r0, IRQ_MODE_BITS # Build IRQ mode CPSR + MSR CPSR_c, r0 # Re-enter IRQ mode + MOV pc, r3 # Return to ISR + + .type _tx_thread_irq_nesting_end,$function + .size _tx_thread_irq_nesting_end,.-_tx_thread_irq_nesting_end + +/* } */ + diff --git a/ports/cortex_r4/green/src/tx_thread_irq_nesting_start.arm b/ports/cortex_r4/green/src/tx_thread_irq_nesting_start.arm new file mode 100644 index 00000000..1d52eab0 --- /dev/null +++ b/ports/cortex_r4/green/src/tx_thread_irq_nesting_start.arm @@ -0,0 +1,102 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + + IRQ_DISABLE = 0x80 # IRQ disable bit + MODE_MASK = 0x1F # Mode mask + SYS_MODE_BITS = 0x1F # System mode bits + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_irq_nesting_start Cortex-R4/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from IRQ mode after */ +/* _tx_thread_context_save has been called and switches the IRQ */ +/* processing to the system mode so nested IRQ interrupt processing */ +/* is possible (system mode has its own "lr" register). Note that */ +/* this function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.arm). */ +/* */ +/* This function returns with IRQ interrupts enabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_irq_nesting_start(VOID) +{ */ + .globl _tx_thread_irq_nesting_start +_tx_thread_irq_nesting_start: + MOV r3,lr # Save ISR return address + MRS r0, CPSR # Pickup the CPSR + BIC r0, r0, MODE_MASK # Clear the mode bits + ORR r0, r0, SYS_MODE_BITS # Build system mode CPSR + MSR CPSR_c, r0 # Enter system mode + STR lr, [sp, -4]! # Push the system mode lr on the system mode stack + BIC r0, r0, IRQ_DISABLE # Build enable IRQ CPSR + MSR CPSR_c, r0 # Enter system mode + MOV pc, r3 # Return to ISR + + .type _tx_thread_irq_nesting_start,$function + .size _tx_thread_irq_nesting_start,.-_tx_thread_irq_nesting_start +/* } */ + diff --git a/ports/cortex_r4/green/src/tx_thread_schedule.arm b/ports/cortex_r4/green/src/tx_thread_schedule.arm new file mode 100644 index 00000000..1fd4cf50 --- /dev/null +++ b/ports/cortex_r4/green/src/tx_thread_schedule.arm @@ -0,0 +1,181 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + ENABLE_INTS = 0xC0 # IRQ & FIQ Interrupts enabled mask +#else + ENABLE_INTS = 0x80 # IRQ Interrupts enabled mask +#endif + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule Cortex-R4/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* _tx_thread_context_restore Restore thread's context */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_schedule(VOID) +{ */ + .globl _tx_thread_schedule +_tx_thread_schedule: + + /* Enable interrupts. */ + +#ifdef TX_BEFORE_ARMV6 + MRS r2, CPSR # Pickup CPSR + BIC r0, r2, ENABLE_INTS # Clear the disable bit(s) + MSR CPSR_c, r0 # Enable interrupts +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSIE if # Enable IRQ and FIQ interrupts +#else + CPSIE i # Enable IRQ interrupts +#endif +#endif + + /* Wait for a thread to execute. */ + /* do + { */ + LDR r1, =_tx_thread_execute_ptr # Address of thread execute ptr + +__tx_thread_schedule_loop: + + LDR r0, [r1] # Pickup next thread to execute + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_schedule_loop # If so, keep looking for a thread + + /* } + while(_tx_thread_execute_ptr == TX_NULL); */ + + /* Yes! We have a thread to execute. Lockout interrupts and + transfer control to it. */ + +#ifdef TX_BEFORE_ARMV6 + MSR CPSR_c, r2 # Disable interrupts +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if # Disable IRQ and FIQ interrupts +#else + CPSID i # Disable IRQ interrupts +#endif +#endif + + /* Setup the current thread pointer. */ + /* _tx_thread_current_ptr = _tx_thread_execute_ptr; */ + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV v1, r0 # Save temp register in non-volatile register + BL _tx_el_thread_running # Call event logging routine + MOV r0, v1 # Restore temp register +#endif + + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread + STR r0, [r1] # Setup current thread pointer + + /* Increment the run count for this thread. */ + /* _tx_thread_current_ptr -> tx_thread_run_count++; */ + + LDR r2, [r0, 4] # Pickup run counter + LDR r3, [r0, 24] # Pickup time-slice for this thread + ADD r2, r2, 1 # Increment thread run-counter + STR r2, [r0, 4] # Store the new run counter + + /* Setup time-slice, if present. */ + /* _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; */ + + LDR r2, =_tx_timer_time_slice # Pickup address of time slice + /* # variable */ + LDR sp, [r0, 8] # Switch stack pointers + STR r3, [r2] # Setup time-slice + + /* Switch to the thread's stack. */ + /* sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread entry function to indicate the thread is executing. */ + + BL _tx_execution_thread_enter # Call the thread execution enter function +#endif + + /* Determine if an interrupt frame or a synchronous task suspension frame + is present. */ + + LDMIA sp!, {r0, r1} # Pickup the stack type and saved CPSR + MSR SPSR_cxsf, r1 # Setup SPSR for return + CMP r0, 0 # Check for synchronous context switch + LDMNEIA sp!, {r0-r12, lr, pc}^ # If non-zero, return to point of interrupt + /* # in the thread */ + LDMIA sp!, {v1-r11, lr} # Otherwise, return to thread synchronously + MSR CPSR_cxsf,r1 # Recover CPSR (r1 is still valid) + RET # Return to caller (Thumb safe) + + .type _tx_thread_schedule,$function + .size _tx_thread_schedule,.-_tx_thread_schedule +/* } */ + diff --git a/ports/cortex_r4/green/src/tx_thread_stack_build.arm b/ports/cortex_r4/green/src/tx_thread_stack_build.arm new file mode 100644 index 00000000..d6e9ce66 --- /dev/null +++ b/ports/cortex_r4/green/src/tx_thread_stack_build.arm @@ -0,0 +1,161 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" */ + + SVC_MODE = 0x13 # SVC mode +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSR_MASK = 0xDF # Mask initial CPSR, IRQ & FIQ ints enabled +#else + CPSR_MASK = 0x9F # Mask initial CPSR, IRQ ints enabled +#endif + + THUMB_BIT = 0x20 # Thumb-bit + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build Cortex-R4/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +{ */ + .globl _tx_thread_stack_build +_tx_thread_stack_build: + + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-R4 should look like the following after it is built: + + Stack Top: 1 Interrupt stack frame type + CPSR Initial value for CPSR + r0 (a1) Initial value for r0 + r1 (a2) Initial value for r1 + r2 (a3) Initial value for r2 + r3 (a4) Initial value for r3 + r4 (v1) Initial value for r4 + r5 (v2) Initial value for r5 + r6 (v3) Initial value for r6 + r7 (v4) Initial value for r7 + r8 (v5) Initial value for r8 + r9 (sb) Initial value for r9 + r10 (sl) Initial value for r10 + r11 (fp) Initial value for r11 + r12 (ip) Initial value for r12 + lr Initial value for lr + pc Initial value for pc + 0 For stack backtracing + + Stack Bottom: (higher memory address) */ + + LDR r2, [r0, 16] # Pickup end of stack area + BIC r2, r2, 7 # Ensure 8-byte alignment + SUB r2, r2, 76 # Allocate space for the stack frame + + /* Actually build the stack frame. */ + + MOV r3, 1 # Build interrupt stack type + STR r3, [r2] # Store stack type + MOV r3, 0 # Build initial register value + STR r3, [r2, 8] # Store initial r0 + STR r3, [r2, 12] # Store initial r1 + STR r3, [r2, 16] # Store initial r2 + STR r3, [r2, 20] # Store initial r3 + STR r3, [r2, 24] # Store initial r4 + STR r3, [r2, 28] # Store initial r5 + STR r3, [r2, 32] # Store initial r6 + STR r3, [r2, 36] # Store initial r7 + STR r3, [r2, 40] # Store initial r8 + STR r3, [r2, 44] # Store initial r9 + LDR r3, [r0, 12] # Pickup stack starting address + STR r3, [r2, 48] # Store initial r10 + MOV r3, 0 # Build initial register value + STR r3, [r2, 52] # Store initial r11 + STR r3, [r2, 56] # Store initial r12 + STR r3, [r2, 60] # Store initial lr + STR r1, [r2, 64] # Store initial pc + STR r3, [r2, 68] # 0 for back-trace + + MRS r3, CPSR # Pickup CPSR + BIC r3, r3, CPSR_MASK # Mask mode bits of CPSR + ORR r3, r3, SVC_MODE # Build CPSR, SVC mode, interrupts enabled + BIC r3, r3, #THUMB_BIT # Clear Thumb-bit by default + AND r1, r1, #1 # Determine if the entry function is in Thumb mode + CMP r1, 1 # Is the Thumb-bit set? + ORREQ r3, r3, #THUMB_BIT # Yes, set the Thumb-bit + STR r3, [r2, 4] # Store initial CPSR + + /* Setup stack pointer. */ + /* thread_ptr -> tx_thread_stack_ptr = r2; */ + + STR r2, [r0, 8] # Save stack pointer in thread's + /* # control block */ + RET # Return to caller + + .type _tx_thread_stack_build,$function + .size _tx_thread_stack_build,.-_tx_thread_stack_build +/* } */ + diff --git a/ports/cortex_r4/green/src/tx_thread_system_return.arm b/ports/cortex_r4/green/src/tx_thread_system_return.arm new file mode 100644 index 00000000..93c34aac --- /dev/null +++ b/ports/cortex_r4/green/src/tx_thread_system_return.arm @@ -0,0 +1,149 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # IRQ & FIQ interrupts disabled +#else + DISABLE_INTS = 0x80 # IRQ interrupts disabled +#endif + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return Cortex-R4/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the ThreadX system. Only a */ +/* minimal context is saved since the compiler assumes temp registers */ +/* are going to get slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_system_return(VOID) +{ */ + .globl _tx_thread_system_return +_tx_thread_system_return: + + /* Save minimal context on the stack. */ + + MOV r0, 0 # Build a solicited stack type + MRS r1, CPSR # Pickup the CPSR + STMDB sp!, {r0-r1, r4-r11, lr} # Save minimal context + + /* Lockout interrupts. */ + +#ifdef TX_BEFORE_ARMV6 + ORR r2, r1, DISABLE_INTS # Build disable interrupt CPSR + MSR CPSR_c, r2 # Disable interrupts +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if # Disable IRQ and FIQ interrupts +#else + CPSID i # Disable IRQ interrutps +#endif +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread exit function to indicate the thread is no longer executing. */ + + BL _tx_execution_thread_exit # Call the thread exit function +#endif + + LDR r3, =_tx_thread_current_ptr # Pickup address of current ptr + LDR r0, [r3] # Pickup current thread pointer + LDR r2, =_tx_timer_time_slice # Pickup address of time slice + LDR r1, [r2] # Pickup current time slice + + /* Save current stack and switch to system stack. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; + sp = _tx_thread_system_stack_ptr; */ + + STR sp, [r0, 8] # Save thread stack pointer + + /* Determine if the time-slice is active. */ + /* if (_tx_timer_time_slice) + { */ + + MOV r4, 0 # Build clear value + CMP r1, 0 # Is a time-slice active? + BEQ __tx_thread_dont_save_ts # No, don't save the time-slice + + /* Save time-slice for the thread and clear the current time-slice. */ + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + STR r4, [r2, 0] # Clear time-slice + STR r1, [r0, 24] # Save current time-slice + + /* } */ +__tx_thread_dont_save_ts: + + /* Clear the current thread pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + STR r4, [r3] # Clear current thread pointer + B _tx_thread_schedule # Jump to scheduler! + + .type _tx_thread_system_return,$function + .size _tx_thread_system_return,.-_tx_thread_system_return +/* } */ + diff --git a/ports/cortex_r4/green/src/tx_thread_vectored_context_save.arm b/ports/cortex_r4/green/src/tx_thread_vectored_context_save.arm new file mode 100644 index 00000000..a41cff9f --- /dev/null +++ b/ports/cortex_r4/green/src/tx_thread_vectored_context_save.arm @@ -0,0 +1,196 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # IRQ & FIQ interrupts disabled +#else + DISABLE_INTS = 0x80 # IRQ interrupts disabled +#endif + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_vectored_context_save Cortex-R4/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_vectored_context_save(VOID) +{ */ + .globl _tx_thread_vectored_context_save +_tx_thread_vectored_context_save: + + /* Upon entry to this routine, it is assumed that IRQ interrupts are locked + out, we are in IRQ mode, the minimal context is already saved, and the + lr register contains the return ISR address. */ + + /* Check for a nested interrupt condition. */ + /* if (_tx_thread_system_state++) + { */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#ifdef TX_BEFORE_ARMV6 + MRS r0, CPSR # Pickup the CPSR + ORR r0, r0, DISABLE_INTS # Build disable interrupt CPSR + MSR CPSR_c, r0 # Disable interrupts +#else + CPSID if # Disable IRQ and FIQ interrupts +#endif +#endif + LDR r3, =_tx_thread_system_state # Pickup address of system state var + LDR r2, [r3] # Pickup system state + CMP r2, 0 # Is this the first interrupt? + BEQ __tx_thread_not_nested_save # Yes, not a nested context save + + /* Nested interrupt condition. */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + + /* Note: Minimal context of interrupted thread is already saved. */ + + /* Return to the ISR. */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + MOV pc, lr # Return to caller + +__tx_thread_not_nested_save: + /* } */ + + /* Otherwise, not nested, check to see if a thread was running. */ + /* else if (_tx_thread_current_ptr) + { */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup current thread pointer + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_idle_system_save # If so, interrupt occurred in + /* # scheduling loop - nothing needs saving! */ + + /* Note: Minimal context of interrupted thread is already saved. */ + + /* Save the current stack pointer in the thread's control block. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ + + /* Switch to the system stack. */ + /* sp = _tx_thread_system_stack_ptr; */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + MOV pc, lr # Return to caller + + /* } + else + { */ + +__tx_thread_idle_system_save: + + /* Interrupt occurred in the scheduling loop. */ + + /* Not much to do here, just adjust the stack pointer, and return to IRQ + processing. */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + ADD sp, sp, 32 # Recover saved registers + MOV pc, lr # Return to caller + + .type _tx_thread_vectored_context_save,$function + .size _tx_thread_vectored_context_save,.-_tx_thread_vectored_context_save + + /* } +} */ + diff --git a/ports/cortex_r4/green/src/tx_timer_interrupt.arm b/ports/cortex_r4/green/src/tx_timer_interrupt.arm new file mode 100644 index 00000000..36ce56a3 --- /dev/null +++ b/ports/cortex_r4/green/src/tx_timer_interrupt.arm @@ -0,0 +1,241 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_timer.h" + #include "tx_thread.h" */ + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt Cortex-R4/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Process timer expiration */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_timer_interrupt(VOID) +{ */ + .globl _tx_timer_interrupt +_tx_timer_interrupt: + + /* Upon entry to this routine, it is assumed that context save has already + been called, and therefore the compiler scratch registers are available + for use. */ + + /* Increment the system clock. */ + /* _tx_timer_system_clock++; */ + + LDR r1, =_tx_timer_system_clock # Pickup address of system clock + LDR r0, [r1] # Pickup system clock + ADD r0, r0, 1 # Increment system clock + STR r0, [r1] # Store new system clock + + /* Test for time-slice expiration. */ + /* if (_tx_timer_time_slice) + { */ + + LDR r3, =_tx_timer_time_slice # Pickup address of time-slice + LDR r2, [r3] # Pickup time-slice + CMP r2, 0 # Is it non-active? + BEQ __tx_timer_no_time_slice # Yes, skip time-slice processing + + /* Decrement the time_slice. */ + /* _tx_timer_time_slice--; */ + + SUB r2, r2, 1 # Decrement the time-slice + STR r2, [r3] # Store new time-slice value + + /* Check for expiration. */ + /* if (__tx_timer_time_slice == 0) */ + + CMP r2, 0 # Has it expired? + BNE __tx_timer_no_time_slice # No, skip expiration processing + + /* Set the time-slice expired flag. */ + /* _tx_timer_expired_time_slice = TX_TRUE; */ + + LDR r3,=_tx_timer_expired_time_slice # Pickup address of expired flag + MOV r0, 1 # Build expired value + STR r0, [r3] # Set time-slice expiration flag + + /* } */ + +__tx_timer_no_time_slice: + + /* Test for timer expiration. */ + /* if (*_tx_timer_current_ptr) + { */ + + LDR r1, =_tx_timer_current_ptr # Pickup current timer pointer addr + LDR r0, [r1] # Pickup current timer + LDR r2, [r0] # Pickup timer list entry + CMP r2, 0 # Is there anything in the list? + BEQ __tx_timer_no_timer # No, just increment the timer + + /* Set expiration flag. */ + /* _tx_timer_expired = TX_TRUE; */ + + LDR r3, =_tx_timer_expired # Pickup expiration flag address + MOV r2, 1 # Build expired value + STR r2, [r3] # Set expired flag + B __tx_timer_done # Finished timer processing + + /* } + else + { */ +__tx_timer_no_timer: + + /* No timer expired, increment the timer pointer. */ + /* _tx_timer_current_ptr++; */ + + ADD r0, r0, 4 # Move to next timer + + /* Check for wrap-around. */ + /* if (_tx_timer_current_ptr == _tx_timer_list_end) */ + + LDR r3, =_tx_timer_list_end # Pickup addr of timer list end + LDR r2, [r3] # Pickup list end + CMP r0, r2 # Are we at list end? + BNE __tx_timer_skip_wrap # No, skip wrap-around logic + + /* Wrap to beginning of list. */ + /* _tx_timer_current_ptr = _tx_timer_list_start; */ + + LDR r3, =_tx_timer_list_start # Pickup addr of timer list start + LDR r0, [r3] # Set current pointer to list start + +__tx_timer_skip_wrap: + + STR r0, [r1] # Store new current timer pointer + /* } */ + +__tx_timer_done: + + + /* See if anything has expired. */ + /* if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) + { */ + + LDR r3, =_tx_timer_expired_time_slice # Pickup addr of expired flag + LDR r2, [r3] # Pickup time-slice expired flag + CMP r2, 0 # Did a time-slice expire? + BNE __tx_something_expired # If non-zero, time-slice expired + LDR r1, =_tx_timer_expired # Pickup addr of other expired flag + LDR r0, [r1] # Pickup timer expired flag + CMP r0, 0 # Did a timer expire? + BEQ __tx_timer_nothing_expired # No, nothing expired + +__tx_something_expired: + + + STMDB sp!, {r0, lr} # Save the lr register on the stack + /* # and save r0 just to keep 8-byte alignment */ + + /* Did a timer expire? */ + /* if (_tx_timer_expired) + { */ + + LDR r1, =_tx_timer_expired # Pickup addr of expired flag + LDR r0, [r1] # Pickup timer expired flag + CMP r0, 0 # Check for timer expiration + BEQ __tx_timer_dont_activate # If not set, skip timer activation + + /* Process the timer expiration. */ + /* _tx_timer_expiration_process(); */ + BL _tx_timer_expiration_process # Call the timer expiration handling routine + + /* } */ +__tx_timer_dont_activate: + + /* Did time slice expire? */ + /* if (_tx_timer_expired_time_slice) + { */ + + LDR r3, =_tx_timer_expired_time_slice # Pickup addr of time-slice expired + LDR r2, [r3] # Pickup the actual flag + CMP r2, 0 # See if the flag is set + BEQ __tx_timer_not_ts_expiration # No, skip time-slice processing + + /* Time slice interrupted thread. */ + /* _tx_thread_time_slice(); */ + + BL _tx_thread_time_slice # Call time-slice processing + + /* } */ +__tx_timer_not_ts_expiration: + + + LDMIA sp!, {r0, lr} # Recover lr register (r0 is just there for + /* # the 8-byte stack alignment */ + + /* } */ + +__tx_timer_nothing_expired: + + RET # Return to caller + + .type _tx_timer_interrupt,$function + .size _tx_timer_interrupt,.-_tx_timer_interrupt +/* } */ + diff --git a/ports/cortex_r4/iar/example_build/tx_initialize_low_level.s b/ports/cortex_r4/iar/example_build/tx_initialize_low_level.s index a05d79d1..b2fea266 100644 --- a/ports/cortex_r4/iar/example_build/tx_initialize_low_level.s +++ b/ports/cortex_r4/iar/example_build/tx_initialize_low_level.s @@ -71,7 +71,7 @@ __tx_free_memory_start ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level Cortex-R4/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -104,7 +104,7 @@ __tx_free_memory_start ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_r4/iar/inc/tx_port.h b/ports/cortex_r4/iar/inc/tx_port.h index 362edaf5..701b0308 100644 --- a/ports/cortex_r4/iar/inc/tx_port.h +++ b/ports/cortex_r4/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-R4/IAR */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -364,7 +364,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/IAR Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/IAR Version 6.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_r4/iar/readme_threadx.txt b/ports/cortex_r4/iar/readme_threadx.txt index dbf6f32b..32832714 100644 --- a/ports/cortex_r4/iar/readme_threadx.txt +++ b/ports/cortex_r4/iar/readme_threadx.txt @@ -416,7 +416,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX version 6.0.1 for Cortex-R4 using IAR's ARM tools. +09-30-2020 Initial ThreadX version 6.1 for Cortex-R4 using IAR's ARM tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_r4/iar/src/tx_thread_context_restore.s b/ports/cortex_r4/iar/src/tx_thread_context_restore.s index eb9c7446..f5dfdbfc 100644 --- a/ports/cortex_r4/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_r4/iar/src/tx_thread_context_restore.s @@ -53,7 +53,7 @@ THUMB_MASK DEFINE 0x20 ; Thumb bit mask ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore Cortex-R4/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -85,7 +85,7 @@ THUMB_MASK DEFINE 0x20 ; Thumb bit mask ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_r4/iar/src/tx_thread_context_save.s b/ports/cortex_r4/iar/src/tx_thread_context_save.s index 9c28acb1..2e4b38de 100644 --- a/ports/cortex_r4/iar/src/tx_thread_context_save.s +++ b/ports/cortex_r4/iar/src/tx_thread_context_save.s @@ -42,7 +42,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save Cortex-R4/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -73,7 +73,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_r4/iar/src/tx_thread_interrupt_control.s b/ports/cortex_r4/iar/src/tx_thread_interrupt_control.s index 934de0dd..24a8f2a2 100644 --- a/ports/cortex_r4/iar/src/tx_thread_interrupt_control.s +++ b/ports/cortex_r4/iar/src/tx_thread_interrupt_control.s @@ -38,7 +38,7 @@ INT_MASK DEFINE 0x80 ; Interrupt bit mask ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control Cortex-R4/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -68,7 +68,7 @@ INT_MASK DEFINE 0x80 ; Interrupt bit mask ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_r4/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_r4/iar/src/tx_thread_interrupt_disable.s index 64c26b4b..d6b8ab47 100644 --- a/ports/cortex_r4/iar/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_r4/iar/src/tx_thread_interrupt_disable.s @@ -38,7 +38,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_disable Cortex-R4/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -67,7 +67,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports/cortex_r4/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_r4/iar/src/tx_thread_interrupt_restore.s index f128b115..a8676e48 100644 --- a/ports/cortex_r4/iar/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_r4/iar/src/tx_thread_interrupt_restore.s @@ -34,7 +34,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-R4/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -64,7 +64,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;void _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_r4/iar/src/tx_thread_irq_nesting_end.s b/ports/cortex_r4/iar/src/tx_thread_irq_nesting_end.s index 04bc7792..7318d90c 100644 --- a/ports/cortex_r4/iar/src/tx_thread_irq_nesting_end.s +++ b/ports/cortex_r4/iar/src/tx_thread_irq_nesting_end.s @@ -39,7 +39,7 @@ IRQ_MODE DEFINE 0x12 ; IRQ mode ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_irq_nesting_end Cortex-R4/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -78,7 +78,7 @@ IRQ_MODE DEFINE 0x12 ; IRQ mode ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports/cortex_r4/iar/src/tx_thread_irq_nesting_start.s b/ports/cortex_r4/iar/src/tx_thread_irq_nesting_start.s index 21dc597b..741e729d 100644 --- a/ports/cortex_r4/iar/src/tx_thread_irq_nesting_start.s +++ b/ports/cortex_r4/iar/src/tx_thread_irq_nesting_start.s @@ -39,7 +39,7 @@ SYS_MODE DEFINE 0x1F ; System mode ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_irq_nesting_start Cortex-R4/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -75,7 +75,7 @@ SYS_MODE DEFINE 0x1F ; System mode ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_r4/iar/src/tx_thread_schedule.s b/ports/cortex_r4/iar/src/tx_thread_schedule.s index 58092c84..119fab27 100644 --- a/ports/cortex_r4/iar/src/tx_thread_schedule.s +++ b/ports/cortex_r4/iar/src/tx_thread_schedule.s @@ -43,7 +43,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-R4/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -76,7 +76,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_r4/iar/src/tx_thread_stack_build.s b/ports/cortex_r4/iar/src/tx_thread_stack_build.s index 253006fc..52bf37f7 100644 --- a/ports/cortex_r4/iar/src/tx_thread_stack_build.s +++ b/ports/cortex_r4/iar/src/tx_thread_stack_build.s @@ -39,7 +39,7 @@ CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints en ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build Cortex-R4/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints en ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_r4/iar/src/tx_thread_system_return.s b/ports/cortex_r4/iar/src/tx_thread_system_return.s index c0014a8b..8c8fc7e7 100644 --- a/ports/cortex_r4/iar/src/tx_thread_system_return.s +++ b/ports/cortex_r4/iar/src/tx_thread_system_return.s @@ -43,7 +43,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return Cortex-R4/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -75,7 +75,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_r4/iar/src/tx_thread_vectored_context_save.s b/ports/cortex_r4/iar/src/tx_thread_vectored_context_save.s index 07b5cc5f..6c920825 100644 --- a/ports/cortex_r4/iar/src/tx_thread_vectored_context_save.s +++ b/ports/cortex_r4/iar/src/tx_thread_vectored_context_save.s @@ -41,7 +41,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_vectored_context_save Cortex-R4/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) diff --git a/ports/cortex_r4/iar/src/tx_timer_interrupt.s b/ports/cortex_r4/iar/src/tx_timer_interrupt.s index 420e42ad..6a7b88fd 100644 --- a/ports/cortex_r4/iar/src/tx_timer_interrupt.s +++ b/ports/cortex_r4/iar/src/tx_timer_interrupt.s @@ -49,7 +49,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt Cortex-R4/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -83,7 +83,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_r5/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_r5/ac5/example_build/tx_initialize_low_level.s index b4cbb423..19cc38fa 100644 --- a/ports/cortex_r5/ac5/example_build/tx_initialize_low_level.s +++ b/ports/cortex_r5/ac5/example_build/tx_initialize_low_level.s @@ -96,7 +96,7 @@ __vectors ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level Cortex-R5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -129,7 +129,7 @@ __vectors ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_r5/ac5/inc/tx_port.h b/ports/cortex_r5/ac5/inc/tx_port.h index 459a9a94..a6cf6036 100644 --- a/ports/cortex_r5/ac5/inc/tx_port.h +++ b/ports/cortex_r5/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-R5/AC5 */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -317,7 +317,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R5/AC5 Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R5/AC5 Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r5/ac5/readme_threadx.txt b/ports/cortex_r5/ac5/readme_threadx.txt index bc4d497d..d6b8b6d7 100644 --- a/ports/cortex_r5/ac5/readme_threadx.txt +++ b/ports/cortex_r5/ac5/readme_threadx.txt @@ -519,7 +519,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-R5 using AC5 tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-R5 using AC5 tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_r5/ac5/src/tx_thread_context_restore.s b/ports/cortex_r5/ac5/src/tx_thread_context_restore.s index 1a1e3c0c..d4114be6 100644 --- a/ports/cortex_r5/ac5/src/tx_thread_context_restore.s +++ b/ports/cortex_r5/ac5/src/tx_thread_context_restore.s @@ -60,7 +60,7 @@ SVC_MODE EQU 0x93 ; SVC mode ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore Cortex-R5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -92,7 +92,7 @@ SVC_MODE EQU 0x93 ; SVC mode ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_r5/ac5/src/tx_thread_context_save.s b/ports/cortex_r5/ac5/src/tx_thread_context_save.s index d7d5d406..fe660b48 100644 --- a/ports/cortex_r5/ac5/src/tx_thread_context_save.s +++ b/ports/cortex_r5/ac5/src/tx_thread_context_save.s @@ -45,7 +45,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save Cortex-R5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -76,7 +76,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_r5/ac5/src/tx_thread_fiq_context_restore.s b/ports/cortex_r5/ac5/src/tx_thread_fiq_context_restore.s index c80122bb..e5e9b8d7 100644 --- a/ports/cortex_r5/ac5/src/tx_thread_fiq_context_restore.s +++ b/ports/cortex_r5/ac5/src/tx_thread_fiq_context_restore.s @@ -56,7 +56,7 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_context_restore Cortex-R5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -88,7 +88,7 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_context_restore(VOID) diff --git a/ports/cortex_r5/ac5/src/tx_thread_fiq_context_save.s b/ports/cortex_r5/ac5/src/tx_thread_fiq_context_save.s index d3fceec4..1507773b 100644 --- a/ports/cortex_r5/ac5/src/tx_thread_fiq_context_save.s +++ b/ports/cortex_r5/ac5/src/tx_thread_fiq_context_save.s @@ -45,7 +45,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_context_save Cortex-R5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -76,7 +76,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ; VOID _tx_thread_fiq_context_save(VOID) diff --git a/ports/cortex_r5/ac5/src/tx_thread_fiq_nesting_end.s b/ports/cortex_r5/ac5/src/tx_thread_fiq_nesting_end.s index 0bfad1ba..4c9fd73b 100644 --- a/ports/cortex_r5/ac5/src/tx_thread_fiq_nesting_end.s +++ b/ports/cortex_r5/ac5/src/tx_thread_fiq_nesting_end.s @@ -45,7 +45,7 @@ FIQ_MODE_BITS EQU 0x11 ; FIQ mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_nesting_end Cortex-R5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -84,7 +84,7 @@ FIQ_MODE_BITS EQU 0x11 ; FIQ mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_end(VOID) diff --git a/ports/cortex_r5/ac5/src/tx_thread_fiq_nesting_start.s b/ports/cortex_r5/ac5/src/tx_thread_fiq_nesting_start.s index fc9c725e..8e734d18 100644 --- a/ports/cortex_r5/ac5/src/tx_thread_fiq_nesting_start.s +++ b/ports/cortex_r5/ac5/src/tx_thread_fiq_nesting_start.s @@ -41,7 +41,7 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_fiq_nesting_start Cortex-R5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/cortex_r5/ac5/src/tx_thread_interrupt_control.s b/ports/cortex_r5/ac5/src/tx_thread_interrupt_control.s index 856eae8d..ebde36c1 100644 --- a/ports/cortex_r5/ac5/src/tx_thread_interrupt_control.s +++ b/ports/cortex_r5/ac5/src/tx_thread_interrupt_control.s @@ -42,7 +42,7 @@ INT_MASK EQU 0x80 ; Interrupt bit mask ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control Cortex-R5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ INT_MASK EQU 0x80 ; Interrupt bit mask ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_r5/ac5/src/tx_thread_interrupt_disable.s b/ports/cortex_r5/ac5/src/tx_thread_interrupt_disable.s index f558daa3..27339584 100644 --- a/ports/cortex_r5/ac5/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_r5/ac5/src/tx_thread_interrupt_disable.s @@ -35,7 +35,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_disable Cortex-R5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -64,7 +64,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(void) diff --git a/ports/cortex_r5/ac5/src/tx_thread_interrupt_restore.s b/ports/cortex_r5/ac5/src/tx_thread_interrupt_restore.s index e0b1e8ef..b3b697a5 100644 --- a/ports/cortex_r5/ac5/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_r5/ac5/src/tx_thread_interrupt_restore.s @@ -35,7 +35,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-R5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -65,7 +65,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_r5/ac5/src/tx_thread_irq_nesting_end.s b/ports/cortex_r5/ac5/src/tx_thread_irq_nesting_end.s index 67a6526d..b534330b 100644 --- a/ports/cortex_r5/ac5/src/tx_thread_irq_nesting_end.s +++ b/ports/cortex_r5/ac5/src/tx_thread_irq_nesting_end.s @@ -45,7 +45,7 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_irq_nesting_end Cortex-R5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -84,7 +84,7 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports/cortex_r5/ac5/src/tx_thread_irq_nesting_start.s b/ports/cortex_r5/ac5/src/tx_thread_irq_nesting_start.s index 9096f016..0232cb71 100644 --- a/ports/cortex_r5/ac5/src/tx_thread_irq_nesting_start.s +++ b/ports/cortex_r5/ac5/src/tx_thread_irq_nesting_start.s @@ -41,7 +41,7 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_irq_nesting_start Cortex-R5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_r5/ac5/src/tx_thread_schedule.s b/ports/cortex_r5/ac5/src/tx_thread_schedule.s index f4857766..49116702 100644 --- a/ports/cortex_r5/ac5/src/tx_thread_schedule.s +++ b/ports/cortex_r5/ac5/src/tx_thread_schedule.s @@ -46,7 +46,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-R5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -79,7 +79,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_r5/ac5/src/tx_thread_stack_build.s b/ports/cortex_r5/ac5/src/tx_thread_stack_build.s index 26281be6..8174d9b4 100644 --- a/ports/cortex_r5/ac5/src/tx_thread_stack_build.s +++ b/ports/cortex_r5/ac5/src/tx_thread_stack_build.s @@ -47,7 +47,7 @@ THUMB_BIT EQU 0x20 ; Thumb-bit ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build Cortex-R5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -79,7 +79,7 @@ THUMB_BIT EQU 0x20 ; Thumb-bit ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_r5/ac5/src/tx_thread_system_return.s b/ports/cortex_r5/ac5/src/tx_thread_system_return.s index 5ecd61fd..aa53ad31 100644 --- a/ports/cortex_r5/ac5/src/tx_thread_system_return.s +++ b/ports/cortex_r5/ac5/src/tx_thread_system_return.s @@ -45,7 +45,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return Cortex-R5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_r5/ac5/src/tx_thread_vectored_context_save.s b/ports/cortex_r5/ac5/src/tx_thread_vectored_context_save.s index 77015e9a..bb0d9a45 100644 --- a/ports/cortex_r5/ac5/src/tx_thread_vectored_context_save.s +++ b/ports/cortex_r5/ac5/src/tx_thread_vectored_context_save.s @@ -44,7 +44,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_vectored_context_save Cortex-R5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -75,7 +75,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) diff --git a/ports/cortex_r5/ac5/src/tx_timer_interrupt.s b/ports/cortex_r5/ac5/src/tx_timer_interrupt.s index d498e16f..2025e082 100644 --- a/ports/cortex_r5/ac5/src/tx_timer_interrupt.s +++ b/ports/cortex_r5/ac5/src/tx_timer_interrupt.s @@ -50,7 +50,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt Cortex-R5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -84,7 +84,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_r5/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_r5/ac6/example_build/sample_threadx/tx_initialize_low_level.S index e744c843..7b0cdc5f 100644 --- a/ports/cortex_r5/ac6/example_build/sample_threadx/tx_initialize_low_level.S +++ b/ports/cortex_r5/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -75,7 +75,7 @@ $_tx_initialize_low_level: @/* FUNCTION RELEASE */ @/* */ @/* _tx_initialize_low_level Cortex-R5/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -108,7 +108,7 @@ $_tx_initialize_low_level: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_r5/ac6/inc/tx_port.h b/ports/cortex_r5/ac6/inc/tx_port.h index dc2eee31..e27c542d 100644 --- a/ports/cortex_r5/ac6/inc/tx_port.h +++ b/ports/cortex_r5/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-R5/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -306,7 +306,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R5/AC6 Version 6.0.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R5/AC6 Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r5/ac6/readme_threadx.txt b/ports/cortex_r5/ac6/readme_threadx.txt index 410f78bf..bb3804c6 100644 --- a/ports/cortex_r5/ac6/readme_threadx.txt +++ b/ports/cortex_r5/ac6/readme_threadx.txt @@ -315,7 +315,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-R5 using AC6 tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-R5 using AC6 tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_r5/ac6/src/tx_thread_context_restore.S b/ports/cortex_r5/ac6/src/tx_thread_context_restore.S index 91ea27dc..ca89d5b0 100644 --- a/ports/cortex_r5/ac6/src/tx_thread_context_restore.S +++ b/ports/cortex_r5/ac6/src/tx_thread_context_restore.S @@ -59,7 +59,7 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_restore Cortex-R5/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -91,7 +91,7 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_r5/ac6/src/tx_thread_context_save.S b/ports/cortex_r5/ac6/src/tx_thread_context_save.S index 25368660..19b5356e 100644 --- a/ports/cortex_r5/ac6/src/tx_thread_context_save.S +++ b/ports/cortex_r5/ac6/src/tx_thread_context_save.S @@ -47,7 +47,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_save Cortex-R5/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -78,7 +78,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_r5/ac6/src/tx_thread_fiq_context_restore.S b/ports/cortex_r5/ac6/src/tx_thread_fiq_context_restore.S index bcd9072c..54a33e29 100644 --- a/ports/cortex_r5/ac6/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_r5/ac6/src/tx_thread_fiq_context_restore.S @@ -58,7 +58,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_context_restore Cortex-R5/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -90,7 +90,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_context_restore(VOID) diff --git a/ports/cortex_r5/ac6/src/tx_thread_fiq_context_save.S b/ports/cortex_r5/ac6/src/tx_thread_fiq_context_save.S index 0ae85699..be4da53e 100644 --- a/ports/cortex_r5/ac6/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_r5/ac6/src/tx_thread_fiq_context_save.S @@ -46,7 +46,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_context_save Cortex-R5/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @ VOID _tx_thread_fiq_context_save(VOID) diff --git a/ports/cortex_r5/ac6/src/tx_thread_fiq_nesting_end.S b/ports/cortex_r5/ac6/src/tx_thread_fiq_nesting_end.S index b7c7edbf..1f9ab175 100644 --- a/ports/cortex_r5/ac6/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_r5/ac6/src/tx_thread_fiq_nesting_end.S @@ -50,7 +50,7 @@ FIQ_MODE_BITS = 0x11 @ FIQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_nesting_end Cortex-R5/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -89,7 +89,7 @@ FIQ_MODE_BITS = 0x11 @ FIQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_end(VOID) diff --git a/ports/cortex_r5/ac6/src/tx_thread_fiq_nesting_start.S b/ports/cortex_r5/ac6/src/tx_thread_fiq_nesting_start.S index 8ad04e55..267abc14 100644 --- a/ports/cortex_r5/ac6/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_r5/ac6/src/tx_thread_fiq_nesting_start.S @@ -46,7 +46,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_nesting_start Cortex-R5/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/cortex_r5/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_r5/ac6/src/tx_thread_interrupt_control.S index 6cbb502d..f01a72de 100644 --- a/ports/cortex_r5/ac6/src/tx_thread_interrupt_control.S +++ b/ports/cortex_r5/ac6/src/tx_thread_interrupt_control.S @@ -56,7 +56,7 @@ $_tx_thread_interrupt_control: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_control Cortex-R5/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -86,7 +86,7 @@ $_tx_thread_interrupt_control: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_r5/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_r5/ac6/src/tx_thread_interrupt_disable.S index 0a50e7b0..149fe31b 100644 --- a/ports/cortex_r5/ac6/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_r5/ac6/src/tx_thread_interrupt_disable.S @@ -53,7 +53,7 @@ $_tx_thread_interrupt_disable: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_disable Cortex-R5/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ $_tx_thread_interrupt_disable: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_disable(void) diff --git a/ports/cortex_r5/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_r5/ac6/src/tx_thread_interrupt_restore.S index b5af0546..ef4779fe 100644 --- a/ports/cortex_r5/ac6/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_r5/ac6/src/tx_thread_interrupt_restore.S @@ -53,7 +53,7 @@ $_tx_thread_interrupt_restore: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_restore Cortex-R5/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -83,7 +83,7 @@ $_tx_thread_interrupt_restore: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_r5/ac6/src/tx_thread_irq_nesting_end.S b/ports/cortex_r5/ac6/src/tx_thread_irq_nesting_end.S index 829e20b8..970b41fa 100644 --- a/ports/cortex_r5/ac6/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_r5/ac6/src/tx_thread_irq_nesting_end.S @@ -50,7 +50,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_irq_nesting_end Cortex-R5/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -89,7 +89,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports/cortex_r5/ac6/src/tx_thread_irq_nesting_start.S b/ports/cortex_r5/ac6/src/tx_thread_irq_nesting_start.S index 10e834fd..11928572 100644 --- a/ports/cortex_r5/ac6/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_r5/ac6/src/tx_thread_irq_nesting_start.S @@ -46,7 +46,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_irq_nesting_start Cortex-R5/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_r5/ac6/src/tx_thread_schedule.S b/ports/cortex_r5/ac6/src/tx_thread_schedule.S index 537a6b90..6c474284 100644 --- a/ports/cortex_r5/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_r5/ac6/src/tx_thread_schedule.S @@ -61,7 +61,7 @@ $_tx_thread_schedule: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule Cortex-R5/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -94,7 +94,7 @@ $_tx_thread_schedule: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_r5/ac6/src/tx_thread_stack_build.S b/ports/cortex_r5/ac6/src/tx_thread_stack_build.S index 21fa32e9..5bdd5197 100644 --- a/ports/cortex_r5/ac6/src/tx_thread_stack_build.S +++ b/ports/cortex_r5/ac6/src/tx_thread_stack_build.S @@ -64,7 +64,7 @@ $_tx_thread_stack_build: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_stack_build Cortex-R5/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -96,7 +96,7 @@ $_tx_thread_stack_build: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_r5/ac6/src/tx_thread_system_return.S b/ports/cortex_r5/ac6/src/tx_thread_system_return.S index 55721890..732d8fff 100644 --- a/ports/cortex_r5/ac6/src/tx_thread_system_return.S +++ b/ports/cortex_r5/ac6/src/tx_thread_system_return.S @@ -63,7 +63,7 @@ $_tx_thread_system_return: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_system_return Cortex-R5/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -95,7 +95,7 @@ $_tx_thread_system_return: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_r5/ac6/src/tx_thread_vectored_context_save.S b/ports/cortex_r5/ac6/src/tx_thread_vectored_context_save.S index 00ed6fbf..6e79817d 100644 --- a/ports/cortex_r5/ac6/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_r5/ac6/src/tx_thread_vectored_context_save.S @@ -46,7 +46,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_vectored_context_save Cortex-R5/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_vectored_context_save(VOID) diff --git a/ports/cortex_r5/ac6/src/tx_timer_interrupt.S b/ports/cortex_r5/ac6/src/tx_timer_interrupt.S index 899853e7..98accd0a 100644 --- a/ports/cortex_r5/ac6/src/tx_timer_interrupt.S +++ b/ports/cortex_r5/ac6/src/tx_timer_interrupt.S @@ -71,7 +71,7 @@ $_tx_timer_interrupt: @/* FUNCTION RELEASE */ @/* */ @/* _tx_timer_interrupt Cortex-R5/AC6 */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -105,7 +105,7 @@ $_tx_timer_interrupt: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_r5/gnu/example_build/tx_initialize_low_level.S b/ports/cortex_r5/gnu/example_build/tx_initialize_low_level.S index bab0097a..6952e66c 100644 --- a/ports/cortex_r5/gnu/example_build/tx_initialize_low_level.S +++ b/ports/cortex_r5/gnu/example_build/tx_initialize_low_level.S @@ -78,7 +78,7 @@ $_tx_initialize_low_level: @/* FUNCTION RELEASE */ @/* */ @/* _tx_initialize_low_level Cortex-R5/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -111,7 +111,7 @@ $_tx_initialize_low_level: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_r5/gnu/inc/tx_port.h b/ports/cortex_r5/gnu/inc/tx_port.h index c5251fa8..ec06dd37 100644 --- a/ports/cortex_r5/gnu/inc/tx_port.h +++ b/ports/cortex_r5/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-R5/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -306,7 +306,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R5/GNU Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R5/GNU Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r5/gnu/readme_threadx.txt b/ports/cortex_r5/gnu/readme_threadx.txt index 8c26cebd..148bf630 100644 --- a/ports/cortex_r5/gnu/readme_threadx.txt +++ b/ports/cortex_r5/gnu/readme_threadx.txt @@ -486,7 +486,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-R5 using GNU tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-R5 using GNU tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_r5/gnu/src/tx_thread_context_restore.S b/ports/cortex_r5/gnu/src/tx_thread_context_restore.S index cdca28e5..9b6409ec 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_context_restore.S +++ b/ports/cortex_r5/gnu/src/tx_thread_context_restore.S @@ -60,7 +60,7 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_restore Cortex-R5/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -92,7 +92,7 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_r5/gnu/src/tx_thread_context_save.S b/ports/cortex_r5/gnu/src/tx_thread_context_save.S index ac7a98f4..4b392465 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_context_save.S +++ b/ports/cortex_r5/gnu/src/tx_thread_context_save.S @@ -48,7 +48,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_save Cortex-R5/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -79,7 +79,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_r5/gnu/src/tx_thread_fiq_context_restore.S b/ports/cortex_r5/gnu/src/tx_thread_fiq_context_restore.S index 955a9e8c..021144db 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_fiq_context_restore.S +++ b/ports/cortex_r5/gnu/src/tx_thread_fiq_context_restore.S @@ -59,7 +59,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_context_restore Cortex-R5/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -91,7 +91,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_context_restore(VOID) diff --git a/ports/cortex_r5/gnu/src/tx_thread_fiq_context_save.S b/ports/cortex_r5/gnu/src/tx_thread_fiq_context_save.S index 576ecc4c..e3a94fe8 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_fiq_context_save.S +++ b/ports/cortex_r5/gnu/src/tx_thread_fiq_context_save.S @@ -47,7 +47,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_context_save Cortex-R5/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -78,7 +78,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @ VOID _tx_thread_fiq_context_save(VOID) diff --git a/ports/cortex_r5/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_r5/gnu/src/tx_thread_fiq_nesting_end.S index d3e4972a..c7e326d4 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_fiq_nesting_end.S +++ b/ports/cortex_r5/gnu/src/tx_thread_fiq_nesting_end.S @@ -50,7 +50,7 @@ FIQ_MODE_BITS = 0x11 @ FIQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_nesting_end Cortex-R5/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -89,7 +89,7 @@ FIQ_MODE_BITS = 0x11 @ FIQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_end(VOID) diff --git a/ports/cortex_r5/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_r5/gnu/src/tx_thread_fiq_nesting_start.S index 0b2ef7e0..8a53e6dd 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_fiq_nesting_start.S +++ b/ports/cortex_r5/gnu/src/tx_thread_fiq_nesting_start.S @@ -46,7 +46,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_fiq_nesting_start Cortex-R5/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_fiq_nesting_start(VOID) diff --git a/ports/cortex_r5/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_r5/gnu/src/tx_thread_interrupt_control.S index ac10ca1e..fae99ffe 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_interrupt_control.S +++ b/ports/cortex_r5/gnu/src/tx_thread_interrupt_control.S @@ -56,7 +56,7 @@ $_tx_thread_interrupt_control: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_control Cortex-R5/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -86,7 +86,7 @@ $_tx_thread_interrupt_control: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_r5/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_r5/gnu/src/tx_thread_interrupt_disable.S index dd2ba781..4fa3d25e 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_interrupt_disable.S +++ b/ports/cortex_r5/gnu/src/tx_thread_interrupt_disable.S @@ -53,7 +53,7 @@ $_tx_thread_interrupt_disable: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_disable Cortex-R5/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ $_tx_thread_interrupt_disable: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_disable(void) diff --git a/ports/cortex_r5/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_r5/gnu/src/tx_thread_interrupt_restore.S index 885b43c8..5cd41268 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_interrupt_restore.S +++ b/ports/cortex_r5/gnu/src/tx_thread_interrupt_restore.S @@ -53,7 +53,7 @@ $_tx_thread_interrupt_restore: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_restore Cortex-R5/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -83,7 +83,7 @@ $_tx_thread_interrupt_restore: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_r5/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_r5/gnu/src/tx_thread_irq_nesting_end.S index 8d1d1952..16a6ce01 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports/cortex_r5/gnu/src/tx_thread_irq_nesting_end.S @@ -50,7 +50,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_irq_nesting_end Cortex-R5/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -89,7 +89,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports/cortex_r5/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_r5/gnu/src/tx_thread_irq_nesting_start.S index e2d38c62..36cdcd44 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports/cortex_r5/gnu/src/tx_thread_irq_nesting_start.S @@ -46,7 +46,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_irq_nesting_start Cortex-R5/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_r5/gnu/src/tx_thread_schedule.S b/ports/cortex_r5/gnu/src/tx_thread_schedule.S index e62fc22c..d7b6ebce 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_r5/gnu/src/tx_thread_schedule.S @@ -62,7 +62,7 @@ $_tx_thread_schedule: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule Cortex-R5/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -95,7 +95,7 @@ $_tx_thread_schedule: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_r5/gnu/src/tx_thread_stack_build.S b/ports/cortex_r5/gnu/src/tx_thread_stack_build.S index bed62a6d..2e7a01da 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_r5/gnu/src/tx_thread_stack_build.S @@ -64,7 +64,7 @@ $_tx_thread_stack_build: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_stack_build Cortex-R5/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -96,7 +96,7 @@ $_tx_thread_stack_build: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_r5/gnu/src/tx_thread_system_return.S b/ports/cortex_r5/gnu/src/tx_thread_system_return.S index c7c551a5..438a2298 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_system_return.S +++ b/ports/cortex_r5/gnu/src/tx_thread_system_return.S @@ -64,7 +64,7 @@ $_tx_thread_system_return: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_system_return Cortex-R5/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -96,7 +96,7 @@ $_tx_thread_system_return: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_r5/gnu/src/tx_thread_vectored_context_save.S b/ports/cortex_r5/gnu/src/tx_thread_vectored_context_save.S index 3d99f69f..d9e6c0ae 100644 --- a/ports/cortex_r5/gnu/src/tx_thread_vectored_context_save.S +++ b/ports/cortex_r5/gnu/src/tx_thread_vectored_context_save.S @@ -47,7 +47,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_vectored_context_save Cortex-R5/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -78,7 +78,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_vectored_context_save(VOID) diff --git a/ports/cortex_r5/gnu/src/tx_timer_interrupt.S b/ports/cortex_r5/gnu/src/tx_timer_interrupt.S index 050258bd..a69a4b81 100644 --- a/ports/cortex_r5/gnu/src/tx_timer_interrupt.S +++ b/ports/cortex_r5/gnu/src/tx_timer_interrupt.S @@ -71,7 +71,7 @@ $_tx_timer_interrupt: @/* FUNCTION RELEASE */ @/* */ @/* _tx_timer_interrupt Cortex-R5/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -105,7 +105,7 @@ $_tx_timer_interrupt: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_r5/green/example_build/azure_rtos_workspace.gpj b/ports/cortex_r5/green/example_build/azure_rtos_workspace.gpj new file mode 100644 index 00000000..2d8209c3 --- /dev/null +++ b/ports/cortex_r5/green/example_build/azure_rtos_workspace.gpj @@ -0,0 +1,12 @@ +#!gbuild +primaryTarget=arm_standalone.tgt +[Project] + -bsp generic + -G + -cpu=cortexr5 + -littleendian +sample_threadx.gpj [Program] +sample_threadx_el.gpj [Program] +tx.gpj [Library] +txe.gpj [Library] +..\readme_threadx.txt diff --git a/ports/cortex_r5/green/example_build/reset.arm b/ports/cortex_r5/green/example_build/reset.arm new file mode 100644 index 00000000..37ea5885 --- /dev/null +++ b/ports/cortex_r5/green/example_build/reset.arm @@ -0,0 +1,45 @@ +# +# +#/* Define the Cortex-R5 vector area. This should be located or copied to 0. */ +# + + .section ".reset", .text + .globl __vectors +__vectors: + B __entry # Reset goes to the entry function + LDR pc,UNDEFINED # Undefined handler + LDR pc,SWI # Software interrupt handler + LDR pc,PREFETCH # Prefetch exception handler + LDR pc,ABORT # Abort exception handler + LDR pc,RESERVED # Reserved exception handler + LDR pc,IRQ # IRQ interrupt handler + LDR pc,FIQ # FIQ interrupt handler +# +# +__entry: + LDR sp,STACK # Setup stack pointer + LDR pc,START # Jump to Green Hills startup +# +# +STACK: + .data.w __ghsend_stack +START: + .data.w _start # Reset goes to startup function +UNDEFINED: + .data.w __tx_undefined # Undefined handler +SWI: + .data.w __tx_swi_interrupt # Software interrupt handler +PREFETCH: + .data.w __tx_prefetch_handler # Prefetch exception handler +ABORT: + .data.w __tx_abort_handler # Abort exception handler +RESERVED: + .data.w __tx_reserved_handler # Reserved exception handler +IRQ: + .data.w __tx_irq_handler # IRQ interrupt handler +FIQ: + .data.w __tx_fiq_handler # FIQ interrupt handler +# +# + .type __vectors,$function + .size __vectors,.-__vectors diff --git a/ports/cortex_r5/green/example_build/sample_threadx.c b/ports/cortex_r5/green/example_build/sample_threadx.c new file mode 100644 index 00000000..418ec634 --- /dev/null +++ b/ports/cortex_r5/green/example_build/sample_threadx.c @@ -0,0 +1,369 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_r5/green/example_build/sample_threadx.con b/ports/cortex_r5/green/example_build/sample_threadx.con new file mode 100644 index 00000000..c4d4c538 --- /dev/null +++ b/ports/cortex_r5/green/example_build/sample_threadx.con @@ -0,0 +1,11 @@ +target_connection.00000000.title="Simulator connection for ThreadX" +target_connection.00000000.type="Custom" +target_connection.00000000.short_type="Custom" +target_connection.00000000.args="simarm -cpu=cortexr5 -fpu -rom" +target_connection.00000000.command="simarm -cpu=cortexr5 -fpu -rom" +target_connection.00000000.logfile="" +target_connection.00000000.mode="download" +target_connection.00000000.setup_script="" +target_connection.00000000.sane="yes" +target_connection.00000000.log="no" +target_connection.00000000.timestamp="1192825758" diff --git a/ports/cortex_r5/green/example_build/sample_threadx.gpj b/ports/cortex_r5/green/example_build/sample_threadx.gpj new file mode 100644 index 00000000..b9b2c04c --- /dev/null +++ b/ports/cortex_r5/green/example_build/sample_threadx.gpj @@ -0,0 +1,11 @@ +#!gbuild +[Program] + -I../../../../common/inc + -I../../../../ports_common_green/inc + -I../inc +reset.arm +tx_initialize_low_level.arm +sample_threadx.c +tx.a +sample_threadx.ld +sample_threadx.con diff --git a/ports/cortex_r5/green/example_build/sample_threadx.ld b/ports/cortex_r5/green/example_build/sample_threadx.ld new file mode 100644 index 00000000..8d1ab4df --- /dev/null +++ b/ports/cortex_r5/green/example_build/sample_threadx.ld @@ -0,0 +1,44 @@ +# The following explains what the default Green Hills sections are for: +# +# picbase - base of the text sections, relocatable in -pic mode +# text - text section +# syscall - syscall section, for host I/O under Multi +# fixaddr/fixtype - for PIC/PID fixups +# rodata - read only data +# romdata - the ROM image of .data +# romsdata - the ROM image of .sdata +# secinfo - section information section, used by the start-up code +# pidbase - base of the data sections, relocatable in -pid mode +# sdabase - base of the small data area section pointer +# sbss - small BSS (zeroed data) section +# sdata - small data section +# data - non-zeroed writeable data section +# bss - zeroed data section +# heap - the heap, grows upward +# stack - the stack, grows downward + +-sec +{ + .reset 0x000000 : + .picbase 0x1000 : + .text : + .comment : + .intercall : + .interfunc : + .syscall : + .fixaddr : + .fixtype : + .rodata : + .romdata ROM(.data) : + .romsdata ROM(.sdata) : + .secinfo : + .pidbase align(16) : + .sdabase : + .sbss : + .sdata : + .data : + .bss : + .heap align(16) pad(0x10000) : + .stack align(16) pad(0x1000) : + .free_mem align(16) pad(0x10000) : +} diff --git a/ports/cortex_r5/green/example_build/sample_threadx_el.gpj b/ports/cortex_r5/green/example_build/sample_threadx_el.gpj new file mode 100644 index 00000000..a51049ca --- /dev/null +++ b/ports/cortex_r5/green/example_build/sample_threadx_el.gpj @@ -0,0 +1,13 @@ +#!gbuild +[Program] + -DTX_ENABLE_EVENT_LOGGING + -I../../../../common/inc + -I../../../../ports_common_green/inc + -I../inc +reset.arm +tx_initialize_low_level.arm +sample_threadx.c +txe.a +sample_threadx_el.ld +sample_threadx.con +readme_threadx.txt diff --git a/ports/cortex_r5/green/example_build/sample_threadx_el.ld b/ports/cortex_r5/green/example_build/sample_threadx_el.ld new file mode 100644 index 00000000..33c0f934 --- /dev/null +++ b/ports/cortex_r5/green/example_build/sample_threadx_el.ld @@ -0,0 +1,45 @@ +# The following explains what the default Green Hills sections are for: +# +# picbase - base of the text sections, relocatable in -pic mode +# text - text section +# syscall - syscall section, for host I/O under Multi +# fixaddr/fixtype - for PIC/PID fixups +# rodata - read only data +# romdata - the ROM image of .data +# romsdata - the ROM image of .sdata +# secinfo - section information section, used by the start-up code +# pidbase - base of the data sections, relocatable in -pid mode +# sdabase - base of the small data area section pointer +# sbss - small BSS (zeroed data) section +# sdata - small data section +# data - non-zeroed writeable data section +# bss - zeroed data section +# heap - the heap, grows upward +# stack - the stack, grows downward + +-sec +{ + .reset 0x000000 : + .picbase 0x1000 : + .text : + .comment : + .intercall : + .interfunc : + .syscall : + .fixaddr : + .fixtype : + .rodata : + .romdata ROM(.data) : + .romsdata ROM(.sdata) : + .secinfo : + .pidbase align(16) : + .sdabase : + .sbss : + .sdata : + .data : + .bss : + .heap align(16) pad(0x1000) : + .stack align(16) pad(0x1000) : + .eventlog align(16) pad(0x10000) : + .free_mem align(16) pad(0x10000) : +} diff --git a/ports/cortex_r5/green/example_build/tx.gpj b/ports/cortex_r5/green/example_build/tx.gpj new file mode 100644 index 00000000..afbd6bef --- /dev/null +++ b/ports/cortex_r5/green/example_build/tx.gpj @@ -0,0 +1,283 @@ +#!gbuild +[Library] + -I../../../../common/inc + -I../../../../ports_common_green/inc + -I../inc +..\..\..\..\common\inc\tx_api.h +..\..\..\..\common\inc\tx_block_pool.h +..\..\..\..\common\inc\tx_byte_pool.h +..\..\..\..\common\inc\tx_event_flags.h +..\..\..\..\common\inc\tx_initialize.h +..\..\..\..\common\inc\tx_mutex.h +..\..\..\..\common\inc\tx_queue.h +..\..\..\..\common\inc\tx_semaphore.h +..\..\..\..\common\inc\tx_thread.h +..\..\..\..\common\inc\tx_timer.h +..\..\..\..\common\inc\tx_trace.h +..\..\..\..\common\inc\tx_user_sample.h +..\inc\tx_port.h +..\..\..\..\ports_common_green\inc\tx_el.h +..\..\..\..\ports_common_green\inc\tx_ghs.h +..\src\tx_thread_context_restore.arm +..\src\tx_thread_context_save.arm +..\src\tx_thread_fiq_context_restore.arm +..\src\tx_thread_fiq_context_save.arm +..\src\tx_thread_fiq_nesting_end.arm +..\src\tx_thread_fiq_nesting_start.arm +..\src\tx_thread_interrupt_control.arm +..\src\tx_thread_interrupt_disable.arm +..\src\tx_thread_interrupt_restore.arm +..\src\tx_thread_irq_nesting_end.arm +..\src\tx_thread_irq_nesting_start.arm +..\src\tx_thread_schedule.arm +..\src\tx_thread_stack_build.arm +..\src\tx_thread_system_return.arm +..\src\tx_thread_vectored_context_save.arm +..\src\tx_timer_interrupt.arm +..\..\..\..\common\src\tx_block_allocate.c +..\..\..\..\common\src\tx_block_pool_cleanup.c +..\..\..\..\common\src\tx_block_pool_create.c +..\..\..\..\common\src\tx_block_pool_delete.c +..\..\..\..\common\src\tx_block_pool_info_get.c +..\..\..\..\common\src\tx_block_pool_initialize.c +..\..\..\..\common\src\tx_block_pool_performance_info_get.c +..\..\..\..\common\src\tx_block_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_block_pool_prioritize.c +..\..\..\..\common\src\tx_block_release.c +..\..\..\..\common\src\tx_byte_allocate.c +..\..\..\..\common\src\tx_byte_pool_cleanup.c +..\..\..\..\common\src\tx_byte_pool_create.c +..\..\..\..\common\src\tx_byte_pool_delete.c +..\..\..\..\common\src\tx_byte_pool_info_get.c +..\..\..\..\common\src\tx_byte_pool_initialize.c +..\..\..\..\common\src\tx_byte_pool_performance_info_get.c +..\..\..\..\common\src\tx_byte_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_byte_pool_prioritize.c +..\..\..\..\common\src\tx_byte_pool_search.c +..\..\..\..\common\src\tx_byte_release.c +..\..\..\..\common\src\tx_event_flags_cleanup.c +..\..\..\..\common\src\tx_event_flags_create.c +..\..\..\..\common\src\tx_event_flags_delete.c +..\..\..\..\common\src\tx_event_flags_get.c +..\..\..\..\common\src\tx_event_flags_info_get.c +..\..\..\..\common\src\tx_event_flags_initialize.c +..\..\..\..\common\src\tx_event_flags_performance_info_get.c +..\..\..\..\common\src\tx_event_flags_performance_system_info_get.c +..\..\..\..\common\src\tx_event_flags_set.c +..\..\..\..\common\src\tx_event_flags_set_notify.c +..\..\..\..\common\src\tx_initialize_high_level.c +..\..\..\..\common\src\tx_initialize_kernel_enter.c +..\..\..\..\common\src\tx_initialize_kernel_setup.c +..\..\..\..\common\src\tx_mutex_cleanup.c +..\..\..\..\common\src\tx_mutex_create.c +..\..\..\..\common\src\tx_mutex_delete.c +..\..\..\..\common\src\tx_mutex_get.c +..\..\..\..\common\src\tx_mutex_info_get.c +..\..\..\..\common\src\tx_mutex_initialize.c +..\..\..\..\common\src\tx_mutex_performance_info_get.c +..\..\..\..\common\src\tx_mutex_performance_system_info_get.c +..\..\..\..\common\src\tx_mutex_prioritize.c +..\..\..\..\common\src\tx_mutex_priority_change.c +..\..\..\..\common\src\tx_mutex_put.c +..\..\..\..\common\src\tx_queue_cleanup.c +..\..\..\..\common\src\tx_queue_create.c +..\..\..\..\common\src\tx_queue_delete.c +..\..\..\..\common\src\tx_queue_flush.c +..\..\..\..\common\src\tx_queue_front_send.c +..\..\..\..\common\src\tx_queue_info_get.c +..\..\..\..\common\src\tx_queue_initialize.c +..\..\..\..\common\src\tx_queue_performance_info_get.c +..\..\..\..\common\src\tx_queue_performance_system_info_get.c +..\..\..\..\common\src\tx_queue_prioritize.c +..\..\..\..\common\src\tx_queue_receive.c +..\..\..\..\common\src\tx_queue_send.c +..\..\..\..\common\src\tx_queue_send_notify.c +..\..\..\..\common\src\tx_semaphore_ceiling_put.c +..\..\..\..\common\src\tx_semaphore_cleanup.c +..\..\..\..\common\src\tx_semaphore_create.c +..\..\..\..\common\src\tx_semaphore_delete.c +..\..\..\..\common\src\tx_semaphore_get.c +..\..\..\..\common\src\tx_semaphore_info_get.c +..\..\..\..\common\src\tx_semaphore_initialize.c +..\..\..\..\common\src\tx_semaphore_performance_info_get.c +..\..\..\..\common\src\tx_semaphore_performance_system_info_get.c +..\..\..\..\common\src\tx_semaphore_prioritize.c +..\..\..\..\common\src\tx_semaphore_put.c +..\..\..\..\common\src\tx_semaphore_put_notify.c +..\..\..\..\common\src\tx_thread_create.c +..\..\..\..\common\src\tx_thread_delete.c +..\..\..\..\common\src\tx_thread_entry_exit_notify.c +..\..\..\..\common\src\tx_thread_identify.c +..\..\..\..\common\src\tx_thread_info_get.c +..\..\..\..\common\src\tx_thread_initialize.c +..\..\..\..\common\src\tx_thread_performance_info_get.c +..\..\..\..\common\src\tx_thread_performance_system_info_get.c +..\..\..\..\common\src\tx_thread_preemption_change.c +..\..\..\..\common\src\tx_thread_priority_change.c +..\..\..\..\common\src\tx_thread_relinquish.c +..\..\..\..\common\src\tx_thread_reset.c +..\..\..\..\common\src\tx_thread_resume.c +..\..\..\..\common\src\tx_thread_shell_entry.c +..\..\..\..\common\src\tx_thread_sleep.c +..\..\..\..\common\src\tx_thread_stack_analyze.c +..\..\..\..\common\src\tx_thread_stack_error_handler.c +..\..\..\..\common\src\tx_thread_stack_error_notify.c +..\..\..\..\common\src\tx_thread_suspend.c +..\..\..\..\common\src\tx_thread_system_preempt_check.c +..\..\..\..\common\src\tx_thread_system_resume.c +..\..\..\..\common\src\tx_thread_system_suspend.c +..\..\..\..\common\src\tx_thread_terminate.c +..\..\..\..\common\src\tx_thread_time_slice.c +..\..\..\..\common\src\tx_thread_time_slice_change.c +..\..\..\..\common\src\tx_thread_timeout.c +..\..\..\..\common\src\tx_thread_wait_abort.c +..\..\..\..\common\src\tx_time_get.c +..\..\..\..\common\src\tx_time_set.c +..\..\..\..\common\src\tx_timer_activate.c +..\..\..\..\common\src\tx_timer_change.c +..\..\..\..\common\src\tx_timer_create.c +..\..\..\..\common\src\tx_timer_deactivate.c +..\..\..\..\common\src\tx_timer_delete.c +..\..\..\..\common\src\tx_timer_expiration_process.c +..\..\..\..\common\src\tx_timer_info_get.c +..\..\..\..\common\src\tx_timer_initialize.c +..\..\..\..\common\src\tx_timer_performance_info_get.c +..\..\..\..\common\src\tx_timer_performance_system_info_get.c +..\..\..\..\common\src\tx_timer_system_activate.c +..\..\..\..\common\src\tx_timer_system_deactivate.c +..\..\..\..\common\src\tx_timer_thread_entry.c +..\..\..\..\common\src\tx_trace_buffer_full_notify.c +..\..\..\..\common\src\tx_trace_disable.c +..\..\..\..\common\src\tx_trace_enable.c +..\..\..\..\common\src\tx_trace_event_filter.c +..\..\..\..\common\src\tx_trace_event_unfilter.c +..\..\..\..\common\src\tx_trace_initialize.c +..\..\..\..\common\src\tx_trace_interrupt_control.c +..\..\..\..\common\src\tx_trace_isr_enter_insert.c +..\..\..\..\common\src\tx_trace_isr_exit_insert.c +..\..\..\..\common\src\tx_trace_object_register.c +..\..\..\..\common\src\tx_trace_object_unregister.c +..\..\..\..\common\src\tx_trace_user_event_insert.c +..\..\..\..\common\src\txe_block_allocate.c +..\..\..\..\common\src\txe_block_pool_create.c +..\..\..\..\common\src\txe_block_pool_delete.c +..\..\..\..\common\src\txe_block_pool_info_get.c +..\..\..\..\common\src\txe_block_pool_prioritize.c +..\..\..\..\common\src\txe_block_release.c +..\..\..\..\common\src\txe_byte_allocate.c +..\..\..\..\common\src\txe_byte_pool_create.c +..\..\..\..\common\src\txe_byte_pool_delete.c +..\..\..\..\common\src\txe_byte_pool_info_get.c +..\..\..\..\common\src\txe_byte_pool_prioritize.c +..\..\..\..\common\src\txe_byte_release.c +..\..\..\..\common\src\txe_event_flags_create.c +..\..\..\..\common\src\txe_event_flags_delete.c +..\..\..\..\common\src\txe_event_flags_get.c +..\..\..\..\common\src\txe_event_flags_info_get.c +..\..\..\..\common\src\txe_event_flags_set.c +..\..\..\..\common\src\txe_event_flags_set_notify.c +..\..\..\..\common\src\txe_mutex_create.c +..\..\..\..\common\src\txe_mutex_delete.c +..\..\..\..\common\src\txe_mutex_get.c +..\..\..\..\common\src\txe_mutex_info_get.c +..\..\..\..\common\src\txe_mutex_prioritize.c +..\..\..\..\common\src\txe_mutex_put.c +..\..\..\..\common\src\txe_queue_create.c +..\..\..\..\common\src\txe_queue_delete.c +..\..\..\..\common\src\txe_queue_flush.c +..\..\..\..\common\src\txe_queue_front_send.c +..\..\..\..\common\src\txe_queue_info_get.c +..\..\..\..\common\src\txe_queue_prioritize.c +..\..\..\..\common\src\txe_queue_receive.c +..\..\..\..\common\src\txe_queue_send.c +..\..\..\..\common\src\txe_queue_send_notify.c +..\..\..\..\common\src\txe_semaphore_ceiling_put.c +..\..\..\..\common\src\txe_semaphore_create.c +..\..\..\..\common\src\txe_semaphore_delete.c +..\..\..\..\common\src\txe_semaphore_get.c +..\..\..\..\common\src\txe_semaphore_info_get.c +..\..\..\..\common\src\txe_semaphore_prioritize.c +..\..\..\..\common\src\txe_semaphore_put.c +..\..\..\..\common\src\txe_semaphore_put_notify.c +..\..\..\..\common\src\txe_thread_create.c +..\..\..\..\common\src\txe_thread_delete.c +..\..\..\..\common\src\txe_thread_entry_exit_notify.c +..\..\..\..\common\src\txe_thread_info_get.c +..\..\..\..\common\src\txe_thread_preemption_change.c +..\..\..\..\common\src\txe_thread_priority_change.c +..\..\..\..\common\src\txe_thread_relinquish.c +..\..\..\..\common\src\txe_thread_reset.c +..\..\..\..\common\src\txe_thread_resume.c +..\..\..\..\common\src\txe_thread_suspend.c +..\..\..\..\common\src\txe_thread_terminate.c +..\..\..\..\common\src\txe_thread_time_slice_change.c +..\..\..\..\common\src\txe_thread_wait_abort.c +..\..\..\..\common\src\txe_timer_activate.c +..\..\..\..\common\src\txe_timer_change.c +..\..\..\..\common\src\txe_timer_create.c +..\..\..\..\common\src\txe_timer_deactivate.c +..\..\..\..\common\src\txe_timer_delete.c +..\..\..\..\common\src\txe_timer_info_get.c +..\..\..\..\ports_common_green\src\tx_el.c +..\..\..\..\ports_common_green\src\tx_ghs.c +..\..\..\..\ports_common_green\src\tx_ghse.c +..\..\..\..\ports_common_green\src\txr_block_allocate.c +..\..\..\..\ports_common_green\src\txr_block_pool_create.c +..\..\..\..\ports_common_green\src\txr_block_pool_delete.c +..\..\..\..\ports_common_green\src\txr_block_pool_info_get.c +..\..\..\..\ports_common_green\src\txr_block_pool_prioritize.c +..\..\..\..\ports_common_green\src\txr_block_release.c +..\..\..\..\ports_common_green\src\txr_byte_allocate.c +..\..\..\..\ports_common_green\src\txr_byte_pool_create.c +..\..\..\..\ports_common_green\src\txr_byte_pool_delete.c +..\..\..\..\ports_common_green\src\txr_byte_pool_info_get.c +..\..\..\..\ports_common_green\src\txr_byte_pool_prioritize.c +..\..\..\..\ports_common_green\src\txr_byte_release.c +..\..\..\..\ports_common_green\src\txr_event_flags_create.c +..\..\..\..\ports_common_green\src\txr_event_flags_delete.c +..\..\..\..\ports_common_green\src\txr_event_flags_get.c +..\..\..\..\ports_common_green\src\txr_event_flags_info_get.c +..\..\..\..\ports_common_green\src\txr_event_flags_set.c +..\..\..\..\ports_common_green\src\txr_event_flags_set_notify.c +..\..\..\..\ports_common_green\src\txr_ghs.c +..\..\..\..\ports_common_green\src\txr_mutex_create.c +..\..\..\..\ports_common_green\src\txr_mutex_delete.c +..\..\..\..\ports_common_green\src\txr_mutex_get.c +..\..\..\..\ports_common_green\src\txr_mutex_info_get.c +..\..\..\..\ports_common_green\src\txr_mutex_prioritize.c +..\..\..\..\ports_common_green\src\txr_mutex_put.c +..\..\..\..\ports_common_green\src\txr_queue_create.c +..\..\..\..\ports_common_green\src\txr_queue_delete.c +..\..\..\..\ports_common_green\src\txr_queue_flush.c +..\..\..\..\ports_common_green\src\txr_queue_front_send.c +..\..\..\..\ports_common_green\src\txr_queue_info_get.c +..\..\..\..\ports_common_green\src\txr_queue_prioritize.c +..\..\..\..\ports_common_green\src\txr_queue_receive.c +..\..\..\..\ports_common_green\src\txr_queue_send.c +..\..\..\..\ports_common_green\src\txr_queue_send_notify.c +..\..\..\..\ports_common_green\src\txr_semaphore_ceiling_put.c +..\..\..\..\ports_common_green\src\txr_semaphore_create.c +..\..\..\..\ports_common_green\src\txr_semaphore_delete.c +..\..\..\..\ports_common_green\src\txr_semaphore_get.c +..\..\..\..\ports_common_green\src\txr_semaphore_info_get.c +..\..\..\..\ports_common_green\src\txr_semaphore_prioritize.c +..\..\..\..\ports_common_green\src\txr_semaphore_put.c +..\..\..\..\ports_common_green\src\txr_semaphore_put_notify.c +..\..\..\..\ports_common_green\src\txr_thread_create.c +..\..\..\..\ports_common_green\src\txr_thread_delete.c +..\..\..\..\ports_common_green\src\txr_thread_entry_exit_notify.c +..\..\..\..\ports_common_green\src\txr_thread_info_get.c +..\..\..\..\ports_common_green\src\txr_thread_preemption_change.c +..\..\..\..\ports_common_green\src\txr_thread_priority_change.c +..\..\..\..\ports_common_green\src\txr_thread_reset.c +..\..\..\..\ports_common_green\src\txr_thread_resume.c +..\..\..\..\ports_common_green\src\txr_thread_suspend.c +..\..\..\..\ports_common_green\src\txr_thread_terminate.c +..\..\..\..\ports_common_green\src\txr_thread_time_slice_change.c +..\..\..\..\ports_common_green\src\txr_thread_wait_abort.c +..\..\..\..\ports_common_green\src\txr_timer_activate.c +..\..\..\..\ports_common_green\src\txr_timer_change.c +..\..\..\..\ports_common_green\src\txr_timer_create.c +..\..\..\..\ports_common_green\src\txr_timer_deactivate.c +..\..\..\..\ports_common_green\src\txr_timer_delete.c +..\..\..\..\ports_common_green\src\txr_timer_info_get.c diff --git a/ports/cortex_r5/green/example_build/tx_initialize_low_level.arm b/ports/cortex_r5/green/example_build/tx_initialize_low_level.arm new file mode 100644 index 00000000..64d60464 --- /dev/null +++ b/ports/cortex_r5/green/example_build/tx_initialize_low_level.arm @@ -0,0 +1,319 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_initialize.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + SVC_MODE = 0xD3 # Disable IRQ/FIQ SVC mode + IRQ_MODE = 0xD2 # Disable IRQ/FIQ IRQ mode + FIQ_MODE = 0xD1 # Disable IRQ/FIQ FIQ mode + SYS_MODE = 0xDF # Disable IRQ/FIQ SYS mode + MODE_MASK = 0x1F # Mode mask + FIQ_STACK_SIZE = 512 # FIQ stack size + IRQ_STACK_SIZE = 1024 # IRQ stack size + SYS_STACK_SIZE = 1024 # SYS stack size + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-R5/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_initialize_low_level(VOID) +{ */ + .globl _tx_initialize_low_level +_tx_initialize_low_level: + + /****** NOTE ****** We must be in SVC MODE at this point. Some monitors + enter this routine in USER mode and require a software interrupt to + change into SVC mode. */ + + /* Save the system stack pointer. */ + /* _tx_thread_system_stack_ptr = (VOID_PTR) (sp); */ + + LDR r1,=_tx_thread_system_stack_ptr # Pickup address of system stack ptr + STR sp, [r1] # Save system stack + + /* Pickup the first available memory address. */ + + LDR r0,=__ghsbegin_free_mem # Pickup free memory address + + /* Setup initial stack pointers for IRQ and FIQ modes. */ + + MRS r12, CPSR # Pickup current CPSR + MOV r1, r0 # Get first available memory +#ifdef TX_ENABLE_IRQ_NESTING + /* Setup the system mode stack for nested interrupt support */ + LDR r2, =SYS_STACK_SIZE # Pickup stack size + BIC r3, r12, MODE_MASK # Clear mode bits + ORR r3, r3, SYS_MODE # Build SYS mode CPSR + MSR CPSR_c, r3 # Enter SYS mode + ADD r1, r1, r2 # Calculate start of SYS stack + SUB r1, r1, 1 # Backup one byte + BIC r1, r1, 7 # Insure 8-byte alignment + MOV sp, r1 # Setup SYS stack pointer +#endif + LDR r2, =FIQ_STACK_SIZE # Pickup stack size + BIC r3, r12, MODE_MASK # Clear mode bits + ORR r3, r3, FIQ_MODE # Build FIQ mode CPSR + MSR CPSR_c, r3 # Enter FIQ mode + ADD r1, r1, r2 # Calculate start of FIQ stack + SUB r1, r1, 1 # Backup one byte + BIC r1, r1, 7 # Insure 8-byte alignment + MOV sp, r1 # Setup FIQ stack pointer + MOV r10, 0 # Clear sl + MOV r11, 0 # Clear fp + LDR r2, =IRQ_STACK_SIZE # Pickup IRQ (system stack size) + BIC r3, r12, MODE_MASK # Clear mode bits + ORR r3, r3, IRQ_MODE # Build IRQ mode CPSR + MSR CPSR_c, r3 # Enter IRQ mode + ADD r1, r1, r2 # Calculate start of IRQ stack + SUB r1, r1, 1 # Backup one byte + BIC r1, r1, 7 # Insure 8-byte alignment + MOV sp, r1 # Setup IRQ stack pointer + MSR CPSR_c, r12 # Restore previous mode + ADD r0, r1, 4 # Adjust the new free memory + + + /* Save the first available memory address. */ + /* _tx_initialize_unused_memory = (VOID_PTR) __ghsbegin_free_mem + [SYS_STACK] + FIQ_STACK + IRQ_STACK; */ + + LDR r2,=_tx_initialize_unused_memory # Pickup unused memory ptr address + STR r0, [r2] # Save first free memory address + + + /* Setup Timer for periodic interrupts. To generate timer interrupts with + the Green Hills simulator, enter the following command in the target + window: timer 9999 irq */ + + /* Done, return to caller. */ + + RET # Return to caller + + .type _tx_initialize_low_level,$function + .size _tx_initialize_low_level,.-_tx_initialize_low_level +/* } */ + + +/* Define shells for each of the interrupt vectors. */ + + .globl __tx_undefined +__tx_undefined: + B __tx_undefined # Undefined handler + + .type __tx_undefined,$function + .size __tx_undefined,.-__tx_undefined + + .globl __tx_swi_interrupt +__tx_swi_interrupt: + B __tx_swi_interrupt # Software interrupt handler + + .type __tx_swi_interrupt,$function + .size __tx_swi_interrupt,.-__tx_swi_interrupt + + .globl __tx_prefetch_handler +__tx_prefetch_handler: + B __tx_prefetch_handler # Prefetch exception handler + + .type __tx_prefetch_handler,$function + .size __tx_prefetch_handler,.-__tx_prefetch_handler + + .globl __tx_abort_handler +__tx_abort_handler: + B __tx_abort_handler # Abort exception handler + + .type __tx_abort_handler,$function + .size __tx_abort_handler,.-__tx_abort_handler + + .globl __tx_reserved_handler +__tx_reserved_handler: + B __tx_reserved_handler # Reserved exception handler + + .type __tx_reserved_handler,$function + .size __tx_reserved_handler,.-__tx_reserved_handler + + .globl __tx_irq_handler + .globl __tx_irq_processing_return +__tx_irq_handler: + + /* Jump to context save to save system context. */ + B _tx_thread_context_save + + .type __tx_irq_handler,$function + .size __tx_irq_handler,.-__tx_irq_handler + +__tx_irq_processing_return: + + /* At this point execution is still in the IRQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. */ + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 0 # Build interrupt code + BL _tx_el_interrupt # Call interrupt event logging +#endif + + /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start + from IRQ mode with interrupts disabled. This routine switches to the + system mode and returns with IRQ interrupts enabled. + + NOTE: It is very important to ensure all IRQ interrupts are cleared + prior to enabling nested IRQ interrupts. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_start +#endif + + + /* For debug purpose, execute the timer interrupt processing here. In + a real system, some kind of status indication would have to be checked + before the timer interrupt handler could be called. */ + BL _tx_timer_interrupt # Timer interrupt handler + + /* Application IRQ handlers can be called here! */ + + /* If interrupt nesting was started earlier, the end of interrupt nesting + service must be called before returning to _tx_thread_context_restore. + This routine returns in processing in IRQ mode with interrupts disabled. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_end +#endif + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 0 # Build interrupt code + BL _tx_el_interrupt_end # Call interrupt event logging +#endif + + /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + .type __tx_irq_processing_return,$function + .size __tx_irq_processing_return,.-__tx_irq_processing_return + +#ifdef TX_ENABLE_FIQ_SUPPORT + + .globl __tx_fiq_handler + .globl __tx_fiq_processing_return +__tx_fiq_handler: + /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save + + .type __tx_fiq_handler,$function + .size __tx_fiq_handler,.-__tx_fiq_handler + +__tx_fiq_processing_return: + + /* At this point execution is still in the FIQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. */ + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 1 # Build interrupt code + BL _tx_el_interrupt # Call interrupt event logging +#endif + + /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start + from FIQ mode with interrupts disabled. This routine switches to the + system mode and returns with FIQ interrupts enabled. + + NOTE: It is very important to ensure all FIQ interrupts are cleared + prior to enabling nested FIQ interrupts. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_start +#endif + + /* Application FIQ handlers can be called here! */ + + /* If interrupt nesting was started earlier, the end of interrupt nesting + service must be called before returning to _tx_thread_fiq_context_restore. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_end +#endif + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 1 # Build interrupt code + BL _tx_el_interrupt_end # Call interrupt event logging +#endif + + /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + .type __tx_fiq_processing_return,$function + .size __tx_fiq_processing_return,.-__tx_fiq_processing_return + +#else + .globl __tx_fiq_handler +__tx_fiq_handler: + B __tx_fiq_handler # FIQ interrupt handler + + .type __tx_fiq_handler,$function + .size __tx_fiq_handler,.-__tx_fiq_handler +#endif + + /* Reference build options and version ID to ensure they come in. */ + +BUILD_OPTIONS: + .data.w _tx_build_options +VERSION_ID: + .data.w _tx_version_id diff --git a/ports/cortex_r5/green/example_build/txe.gpj b/ports/cortex_r5/green/example_build/txe.gpj new file mode 100644 index 00000000..662bcd16 --- /dev/null +++ b/ports/cortex_r5/green/example_build/txe.gpj @@ -0,0 +1,284 @@ +#!gbuild +[Library] + -DTX_ENABLE_EVENT_LOGGING + -I../../../../common/inc + -I../../../../ports_common_green/inc + -I../inc +..\..\..\..\common\inc\tx_api.h +..\..\..\..\common\inc\tx_block_pool.h +..\..\..\..\common\inc\tx_byte_pool.h +..\..\..\..\common\inc\tx_event_flags.h +..\..\..\..\common\inc\tx_initialize.h +..\..\..\..\common\inc\tx_mutex.h +..\..\..\..\common\inc\tx_queue.h +..\..\..\..\common\inc\tx_semaphore.h +..\..\..\..\common\inc\tx_thread.h +..\..\..\..\common\inc\tx_timer.h +..\..\..\..\common\inc\tx_trace.h +..\..\..\..\common\inc\tx_user_sample.h +..\inc\tx_port.h +..\..\..\..\ports_common_green\inc\tx_el.h +..\..\..\..\ports_common_green\inc\tx_ghs.h +..\src\tx_thread_context_restore.arm +..\src\tx_thread_context_save.arm +..\src\tx_thread_fiq_context_restore.arm +..\src\tx_thread_fiq_context_save.arm +..\src\tx_thread_fiq_nesting_end.arm +..\src\tx_thread_fiq_nesting_start.arm +..\src\tx_thread_interrupt_control.arm +..\src\tx_thread_interrupt_disable.arm +..\src\tx_thread_interrupt_restore.arm +..\src\tx_thread_irq_nesting_end.arm +..\src\tx_thread_irq_nesting_start.arm +..\src\tx_thread_schedule.arm +..\src\tx_thread_stack_build.arm +..\src\tx_thread_system_return.arm +..\src\tx_thread_vectored_context_save.arm +..\src\tx_timer_interrupt.arm +..\..\..\..\common\src\tx_block_allocate.c +..\..\..\..\common\src\tx_block_pool_cleanup.c +..\..\..\..\common\src\tx_block_pool_create.c +..\..\..\..\common\src\tx_block_pool_delete.c +..\..\..\..\common\src\tx_block_pool_info_get.c +..\..\..\..\common\src\tx_block_pool_initialize.c +..\..\..\..\common\src\tx_block_pool_performance_info_get.c +..\..\..\..\common\src\tx_block_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_block_pool_prioritize.c +..\..\..\..\common\src\tx_block_release.c +..\..\..\..\common\src\tx_byte_allocate.c +..\..\..\..\common\src\tx_byte_pool_cleanup.c +..\..\..\..\common\src\tx_byte_pool_create.c +..\..\..\..\common\src\tx_byte_pool_delete.c +..\..\..\..\common\src\tx_byte_pool_info_get.c +..\..\..\..\common\src\tx_byte_pool_initialize.c +..\..\..\..\common\src\tx_byte_pool_performance_info_get.c +..\..\..\..\common\src\tx_byte_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_byte_pool_prioritize.c +..\..\..\..\common\src\tx_byte_pool_search.c +..\..\..\..\common\src\tx_byte_release.c +..\..\..\..\common\src\tx_event_flags_cleanup.c +..\..\..\..\common\src\tx_event_flags_create.c +..\..\..\..\common\src\tx_event_flags_delete.c +..\..\..\..\common\src\tx_event_flags_get.c +..\..\..\..\common\src\tx_event_flags_info_get.c +..\..\..\..\common\src\tx_event_flags_initialize.c +..\..\..\..\common\src\tx_event_flags_performance_info_get.c +..\..\..\..\common\src\tx_event_flags_performance_system_info_get.c +..\..\..\..\common\src\tx_event_flags_set.c +..\..\..\..\common\src\tx_event_flags_set_notify.c +..\..\..\..\common\src\tx_initialize_high_level.c +..\..\..\..\common\src\tx_initialize_kernel_enter.c +..\..\..\..\common\src\tx_initialize_kernel_setup.c +..\..\..\..\common\src\tx_mutex_cleanup.c +..\..\..\..\common\src\tx_mutex_create.c +..\..\..\..\common\src\tx_mutex_delete.c +..\..\..\..\common\src\tx_mutex_get.c +..\..\..\..\common\src\tx_mutex_info_get.c +..\..\..\..\common\src\tx_mutex_initialize.c +..\..\..\..\common\src\tx_mutex_performance_info_get.c +..\..\..\..\common\src\tx_mutex_performance_system_info_get.c +..\..\..\..\common\src\tx_mutex_prioritize.c +..\..\..\..\common\src\tx_mutex_priority_change.c +..\..\..\..\common\src\tx_mutex_put.c +..\..\..\..\common\src\tx_queue_cleanup.c +..\..\..\..\common\src\tx_queue_create.c +..\..\..\..\common\src\tx_queue_delete.c +..\..\..\..\common\src\tx_queue_flush.c +..\..\..\..\common\src\tx_queue_front_send.c +..\..\..\..\common\src\tx_queue_info_get.c +..\..\..\..\common\src\tx_queue_initialize.c +..\..\..\..\common\src\tx_queue_performance_info_get.c +..\..\..\..\common\src\tx_queue_performance_system_info_get.c +..\..\..\..\common\src\tx_queue_prioritize.c +..\..\..\..\common\src\tx_queue_receive.c +..\..\..\..\common\src\tx_queue_send.c +..\..\..\..\common\src\tx_queue_send_notify.c +..\..\..\..\common\src\tx_semaphore_ceiling_put.c +..\..\..\..\common\src\tx_semaphore_cleanup.c +..\..\..\..\common\src\tx_semaphore_create.c +..\..\..\..\common\src\tx_semaphore_delete.c +..\..\..\..\common\src\tx_semaphore_get.c +..\..\..\..\common\src\tx_semaphore_info_get.c +..\..\..\..\common\src\tx_semaphore_initialize.c +..\..\..\..\common\src\tx_semaphore_performance_info_get.c +..\..\..\..\common\src\tx_semaphore_performance_system_info_get.c +..\..\..\..\common\src\tx_semaphore_prioritize.c +..\..\..\..\common\src\tx_semaphore_put.c +..\..\..\..\common\src\tx_semaphore_put_notify.c +..\..\..\..\common\src\tx_thread_create.c +..\..\..\..\common\src\tx_thread_delete.c +..\..\..\..\common\src\tx_thread_entry_exit_notify.c +..\..\..\..\common\src\tx_thread_identify.c +..\..\..\..\common\src\tx_thread_info_get.c +..\..\..\..\common\src\tx_thread_initialize.c +..\..\..\..\common\src\tx_thread_performance_info_get.c +..\..\..\..\common\src\tx_thread_performance_system_info_get.c +..\..\..\..\common\src\tx_thread_preemption_change.c +..\..\..\..\common\src\tx_thread_priority_change.c +..\..\..\..\common\src\tx_thread_relinquish.c +..\..\..\..\common\src\tx_thread_reset.c +..\..\..\..\common\src\tx_thread_resume.c +..\..\..\..\common\src\tx_thread_shell_entry.c +..\..\..\..\common\src\tx_thread_sleep.c +..\..\..\..\common\src\tx_thread_stack_analyze.c +..\..\..\..\common\src\tx_thread_stack_error_handler.c +..\..\..\..\common\src\tx_thread_stack_error_notify.c +..\..\..\..\common\src\tx_thread_suspend.c +..\..\..\..\common\src\tx_thread_system_preempt_check.c +..\..\..\..\common\src\tx_thread_system_resume.c +..\..\..\..\common\src\tx_thread_system_suspend.c +..\..\..\..\common\src\tx_thread_terminate.c +..\..\..\..\common\src\tx_thread_time_slice.c +..\..\..\..\common\src\tx_thread_time_slice_change.c +..\..\..\..\common\src\tx_thread_timeout.c +..\..\..\..\common\src\tx_thread_wait_abort.c +..\..\..\..\common\src\tx_time_get.c +..\..\..\..\common\src\tx_time_set.c +..\..\..\..\common\src\tx_timer_activate.c +..\..\..\..\common\src\tx_timer_change.c +..\..\..\..\common\src\tx_timer_create.c +..\..\..\..\common\src\tx_timer_deactivate.c +..\..\..\..\common\src\tx_timer_delete.c +..\..\..\..\common\src\tx_timer_expiration_process.c +..\..\..\..\common\src\tx_timer_info_get.c +..\..\..\..\common\src\tx_timer_initialize.c +..\..\..\..\common\src\tx_timer_performance_info_get.c +..\..\..\..\common\src\tx_timer_performance_system_info_get.c +..\..\..\..\common\src\tx_timer_system_activate.c +..\..\..\..\common\src\tx_timer_system_deactivate.c +..\..\..\..\common\src\tx_timer_thread_entry.c +..\..\..\..\common\src\tx_trace_buffer_full_notify.c +..\..\..\..\common\src\tx_trace_disable.c +..\..\..\..\common\src\tx_trace_enable.c +..\..\..\..\common\src\tx_trace_event_filter.c +..\..\..\..\common\src\tx_trace_event_unfilter.c +..\..\..\..\common\src\tx_trace_initialize.c +..\..\..\..\common\src\tx_trace_interrupt_control.c +..\..\..\..\common\src\tx_trace_isr_enter_insert.c +..\..\..\..\common\src\tx_trace_isr_exit_insert.c +..\..\..\..\common\src\tx_trace_object_register.c +..\..\..\..\common\src\tx_trace_object_unregister.c +..\..\..\..\common\src\tx_trace_user_event_insert.c +..\..\..\..\common\src\txe_block_allocate.c +..\..\..\..\common\src\txe_block_pool_create.c +..\..\..\..\common\src\txe_block_pool_delete.c +..\..\..\..\common\src\txe_block_pool_info_get.c +..\..\..\..\common\src\txe_block_pool_prioritize.c +..\..\..\..\common\src\txe_block_release.c +..\..\..\..\common\src\txe_byte_allocate.c +..\..\..\..\common\src\txe_byte_pool_create.c +..\..\..\..\common\src\txe_byte_pool_delete.c +..\..\..\..\common\src\txe_byte_pool_info_get.c +..\..\..\..\common\src\txe_byte_pool_prioritize.c +..\..\..\..\common\src\txe_byte_release.c +..\..\..\..\common\src\txe_event_flags_create.c +..\..\..\..\common\src\txe_event_flags_delete.c +..\..\..\..\common\src\txe_event_flags_get.c +..\..\..\..\common\src\txe_event_flags_info_get.c +..\..\..\..\common\src\txe_event_flags_set.c +..\..\..\..\common\src\txe_event_flags_set_notify.c +..\..\..\..\common\src\txe_mutex_create.c +..\..\..\..\common\src\txe_mutex_delete.c +..\..\..\..\common\src\txe_mutex_get.c +..\..\..\..\common\src\txe_mutex_info_get.c +..\..\..\..\common\src\txe_mutex_prioritize.c +..\..\..\..\common\src\txe_mutex_put.c +..\..\..\..\common\src\txe_queue_create.c +..\..\..\..\common\src\txe_queue_delete.c +..\..\..\..\common\src\txe_queue_flush.c +..\..\..\..\common\src\txe_queue_front_send.c +..\..\..\..\common\src\txe_queue_info_get.c +..\..\..\..\common\src\txe_queue_prioritize.c +..\..\..\..\common\src\txe_queue_receive.c +..\..\..\..\common\src\txe_queue_send.c +..\..\..\..\common\src\txe_queue_send_notify.c +..\..\..\..\common\src\txe_semaphore_ceiling_put.c +..\..\..\..\common\src\txe_semaphore_create.c +..\..\..\..\common\src\txe_semaphore_delete.c +..\..\..\..\common\src\txe_semaphore_get.c +..\..\..\..\common\src\txe_semaphore_info_get.c +..\..\..\..\common\src\txe_semaphore_prioritize.c +..\..\..\..\common\src\txe_semaphore_put.c +..\..\..\..\common\src\txe_semaphore_put_notify.c +..\..\..\..\common\src\txe_thread_create.c +..\..\..\..\common\src\txe_thread_delete.c +..\..\..\..\common\src\txe_thread_entry_exit_notify.c +..\..\..\..\common\src\txe_thread_info_get.c +..\..\..\..\common\src\txe_thread_preemption_change.c +..\..\..\..\common\src\txe_thread_priority_change.c +..\..\..\..\common\src\txe_thread_relinquish.c +..\..\..\..\common\src\txe_thread_reset.c +..\..\..\..\common\src\txe_thread_resume.c +..\..\..\..\common\src\txe_thread_suspend.c +..\..\..\..\common\src\txe_thread_terminate.c +..\..\..\..\common\src\txe_thread_time_slice_change.c +..\..\..\..\common\src\txe_thread_wait_abort.c +..\..\..\..\common\src\txe_timer_activate.c +..\..\..\..\common\src\txe_timer_change.c +..\..\..\..\common\src\txe_timer_create.c +..\..\..\..\common\src\txe_timer_deactivate.c +..\..\..\..\common\src\txe_timer_delete.c +..\..\..\..\common\src\txe_timer_info_get.c +..\..\..\..\ports_common_green\src\tx_el.c +..\..\..\..\ports_common_green\src\tx_ghs.c +..\..\..\..\ports_common_green\src\tx_ghse.c +..\..\..\..\ports_common_green\src\txr_block_allocate.c +..\..\..\..\ports_common_green\src\txr_block_pool_create.c +..\..\..\..\ports_common_green\src\txr_block_pool_delete.c +..\..\..\..\ports_common_green\src\txr_block_pool_info_get.c +..\..\..\..\ports_common_green\src\txr_block_pool_prioritize.c +..\..\..\..\ports_common_green\src\txr_block_release.c +..\..\..\..\ports_common_green\src\txr_byte_allocate.c +..\..\..\..\ports_common_green\src\txr_byte_pool_create.c +..\..\..\..\ports_common_green\src\txr_byte_pool_delete.c +..\..\..\..\ports_common_green\src\txr_byte_pool_info_get.c +..\..\..\..\ports_common_green\src\txr_byte_pool_prioritize.c +..\..\..\..\ports_common_green\src\txr_byte_release.c +..\..\..\..\ports_common_green\src\txr_event_flags_create.c +..\..\..\..\ports_common_green\src\txr_event_flags_delete.c +..\..\..\..\ports_common_green\src\txr_event_flags_get.c +..\..\..\..\ports_common_green\src\txr_event_flags_info_get.c +..\..\..\..\ports_common_green\src\txr_event_flags_set.c +..\..\..\..\ports_common_green\src\txr_event_flags_set_notify.c +..\..\..\..\ports_common_green\src\txr_ghs.c +..\..\..\..\ports_common_green\src\txr_mutex_create.c +..\..\..\..\ports_common_green\src\txr_mutex_delete.c +..\..\..\..\ports_common_green\src\txr_mutex_get.c +..\..\..\..\ports_common_green\src\txr_mutex_info_get.c +..\..\..\..\ports_common_green\src\txr_mutex_prioritize.c +..\..\..\..\ports_common_green\src\txr_mutex_put.c +..\..\..\..\ports_common_green\src\txr_queue_create.c +..\..\..\..\ports_common_green\src\txr_queue_delete.c +..\..\..\..\ports_common_green\src\txr_queue_flush.c +..\..\..\..\ports_common_green\src\txr_queue_front_send.c +..\..\..\..\ports_common_green\src\txr_queue_info_get.c +..\..\..\..\ports_common_green\src\txr_queue_prioritize.c +..\..\..\..\ports_common_green\src\txr_queue_receive.c +..\..\..\..\ports_common_green\src\txr_queue_send.c +..\..\..\..\ports_common_green\src\txr_queue_send_notify.c +..\..\..\..\ports_common_green\src\txr_semaphore_ceiling_put.c +..\..\..\..\ports_common_green\src\txr_semaphore_create.c +..\..\..\..\ports_common_green\src\txr_semaphore_delete.c +..\..\..\..\ports_common_green\src\txr_semaphore_get.c +..\..\..\..\ports_common_green\src\txr_semaphore_info_get.c +..\..\..\..\ports_common_green\src\txr_semaphore_prioritize.c +..\..\..\..\ports_common_green\src\txr_semaphore_put.c +..\..\..\..\ports_common_green\src\txr_semaphore_put_notify.c +..\..\..\..\ports_common_green\src\txr_thread_create.c +..\..\..\..\ports_common_green\src\txr_thread_delete.c +..\..\..\..\ports_common_green\src\txr_thread_entry_exit_notify.c +..\..\..\..\ports_common_green\src\txr_thread_info_get.c +..\..\..\..\ports_common_green\src\txr_thread_preemption_change.c +..\..\..\..\ports_common_green\src\txr_thread_priority_change.c +..\..\..\..\ports_common_green\src\txr_thread_reset.c +..\..\..\..\ports_common_green\src\txr_thread_resume.c +..\..\..\..\ports_common_green\src\txr_thread_suspend.c +..\..\..\..\ports_common_green\src\txr_thread_terminate.c +..\..\..\..\ports_common_green\src\txr_thread_time_slice_change.c +..\..\..\..\ports_common_green\src\txr_thread_wait_abort.c +..\..\..\..\ports_common_green\src\txr_timer_activate.c +..\..\..\..\ports_common_green\src\txr_timer_change.c +..\..\..\..\ports_common_green\src\txr_timer_create.c +..\..\..\..\ports_common_green\src\txr_timer_deactivate.c +..\..\..\..\ports_common_green\src\txr_timer_delete.c +..\..\..\..\ports_common_green\src\txr_timer_info_get.c diff --git a/ports/cortex_r5/green/inc/tx_port.h b/ports/cortex_r5/green/inc/tx_port.h new file mode 100644 index 00000000..c46ef3b8 --- /dev/null +++ b/ports/cortex_r5/green/inc/tx_port.h @@ -0,0 +1,402 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-R5/Green Hills */ +/* 6.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include +#include +#include "tx_ghs.h" + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define constants for Green Hills EventAnalyzer. */ + +/* Define the number of ticks per second. This informs the EventAnalyzer what the timestamps + represent. By default, this is set to 1,000,000 i.e., one tick every microsecond. */ + +#define TX_EL_TICKS_PER_SECOND 1000000 + +/* Define the method of how to get the upper and lower 32-bits of the time stamp. By default, simply + simulate the time-stamp source with a counter. */ + +#define read_tbu() _tx_el_time_base_upper +#define read_tbl() ++_tx_el_time_base_lower + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ + VOID *tx_thread_eh_globals; \ + int Errno; /* errno. */ \ + char *strtok_saved_pos; /* strtok() position. */ +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + +#if (__GHS_VERSION_NUMBER >= 500) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) \ + { \ + extern void __tx_cpp_exception_init(TX_THREAD *thread_ptr); \ + __tx_cpp_exception_init(thread_ptr); \ + } +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) \ + { \ + #pragma weak __cpp_exception_init \ + extern void __cpp_exception_init(void **); \ + static void (*const cpp_init_funcp)(void **) = __cpp_exception_init; \ + if (cpp_init_funcp) \ + __cpp_exception_init(&(thread_ptr -> tx_thread_eh_globals)); \ + } +#endif + +#if (__GHS_VERSION_NUMBER >= 500) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) \ + { \ + extern void __tx_cpp_exception_cleanup(TX_THREAD *thread_ptr); \ + __tx_cpp_exception_cleanup(thread_ptr); \ + } +#else +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) \ + { \ + #pragma weak __cpp_exception_cleanup \ + extern void __cpp_exception_cleanup(void **); \ + static void (*const cpp_cleanup_funcp)(void **) = \ + __cpp_exception_cleanup; \ + if (cpp_cleanup_funcp) \ + __cpp_exception_cleanup(&(thread_ptr -> tx_thread_eh_globals)); \ + } +#endif + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + b = __CLZ32(m); \ + b = 31 - b; + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#if defined(__THUMB) + +unsigned int _tx_thread_interrupt_disable(void); +void _tx_thread_interrupt_restore(unsigned int new_posture); + +#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); + +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; + +#if defined(__GHS_VERSION_NUMBER) && (__GHS_VERSION_NUMBER >= 350) + +/* Define ThreadX interrupt lockout and restore macros using + compiler built-in functions if using Green Hills ARM compiler + version 3.5 or later. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_DISABLE interrupt_save = __GETSR(); \ + __SETSR(interrupt_save | 0xC0); + +#define TX_RESTORE __SETSR(interrupt_save); +#else +#define TX_DISABLE interrupt_save = __GETSR(); \ + __SETSR(interrupt_save | 0x80); + +#define TX_RESTORE __SETSR(interrupt_save); +#endif + +#else + +/* Define ThreadX interrupt lockout and restore macros using + asm macros if using Green Hills ARM compiler earlier than + version 3.5. */ + +asm int disable_ints(void) +{ +% + MRS r0,CPSR +#ifdef TX_BEFORE_ARMV6 +#ifdef TX_ENABLE_FIQ_SUPPORT + ORR r1,r0,0xC0 +#else + ORR r1,r0,0x80 +#endif + MSR CPSR_c,r1 +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if +#else + CPSID i +#endif +#endif +%error +} + +asm void restore_ints(int a) +{ +%reg a + MSR CPSR_c,a +%mem a + LDR r0,a + MSR CPSR_c,r0 +%error +} + +#define TX_DISABLE interrupt_save = disable_ints(); + +#define TX_RESTORE restore_ints(interrupt_save); +#endif +#endif + + +/* Define VFP extension for the Cortex-R5. Each is assumed to be called in the context of the executing + thread. */ + +void tx_thread_vfp_enable(void); +void tx_thread_vfp_disable(void); + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R5/Green Hills Version 6.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + diff --git a/ports/cortex_r5/green/readme_threadx.txt b/ports/cortex_r5/green/readme_threadx.txt new file mode 100644 index 00000000..f2afb94d --- /dev/null +++ b/ports/cortex_r5/green/readme_threadx.txt @@ -0,0 +1,527 @@ + Microsoft's Azure RTOS ThreadX for Cortex-R5 + + Using the Green Hills Software Tools + +1. Open the ThreadX Project Workspace + +In order to build the ThreadX library and the ThreadX demonstration first load +the Azure RTOS Workspace azure_rtos_workspace.gpj, which is located inside the +"example_build" directory. + + +2. Building the ThreadX run-time Library + +Building the ThreadX library is easy; simply select the MULTI project file +tx.gpj and then select the build button. You should now observe the +compilation and assembly of the ThreadX library. This project build produces +the ThreadX library file tx.a. + + +3. Demonstration System + +The ThreadX demonstration is designed to execute under the MULTI environment +on the Green Hills Cortex-R5 simulator. The instructions that follow describe +how to get the ThreadX evaluation running under the MULTI Cortex-R5 simulation +environment. + +Building the demonstration is easy; simply select the MULTI project file +sample_threadx.gpj. At this point, select the "Project Build" button and observe +the compilation, assembly, and linkage of the ThreadX demonstration application. + +After the demonstration is built, invoke the MULTI ARM simulator by selecting +the simulator connection from within the sample_threadx.con connection file. +Once connected to the simulator, select the "Debug" button. You should now +observe the main function of sample_threadx.c. + +At this point, you should setup a simulated timer interrupt for ThreadX +by entering "timer 9999 irq" in the "target" window of the debugger. + +You are now ready to execute the ThreadX demonstration system. Select +breakpoints and data watches to observe the execution of the sample_threadx.c +application. + + +4. EventAnalyzer Demonstration + +To build a demonstration system that also logs events for the MULTI EventAnalyzer, +perform the same steps as the regular demo, except build the ThreadX library with +txe.gpj file and use the sample_threadx_el.gpj build file to build the demonstration. +The resulting image will log all system events, which can then be displayed by the +MULTI EventAnalyzer. + + +5. System Initialization + +The system entry point using the Green Hills tools is at the label _start. +This is defined within the crt0.arm file supplied by Green Hills. In addition, +this is where all static and global preset C variable initialization +processing is called from. + +After the Green Hills startup function returns, ThreadX initialization is +called. The main initialization function is _tx_initialize_low_level and +is located in the file tx_initialize_low_level.arm. This function is responsible +for setting up various system data structures, interrupt vectors, and the +periodic timer interrupt source of ThreadX. + +In addition, _tx_initialize_low_level determines where the first available +RAM memory address is located. This address is supplied to tx_application_define. + +By default, the first available RAM memory address is assumed to start at the +beginning of the ThreadX section .free_mem. If changes are made to the +sample_threadx.ld file, the .free_mem section should remain the last allocated +section in the main RAM area. The starting address of this section is passed +to tx_application_define. + + +6. User defines + +The following defines and their associated action are as follows: + + Define Meaning + + TX_ENABLE_IRQ_NESTING If defined, this brings in special IRQ + interrupt nesting logic into the ThreadX + library. This define should be applied + to the entire ThreadX library. + + TX_ENABLE_FIQ_NESTING If defined, this brings in special FIQ + interrupt nesting logic into the ThreadX + library. This define should be applied + to the entire ThreadX library and the + define TX_ENABLE_FIQ_SUPPORT should also + be defined. + + TX_ENABLE_FIQ_SUPPORT If defined, this brings in FIQ context + save and restore logic necessary for + applications to call ThreadX services from + FIQ interrupt handlers. This define + should be applied to the entire ThreadX + library. + + + TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, + this define causes basic ThreadX error + checking to be disabled. Please see + Chapter 4 in the "ThreadX User Guide" + for more details. + + TX_ENABLE_EVENT_LOGGING This define enables event logging for any + or all of the ThreadX source code. If this + option is used anywhere, the tx_initialize_high_level.c + file must be compiled with it as well, since this + is where the event log is initialized. + + TX_NO_EVENT_INFO This is a sub-option for event logging. + If this is enabled, only basic information + is saved in the log. + + TX_ENABLE_EVENT_FILTERS This is also a sub-option for event-logging. + If this is enabled, run-time filtering logic + is added to the event logging code. + + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By + default, this value is set to 32 priority levels. + + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found + in tx_port.h. + + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default + value is port-specific and is found in tx_port.h. + + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined + in tx_port.h. + + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. + By default, this option is not defined. + + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. + By default, this option is not defined. + + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is + not defined. + + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. + By default, this option is not defined. + + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. + By default, this option is not defined. + + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. + By default, this option is not defined. + + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size + and improves performance. + + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is + not defined. + + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is + not defined. + + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option + is not defined. + + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is + not defined. + + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is + not defined. + + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is + not defined. + + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is + not defined. + + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is + not defined. + + + +7. Register Usage and Stack Frames + +The Green Hills compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) +are scratch registers for each function. All other registers used by a C +function must be preserved by the function. ThreadX takes advantage of this +in situations where a context switch happens as a result of making a ThreadX +service call (which is itself a C function). In such cases, the saved +context of a thread is only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 CPSR CPSR + 0x08 r0 (a1) r4 (v1) + 0x0C r1 (a2) r5 (v2) + 0x10 r2 (a3) r6 (v3) + 0x14 r3 (a4) r7 (v4) + 0x18 r4 (v1) r8 (v5) + 0x1C r5 (v2) r9 (v6) + 0x20 r6 (v3) r10 (v7) + 0x24 r7 (v4) r11 (fp) + 0x28 r8 (v5) r14 (lr) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) + 0x3C r14 (lr) + 0x40 PC + + +8. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make ThreadX run faster, you can change the tx.gpj project +to disable debug information and enable the desired optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined before tx_api.h is included. + + +9. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-R5 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +9.1 Vector Area + +The Cortex-R5 vectors start at address zero. The demonstration system reset.arm +file contains the reset section (which contains all the ARM vectors) and is +typically loaded at address zero. On actual hardware platforms, this section +might have to be copied to address 0. + +9.2 IRQ ISRs + +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested +IRQ interrupts. The following sub-sections define the IRQ capabilities. + + +9.2.1 Standard IRQ ISRs + +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +is the default IRQ handler defined in tx_initialize_low_level.arm: + + + .globl __tx_irq_handler + .globl __tx_irq_processing_return +__tx_irq_handler: + + /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return: + + /* At this point execution is still in the IRQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. Note + that IRQ interrupts are still disabled upon return from the context + save function. */ + + /* Application ISR call(s) go here! */ + + /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +9.2.2 Vectored IRQ ISRs + +The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified +by the particular implementation. The following is an example IRQ handler defined in +tx_initialize_low_level.arm: + + .globl __tx_irq_example_handler +__tx_irq_example_handler: + + /* Call context save to save system context. */ + + STMDB sp!, {r0-r3} # Save some scratch registers + MRS r0, SPSR # Pickup saved SPSR + SUB lr, lr, #4 # Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} # Store other scratch registers + BL _tx_thread_vectored_context_save # Call the vectored IRQ context save + + /* At this point execution is still in the IRQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. Note + that IRQ interrupts are still disabled upon return from the context + save function. */ + + /* Application ISR call goes here! */ + + /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +9.2.3 Nested IRQ Support + +By default, nested IRQ interrupt support is not enabled. To enable nested +IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING +defined. With this defined, two new IRQ interrupt management services are +available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. +These function should be called between the IRQ context save and restore +calls. + +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +by switching from IRQ mode to SYS mode and enabling IRQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.arm. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables nesting +by disabling IRQ interrupts and switching back to IRQ mode in preparation for +the IRQ context restore service. + +The following is an example of enabling IRQ nested interrupts in the +typical IRQ handler: + + .globl __tx_irq_handler + .globl __tx_irq_processing_return +__tx_irq_handler: + + /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return: + + /* Enable nested IRQ interrupts. NOTE: Since this service returns + with IRQ interrupts enabled, all IRQ interrupt sources must be + cleared prior to calling this service. */ + BL _tx_thread_irq_nesting_start + + /* Application ISR call(s) go here! */ + + /* Disable nested IRQ interrupts. The mode is switched back to + IRQ mode and IRQ interrupts are disable upon return. */ + BL _tx_thread_irq_nesting_end + + /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +9.3 FIQ Interrupts + +By default, Cortex-R5 FIQ interrupts are left completely enabled by ThreadX. +Of course, this means that the application is fully responsible for +saving/restoring any registers used in the FIQ ISR processing. In addition, +no ThreadX service calls are allowed from the default FIQ ISRs. The default +FIQ interrupt shell is located in tx_initialize_low_level.arm. + +9.3.1 Managed FIQ Interrupts + +Full ThreadX management of FIQ interrupts is provided if the ThreadX sources +are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built +this way, the FIQ interrupt handlers are very similar to the IRQ interrupt +handlers defined previously. The following is default FIQ handler +defined in tx_initialize_low_level.arm: + + + .globl __tx_fiq_handler + .globl __tx_fiq_processing_return +__tx_fiq_handler: + + /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: + + /* At this point execution is still in the FIQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. */ + + /* Application FIQ handlers can be called here! */ + + /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +9.3.1.1 Nested FIQ Support + +By default, nested FIQ interrupt support is not enabled. To enable nested +FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING +defined. With this defined, two new FIQ interrupt management services are +available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. +These function should be called between the FIQ context save and restore +calls. + +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +by switching from FIQ mode to SYS mode and enabling FIQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.arm. When nested FIQ interrupts are no longer +required, calling the _tx_thread_fiq_nesting_end service disables nesting by +disabling FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +context restore service. + +The following is an example of enabling FIQ nested interrupts in the +typical FIQ handler: + + + .globl __tx_fiq_handler + .globl __tx_fiq_processing_return +__tx_fiq_handler: + + /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: + + /* At this point execution is still in the FIQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. */ + + /* Enable nested FIQ interrupts. NOTE: Since this service returns + with FIQ interrupts enabled, all FIQ interrupt sources must be + cleared prior to calling this service. */ + BL _tx_thread_fiq_nesting_start + + /* Application FIQ handlers can be called here! */ + + /* Disable nested FIQ interrupts. The mode is switched back to + FIQ mode and FIQ interrupts are disable upon return. */ + BL _tx_thread_fiq_nesting_end + + /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + + +10. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional. However, all other +ThreadX services are operational without a periodic timer source. + +To add the timer interrupt processing, simply make a call to +_tx_timer_interrupt in the IRQ processing. An example of this can be +found in the file tx_initialize_low_level.arm. + + +11. Thumb/Cortex-R5 Mixed Mode + +By default, ThreadX is setup for running in Cortex-R5 32-bit mode. This is +also true for the demonstration system. It is possible to build any +ThreadX file and/or the application in Thumb mode. The only exception +to this is the file tx_thread_shell_entry.c. This file must always be +built in 32-bit mode. + + +12. VFP Support + +By default, VFP support is disabled for each thread. If saving the context of the VFP registers +is needed, the following API call must be made from the context of the application thread - before +the VFP usage: + +void tx_thread_vfp_enable(void); + +After this API is called in the application, VFP registers will be saved/restored for this thread if it +is preempted via an interrupt. All other suspension of the this thread will not require the VFP registers +to be saved/restored. + +To disable VFP register context saving, simply call the following API: + +void tx_thread_vfp_disable(void); + + +13. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +05/19/2020 Initial ThreadX version of Cortex-R5/Green Hills port. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_r5/green/src/tx_thread_context_restore.arm b/ports/cortex_r5/green/src/tx_thread_context_restore.arm new file mode 100644 index 00000000..d15c2a41 --- /dev/null +++ b/ports/cortex_r5/green/src/tx_thread_context_restore.arm @@ -0,0 +1,258 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # Disable IRQ and FIQ interrupts +#else + DISABLE_INTS = 0x80 # Disable IRQ interrupts +#endif + SVC_MODE = (0x13 | DISABLE_INTS) # SVC mode + IRQ_MODE = (0x12 | DISABLE_INTS) # IRQ mode + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore Cortex-R5/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores the interrupt context if it is processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_restore(VOID) +{ */ + .globl _tx_thread_context_restore +_tx_thread_context_restore: + + /* Lockout interrupts. */ + +#ifdef TX_BEFORE_ARMV6 + MRS r3, CPSR # Pickup current CPSR + ORR r0, r3, DISABLE_INTS # Build interrupt disable value + MSR CPSR_c, r0 # Lockout interrupts +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if # Disable IRQ and FIQ interrupts +#else + CPSID i # Disable IRQ interrupts +#endif +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR exit function to indicate an ISR is complete. */ + + BL _tx_execution_isr_exit # Call the ISR exit function +#endif + + /* Determine if interrupts are nested. */ + /* if (--_tx_thread_system_state) + { */ + + LDR r3, =_tx_thread_system_state # Pickup address of system state var + LDR r2, [r3] # Pickup system state + SUB r2, r2, 1 # Decrement the counter + STR r2, [r3] # Store the counter + CMP r2, 0 # Was this the first interrupt? + BEQ __tx_thread_not_nested_restore # If so, not a nested restore + + /* Interrupts are nested. */ + + /* Just recover the saved registers and return to the point of + interrupt. */ + + LDMIA sp!, {r0, r10, r12, lr} # Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 # Put SPSR back + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOVS pc, lr # Return to point of interrupt + + /* } */ +__tx_thread_not_nested_restore: + + /* Determine if a thread was interrupted and no preemption is required. */ + /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) + || (_tx_thread_preempt_disable)) + { */ + + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup actual current thread pointer + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_idle_system_restore # Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable # Pickup preempt disable address + LDR r2, [r3] # Pickup actual preempt disable flag + CMP r2, 0 # Is it set? + BNE __tx_thread_no_preempt_restore # Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr # Pickup address of execute thread ptr + LDR r2, [r3] # Pickup actual execute thread pointer + CMP r0, r2 # Is the same thread highest priority? + BNE __tx_thread_preempt_restore # No, preemption needs to happen + + +__tx_thread_no_preempt_restore: + + /* Restore interrupted thread or ISR. */ + + /* Pickup the saved stack pointer. */ + /* tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; */ + + /* Recover the saved context and return to the point of interrupt. */ + + LDMIA sp!, {r0, r10, r12, lr} # Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 # Put SPSR back + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOVS pc, lr # Return to point of interrupt + + /* } + else + { */ +__tx_thread_preempt_restore: + + LDMIA sp!, {r3, r10, r12, lr} # Recover temporarily saved registers + MOV r1, lr # Save lr (point of interrupt) + MOV r2, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r2 # Enter SVC mode + STR r1, [sp, -4]! # Save point of interrupt + STMDB sp!, {r4-r12, lr} # Save upper half of registers + MOV r4, r3 # Save SPSR in r4 + MOV r2, IRQ_MODE # Build IRQ mode CPSR + MSR CPSR_c, r2 # Re-enter IRQ mode + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOV r5, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r5 # Enter SVC mode + STMDB sp!, {r0-r3} # Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup current thread pointer + +#ifdef __VFP__ + LDR r2, [r0, 144] # Pickup the VFP enabled flag + CMP r2, 0 # Is the VFP enabled? + BEQ _tx_skip_irq_vfp_save # No, skip VFP IRQ save + VMRS r2, FPSCR # Pickup the FPSCR + STR r2, [sp, -4]! # Save FPSCR + VSTMDB sp!, {D0-D15} # Save D0-D15 +_tx_skip_irq_vfp_save: +#endif + + MOV r3, 1 # Build interrupt stack type + STMDB sp!, {r3, r4} # Save interrupt stack type and SPSR + STR sp, [r0, 8] # Save stack pointer in thread control + /* # block */ + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r4, r0 # Save r0 + MOV r5, r1 # Save r1 + BL _tx_el_thread_preempted # Call thread preempted routine + MOV r0, r4 # Restore r0 + MOV r1, r5 # Restore r1 +#endif + + /* Save the remaining time-slice and disable it. */ + /* if (_tx_timer_time_slice) + { */ + + LDR r3, =_tx_timer_time_slice # Pickup time-slice variable address + LDR r2, [r3] # Pickup time-slice + CMP r2, 0 # Is it active? + BEQ __tx_thread_dont_save_ts # No, don't save it + + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + STR r2, [r0, 24] # Save thread's time-slice + MOV r2, 0 # Clear value + STR r2, [r3] # Disable global time-slice flag + + /* } */ +__tx_thread_dont_save_ts: + + + /* Clear the current task pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + MOV r0, 0 # NULL value + STR r0, [r1] # Clear current thread pointer + + /* Return to the scheduler. */ + /* _tx_thread_schedule(); */ + + B _tx_thread_schedule # Return to scheduler + /* } */ + +__tx_thread_idle_system_restore: + + /* Just return back to the scheduler! */ + + + MOV r3, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r3 # Lockout interrupts + B _tx_thread_schedule # Return to scheduler + + .type _tx_thread_context_restore,$function + .size _tx_thread_context_restore,.-_tx_thread_context_restore + +/* } */ + diff --git a/ports/cortex_r5/green/src/tx_thread_context_save.arm b/ports/cortex_r5/green/src/tx_thread_context_save.arm new file mode 100644 index 00000000..ef250e66 --- /dev/null +++ b/ports/cortex_r5/green/src/tx_thread_context_save.arm @@ -0,0 +1,207 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # IRQ & FIQ interrupts disabled +#else + DISABLE_INTS = 0x80 # IRQ interrupts disabled +#endif + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save Cortex-R5/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_save(VOID) +{ */ + .globl _tx_thread_context_save +_tx_thread_context_save: + + /* Upon entry to this routine, it is assumed that IRQ interrupts are locked + out, we are in IRQ mode, and all registers are intact. */ + + /* Check for a nested interrupt condition. */ + /* if (_tx_thread_system_state++) + { */ + + STMDB sp!, {r0-r3} # Save some working registers + +#ifdef TX_ENABLE_FIQ_SUPPORT +#ifdef TX_BEFORE_ARMV6 + MRS r0, CPSR # Pickup the CPSR + ORR r0, r0, DISABLE_INTS # Build disable interrupt CPSR + MSR CPSR_c, r0 # Disable interrupts +#else + CPSID if # Disable FIQ interrupts +#endif +#endif + + LDR r3, =_tx_thread_system_state # Pickup address of system state var + LDR r2, [r3] # Pickup system state + CMP r2, 0 # Is this the first interrupt? + BEQ __tx_thread_not_nested_save # Yes, not a nested context save + + /* Nested interrupt condition. */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + + /* Save the rest of the scratch registers on the stack and return to the + calling ISR. */ + + MRS r0, SPSR # Pickup saved SPSR + SUB lr, lr, 4 # Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} # Store other registers + + /* Return to the ISR. */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + B __tx_irq_processing_return # Continue IRQ processing + +__tx_thread_not_nested_save: + /* } */ + + /* Otherwise, not nested, check to see if a thread was running. */ + /* else if (_tx_thread_current_ptr) + { */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup current thread pointer + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_idle_system_save # If so, interrupt occurred in + /* # scheduling loop - nothing needs saving! */ + + /* Save minimal context of interrupted thread. */ + + MRS r2, SPSR # Pickup saved SPSR + SUB lr, lr, 4 # Adjust point of interrupt + STMDB sp!, {r2, r10, r12, lr} # Store other registers + + /* Save the current stack pointer in the thread's control block. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ + + /* Switch to the system stack. */ + /* sp = _tx_thread_system_stack_ptr; */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + B __tx_irq_processing_return # Continue IRQ processing + + /* } + else + { */ + +__tx_thread_idle_system_save: + + /* Interrupt occurred in the scheduling loop. */ + + /* Not much to do here, just adjust the stack pointer, and return to IRQ + processing. */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + ADD sp, sp, 16 # Recover saved registers + B __tx_irq_processing_return # Continue IRQ processing + + .type _tx_thread_context_save,$function + .size _tx_thread_context_save,.-_tx_thread_context_save + + /* } +} */ + diff --git a/ports/cortex_r5/green/src/tx_thread_fiq_context_restore.arm b/ports/cortex_r5/green/src/tx_thread_fiq_context_restore.arm new file mode 100644 index 00000000..3cf756c8 --- /dev/null +++ b/ports/cortex_r5/green/src/tx_thread_fiq_context_restore.arm @@ -0,0 +1,263 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + SVC_MODE = 0xD3 # SVC mode + FIQ_MODE = 0xD1 # FIQ mode +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # Disable IRQ and FIQ interrupts +#else + DISABLE_INTS = 0x80 # Disable IRQ interrupts +#endif + MODE_MASK = 0x1F # Mode mask + IRQ_MODE_BITS = 0x12 # IRQ mode bits + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_context_restore Cortex-R5/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores the fiq interrupt context when processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* FIQ ISR Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_fiq_context_restore(VOID) +{ */ + .globl _tx_thread_fiq_context_restore +_tx_thread_fiq_context_restore: + + /* Lockout interrupts. */ + +#ifdef TX_BEFORE_ARMV6 + MRS r3, CPSR # Pickup current CPSR + ORR r0, r3, DISABLE_INTS # Build interrupt disable value + MSR CPSR_c, r0 # Lockout interrupts +#else + CPSID if # Disable IRQ and FIQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR exit function to indicate an ISR is complete. */ + + BL _tx_execution_isr_exit # Call the ISR exit function +#endif + + /* Determine if interrupts are nested. */ + /* if (--_tx_thread_system_state) + { */ + + LDR r3, =_tx_thread_system_state # Pickup address of system state var + LDR r2, [r3] # Pickup system state + SUB r2, r2, 1 # Decrement the counter + STR r2, [r3] # Store the counter + CMP r2, 0 # Was this the first interrupt? + BEQ __tx_thread_fiq_not_nested_restore # If so, not a nested restore + + /* Interrupts are nested. */ + + /* Just recover the saved registers and return to the point of + interrupt. */ + + LDMIA sp!, {r0, r10, r12, lr} # Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 # Put SPSR back + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOVS pc, lr # Return to point of interrupt + + /* } */ +__tx_thread_fiq_not_nested_restore: + + /* Determine if a thread was interrupted and no preemption is required. */ + /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) + || (_tx_thread_preempt_disable)) + { */ + + LDR r1, [sp] # Pickup the saved SPSR + MOV r2, MODE_MASK # Build mask to isolate the interrupted mode + AND r1, r1, r2 # Isolate mode bits + CMP r1, IRQ_MODE_BITS # Was an interrupt taken in IRQ mode before we + /* # got to context save? */ + BEQ __tx_thread_fiq_no_preempt_restore # Yes, just go back to point of interrupt + + + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup actual current thread pointer + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_fiq_idle_system_restore # Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable # Pickup preempt disable address + LDR r2, [r3] # Pickup actual preempt disable flag + CMP r2, 0 # Is it set? + BNE __tx_thread_fiq_no_preempt_restore # Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr # Pickup address of execute thread ptr + LDR r2, [r3] # Pickup actual execute thread pointer + CMP r0, r2 # Is the same thread highest priority? + BNE __tx_thread_fiq_preempt_restore # No, preemption needs to happen + + +__tx_thread_fiq_no_preempt_restore: + + /* Restore interrupted thread or ISR. */ + + /* Pickup the saved stack pointer. */ + /* tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; */ + + /* Recover the saved context and return to the point of interrupt. */ + + LDMIA sp!, {r0, lr} # Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 # Put SPSR back + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOVS pc, lr # Return to point of interrupt + + /* } + else + { */ +__tx_thread_fiq_preempt_restore: + + LDMIA sp!, {r3, lr} # Recover temporarily saved registers + MOV r1, lr # Save lr (point of interrupt) + MOV r2, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r2 # Enter SVC mode + STR r1, [sp, -4]! # Save point of interrupt + STMDB sp!, {r4-r12, lr} # Save upper half of registers + MOV r4, r3 # Save SPSR in r4 + MOV r2, FIQ_MODE # Build FIQ mode CPSR + MSR CPSR_c, r2 # Re-enter FIQ mode + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOV r5, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r5 # Enter SVC mode + STMDB sp!, {r0-r3} # Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup current thread pointer + +#ifdef __VFP__ + LDR r2, [r0, 144] # Pickup the VFP enabled flag + CMP r2, 0 # Is the VFP enabled? + BEQ _tx_skip_fiq_vfp_save # No, skip VFP IRQ save + VMRS r2, FPSCR # Pickup the FPSCR + STR r2, [sp, -4]! # Save FPSCR + VSTMDB sp!, {D0-D15} # Save D0-D15 +_tx_skip_fiq_vfp_save: +#endif + + MOV r3, 1 # Build interrupt stack type + STMDB sp!, {r3, r4} # Save interrupt stack type and SPSR + STR sp, [r0, 8] # Save stack pointer in thread control + /* # block */ + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r4, r0 # Save r0 + MOV r5, r1 # Save r1 + BL _tx_el_thread_preempted # Call thread preempted routine + MOV r0, r4 # Restore r0 + MOV r1, r5 # Restore r1 +#endif + + /* Save the remaining time-slice and disable it. */ + /* if (_tx_timer_time_slice) + { */ + + LDR r3, =_tx_timer_time_slice # Pickup time-slice variable address + LDR r2, [r3] # Pickup time-slice + CMP r2, 0 # Is it active? + BEQ __tx_thread_fiq_dont_save_ts # No, don't save it + + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + STR r2, [r0, 24] # Save thread's time-slice + MOV r2, 0 # Clear value + STR r2, [r3] # Disable global time-slice flag + + /* } */ +__tx_thread_fiq_dont_save_ts: + + + /* Clear the current task pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + MOV r0, 0 # NULL value + STR r0, [r1] # Clear current thread pointer + + /* Return to the scheduler. */ + /* _tx_thread_schedule(); */ + + B _tx_thread_schedule # Return to scheduler + /* } */ + +__tx_thread_fiq_idle_system_restore: + + /* Just return back to the scheduler! */ + + ADD sp, sp, 24 # Recover FIQ stack space + MOV r3, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r3 # Lockout interrupts + B _tx_thread_schedule # Return to scheduler + + .type _tx_thread_fiq_context_restore,$function + .size _tx_thread_fiq_context_restore,.-_tx_thread_fiq_context_restore + +/* } */ + diff --git a/ports/cortex_r5/green/src/tx_thread_fiq_context_save.arm b/ports/cortex_r5/green/src/tx_thread_fiq_context_save.arm new file mode 100644 index 00000000..a8b277d4 --- /dev/null +++ b/ports/cortex_r5/green/src/tx_thread_fiq_context_save.arm @@ -0,0 +1,197 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_context_save Cortex-R5/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_fiq_context_save(VOID) +{ */ + .globl _tx_thread_fiq_context_save +_tx_thread_fiq_context_save: + + /* Upon entry to this routine, it is assumed that IRQ interrupts are locked + out, we are in IRQ mode, and all registers are intact. */ + + /* Check for a nested interrupt condition. */ + /* if (_tx_thread_system_state++) + { */ + + STMDB sp!, {r0-r3} # Save some working registers + LDR r3, =_tx_thread_system_state # Pickup address of system state var + LDR r2, [r3] # Pickup system state + CMP r2, 0 # Is this the first interrupt? + BEQ __tx_thread_fiq_not_nested_save # Yes, not a nested context save + + /* Nested interrupt condition. */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + + /* Save the rest of the scratch registers on the stack and return to the + calling ISR. */ + + MRS r0, SPSR # Pickup saved SPSR + SUB lr, lr, 4 # Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} # Store other registers + + /* Return to the ISR. */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + B __tx_fiq_processing_return # Continue FIQ processing + +__tx_thread_fiq_not_nested_save: + /* } */ + + /* Otherwise, not nested, check to see if a thread was running. */ + /* else if (_tx_thread_current_ptr) + { */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup current thread pointer + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_fiq_idle_system_save # If so, interrupt occurred in + /* # scheduling loop - nothing needs saving! */ + + /* Save minimal context of interrupted thread. */ + + MRS r2, SPSR # Pickup saved SPSR + SUB lr, lr, 4 # Adjust point of interrupt + STMDB sp!, {r2, lr} # Store other registers, Note that we don't + /* # need to save sl and ip since FIQ has + # copies of these registers. Nested + # interrupt processing does need to save + # these registers. */ + + /* Save the current stack pointer in the thread's control block. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ + + /* Switch to the system stack. */ + /* sp = _tx_thread_system_stack_ptr; */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + B __tx_fiq_processing_return # Continue FIQ processing + + /* } + else + { */ + +__tx_thread_fiq_idle_system_save: + + /* Interrupt occurred in the scheduling loop. */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + /* Not much to do here, save the current SPSR and LR for possible + use in IRQ interrupted in idle system conditions, and return to + FIQ interrupt processing. */ + + MRS r0, SPSR # Pickup saved SPSR + SUB lr, lr, 4 # Adjust point of interrupt + STMDB sp!, {r0, lr} # Store other registers that will get used + /* # or stripped off the stack in context + # restore */ + B __tx_fiq_processing_return # Continue FIQ processing + + .type _tx_thread_fiq_context_save,$function + .size _tx_thread_fiq_context_save,.-_tx_thread_fiq_context_save + + /* } +} */ + diff --git a/ports/cortex_r5/green/src/tx_thread_fiq_nesting_end.arm b/ports/cortex_r5/green/src/tx_thread_fiq_nesting_end.arm new file mode 100644 index 00000000..e87f701b --- /dev/null +++ b/ports/cortex_r5/green/src/tx_thread_fiq_nesting_end.arm @@ -0,0 +1,109 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # Disable IRQ and FIQ interrupts +#else + DISABLE_INTS = 0x80 # Disable IRQ interrupts +#endif + MODE_MASK = 0x1F # Mode mask + FIQ_MODE_BITS = 0x11 # FIQ mode bits + SVC_MODE_BITS = 0x13 # SVC mode value */ + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_nesting_end Cortex-R5/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from FIQ mode after */ +/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +/* processing from system mode back to FIQ mode prior to the ISR */ +/* calling _tx_thread_fiq_context_restore. Note that this function */ +/* assumes the system stack pointer is in the same position after */ +/* nesting start function was called. */ +/* */ +/* This function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.arm). */ +/* */ +/* This function returns with FIQ interrupts disabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_fiq_nesting_end(VOID) +{ */ + .globl _tx_thread_fiq_nesting_end +_tx_thread_fiq_nesting_end: + MOV r3,lr # Save ISR return address + MRS r0, CPSR # Pickup the CPSR + ORR r0, r0, DISABLE_INTS # Build disable interrupt value + MSR CPSR_c, r0 # Disable interrupts + LDR lr, [sp] # Pickup saved lr + ADD sp, sp, 4 # Adjust stack pointer + BIC r0, r0, MODE_MASK # Clear mode bits + ORR r0, r0, FIQ_MODE_BITS # Build IRQ mode CPSR + MSR CPSR_c, r0 # Re-enter IRQ mode + MOV pc, r3 # Return to ISR + + .type _tx_thread_fiq_nesting_end,$function + .size _tx_thread_fiq_nesting_end,.-_tx_thread_fiq_nesting_end +/* } */ + diff --git a/ports/cortex_r5/green/src/tx_thread_fiq_nesting_start.arm b/ports/cortex_r5/green/src/tx_thread_fiq_nesting_start.arm new file mode 100644 index 00000000..c51476d8 --- /dev/null +++ b/ports/cortex_r5/green/src/tx_thread_fiq_nesting_start.arm @@ -0,0 +1,103 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + + FIQ_DISABLE = 0x40 # FIQ disable bit + MODE_MASK = 0x1F # Mode mask + SYS_MODE_BITS = 0x1F # System mode bits + + + .text + .align 4 + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_nesting_start Cortex-R5/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from FIQ mode after */ +/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +/* processing to the system mode so nested FIQ interrupt processing */ +/* is possible (system mode has its own "lr" register). Note that */ +/* this function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.arm). */ +/* */ +/* This function returns with FIQ interrupts enabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_fiq_nesting_start(VOID) +{ */ + .globl _tx_thread_fiq_nesting_start +_tx_thread_fiq_nesting_start: + MOV r3,lr # Save ISR return address + MRS r0, CPSR # Pickup the CPSR + BIC r0, r0, MODE_MASK # Clear the mode bits + ORR r0, r0, SYS_MODE_BITS # Build system mode CPSR + MSR CPSR_c, r0 # Enter system mode + STR lr, [sp, -4]! # Push the system mode lr on the system mode stack + BIC r0, r0, FIQ_DISABLE # Build enable FIQ CPSR + MSR CPSR_c, r0 # Enter system mode + MOV pc, r3 # Return to ISR + + .type _tx_thread_fiq_nesting_start,$function + .size _tx_thread_fiq_nesting_start,.-_tx_thread_fiq_nesting_start +/* } */ + diff --git a/ports/cortex_r5/green/src/tx_thread_interrupt_control.arm b/ports/cortex_r5/green/src/tx_thread_interrupt_control.arm new file mode 100644 index 00000000..27465d58 --- /dev/null +++ b/ports/cortex_r5/green/src/tx_thread_interrupt_control.arm @@ -0,0 +1,101 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" */ + + +#ifdef TX_ENABLE_FIQ_SUPPORT + INT_MASK = 0xC0 # Interrupt bit mask +#else + INT_MASK = 0x80 # Interrupt bit mask +#endif + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control Cortex-R5/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_control(UINT new_posture) +{ */ + .globl _tx_thread_interrupt_control +_tx_thread_interrupt_control: + + /* Pickup current interrupt lockout posture. */ + + MRS r3, CPSR # Pickup current CPSR + BIC r1, r3, INT_MASK # Clear interrupt lockout bits + ORR r1, r1, r0 # Or-in new interrupt lockout bits + + /* Apply the new interrupt posture. */ + + MSR CPSR_c, r1 # Setup new CPSR + AND r0, r3, INT_MASK # Return previous interrupt mask + RET # Return to caller + + .type _tx_thread_interrupt_control,$function + .size _tx_thread_interrupt_control,.-_tx_thread_interrupt_control +/* } */ + + + diff --git a/ports/cortex_r5/green/src/tx_thread_interrupt_disable.arm b/ports/cortex_r5/green/src/tx_thread_interrupt_disable.arm new file mode 100644 index 00000000..c62743b4 --- /dev/null +++ b/ports/cortex_r5/green/src/tx_thread_interrupt_disable.arm @@ -0,0 +1,105 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" */ + + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # IRQ & FIQ interrupts disabled +#else + DISABLE_INTS = 0x80 # IRQ interrupts disabled +#endif + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_disable Cortex-R5/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for disabling interrupts */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_disable(void) +{ */ + .globl _tx_thread_interrupt_disable +_tx_thread_interrupt_disable: + + /* Pickup current interrupt lockout posture. */ + + MRS r0, CPSR # Pickup current CPSR + + /* Mask interrupts. */ + +#ifdef TX_BEFORE_ARMV6 + ORR r1, r0, DISABLE_INTS # Mask interrupts + MSR CPSR_c, r1 # Setup new CPSR +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if # Disable IRQ and FIQ +#else + CPSID i # Disable IRQ +#endif +#endif + + RET # Return previous CPSR value + + .type _tx_thread_interrupt_disable,$function + .size _tx_thread_interrupt_disable,.-_tx_thread_interrupt_disable +/* } */ + diff --git a/ports/cortex_r5/green/src/tx_thread_interrupt_restore.arm b/ports/cortex_r5/green/src/tx_thread_interrupt_restore.arm new file mode 100644 index 00000000..76d38dc8 --- /dev/null +++ b/ports/cortex_r5/green/src/tx_thread_interrupt_restore.arm @@ -0,0 +1,85 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" */ + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_restore Cortex-R5/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for restoring interrupts to the state */ +/* returned by a previous _tx_thread_interrupt_disable call. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_interrupt_restore(UINT new_posture) +{ */ + .globl _tx_thread_interrupt_restore +_tx_thread_interrupt_restore: + + /* Apply the new interrupt posture. */ + + MSR CPSR_c, r0 # Setup new CPSR + RET + + .type _tx_thread_interrupt_restore,$function + .size _tx_thread_interrupt_restore,.-_tx_thread_interrupt_restore +/* } */ + diff --git a/ports/cortex_r5/green/src/tx_thread_irq_nesting_end.arm b/ports/cortex_r5/green/src/tx_thread_irq_nesting_end.arm new file mode 100644 index 00000000..49c3bee5 --- /dev/null +++ b/ports/cortex_r5/green/src/tx_thread_irq_nesting_end.arm @@ -0,0 +1,109 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # Disable IRQ and FIQ interrupts +#else + DISABLE_INTS = 0x80 # Disable IRQ interrupts +#endif + MODE_MASK = 0x1F # Mode mask + IRQ_MODE_BITS = 0x12 # IRQ mode bits + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_irq_nesting_end Cortex-R5/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from IRQ mode after */ +/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +/* processing from system mode back to IRQ mode prior to the ISR */ +/* calling _tx_thread_context_restore. Note that this function */ +/* assumes the system stack pointer is in the same position after */ +/* nesting start function was called. */ +/* */ +/* This function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.arm). */ +/* */ +/* This function returns with IRQ interrupts disabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_irq_nesting_end(VOID) +{ */ + .globl _tx_thread_irq_nesting_end +_tx_thread_irq_nesting_end: + MOV r3,lr # Save ISR return address + MRS r0, CPSR # Pickup the CPSR + ORR r0, r0, DISABLE_INTS # Build disable interrupt value + MSR CPSR_c, r0 # Disable interrupts + LDR lr, [sp] # Pickup saved lr + ADD sp, sp, 4 # Adjust stack pointer + BIC r0, r0, MODE_MASK # Clear mode bits + ORR r0, r0, IRQ_MODE_BITS # Build IRQ mode CPSR + MSR CPSR_c, r0 # Re-enter IRQ mode + MOV pc, r3 # Return to ISR + + .type _tx_thread_irq_nesting_end,$function + .size _tx_thread_irq_nesting_end,.-_tx_thread_irq_nesting_end + +/* } */ + diff --git a/ports/cortex_r5/green/src/tx_thread_irq_nesting_start.arm b/ports/cortex_r5/green/src/tx_thread_irq_nesting_start.arm new file mode 100644 index 00000000..487a3c60 --- /dev/null +++ b/ports/cortex_r5/green/src/tx_thread_irq_nesting_start.arm @@ -0,0 +1,102 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + + IRQ_DISABLE = 0x80 # IRQ disable bit + MODE_MASK = 0x1F # Mode mask + SYS_MODE_BITS = 0x1F # System mode bits + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_irq_nesting_start Cortex-R5/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from IRQ mode after */ +/* _tx_thread_context_save has been called and switches the IRQ */ +/* processing to the system mode so nested IRQ interrupt processing */ +/* is possible (system mode has its own "lr" register). Note that */ +/* this function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.arm). */ +/* */ +/* This function returns with IRQ interrupts enabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_irq_nesting_start(VOID) +{ */ + .globl _tx_thread_irq_nesting_start +_tx_thread_irq_nesting_start: + MOV r3,lr # Save ISR return address + MRS r0, CPSR # Pickup the CPSR + BIC r0, r0, MODE_MASK # Clear the mode bits + ORR r0, r0, SYS_MODE_BITS # Build system mode CPSR + MSR CPSR_c, r0 # Enter system mode + STR lr, [sp, -4]! # Push the system mode lr on the system mode stack + BIC r0, r0, IRQ_DISABLE # Build enable IRQ CPSR + MSR CPSR_c, r0 # Enter system mode + MOV pc, r3 # Return to ISR + + .type _tx_thread_irq_nesting_start,$function + .size _tx_thread_irq_nesting_start,.-_tx_thread_irq_nesting_start +/* } */ + diff --git a/ports/cortex_r5/green/src/tx_thread_schedule.arm b/ports/cortex_r5/green/src/tx_thread_schedule.arm new file mode 100644 index 00000000..3d7fe7ea --- /dev/null +++ b/ports/cortex_r5/green/src/tx_thread_schedule.arm @@ -0,0 +1,252 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + ENABLE_INTS = 0xC0 # IRQ & FIQ Interrupts enabled mask +#else + ENABLE_INTS = 0x80 # IRQ Interrupts enabled mask +#endif + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule Cortex-R5/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* _tx_thread_context_restore Restore thread's context */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_schedule(VOID) +{ */ + .globl _tx_thread_schedule +_tx_thread_schedule: + + /* Enable interrupts. */ + +#ifdef TX_BEFORE_ARMV6 + MRS r2, CPSR # Pickup CPSR + BIC r0, r2, ENABLE_INTS # Clear the disable bit(s) + MSR CPSR_c, r0 # Enable interrupts +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSIE if # Enable IRQ and FIQ interrupts +#else + CPSIE i # Enable IRQ interrupts +#endif +#endif + + /* Wait for a thread to execute. */ + /* do + { */ + LDR r1, =_tx_thread_execute_ptr # Address of thread execute ptr + +__tx_thread_schedule_loop: + + LDR r0, [r1] # Pickup next thread to execute + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_schedule_loop # If so, keep looking for a thread + + /* } + while(_tx_thread_execute_ptr == TX_NULL); */ + + /* Yes! We have a thread to execute. Lockout interrupts and + transfer control to it. */ + +#ifdef TX_BEFORE_ARMV6 + MSR CPSR_c, r2 # Disable interrupts +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if # Disable IRQ and FIQ interrupts +#else + CPSID i # Disable IRQ interrupts +#endif +#endif + + /* Setup the current thread pointer. */ + /* _tx_thread_current_ptr = _tx_thread_execute_ptr; */ + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV v1, r0 # Save temp register in non-volatile register + BL _tx_el_thread_running # Call event logging routine + MOV r0, v1 # Restore temp register +#endif + + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread + STR r0, [r1] # Setup current thread pointer + + /* Increment the run count for this thread. */ + /* _tx_thread_current_ptr -> tx_thread_run_count++; */ + + LDR r2, [r0, 4] # Pickup run counter + LDR r3, [r0, 24] # Pickup time-slice for this thread + ADD r2, r2, 1 # Increment thread run-counter + STR r2, [r0, 4] # Store the new run counter + + /* Setup time-slice, if present. */ + /* _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; */ + + LDR r2, =_tx_timer_time_slice # Pickup address of time slice + /* # variable */ + LDR sp, [r0, 8] # Switch stack pointers + STR r3, [r2] # Setup time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread entry function to indicate the thread is executing. */ + + MOV r5, r0 # Save r0 + BL _tx_execution_thread_enter # Call the thread execution enter function + MOV r0, r5 # Restore r0 +#endif + + /* Switch to the thread's stack. */ + /* sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; */ + + /* Determine if an interrupt frame or a synchronous task suspension frame + is present. */ + + LDMIA sp!, {r4, r5} # Pickup the stack type and saved CPSR + CMP r4, 0 # Check for synchronous context switch + BEQ _tx_solicited_return + MSR SPSR_cxsf, r5 # Setup SPSR for return +#ifdef __VFP__ + LDR r1, [r0, 144] # Pickup the VFP enabled flag + CMP r1, 0 # Is the VFP enabled? + BEQ _tx_skip_interrupt_vfp_restore # No, skip VFP interrupt restore + VLDMIA sp!, {D0-D15} # Recover D0-D15 + LDR r4, [sp], 4 # Pickup FPSCR + VMSR FPSCR, r4 # Restore FPSCR +_tx_skip_interrupt_vfp_restore: +#endif + LDMIA sp!, {r0-r12, lr, pc}^ # Return to point of thread interrupt + +_tx_solicited_return: +#ifdef __VFP__ + LDR r1, [r0, 144] # Pickup the VFP enabled flag + CMP r1, 0 # Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_restore # No, skip VFP solicited restore + VLDMIA sp!, {D8-D15} # Recover D8-D15 + LDR r4, [sp], 4 # Pickup FPSCR + VMSR FPSCR, r4 # Restore FPSCR +_tx_skip_solicited_vfp_restore: +#endif + MSR CPSR_cxsf, r5 # Recover CPSR + LDMIA sp!, {r4-r11, lr} # Return to thread synchronously + RET # Return to caller (Thumb safe) + + .type _tx_thread_schedule,$function + .size _tx_thread_schedule,.-_tx_thread_schedule + +#ifdef __VFP__ + .globl tx_thread_vfp_enable +tx_thread_vfp_enable: + MRS r2, CPSR # Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if # Disable IRQ and FIQ interrupts +#else + CPSID i # Disable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr # Build current thread pointer address + LDR r1, [r0] # Pickup current thread pointer + CMP r1, 0 # Check for NULL thread pointer + BEQ __tx_no_thread_to_enable # If NULL, skip VFP enable + MOV r0, 1 # Build enable value + STR r0, [r1, 144] # Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_enable: + MSR CPSR_cxsf, r2 # Recover CPSR + RET # Return to caller (Thumb safe) + + .type tx_thread_vfp_enable,$function + .size tx_thread_vfp_enable,.-tx_thread_vfp_enable + + + .globl tx_thread_vfp_disable +tx_thread_vfp_disable: + MRS r2, CPSR # Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if # Disable IRQ and FIQ interrupts +#else + CPSID i # Disable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr # Build current thread pointer address + LDR r1, [r0] # Pickup current thread pointer + CMP r1, 0 # Check for NULL thread pointer + BEQ __tx_no_thread_to_disable # If NULL, skip VFP disable + MOV r0, 0 # Build disable value + STR r0, [r1, 144] # Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_disable: + MSR CPSR_cxsf, r2 # Recover CPSR + RET # Return to caller (Thumb safe) + + .type tx_thread_vfp_disable,$function + .size tx_thread_vfp_disable,.-tx_thread_vfp_disable + +#endif + +/* } */ + + + diff --git a/ports/cortex_r5/green/src/tx_thread_stack_build.arm b/ports/cortex_r5/green/src/tx_thread_stack_build.arm new file mode 100644 index 00000000..1d4a22ea --- /dev/null +++ b/ports/cortex_r5/green/src/tx_thread_stack_build.arm @@ -0,0 +1,161 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" */ + + SVC_MODE = 0x13 # SVC mode +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSR_MASK = 0xDF # Mask initial CPSR, IRQ & FIQ ints enabled +#else + CPSR_MASK = 0x9F # Mask initial CPSR, IRQ ints enabled +#endif + + THUMB_BIT = 0x20 # Thumb-bit + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build Cortex-R5/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +{ */ + .globl _tx_thread_stack_build +_tx_thread_stack_build: + + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-R5 should look like the following after it is built: + + Stack Top: 1 Interrupt stack frame type + CPSR Initial value for CPSR + r0 (a1) Initial value for r0 + r1 (a2) Initial value for r1 + r2 (a3) Initial value for r2 + r3 (a4) Initial value for r3 + r4 (v1) Initial value for r4 + r5 (v2) Initial value for r5 + r6 (v3) Initial value for r6 + r7 (v4) Initial value for r7 + r8 (v5) Initial value for r8 + r9 (sb) Initial value for r9 + r10 (sl) Initial value for r10 + r11 (fp) Initial value for r11 + r12 (ip) Initial value for r12 + lr Initial value for lr + pc Initial value for pc + 0 For stack backtracing + + Stack Bottom: (higher memory address) */ + + LDR r2, [r0, 16] # Pickup end of stack area + BIC r2, r2, 7 # Ensure 8-byte alignment + SUB r2, r2, 76 # Allocate space for the stack frame + + /* Actually build the stack frame. */ + + MOV r3, 1 # Build interrupt stack type + STR r3, [r2] # Store stack type + MOV r3, 0 # Build initial register value + STR r3, [r2, 8] # Store initial r0 + STR r3, [r2, 12] # Store initial r1 + STR r3, [r2, 16] # Store initial r2 + STR r3, [r2, 20] # Store initial r3 + STR r3, [r2, 24] # Store initial r4 + STR r3, [r2, 28] # Store initial r5 + STR r3, [r2, 32] # Store initial r6 + STR r3, [r2, 36] # Store initial r7 + STR r3, [r2, 40] # Store initial r8 + STR r3, [r2, 44] # Store initial r9 + LDR r3, [r0, 12] # Pickup stack starting address + STR r3, [r2, 48] # Store initial r10 + MOV r3, 0 # Build initial register value + STR r3, [r2, 52] # Store initial r11 + STR r3, [r2, 56] # Store initial r12 + STR r3, [r2, 60] # Store initial lr + STR r1, [r2, 64] # Store initial pc + STR r3, [r2, 68] # 0 for back-trace + + MRS r3, CPSR # Pickup CPSR + BIC r3, r3, CPSR_MASK # Mask mode bits of CPSR + ORR r3, r3, SVC_MODE # Build CPSR, SVC mode, interrupts enabled + BIC r3, r3, #THUMB_BIT # Clear Thumb-bit by default + AND r1, r1, #1 # Determine if the entry function is in Thumb mode + CMP r1, 1 # Is the Thumb-bit set? + ORREQ r3, r3, #THUMB_BIT # Yes, set the Thumb-bit + STR r3, [r2, 4] # Store initial CPSR + + /* Setup stack pointer. */ + /* thread_ptr -> tx_thread_stack_ptr = r2; */ + + STR r2, [r0, 8] # Save stack pointer in thread's + /* # control block */ + RET # Return to caller + + .type _tx_thread_stack_build,$function + .size _tx_thread_stack_build,.-_tx_thread_stack_build +/* } */ + diff --git a/ports/cortex_r5/green/src/tx_thread_system_return.arm b/ports/cortex_r5/green/src/tx_thread_system_return.arm new file mode 100644 index 00000000..87e1377a --- /dev/null +++ b/ports/cortex_r5/green/src/tx_thread_system_return.arm @@ -0,0 +1,166 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # IRQ & FIQ interrupts disabled +#else + DISABLE_INTS = 0x80 # IRQ interrupts disabled +#endif + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return Cortex-R5/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the ThreadX system. Only a */ +/* minimal context is saved since the compiler assumes temp registers */ +/* are going to get slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_system_return(VOID) +{ */ + .globl _tx_thread_system_return +_tx_thread_system_return: + + /* Save minimal context on the stack. */ + + MOV r0, 0 # Build a solicited stack type + MRS r1, CPSR # Pickup the CPSR + STMDB sp!, {r4-r11, lr} # Save minimal context + + LDR r4, =_tx_thread_current_ptr # Pickup address of current ptr + LDR r5, [r4] # Pickup current thread pointer + +#ifdef __VFP__ + LDR r1, [r5, 144] # Pickup the VFP enabled flag + CMP r1, 0 # Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_save # No, skip VFP solicited save + VMRS r1, FPSCR # Pickup the FPSCR + STR r1, [sp, -4]! # Save FPSCR + VSTMDB sp!, {D8-D15} # Save D8-D15 +_tx_skip_solicited_vfp_save: +#endif + + MOV r0, #0 # Build a solicited stack type + MRS r1, CPSR # Pickup the CPSR + STMDB sp!, {r0-r1} # Save type and CPSR + + /* Lockout interrupts. */ + +#ifdef TX_BEFORE_ARMV6 + ORR r2, r1, DISABLE_INTS # Build disable interrupt CPSR + MSR CPSR_c, r2 # Disable interrupts +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if # Disable IRQ and FIQ interrupts +#else + CPSID i # Disable IRQ interrutps +#endif +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread exit function to indicate the thread is no longer executing. */ + + BL _tx_execution_thread_exit # Call the thread exit function +#endif + + MOV r3, r4 # Pickup address of current ptr + MOV r0, r5 # Pickup current thread pointer + LDR r2, =_tx_timer_time_slice # Pickup address of time slice + LDR r1, [r2] # Pickup current time slice + + /* Save current stack and switch to system stack. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; + sp = _tx_thread_system_stack_ptr; */ + + STR sp, [r0, 8] # Save thread stack pointer + + /* Determine if the time-slice is active. */ + /* if (_tx_timer_time_slice) + { */ + + MOV r4, 0 # Build clear value + CMP r1, 0 # Is a time-slice active? + BEQ __tx_thread_dont_save_ts # No, don't save the time-slice + + /* Save time-slice for the thread and clear the current time-slice. */ + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + STR r4, [r2, 0] # Clear time-slice + STR r1, [r0, 24] # Save current time-slice + + /* } */ +__tx_thread_dont_save_ts: + + /* Clear the current thread pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + STR r4, [r3] # Clear current thread pointer + B _tx_thread_schedule # Jump to scheduler! + + .type _tx_thread_system_return,$function + .size _tx_thread_system_return,.-_tx_thread_system_return +/* } */ + diff --git a/ports/cortex_r5/green/src/tx_thread_vectored_context_save.arm b/ports/cortex_r5/green/src/tx_thread_vectored_context_save.arm new file mode 100644 index 00000000..01a57231 --- /dev/null +++ b/ports/cortex_r5/green/src/tx_thread_vectored_context_save.arm @@ -0,0 +1,196 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # IRQ & FIQ interrupts disabled +#else + DISABLE_INTS = 0x80 # IRQ interrupts disabled +#endif + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_vectored_context_save Cortex-R5/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_vectored_context_save(VOID) +{ */ + .globl _tx_thread_vectored_context_save +_tx_thread_vectored_context_save: + + /* Upon entry to this routine, it is assumed that IRQ interrupts are locked + out, we are in IRQ mode, the minimal context is already saved, and the + lr register contains the return ISR address. */ + + /* Check for a nested interrupt condition. */ + /* if (_tx_thread_system_state++) + { */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#ifdef TX_BEFORE_ARMV6 + MRS r0, CPSR # Pickup the CPSR + ORR r0, r0, DISABLE_INTS # Build disable interrupt CPSR + MSR CPSR_c, r0 # Disable interrupts +#else + CPSID if # Disable IRQ and FIQ interrupts +#endif +#endif + LDR r3, =_tx_thread_system_state # Pickup address of system state var + LDR r2, [r3] # Pickup system state + CMP r2, 0 # Is this the first interrupt? + BEQ __tx_thread_not_nested_save # Yes, not a nested context save + + /* Nested interrupt condition. */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + + /* Note: Minimal context of interrupted thread is already saved. */ + + /* Return to the ISR. */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + MOV pc, lr # Return to caller + +__tx_thread_not_nested_save: + /* } */ + + /* Otherwise, not nested, check to see if a thread was running. */ + /* else if (_tx_thread_current_ptr) + { */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup current thread pointer + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_idle_system_save # If so, interrupt occurred in + /* # scheduling loop - nothing needs saving! */ + + /* Note: Minimal context of interrupted thread is already saved. */ + + /* Save the current stack pointer in the thread's control block. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ + + /* Switch to the system stack. */ + /* sp = _tx_thread_system_stack_ptr; */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + MOV pc, lr # Return to caller + + /* } + else + { */ + +__tx_thread_idle_system_save: + + /* Interrupt occurred in the scheduling loop. */ + + /* Not much to do here, just adjust the stack pointer, and return to IRQ + processing. */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + ADD sp, sp, 32 # Recover saved registers + MOV pc, lr # Return to caller + + .type _tx_thread_vectored_context_save,$function + .size _tx_thread_vectored_context_save,.-_tx_thread_vectored_context_save + + /* } +} */ + diff --git a/ports/cortex_r5/green/src/tx_timer_interrupt.arm b/ports/cortex_r5/green/src/tx_timer_interrupt.arm new file mode 100644 index 00000000..aaf7b9b2 --- /dev/null +++ b/ports/cortex_r5/green/src/tx_timer_interrupt.arm @@ -0,0 +1,241 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_timer.h" + #include "tx_thread.h" */ + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt Cortex-R5/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Process timer expiration */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_timer_interrupt(VOID) +{ */ + .globl _tx_timer_interrupt +_tx_timer_interrupt: + + /* Upon entry to this routine, it is assumed that context save has already + been called, and therefore the compiler scratch registers are available + for use. */ + + /* Increment the system clock. */ + /* _tx_timer_system_clock++; */ + + LDR r1, =_tx_timer_system_clock # Pickup address of system clock + LDR r0, [r1] # Pickup system clock + ADD r0, r0, 1 # Increment system clock + STR r0, [r1] # Store new system clock + + /* Test for time-slice expiration. */ + /* if (_tx_timer_time_slice) + { */ + + LDR r3, =_tx_timer_time_slice # Pickup address of time-slice + LDR r2, [r3] # Pickup time-slice + CMP r2, 0 # Is it non-active? + BEQ __tx_timer_no_time_slice # Yes, skip time-slice processing + + /* Decrement the time_slice. */ + /* _tx_timer_time_slice--; */ + + SUB r2, r2, 1 # Decrement the time-slice + STR r2, [r3] # Store new time-slice value + + /* Check for expiration. */ + /* if (__tx_timer_time_slice == 0) */ + + CMP r2, 0 # Has it expired? + BNE __tx_timer_no_time_slice # No, skip expiration processing + + /* Set the time-slice expired flag. */ + /* _tx_timer_expired_time_slice = TX_TRUE; */ + + LDR r3,=_tx_timer_expired_time_slice # Pickup address of expired flag + MOV r0, 1 # Build expired value + STR r0, [r3] # Set time-slice expiration flag + + /* } */ + +__tx_timer_no_time_slice: + + /* Test for timer expiration. */ + /* if (*_tx_timer_current_ptr) + { */ + + LDR r1, =_tx_timer_current_ptr # Pickup current timer pointer addr + LDR r0, [r1] # Pickup current timer + LDR r2, [r0] # Pickup timer list entry + CMP r2, 0 # Is there anything in the list? + BEQ __tx_timer_no_timer # No, just increment the timer + + /* Set expiration flag. */ + /* _tx_timer_expired = TX_TRUE; */ + + LDR r3, =_tx_timer_expired # Pickup expiration flag address + MOV r2, 1 # Build expired value + STR r2, [r3] # Set expired flag + B __tx_timer_done # Finished timer processing + + /* } + else + { */ +__tx_timer_no_timer: + + /* No timer expired, increment the timer pointer. */ + /* _tx_timer_current_ptr++; */ + + ADD r0, r0, 4 # Move to next timer + + /* Check for wrap-around. */ + /* if (_tx_timer_current_ptr == _tx_timer_list_end) */ + + LDR r3, =_tx_timer_list_end # Pickup addr of timer list end + LDR r2, [r3] # Pickup list end + CMP r0, r2 # Are we at list end? + BNE __tx_timer_skip_wrap # No, skip wrap-around logic + + /* Wrap to beginning of list. */ + /* _tx_timer_current_ptr = _tx_timer_list_start; */ + + LDR r3, =_tx_timer_list_start # Pickup addr of timer list start + LDR r0, [r3] # Set current pointer to list start + +__tx_timer_skip_wrap: + + STR r0, [r1] # Store new current timer pointer + /* } */ + +__tx_timer_done: + + + /* See if anything has expired. */ + /* if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) + { */ + + LDR r3, =_tx_timer_expired_time_slice # Pickup addr of expired flag + LDR r2, [r3] # Pickup time-slice expired flag + CMP r2, 0 # Did a time-slice expire? + BNE __tx_something_expired # If non-zero, time-slice expired + LDR r1, =_tx_timer_expired # Pickup addr of other expired flag + LDR r0, [r1] # Pickup timer expired flag + CMP r0, 0 # Did a timer expire? + BEQ __tx_timer_nothing_expired # No, nothing expired + +__tx_something_expired: + + + STMDB sp!, {r0, lr} # Save the lr register on the stack + /* # and save r0 just to keep 8-byte alignment */ + + /* Did a timer expire? */ + /* if (_tx_timer_expired) + { */ + + LDR r1, =_tx_timer_expired # Pickup addr of expired flag + LDR r0, [r1] # Pickup timer expired flag + CMP r0, 0 # Check for timer expiration + BEQ __tx_timer_dont_activate # If not set, skip timer activation + + /* Process the timer expiration. */ + /* _tx_timer_expiration_process(); */ + BL _tx_timer_expiration_process # Call the timer expiration handling routine + + /* } */ +__tx_timer_dont_activate: + + /* Did time slice expire? */ + /* if (_tx_timer_expired_time_slice) + { */ + + LDR r3, =_tx_timer_expired_time_slice # Pickup addr of time-slice expired + LDR r2, [r3] # Pickup the actual flag + CMP r2, 0 # See if the flag is set + BEQ __tx_timer_not_ts_expiration # No, skip time-slice processing + + /* Time slice interrupted thread. */ + /* _tx_thread_time_slice(); */ + + BL _tx_thread_time_slice # Call time-slice processing + + /* } */ +__tx_timer_not_ts_expiration: + + + LDMIA sp!, {r0, lr} # Recover lr register (r0 is just there for + /* # the 8-byte stack alignment */ + + /* } */ + +__tx_timer_nothing_expired: + + RET # Return to caller + + .type _tx_timer_interrupt,$function + .size _tx_timer_interrupt,.-_tx_timer_interrupt +/* } */ + diff --git a/ports/cortex_r5/iar/example_build/tx_initialize_low_level.s b/ports/cortex_r5/iar/example_build/tx_initialize_low_level.s index 6e5da9e4..0bb6f356 100644 --- a/ports/cortex_r5/iar/example_build/tx_initialize_low_level.s +++ b/ports/cortex_r5/iar/example_build/tx_initialize_low_level.s @@ -71,7 +71,7 @@ __tx_free_memory_start ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level Cortex-R5/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -104,7 +104,7 @@ __tx_free_memory_start ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports/cortex_r5/iar/inc/tx_port.h b/ports/cortex_r5/iar/inc/tx_port.h index 5c597d04..f2a990ed 100644 --- a/ports/cortex_r5/iar/inc/tx_port.h +++ b/ports/cortex_r5/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-R5/IAR */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -364,7 +364,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R5/IAR Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R5/IAR Version 6.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_r5/iar/readme_threadx.txt b/ports/cortex_r5/iar/readme_threadx.txt index 96f7a37f..e5bb364f 100644 --- a/ports/cortex_r5/iar/readme_threadx.txt +++ b/ports/cortex_r5/iar/readme_threadx.txt @@ -416,7 +416,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX version for Cortex-R5 using IAR's ARM tools. +09-30-2020 Initial ThreadX version for Cortex-R5 using IAR's ARM tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/cortex_r5/iar/src/tx_thread_context_restore.s b/ports/cortex_r5/iar/src/tx_thread_context_restore.s index 3d28fdb5..deb16b8e 100644 --- a/ports/cortex_r5/iar/src/tx_thread_context_restore.s +++ b/ports/cortex_r5/iar/src/tx_thread_context_restore.s @@ -53,7 +53,7 @@ THUMB_MASK DEFINE 0x20 ; Thumb bit mask ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore Cortex-R5/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -85,7 +85,7 @@ THUMB_MASK DEFINE 0x20 ; Thumb bit mask ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports/cortex_r5/iar/src/tx_thread_context_save.s b/ports/cortex_r5/iar/src/tx_thread_context_save.s index 97b1d3cf..c9079fd6 100644 --- a/ports/cortex_r5/iar/src/tx_thread_context_save.s +++ b/ports/cortex_r5/iar/src/tx_thread_context_save.s @@ -42,7 +42,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save Cortex-R5/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -73,7 +73,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) diff --git a/ports/cortex_r5/iar/src/tx_thread_interrupt_control.s b/ports/cortex_r5/iar/src/tx_thread_interrupt_control.s index ad3a6bae..873a096f 100644 --- a/ports/cortex_r5/iar/src/tx_thread_interrupt_control.s +++ b/ports/cortex_r5/iar/src/tx_thread_interrupt_control.s @@ -38,7 +38,7 @@ INT_MASK DEFINE 0x80 ; Interrupt bit mask ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control Cortex-R5/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -68,7 +68,7 @@ INT_MASK DEFINE 0x80 ; Interrupt bit mask ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/cortex_r5/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_r5/iar/src/tx_thread_interrupt_disable.s index b795d14f..0f5256ce 100644 --- a/ports/cortex_r5/iar/src/tx_thread_interrupt_disable.s +++ b/ports/cortex_r5/iar/src/tx_thread_interrupt_disable.s @@ -38,7 +38,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_disable Cortex-R5/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -67,7 +67,7 @@ DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(VOID) diff --git a/ports/cortex_r5/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_r5/iar/src/tx_thread_interrupt_restore.s index 9fc7b4e4..f484916f 100644 --- a/ports/cortex_r5/iar/src/tx_thread_interrupt_restore.s +++ b/ports/cortex_r5/iar/src/tx_thread_interrupt_restore.s @@ -34,7 +34,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-R5/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -64,7 +64,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;void _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports/cortex_r5/iar/src/tx_thread_irq_nesting_end.s b/ports/cortex_r5/iar/src/tx_thread_irq_nesting_end.s index e9bb5eee..114d35d4 100644 --- a/ports/cortex_r5/iar/src/tx_thread_irq_nesting_end.s +++ b/ports/cortex_r5/iar/src/tx_thread_irq_nesting_end.s @@ -39,7 +39,7 @@ IRQ_MODE DEFINE 0x12 ; IRQ mode ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_irq_nesting_end Cortex-R5/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -78,7 +78,7 @@ IRQ_MODE DEFINE 0x12 ; IRQ mode ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports/cortex_r5/iar/src/tx_thread_irq_nesting_start.s b/ports/cortex_r5/iar/src/tx_thread_irq_nesting_start.s index 70e6116b..ebdc203b 100644 --- a/ports/cortex_r5/iar/src/tx_thread_irq_nesting_start.s +++ b/ports/cortex_r5/iar/src/tx_thread_irq_nesting_start.s @@ -39,7 +39,7 @@ SYS_MODE DEFINE 0x1F ; System mode ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_irq_nesting_start Cortex-R5/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -75,7 +75,7 @@ SYS_MODE DEFINE 0x1F ; System mode ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports/cortex_r5/iar/src/tx_thread_schedule.s b/ports/cortex_r5/iar/src/tx_thread_schedule.s index 14403ee3..9cd41053 100644 --- a/ports/cortex_r5/iar/src/tx_thread_schedule.s +++ b/ports/cortex_r5/iar/src/tx_thread_schedule.s @@ -43,7 +43,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-R5/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -76,7 +76,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) diff --git a/ports/cortex_r5/iar/src/tx_thread_stack_build.s b/ports/cortex_r5/iar/src/tx_thread_stack_build.s index b09b4f98..103af6a7 100644 --- a/ports/cortex_r5/iar/src/tx_thread_stack_build.s +++ b/ports/cortex_r5/iar/src/tx_thread_stack_build.s @@ -39,7 +39,7 @@ CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints en ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build Cortex-R5/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints en ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/cortex_r5/iar/src/tx_thread_system_return.s b/ports/cortex_r5/iar/src/tx_thread_system_return.s index fbd5b756..2b0cb9e7 100644 --- a/ports/cortex_r5/iar/src/tx_thread_system_return.s +++ b/ports/cortex_r5/iar/src/tx_thread_system_return.s @@ -43,7 +43,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return Cortex-R5/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -75,7 +75,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) diff --git a/ports/cortex_r5/iar/src/tx_thread_vectored_context_save.s b/ports/cortex_r5/iar/src/tx_thread_vectored_context_save.s index ebc54f54..8e9e3e2e 100644 --- a/ports/cortex_r5/iar/src/tx_thread_vectored_context_save.s +++ b/ports/cortex_r5/iar/src/tx_thread_vectored_context_save.s @@ -41,7 +41,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_vectored_context_save Cortex-R5/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) diff --git a/ports/cortex_r5/iar/src/tx_timer_interrupt.s b/ports/cortex_r5/iar/src/tx_timer_interrupt.s index 007fc2aa..676f4f53 100644 --- a/ports/cortex_r5/iar/src/tx_timer_interrupt.s +++ b/ports/cortex_r5/iar/src/tx_timer_interrupt.s @@ -49,7 +49,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt Cortex-R5/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -83,7 +83,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) diff --git a/ports/cortex_r7/green/example_build/azure_rtos_workspace.gpj b/ports/cortex_r7/green/example_build/azure_rtos_workspace.gpj new file mode 100644 index 00000000..d44ebde2 --- /dev/null +++ b/ports/cortex_r7/green/example_build/azure_rtos_workspace.gpj @@ -0,0 +1,12 @@ +#!gbuild +primaryTarget=arm_standalone.tgt +[Project] + -G + -littleendian + -bsp generic + -cpu=cortexr7 +sample_threadx.gpj [Program] +sample_threadx_el.gpj [Program] +tx.gpj [Library] +txe.gpj [Library] +..\readme_threadx.txt diff --git a/ports/cortex_r7/green/example_build/reset.arm b/ports/cortex_r7/green/example_build/reset.arm new file mode 100644 index 00000000..ec0fe3da --- /dev/null +++ b/ports/cortex_r7/green/example_build/reset.arm @@ -0,0 +1,45 @@ +# +# +#/* Define the Cortex-R7 vector area. This should be located or copied to 0. */ +# + + .section ".reset", .text + .globl __vectors +__vectors: + B __entry # Reset goes to the entry function + LDR pc,UNDEFINED # Undefined handler + LDR pc,SWI # Software interrupt handler + LDR pc,PREFETCH # Prefetch exception handler + LDR pc,ABORT # Abort exception handler + LDR pc,RESERVED # Reserved exception handler + LDR pc,IRQ # IRQ interrupt handler + LDR pc,FIQ # FIQ interrupt handler +# +# +__entry: + LDR sp,STACK # Setup stack pointer + LDR pc,START # Jump to Green Hills startup +# +# +STACK: + .data.w __ghsend_stack +START: + .data.w _start # Reset goes to startup function +UNDEFINED: + .data.w __tx_undefined # Undefined handler +SWI: + .data.w __tx_swi_interrupt # Software interrupt handler +PREFETCH: + .data.w __tx_prefetch_handler # Prefetch exception handler +ABORT: + .data.w __tx_abort_handler # Abort exception handler +RESERVED: + .data.w __tx_reserved_handler # Reserved exception handler +IRQ: + .data.w __tx_irq_handler # IRQ interrupt handler +FIQ: + .data.w __tx_fiq_handler # FIQ interrupt handler +# +# + .type __vectors,$function + .size __vectors,.-__vectors diff --git a/ports/cortex_r7/green/example_build/sample_threadx.c b/ports/cortex_r7/green/example_build/sample_threadx.c new file mode 100644 index 00000000..418ec634 --- /dev/null +++ b/ports/cortex_r7/green/example_build/sample_threadx.c @@ -0,0 +1,369 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_r7/green/example_build/sample_threadx.con b/ports/cortex_r7/green/example_build/sample_threadx.con new file mode 100644 index 00000000..2f67f831 --- /dev/null +++ b/ports/cortex_r7/green/example_build/sample_threadx.con @@ -0,0 +1,17 @@ +target_connection { + { + title = "Simulator connection for ThreadX" + type = "Custom" + short_type = "Custom" + args = "simarm -cpu=cortexr7 -fpu -rom" + command = "simarm -cpu=cortexr7 -fpu -rom" + logfile = "" + mode = "" + setup_script = "" + run_mode_partner = "" + run_mode_policy = "" + sane = "yes" + log = "no" + timestamp = "0" + } +} diff --git a/ports/cortex_r7/green/example_build/sample_threadx.gpj b/ports/cortex_r7/green/example_build/sample_threadx.gpj new file mode 100644 index 00000000..b9b2c04c --- /dev/null +++ b/ports/cortex_r7/green/example_build/sample_threadx.gpj @@ -0,0 +1,11 @@ +#!gbuild +[Program] + -I../../../../common/inc + -I../../../../ports_common_green/inc + -I../inc +reset.arm +tx_initialize_low_level.arm +sample_threadx.c +tx.a +sample_threadx.ld +sample_threadx.con diff --git a/ports/cortex_r7/green/example_build/sample_threadx.ld b/ports/cortex_r7/green/example_build/sample_threadx.ld new file mode 100644 index 00000000..8d1ab4df --- /dev/null +++ b/ports/cortex_r7/green/example_build/sample_threadx.ld @@ -0,0 +1,44 @@ +# The following explains what the default Green Hills sections are for: +# +# picbase - base of the text sections, relocatable in -pic mode +# text - text section +# syscall - syscall section, for host I/O under Multi +# fixaddr/fixtype - for PIC/PID fixups +# rodata - read only data +# romdata - the ROM image of .data +# romsdata - the ROM image of .sdata +# secinfo - section information section, used by the start-up code +# pidbase - base of the data sections, relocatable in -pid mode +# sdabase - base of the small data area section pointer +# sbss - small BSS (zeroed data) section +# sdata - small data section +# data - non-zeroed writeable data section +# bss - zeroed data section +# heap - the heap, grows upward +# stack - the stack, grows downward + +-sec +{ + .reset 0x000000 : + .picbase 0x1000 : + .text : + .comment : + .intercall : + .interfunc : + .syscall : + .fixaddr : + .fixtype : + .rodata : + .romdata ROM(.data) : + .romsdata ROM(.sdata) : + .secinfo : + .pidbase align(16) : + .sdabase : + .sbss : + .sdata : + .data : + .bss : + .heap align(16) pad(0x10000) : + .stack align(16) pad(0x1000) : + .free_mem align(16) pad(0x10000) : +} diff --git a/ports/cortex_r7/green/example_build/sample_threadx_el.gpj b/ports/cortex_r7/green/example_build/sample_threadx_el.gpj new file mode 100644 index 00000000..a51049ca --- /dev/null +++ b/ports/cortex_r7/green/example_build/sample_threadx_el.gpj @@ -0,0 +1,13 @@ +#!gbuild +[Program] + -DTX_ENABLE_EVENT_LOGGING + -I../../../../common/inc + -I../../../../ports_common_green/inc + -I../inc +reset.arm +tx_initialize_low_level.arm +sample_threadx.c +txe.a +sample_threadx_el.ld +sample_threadx.con +readme_threadx.txt diff --git a/ports/cortex_r7/green/example_build/sample_threadx_el.ld b/ports/cortex_r7/green/example_build/sample_threadx_el.ld new file mode 100644 index 00000000..33c0f934 --- /dev/null +++ b/ports/cortex_r7/green/example_build/sample_threadx_el.ld @@ -0,0 +1,45 @@ +# The following explains what the default Green Hills sections are for: +# +# picbase - base of the text sections, relocatable in -pic mode +# text - text section +# syscall - syscall section, for host I/O under Multi +# fixaddr/fixtype - for PIC/PID fixups +# rodata - read only data +# romdata - the ROM image of .data +# romsdata - the ROM image of .sdata +# secinfo - section information section, used by the start-up code +# pidbase - base of the data sections, relocatable in -pid mode +# sdabase - base of the small data area section pointer +# sbss - small BSS (zeroed data) section +# sdata - small data section +# data - non-zeroed writeable data section +# bss - zeroed data section +# heap - the heap, grows upward +# stack - the stack, grows downward + +-sec +{ + .reset 0x000000 : + .picbase 0x1000 : + .text : + .comment : + .intercall : + .interfunc : + .syscall : + .fixaddr : + .fixtype : + .rodata : + .romdata ROM(.data) : + .romsdata ROM(.sdata) : + .secinfo : + .pidbase align(16) : + .sdabase : + .sbss : + .sdata : + .data : + .bss : + .heap align(16) pad(0x1000) : + .stack align(16) pad(0x1000) : + .eventlog align(16) pad(0x10000) : + .free_mem align(16) pad(0x10000) : +} diff --git a/ports/cortex_r7/green/example_build/tx.gpj b/ports/cortex_r7/green/example_build/tx.gpj new file mode 100644 index 00000000..afbd6bef --- /dev/null +++ b/ports/cortex_r7/green/example_build/tx.gpj @@ -0,0 +1,283 @@ +#!gbuild +[Library] + -I../../../../common/inc + -I../../../../ports_common_green/inc + -I../inc +..\..\..\..\common\inc\tx_api.h +..\..\..\..\common\inc\tx_block_pool.h +..\..\..\..\common\inc\tx_byte_pool.h +..\..\..\..\common\inc\tx_event_flags.h +..\..\..\..\common\inc\tx_initialize.h +..\..\..\..\common\inc\tx_mutex.h +..\..\..\..\common\inc\tx_queue.h +..\..\..\..\common\inc\tx_semaphore.h +..\..\..\..\common\inc\tx_thread.h +..\..\..\..\common\inc\tx_timer.h +..\..\..\..\common\inc\tx_trace.h +..\..\..\..\common\inc\tx_user_sample.h +..\inc\tx_port.h +..\..\..\..\ports_common_green\inc\tx_el.h +..\..\..\..\ports_common_green\inc\tx_ghs.h +..\src\tx_thread_context_restore.arm +..\src\tx_thread_context_save.arm +..\src\tx_thread_fiq_context_restore.arm +..\src\tx_thread_fiq_context_save.arm +..\src\tx_thread_fiq_nesting_end.arm +..\src\tx_thread_fiq_nesting_start.arm +..\src\tx_thread_interrupt_control.arm +..\src\tx_thread_interrupt_disable.arm +..\src\tx_thread_interrupt_restore.arm +..\src\tx_thread_irq_nesting_end.arm +..\src\tx_thread_irq_nesting_start.arm +..\src\tx_thread_schedule.arm +..\src\tx_thread_stack_build.arm +..\src\tx_thread_system_return.arm +..\src\tx_thread_vectored_context_save.arm +..\src\tx_timer_interrupt.arm +..\..\..\..\common\src\tx_block_allocate.c +..\..\..\..\common\src\tx_block_pool_cleanup.c +..\..\..\..\common\src\tx_block_pool_create.c +..\..\..\..\common\src\tx_block_pool_delete.c +..\..\..\..\common\src\tx_block_pool_info_get.c +..\..\..\..\common\src\tx_block_pool_initialize.c +..\..\..\..\common\src\tx_block_pool_performance_info_get.c +..\..\..\..\common\src\tx_block_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_block_pool_prioritize.c +..\..\..\..\common\src\tx_block_release.c +..\..\..\..\common\src\tx_byte_allocate.c +..\..\..\..\common\src\tx_byte_pool_cleanup.c +..\..\..\..\common\src\tx_byte_pool_create.c +..\..\..\..\common\src\tx_byte_pool_delete.c +..\..\..\..\common\src\tx_byte_pool_info_get.c +..\..\..\..\common\src\tx_byte_pool_initialize.c +..\..\..\..\common\src\tx_byte_pool_performance_info_get.c +..\..\..\..\common\src\tx_byte_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_byte_pool_prioritize.c +..\..\..\..\common\src\tx_byte_pool_search.c +..\..\..\..\common\src\tx_byte_release.c +..\..\..\..\common\src\tx_event_flags_cleanup.c +..\..\..\..\common\src\tx_event_flags_create.c +..\..\..\..\common\src\tx_event_flags_delete.c +..\..\..\..\common\src\tx_event_flags_get.c +..\..\..\..\common\src\tx_event_flags_info_get.c +..\..\..\..\common\src\tx_event_flags_initialize.c +..\..\..\..\common\src\tx_event_flags_performance_info_get.c +..\..\..\..\common\src\tx_event_flags_performance_system_info_get.c +..\..\..\..\common\src\tx_event_flags_set.c +..\..\..\..\common\src\tx_event_flags_set_notify.c +..\..\..\..\common\src\tx_initialize_high_level.c +..\..\..\..\common\src\tx_initialize_kernel_enter.c +..\..\..\..\common\src\tx_initialize_kernel_setup.c +..\..\..\..\common\src\tx_mutex_cleanup.c +..\..\..\..\common\src\tx_mutex_create.c +..\..\..\..\common\src\tx_mutex_delete.c +..\..\..\..\common\src\tx_mutex_get.c +..\..\..\..\common\src\tx_mutex_info_get.c +..\..\..\..\common\src\tx_mutex_initialize.c +..\..\..\..\common\src\tx_mutex_performance_info_get.c +..\..\..\..\common\src\tx_mutex_performance_system_info_get.c +..\..\..\..\common\src\tx_mutex_prioritize.c +..\..\..\..\common\src\tx_mutex_priority_change.c +..\..\..\..\common\src\tx_mutex_put.c +..\..\..\..\common\src\tx_queue_cleanup.c +..\..\..\..\common\src\tx_queue_create.c +..\..\..\..\common\src\tx_queue_delete.c +..\..\..\..\common\src\tx_queue_flush.c +..\..\..\..\common\src\tx_queue_front_send.c +..\..\..\..\common\src\tx_queue_info_get.c +..\..\..\..\common\src\tx_queue_initialize.c +..\..\..\..\common\src\tx_queue_performance_info_get.c +..\..\..\..\common\src\tx_queue_performance_system_info_get.c +..\..\..\..\common\src\tx_queue_prioritize.c +..\..\..\..\common\src\tx_queue_receive.c +..\..\..\..\common\src\tx_queue_send.c +..\..\..\..\common\src\tx_queue_send_notify.c +..\..\..\..\common\src\tx_semaphore_ceiling_put.c +..\..\..\..\common\src\tx_semaphore_cleanup.c +..\..\..\..\common\src\tx_semaphore_create.c +..\..\..\..\common\src\tx_semaphore_delete.c +..\..\..\..\common\src\tx_semaphore_get.c +..\..\..\..\common\src\tx_semaphore_info_get.c +..\..\..\..\common\src\tx_semaphore_initialize.c +..\..\..\..\common\src\tx_semaphore_performance_info_get.c +..\..\..\..\common\src\tx_semaphore_performance_system_info_get.c +..\..\..\..\common\src\tx_semaphore_prioritize.c +..\..\..\..\common\src\tx_semaphore_put.c +..\..\..\..\common\src\tx_semaphore_put_notify.c +..\..\..\..\common\src\tx_thread_create.c +..\..\..\..\common\src\tx_thread_delete.c +..\..\..\..\common\src\tx_thread_entry_exit_notify.c +..\..\..\..\common\src\tx_thread_identify.c +..\..\..\..\common\src\tx_thread_info_get.c +..\..\..\..\common\src\tx_thread_initialize.c +..\..\..\..\common\src\tx_thread_performance_info_get.c +..\..\..\..\common\src\tx_thread_performance_system_info_get.c +..\..\..\..\common\src\tx_thread_preemption_change.c +..\..\..\..\common\src\tx_thread_priority_change.c +..\..\..\..\common\src\tx_thread_relinquish.c +..\..\..\..\common\src\tx_thread_reset.c +..\..\..\..\common\src\tx_thread_resume.c +..\..\..\..\common\src\tx_thread_shell_entry.c +..\..\..\..\common\src\tx_thread_sleep.c +..\..\..\..\common\src\tx_thread_stack_analyze.c +..\..\..\..\common\src\tx_thread_stack_error_handler.c +..\..\..\..\common\src\tx_thread_stack_error_notify.c +..\..\..\..\common\src\tx_thread_suspend.c +..\..\..\..\common\src\tx_thread_system_preempt_check.c +..\..\..\..\common\src\tx_thread_system_resume.c +..\..\..\..\common\src\tx_thread_system_suspend.c +..\..\..\..\common\src\tx_thread_terminate.c +..\..\..\..\common\src\tx_thread_time_slice.c +..\..\..\..\common\src\tx_thread_time_slice_change.c +..\..\..\..\common\src\tx_thread_timeout.c +..\..\..\..\common\src\tx_thread_wait_abort.c +..\..\..\..\common\src\tx_time_get.c +..\..\..\..\common\src\tx_time_set.c +..\..\..\..\common\src\tx_timer_activate.c +..\..\..\..\common\src\tx_timer_change.c +..\..\..\..\common\src\tx_timer_create.c +..\..\..\..\common\src\tx_timer_deactivate.c +..\..\..\..\common\src\tx_timer_delete.c +..\..\..\..\common\src\tx_timer_expiration_process.c +..\..\..\..\common\src\tx_timer_info_get.c +..\..\..\..\common\src\tx_timer_initialize.c +..\..\..\..\common\src\tx_timer_performance_info_get.c +..\..\..\..\common\src\tx_timer_performance_system_info_get.c +..\..\..\..\common\src\tx_timer_system_activate.c +..\..\..\..\common\src\tx_timer_system_deactivate.c +..\..\..\..\common\src\tx_timer_thread_entry.c +..\..\..\..\common\src\tx_trace_buffer_full_notify.c +..\..\..\..\common\src\tx_trace_disable.c +..\..\..\..\common\src\tx_trace_enable.c +..\..\..\..\common\src\tx_trace_event_filter.c +..\..\..\..\common\src\tx_trace_event_unfilter.c +..\..\..\..\common\src\tx_trace_initialize.c +..\..\..\..\common\src\tx_trace_interrupt_control.c +..\..\..\..\common\src\tx_trace_isr_enter_insert.c +..\..\..\..\common\src\tx_trace_isr_exit_insert.c +..\..\..\..\common\src\tx_trace_object_register.c +..\..\..\..\common\src\tx_trace_object_unregister.c +..\..\..\..\common\src\tx_trace_user_event_insert.c +..\..\..\..\common\src\txe_block_allocate.c +..\..\..\..\common\src\txe_block_pool_create.c +..\..\..\..\common\src\txe_block_pool_delete.c +..\..\..\..\common\src\txe_block_pool_info_get.c +..\..\..\..\common\src\txe_block_pool_prioritize.c +..\..\..\..\common\src\txe_block_release.c +..\..\..\..\common\src\txe_byte_allocate.c +..\..\..\..\common\src\txe_byte_pool_create.c +..\..\..\..\common\src\txe_byte_pool_delete.c +..\..\..\..\common\src\txe_byte_pool_info_get.c +..\..\..\..\common\src\txe_byte_pool_prioritize.c +..\..\..\..\common\src\txe_byte_release.c +..\..\..\..\common\src\txe_event_flags_create.c +..\..\..\..\common\src\txe_event_flags_delete.c +..\..\..\..\common\src\txe_event_flags_get.c +..\..\..\..\common\src\txe_event_flags_info_get.c +..\..\..\..\common\src\txe_event_flags_set.c +..\..\..\..\common\src\txe_event_flags_set_notify.c +..\..\..\..\common\src\txe_mutex_create.c +..\..\..\..\common\src\txe_mutex_delete.c +..\..\..\..\common\src\txe_mutex_get.c +..\..\..\..\common\src\txe_mutex_info_get.c +..\..\..\..\common\src\txe_mutex_prioritize.c +..\..\..\..\common\src\txe_mutex_put.c +..\..\..\..\common\src\txe_queue_create.c +..\..\..\..\common\src\txe_queue_delete.c +..\..\..\..\common\src\txe_queue_flush.c +..\..\..\..\common\src\txe_queue_front_send.c +..\..\..\..\common\src\txe_queue_info_get.c +..\..\..\..\common\src\txe_queue_prioritize.c +..\..\..\..\common\src\txe_queue_receive.c +..\..\..\..\common\src\txe_queue_send.c +..\..\..\..\common\src\txe_queue_send_notify.c +..\..\..\..\common\src\txe_semaphore_ceiling_put.c +..\..\..\..\common\src\txe_semaphore_create.c +..\..\..\..\common\src\txe_semaphore_delete.c +..\..\..\..\common\src\txe_semaphore_get.c +..\..\..\..\common\src\txe_semaphore_info_get.c +..\..\..\..\common\src\txe_semaphore_prioritize.c +..\..\..\..\common\src\txe_semaphore_put.c +..\..\..\..\common\src\txe_semaphore_put_notify.c +..\..\..\..\common\src\txe_thread_create.c +..\..\..\..\common\src\txe_thread_delete.c +..\..\..\..\common\src\txe_thread_entry_exit_notify.c +..\..\..\..\common\src\txe_thread_info_get.c +..\..\..\..\common\src\txe_thread_preemption_change.c +..\..\..\..\common\src\txe_thread_priority_change.c +..\..\..\..\common\src\txe_thread_relinquish.c +..\..\..\..\common\src\txe_thread_reset.c +..\..\..\..\common\src\txe_thread_resume.c +..\..\..\..\common\src\txe_thread_suspend.c +..\..\..\..\common\src\txe_thread_terminate.c +..\..\..\..\common\src\txe_thread_time_slice_change.c +..\..\..\..\common\src\txe_thread_wait_abort.c +..\..\..\..\common\src\txe_timer_activate.c +..\..\..\..\common\src\txe_timer_change.c +..\..\..\..\common\src\txe_timer_create.c +..\..\..\..\common\src\txe_timer_deactivate.c +..\..\..\..\common\src\txe_timer_delete.c +..\..\..\..\common\src\txe_timer_info_get.c +..\..\..\..\ports_common_green\src\tx_el.c +..\..\..\..\ports_common_green\src\tx_ghs.c +..\..\..\..\ports_common_green\src\tx_ghse.c +..\..\..\..\ports_common_green\src\txr_block_allocate.c +..\..\..\..\ports_common_green\src\txr_block_pool_create.c +..\..\..\..\ports_common_green\src\txr_block_pool_delete.c +..\..\..\..\ports_common_green\src\txr_block_pool_info_get.c +..\..\..\..\ports_common_green\src\txr_block_pool_prioritize.c +..\..\..\..\ports_common_green\src\txr_block_release.c +..\..\..\..\ports_common_green\src\txr_byte_allocate.c +..\..\..\..\ports_common_green\src\txr_byte_pool_create.c +..\..\..\..\ports_common_green\src\txr_byte_pool_delete.c +..\..\..\..\ports_common_green\src\txr_byte_pool_info_get.c +..\..\..\..\ports_common_green\src\txr_byte_pool_prioritize.c +..\..\..\..\ports_common_green\src\txr_byte_release.c +..\..\..\..\ports_common_green\src\txr_event_flags_create.c +..\..\..\..\ports_common_green\src\txr_event_flags_delete.c +..\..\..\..\ports_common_green\src\txr_event_flags_get.c +..\..\..\..\ports_common_green\src\txr_event_flags_info_get.c +..\..\..\..\ports_common_green\src\txr_event_flags_set.c +..\..\..\..\ports_common_green\src\txr_event_flags_set_notify.c +..\..\..\..\ports_common_green\src\txr_ghs.c +..\..\..\..\ports_common_green\src\txr_mutex_create.c +..\..\..\..\ports_common_green\src\txr_mutex_delete.c +..\..\..\..\ports_common_green\src\txr_mutex_get.c +..\..\..\..\ports_common_green\src\txr_mutex_info_get.c +..\..\..\..\ports_common_green\src\txr_mutex_prioritize.c +..\..\..\..\ports_common_green\src\txr_mutex_put.c +..\..\..\..\ports_common_green\src\txr_queue_create.c +..\..\..\..\ports_common_green\src\txr_queue_delete.c +..\..\..\..\ports_common_green\src\txr_queue_flush.c +..\..\..\..\ports_common_green\src\txr_queue_front_send.c +..\..\..\..\ports_common_green\src\txr_queue_info_get.c +..\..\..\..\ports_common_green\src\txr_queue_prioritize.c +..\..\..\..\ports_common_green\src\txr_queue_receive.c +..\..\..\..\ports_common_green\src\txr_queue_send.c +..\..\..\..\ports_common_green\src\txr_queue_send_notify.c +..\..\..\..\ports_common_green\src\txr_semaphore_ceiling_put.c +..\..\..\..\ports_common_green\src\txr_semaphore_create.c +..\..\..\..\ports_common_green\src\txr_semaphore_delete.c +..\..\..\..\ports_common_green\src\txr_semaphore_get.c +..\..\..\..\ports_common_green\src\txr_semaphore_info_get.c +..\..\..\..\ports_common_green\src\txr_semaphore_prioritize.c +..\..\..\..\ports_common_green\src\txr_semaphore_put.c +..\..\..\..\ports_common_green\src\txr_semaphore_put_notify.c +..\..\..\..\ports_common_green\src\txr_thread_create.c +..\..\..\..\ports_common_green\src\txr_thread_delete.c +..\..\..\..\ports_common_green\src\txr_thread_entry_exit_notify.c +..\..\..\..\ports_common_green\src\txr_thread_info_get.c +..\..\..\..\ports_common_green\src\txr_thread_preemption_change.c +..\..\..\..\ports_common_green\src\txr_thread_priority_change.c +..\..\..\..\ports_common_green\src\txr_thread_reset.c +..\..\..\..\ports_common_green\src\txr_thread_resume.c +..\..\..\..\ports_common_green\src\txr_thread_suspend.c +..\..\..\..\ports_common_green\src\txr_thread_terminate.c +..\..\..\..\ports_common_green\src\txr_thread_time_slice_change.c +..\..\..\..\ports_common_green\src\txr_thread_wait_abort.c +..\..\..\..\ports_common_green\src\txr_timer_activate.c +..\..\..\..\ports_common_green\src\txr_timer_change.c +..\..\..\..\ports_common_green\src\txr_timer_create.c +..\..\..\..\ports_common_green\src\txr_timer_deactivate.c +..\..\..\..\ports_common_green\src\txr_timer_delete.c +..\..\..\..\ports_common_green\src\txr_timer_info_get.c diff --git a/ports/cortex_r7/green/example_build/tx_initialize_low_level.arm b/ports/cortex_r7/green/example_build/tx_initialize_low_level.arm new file mode 100644 index 00000000..777091fc --- /dev/null +++ b/ports/cortex_r7/green/example_build/tx_initialize_low_level.arm @@ -0,0 +1,319 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_initialize.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + SVC_MODE = 0xD3 # Disable IRQ/FIQ SVC mode + IRQ_MODE = 0xD2 # Disable IRQ/FIQ IRQ mode + FIQ_MODE = 0xD1 # Disable IRQ/FIQ FIQ mode + SYS_MODE = 0xDF # Disable IRQ/FIQ SYS mode + MODE_MASK = 0x1F # Mode mask + FIQ_STACK_SIZE = 512 # FIQ stack size + IRQ_STACK_SIZE = 1024 # IRQ stack size + SYS_STACK_SIZE = 1024 # SYS stack size + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-R7/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_initialize_low_level(VOID) +{ */ + .globl _tx_initialize_low_level +_tx_initialize_low_level: + + /****** NOTE ****** We must be in SVC MODE at this point. Some monitors + enter this routine in USER mode and require a software interrupt to + change into SVC mode. */ + + /* Save the system stack pointer. */ + /* _tx_thread_system_stack_ptr = (VOID_PTR) (sp); */ + + LDR r1,=_tx_thread_system_stack_ptr # Pickup address of system stack ptr + STR sp, [r1] # Save system stack + + /* Pickup the first available memory address. */ + + LDR r0,=__ghsbegin_free_mem # Pickup free memory address + + /* Setup initial stack pointers for IRQ and FIQ modes. */ + + MRS r12, CPSR # Pickup current CPSR + MOV r1, r0 # Get first available memory +#ifdef TX_ENABLE_IRQ_NESTING + /* Setup the system mode stack for nested interrupt support */ + LDR r2, =SYS_STACK_SIZE # Pickup stack size + BIC r3, r12, MODE_MASK # Clear mode bits + ORR r3, r3, SYS_MODE # Build SYS mode CPSR + MSR CPSR_c, r3 # Enter SYS mode + ADD r1, r1, r2 # Calculate start of SYS stack + SUB r1, r1, 1 # Backup one byte + BIC r1, r1, 7 # Insure 8-byte alignment + MOV sp, r1 # Setup SYS stack pointer +#endif + LDR r2, =FIQ_STACK_SIZE # Pickup stack size + BIC r3, r12, MODE_MASK # Clear mode bits + ORR r3, r3, FIQ_MODE # Build FIQ mode CPSR + MSR CPSR_c, r3 # Enter FIQ mode + ADD r1, r1, r2 # Calculate start of FIQ stack + SUB r1, r1, 1 # Backup one byte + BIC r1, r1, 7 # Insure 8-byte alignment + MOV sp, r1 # Setup FIQ stack pointer + MOV r10, 0 # Clear sl + MOV r11, 0 # Clear fp + LDR r2, =IRQ_STACK_SIZE # Pickup IRQ (system stack size) + BIC r3, r12, MODE_MASK # Clear mode bits + ORR r3, r3, IRQ_MODE # Build IRQ mode CPSR + MSR CPSR_c, r3 # Enter IRQ mode + ADD r1, r1, r2 # Calculate start of IRQ stack + SUB r1, r1, 1 # Backup one byte + BIC r1, r1, 7 # Insure 8-byte alignment + MOV sp, r1 # Setup IRQ stack pointer + MSR CPSR_c, r12 # Restore previous mode + ADD r0, r1, 4 # Adjust the new free memory + + + /* Save the first available memory address. */ + /* _tx_initialize_unused_memory = (VOID_PTR) __ghsbegin_free_mem + [SYS_STACK] + FIQ_STACK + IRQ_STACK; */ + + LDR r2,=_tx_initialize_unused_memory # Pickup unused memory ptr address + STR r0, [r2] # Save first free memory address + + + /* Setup Timer for periodic interrupts. To generate timer interrupts with + the Green Hills simulator, enter the following command in the target + window: timer 9999 irq */ + + /* Done, return to caller. */ + + RET # Return to caller + + .type _tx_initialize_low_level,$function + .size _tx_initialize_low_level,.-_tx_initialize_low_level +/* } */ + + +/* Define shells for each of the interrupt vectors. */ + + .globl __tx_undefined +__tx_undefined: + B __tx_undefined # Undefined handler + + .type __tx_undefined,$function + .size __tx_undefined,.-__tx_undefined + + .globl __tx_swi_interrupt +__tx_swi_interrupt: + B __tx_swi_interrupt # Software interrupt handler + + .type __tx_swi_interrupt,$function + .size __tx_swi_interrupt,.-__tx_swi_interrupt + + .globl __tx_prefetch_handler +__tx_prefetch_handler: + B __tx_prefetch_handler # Prefetch exception handler + + .type __tx_prefetch_handler,$function + .size __tx_prefetch_handler,.-__tx_prefetch_handler + + .globl __tx_abort_handler +__tx_abort_handler: + B __tx_abort_handler # Abort exception handler + + .type __tx_abort_handler,$function + .size __tx_abort_handler,.-__tx_abort_handler + + .globl __tx_reserved_handler +__tx_reserved_handler: + B __tx_reserved_handler # Reserved exception handler + + .type __tx_reserved_handler,$function + .size __tx_reserved_handler,.-__tx_reserved_handler + + .globl __tx_irq_handler + .globl __tx_irq_processing_return +__tx_irq_handler: + + /* Jump to context save to save system context. */ + B _tx_thread_context_save + + .type __tx_irq_handler,$function + .size __tx_irq_handler,.-__tx_irq_handler + +__tx_irq_processing_return: + + /* At this point execution is still in the IRQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. */ + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 0 # Build interrupt code + BL _tx_el_interrupt # Call interrupt event logging +#endif + + /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start + from IRQ mode with interrupts disabled. This routine switches to the + system mode and returns with IRQ interrupts enabled. + + NOTE: It is very important to ensure all IRQ interrupts are cleared + prior to enabling nested IRQ interrupts. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_start +#endif + + + /* For debug purpose, execute the timer interrupt processing here. In + a real system, some kind of status indication would have to be checked + before the timer interrupt handler could be called. */ + BL _tx_timer_interrupt # Timer interrupt handler + + /* Application IRQ handlers can be called here! */ + + /* If interrupt nesting was started earlier, the end of interrupt nesting + service must be called before returning to _tx_thread_context_restore. + This routine returns in processing in IRQ mode with interrupts disabled. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_end +#endif + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 0 # Build interrupt code + BL _tx_el_interrupt_end # Call interrupt event logging +#endif + + /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + .type __tx_irq_processing_return,$function + .size __tx_irq_processing_return,.-__tx_irq_processing_return + +#ifdef TX_ENABLE_FIQ_SUPPORT + + .globl __tx_fiq_handler + .globl __tx_fiq_processing_return +__tx_fiq_handler: + /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save + + .type __tx_fiq_handler,$function + .size __tx_fiq_handler,.-__tx_fiq_handler + +__tx_fiq_processing_return: + + /* At this point execution is still in the FIQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. */ + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 1 # Build interrupt code + BL _tx_el_interrupt # Call interrupt event logging +#endif + + /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start + from FIQ mode with interrupts disabled. This routine switches to the + system mode and returns with FIQ interrupts enabled. + + NOTE: It is very important to ensure all FIQ interrupts are cleared + prior to enabling nested FIQ interrupts. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_start +#endif + + /* Application FIQ handlers can be called here! */ + + /* If interrupt nesting was started earlier, the end of interrupt nesting + service must be called before returning to _tx_thread_fiq_context_restore. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_end +#endif + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r0, 1 # Build interrupt code + BL _tx_el_interrupt_end # Call interrupt event logging +#endif + + /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + .type __tx_fiq_processing_return,$function + .size __tx_fiq_processing_return,.-__tx_fiq_processing_return + +#else + .globl __tx_fiq_handler +__tx_fiq_handler: + B __tx_fiq_handler # FIQ interrupt handler + + .type __tx_fiq_handler,$function + .size __tx_fiq_handler,.-__tx_fiq_handler +#endif + + /* Reference build options and version ID to ensure they come in. */ + +BUILD_OPTIONS: + .data.w _tx_build_options +VERSION_ID: + .data.w _tx_version_id diff --git a/ports/cortex_r7/green/example_build/txe.gpj b/ports/cortex_r7/green/example_build/txe.gpj new file mode 100644 index 00000000..662bcd16 --- /dev/null +++ b/ports/cortex_r7/green/example_build/txe.gpj @@ -0,0 +1,284 @@ +#!gbuild +[Library] + -DTX_ENABLE_EVENT_LOGGING + -I../../../../common/inc + -I../../../../ports_common_green/inc + -I../inc +..\..\..\..\common\inc\tx_api.h +..\..\..\..\common\inc\tx_block_pool.h +..\..\..\..\common\inc\tx_byte_pool.h +..\..\..\..\common\inc\tx_event_flags.h +..\..\..\..\common\inc\tx_initialize.h +..\..\..\..\common\inc\tx_mutex.h +..\..\..\..\common\inc\tx_queue.h +..\..\..\..\common\inc\tx_semaphore.h +..\..\..\..\common\inc\tx_thread.h +..\..\..\..\common\inc\tx_timer.h +..\..\..\..\common\inc\tx_trace.h +..\..\..\..\common\inc\tx_user_sample.h +..\inc\tx_port.h +..\..\..\..\ports_common_green\inc\tx_el.h +..\..\..\..\ports_common_green\inc\tx_ghs.h +..\src\tx_thread_context_restore.arm +..\src\tx_thread_context_save.arm +..\src\tx_thread_fiq_context_restore.arm +..\src\tx_thread_fiq_context_save.arm +..\src\tx_thread_fiq_nesting_end.arm +..\src\tx_thread_fiq_nesting_start.arm +..\src\tx_thread_interrupt_control.arm +..\src\tx_thread_interrupt_disable.arm +..\src\tx_thread_interrupt_restore.arm +..\src\tx_thread_irq_nesting_end.arm +..\src\tx_thread_irq_nesting_start.arm +..\src\tx_thread_schedule.arm +..\src\tx_thread_stack_build.arm +..\src\tx_thread_system_return.arm +..\src\tx_thread_vectored_context_save.arm +..\src\tx_timer_interrupt.arm +..\..\..\..\common\src\tx_block_allocate.c +..\..\..\..\common\src\tx_block_pool_cleanup.c +..\..\..\..\common\src\tx_block_pool_create.c +..\..\..\..\common\src\tx_block_pool_delete.c +..\..\..\..\common\src\tx_block_pool_info_get.c +..\..\..\..\common\src\tx_block_pool_initialize.c +..\..\..\..\common\src\tx_block_pool_performance_info_get.c +..\..\..\..\common\src\tx_block_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_block_pool_prioritize.c +..\..\..\..\common\src\tx_block_release.c +..\..\..\..\common\src\tx_byte_allocate.c +..\..\..\..\common\src\tx_byte_pool_cleanup.c +..\..\..\..\common\src\tx_byte_pool_create.c +..\..\..\..\common\src\tx_byte_pool_delete.c +..\..\..\..\common\src\tx_byte_pool_info_get.c +..\..\..\..\common\src\tx_byte_pool_initialize.c +..\..\..\..\common\src\tx_byte_pool_performance_info_get.c +..\..\..\..\common\src\tx_byte_pool_performance_system_info_get.c +..\..\..\..\common\src\tx_byte_pool_prioritize.c +..\..\..\..\common\src\tx_byte_pool_search.c +..\..\..\..\common\src\tx_byte_release.c +..\..\..\..\common\src\tx_event_flags_cleanup.c +..\..\..\..\common\src\tx_event_flags_create.c +..\..\..\..\common\src\tx_event_flags_delete.c +..\..\..\..\common\src\tx_event_flags_get.c +..\..\..\..\common\src\tx_event_flags_info_get.c +..\..\..\..\common\src\tx_event_flags_initialize.c +..\..\..\..\common\src\tx_event_flags_performance_info_get.c +..\..\..\..\common\src\tx_event_flags_performance_system_info_get.c +..\..\..\..\common\src\tx_event_flags_set.c +..\..\..\..\common\src\tx_event_flags_set_notify.c +..\..\..\..\common\src\tx_initialize_high_level.c +..\..\..\..\common\src\tx_initialize_kernel_enter.c +..\..\..\..\common\src\tx_initialize_kernel_setup.c +..\..\..\..\common\src\tx_mutex_cleanup.c +..\..\..\..\common\src\tx_mutex_create.c +..\..\..\..\common\src\tx_mutex_delete.c +..\..\..\..\common\src\tx_mutex_get.c +..\..\..\..\common\src\tx_mutex_info_get.c +..\..\..\..\common\src\tx_mutex_initialize.c +..\..\..\..\common\src\tx_mutex_performance_info_get.c +..\..\..\..\common\src\tx_mutex_performance_system_info_get.c +..\..\..\..\common\src\tx_mutex_prioritize.c +..\..\..\..\common\src\tx_mutex_priority_change.c +..\..\..\..\common\src\tx_mutex_put.c +..\..\..\..\common\src\tx_queue_cleanup.c +..\..\..\..\common\src\tx_queue_create.c +..\..\..\..\common\src\tx_queue_delete.c +..\..\..\..\common\src\tx_queue_flush.c +..\..\..\..\common\src\tx_queue_front_send.c +..\..\..\..\common\src\tx_queue_info_get.c +..\..\..\..\common\src\tx_queue_initialize.c +..\..\..\..\common\src\tx_queue_performance_info_get.c +..\..\..\..\common\src\tx_queue_performance_system_info_get.c +..\..\..\..\common\src\tx_queue_prioritize.c +..\..\..\..\common\src\tx_queue_receive.c +..\..\..\..\common\src\tx_queue_send.c +..\..\..\..\common\src\tx_queue_send_notify.c +..\..\..\..\common\src\tx_semaphore_ceiling_put.c +..\..\..\..\common\src\tx_semaphore_cleanup.c +..\..\..\..\common\src\tx_semaphore_create.c +..\..\..\..\common\src\tx_semaphore_delete.c +..\..\..\..\common\src\tx_semaphore_get.c +..\..\..\..\common\src\tx_semaphore_info_get.c +..\..\..\..\common\src\tx_semaphore_initialize.c +..\..\..\..\common\src\tx_semaphore_performance_info_get.c +..\..\..\..\common\src\tx_semaphore_performance_system_info_get.c +..\..\..\..\common\src\tx_semaphore_prioritize.c +..\..\..\..\common\src\tx_semaphore_put.c +..\..\..\..\common\src\tx_semaphore_put_notify.c +..\..\..\..\common\src\tx_thread_create.c +..\..\..\..\common\src\tx_thread_delete.c +..\..\..\..\common\src\tx_thread_entry_exit_notify.c +..\..\..\..\common\src\tx_thread_identify.c +..\..\..\..\common\src\tx_thread_info_get.c +..\..\..\..\common\src\tx_thread_initialize.c +..\..\..\..\common\src\tx_thread_performance_info_get.c +..\..\..\..\common\src\tx_thread_performance_system_info_get.c +..\..\..\..\common\src\tx_thread_preemption_change.c +..\..\..\..\common\src\tx_thread_priority_change.c +..\..\..\..\common\src\tx_thread_relinquish.c +..\..\..\..\common\src\tx_thread_reset.c +..\..\..\..\common\src\tx_thread_resume.c +..\..\..\..\common\src\tx_thread_shell_entry.c +..\..\..\..\common\src\tx_thread_sleep.c +..\..\..\..\common\src\tx_thread_stack_analyze.c +..\..\..\..\common\src\tx_thread_stack_error_handler.c +..\..\..\..\common\src\tx_thread_stack_error_notify.c +..\..\..\..\common\src\tx_thread_suspend.c +..\..\..\..\common\src\tx_thread_system_preempt_check.c +..\..\..\..\common\src\tx_thread_system_resume.c +..\..\..\..\common\src\tx_thread_system_suspend.c +..\..\..\..\common\src\tx_thread_terminate.c +..\..\..\..\common\src\tx_thread_time_slice.c +..\..\..\..\common\src\tx_thread_time_slice_change.c +..\..\..\..\common\src\tx_thread_timeout.c +..\..\..\..\common\src\tx_thread_wait_abort.c +..\..\..\..\common\src\tx_time_get.c +..\..\..\..\common\src\tx_time_set.c +..\..\..\..\common\src\tx_timer_activate.c +..\..\..\..\common\src\tx_timer_change.c +..\..\..\..\common\src\tx_timer_create.c +..\..\..\..\common\src\tx_timer_deactivate.c +..\..\..\..\common\src\tx_timer_delete.c +..\..\..\..\common\src\tx_timer_expiration_process.c +..\..\..\..\common\src\tx_timer_info_get.c +..\..\..\..\common\src\tx_timer_initialize.c +..\..\..\..\common\src\tx_timer_performance_info_get.c +..\..\..\..\common\src\tx_timer_performance_system_info_get.c +..\..\..\..\common\src\tx_timer_system_activate.c +..\..\..\..\common\src\tx_timer_system_deactivate.c +..\..\..\..\common\src\tx_timer_thread_entry.c +..\..\..\..\common\src\tx_trace_buffer_full_notify.c +..\..\..\..\common\src\tx_trace_disable.c +..\..\..\..\common\src\tx_trace_enable.c +..\..\..\..\common\src\tx_trace_event_filter.c +..\..\..\..\common\src\tx_trace_event_unfilter.c +..\..\..\..\common\src\tx_trace_initialize.c +..\..\..\..\common\src\tx_trace_interrupt_control.c +..\..\..\..\common\src\tx_trace_isr_enter_insert.c +..\..\..\..\common\src\tx_trace_isr_exit_insert.c +..\..\..\..\common\src\tx_trace_object_register.c +..\..\..\..\common\src\tx_trace_object_unregister.c +..\..\..\..\common\src\tx_trace_user_event_insert.c +..\..\..\..\common\src\txe_block_allocate.c +..\..\..\..\common\src\txe_block_pool_create.c +..\..\..\..\common\src\txe_block_pool_delete.c +..\..\..\..\common\src\txe_block_pool_info_get.c +..\..\..\..\common\src\txe_block_pool_prioritize.c +..\..\..\..\common\src\txe_block_release.c +..\..\..\..\common\src\txe_byte_allocate.c +..\..\..\..\common\src\txe_byte_pool_create.c +..\..\..\..\common\src\txe_byte_pool_delete.c +..\..\..\..\common\src\txe_byte_pool_info_get.c +..\..\..\..\common\src\txe_byte_pool_prioritize.c +..\..\..\..\common\src\txe_byte_release.c +..\..\..\..\common\src\txe_event_flags_create.c +..\..\..\..\common\src\txe_event_flags_delete.c +..\..\..\..\common\src\txe_event_flags_get.c +..\..\..\..\common\src\txe_event_flags_info_get.c +..\..\..\..\common\src\txe_event_flags_set.c +..\..\..\..\common\src\txe_event_flags_set_notify.c +..\..\..\..\common\src\txe_mutex_create.c +..\..\..\..\common\src\txe_mutex_delete.c +..\..\..\..\common\src\txe_mutex_get.c +..\..\..\..\common\src\txe_mutex_info_get.c +..\..\..\..\common\src\txe_mutex_prioritize.c +..\..\..\..\common\src\txe_mutex_put.c +..\..\..\..\common\src\txe_queue_create.c +..\..\..\..\common\src\txe_queue_delete.c +..\..\..\..\common\src\txe_queue_flush.c +..\..\..\..\common\src\txe_queue_front_send.c +..\..\..\..\common\src\txe_queue_info_get.c +..\..\..\..\common\src\txe_queue_prioritize.c +..\..\..\..\common\src\txe_queue_receive.c +..\..\..\..\common\src\txe_queue_send.c +..\..\..\..\common\src\txe_queue_send_notify.c +..\..\..\..\common\src\txe_semaphore_ceiling_put.c +..\..\..\..\common\src\txe_semaphore_create.c +..\..\..\..\common\src\txe_semaphore_delete.c +..\..\..\..\common\src\txe_semaphore_get.c +..\..\..\..\common\src\txe_semaphore_info_get.c +..\..\..\..\common\src\txe_semaphore_prioritize.c +..\..\..\..\common\src\txe_semaphore_put.c +..\..\..\..\common\src\txe_semaphore_put_notify.c +..\..\..\..\common\src\txe_thread_create.c +..\..\..\..\common\src\txe_thread_delete.c +..\..\..\..\common\src\txe_thread_entry_exit_notify.c +..\..\..\..\common\src\txe_thread_info_get.c +..\..\..\..\common\src\txe_thread_preemption_change.c +..\..\..\..\common\src\txe_thread_priority_change.c +..\..\..\..\common\src\txe_thread_relinquish.c +..\..\..\..\common\src\txe_thread_reset.c +..\..\..\..\common\src\txe_thread_resume.c +..\..\..\..\common\src\txe_thread_suspend.c +..\..\..\..\common\src\txe_thread_terminate.c +..\..\..\..\common\src\txe_thread_time_slice_change.c +..\..\..\..\common\src\txe_thread_wait_abort.c +..\..\..\..\common\src\txe_timer_activate.c +..\..\..\..\common\src\txe_timer_change.c +..\..\..\..\common\src\txe_timer_create.c +..\..\..\..\common\src\txe_timer_deactivate.c +..\..\..\..\common\src\txe_timer_delete.c +..\..\..\..\common\src\txe_timer_info_get.c +..\..\..\..\ports_common_green\src\tx_el.c +..\..\..\..\ports_common_green\src\tx_ghs.c +..\..\..\..\ports_common_green\src\tx_ghse.c +..\..\..\..\ports_common_green\src\txr_block_allocate.c +..\..\..\..\ports_common_green\src\txr_block_pool_create.c +..\..\..\..\ports_common_green\src\txr_block_pool_delete.c +..\..\..\..\ports_common_green\src\txr_block_pool_info_get.c +..\..\..\..\ports_common_green\src\txr_block_pool_prioritize.c +..\..\..\..\ports_common_green\src\txr_block_release.c +..\..\..\..\ports_common_green\src\txr_byte_allocate.c +..\..\..\..\ports_common_green\src\txr_byte_pool_create.c +..\..\..\..\ports_common_green\src\txr_byte_pool_delete.c +..\..\..\..\ports_common_green\src\txr_byte_pool_info_get.c +..\..\..\..\ports_common_green\src\txr_byte_pool_prioritize.c +..\..\..\..\ports_common_green\src\txr_byte_release.c +..\..\..\..\ports_common_green\src\txr_event_flags_create.c +..\..\..\..\ports_common_green\src\txr_event_flags_delete.c +..\..\..\..\ports_common_green\src\txr_event_flags_get.c +..\..\..\..\ports_common_green\src\txr_event_flags_info_get.c +..\..\..\..\ports_common_green\src\txr_event_flags_set.c +..\..\..\..\ports_common_green\src\txr_event_flags_set_notify.c +..\..\..\..\ports_common_green\src\txr_ghs.c +..\..\..\..\ports_common_green\src\txr_mutex_create.c +..\..\..\..\ports_common_green\src\txr_mutex_delete.c +..\..\..\..\ports_common_green\src\txr_mutex_get.c +..\..\..\..\ports_common_green\src\txr_mutex_info_get.c +..\..\..\..\ports_common_green\src\txr_mutex_prioritize.c +..\..\..\..\ports_common_green\src\txr_mutex_put.c +..\..\..\..\ports_common_green\src\txr_queue_create.c +..\..\..\..\ports_common_green\src\txr_queue_delete.c +..\..\..\..\ports_common_green\src\txr_queue_flush.c +..\..\..\..\ports_common_green\src\txr_queue_front_send.c +..\..\..\..\ports_common_green\src\txr_queue_info_get.c +..\..\..\..\ports_common_green\src\txr_queue_prioritize.c +..\..\..\..\ports_common_green\src\txr_queue_receive.c +..\..\..\..\ports_common_green\src\txr_queue_send.c +..\..\..\..\ports_common_green\src\txr_queue_send_notify.c +..\..\..\..\ports_common_green\src\txr_semaphore_ceiling_put.c +..\..\..\..\ports_common_green\src\txr_semaphore_create.c +..\..\..\..\ports_common_green\src\txr_semaphore_delete.c +..\..\..\..\ports_common_green\src\txr_semaphore_get.c +..\..\..\..\ports_common_green\src\txr_semaphore_info_get.c +..\..\..\..\ports_common_green\src\txr_semaphore_prioritize.c +..\..\..\..\ports_common_green\src\txr_semaphore_put.c +..\..\..\..\ports_common_green\src\txr_semaphore_put_notify.c +..\..\..\..\ports_common_green\src\txr_thread_create.c +..\..\..\..\ports_common_green\src\txr_thread_delete.c +..\..\..\..\ports_common_green\src\txr_thread_entry_exit_notify.c +..\..\..\..\ports_common_green\src\txr_thread_info_get.c +..\..\..\..\ports_common_green\src\txr_thread_preemption_change.c +..\..\..\..\ports_common_green\src\txr_thread_priority_change.c +..\..\..\..\ports_common_green\src\txr_thread_reset.c +..\..\..\..\ports_common_green\src\txr_thread_resume.c +..\..\..\..\ports_common_green\src\txr_thread_suspend.c +..\..\..\..\ports_common_green\src\txr_thread_terminate.c +..\..\..\..\ports_common_green\src\txr_thread_time_slice_change.c +..\..\..\..\ports_common_green\src\txr_thread_wait_abort.c +..\..\..\..\ports_common_green\src\txr_timer_activate.c +..\..\..\..\ports_common_green\src\txr_timer_change.c +..\..\..\..\ports_common_green\src\txr_timer_create.c +..\..\..\..\ports_common_green\src\txr_timer_deactivate.c +..\..\..\..\ports_common_green\src\txr_timer_delete.c +..\..\..\..\ports_common_green\src\txr_timer_info_get.c diff --git a/ports/cortex_r7/green/inc/tx_port.h b/ports/cortex_r7/green/inc/tx_port.h new file mode 100644 index 00000000..6ed7fd94 --- /dev/null +++ b/ports/cortex_r7/green/inc/tx_port.h @@ -0,0 +1,404 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-R7/Green Hills */ +/* 6.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include +#include +#include "tx_ghs.h" + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define constants for Green Hills EventAnalyzer. */ + +/* Define the number of ticks per second. This informs the EventAnalyzer what the timestamps + represent. By default, this is set to 1,000,000 i.e., one tick every microsecond. */ + +#define TX_EL_TICKS_PER_SECOND 1000000 + +/* Define the method of how to get the upper and lower 32-bits of the time stamp. By default, simply + simulate the time-stamp source with a counter. */ + +#define read_tbu() _tx_el_time_base_upper +#define read_tbl() ++_tx_el_time_base_lower + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ + VOID *tx_thread_eh_globals; \ + int Errno; /* errno. */ \ + char *strtok_saved_pos; /* strtok() position. */ +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + +#if (__GHS_VERSION_NUMBER >= 500) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) \ + { \ + extern void __tx_cpp_exception_init(TX_THREAD *thread_ptr); \ + __tx_cpp_exception_init(thread_ptr); \ + } +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) \ + { \ + #pragma weak __cpp_exception_init \ + extern void __cpp_exception_init(void **); \ + static void (*const cpp_init_funcp)(void **) = __cpp_exception_init; \ + if (cpp_init_funcp) \ + __cpp_exception_init(&(thread_ptr -> tx_thread_eh_globals)); \ + } +#endif + +#if (__GHS_VERSION_NUMBER >= 500) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) \ + { \ + extern void __tx_cpp_exception_cleanup(TX_THREAD *thread_ptr); \ + __tx_cpp_exception_cleanup(thread_ptr); \ + } +#else +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) \ + { \ + #pragma weak __cpp_exception_cleanup \ + extern void __cpp_exception_cleanup(void **); \ + static void (*const cpp_cleanup_funcp)(void **) = \ + __cpp_exception_cleanup; \ + if (cpp_cleanup_funcp) \ + __cpp_exception_cleanup(&(thread_ptr -> tx_thread_eh_globals)); \ + } +#endif + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + b = __CLZ32(m); \ + b = 31 - b; + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#if defined(__THUMB) + +unsigned int _tx_thread_interrupt_disable(void); +void _tx_thread_interrupt_restore(unsigned int new_posture); + +#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); + +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; + +#if defined(__GHS_VERSION_NUMBER) && (__GHS_VERSION_NUMBER >= 350) + +/* Define ThreadX interrupt lockout and restore macros using + compiler built-in functions if using Green Hills ARM compiler + version 3.5 or later. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_DISABLE interrupt_save = __GETSR(); \ + __SETSR(interrupt_save | 0xC0); + +#define TX_RESTORE __SETSR(interrupt_save); +#else +#define TX_DISABLE interrupt_save = __GETSR(); \ + __SETSR(interrupt_save | 0x80); + +#define TX_RESTORE __SETSR(interrupt_save); +#endif + +#else + +/* Define ThreadX interrupt lockout and restore macros using + asm macros if using Green Hills ARM compiler earlier than + version 3.5. */ + +asm int disable_ints(void) +{ +% + MRS r0,CPSR +#ifdef TX_BEFORE_ARMV6 +#ifdef TX_ENABLE_FIQ_SUPPORT + ORR r1,r0,0xC0 +#else + ORR r1,r0,0x80 +#endif + MSR CPSR_c,r1 +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if +#else + CPSID i +#endif +#endif +%error +} + +asm void restore_ints(int a) +{ +%reg a + MSR CPSR_c,a +%mem a + LDR r0,a + MSR CPSR_c,r0 +%error +} + +#define TX_DISABLE interrupt_save = disable_ints(); + +#define TX_RESTORE restore_ints(interrupt_save); +#endif +#endif + + +/* Define VFP extension for the Cortex-R7. Each is assumed to be called in the context of the executing + thread. */ + +void tx_thread_vfp_enable(void); +void tx_thread_vfp_disable(void); + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R7/Green Hills Version 6.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + + + diff --git a/ports/cortex_r7/green/readme_threadx.txt b/ports/cortex_r7/green/readme_threadx.txt new file mode 100644 index 00000000..4fd097d4 --- /dev/null +++ b/ports/cortex_r7/green/readme_threadx.txt @@ -0,0 +1,527 @@ + Microsoft's Azure RTOS ThreadX for Cortex-R7 + + Using the Green Hills Software Tools + +1. Open the ThreadX Project Workspace + +In order to build the ThreadX library and the ThreadX demonstration first load +the Azure RTOS Workspace azure_rtos_workspace.gpj, which is located inside the +"example_build" directory. + + +2. Building the ThreadX run-time Library + +Building the ThreadX library is easy; simply select the MULTI project file +tx.gpj and then select the build button. You should now observe the +compilation and assembly of the ThreadX library. This project build produces +the ThreadX library file tx.a. + + +3. Demonstration System + +The ThreadX demonstration is designed to execute under the MULTI environment +on the Green Hills Cortex-R7 simulator. The instructions that follow describe +how to get the ThreadX evaluation running under the MULTI Cortex-R7 simulation +environment. + +Building the demonstration is easy; simply select the MULTI project file +sample_threadx.gpj. At this point, select the "Project Build" button and observe +the compilation, assembly, and linkage of the ThreadX demonstration application. + +After the demonstration is built, invoke the MULTI ARM simulator by selecting +the simulator connection from within the sample_threadx.con connection file. +Once connected to the simulator, select the "Debug" button. You should now +observe the main function of sample_threadx.c. + +At this point, you should setup a simulated timer interrupt for ThreadX +by entering "timer 9999 irq" in the "target" window of the debugger. + +You are now ready to execute the ThreadX demonstration system. Select +breakpoints and data watches to observe the execution of the sample_threadx.c +application. + + +4. EventAnalyzer Demonstration + +To build a demonstration system that also logs events for the MULTI EventAnalyzer, +perform the same steps as the regular demo, except build the ThreadX library with +txe.gpj file and use the sample_threadx_el.gpj build file to build the demonstration. +The resulting image will log all system events, which can then be displayed by the +MULTI EventAnalyzer. + + +5. System Initialization + +The system entry point using the Green Hills tools is at the label _start. +This is defined within the crt0.arm file supplied by Green Hills. In addition, +this is where all static and global preset C variable initialization +processing is called from. + +After the Green Hills startup function returns, ThreadX initialization is +called. The main initialization function is _tx_initialize_low_level and +is located in the file tx_initialize_low_level.arm. This function is responsible +for setting up various system data structures, interrupt vectors, and the +periodic timer interrupt source of ThreadX. + +In addition, _tx_initialize_low_level determines where the first available +RAM memory address is located. This address is supplied to tx_application_define. + +By default, the first available RAM memory address is assumed to start at the +beginning of the ThreadX section .free_mem. If changes are made to the +sample_threadx.ld file, the .free_mem section should remain the last allocated +section in the main RAM area. The starting address of this section is passed +to tx_application_define. + + +6. User defines + +The following defines and their associated action are as follows: + + Define Meaning + + TX_ENABLE_IRQ_NESTING If defined, this brings in special IRQ + interrupt nesting logic into the ThreadX + library. This define should be applied + to the entire ThreadX library. + + TX_ENABLE_FIQ_NESTING If defined, this brings in special FIQ + interrupt nesting logic into the ThreadX + library. This define should be applied + to the entire ThreadX library and the + define TX_ENABLE_FIQ_SUPPORT should also + be defined. + + TX_ENABLE_FIQ_SUPPORT If defined, this brings in FIQ context + save and restore logic necessary for + applications to call ThreadX services from + FIQ interrupt handlers. This define + should be applied to the entire ThreadX + library. + + + TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, + this define causes basic ThreadX error + checking to be disabled. Please see + Chapter 4 in the "ThreadX User Guide" + for more details. + + TX_ENABLE_EVENT_LOGGING This define enables event logging for any + or all of the ThreadX source code. If this + option is used anywhere, the tx_initialize_high_level.c + file must be compiled with it as well, since this + is where the event log is initialized. + + TX_NO_EVENT_INFO This is a sub-option for event logging. + If this is enabled, only basic information + is saved in the log. + + TX_ENABLE_EVENT_FILTERS This is also a sub-option for event-logging. + If this is enabled, run-time filtering logic + is added to the event logging code. + + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By + default, this value is set to 32 priority levels. + + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found + in tx_port.h. + + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default + value is port-specific and is found in tx_port.h. + + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined + in tx_port.h. + + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. + By default, this option is not defined. + + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. + By default, this option is not defined. + + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is + not defined. + + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. + By default, this option is not defined. + + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. + By default, this option is not defined. + + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. + By default, this option is not defined. + + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size + and improves performance. + + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is + not defined. + + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is + not defined. + + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option + is not defined. + + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is + not defined. + + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is + not defined. + + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is + not defined. + + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is + not defined. + + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is + not defined. + + + +7. Register Usage and Stack Frames + +The Green Hills compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) +are scratch registers for each function. All other registers used by a C +function must be preserved by the function. ThreadX takes advantage of this +in situations where a context switch happens as a result of making a ThreadX +service call (which is itself a C function). In such cases, the saved +context of a thread is only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 CPSR CPSR + 0x08 r0 (a1) r4 (v1) + 0x0C r1 (a2) r5 (v2) + 0x10 r2 (a3) r6 (v3) + 0x14 r3 (a4) r7 (v4) + 0x18 r4 (v1) r8 (v5) + 0x1C r5 (v2) r9 (v6) + 0x20 r6 (v3) r10 (v7) + 0x24 r7 (v4) r11 (fp) + 0x28 r8 (v5) r14 (lr) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) + 0x3C r14 (lr) + 0x40 PC + + +8. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make ThreadX run faster, you can change the tx.gpj project +to disable debug information and enable the desired optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined before tx_api.h is included. + + +9. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-R7 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +9.1 Vector Area + +The Cortex-R7 vectors start at address zero. The demonstration system reset.arm +file contains the reset section (which contains all the ARM vectors) and is +typically loaded at address zero. On actual hardware platforms, this section +might have to be copied to address 0. + +9.2 IRQ ISRs + +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested +IRQ interrupts. The following sub-sections define the IRQ capabilities. + + +9.2.1 Standard IRQ ISRs + +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +is the default IRQ handler defined in tx_initialize_low_level.arm: + + + .globl __tx_irq_handler + .globl __tx_irq_processing_return +__tx_irq_handler: + + /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return: + + /* At this point execution is still in the IRQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. Note + that IRQ interrupts are still disabled upon return from the context + save function. */ + + /* Application ISR call(s) go here! */ + + /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +9.2.2 Vectored IRQ ISRs + +The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified +by the particular implementation. The following is an example IRQ handler defined in +tx_initialize_low_level.arm: + + .globl __tx_irq_example_handler +__tx_irq_example_handler: + + /* Call context save to save system context. */ + + STMDB sp!, {r0-r3} # Save some scratch registers + MRS r0, SPSR # Pickup saved SPSR + SUB lr, lr, #4 # Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} # Store other scratch registers + BL _tx_thread_vectored_context_save # Call the vectored IRQ context save + + /* At this point execution is still in the IRQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. Note + that IRQ interrupts are still disabled upon return from the context + save function. */ + + /* Application ISR call goes here! */ + + /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +9.2.3 Nested IRQ Support + +By default, nested IRQ interrupt support is not enabled. To enable nested +IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING +defined. With this defined, two new IRQ interrupt management services are +available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. +These function should be called between the IRQ context save and restore +calls. + +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +by switching from IRQ mode to SYS mode and enabling IRQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.arm. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables nesting +by disabling IRQ interrupts and switching back to IRQ mode in preparation for +the IRQ context restore service. + +The following is an example of enabling IRQ nested interrupts in the +typical IRQ handler: + + .globl __tx_irq_handler + .globl __tx_irq_processing_return +__tx_irq_handler: + + /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return: + + /* Enable nested IRQ interrupts. NOTE: Since this service returns + with IRQ interrupts enabled, all IRQ interrupt sources must be + cleared prior to calling this service. */ + BL _tx_thread_irq_nesting_start + + /* Application ISR call(s) go here! */ + + /* Disable nested IRQ interrupts. The mode is switched back to + IRQ mode and IRQ interrupts are disable upon return. */ + BL _tx_thread_irq_nesting_end + + /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +9.3 FIQ Interrupts + +By default, Cortex-R7 FIQ interrupts are left completely enabled by ThreadX. +Of course, this means that the application is fully responsible for +saving/restoring any registers used in the FIQ ISR processing. In addition, +no ThreadX service calls are allowed from the default FIQ ISRs. The default +FIQ interrupt shell is located in tx_initialize_low_level.arm. + +9.3.1 Managed FIQ Interrupts + +Full ThreadX management of FIQ interrupts is provided if the ThreadX sources +are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built +this way, the FIQ interrupt handlers are very similar to the IRQ interrupt +handlers defined previously. The following is default FIQ handler +defined in tx_initialize_low_level.arm: + + + .globl __tx_fiq_handler + .globl __tx_fiq_processing_return +__tx_fiq_handler: + + /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: + + /* At this point execution is still in the FIQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. */ + + /* Application FIQ handlers can be called here! */ + + /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +9.3.1.1 Nested FIQ Support + +By default, nested FIQ interrupt support is not enabled. To enable nested +FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING +defined. With this defined, two new FIQ interrupt management services are +available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. +These function should be called between the FIQ context save and restore +calls. + +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +by switching from FIQ mode to SYS mode and enabling FIQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.arm. When nested FIQ interrupts are no longer +required, calling the _tx_thread_fiq_nesting_end service disables nesting by +disabling FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +context restore service. + +The following is an example of enabling FIQ nested interrupts in the +typical FIQ handler: + + + .globl __tx_fiq_handler + .globl __tx_fiq_processing_return +__tx_fiq_handler: + + /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: + + /* At this point execution is still in the FIQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. */ + + /* Enable nested FIQ interrupts. NOTE: Since this service returns + with FIQ interrupts enabled, all FIQ interrupt sources must be + cleared prior to calling this service. */ + BL _tx_thread_fiq_nesting_start + + /* Application FIQ handlers can be called here! */ + + /* Disable nested FIQ interrupts. The mode is switched back to + FIQ mode and FIQ interrupts are disable upon return. */ + BL _tx_thread_fiq_nesting_end + + /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + + +10. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional. However, all other +ThreadX services are operational without a periodic timer source. + +To add the timer interrupt processing, simply make a call to +_tx_timer_interrupt in the IRQ processing. An example of this can be +found in the file tx_initialize_low_level.arm. + + +11. Thumb/Cortex-R7 Mixed Mode + +By default, ThreadX is setup for running in Cortex-R7 32-bit mode. This is +also true for the demonstration system. It is possible to build any +ThreadX file and/or the application in Thumb mode. The only exception +to this is the file tx_thread_shell_entry.c. This file must always be +built in 32-bit mode. + + +12. VFP Support + +By default, VFP support is disabled for each thread. If saving the context of the VFP registers +is needed, the following API call must be made from the context of the application thread - before +the VFP usage: + +void tx_thread_vfp_enable(void); + +After this API is called in the application, VFP registers will be saved/restored for this thread if it +is preempted via an interrupt. All other suspension of the this thread will not require the VFP registers +to be saved/restored. + +To disable VFP register context saving, simply call the following API: + +void tx_thread_vfp_disable(void); + + +13. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +05/19/2020 Initial ThreadX version of Cortex-R7/Green Hills port. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_r7/green/src/tx_thread_context_restore.arm b/ports/cortex_r7/green/src/tx_thread_context_restore.arm new file mode 100644 index 00000000..96c4c91b --- /dev/null +++ b/ports/cortex_r7/green/src/tx_thread_context_restore.arm @@ -0,0 +1,258 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # Disable IRQ and FIQ interrupts +#else + DISABLE_INTS = 0x80 # Disable IRQ interrupts +#endif + SVC_MODE = (0x13 | DISABLE_INTS) # SVC mode + IRQ_MODE = (0x12 | DISABLE_INTS) # IRQ mode + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore Cortex-R7/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores the interrupt context if it is processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_restore(VOID) +{ */ + .globl _tx_thread_context_restore +_tx_thread_context_restore: + + /* Lockout interrupts. */ + +#ifdef TX_BEFORE_ARMV6 + MRS r3, CPSR # Pickup current CPSR + ORR r0, r3, DISABLE_INTS # Build interrupt disable value + MSR CPSR_c, r0 # Lockout interrupts +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if # Disable IRQ and FIQ interrupts +#else + CPSID i # Disable IRQ interrupts +#endif +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR exit function to indicate an ISR is complete. */ + + BL _tx_execution_isr_exit # Call the ISR exit function +#endif + + /* Determine if interrupts are nested. */ + /* if (--_tx_thread_system_state) + { */ + + LDR r3, =_tx_thread_system_state # Pickup address of system state var + LDR r2, [r3] # Pickup system state + SUB r2, r2, 1 # Decrement the counter + STR r2, [r3] # Store the counter + CMP r2, 0 # Was this the first interrupt? + BEQ __tx_thread_not_nested_restore # If so, not a nested restore + + /* Interrupts are nested. */ + + /* Just recover the saved registers and return to the point of + interrupt. */ + + LDMIA sp!, {r0, r10, r12, lr} # Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 # Put SPSR back + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOVS pc, lr # Return to point of interrupt + + /* } */ +__tx_thread_not_nested_restore: + + /* Determine if a thread was interrupted and no preemption is required. */ + /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) + || (_tx_thread_preempt_disable)) + { */ + + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup actual current thread pointer + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_idle_system_restore # Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable # Pickup preempt disable address + LDR r2, [r3] # Pickup actual preempt disable flag + CMP r2, 0 # Is it set? + BNE __tx_thread_no_preempt_restore # Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr # Pickup address of execute thread ptr + LDR r2, [r3] # Pickup actual execute thread pointer + CMP r0, r2 # Is the same thread highest priority? + BNE __tx_thread_preempt_restore # No, preemption needs to happen + + +__tx_thread_no_preempt_restore: + + /* Restore interrupted thread or ISR. */ + + /* Pickup the saved stack pointer. */ + /* tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; */ + + /* Recover the saved context and return to the point of interrupt. */ + + LDMIA sp!, {r0, r10, r12, lr} # Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 # Put SPSR back + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOVS pc, lr # Return to point of interrupt + + /* } + else + { */ +__tx_thread_preempt_restore: + + LDMIA sp!, {r3, r10, r12, lr} # Recover temporarily saved registers + MOV r1, lr # Save lr (point of interrupt) + MOV r2, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r2 # Enter SVC mode + STR r1, [sp, -4]! # Save point of interrupt + STMDB sp!, {r4-r12, lr} # Save upper half of registers + MOV r4, r3 # Save SPSR in r4 + MOV r2, IRQ_MODE # Build IRQ mode CPSR + MSR CPSR_c, r2 # Re-enter IRQ mode + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOV r5, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r5 # Enter SVC mode + STMDB sp!, {r0-r3} # Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup current thread pointer + +#ifdef __VFP__ + LDR r2, [r0, 144] # Pickup the VFP enabled flag + CMP r2, 0 # Is the VFP enabled? + BEQ _tx_skip_irq_vfp_save # No, skip VFP IRQ save + VMRS r2, FPSCR # Pickup the FPSCR + STR r2, [sp, -4]! # Save FPSCR + VSTMDB sp!, {D0-D15} # Save D0-D15 +_tx_skip_irq_vfp_save: +#endif + + MOV r3, 1 # Build interrupt stack type + STMDB sp!, {r3, r4} # Save interrupt stack type and SPSR + STR sp, [r0, 8] # Save stack pointer in thread control + /* # block */ + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r4, r0 # Save r0 + MOV r5, r1 # Save r1 + BL _tx_el_thread_preempted # Call thread preempted routine + MOV r0, r4 # Restore r0 + MOV r1, r5 # Restore r1 +#endif + + /* Save the remaining time-slice and disable it. */ + /* if (_tx_timer_time_slice) + { */ + + LDR r3, =_tx_timer_time_slice # Pickup time-slice variable address + LDR r2, [r3] # Pickup time-slice + CMP r2, 0 # Is it active? + BEQ __tx_thread_dont_save_ts # No, don't save it + + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + STR r2, [r0, 24] # Save thread's time-slice + MOV r2, 0 # Clear value + STR r2, [r3] # Disable global time-slice flag + + /* } */ +__tx_thread_dont_save_ts: + + + /* Clear the current task pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + MOV r0, 0 # NULL value + STR r0, [r1] # Clear current thread pointer + + /* Return to the scheduler. */ + /* _tx_thread_schedule(); */ + + B _tx_thread_schedule # Return to scheduler + /* } */ + +__tx_thread_idle_system_restore: + + /* Just return back to the scheduler! */ + + + MOV r3, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r3 # Lockout interrupts + B _tx_thread_schedule # Return to scheduler + + .type _tx_thread_context_restore,$function + .size _tx_thread_context_restore,.-_tx_thread_context_restore + +/* } */ + diff --git a/ports/cortex_r7/green/src/tx_thread_context_save.arm b/ports/cortex_r7/green/src/tx_thread_context_save.arm new file mode 100644 index 00000000..fd00e91f --- /dev/null +++ b/ports/cortex_r7/green/src/tx_thread_context_save.arm @@ -0,0 +1,207 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # IRQ & FIQ interrupts disabled +#else + DISABLE_INTS = 0x80 # IRQ interrupts disabled +#endif + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save Cortex-R7/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_save(VOID) +{ */ + .globl _tx_thread_context_save +_tx_thread_context_save: + + /* Upon entry to this routine, it is assumed that IRQ interrupts are locked + out, we are in IRQ mode, and all registers are intact. */ + + /* Check for a nested interrupt condition. */ + /* if (_tx_thread_system_state++) + { */ + + STMDB sp!, {r0-r3} # Save some working registers + +#ifdef TX_ENABLE_FIQ_SUPPORT +#ifdef TX_BEFORE_ARMV6 + MRS r0, CPSR # Pickup the CPSR + ORR r0, r0, DISABLE_INTS # Build disable interrupt CPSR + MSR CPSR_c, r0 # Disable interrupts +#else + CPSID if # Disable FIQ interrupts +#endif +#endif + + LDR r3, =_tx_thread_system_state # Pickup address of system state var + LDR r2, [r3] # Pickup system state + CMP r2, 0 # Is this the first interrupt? + BEQ __tx_thread_not_nested_save # Yes, not a nested context save + + /* Nested interrupt condition. */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + + /* Save the rest of the scratch registers on the stack and return to the + calling ISR. */ + + MRS r0, SPSR # Pickup saved SPSR + SUB lr, lr, 4 # Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} # Store other registers + + /* Return to the ISR. */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + B __tx_irq_processing_return # Continue IRQ processing + +__tx_thread_not_nested_save: + /* } */ + + /* Otherwise, not nested, check to see if a thread was running. */ + /* else if (_tx_thread_current_ptr) + { */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup current thread pointer + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_idle_system_save # If so, interrupt occurred in + /* # scheduling loop - nothing needs saving! */ + + /* Save minimal context of interrupted thread. */ + + MRS r2, SPSR # Pickup saved SPSR + SUB lr, lr, 4 # Adjust point of interrupt + STMDB sp!, {r2, r10, r12, lr} # Store other registers + + /* Save the current stack pointer in the thread's control block. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ + + /* Switch to the system stack. */ + /* sp = _tx_thread_system_stack_ptr; */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + B __tx_irq_processing_return # Continue IRQ processing + + /* } + else + { */ + +__tx_thread_idle_system_save: + + /* Interrupt occurred in the scheduling loop. */ + + /* Not much to do here, just adjust the stack pointer, and return to IRQ + processing. */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + ADD sp, sp, 16 # Recover saved registers + B __tx_irq_processing_return # Continue IRQ processing + + .type _tx_thread_context_save,$function + .size _tx_thread_context_save,.-_tx_thread_context_save + + /* } +} */ + diff --git a/ports/cortex_r7/green/src/tx_thread_fiq_context_restore.arm b/ports/cortex_r7/green/src/tx_thread_fiq_context_restore.arm new file mode 100644 index 00000000..2a425acc --- /dev/null +++ b/ports/cortex_r7/green/src/tx_thread_fiq_context_restore.arm @@ -0,0 +1,263 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + SVC_MODE = 0xD3 # SVC mode + FIQ_MODE = 0xD1 # FIQ mode +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # Disable IRQ and FIQ interrupts +#else + DISABLE_INTS = 0x80 # Disable IRQ interrupts +#endif + MODE_MASK = 0x1F # Mode mask + IRQ_MODE_BITS = 0x12 # IRQ mode bits + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_context_restore Cortex-R7/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores the fiq interrupt context when processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* FIQ ISR Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_fiq_context_restore(VOID) +{ */ + .globl _tx_thread_fiq_context_restore +_tx_thread_fiq_context_restore: + + /* Lockout interrupts. */ + +#ifdef TX_BEFORE_ARMV6 + MRS r3, CPSR # Pickup current CPSR + ORR r0, r3, DISABLE_INTS # Build interrupt disable value + MSR CPSR_c, r0 # Lockout interrupts +#else + CPSID if # Disable IRQ and FIQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR exit function to indicate an ISR is complete. */ + + BL _tx_execution_isr_exit # Call the ISR exit function +#endif + + /* Determine if interrupts are nested. */ + /* if (--_tx_thread_system_state) + { */ + + LDR r3, =_tx_thread_system_state # Pickup address of system state var + LDR r2, [r3] # Pickup system state + SUB r2, r2, 1 # Decrement the counter + STR r2, [r3] # Store the counter + CMP r2, 0 # Was this the first interrupt? + BEQ __tx_thread_fiq_not_nested_restore # If so, not a nested restore + + /* Interrupts are nested. */ + + /* Just recover the saved registers and return to the point of + interrupt. */ + + LDMIA sp!, {r0, r10, r12, lr} # Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 # Put SPSR back + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOVS pc, lr # Return to point of interrupt + + /* } */ +__tx_thread_fiq_not_nested_restore: + + /* Determine if a thread was interrupted and no preemption is required. */ + /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) + || (_tx_thread_preempt_disable)) + { */ + + LDR r1, [sp] # Pickup the saved SPSR + MOV r2, MODE_MASK # Build mask to isolate the interrupted mode + AND r1, r1, r2 # Isolate mode bits + CMP r1, IRQ_MODE_BITS # Was an interrupt taken in IRQ mode before we + /* # got to context save? */ + BEQ __tx_thread_fiq_no_preempt_restore # Yes, just go back to point of interrupt + + + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup actual current thread pointer + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_fiq_idle_system_restore # Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable # Pickup preempt disable address + LDR r2, [r3] # Pickup actual preempt disable flag + CMP r2, 0 # Is it set? + BNE __tx_thread_fiq_no_preempt_restore # Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr # Pickup address of execute thread ptr + LDR r2, [r3] # Pickup actual execute thread pointer + CMP r0, r2 # Is the same thread highest priority? + BNE __tx_thread_fiq_preempt_restore # No, preemption needs to happen + + +__tx_thread_fiq_no_preempt_restore: + + /* Restore interrupted thread or ISR. */ + + /* Pickup the saved stack pointer. */ + /* tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; */ + + /* Recover the saved context and return to the point of interrupt. */ + + LDMIA sp!, {r0, lr} # Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 # Put SPSR back + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOVS pc, lr # Return to point of interrupt + + /* } + else + { */ +__tx_thread_fiq_preempt_restore: + + LDMIA sp!, {r3, lr} # Recover temporarily saved registers + MOV r1, lr # Save lr (point of interrupt) + MOV r2, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r2 # Enter SVC mode + STR r1, [sp, -4]! # Save point of interrupt + STMDB sp!, {r4-r12, lr} # Save upper half of registers + MOV r4, r3 # Save SPSR in r4 + MOV r2, FIQ_MODE # Build FIQ mode CPSR + MSR CPSR_c, r2 # Re-enter FIQ mode + LDMIA sp!, {r0-r3} # Recover r0-r3 + MOV r5, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r5 # Enter SVC mode + STMDB sp!, {r0-r3} # Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup current thread pointer + +#ifdef __VFP__ + LDR r2, [r0, 144] # Pickup the VFP enabled flag + CMP r2, 0 # Is the VFP enabled? + BEQ _tx_skip_fiq_vfp_save # No, skip VFP IRQ save + VMRS r2, FPSCR # Pickup the FPSCR + STR r2, [sp, -4]! # Save FPSCR + VSTMDB sp!, {D0-D15} # Save D0-D15 +_tx_skip_fiq_vfp_save: +#endif + + MOV r3, 1 # Build interrupt stack type + STMDB sp!, {r3, r4} # Save interrupt stack type and SPSR + STR sp, [r0, 8] # Save stack pointer in thread control + /* # block */ + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV r4, r0 # Save r0 + MOV r5, r1 # Save r1 + BL _tx_el_thread_preempted # Call thread preempted routine + MOV r0, r4 # Restore r0 + MOV r1, r5 # Restore r1 +#endif + + /* Save the remaining time-slice and disable it. */ + /* if (_tx_timer_time_slice) + { */ + + LDR r3, =_tx_timer_time_slice # Pickup time-slice variable address + LDR r2, [r3] # Pickup time-slice + CMP r2, 0 # Is it active? + BEQ __tx_thread_fiq_dont_save_ts # No, don't save it + + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + STR r2, [r0, 24] # Save thread's time-slice + MOV r2, 0 # Clear value + STR r2, [r3] # Disable global time-slice flag + + /* } */ +__tx_thread_fiq_dont_save_ts: + + + /* Clear the current task pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + MOV r0, 0 # NULL value + STR r0, [r1] # Clear current thread pointer + + /* Return to the scheduler. */ + /* _tx_thread_schedule(); */ + + B _tx_thread_schedule # Return to scheduler + /* } */ + +__tx_thread_fiq_idle_system_restore: + + /* Just return back to the scheduler! */ + + ADD sp, sp, 24 # Recover FIQ stack space + MOV r3, SVC_MODE # Build SVC mode CPSR + MSR CPSR_c, r3 # Lockout interrupts + B _tx_thread_schedule # Return to scheduler + + .type _tx_thread_fiq_context_restore,$function + .size _tx_thread_fiq_context_restore,.-_tx_thread_fiq_context_restore + +/* } */ + diff --git a/ports/cortex_r7/green/src/tx_thread_fiq_context_save.arm b/ports/cortex_r7/green/src/tx_thread_fiq_context_save.arm new file mode 100644 index 00000000..4cee8b52 --- /dev/null +++ b/ports/cortex_r7/green/src/tx_thread_fiq_context_save.arm @@ -0,0 +1,197 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_context_save Cortex-R7/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_fiq_context_save(VOID) +{ */ + .globl _tx_thread_fiq_context_save +_tx_thread_fiq_context_save: + + /* Upon entry to this routine, it is assumed that IRQ interrupts are locked + out, we are in IRQ mode, and all registers are intact. */ + + /* Check for a nested interrupt condition. */ + /* if (_tx_thread_system_state++) + { */ + + STMDB sp!, {r0-r3} # Save some working registers + LDR r3, =_tx_thread_system_state # Pickup address of system state var + LDR r2, [r3] # Pickup system state + CMP r2, 0 # Is this the first interrupt? + BEQ __tx_thread_fiq_not_nested_save # Yes, not a nested context save + + /* Nested interrupt condition. */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + + /* Save the rest of the scratch registers on the stack and return to the + calling ISR. */ + + MRS r0, SPSR # Pickup saved SPSR + SUB lr, lr, 4 # Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} # Store other registers + + /* Return to the ISR. */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + B __tx_fiq_processing_return # Continue FIQ processing + +__tx_thread_fiq_not_nested_save: + /* } */ + + /* Otherwise, not nested, check to see if a thread was running. */ + /* else if (_tx_thread_current_ptr) + { */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup current thread pointer + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_fiq_idle_system_save # If so, interrupt occurred in + /* # scheduling loop - nothing needs saving! */ + + /* Save minimal context of interrupted thread. */ + + MRS r2, SPSR # Pickup saved SPSR + SUB lr, lr, 4 # Adjust point of interrupt + STMDB sp!, {r2, lr} # Store other registers, Note that we don't + /* # need to save sl and ip since FIQ has + # copies of these registers. Nested + # interrupt processing does need to save + # these registers. */ + + /* Save the current stack pointer in the thread's control block. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ + + /* Switch to the system stack. */ + /* sp = _tx_thread_system_stack_ptr; */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + B __tx_fiq_processing_return # Continue FIQ processing + + /* } + else + { */ + +__tx_thread_fiq_idle_system_save: + + /* Interrupt occurred in the scheduling loop. */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + /* Not much to do here, save the current SPSR and LR for possible + use in IRQ interrupted in idle system conditions, and return to + FIQ interrupt processing. */ + + MRS r0, SPSR # Pickup saved SPSR + SUB lr, lr, 4 # Adjust point of interrupt + STMDB sp!, {r0, lr} # Store other registers that will get used + /* # or stripped off the stack in context + # restore */ + B __tx_fiq_processing_return # Continue FIQ processing + + .type _tx_thread_fiq_context_save,$function + .size _tx_thread_fiq_context_save,.-_tx_thread_fiq_context_save + + /* } +} */ + diff --git a/ports/cortex_r7/green/src/tx_thread_fiq_nesting_end.arm b/ports/cortex_r7/green/src/tx_thread_fiq_nesting_end.arm new file mode 100644 index 00000000..3a300fd0 --- /dev/null +++ b/ports/cortex_r7/green/src/tx_thread_fiq_nesting_end.arm @@ -0,0 +1,109 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # Disable IRQ and FIQ interrupts +#else + DISABLE_INTS = 0x80 # Disable IRQ interrupts +#endif + MODE_MASK = 0x1F # Mode mask + FIQ_MODE_BITS = 0x11 # FIQ mode bits + SVC_MODE_BITS = 0x13 # SVC mode value */ + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_nesting_end Cortex-R7/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from FIQ mode after */ +/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +/* processing from system mode back to FIQ mode prior to the ISR */ +/* calling _tx_thread_fiq_context_restore. Note that this function */ +/* assumes the system stack pointer is in the same position after */ +/* nesting start function was called. */ +/* */ +/* This function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.arm). */ +/* */ +/* This function returns with FIQ interrupts disabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_fiq_nesting_end(VOID) +{ */ + .globl _tx_thread_fiq_nesting_end +_tx_thread_fiq_nesting_end: + MOV r3,lr # Save ISR return address + MRS r0, CPSR # Pickup the CPSR + ORR r0, r0, DISABLE_INTS # Build disable interrupt value + MSR CPSR_c, r0 # Disable interrupts + LDR lr, [sp] # Pickup saved lr + ADD sp, sp, 4 # Adjust stack pointer + BIC r0, r0, MODE_MASK # Clear mode bits + ORR r0, r0, FIQ_MODE_BITS # Build IRQ mode CPSR + MSR CPSR_c, r0 # Re-enter IRQ mode + MOV pc, r3 # Return to ISR + + .type _tx_thread_fiq_nesting_end,$function + .size _tx_thread_fiq_nesting_end,.-_tx_thread_fiq_nesting_end +/* } */ + diff --git a/ports/cortex_r7/green/src/tx_thread_fiq_nesting_start.arm b/ports/cortex_r7/green/src/tx_thread_fiq_nesting_start.arm new file mode 100644 index 00000000..95512d3b --- /dev/null +++ b/ports/cortex_r7/green/src/tx_thread_fiq_nesting_start.arm @@ -0,0 +1,103 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + + FIQ_DISABLE = 0x40 # FIQ disable bit + MODE_MASK = 0x1F # Mode mask + SYS_MODE_BITS = 0x1F # System mode bits + + + .text + .align 4 + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_nesting_start Cortex-R7/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from FIQ mode after */ +/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +/* processing to the system mode so nested FIQ interrupt processing */ +/* is possible (system mode has its own "lr" register). Note that */ +/* this function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.arm). */ +/* */ +/* This function returns with FIQ interrupts enabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_fiq_nesting_start(VOID) +{ */ + .globl _tx_thread_fiq_nesting_start +_tx_thread_fiq_nesting_start: + MOV r3,lr # Save ISR return address + MRS r0, CPSR # Pickup the CPSR + BIC r0, r0, MODE_MASK # Clear the mode bits + ORR r0, r0, SYS_MODE_BITS # Build system mode CPSR + MSR CPSR_c, r0 # Enter system mode + STR lr, [sp, -4]! # Push the system mode lr on the system mode stack + BIC r0, r0, FIQ_DISABLE # Build enable FIQ CPSR + MSR CPSR_c, r0 # Enter system mode + MOV pc, r3 # Return to ISR + + .type _tx_thread_fiq_nesting_start,$function + .size _tx_thread_fiq_nesting_start,.-_tx_thread_fiq_nesting_start +/* } */ + diff --git a/ports/cortex_r7/green/src/tx_thread_interrupt_control.arm b/ports/cortex_r7/green/src/tx_thread_interrupt_control.arm new file mode 100644 index 00000000..c881fd4d --- /dev/null +++ b/ports/cortex_r7/green/src/tx_thread_interrupt_control.arm @@ -0,0 +1,101 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" */ + + +#ifdef TX_ENABLE_FIQ_SUPPORT + INT_MASK = 0xC0 # Interrupt bit mask +#else + INT_MASK = 0x80 # Interrupt bit mask +#endif + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control Cortex-R7/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_control(UINT new_posture) +{ */ + .globl _tx_thread_interrupt_control +_tx_thread_interrupt_control: + + /* Pickup current interrupt lockout posture. */ + + MRS r3, CPSR # Pickup current CPSR + BIC r1, r3, INT_MASK # Clear interrupt lockout bits + ORR r1, r1, r0 # Or-in new interrupt lockout bits + + /* Apply the new interrupt posture. */ + + MSR CPSR_c, r1 # Setup new CPSR + AND r0, r3, INT_MASK # Return previous interrupt mask + RET # Return to caller + + .type _tx_thread_interrupt_control,$function + .size _tx_thread_interrupt_control,.-_tx_thread_interrupt_control +/* } */ + + + diff --git a/ports/cortex_r7/green/src/tx_thread_interrupt_disable.arm b/ports/cortex_r7/green/src/tx_thread_interrupt_disable.arm new file mode 100644 index 00000000..7507a10f --- /dev/null +++ b/ports/cortex_r7/green/src/tx_thread_interrupt_disable.arm @@ -0,0 +1,105 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" */ + + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # IRQ & FIQ interrupts disabled +#else + DISABLE_INTS = 0x80 # IRQ interrupts disabled +#endif + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_disable Cortex-R7/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for disabling interrupts */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_disable(void) +{ */ + .globl _tx_thread_interrupt_disable +_tx_thread_interrupt_disable: + + /* Pickup current interrupt lockout posture. */ + + MRS r0, CPSR # Pickup current CPSR + + /* Mask interrupts. */ + +#ifdef TX_BEFORE_ARMV6 + ORR r1, r0, DISABLE_INTS # Mask interrupts + MSR CPSR_c, r1 # Setup new CPSR +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if # Disable IRQ and FIQ +#else + CPSID i # Disable IRQ +#endif +#endif + + RET # Return previous CPSR value + + .type _tx_thread_interrupt_disable,$function + .size _tx_thread_interrupt_disable,.-_tx_thread_interrupt_disable +/* } */ + diff --git a/ports/cortex_r7/green/src/tx_thread_interrupt_restore.arm b/ports/cortex_r7/green/src/tx_thread_interrupt_restore.arm new file mode 100644 index 00000000..af6e872e --- /dev/null +++ b/ports/cortex_r7/green/src/tx_thread_interrupt_restore.arm @@ -0,0 +1,85 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" */ + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_restore Cortex-R7/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for restoring interrupts to the state */ +/* returned by a previous _tx_thread_interrupt_disable call. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_interrupt_restore(UINT new_posture) +{ */ + .globl _tx_thread_interrupt_restore +_tx_thread_interrupt_restore: + + /* Apply the new interrupt posture. */ + + MSR CPSR_c, r0 # Setup new CPSR + RET + + .type _tx_thread_interrupt_restore,$function + .size _tx_thread_interrupt_restore,.-_tx_thread_interrupt_restore +/* } */ + diff --git a/ports/cortex_r7/green/src/tx_thread_irq_nesting_end.arm b/ports/cortex_r7/green/src/tx_thread_irq_nesting_end.arm new file mode 100644 index 00000000..d628ef03 --- /dev/null +++ b/ports/cortex_r7/green/src/tx_thread_irq_nesting_end.arm @@ -0,0 +1,109 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # Disable IRQ and FIQ interrupts +#else + DISABLE_INTS = 0x80 # Disable IRQ interrupts +#endif + MODE_MASK = 0x1F # Mode mask + IRQ_MODE_BITS = 0x12 # IRQ mode bits + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_irq_nesting_end Cortex-R7/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from IRQ mode after */ +/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +/* processing from system mode back to IRQ mode prior to the ISR */ +/* calling _tx_thread_context_restore. Note that this function */ +/* assumes the system stack pointer is in the same position after */ +/* nesting start function was called. */ +/* */ +/* This function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.arm). */ +/* */ +/* This function returns with IRQ interrupts disabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_irq_nesting_end(VOID) +{ */ + .globl _tx_thread_irq_nesting_end +_tx_thread_irq_nesting_end: + MOV r3,lr # Save ISR return address + MRS r0, CPSR # Pickup the CPSR + ORR r0, r0, DISABLE_INTS # Build disable interrupt value + MSR CPSR_c, r0 # Disable interrupts + LDR lr, [sp] # Pickup saved lr + ADD sp, sp, 4 # Adjust stack pointer + BIC r0, r0, MODE_MASK # Clear mode bits + ORR r0, r0, IRQ_MODE_BITS # Build IRQ mode CPSR + MSR CPSR_c, r0 # Re-enter IRQ mode + MOV pc, r3 # Return to ISR + + .type _tx_thread_irq_nesting_end,$function + .size _tx_thread_irq_nesting_end,.-_tx_thread_irq_nesting_end + +/* } */ + diff --git a/ports/cortex_r7/green/src/tx_thread_irq_nesting_start.arm b/ports/cortex_r7/green/src/tx_thread_irq_nesting_start.arm new file mode 100644 index 00000000..8650b277 --- /dev/null +++ b/ports/cortex_r7/green/src/tx_thread_irq_nesting_start.arm @@ -0,0 +1,102 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + + IRQ_DISABLE = 0x80 # IRQ disable bit + MODE_MASK = 0x1F # Mode mask + SYS_MODE_BITS = 0x1F # System mode bits + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_irq_nesting_start Cortex-R7/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from IRQ mode after */ +/* _tx_thread_context_save has been called and switches the IRQ */ +/* processing to the system mode so nested IRQ interrupt processing */ +/* is possible (system mode has its own "lr" register). Note that */ +/* this function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.arm). */ +/* */ +/* This function returns with IRQ interrupts enabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_irq_nesting_start(VOID) +{ */ + .globl _tx_thread_irq_nesting_start +_tx_thread_irq_nesting_start: + MOV r3,lr # Save ISR return address + MRS r0, CPSR # Pickup the CPSR + BIC r0, r0, MODE_MASK # Clear the mode bits + ORR r0, r0, SYS_MODE_BITS # Build system mode CPSR + MSR CPSR_c, r0 # Enter system mode + STR lr, [sp, -4]! # Push the system mode lr on the system mode stack + BIC r0, r0, IRQ_DISABLE # Build enable IRQ CPSR + MSR CPSR_c, r0 # Enter system mode + MOV pc, r3 # Return to ISR + + .type _tx_thread_irq_nesting_start,$function + .size _tx_thread_irq_nesting_start,.-_tx_thread_irq_nesting_start +/* } */ + diff --git a/ports/cortex_r7/green/src/tx_thread_schedule.arm b/ports/cortex_r7/green/src/tx_thread_schedule.arm new file mode 100644 index 00000000..08f885b2 --- /dev/null +++ b/ports/cortex_r7/green/src/tx_thread_schedule.arm @@ -0,0 +1,252 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + ENABLE_INTS = 0xC0 # IRQ & FIQ Interrupts enabled mask +#else + ENABLE_INTS = 0x80 # IRQ Interrupts enabled mask +#endif + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule Cortex-R7/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* _tx_thread_context_restore Restore thread's context */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_schedule(VOID) +{ */ + .globl _tx_thread_schedule +_tx_thread_schedule: + + /* Enable interrupts. */ + +#ifdef TX_BEFORE_ARMV6 + MRS r2, CPSR # Pickup CPSR + BIC r0, r2, ENABLE_INTS # Clear the disable bit(s) + MSR CPSR_c, r0 # Enable interrupts +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSIE if # Enable IRQ and FIQ interrupts +#else + CPSIE i # Enable IRQ interrupts +#endif +#endif + + /* Wait for a thread to execute. */ + /* do + { */ + LDR r1, =_tx_thread_execute_ptr # Address of thread execute ptr + +__tx_thread_schedule_loop: + + LDR r0, [r1] # Pickup next thread to execute + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_schedule_loop # If so, keep looking for a thread + + /* } + while(_tx_thread_execute_ptr == TX_NULL); */ + + /* Yes! We have a thread to execute. Lockout interrupts and + transfer control to it. */ + +#ifdef TX_BEFORE_ARMV6 + MSR CPSR_c, r2 # Disable interrupts +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if # Disable IRQ and FIQ interrupts +#else + CPSID i # Disable IRQ interrupts +#endif +#endif + + /* Setup the current thread pointer. */ + /* _tx_thread_current_ptr = _tx_thread_execute_ptr; */ + +#ifdef TX_ENABLE_EVENT_LOGGING + MOV v1, r0 # Save temp register in non-volatile register + BL _tx_el_thread_running # Call event logging routine + MOV r0, v1 # Restore temp register +#endif + + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread + STR r0, [r1] # Setup current thread pointer + + /* Increment the run count for this thread. */ + /* _tx_thread_current_ptr -> tx_thread_run_count++; */ + + LDR r2, [r0, 4] # Pickup run counter + LDR r3, [r0, 24] # Pickup time-slice for this thread + ADD r2, r2, 1 # Increment thread run-counter + STR r2, [r0, 4] # Store the new run counter + + /* Setup time-slice, if present. */ + /* _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; */ + + LDR r2, =_tx_timer_time_slice # Pickup address of time slice + /* # variable */ + LDR sp, [r0, 8] # Switch stack pointers + STR r3, [r2] # Setup time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread entry function to indicate the thread is executing. */ + + MOV r5, r0 # Save r0 + BL _tx_execution_thread_enter # Call the thread execution enter function + MOV r0, r5 # Restore r0 +#endif + + /* Switch to the thread's stack. */ + /* sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; */ + + /* Determine if an interrupt frame or a synchronous task suspension frame + is present. */ + + LDMIA sp!, {r4, r5} # Pickup the stack type and saved CPSR + CMP r4, 0 # Check for synchronous context switch + BEQ _tx_solicited_return + MSR SPSR_cxsf, r5 # Setup SPSR for return +#ifdef __VFP__ + LDR r1, [r0, 144] # Pickup the VFP enabled flag + CMP r1, 0 # Is the VFP enabled? + BEQ _tx_skip_interrupt_vfp_restore # No, skip VFP interrupt restore + VLDMIA sp!, {D0-D15} # Recover D0-D15 + LDR r4, [sp], 4 # Pickup FPSCR + VMSR FPSCR, r4 # Restore FPSCR +_tx_skip_interrupt_vfp_restore: +#endif + LDMIA sp!, {r0-r12, lr, pc}^ # Return to point of thread interrupt + +_tx_solicited_return: +#ifdef __VFP__ + LDR r1, [r0, 144] # Pickup the VFP enabled flag + CMP r1, 0 # Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_restore # No, skip VFP solicited restore + VLDMIA sp!, {D8-D15} # Recover D8-D15 + LDR r4, [sp], 4 # Pickup FPSCR + VMSR FPSCR, r4 # Restore FPSCR +_tx_skip_solicited_vfp_restore: +#endif + MSR CPSR_cxsf, r5 # Recover CPSR + LDMIA sp!, {r4-r11, lr} # Return to thread synchronously + RET # Return to caller (Thumb safe) + + .type _tx_thread_schedule,$function + .size _tx_thread_schedule,.-_tx_thread_schedule + +#ifdef __VFP__ + .globl tx_thread_vfp_enable +tx_thread_vfp_enable: + MRS r2, CPSR # Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if # Disable IRQ and FIQ interrupts +#else + CPSID i # Disable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr # Build current thread pointer address + LDR r1, [r0] # Pickup current thread pointer + CMP r1, 0 # Check for NULL thread pointer + BEQ __tx_no_thread_to_enable # If NULL, skip VFP enable + MOV r0, 1 # Build enable value + STR r0, [r1, 144] # Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_enable: + MSR CPSR_cxsf, r2 # Recover CPSR + RET # Return to caller (Thumb safe) + + .type tx_thread_vfp_enable,$function + .size tx_thread_vfp_enable,.-tx_thread_vfp_enable + + + .globl tx_thread_vfp_disable +tx_thread_vfp_disable: + MRS r2, CPSR # Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if # Disable IRQ and FIQ interrupts +#else + CPSID i # Disable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr # Build current thread pointer address + LDR r1, [r0] # Pickup current thread pointer + CMP r1, 0 # Check for NULL thread pointer + BEQ __tx_no_thread_to_disable # If NULL, skip VFP disable + MOV r0, 0 # Build disable value + STR r0, [r1, 144] # Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_disable: + MSR CPSR_cxsf, r2 # Recover CPSR + RET # Return to caller (Thumb safe) + + .type tx_thread_vfp_disable,$function + .size tx_thread_vfp_disable,.-tx_thread_vfp_disable + +#endif + +/* } */ + + + diff --git a/ports/cortex_r7/green/src/tx_thread_stack_build.arm b/ports/cortex_r7/green/src/tx_thread_stack_build.arm new file mode 100644 index 00000000..d02abbe0 --- /dev/null +++ b/ports/cortex_r7/green/src/tx_thread_stack_build.arm @@ -0,0 +1,161 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" */ + + SVC_MODE = 0x13 # SVC mode +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSR_MASK = 0xDF # Mask initial CPSR, IRQ & FIQ ints enabled +#else + CPSR_MASK = 0x9F # Mask initial CPSR, IRQ ints enabled +#endif + + THUMB_BIT = 0x20 # Thumb-bit + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build Cortex-R7/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +{ */ + .globl _tx_thread_stack_build +_tx_thread_stack_build: + + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-R7 should look like the following after it is built: + + Stack Top: 1 Interrupt stack frame type + CPSR Initial value for CPSR + r0 (a1) Initial value for r0 + r1 (a2) Initial value for r1 + r2 (a3) Initial value for r2 + r3 (a4) Initial value for r3 + r4 (v1) Initial value for r4 + r5 (v2) Initial value for r5 + r6 (v3) Initial value for r6 + r7 (v4) Initial value for r7 + r8 (v5) Initial value for r8 + r9 (sb) Initial value for r9 + r10 (sl) Initial value for r10 + r11 (fp) Initial value for r11 + r12 (ip) Initial value for r12 + lr Initial value for lr + pc Initial value for pc + 0 For stack backtracing + + Stack Bottom: (higher memory address) */ + + LDR r2, [r0, 16] # Pickup end of stack area + BIC r2, r2, 7 # Ensure 8-byte alignment + SUB r2, r2, 76 # Allocate space for the stack frame + + /* Actually build the stack frame. */ + + MOV r3, 1 # Build interrupt stack type + STR r3, [r2] # Store stack type + MOV r3, 0 # Build initial register value + STR r3, [r2, 8] # Store initial r0 + STR r3, [r2, 12] # Store initial r1 + STR r3, [r2, 16] # Store initial r2 + STR r3, [r2, 20] # Store initial r3 + STR r3, [r2, 24] # Store initial r4 + STR r3, [r2, 28] # Store initial r5 + STR r3, [r2, 32] # Store initial r6 + STR r3, [r2, 36] # Store initial r7 + STR r3, [r2, 40] # Store initial r8 + STR r3, [r2, 44] # Store initial r9 + LDR r3, [r0, 12] # Pickup stack starting address + STR r3, [r2, 48] # Store initial r10 + MOV r3, 0 # Build initial register value + STR r3, [r2, 52] # Store initial r11 + STR r3, [r2, 56] # Store initial r12 + STR r3, [r2, 60] # Store initial lr + STR r1, [r2, 64] # Store initial pc + STR r3, [r2, 68] # 0 for back-trace + + MRS r3, CPSR # Pickup CPSR + BIC r3, r3, CPSR_MASK # Mask mode bits of CPSR + ORR r3, r3, SVC_MODE # Build CPSR, SVC mode, interrupts enabled + BIC r3, r3, #THUMB_BIT # Clear Thumb-bit by default + AND r1, r1, #1 # Determine if the entry function is in Thumb mode + CMP r1, 1 # Is the Thumb-bit set? + ORREQ r3, r3, #THUMB_BIT # Yes, set the Thumb-bit + STR r3, [r2, 4] # Store initial CPSR + + /* Setup stack pointer. */ + /* thread_ptr -> tx_thread_stack_ptr = r2; */ + + STR r2, [r0, 8] # Save stack pointer in thread's + /* # control block */ + RET # Return to caller + + .type _tx_thread_stack_build,$function + .size _tx_thread_stack_build,.-_tx_thread_stack_build +/* } */ + diff --git a/ports/cortex_r7/green/src/tx_thread_system_return.arm b/ports/cortex_r7/green/src/tx_thread_system_return.arm new file mode 100644 index 00000000..2ce606fa --- /dev/null +++ b/ports/cortex_r7/green/src/tx_thread_system_return.arm @@ -0,0 +1,166 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # IRQ & FIQ interrupts disabled +#else + DISABLE_INTS = 0x80 # IRQ interrupts disabled +#endif + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return Cortex-R7/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the ThreadX system. Only a */ +/* minimal context is saved since the compiler assumes temp registers */ +/* are going to get slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_system_return(VOID) +{ */ + .globl _tx_thread_system_return +_tx_thread_system_return: + + /* Save minimal context on the stack. */ + + MOV r0, 0 # Build a solicited stack type + MRS r1, CPSR # Pickup the CPSR + STMDB sp!, {r4-r11, lr} # Save minimal context + + LDR r4, =_tx_thread_current_ptr # Pickup address of current ptr + LDR r5, [r4] # Pickup current thread pointer + +#ifdef __VFP__ + LDR r1, [r5, 144] # Pickup the VFP enabled flag + CMP r1, 0 # Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_save # No, skip VFP solicited save + VMRS r1, FPSCR # Pickup the FPSCR + STR r1, [sp, -4]! # Save FPSCR + VSTMDB sp!, {D8-D15} # Save D8-D15 +_tx_skip_solicited_vfp_save: +#endif + + MOV r0, #0 # Build a solicited stack type + MRS r1, CPSR # Pickup the CPSR + STMDB sp!, {r0-r1} # Save type and CPSR + + /* Lockout interrupts. */ + +#ifdef TX_BEFORE_ARMV6 + ORR r2, r1, DISABLE_INTS # Build disable interrupt CPSR + MSR CPSR_c, r2 # Disable interrupts +#else +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if # Disable IRQ and FIQ interrupts +#else + CPSID i # Disable IRQ interrutps +#endif +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread exit function to indicate the thread is no longer executing. */ + + BL _tx_execution_thread_exit # Call the thread exit function +#endif + + MOV r3, r4 # Pickup address of current ptr + MOV r0, r5 # Pickup current thread pointer + LDR r2, =_tx_timer_time_slice # Pickup address of time slice + LDR r1, [r2] # Pickup current time slice + + /* Save current stack and switch to system stack. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; + sp = _tx_thread_system_stack_ptr; */ + + STR sp, [r0, 8] # Save thread stack pointer + + /* Determine if the time-slice is active. */ + /* if (_tx_timer_time_slice) + { */ + + MOV r4, 0 # Build clear value + CMP r1, 0 # Is a time-slice active? + BEQ __tx_thread_dont_save_ts # No, don't save the time-slice + + /* Save time-slice for the thread and clear the current time-slice. */ + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + STR r4, [r2, 0] # Clear time-slice + STR r1, [r0, 24] # Save current time-slice + + /* } */ +__tx_thread_dont_save_ts: + + /* Clear the current thread pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + STR r4, [r3] # Clear current thread pointer + B _tx_thread_schedule # Jump to scheduler! + + .type _tx_thread_system_return,$function + .size _tx_thread_system_return,.-_tx_thread_system_return +/* } */ + diff --git a/ports/cortex_r7/green/src/tx_thread_vectored_context_save.arm b/ports/cortex_r7/green/src/tx_thread_vectored_context_save.arm new file mode 100644 index 00000000..d6cae28a --- /dev/null +++ b/ports/cortex_r7/green/src/tx_thread_vectored_context_save.arm @@ -0,0 +1,196 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + DISABLE_INTS = 0xC0 # IRQ & FIQ interrupts disabled +#else + DISABLE_INTS = 0x80 # IRQ interrupts disabled +#endif + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_vectored_context_save Cortex-R7/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_vectored_context_save(VOID) +{ */ + .globl _tx_thread_vectored_context_save +_tx_thread_vectored_context_save: + + /* Upon entry to this routine, it is assumed that IRQ interrupts are locked + out, we are in IRQ mode, the minimal context is already saved, and the + lr register contains the return ISR address. */ + + /* Check for a nested interrupt condition. */ + /* if (_tx_thread_system_state++) + { */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#ifdef TX_BEFORE_ARMV6 + MRS r0, CPSR # Pickup the CPSR + ORR r0, r0, DISABLE_INTS # Build disable interrupt CPSR + MSR CPSR_c, r0 # Disable interrupts +#else + CPSID if # Disable IRQ and FIQ interrupts +#endif +#endif + LDR r3, =_tx_thread_system_state # Pickup address of system state var + LDR r2, [r3] # Pickup system state + CMP r2, 0 # Is this the first interrupt? + BEQ __tx_thread_not_nested_save # Yes, not a nested context save + + /* Nested interrupt condition. */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + + /* Note: Minimal context of interrupted thread is already saved. */ + + /* Return to the ISR. */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + MOV pc, lr # Return to caller + +__tx_thread_not_nested_save: + /* } */ + + /* Otherwise, not nested, check to see if a thread was running. */ + /* else if (_tx_thread_current_ptr) + { */ + + ADD r2, r2, 1 # Increment the interrupt counter + STR r2, [r3] # Store it back in the variable + LDR r1, =_tx_thread_current_ptr # Pickup address of current thread ptr + LDR r0, [r1] # Pickup current thread pointer + CMP r0, 0 # Is it NULL? + BEQ __tx_thread_idle_system_save # If so, interrupt occurred in + /* # scheduling loop - nothing needs saving! */ + + /* Note: Minimal context of interrupted thread is already saved. */ + + /* Save the current stack pointer in the thread's control block. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ + + /* Switch to the system stack. */ + /* sp = _tx_thread_system_stack_ptr; */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + MOV pc, lr # Return to caller + + /* } + else + { */ + +__tx_thread_idle_system_save: + + /* Interrupt occurred in the scheduling loop. */ + + /* Not much to do here, just adjust the stack pointer, and return to IRQ + processing. */ + + MOV r10, 0 # Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} # Save ISR lr + BL _tx_execution_isr_enter # Call the ISR enter function + POP {lr} # Recover ISR lr +#endif + + ADD sp, sp, 32 # Recover saved registers + MOV pc, lr # Return to caller + + .type _tx_thread_vectored_context_save,$function + .size _tx_thread_vectored_context_save,.-_tx_thread_vectored_context_save + + /* } +} */ + diff --git a/ports/cortex_r7/green/src/tx_timer_interrupt.arm b/ports/cortex_r7/green/src/tx_timer_interrupt.arm new file mode 100644 index 00000000..0e785832 --- /dev/null +++ b/ports/cortex_r7/green/src/tx_timer_interrupt.arm @@ -0,0 +1,241 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_timer.h" + #include "tx_thread.h" */ + + + .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt Cortex-R7/Green Hills */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Process timer expiration */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_timer_interrupt(VOID) +{ */ + .globl _tx_timer_interrupt +_tx_timer_interrupt: + + /* Upon entry to this routine, it is assumed that context save has already + been called, and therefore the compiler scratch registers are available + for use. */ + + /* Increment the system clock. */ + /* _tx_timer_system_clock++; */ + + LDR r1, =_tx_timer_system_clock # Pickup address of system clock + LDR r0, [r1] # Pickup system clock + ADD r0, r0, 1 # Increment system clock + STR r0, [r1] # Store new system clock + + /* Test for time-slice expiration. */ + /* if (_tx_timer_time_slice) + { */ + + LDR r3, =_tx_timer_time_slice # Pickup address of time-slice + LDR r2, [r3] # Pickup time-slice + CMP r2, 0 # Is it non-active? + BEQ __tx_timer_no_time_slice # Yes, skip time-slice processing + + /* Decrement the time_slice. */ + /* _tx_timer_time_slice--; */ + + SUB r2, r2, 1 # Decrement the time-slice + STR r2, [r3] # Store new time-slice value + + /* Check for expiration. */ + /* if (__tx_timer_time_slice == 0) */ + + CMP r2, 0 # Has it expired? + BNE __tx_timer_no_time_slice # No, skip expiration processing + + /* Set the time-slice expired flag. */ + /* _tx_timer_expired_time_slice = TX_TRUE; */ + + LDR r3,=_tx_timer_expired_time_slice # Pickup address of expired flag + MOV r0, 1 # Build expired value + STR r0, [r3] # Set time-slice expiration flag + + /* } */ + +__tx_timer_no_time_slice: + + /* Test for timer expiration. */ + /* if (*_tx_timer_current_ptr) + { */ + + LDR r1, =_tx_timer_current_ptr # Pickup current timer pointer addr + LDR r0, [r1] # Pickup current timer + LDR r2, [r0] # Pickup timer list entry + CMP r2, 0 # Is there anything in the list? + BEQ __tx_timer_no_timer # No, just increment the timer + + /* Set expiration flag. */ + /* _tx_timer_expired = TX_TRUE; */ + + LDR r3, =_tx_timer_expired # Pickup expiration flag address + MOV r2, 1 # Build expired value + STR r2, [r3] # Set expired flag + B __tx_timer_done # Finished timer processing + + /* } + else + { */ +__tx_timer_no_timer: + + /* No timer expired, increment the timer pointer. */ + /* _tx_timer_current_ptr++; */ + + ADD r0, r0, 4 # Move to next timer + + /* Check for wrap-around. */ + /* if (_tx_timer_current_ptr == _tx_timer_list_end) */ + + LDR r3, =_tx_timer_list_end # Pickup addr of timer list end + LDR r2, [r3] # Pickup list end + CMP r0, r2 # Are we at list end? + BNE __tx_timer_skip_wrap # No, skip wrap-around logic + + /* Wrap to beginning of list. */ + /* _tx_timer_current_ptr = _tx_timer_list_start; */ + + LDR r3, =_tx_timer_list_start # Pickup addr of timer list start + LDR r0, [r3] # Set current pointer to list start + +__tx_timer_skip_wrap: + + STR r0, [r1] # Store new current timer pointer + /* } */ + +__tx_timer_done: + + + /* See if anything has expired. */ + /* if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) + { */ + + LDR r3, =_tx_timer_expired_time_slice # Pickup addr of expired flag + LDR r2, [r3] # Pickup time-slice expired flag + CMP r2, 0 # Did a time-slice expire? + BNE __tx_something_expired # If non-zero, time-slice expired + LDR r1, =_tx_timer_expired # Pickup addr of other expired flag + LDR r0, [r1] # Pickup timer expired flag + CMP r0, 0 # Did a timer expire? + BEQ __tx_timer_nothing_expired # No, nothing expired + +__tx_something_expired: + + + STMDB sp!, {r0, lr} # Save the lr register on the stack + /* # and save r0 just to keep 8-byte alignment */ + + /* Did a timer expire? */ + /* if (_tx_timer_expired) + { */ + + LDR r1, =_tx_timer_expired # Pickup addr of expired flag + LDR r0, [r1] # Pickup timer expired flag + CMP r0, 0 # Check for timer expiration + BEQ __tx_timer_dont_activate # If not set, skip timer activation + + /* Process the timer expiration. */ + /* _tx_timer_expiration_process(); */ + BL _tx_timer_expiration_process # Call the timer expiration handling routine + + /* } */ +__tx_timer_dont_activate: + + /* Did time slice expire? */ + /* if (_tx_timer_expired_time_slice) + { */ + + LDR r3, =_tx_timer_expired_time_slice # Pickup addr of time-slice expired + LDR r2, [r3] # Pickup the actual flag + CMP r2, 0 # See if the flag is set + BEQ __tx_timer_not_ts_expiration # No, skip time-slice processing + + /* Time slice interrupted thread. */ + /* _tx_thread_time_slice(); */ + + BL _tx_thread_time_slice # Call time-slice processing + + /* } */ +__tx_timer_not_ts_expiration: + + + LDMIA sp!, {r0, lr} # Recover lr register (r0 is just there for + /* # the 8-byte stack alignment */ + + /* } */ + +__tx_timer_nothing_expired: + + RET # Return to caller + + .type _tx_timer_interrupt,$function + .size _tx_timer_interrupt,.-_tx_timer_interrupt +/* } */ + diff --git a/ports/linux/gnu/CMakeLists.txt b/ports/linux/gnu/CMakeLists.txt new file mode 100644 index 00000000..4b517940 --- /dev/null +++ b/ports/linux/gnu/CMakeLists.txt @@ -0,0 +1,22 @@ + +target_sources(${PROJECT_NAME} + PRIVATE + # {{BEGIN_TARGET_SOURCES}} + ${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_schedule.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.c + + # {{END_TARGET_SOURCES}} +) + +target_include_directories(${PROJECT_NAME} + PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/inc +) + +target_compile_definitions(${PROJECT_NAME} PUBLIC "-D_GNU_SOURCE -DTX_LINUX_DEBUG_ENABLE") \ No newline at end of file diff --git a/ports/linux/gnu/inc/tx_port.h b/ports/linux/gnu/inc/tx_port.h index 9422e100..feb7d8cc 100644 --- a/ports/linux/gnu/inc/tx_port.h +++ b/ports/linux/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Linux/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -510,7 +510,7 @@ VOID _tx_thread_interrupt_restore(UINT previous_posture); #define tx_linux_mutex_lock(p) pthread_mutex_lock(&p) #define tx_linux_mutex_unlock(p) pthread_mutex_unlock(&p) #define tx_linux_mutex_recursive_unlock(p) {\ - int _recursive_count = tx_linux_mutex_recursive_count;\ + int _recursive_count = (int)tx_linux_mutex_recursive_count;\ while(_recursive_count)\ {\ pthread_mutex_unlock(&p);\ @@ -539,7 +539,7 @@ VOID _tx_thread_interrupt_restore(UINT previous_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation * ThreadX Linux/gcc Version 6.0 *"; + "Copyright (c) Microsoft Corporation * ThreadX Linux/gcc Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/linux/gnu/readme_threadx.txt b/ports/linux/gnu/readme_threadx.txt index 5fdd6c3f..e3ac5cf6 100644 --- a/ports/linux/gnu/readme_threadx.txt +++ b/ports/linux/gnu/readme_threadx.txt @@ -145,7 +145,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX 6.0.1 version for Linux using GNU GCC tools. +09-30-2020 Initial ThreadX 6.1 version for Linux using GNU GCC tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/linux/gnu/src/tx_initialize_low_level.c b/ports/linux/gnu/src/tx_initialize_low_level.c index f8cd604b..dfac5b38 100644 --- a/ports/linux/gnu/src/tx_initialize_low_level.c +++ b/ports/linux/gnu/src/tx_initialize_low_level.c @@ -62,6 +62,9 @@ sem_t _tx_linux_timer_semaphore; sem_t _tx_linux_isr_semaphore; void *_tx_linux_timer_interrupt(void *p); +void _tx_linux_thread_resume_handler(int sig); +void _tx_linux_thread_suspend_handler(int sig); +void _tx_linux_thread_suspend(pthread_t thread_id); #ifdef TX_LINUX_DEBUG_ENABLE @@ -172,7 +175,7 @@ extern VOID *_tx_initialize_unused_memory; /* FUNCTION RELEASE */ /* */ /* _tx_initialize_low_level Linux/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -214,7 +217,7 @@ extern VOID *_tx_initialize_unused_memory; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_initialize_low_level(VOID) @@ -321,6 +324,8 @@ struct timespec ts; long timer_periodic_nsec; int err; + (VOID)p; + /* Calculate periodic timer. */ timer_periodic_nsec = 1000000000 / TX_TIMER_TICKS_PER_SECOND; nice(10); @@ -379,10 +384,13 @@ int err; /* Define functions for linux thread. */ void _tx_linux_thread_resume_handler(int sig) { + (VOID)sig; } void _tx_linux_thread_suspend_handler(int sig) { + (VOID)sig; + if(pthread_equal(pthread_self(), _tx_linux_timer_id)) tx_linux_sem_post_nolock(&_tx_linux_thread_timer_wait); else diff --git a/ports/linux/gnu/src/tx_thread_context_restore.c b/ports/linux/gnu/src/tx_thread_context_restore.c index ab24759e..7d1ff919 100644 --- a/ports/linux/gnu/src/tx_thread_context_restore.c +++ b/ports/linux/gnu/src/tx_thread_context_restore.c @@ -37,7 +37,7 @@ UINT _tx_linux_timer_waiting = 0; /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore Linux/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -75,7 +75,7 @@ UINT _tx_linux_timer_waiting = 0; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_context_restore(VOID) diff --git a/ports/linux/gnu/src/tx_thread_context_save.c b/ports/linux/gnu/src/tx_thread_context_save.c index d2b54b23..4dce0166 100644 --- a/ports/linux/gnu/src/tx_thread_context_save.c +++ b/ports/linux/gnu/src/tx_thread_context_save.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save Linux/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_context_save(VOID) diff --git a/ports/linux/gnu/src/tx_thread_interrupt_control.c b/ports/linux/gnu/src/tx_thread_interrupt_control.c index ea75e19f..17ae8902 100644 --- a/ports/linux/gnu/src/tx_thread_interrupt_control.c +++ b/ports/linux/gnu/src/tx_thread_interrupt_control.c @@ -53,7 +53,7 @@ VOID _tx_thread_interrupt_restore(UINT previous_posture) /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control Linux/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -87,7 +87,7 @@ VOID _tx_thread_interrupt_restore(UINT previous_posture) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/linux/gnu/src/tx_thread_schedule.c b/ports/linux/gnu/src/tx_thread_schedule.c index 7843a3ec..85fb3e5c 100644 --- a/ports/linux/gnu/src/tx_thread_schedule.c +++ b/ports/linux/gnu/src/tx_thread_schedule.c @@ -41,7 +41,7 @@ extern pthread_t _tx_linux_timer_id; /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Linux/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -78,7 +78,7 @@ extern pthread_t _tx_linux_timer_id; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_schedule(VOID) diff --git a/ports/linux/gnu/src/tx_thread_stack_build.c b/ports/linux/gnu/src/tx_thread_stack_build.c index b18ae2fb..b9a268d2 100644 --- a/ports/linux/gnu/src/tx_thread_stack_build.c +++ b/ports/linux/gnu/src/tx_thread_stack_build.c @@ -42,7 +42,7 @@ void *_tx_linux_thread_entry(void *ptr); /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build Linux/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -80,13 +80,15 @@ void *_tx_linux_thread_entry(void *ptr); /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) { struct sched_param sp; + (VOID)function_ptr; + /* Create the run semaphore for the thread. This will allow the scheduler control over when the thread actually runs. */ if(sem_init(&thread_ptr -> tx_thread_linux_thread_run_semaphore, 0, 0)) diff --git a/ports/linux/gnu/src/tx_thread_system_return.c b/ports/linux/gnu/src/tx_thread_system_return.c index 9ee68d0d..84553a3f 100644 --- a/ports/linux/gnu/src/tx_thread_system_return.c +++ b/ports/linux/gnu/src/tx_thread_system_return.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return Linux/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -78,7 +78,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_system_return(VOID) diff --git a/ports/linux/gnu/src/tx_timer_interrupt.c b/ports/linux/gnu/src/tx_timer_interrupt.c index 55207c14..7ab28c29 100644 --- a/ports/linux/gnu/src/tx_timer_interrupt.c +++ b/ports/linux/gnu/src/tx_timer_interrupt.c @@ -30,12 +30,13 @@ #include "tx_thread.h" +VOID _tx_timer_interrupt(VOID); /**************************************************************************/ /* */ /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt Linux/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -72,7 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_timer_interrupt(VOID) diff --git a/ports/risc-v32/iar/example_build/azure_rtos.eww b/ports/risc-v32/iar/example_build/azure_rtos.eww new file mode 100644 index 00000000..e59cd2b4 --- /dev/null +++ b/ports/risc-v32/iar/example_build/azure_rtos.eww @@ -0,0 +1,10 @@ + + + + $WS_DIR$\sample_threadx.ewp + + + $WS_DIR$\tx.ewp + + + diff --git a/ports/risc-v32/iar/example_build/sample_threadx.c b/ports/risc-v32/iar/example_build/sample_threadx.c new file mode 100644 index 00000000..525dcc5b --- /dev/null +++ b/ports/risc-v32/iar/example_build/sample_threadx.c @@ -0,0 +1,395 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. Please refer to Chapter 6 of the ThreadX User Guide for a complete + description of this demonstration. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define byte pool memory. */ + +UCHAR byte_pool_memory[DEMO_BYTE_POOL_SIZE]; + + +/* Define event buffer. */ + +#ifdef TX_ENABLE_EVENT_TRACE +UCHAR trace_buffer[0x10000]; +#endif + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Please refer to Chapter 6 of the ThreadX User Guide for a complete + description of this demonstration. */ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer; + + +#ifdef TX_ENABLE_EVENT_TRACE + tx_trace_enable(trace_buffer, sizeof(trace_buffer), 32); +#endif + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", byte_pool_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +#pragma vector = 3 +__interrupt void test() +{ + thread_6_and_7_entry(1); +} \ No newline at end of file diff --git a/ports/risc-v32/iar/example_build/sample_threadx.ewd b/ports/risc-v32/iar/example_build/sample_threadx.ewd new file mode 100644 index 00000000..cd439587 --- /dev/null +++ b/ports/risc-v32/iar/example_build/sample_threadx.ewd @@ -0,0 +1,848 @@ + + + 3 + + Debug + + RISCV + + 1 + + C-SPY + 3 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IJETRISCV + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + SIMRISCV + 3 + + 0 + 1 + 1 + + + + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + RISCV + + 0 + + C-SPY + 3 + + 1 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IJETRISCV + 2 + + 1 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + SIMRISCV + 3 + + 0 + 1 + 0 + + + + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/ports/risc-v32/iar/example_build/sample_threadx.ewp b/ports/risc-v32/iar/example_build/sample_threadx.ewp new file mode 100644 index 00000000..695f8deb --- /dev/null +++ b/ports/risc-v32/iar/example_build/sample_threadx.ewp @@ -0,0 +1,1800 @@ + + + 3 + + Debug + + RISCV + + 1 + + General + 3 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCRISCV + 3 + + 6 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IASMRISCV + 3 + + 0 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 3 + + 0 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 3 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 3 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + RISCV + + 0 + + General + 3 + + 1 + 1 + 0 + + + + + + + + + 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+/////////////////////////////////////////////////////////////////////////////// +// RISC-V ilink configuration file. +// + +define exported symbol _link_file_version_2 = 1; +define exported symbol _auto_vector_setup = 1; +define exported symbol _max_vector = 16; +define exported symbol _CLINT = 1; + +define memory mem with size = 4G; + +define region RAM_region32 = mem:[from 0x80000000 to 0x8003FFFF]; +define region ROM_region32 = mem:[from 0x20000000 to 0x3FFFFFFF]; + +initialize by copy { rw }; +do not initialize { section *.noinit }; + +define block CSTACK with alignment = 16, size = CSTACK_SIZE { }; +define block HEAP with alignment = 16, size = HEAP_SIZE { }; + +define block MVECTOR with alignment = 128 { ro section .mintvec }; + +if (isdefinedsymbol(_uses_clic)) +{ + define block MINTERRUPT with alignment = 128 { ro section .mtext }; + define block MINTERRUPTS { block MVECTOR, + block MINTERRUPT }; +} +else +{ + define block MINTERRUPTS with maximum size = 64k { ro section .mtext, + midway block MVECTOR }; +} + +define block RW_DATA with static base GPREL { rw data }; +keep { symbol __iar_cstart_init_gp }; // defined in cstartup.s + +"CSTARTUP32" : place at start of ROM_region32 { ro section .cstartup }; + +"ROM32":place in ROM_region32 { ro, + block MINTERRUPTS }; + +"RAM32":place in RAM_region32 { block RW_DATA, + block HEAP, + block CSTACK }; + +"RAM32":place in RAM_region32 { last section FREE_MEM}; diff --git a/ports/risc-v32/iar/example_build/tx.ewp b/ports/risc-v32/iar/example_build/tx.ewp new file mode 100644 index 00000000..2644c12b --- /dev/null +++ b/ports/risc-v32/iar/example_build/tx.ewp @@ -0,0 +1,2406 @@ + + + 3 + + Debug + + RISCV + + 1 + + General + 3 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCRISCV + 3 + + 6 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IASMRISCV + 3 + + 0 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\common\inc\tx_byte_pool.h + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_cleanup.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_initialize.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_performance_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_performance_system_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_prioritize.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_search.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_release.c + + + $PROJ_DIR$\..\..\..\..\common\inc\tx_event_flags.h + + + $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_cleanup.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_delete.c + + + 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$PROJ_DIR$\..\..\..\..\common\src\txe_timer_activate.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_change.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_deactivate.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_info_get.c + + diff --git a/ports/risc-v32/iar/inc/tx_port.h b/ports/risc-v32/iar/inc/tx_port.h new file mode 100644 index 00000000..f2db9c14 --- /dev/null +++ b/ports/risc-v32/iar/inc/tx_port.h @@ -0,0 +1,275 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h RISC-V32/IAR */ +/* 6.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Include prototypes for memset. */ + +#include +#include + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 512 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX RISC-V port. */ + +#define TX_INT_DISABLE 0x00000000 /* Disable interrupts value */ +#define TX_INT_ENABLE 0x00000008 /* Enable interrupt value */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0 + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifdef TX_DISABLE_INLINE + +unsigned int _tx_thread_interrupt_control(unsigned int new_posture); + +#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); +#define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA __istate_t interrupt_save; +#define TX_DISABLE {interrupt_save = __get_interrupt_state();__disable_interrupt();}; +#define TX_RESTORE {__set_interrupt_state(interrupt_save);}; + +#endif + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RISC-V32/IAR Version G6.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + +#endif + + + + diff --git a/ports/risc-v32/iar/readme_threadx.txt b/ports/risc-v32/iar/readme_threadx.txt new file mode 100644 index 00000000..5b915792 --- /dev/null +++ b/ports/risc-v32/iar/readme_threadx.txt @@ -0,0 +1,243 @@ + Microsoft's Azure RTOS ThreadX for RISC-V + + 32-bit Mode + + Using the IAR Tools + +1. Building the ThreadX run-time Library + +Building the ThreadX library is easy. First, open the Azure RTOS workspace +azure_rtos.eww. Next, make the tx.ewp project the "active project" in the +IAR Embedded Workbench and select the "Make" button. You should observe +assembly and compilation of a series of ThreadX source files. This +results in the ThreadX run-time library file tx.a, which is needed by +the application. + + +2. Demonstration System + +The ThreadX demonstration is designed to execute under the IAR +Windows-based RISC-V simulator. + +Building the demonstration is easy; simply make the sample_threadx.ewp project +the "active project" in the IAR Embedded Workbench and select the +"Make" button. + +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.out is a +binary file that can be downloaded and executed on IAR's RISC-V simulator. + + +3. System Initialization + +The entry point in ThreadX for the RISC-V using IAR tools is at label +__iar_program_start. This is defined within the IAR compiler's startup code. In +addition, this is where all static and global preset C variable +initialization processing takes place. + +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, and a periodic timer interrupt source. + +The _tx_initialize_low_level function inside of tx_initialize_low_level.s +also determines the first available address for use by the application, which +is supplied as the sole input parameter to your application definition function, +tx_application_define. To accomplish this, a section is created in +tx_initialize_low_level.s called FREE_MEM, which must be located after all +other RAM sections in memory. + + +4. Register Usage and Stack Frames + +The IAR RISC-V compiler assumes that registers t0-t6 and a0-a7 are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread +is only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 s11 (x27) s11 (x27) + 0x08 s10 (x26) s10 (x26) + 0x0C s9 (x25) s9 (x25) + 0x10 s8 (x24) s8 (x24) + 0x14 s7 (x23) s7 (x23) + 0x18 s6 (x22) s6 (x22) + 0x1C s5 (x21) s5 (x21) + 0x20 s4 (x20) s4 (x20) + 0x24 s3 (x19) s3 (x19) + 0x28 s2 (x18) s2 (x18) + 0x2C s1 (x9) s1 (x9) + 0x30 s0 (x8) s0 (x8) + 0x34 t6 (x31) ra (x1) + 0x38 t5 (x30) mstatus + 0x3C t4 (x29) fs0 + 0x40 t3 (x28) fs1 + 0x44 t2 (x7) fs2 + 0x48 t1 (x6) fs3 + 0x4C t0 (x5) fs4 + 0x50 a7 (x17) fs5 + 0x54 a6 (x16) fs6 + 0x58 a5 (x15) fs7 + 0x5C a4 (x14) fs8 + 0x60 a3 (x13) fs9 + 0x64 a2 (x12) fs10 + 0x68 a1 (x11) fs11 + 0x6C a0 (x10) fcsr + 0x70 ra (x1) + 0x74 reserved + 0x78 mepc +#if __iar_riscv_base_isa == rv32e + 0x7C ft0 + 0x80 ft1 + 0x84 ft2 + 0x88 ft3 + 0x8C ft4 + 0x90 ft5 + 0x94 ft6 + 0x98 ft7 + 0x9C fs0 + 0xA0 fs1 + 0xA4 fa0 + 0xA8 fa1 + 0xAC fa2 + 0xB0 fa3 + 0xB4 fa4 + 0xB8 fa5 + 0xBC fa6 + 0xC0 fa7 + 0xC4 fs2 + 0xC8 fs3 + 0xCC fs4 + 0xD0 fs5 + 0xD4 fs6 + 0xD8 fs7 + 0xDC fs8 + 0xE0 fs9 + 0xE4 fs10 + 0xE8 fs11 + 0xEC ft8 + 0xF0 ft9 + 0xF4 ft10 + 0xF8 ft11 + 0xFC fcsr +#endif + + +5. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make ThreadX run faster, you can change the project +options to disable debug information and enable the desired +compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined before tx_api.h is included. + + +6. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for RISC-V +targets.The ThreadX general exception handler sample is defined as follows, +where "*" represents the interrupt vector number: + + PUBLIC _sample_interrupt_handler + PUBLIC __minterrupt_00000* + EXTWEAK __require_minterrupt_vector_table +_sample_interrupt_handler: +__minterrupt_00000*: + REQUIRE __require_minterrupt_vector_table + + + /* Before calling _tx_thread_context_save, we have to allocate an interrupt + stack frame and save the current value of x1 (ra). */ +#if __iar_riscv_base_isa == rv32e + addi sp, sp, -260 ; Allocate space for all registers - with floating point enabled +#else + addi sp, sp, -128 ; Allocate space for all registers - without floating point enabled +#endif + sw x1, 0x70(sp) ; Store RA + call _tx_thread_context_save ; Call ThreadX context save + + /* Call your ISR processing here! */ + call your_ISR_processing + + /* Timer interrupt processing is done, jump to ThreadX context restore. */ + j _tx_thread_context_restore ; Jump to ThreadX context restore function. Note: this does not return! + + +Some additional conditions: + + 1. In the project settings Linker -> Extra Options, --auto_vector_setup should be defined. + 2. The project linker control file should have the following sections to include the vector table: + + define block MVECTOR with alignment = 128 { ro section .mintvec }; + + if (isdefinedsymbol(_uses_clic)) + { + define block MINTERRUPT with alignment = 128 { ro section .mtext }; + define block MINTERRUPTS { block MVECTOR, + block MINTERRUPT }; + } + else + { + define block MINTERRUPTS with maximum size = 64k { ro section .mtext, + midway block MVECTOR }; + } + +6.1 Sample Timer ISR + +The following sample timer ISR using vector 7 is defined in tx_initialize_low_level.s such that timer +functionality is available under IAR simulation: + + PUBLIC _tx_timer_interrupt_handler + PUBLIC __minterrupt_000007 + EXTWEAK __require_minterrupt_vector_table +_tx_timer_interrupt_handler: +__minterrupt_000007: + REQUIRE __require_minterrupt_vector_table + + + /* Before calling _tx_thread_context_save, we have to allocate an interrupt + stack frame and save the current value of x1 (ra). */ +#if __iar_riscv_base_isa == rv32e + addi sp, sp, -260 ; Allocate space for all registers - with floating point enabled +#else + addi sp, sp, -128 ; Allocate space for all registers - without floating point enabled +#endif + sw x1, 0x70(sp) ; Store RA + call _tx_thread_context_save ; Call ThreadX context save + + /* Call the ThreadX timer routine. */ + call _tx_timer_interrupt ; Call timer interrupt handler + + /* Timer interrupt processing is done, jump to ThreadX context restore. */ + j _tx_thread_context_restore ; Jump to ThreadX context restore function. Note: this does not return! + + +7. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +08/09/2020 Initial ThreadX version for RISC-V using IAR Tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/risc-v32/iar/src/tx_initialize_low_level.s b/ports/risc-v32/iar/src/tx_initialize_low_level.s new file mode 100644 index 00000000..79aa0fa3 --- /dev/null +++ b/ports/risc-v32/iar/src/tx_initialize_low_level.s @@ -0,0 +1,130 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_initialize.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_initialize_unused_memory + EXTERN _tx_thread_context_save + EXTERN _tx_thread_context_restore + EXTERN _tx_timer_interrupt + + RSEG FREE_MEM:DATA + PUBLIC __tx_free_memory_start +__tx_free_memory_start: + DS32 4 + + + SECTION `.text`:CODE:REORDER:NOROOT(2) + CODE +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level RISC-V32/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* Tom van Leeuwen, Technolution B.V. */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_initialize_low_level(VOID) +{ */ + PUBLIC _tx_initialize_low_level +_tx_initialize_low_level: + sw sp, _tx_thread_system_stack_ptr, t0 ; Save system stack pointer + + la t0, __tx_free_memory_start ; Pickup first free address + sw t0, _tx_initialize_unused_memory, t1 ; Save unused memory address + + ret + + + /* Define the actual timer interrupt/exception handler. */ + + PUBLIC _tx_timer_interrupt_handler + PUBLIC __minterrupt_000007 + EXTWEAK __require_minterrupt_vector_table +_tx_timer_interrupt_handler: +__minterrupt_000007: + REQUIRE __require_minterrupt_vector_table + + + /* Before calling _tx_thread_context_save, we have to allocate an interrupt + stack frame and save the current value of x1 (ra). */ +#if __iar_riscv_base_isa == rv32e + addi sp, sp, -260 ; Allocate space for all registers - with floating point enabled +#else + addi sp, sp, -128 ; Allocate space for all registers - without floating point enabled +#endif + sw x1, 0x70(sp) ; Store RA + call _tx_thread_context_save ; Call ThreadX context save + + /* Call the ThreadX timer routine. */ + call _tx_timer_interrupt ; Call timer interrupt handler + + /* Timer interrupt processing is done, jump to ThreadX context restore. */ + j _tx_thread_context_restore ; Jump to ThreadX context restore function. Note: this does not return! + + + END + \ No newline at end of file diff --git a/ports/risc-v32/iar/src/tx_thread_context_restore.s b/ports/risc-v32/iar/src/tx_thread_context_restore.s new file mode 100644 index 00000000..8a23b6e8 --- /dev/null +++ b/ports/risc-v32/iar/src/tx_thread_context_restore.s @@ -0,0 +1,344 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + EXTERN _tx_thread_execute_ptr + EXTERN _tx_thread_current_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_preempt_disable + EXTERN _tx_thread_schedule + EXTERN _tx_thread_system_state +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + EXTERN _tx_execution_isr_exit +#endif + + + SECTION `.text`:CODE:REORDER:NOROOT(2) + CODE +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore RISC-V32/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* Tom van Leeuwen, Technolution B.V. */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores the interrupt context if it is processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_restore(VOID) +{ */ + PUBLIC _tx_thread_context_restore +_tx_thread_context_restore: + + /* Lockout interrupts. */ + + csrci mstatus, 0x08 ; Disable interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + call _tx_execution_isr_exit ; Call the ISR execution exit function +#endif + + /* Determine if interrupts are nested. */ + /* if (--_tx_thread_system_state) + { */ + + la t0, _tx_thread_system_state ; Pickup addr of nested interrupt count + lw t1, 0(t0) ; Pickup nested interrupt count + addi t1, t1, -1 ; Decrement the nested interrupt counter + sw t1, 0(t0) ; Store new nested count + beqz t1, _tx_thread_not_nested_restore ; If 0, not nested restore + + /* Interrupts are nested. */ + + /* Just recover the saved registers and return to the point of + interrupt. */ + +#if __iar_riscv_base_isa == rv32e + + /* Recover floating point registers. */ + + flw f0, 0x7C(sp) ; Recover ft0 + flw f1, 0x80(sp) ; Recover ft1 + flw f2, 0x84(sp) ; Recover ft2 + flw f3, 0x88(sp) ; Recover ft3 + flw f4, 0x8C(sp) ; Recover ft4 + flw f5, 0x90(sp) ; Recover ft5 + flw f6, 0x94(sp) ; Recover ft6 + flw f7, 0x98(sp) ; Recover ft7 + flw f10,0xA4(sp) ; Recover fa0 + flw f11,0xA8(sp) ; Recover fa1 + flw f12,0xAC(sp) ; Recover fa2 + flw f13,0xB0(sp) ; Recover fa3 + flw f14,0xB4(sp) ; Recover fa4 + flw f15,0xB8(sp) ; Recover fa5 + flw f16,0xBC(sp) ; Recover fa6 + flw f17,0xC0(sp) ; Recover fa7 + flw f28,0xEC(sp) ; Recover ft8 + flw f29,0xF0(sp) ; Recover ft9 + flw f30,0xF4(sp) ; Recover ft10 + flw f31,0xF8(sp) ; Recover ft11 + lw t0, 0xFC(sp) ; Recover fcsr + csrw fcsr, t0 ; +#endif + + /* Recover standard registers. */ + + /* Restore registers, + Skip global pointer because that does not change + Also skip the saved registers since they have been restored by any function we called. + Except s0 since we use it ourselves. */ + + lw t0, 0x78(sp) ; Recover mepc + csrw mepc, t0 ; Setup mepc + li t0, 0x1880 ; Prepare MPIP + csrw mstatus, t0 ; Enable MPIP + + lw x1, 0x70(sp) ; Recover RA + lw x5, 0x4C(sp) ; Recover t0 + lw x6, 0x48(sp) ; Recover t1 + lw x7, 0x44(sp) ; Recover t2 + lw x8, 0x30(sp) ; Recover s0 + lw x10, 0x6C(sp) ; Recover a0 + lw x11, 0x68(sp) ; Recover a1 + lw x12, 0x64(sp) ; Recover a2 + lw x13, 0x60(sp) ; Recover a3 + lw x14, 0x5C(sp) ; Recover a4 + lw x15, 0x58(sp) ; Recover a5 + lw x16, 0x54(sp) ; Recover a6 + lw x17, 0x50(sp) ; Recover a7 + lw x28, 0x40(sp) ; Recover t3 + lw x29, 0x3C(sp) ; Recover t4 + lw x30, 0x38(sp) ; Recover t5 + lw x31, 0x34(sp) ; Recover t6 + +#if __iar_riscv_base_isa == rv32e + addi sp, sp, 260 ; Recover stack frame - with floating point enabled +#else + addi sp, sp, 128 ; Recover stack frame - without floating point enabled +#endif + mret ; Return to point of interrupt + + /* } */ +_tx_thread_not_nested_restore: + /* Determine if a thread was interrupted and no preemption is required. */ + /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) + || (_tx_thread_preempt_disable)) + { */ + + lw t1, _tx_thread_current_ptr ; Pickup current thread pointer + beqz t1, _tx_thread_idle_system_restore ; If NULL, idle system restore + + lw t2, _tx_thread_preempt_disable ; Pickup preempt disable flag + bgtz t2, _tx_thread_no_preempt_restore ; If set, restore interrupted thread + + lw t2, _tx_thread_execute_ptr ; Pickup thread execute pointer + bne t1, t2, _tx_thread_preempt_restore ; If higher-priority thread is ready, preempt + + +_tx_thread_no_preempt_restore: + /* Restore interrupted thread or ISR. */ + + /* Pickup the saved stack pointer. */ + /* SP = _tx_thread_current_ptr -> tx_thread_stack_ptr; */ + + lw sp, 8(t1) ; Switch back to thread's stack + +#if __iar_riscv_base_isa == rv32e + + /* Recover floating point registers. */ + + flw f0, 0x7C(sp) ; Recover ft0 + flw f1, 0x80(sp) ; Recover ft1 + flw f2, 0x84(sp) ; Recover ft2 + flw f3, 0x88(sp) ; Recover ft3 + flw f4, 0x8C(sp) ; Recover ft4 + flw f5, 0x90(sp) ; Recover ft5 + flw f6, 0x94(sp) ; Recover ft6 + flw f7, 0x98(sp) ; Recover ft7 + flw f10,0xA4(sp) ; Recover fa0 + flw f11,0xA8(sp) ; Recover fa1 + flw f12,0xAC(sp) ; Recover fa2 + flw f13,0xB0(sp) ; Recover fa3 + flw f14,0xB4(sp) ; Recover fa4 + flw f15,0xB8(sp) ; Recover fa5 + flw f16,0xBC(sp) ; Recover fa6 + flw f17,0xC0(sp) ; Recover fa7 + flw f28,0xEC(sp) ; Recover ft8 + flw f29,0xF0(sp) ; Recover ft9 + flw f30,0xF4(sp) ; Recover ft10 + flw f31,0xF8(sp) ; Recover ft11 + lw t0, 0xFC(sp) ; Recover fcsr + csrw fcsr, t0 ; +#endif + + /* Recover the saved context and return to the point of interrupt. */ + + /* Recover standard registers. */ + /* Restore registers, + Skip global pointer because that does not change */ + + lw t0, 0x78(sp) ; Recover mepc + csrw mepc, t0 ; Setup mepc + li t0, 0x1880 ; Prepare MPIP + csrw mstatus, t0 ; Enable MPIP + + lw x1, 0x70(sp) ; Recover RA + lw x5, 0x4C(sp) ; Recover t0 + lw x6, 0x48(sp) ; Recover t1 + lw x7, 0x44(sp) ; Recover t2 + lw x8, 0x30(sp) ; Recover s0 + lw x10, 0x6C(sp) ; Recover a0 + lw x11, 0x68(sp) ; Recover a1 + lw x12, 0x64(sp) ; Recover a2 + lw x13, 0x60(sp) ; Recover a3 + lw x14, 0x5C(sp) ; Recover a4 + lw x15, 0x58(sp) ; Recover a5 + lw x16, 0x54(sp) ; Recover a6 + lw x17, 0x50(sp) ; Recover a7 + lw x28, 0x40(sp) ; Recover t3 + lw x29, 0x3C(sp) ; Recover t4 + lw x30, 0x38(sp) ; Recover t5 + lw x31, 0x34(sp) ; Recover t6 + +#if __iar_riscv_base_isa == rv32e + addi sp, sp, 260 ; Recover stack frame - with floating point enabled +#else + addi sp, sp, 128 ; Recover stack frame - without floating point enabled +#endif + mret ; Return to point of interrupt + + /* } + else + { */ +_tx_thread_preempt_restore: + /* Instead of directly activating the thread again, ensure we save the + entire stack frame by saving the remaining registers. */ + + lw t0, 8(t1) ; Pickup thread's stack pointer + ori t3, x0, 1 ; Build interrupt stack type + sw t3, 0(t0) ; Store stack type + +#if __iar_riscv_base_isa == rv32e + + /* Store floating point preserved registers. */ + + fsw f8, 0x9C(t0) ; Store fs0 + fsw f9, 0xA0(t0) ; Store fs1 + fsw f18, 0xC4(t0) ; Store fs2 + fsw f19, 0xC8(t0) ; Store fs3 + fsw f20, 0xCC(t0) ; Store fs4 + fsw f21, 0xD0(t0) ; Store fs5 + fsw f22, 0xD4(t0) ; Store fs6 + fsw f23, 0xD8(t0) ; Store fs7 + fsw f24, 0xDC(t0) ; Store fs8 + fsw f25, 0xE0(t0) ; Store fs9 + fsw f26, 0xE4(t0) ; Store fs10 + fsw f27, 0xE8(t0) ; Store fs11 +#endif + + /* Store standard preserved registers. */ + + sw x9, 0x2C(t0) ; Store s1 + sw x18, 0x28(t0) ; Store s2 + sw x19, 0x24(t0) ; Store s3 + sw x20, 0x20(t0) ; Store s4 + sw x21, 0x1C(t0) ; Store s5 + sw x22, 0x18(t0) ; Store s6 + sw x23, 0x14(t0) ; Store s7 + sw x24, 0x10(t0) ; Store s8 + sw x25, 0x0C(t0) ; Store s9 + sw x26, 0x08(t0) ; Store s10 + sw x27, 0x04(t0) ; Store s11 + ; Note: s0 is already stored! + + /* Save the remaining time-slice and disable it. */ + /* if (_tx_timer_time_slice) + { */ + + la t0, _tx_timer_time_slice ; Pickup time slice variable address + lw t2, 0(t0) ; Pickup time slice + beqz t2, _tx_thread_dont_save_ts ; If 0, skip time slice processing + + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice + _tx_timer_time_slice = 0; */ + + sw t2, 24(t1) ; Save current time slice + sw x0, 0(t0) ; Clear global time slice + + + /* } */ +_tx_thread_dont_save_ts: + /* Clear the current task pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + /* Return to the scheduler. */ + /* _tx_thread_schedule(); */ + + sw x0, _tx_thread_current_ptr, t0 ; Clear current thread pointer*/ + /* } */ + +_tx_thread_idle_system_restore: + /* Just return back to the scheduler! */ + j _tx_thread_schedule ; Return to scheduler + +/* } */ + END diff --git a/ports/risc-v32/iar/src/tx_thread_context_save.s b/ports/risc-v32/iar/src/tx_thread_context_save.s new file mode 100644 index 00000000..e5eb92bf --- /dev/null +++ b/ports/risc-v32/iar/src/tx_thread_context_save.s @@ -0,0 +1,263 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_system_state + EXTERN _tx_thread_system_stack_ptr +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + EXTERN _tx_execution_isr_enter +#endif + + + SECTION `.text`:CODE:REORDER:NOROOT(2) + CODE +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save RISC-V32/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* Tom van Leeuwen, Technolution B.V. */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_save(VOID) +{ */ + PUBLIC _tx_thread_context_save +_tx_thread_context_save: + + /* Upon entry to this routine, it is assumed that interrupts are locked + out and the interrupt stack fame has been allocated and x1 (ra) has + been saved on the stack. */ + + sw x5, 0x4C(sp) ; First store t0 and t1 + sw x6, 0x48(sp) + + la x5, _tx_thread_system_state ; Pickup address of system state + lw x6, 0(x5) ; Pickup system state + + /* Check for a nested interrupt condition. */ + /* if (_tx_thread_system_state++) + { */ + beqz x6, _tx_thread_not_nested_save ; If 0, first interrupt condition + addi x6, x6, 1 ; Increment the interrupt counter + sw x6, 0(x5) ; Store the interrupt counter + + /* Nested interrupt condition. + Save the reset of the scratch registers on the stack and return to the + calling ISR. */ + + sw x7, 0x44(sp) ; Store t2 + sw x8, 0x30(sp) ; Store s0 + sw x10, 0x6C(sp) ; Store a0 + sw x11, 0x68(sp) ; Store a1 + sw x12, 0x64(sp) ; Store a2 + sw x13, 0x60(sp) ; Store a3 + sw x14, 0x5C(sp) ; Store a4 + sw x15, 0x58(sp) ; Store a5 + sw x16, 0x54(sp) ; Store a6 + sw x17, 0x50(sp) ; Store a7 + sw x28, 0x40(sp) ; Store t3 + sw x29, 0x3C(sp) ; Store t4 + sw x30, 0x38(sp) ; Store t5 + sw x31, 0x34(sp) ; Store t6 + csrr t0, mepc ; Load exception program counter + sw t0, 0x78(sp) ; Save it on the stack + +#if __iar_riscv_base_isa == rv32e + + /* Save floating point scratch registers. */ + + fsw f0, 0x7C(sp) ; Store ft0 + fsw f1, 0x80(sp) ; Store ft1 + fsw f2, 0x84(sp) ; Store ft2 + fsw f3, 0x88(sp) ; Store ft3 + fsw f4, 0x8C(sp) ; Store ft4 + fsw f5, 0x90(sp) ; Store ft5 + fsw f6, 0x94(sp) ; Store ft6 + fsw f7, 0x98(sp) ; Store ft7 + fsw f10,0xA4(sp) ; Store fa0 + fsw f11,0xA8(sp) ; Store fa1 + fsw f12,0xAC(sp) ; Store fa2 + fsw f13,0xB0(sp) ; Store fa3 + fsw f14,0xB4(sp) ; Store fa4 + fsw f15,0xB8(sp) ; Store fa5 + fsw f16,0xBC(sp) ; Store fa6 + fsw f17,0xC0(sp) ; Store fa7 + fsw f28,0xEC(sp) ; Store ft8 + fsw f29,0xF0(sp) ; Store ft9 + fsw f30,0xF4(sp) ; Store ft10 + fsw f31,0xF8(sp) ; Store ft11 + csrr t0, fcsr + sw t0, 0xFC(sp) ; Store fcsr +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + call _tx_execution_isr_enter ; Call the ISR execution enter function +#endif + + ret ; Return to calling ISR + +_tx_thread_not_nested_save: + /* } */ + + /* Otherwise, not nested, check to see if a thread was running. */ + /* else if (_tx_thread_current_ptr) + { */ + addi x6, x6, 1 ; Increment the interrupt counter + sw x6, 0(x5) ; Store the interrupt counter + + /* Not nested: Find the user thread that was running and load our SP */ + + lw x5, _tx_thread_current_ptr ; Pickup current thread pointer + beqz x5, _tx_thread_idle_system_save ; If NULL, idle system was interrupted + + /* Save the standard scratch registers. */ + + sw x7, 0x44(sp) ; Store t2 + sw x8, 0x30(sp) ; Store s0 + sw x10, 0x6C(sp) ; Store a0 + sw x11, 0x68(sp) ; Store a1 + sw x12, 0x64(sp) ; Store a2 + sw x13, 0x60(sp) ; Store a3 + sw x14, 0x5C(sp) ; Store a4 + sw x15, 0x58(sp) ; Store a5 + sw x16, 0x54(sp) ; Store a6 + sw x17, 0x50(sp) ; Store a7 + sw x28, 0x40(sp) ; Store t3 + sw x29, 0x3C(sp) ; Store t4 + sw x30, 0x38(sp) ; Store t5 + sw x31, 0x34(sp) ; Store t6 + + csrr t0, mepc ; Load exception program counter + sw t0, 0x78(sp) ; Save it on the stack + +#if __iar_riscv_base_isa == rv32e + + /* Save floating point scratch registers. */ + + fsw f0, 0x7C(sp) ; Store ft0 + fsw f1, 0x80(sp) ; Store ft1 + fsw f2, 0x84(sp) ; Store ft2 + fsw f3, 0x88(sp) ; Store ft3 + fsw f4, 0x8C(sp) ; Store ft4 + fsw f5, 0x90(sp) ; Store ft5 + fsw f6, 0x94(sp) ; Store ft6 + fsw f7, 0x98(sp) ; Store ft7 + fsw f10,0xA4(sp) ; Store fa0 + fsw f11,0xA8(sp) ; Store fa1 + fsw f12,0xAC(sp) ; Store fa2 + fsw f13,0xB0(sp) ; Store fa3 + fsw f14,0xB4(sp) ; Store fa4 + fsw f15,0xB8(sp) ; Store fa5 + fsw f16,0xBC(sp) ; Store fa6 + fsw f17,0xC0(sp) ; Store fa7 + fsw f28,0xEC(sp) ; Store ft8 + fsw f29,0xF0(sp) ; Store ft9 + fsw f30,0xF4(sp) ; Store ft10 + fsw f31,0xF8(sp) ; Store ft11 + csrr t0, fcsr + sw t0, 0xFC(sp) ; Store fcsr +#endif + + /* Save the current stack pointer in the thread's control block. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ + + /* Switch to the system stack. */ + /* sp = _tx_thread_system_stack_ptr; */ + + lw t1, _tx_thread_current_ptr ; Pickup current thread pointer + sw sp, 8(t1) ; Save stack pointer*/ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + /* _tx_execution_isr_enter is called with thread stack pointer */ + call _tx_execution_isr_enter ; Call the ISR execution enter function +#endif + + + lw sp, _tx_thread_system_stack_ptr ; Switch to system stack + ret ; Return to calling ISR + + /* } + else + { */ + +_tx_thread_idle_system_save: + + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + call _tx_execution_isr_enter ; Call the ISR execution enter function +#endif + + /* Interrupt occurred in the scheduling loop. */ + + /* } +} */ +#if __iar_riscv_base_isa == rv32e + addi sp, sp, 260 ; Recover stack frame - with floating point enabled +#else + addi sp, sp, 128 ; Recover the reserved stack space +#endif + ret ; Return to calling ISR + + END + \ No newline at end of file diff --git a/ports/risc-v32/iar/src/tx_thread_interrupt_control.s b/ports/risc-v32/iar/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..a6ac2989 --- /dev/null +++ b/ports/risc-v32/iar/src/tx_thread_interrupt_control.s @@ -0,0 +1,94 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" */ + +RETURN_MASK DEFINE 0x0000000F +SET_SR_MASK DEFINE 0xFFFFFFF0 + + SECTION `.text`:CODE:REORDER:NOROOT(2) + CODE +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control RISC-V32/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* Tom van Leeuwen, Technolution B.V. */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_control(UINT new_posture) +{ */ + PUBLIC _tx_thread_interrupt_control +_tx_thread_interrupt_control: + /* Pickup current interrupt lockout posture. */ + + csrr t0, mstatus + mv t1, t0 ; Save original mstatus for return + + /* Apply the new interrupt posture. */ + + li t2, SET_SR_MASK ; Build set SR mask + and t0, t0, t2 ; Isolate interrupt lockout bits + or t0, t0, a0 ; Put new lockout bits in + csrw mstatus, t0 + andi a0, t1, RETURN_MASK ; Return original mstatus. + ret +/* } */ + END + \ No newline at end of file diff --git a/ports/risc-v32/iar/src/tx_thread_schedule.s b/ports/risc-v32/iar/src/tx_thread_schedule.s new file mode 100644 index 00000000..72102533 --- /dev/null +++ b/ports/risc-v32/iar/src/tx_thread_schedule.s @@ -0,0 +1,274 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + + EXTERN _tx_thread_execute_ptr + EXTERN _tx_thread_current_ptr + EXTERN _tx_timer_time_slice +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + EXTERN _tx_execution_thread_enter +#endif + + + SECTION `.text`:CODE:REORDER:NOROOT(2) + CODE +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule RISC-V32/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* Tom van Leeuwen, Technolution B.V. */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* _tx_thread_context_restore Restore thread's context */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_schedule(VOID) +{ */ + PUBLIC _tx_thread_schedule +_tx_thread_schedule: + + /* Enable interrupts. */ + csrsi mstatus, 0x08 ; Enable interrupts + + /* Wait for a thread to execute. */ + /* do + { */ + + la t0, _tx_thread_execute_ptr ; Pickup address of execute ptr +_tx_thread_schedule_loop: + lw t1, 0(t0) ; Pickup next thread to execute + beqz t1, _tx_thread_schedule_loop ; If NULL, wait for thread to execute + + /* } + while(_tx_thread_execute_ptr == TX_NULL); */ + + /* Yes! We have a thread to execute. Lockout interrupts and + transfer control to it. */ + csrci mstatus, 0x08 ; Lockout interrupts + + /* Setup the current thread pointer. */ + /* _tx_thread_current_ptr = _tx_thread_execute_ptr; */ + + la t0, _tx_thread_current_ptr ; Pickup current thread pointer address + sw t1, 0(t0) ; Set current thread pointer + + /* Increment the run count for this thread. */ + /* _tx_thread_current_ptr -> tx_thread_run_count++; */ + + lw t2, 4(t1) ; Pickup run count + lw t3, 24(t1) ; Pickup time slice value + addi t2, t2, 1 ; Increment run count + sw t2, 4(t1) ; Store new run count + + /* Setup time-slice, if present. */ + /* _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; */ + + la t2, _tx_timer_time_slice ; Pickup time-slice variable address + + /* Switch to the thread's stack. */ + /* SP = _tx_thread_execute_ptr -> tx_thread_stack_ptr; */ + + lw sp, 8(t1) ; Switch to thread's stack + sw t3, 0(t2) ; Store new time-slice*/ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + call _tx_execution_thread_enter ; Call the thread execution enter function +#endif + + /* Determine if an interrupt frame or a synchronous task suspension frame + is present. */ + + lw t2, 0(sp) ; Pickup stack type + beqz t2, _tx_thread_synch_return ; If 0, solicited thread return + + /* Determine if floating point registers need to be recovered. */ + +#if __iar_riscv_base_isa == rv32e + flw f0, 0x7C(sp) ; Recover ft0 + flw f1, 0x80(sp) ; Recover ft1 + flw f2, 0x84(sp) ; Recover ft2 + flw f3, 0x88(sp) ; Recover ft3 + flw f4, 0x8C(sp) ; Recover ft4 + flw f5, 0x90(sp) ; Recover ft5 + flw f6, 0x94(sp) ; Recover ft6 + flw f7, 0x98(sp) ; Recover ft7 + flw f8, 0x9C(sp) ; Recover fs0 + flw f9, 0xA0(sp) ; Recover fs1 + flw f10,0xA4(sp) ; Recover fa0 + flw f11,0xA8(sp) ; Recover fa1 + flw f12,0xAC(sp) ; Recover fa2 + flw f13,0xB0(sp) ; Recover fa3 + flw f14,0xB4(sp) ; Recover fa4 + flw f15,0xB8(sp) ; Recover fa5 + flw f16,0xBC(sp) ; Recover fa6 + flw f17,0xC0(sp) ; Recover fa7 + flw f18,0xC4(sp) ; Recover fs2 + flw f19,0xC8(sp) ; Recover fs3 + flw f20,0xCC(sp) ; Recover fs4 + flw f21,0xD0(sp) ; Recover fs5 + flw f22,0xD4(sp) ; Recover fs6 + flw f23,0xD8(sp) ; Recover fs7 + flw f24,0xDC(sp) ; Recover fs8 + flw f25,0xE0(sp) ; Recover fs9 + flw f26,0xE4(sp) ; Recover fs10 + flw f27,0xE8(sp) ; Recover fs11 + flw f28,0xEC(sp) ; Recover ft8 + flw f29,0xF0(sp) ; Recover ft9 + flw f30,0xF4(sp) ; Recover ft10 + flw f31,0xF8(sp) ; Recover ft11 + lw t0, 0xFC(sp) ; Recover fcsr + csrw fcsr, t0 ; +#endif + + /* Recover standard registers. */ + + lw t0, 0x78(sp) ; Recover mepc + csrw mepc, t0 ; Store mepc + li t0, 0x1880 ; Prepare MPIP + csrw mstatus, t0 ; Enable MPIP + + lw x1, 0x70(sp) ; Recover RA + lw x5, 0x4C(sp) ; Recover t0 + lw x6, 0x48(sp) ; Recover t1 + lw x7, 0x44(sp) ; Recover t2 + lw x8, 0x30(sp) ; Recover s0 + lw x9, 0x2C(sp) ; Recover s1 + lw x10, 0x6C(sp) ; Recover a0 + lw x11, 0x68(sp) ; Recover a1 + lw x12, 0x64(sp) ; Recover a2 + lw x13, 0x60(sp) ; Recover a3 + lw x14, 0x5C(sp) ; Recover a4 + lw x15, 0x58(sp) ; Recover a5 + lw x16, 0x54(sp) ; Recover a6 + lw x17, 0x50(sp) ; Recover a7 + lw x18, 0x28(sp) ; Recover s2 + lw x19, 0x24(sp) ; Recover s3 + lw x20, 0x20(sp) ; Recover s4 + lw x21, 0x1C(sp) ; Recover s5 + lw x22, 0x18(sp) ; Recover s6 + lw x23, 0x14(sp) ; Recover s7 + lw x24, 0x10(sp) ; Recover s8 + lw x25, 0x0C(sp) ; Recover s9 + lw x26, 0x08(sp) ; Recover s10 + lw x27, 0x04(sp) ; Recover s11 + lw x28, 0x40(sp) ; Recover t3 + lw x29, 0x3C(sp) ; Recover t4 + lw x30, 0x38(sp) ; Recover t5 + lw x31, 0x34(sp) ; Recover t6 + +#if __iar_riscv_base_isa == rv32e + addi sp, sp, 260 ; Recover stack frame - with floating point registers +#else + addi sp, sp, 128 ; Recover stack frame - without floating point registers +#endif + mret ; Return to point of interrupt + +_tx_thread_synch_return: + +#if __iar_riscv_base_isa == rv32e + flw f8, 0x3C(sp) ; Recover fs0 + flw f9, 0x40(sp) ; Recover fs1 + flw f18,0x44(sp) ; Recover fs2 + flw f19,0x48(sp) ; Recover fs3 + flw f20,0x4C(sp) ; Recover fs4 + flw f21,0x50(sp) ; Recover fs5 + flw f22,0x54(sp) ; Recover fs6 + flw f23,0x58(sp) ; Recover fs7 + flw f24,0x5C(sp) ; Recover fs8 + flw f25,0x60(sp) ; Recover fs9 + flw f26,0x64(sp) ; Recover fs10 + flw f27,0x68(sp) ; Recover fs11 + lw t0, 0x6C(sp) ; Recover fcsr + csrw fcsr, t0 ; +#endif + + /* Recover standard preserved registers. */ + /* Recover standard registers. */ + + lw x1, 0x34(sp) ; Recover RA + lw x8, 0x30(sp) ; Recover s0 + lw x9, 0x2C(sp) ; Recover s1 + lw x18, 0x28(sp) ; Recover s2 + lw x19, 0x24(sp) ; Recover s3 + lw x20, 0x20(sp) ; Recover s4 + lw x21, 0x1C(sp) ; Recover s5 + lw x22, 0x18(sp) ; Recover s6 + lw x23, 0x14(sp) ; Recover s7 + lw x24, 0x10(sp) ; Recover s8 + lw x25, 0x0C(sp) ; Recover s9 + lw x26, 0x08(sp) ; Recover s10 + lw x27, 0x04(sp) ; Recover s11 + lw t0, 0x38(sp) ; Recover mstatus + csrw mstatus, t0 ; Store mstatus, enables interrupt +#if __iar_riscv_base_isa == rv32e + addi sp, sp, 116 ; Recover stack frame +#else + addi sp, sp, 64 ; Recover stack frame +#endif + ret ; Return to thread + +/* } */ + END + diff --git a/ports/risc-v32/iar/src/tx_thread_stack_build.s b/ports/risc-v32/iar/src/tx_thread_stack_build.s new file mode 100644 index 00000000..ff07e7b4 --- /dev/null +++ b/ports/risc-v32/iar/src/tx_thread_stack_build.s @@ -0,0 +1,240 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" */ + + SECTION `.text`:CODE:REORDER:NOROOT(2) + CODE +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build RISC-V32/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* Tom van Leeuwen, Technolution B.V. */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +{ */ + PUBLIC _tx_thread_stack_build +_tx_thread_stack_build: + + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the RISC-V RV32 should look like the following after it is built: + + Stack Top: 1 (00) Interrupt stack frame type + x27 (04) Initial s11 + x26 (08) Initial s10 + x25 (12) Initial s9 + x24 (16) Initial s8 + x23 (20) Initial s7 + x22 (24) Initial s6 + x21 (28) Initial s5 + x20 (32) Initial s4 + x19 (36) Initial s3 + x18 (40) Initial s2 + x9 (44) Initial s1 + x8 (48) Initial s0 + x31 (52) Initial t6 + x30 (56) Initial t5 + x29 (60) Initial t4 + x28 (64) Initial t3 + x7 (68) Initial t2 + x6 (72) Initial t1 + x5 (76) Initial t0 + x17 (80) Initial a7 + x16 (84) Initial a6 + x15 (88) Initial a5 + x14 (92) Initial a4 + x13 (96) Initial a3 + x12 (100) Initial a2 + x11 (104) Initial a1 + x10 (108) Initial a0 + x1 (112) Initial ra + mepc (120) Initial mepc +If floating point support: + f0 (124) Inital ft0 + f1 (128) Inital ft1 + f2 (132) Inital ft2 + f3 (136) Inital ft3 + f4 (140) Inital ft4 + f5 (144) Inital ft5 + f6 (148) Inital ft6 + f7 (152) Inital ft7 + f8 (156) Inital fs0 + f9 (160) Inital fs1 + f10 (164) Inital fa0 + f11 (168) Inital fa1 + f12 (172) Inital fa2 + f13 (176) Inital fa3 + f14 (180) Inital fa4 + f15 (184) Inital fa5 + f16 (188) Inital fa6 + f17 (192) Inital fa7 + f18 (196) Inital fs2 + f19 (200) Inital fs3 + f20 (204) Inital fs4 + f21 (208) Inital fs5 + f22 (212) Inital fs6 + f23 (216) Inital fs7 + f24 (220) Inital fs8 + f25 (224) Inital fs9 + f26 (228) Inital fs10 + f27 (232) Inital fs11 + f28 (236) Inital ft8 + f29 (240) Inital ft9 + f30 (244) Inital ft10 + f31 (248) Inital ft11 + fscr (252) Inital fscr + + Stack Bottom: (higher memory address) */ + + lw t0, 16(a0) ; Pickup end of stack area + li t1, ~15 ; Build 16-byte alignment mask + and t0, t0, t1 ; Make sure 16-byte alignment + + /* Actually build the stack frame. */ + +#if __iar_riscv_base_isa == rv32e + addi t0, t0, -260 +#else + addi t0, t0, -128 ; Allocate space for the stack frame +#endif + li t1, 1 ; Build stack type + sw t1, 0(t0) ; Place stack type on the top + sw x0, 4(t0) ; Initial s11 + sw x0, 8(t0) ; Initial s10 + sw x0, 12(t0) ; Initial s9 + sw x0, 16(t0) ; Initial s8 + sw x0, 20(t0) ; Initial s7 + sw x0, 24(t0) ; Initial s6 + sw x0, 28(t0) ; Initial s5 + sw x0, 32(t0) ; Initial s4 + sw x0, 36(t0) ; Initial s3 + sw x0, 40(t0) ; Initial s2 + sw x0, 44(t0) ; Initial s1 + sw x0, 48(t0) ; Initial s0 + sw x0, 52(t0) ; Initial t6 + sw x0, 56(t0) ; Initial t5 + sw x0, 60(t0) ; Initial t4 + sw x0, 64(t0) ; Initial t3 + sw x0, 68(t0) ; Initial t2 + sw x0, 72(t0) ; Initial t1 + sw x0, 76(t0) ; Initial t0 + sw x0, 80(t0) ; Initial a7 + sw x0, 84(t0) ; Initial a6 + sw x0, 88(t0) ; Initial a5 + sw x0, 92(t0) ; Initial a4 + sw x0, 96(t0) ; Initial a3 + sw x0, 100(t0) ; Initial a2 + sw x0, 104(t0) ; Initial a1 + sw x0, 108(t0) ; Initial a0 + sw x0, 112(t0) ; Initial ra + sw a1, 120(t0) ; Initial mepc +#if __iar_riscv_base_isa == rv32e + sw x0, 124(t0) ; Inital ft0 + sw x0, 128(t0) ; Inital ft1 + sw x0, 132(t0) ; Inital ft2 + sw x0, 136(t0) ; Inital ft3 + sw x0, 140(t0) ; Inital ft4 + sw x0, 144(t0) ; Inital ft5 + sw x0, 148(t0) ; Inital ft6 + sw x0, 152(t0) ; Inital ft7 + sw x0, 156(t0) ; Inital fs0 + sw x0, 160(t0) ; Inital fs1 + sw x0, 164(t0) ; Inital fa0 + sw x0, 168(t0) ; Inital fa1 + sw x0, 172(t0) ; Inital fa2 + sw x0, 176(t0) ; Inital fa3 + sw x0, 180(t0) ; Inital fa4 + sw x0, 184(t0) ; Inital fa5 + sw x0, 188(t0) ; Inital fa6 + sw x0, 192(t0) ; Inital fa7 + sw x0, 196(t0) ; Inital fs2 + sw x0, 200(t0) ; Inital fs3 + sw x0, 204(t0) ; Inital fs4 + sw x0, 208(t0) ; Inital fs5 + sw x0, 212(t0) ; Inital fs6 + sw x0, 216(t0) ; Inital fs7 + sw x0, 220(t0) ; Inital fs8 + sw x0, 224(t0) ; Inital fs9 + sw x0, 228(t0) ; Inital fs10 + sw x0, 232(t0) ; Inital fs11 + sw x0, 236(t0) ; Inital ft8 + sw x0, 240(t0) ; Inital ft9 + sw x0, 244(t0) ; Inital ft10 + sw x0, 248(t0) ; Inital ft11 + csrr a1, fcsr ; Read fcsr and use it for initial value for each thread + sw a1, 252(t0) ; Initial fscr + sw x0, 256(t0) ; Reserved word (0) +#else + sw x0, 124(t0) ; Reserved word (0) +#endif + + /* Setup stack pointer. */ + /* thread_ptr -> tx_thread_stack_ptr = t0; */ + + sw t0, 8(a0) ; Save stack pointer in thread's + ret ; control block and return +/* } */ + END + diff --git a/ports/risc-v32/iar/src/tx_thread_system_return.s b/ports/risc-v32/iar/src/tx_thread_system_return.s new file mode 100644 index 00000000..21724f5a --- /dev/null +++ b/ports/risc-v32/iar/src/tx_thread_system_return.s @@ -0,0 +1,184 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_thread.h" + #include "tx_timer.h" */ + + EXTERN _tx_thread_execute_ptr + EXTERN _tx_thread_current_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_thread_schedule +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + EXTERN _tx_execution_thread_exit +#endif + + SECTION `.text`:CODE:REORDER:NOROOT(2) + CODE +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return RISC-V32/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* Tom van Leeuwen, Technolution B.V. */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the system. Only a minimal context */ +/* is saved since the compiler assumes temp registers are going to get */ +/* slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_system_return(VOID) +{ */ + PUBLIC _tx_thread_system_return +_tx_thread_system_return: + + /* Save minimal context on the stack. */ + +#if __iar_riscv_base_isa == rv32e + addi sp, sp, -116 ; Allocate space on the stack - with floating point enabled +#else + addi sp, sp, -64 ; Allocate space on the stack - without floating point enabled +#endif + +#if __iar_riscv_base_isa == rv32e + + /* Store floating point preserved registers. */ + + fsw f8, 0x3C(sp) ; Store fs0 + fsw f9, 0x40(sp) ; Store fs1 + fsw f18, 0x44(sp) ; Store fs2 + fsw f19, 0x48(sp) ; Store fs3 + fsw f20, 0x4C(sp) ; Store fs4 + fsw f21, 0x50(sp) ; Store fs5 + fsw f22, 0x54(sp) ; Store fs6 + fsw f23, 0x58(sp) ; Store fs7 + fsw f24, 0x5C(sp) ; Store fs8 + fsw f25, 0x60(sp) ; Store fs9 + fsw f26, 0x64(sp) ; Store fs10 + fsw f27, 0x68(sp) ; Store fs11 + csrr t0, fcsr + sw t0, 0x6C(sp) ; Store fcsr +#endif + + + sw x0, 0(sp) ; Solicited stack type + sw x1, 0x34(sp) ; Save RA + sw x8, 0x30(sp) ; Save s0 + sw x9, 0x2C(sp) ; Save s1 + sw x18, 0x28(sp) ; Save s2 + sw x19, 0x24(sp) ; Save s3 + sw x20, 0x20(sp) ; Save s4 + sw x21, 0x1C(sp) ; Save s5 + sw x22, 0x18(sp) ; Save s6 + sw x23, 0x14(sp) ; Save s7 + sw x24, 0x10(sp) ; Save s8 + sw x25, 0x0C(sp) ; Save s9 + sw x26, 0x08(sp) ; Save s10 + sw x27, 0x04(sp) ; Save s11 + csrr t0, mstatus ; Pickup mstatus + sw t0, 0x38(sp) ; Save mstatus + + + /* Lockout interrupts. - will be enabled in _tx_thread_schedule */ + + csrci mstatus, 0xF + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + call _tx_execution_thread_exit ; Call the thread execution exit function +#endif + + la t0, _tx_thread_current_ptr ; Pickup address of pointer + lw t1, 0(t0) ; Pickup current thread pointer + la t2,_tx_thread_system_stack_ptr ; Pickup stack pointer address + + /* Save current stack and switch to system stack. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = SP; + SP = _tx_thread_system_stack_ptr; */ + + sw sp, 8(t1) ; Save stack pointer + lw sp, 0(t2) ; Switch to system stack + + /* Determine if the time-slice is active. */ + /* if (_tx_timer_time_slice) + { */ + + la t4, _tx_timer_time_slice ; Pickup time slice variable addr + lw t3, 0(t4) ; Pickup time slice value + la t2, _tx_thread_schedule ; Pickup address of scheduling loop + beqz t3, _tx_thread_dont_save_ts ; If no time-slice, don't save it + + /* Save time-slice for the thread and clear the current time-slice. */ + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + sw t3, 24(t1) ; Save current time-slice for thread + sw x0, 0(t4) ; Clear time-slice variable + + /* } */ +_tx_thread_dont_save_ts: + + /* Clear the current thread pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + sw x0, 0(t0) ; Clear current thread pointer + jr t2 ; Return to thread scheduler + +/* } */ + + END + \ No newline at end of file diff --git a/ports/risc-v32/iar/src/tx_timer_interrupt.s b/ports/risc-v32/iar/src/tx_timer_interrupt.s new file mode 100644 index 00000000..9855987c --- /dev/null +++ b/ports/risc-v32/iar/src/tx_timer_interrupt.s @@ -0,0 +1,234 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" + #include "tx_timer.h" + #include "tx_thread.h" */ + + EXTERN _tx_timer_system_clock + EXTERN _tx_timer_time_slice + EXTERN _tx_timer_expired_time_slice + EXTERN _tx_timer_current_ptr + EXTERN _tx_timer_expired + EXTERN _tx_timer_list_end + EXTERN _tx_timer_list_start + EXTERN _tx_timer_expiration_process + EXTERN _tx_thread_time_slice + + + SECTION `.mtext`:CODE:REORDER:NOROOT(2) + CODE +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt RISC-V32/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* Tom van Leeuwen, Technolution B.V. */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_timer_interrupt(VOID) +{ */ + PUBLIC _tx_timer_interrupt +_tx_timer_interrupt: + + /* Increment the system clock. */ + /* _tx_timer_system_clock++; */ + + la t0, _tx_timer_system_clock ; Pickup address of system clock + lw t1, 0(t0) ; Pickup system clock + la t2, _tx_timer_time_slice ; Pickup address of time slice + lw t3, 0(t2) ; Pickup time slice + addi t1, t1, 1 ; Increment system clock + sw t1, 0(t0) ; Store new system clock + li t6, 0 ; Clear local expired flag + + /* Test for time-slice expiration. */ + /* if (_tx_timer_time_slice) + { */ + + beqz t3, _tx_timer_no_time_slice ; If 0, skip time slice processing + addi t3, t3, -1 ; Decrement the time slice + + /* Decrement the time_slice. */ + /* _tx_timer_time_slice--; */ + + sw t3, 0(t2) ; Store new time slice + + /* Check for expiration. */ + /* if (__tx_timer_time_slice == 0) */ + + bgtz t3, _tx_timer_no_time_slice ; If not 0, has not expired yet + li t1, 1 ; Build expired flag + + /* Set the time-slice expired flag. */ + /* _tx_timer_expired_time_slice = TX_TRUE; */ + + la t4, _tx_timer_expired_time_slice ; Get address of expired flag + sw t1, 0(t4) ; Set expired flag + ori t6, t6, 1 ; Set local expired flag + + /* } */ + +_tx_timer_no_time_slice: + + /* Test for timer expiration. */ + /* if (*_tx_timer_current_ptr) + { */ + + la t0, _tx_timer_current_ptr ; Pickup address of current ptr + lw t1, 0(t0) ; Pickup current pointer + lw t3, 0(t1) ; Pickup the current timer entry + la t2, _tx_timer_expired ; Pickup address of timer expired flag + li t4, 1 ; Build TX_TRUE flag + beqz t3, _tx_timer_no_timer ; If NULL, no timer has expired + + /* Set expiration flag. */ + /* _tx_timer_expired = TX_TRUE; */ + + ori t6, t6, 2 ; Set local expired flag + sw t4, 0(t2) ; Set expired flag in memory + j _tx_timer_done ; Finished timer processing + + + /* } + else + { */ +_tx_timer_no_timer: + + /* No timer expired, increment the timer pointer. */ + /* _tx_timer_current_ptr++; */ + + /* Check for wrap-around. */ + /* if (_tx_timer_current_ptr == _tx_timer_list_end) */ + + la t2, _tx_timer_list_end ; Pickup address of list end pointer + lw t3, 0(t2) ; Pickup actual list end + addi t1, t1, 4 ; Point to next timer entry + sw t1, 0(t0) ; Store new timer pointer + bne t1, t3, _tx_timer_skip_wrap ; If not same, good pointer + + /* Wrap to beginning of list. */ + /* _tx_timer_current_ptr = _tx_timer_list_start; */ + + la t2, _tx_timer_list_start ; Pickup address of list start pointer + lw t4, 0(t2) ; Pickup start of the list + sw t4, 0(t0) ; Store new timer pointer*/ + + +_tx_timer_skip_wrap: + /* } */ + +_tx_timer_done: + + + /* See if anything has expired. */ + /* if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) + { */ + + beqz t6, _tx_timer_nothing_expired ; If nothing expired skip the rest + and t2, t6, 2 ; Isolate the timer expired bit + addi sp, sp, -16 ; Allocate some storage on the stack + sw t6, 0(sp) ; Save local expired flag + sw ra, 4(sp) ; Save ra + + /* Did a timer expire? */ + /* if (_tx_timer_expired) + { */ + + beqz t2, _tx_timer_dont_activate ; No, timer not expired + + /* Call the timer expiration processing. */ + /* _tx_timer_expiration_process(void); */ + + call _tx_timer_expiration_process ; Call _tx_timer_expiration_process + lw t6, 0(sp) ; Recover local expired flag + + /* } */ +_tx_timer_dont_activate: + + /* Did time slice expire? */ + /* if (_tx_timer_expired_time_slice) + { */ + + and t2, t6, 1 ; Is the timer expired bit set? + beqz t2, _tx_timer_not_ts_expiration ; If not, skip time slice processing + + /* Time slice interrupted thread. */ + /* _tx_thread_time_slice(); */ + + call _tx_thread_time_slice ; Call time slice + + /* } */ + +_tx_timer_not_ts_expiration: + + lw ra, 4(sp) ; Recover ra + addi sp, sp, 16 ; Recover stack space + /* } */ + +_tx_timer_nothing_expired: + + ret + +/* } */ + END + \ No newline at end of file diff --git a/ports/win32/vs_2019/CMakeLists.txt b/ports/win32/vs_2019/CMakeLists.txt new file mode 100644 index 00000000..5a766f06 --- /dev/null +++ b/ports/win32/vs_2019/CMakeLists.txt @@ -0,0 +1,20 @@ + +target_sources(${PROJECT_NAME} + PRIVATE + # {{BEGIN_TARGET_SOURCES}} + ${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_schedule.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.c + ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.c + + # {{END_TARGET_SOURCES}} +) + +target_include_directories(${PROJECT_NAME} + PUBLIC + ${CMAKE_CURRENT_LIST_DIR}/inc +) diff --git a/ports/win32/vs_2019/inc/tx_port.h b/ports/win32/vs_2019/inc/tx_port.h index c5f666f8..7ecf4678 100644 --- a/ports/win32/vs_2019/inc/tx_port.h +++ b/ports/win32/vs_2019/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Win32/Visual */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -419,7 +419,7 @@ VOID _tx_thread_interrupt_restore(UINT previous_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Win32/Visual Studio Version 6.0 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Win32/Visual Studio Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/win32/vs_2019/readme_threadx.txt b/ports/win32/vs_2019/readme_threadx.txt index 348d1a37..13ce3d33 100644 --- a/ports/win32/vs_2019/readme_threadx.txt +++ b/ports/win32/vs_2019/readme_threadx.txt @@ -145,7 +145,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX version for Win32 using Microsoft Visual C/C++. +09-30-2020 Initial ThreadX version for Win32 using Microsoft Visual C/C++. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports/win32/vs_2019/src/tx_initialize_low_level.c b/ports/win32/vs_2019/src/tx_initialize_low_level.c index f11df9dc..71cacd10 100644 --- a/ports/win32/vs_2019/src/tx_initialize_low_level.c +++ b/ports/win32/vs_2019/src/tx_initialize_low_level.c @@ -163,7 +163,7 @@ extern VOID *_tx_initialize_unused_memory; /* FUNCTION RELEASE */ /* */ /* _tx_initialize_low_level Win32/Visual */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -201,7 +201,7 @@ extern VOID *_tx_initialize_unused_memory; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_initialize_low_level(VOID) diff --git a/ports/win32/vs_2019/src/tx_thread_context_restore.c b/ports/win32/vs_2019/src/tx_thread_context_restore.c index 8ff1ef23..2bcb4db8 100644 --- a/ports/win32/vs_2019/src/tx_thread_context_restore.c +++ b/ports/win32/vs_2019/src/tx_thread_context_restore.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore Win32/Visual */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_context_restore(VOID) diff --git a/ports/win32/vs_2019/src/tx_thread_context_save.c b/ports/win32/vs_2019/src/tx_thread_context_save.c index 676c2832..17268c36 100644 --- a/ports/win32/vs_2019/src/tx_thread_context_save.c +++ b/ports/win32/vs_2019/src/tx_thread_context_save.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save Win32/Visual */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,7 +69,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_context_save(VOID) diff --git a/ports/win32/vs_2019/src/tx_thread_interrupt_control.c b/ports/win32/vs_2019/src/tx_thread_interrupt_control.c index 671758a1..6b1b2c6a 100644 --- a/ports/win32/vs_2019/src/tx_thread_interrupt_control.c +++ b/ports/win32/vs_2019/src/tx_thread_interrupt_control.c @@ -55,7 +55,7 @@ VOID _tx_thread_interrupt_restore(UINT previous_posture) /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control Win32/Visual */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -92,7 +92,7 @@ VOID _tx_thread_interrupt_restore(UINT previous_posture) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports/win32/vs_2019/src/tx_thread_schedule.c b/ports/win32/vs_2019/src/tx_thread_schedule.c index 5b8a756d..071ffe3c 100644 --- a/ports/win32/vs_2019/src/tx_thread_schedule.c +++ b/ports/win32/vs_2019/src/tx_thread_schedule.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Win32/Visual */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_schedule(VOID) diff --git a/ports/win32/vs_2019/src/tx_thread_stack_build.c b/ports/win32/vs_2019/src/tx_thread_stack_build.c index 649a9066..fb9620cb 100644 --- a/ports/win32/vs_2019/src/tx_thread_stack_build.c +++ b/ports/win32/vs_2019/src/tx_thread_stack_build.c @@ -41,7 +41,7 @@ DWORD WINAPI _tx_win32_thread_entry(LPVOID p); /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build Win32/Visual */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -76,7 +76,7 @@ DWORD WINAPI _tx_win32_thread_entry(LPVOID p); /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports/win32/vs_2019/src/tx_thread_system_return.c b/ports/win32/vs_2019/src/tx_thread_system_return.c index 921ce850..72edda3c 100644 --- a/ports/win32/vs_2019/src/tx_thread_system_return.c +++ b/ports/win32/vs_2019/src/tx_thread_system_return.c @@ -36,7 +36,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return Win32/Visual */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_system_return(VOID) diff --git a/ports/win32/vs_2019/src/tx_timer_interrupt.c b/ports/win32/vs_2019/src/tx_timer_interrupt.c index 83edfa34..5f0b7111 100644 --- a/ports/win32/vs_2019/src/tx_timer_interrupt.c +++ b/ports/win32/vs_2019/src/tx_timer_interrupt.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt Win32/Visual */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_timer_interrupt(VOID) diff --git a/ports_module/cortex-a7/ac5/example_build/build_all.bat b/ports_module/cortex-a7/ac5/example_build/build_all.bat new file mode 100644 index 00000000..84dcc19c --- /dev/null +++ b/ports_module/cortex-a7/ac5/example_build/build_all.bat @@ -0,0 +1,7 @@ + +call build_threadx.bat +call build_threadx_module_library.bat +call build_threadx_module_sample.bat +call ..\..\..\..\common_modules\utilities\module_to_c_array.exe sample_threadx_module.axf module_code.c +powershell -Command "(gc module_code.c) -replace 'unsigned', '__align(4096) unsigned' | Out-File module_code.c" +call build_threadx_module_manager_sample.bat diff --git a/ports_module/cortex-a7/ac5/example_build/build_threadx.bat b/ports_module/cortex-a7/ac5/example_build/build_threadx.bat new file mode 100644 index 00000000..ea349e37 --- /dev/null +++ b/ports_module/cortex-a7/ac5/example_build/build_threadx.bat @@ -0,0 +1,290 @@ +del tx.a +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork tx_initialize_low_level.s +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_stack_build.s +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_schedule.s +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_system_return.s +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_context_save.s +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_context_restore.s +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_interrupt_control.s +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_timer_interrupt.s +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_fiq_context_restore.s +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_fiq_context_save.s +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_fiq_nesting_end.s +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_fiq_nesting_start.s +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_interrupt_disable.s +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_interrupt_restore.s +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_irq_nesting_end.s +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_irq_nesting_start.s +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_vectored_context_save.s +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_allocate.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_cleanup.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_create.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_delete.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_info_get.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_initialize.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_performance_info_get.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_performance_system_info_get.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_prioritize.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_release.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_allocate.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_cleanup.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_create.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_delete.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_info_get.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_initialize.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_performance_info_get.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_prioritize.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_search.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_release.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_cleanup.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_create.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_delete.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_get.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_info_get.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_initialize.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_performance_info_get.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_performance_system_info_get.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_set.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_set_notify.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_initialize_high_level.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_initialize_kernel_enter.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_initialize_kernel_setup.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_cleanup.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_create.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_delete.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_get.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_info_get.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_initialize.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_performance_info_get.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_performance_system_info_get.c +armcc -g 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-g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_front_send.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_info_get.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_prioritize.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_receive.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_send.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_send_notify.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_ceiling_put.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_create.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_delete.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_get.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_info_get.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_prioritize.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_put.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_put_notify.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_create.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_delete.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_entry_exit_notify.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_info_get.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_preemption_change.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_priority_change.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_relinquish.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_reset.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_resume.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_suspend.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_terminate.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_time_slice_change.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_wait_abort.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_activate.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_change.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_create.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_deactivate.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_delete.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_info_get.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../module_manager/src/txm_module_manager_alignment_adjust.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_application_request.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_callback_request.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_event_flags_notify_trampoline.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../module_manager/src/txm_module_manager_external_memory_enable.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_file_load.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_in_place_load.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_internal_load.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_initialize.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../module_manager/src/txm_module_manager_mm_initialize.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_kernel_dispatch.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_maximum_module_priority_set.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../module_manager/src/txm_module_manager_memory_fault_handler.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../module_manager/src/txm_module_manager_memory_fault_notify.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_memory_load.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_allocate.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_deallocate.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_pointer_get.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_pointer_get_extended.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_pool_create.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_properties_get.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_queue_notify_trampoline.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_semaphore_notify_trampoline.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../module_manager/src/txm_module_manager_mm_register_setup.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_start.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_stop.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_thread_create.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_thread_notify_trampoline.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_thread_reset.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_timer_notify_trampoline.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_unload.c +armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_util.c +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork ../module_manager/src/txm_module_manager_thread_stack_build.s +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork ../module_manager/src/txm_module_manager_user_mode_entry.s + +armar --create tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o +armar -r tx.a tx_initialize_low_level.o tx_thread_fiq_context_restore.o tx_thread_fiq_context_save.o tx_thread_fiq_nesting_end.o tx_thread_fiq_nesting_start.o tx_thread_interrupt_disable.o +armar -r tx.a tx_thread_interrupt_restore.o tx_thread_irq_nesting_end.o tx_thread_irq_nesting_start.o +armar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o +armar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o +armar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o +armar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o +armar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o +armar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o +armar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o +armar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o +armar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o +armar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o +armar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o +armar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o +armar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o +armar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o +armar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o +armar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o +armar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o +armar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o +armar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o +armar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o +armar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o +armar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o +armar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o +armar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o +armar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o +armar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o +armar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o +armar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o +armar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o +armar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o +armar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o +armar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o +armar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o + +armar -r tx.a txm_module_manager_alignment_adjust.o txm_module_manager_application_request.o txm_module_manager_callback_request.o +armar -r tx.a txm_module_manager_event_flags_notify_trampoline.o txm_module_manager_external_memory_enable.o txm_module_manager_file_load.o +armar -r tx.a txm_module_manager_in_place_load.o txm_module_manager_initialize.o txm_module_manager_mm_initialize.o +armar -r tx.a txm_module_manager_kernel_dispatch.o txm_module_manager_maximum_module_priority_set.o txm_module_manager_memory_fault_handler.o +armar -r tx.a txm_module_manager_memory_fault_notify.o txm_module_manager_memory_load.o txm_module_manager_object_pointer_get.o +armar -r tx.a txm_module_manager_object_pool_create.o txm_module_manager_queue_notify_trampoline.o txm_module_manager_semaphore_notify_trampoline.o +armar -r tx.a txm_module_manager_mm_register_setup.o txm_module_manager_start.o txm_module_manager_stop.o +armar -r tx.a txm_module_manager_thread_create.o txm_module_manager_thread_notify_trampoline.o txm_module_manager_thread_reset.o +armar -r tx.a txm_module_manager_timer_notify_trampoline.o txm_module_manager_unload.o txm_module_manager_thread_stack_build.o +armar -r tx.a txm_module_manager_user_mode_entry.o +armar -r tx.a txm_module_manager_internal_load.o +armar -r tx.a txm_module_manager_object_allocate.o +armar -r tx.a txm_module_manager_object_deallocate.o +armar -r tx.a txm_module_manager_object_pointer_get_extended.o +armar -r tx.a txm_module_manager_properties_get.o +armar -r tx.a txm_module_manager_util.o diff --git a/ports_module/cortex-a7/ac5/example_build/build_threadx_module_library.bat b/ports_module/cortex-a7/ac5/example_build/build_threadx_module_library.bat new file mode 100644 index 00000000..174a2d25 --- /dev/null +++ b/ports_module/cortex-a7/ac5/example_build/build_threadx_module_library.bat @@ -0,0 +1,120 @@ +del txm.a + +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_block_allocate.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_block_pool_create.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_block_pool_delete.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_block_pool_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_block_pool_performance_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_block_pool_performance_system_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_block_pool_prioritize.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_block_release.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_byte_allocate.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_byte_pool_create.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_byte_pool_delete.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_byte_pool_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_byte_pool_performance_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_byte_pool_performance_system_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_byte_pool_prioritize.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_byte_release.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_event_flags_create.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_event_flags_delete.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_event_flags_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_event_flags_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_event_flags_performance_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_event_flags_performance_system_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_event_flags_set.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_event_flags_set_notify.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_module_application_request.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_module_callback_request_thread_entry.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_module_object_allocate.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_module_object_deallocate.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_module_object_pointer_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../module_lib/src/txm_module_thread_shell_entry.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_module_thread_system_suspend.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_mutex_create.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_mutex_delete.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_mutex_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_mutex_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_mutex_performance_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_mutex_performance_system_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_mutex_prioritize.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_mutex_put.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_queue_create.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_queue_delete.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_queue_flush.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_queue_front_send.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_queue_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_queue_performance_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_queue_performance_system_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_queue_prioritize.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_queue_receive.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_queue_send.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_queue_send_notify.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_semaphore_ceiling_put.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_semaphore_create.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_semaphore_delete.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_semaphore_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_semaphore_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_semaphore_performance_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_semaphore_performance_system_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_semaphore_prioritize.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_semaphore_put.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_semaphore_put_notify.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_create.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_delete.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_entry_exit_notify.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_identify.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_interrupt_control.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_performance_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_performance_system_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_preemption_change.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_priority_change.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_relinquish.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_reset.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_resume.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_sleep.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_stack_error_notify.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_suspend.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_terminate.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_time_slice_change.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_wait_abort.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_time_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_time_set.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_timer_activate.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_timer_change.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_timer_create.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_timer_deactivate.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_timer_delete.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_timer_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_timer_performance_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_timer_performance_system_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_trace_buffer_full_notify.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_trace_disable.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_trace_enable.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_trace_event_filter.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_trace_event_unfilter.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_trace_isr_enter_insert.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_trace_isr_exit_insert.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_trace_user_event_insert.c + +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork/ropi/rwpi ../module_lib/src/txm_module_initialize.s + +armar --create txm.a txm_block_allocate.o txm_block_pool_create.o txm_block_pool_delete.o txm_block_pool_info_get.o txm_block_pool_performance_info_get.o txm_block_pool_performance_system_info_get.o +armar -r txm.a txm_block_pool_prioritize.o txm_block_release.o +armar -r txm.a txm_byte_allocate.o txm_byte_pool_create.o txm_byte_pool_delete.o txm_byte_pool_info_get.o txm_byte_pool_performance_info_get.o txm_byte_pool_performance_system_info_get.o +armar -r txm.a txm_byte_pool_prioritize.o txm_byte_release.o +armar -r txm.a txm_event_flags_create.o txm_event_flags_delete.o txm_event_flags_get.o txm_event_flags_info_get.o txm_event_flags_performance_info_get.o txm_event_flags_performance_system_info_get.o +armar -r txm.a txm_event_flags_set.o txm_event_flags_set_notify.o +armar -r txm.a txm_module_application_request.o txm_module_callback_request_thread_entry.o txm_module_initialize.o txm_module_object_allocate.o txm_module_object_deallocate.o txm_module_object_pointer_get.o txm_module_thread_shell_entry.o txm_module_thread_system_suspend.o +armar -r txm.a txm_mutex_create.o txm_mutex_delete.o txm_mutex_get.o txm_mutex_info_get.o txm_mutex_performance_info_get.o txm_mutex_performance_system_info_get.o txm_mutex_prioritize.o txm_mutex_put.o +armar -r txm.a txm_queue_create.o txm_queue_delete.o txm_queue_flush.o txm_queue_front_send.o txm_queue_info_get.o txm_queue_performance_info_get.o txm_queue_performance_system_info_get.o +armar -r txm.a txm_queue_prioritize.o txm_queue_receive.o txm_queue_send.o txm_queue_send_notify.o +armar -r txm.a txm_semaphore_ceiling_put.o txm_semaphore_create.o txm_semaphore_delete.o txm_semaphore_get.o txm_semaphore_info_get.o txm_semaphore_performance_info_get.o txm_semaphore_performance_system_info_get.o +armar -r txm.a txm_semaphore_prioritize.o txm_semaphore_put.o txm_semaphore_put_notify.o +armar -r txm.a txm_thread_create.o txm_thread_delete.o txm_thread_entry_exit_notify.o txm_thread_identify.o txm_thread_info_get.o txm_thread_interrupt_control.o txm_thread_performance_info_get.o +armar -r txm.a txm_thread_performance_system_info_get.o txm_thread_preemption_change.o txm_thread_priority_change.o txm_thread_relinquish.o txm_thread_reset.o txm_thread_resume.o +armar -r txm.a txm_thread_sleep.o txm_thread_stack_error_notify.o txm_thread_suspend.o txm_thread_terminate.o txm_thread_time_slice_change.o txm_thread_wait_abort.o +armar -r txm.a txm_time_get.o txm_time_set.o +armar -r txm.a txm_timer_activate.o txm_timer_change.o txm_timer_create.o txm_timer_deactivate.o txm_timer_delete.o txm_timer_info_get.o txm_timer_performance_info_get.o txm_timer_performance_system_info_get.o +armar -r txm.a txm_trace_buffer_full_notify.o txm_trace_disable.o txm_trace_enable.o txm_trace_event_filter.o txm_trace_event_unfilter.o txm_trace_isr_enter_insert.o txm_trace_isr_exit_insert.o txm_trace_user_event_insert.o diff --git a/ports_module/cortex-a7/ac5/example_build/build_threadx_module_manager_sample.bat b/ports_module/cortex-a7/ac5/example_build/build_threadx_module_manager_sample.bat new file mode 100644 index 00000000..218ad16f --- /dev/null +++ b/ports_module/cortex-a7/ac5/example_build/build_threadx_module_manager_sample.bat @@ -0,0 +1,5 @@ +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=interwork tx_initialize_low_level.s +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc sample_threadx_module_manager.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c module_code.c +armlink -d -o sample_threadx_module_manager.axf --elf --ro 0x80000000 --first tx_initialize_low_level.o(VECTORS) --remove --map --symbols --list sample_threadx_module_manager.map tx_initialize_low_level.o sample_threadx_module_manager.o module_code.o tx.a + diff --git a/ports_module/cortex-a7/ac5/example_build/build_threadx_module_sample.bat b/ports_module/cortex-a7/ac5/example_build/build_threadx_module_sample.bat new file mode 100644 index 00000000..f06b114a --- /dev/null +++ b/ports_module/cortex-a7/ac5/example_build/build_threadx_module_sample.bat @@ -0,0 +1,4 @@ +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork/ropi/rwpi txm_module_preamble.s +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi --lower_ropi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc sample_threadx_module.c +armlink -d -o sample_threadx_module.axf --elf --ro 0 --first txm_module_preamble.o(Init) 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z#5uk0fRi@&8bE#b9={u==J4}dasGvK%2?Yo>pz+IHiEaj#(g-?a2zMUyY%=?Z?*F0 z3-h*sQ+ZwecFB2|MRQEypOt%W%X~hV9kQ1C0=#k^j8@( zbLe1}{9Lmj>ssH9Oz#$F*0sJyoEG)R(d)J0w5)A^z706DuJtwAGwWJERGk0retgI* H7IpszyWu+X literal 0 HcmV?d00001 diff --git a/ports_module/cortex-a7/ac5/example_build/sample_threadx_module.c b/ports_module/cortex-a7/ac5/example_build/sample_threadx_module.c new file mode 100644 index 00000000..fce2a3fa --- /dev/null +++ b/ports_module/cortex-a7/ac5/example_build/sample_threadx_module.c @@ -0,0 +1,427 @@ +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, + event flags group, byte pool, and block pool. */ + +/* Specify that this is a module! */ + +#define TXM_MODULE + + +/* Include the ThreadX module definitions. */ + +#include "txm_module.h" + + +/* Define constants. */ + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the pool space in the bss section of the module. ULONG is used to + get the word alignment. */ + +ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD *thread_0; +TX_THREAD *thread_1; +TX_THREAD *thread_2; +TX_THREAD *thread_3; +TX_THREAD *thread_4; +TX_THREAD *thread_5; +TX_THREAD *thread_6; +TX_THREAD *thread_7; +TX_QUEUE *queue_0; +TX_SEMAPHORE *semaphore_0; +TX_MUTEX *mutex_0; +TX_EVENT_FLAGS_GROUP *event_flags_0; +TX_BYTE_POOL *byte_pool_0; +TX_BLOCK_POOL *block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; +ULONG semaphore_0_puts; +ULONG event_0_sets; +ULONG queue_0_sends; + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + +void semaphore_0_notify(TX_SEMAPHORE *semaphore_ptr) +{ + + if (semaphore_ptr == semaphore_0) + semaphore_0_puts++; +} + + +void event_0_notify(TX_EVENT_FLAGS_GROUP *event_flag_group_ptr) +{ + + if (event_flag_group_ptr == event_flags_0) + event_0_sets++; +} + + +void queue_0_notify(TX_QUEUE *queue_ptr) +{ + + if (queue_ptr == queue_0) + queue_0_sends++; +} + + +/* Define the module start function. */ + +void demo_module_start(ULONG id) +{ + +CHAR *pointer; + + /* Allocate all the objects. In MMU mode, modules cannot allocate control blocks within + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + the control block(s). */ + txm_module_object_allocate((void *) &thread_0, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &thread_1, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &thread_2, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &thread_3, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &thread_4, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &thread_5, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &thread_6, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &thread_7, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &queue_0, sizeof(TX_QUEUE)); + txm_module_object_allocate((void *) &semaphore_0, sizeof(TX_SEMAPHORE)); + txm_module_object_allocate((void *) &mutex_0, sizeof(TX_MUTEX)); + txm_module_object_allocate((void *) &event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); + txm_module_object_allocate((void *) &byte_pool_0, sizeof(TX_BYTE_POOL)); + txm_module_object_allocate((void *) &block_pool_0, sizeof(TX_BLOCK_POOL)); + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(queue_0, "module queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + tx_queue_send_notify(queue_0, queue_0_notify); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(semaphore_0, "module semaphore 0", 1); + + tx_semaphore_put_notify(semaphore_0, semaphore_0_notify); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(event_flags_0, "module event flags 0"); + + tx_event_flags_set_notify(event_flags_0, event_0_notify); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(mutex_0, "module mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(block_pool_0, "module block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + /* Test external/shared memory. */ + *(ULONG *) 0x90000000 = 0xdeadbeef; + *(ULONG *) 0x90000FFC = 0xfeed0add; + *(ULONG *) 0x90001000 = 0xfedcba01; + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports_module/cortex-a7/ac5/example_build/sample_threadx_module_manager.c b/ports_module/cortex-a7/ac5/example_build/sample_threadx_module_manager.c new file mode 100644 index 00000000..8b17e34a --- /dev/null +++ b/ports_module/cortex-a7/ac5/example_build/sample_threadx_module_manager.c @@ -0,0 +1,132 @@ +/* Small demonstration of the ThreadX module manager. This demonstration assumes the program + manager is loaded at 0 and that RAM addresses 0x200000 through 0x400000 are available for + use. */ + +#include "tx_api.h" +#include "txm_module.h" + + +#define DEMO_STACK_SIZE 1024 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD module_manager; + +/* Define thread prototypes. */ + +void module_manager_entry(ULONG thread_input); + +/* Define the module object pool area. */ +UCHAR object_memory[16384]; + +/* Define the module data pool area. */ +#define MODULE_DATA_SIZE 65536 +unsigned char module_data_area[MODULE_DATA_SIZE]; + +/* Define a module instance. */ +TXM_MODULE_INSTANCE my_module1; +TXM_MODULE_INSTANCE my_module2; + +/* Module code is in an array created by module_to_c_array utility. */ +extern unsigned char module_code[]; + +/* Define the count of memory faults. */ +ULONG memory_faults; + +/* Define fault handler. */ +VOID module_fault_handler(TX_THREAD *thread, TXM_MODULE_INSTANCE *module) +{ + /* Just increment the fault counter. */ + memory_faults++; +} + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + + /* Create the module manager thread. */ + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + first_unused_memory, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); +} + + + +/* Define the test threads. */ + +void module_manager_entry(ULONG thread_input) +{ + + /* Initialize the module manager. */ + txm_module_manager_initialize((VOID *) module_data_area, MODULE_DATA_SIZE); + + /* Create a pool for module objects. */ + txm_module_manager_object_pool_create(object_memory, sizeof(object_memory)); + + /* Register a fault handler. */ + txm_module_manager_memory_fault_notify(module_fault_handler); + + /* Initialize MMU. */ + txm_module_manager_mm_initialize(); + + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ + txm_module_manager_in_place_load(&my_module1, "my module1", (VOID *) module_code); + + /* Load a second instance of the module. */ + //txm_module_manager_in_place_load(&my_module2, "my module2", (VOID *) module_code); + + /* Enable shared memory regions for one module. */ + //txm_module_manager_external_memory_enable(&my_module2, (void*)0x90000000, 0x010000, 0x3F); + + /* Start the modules. */ + txm_module_manager_start(&my_module1); + //txm_module_manager_start(&my_module2); + + /* Sleep for a while and let the modules run.... */ + tx_thread_sleep(50); + + /* Thread 0 in module1 should be terminated due to violating the MMU. */ + + /* Stop the modules. */ + txm_module_manager_stop(&my_module1); + txm_module_manager_stop(&my_module2); + + /* Unload the modules. */ + txm_module_manager_unload(&my_module1); + txm_module_manager_unload(&my_module2); + + /* Reload the modules. */ + txm_module_manager_in_place_load(&my_module2, "my module2", (VOID *) module_code); + txm_module_manager_in_place_load(&my_module1, "my module1", (VOID *) module_code); + + /* Give both modules shared memory. */ + txm_module_manager_external_memory_enable(&my_module2, (void*)0x90000000, 0x010000, 0x3F); + txm_module_manager_external_memory_enable(&my_module1, (void*)0x90000000, 0x010000, 0x3F); + + /* Start the module again. */ + txm_module_manager_start(&my_module2); + txm_module_manager_start(&my_module1); + + /* Now just spin... */ + while(1) + { + tx_thread_sleep(100); + /* Thread 0 and 5 in module1 should not exist because they violate the maximum priority. */ + } +} + + + + diff --git a/ports_module/cortex-a7/ac5/example_build/scatter.scat b/ports_module/cortex-a7/ac5/example_build/scatter.scat new file mode 100644 index 00000000..a9e2d1d8 --- /dev/null +++ b/ports_module/cortex-a7/ac5/example_build/scatter.scat @@ -0,0 +1,41 @@ +;************************************************** +; Copyright (c) 2011 ARM Ltd. All rights reserved. +;************************************************** + +; This scatter-file places application code, data, stack and heap at base address 0x80000000. +; Using a scatter-file with ARM_LIB_STACKHEAP eliminates the need to set stack-limit or heap-base in the debugger. + + +SDRAM 0x80000000 +{ + VECTORS +0 + { + * (VECTORS, +FIRST) ; Vector table and other (assembler) startup code + * (InRoot$$Sections) ; All (library) code that must be in a root region + } + + RO_CODE +0 + { * (+RO-CODE) } ; Application RO code (.text) + + RO_DATA +0 + { * (+RO-DATA) } ; Application RO data (.constdata) + + RW_DATA +0 + { * (+RW) } ; Application RW data (.data) + + ZI_DATA +0 + { * (+ZI) } ; Application ZI data (.bss) + + ARM_LIB_HEAP 0x80040000 EMPTY 0x00040000 ; Application heap + { } + + ARM_LIB_STACK 0x80090000 EMPTY -0x00010000 ; Application (SVC mode) stack + { } + + IRQ_STACK 0x800A0000 EMPTY -0x00010000 ; IRQ mode stack + { } + + TTB 0x80100000 EMPTY 0x4000 ; Level-1 Translation Table for MMU + { } + +} diff --git a/ports_module/cortex-a7/ac5/example_build/tx_initialize_low_level.s b/ports_module/cortex-a7/ac5/example_build/tx_initialize_low_level.s new file mode 100644 index 00000000..9621aea4 --- /dev/null +++ b/ports_module/cortex-a7/ac5/example_build/tx_initialize_low_level.s @@ -0,0 +1,659 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_initialize.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + +THUMB_MASK EQU 0x20 ; Thumb bit (5) of CPSR/SPSR +FIQ_MODE EQU 0x11 ; FIQ mode +IRQ_MODE EQU 0x12 ; IRQ mode +SVC_MODE EQU 0x13 ; SVC mode +ABT_MODE EQU 0x17 ; ABT mode +SYS_MODE EQU 0x1F ; SYS mode + +HEAP_SIZE EQU 4096 ; Heap size +FIQ_STACK_SIZE EQU 512 ; FIQ stack size +SYS_STACK_SIZE EQU 1024 ; SYS stack size +IRQ_STACK_SIZE EQU 1024 ; IRQ stack size +SVC_STACK_SIZE EQU 512 ; SVC stack size +ABT_STACK_SIZE EQU 512 ; ABT stack size + +VFPEnable EQU 0x40000000 ; VFP enable value + +; +; + IMPORT __tx_swi_interrupt + IMPORT _tx_thread_system_stack_ptr + IMPORT _tx_initialize_unused_memory + IMPORT _tx_thread_context_save + IMPORT _tx_thread_context_restore + IF :DEF:TX_ENABLE_FIQ_SUPPORT + IMPORT _tx_thread_fiq_context_save + IMPORT _tx_thread_fiq_context_restore + ENDIF + IF :DEF:TX_ENABLE_IRQ_NESTING + IMPORT _tx_thread_irq_nesting_start + IMPORT _tx_thread_irq_nesting_end + ENDIF + IF :DEF:TX_ENABLE_FIQ_NESTING + IMPORT _tx_thread_fiq_nesting_start + IMPORT _tx_thread_fiq_nesting_end + ENDIF + IMPORT _tx_timer_interrupt + IMPORT __main + IMPORT _tx_version_id + IMPORT _tx_build_options + IMPORT |Image$$ZI$$Limit| +; +; + AREA VECTORS, CODE, READONLY + PRESERVE8 +; +;/* Define the default Cortex-A7 vector area. This should be located or copied to 0. */ +; + EXPORT __vectors +__vectors + LDR pc,=Reset_Vector ; Reset goes to startup function + LDR pc,=__tx_undefined ; Undefined handler + LDR pc,=__tx_swi_interrupt ; Software interrupt handler + LDR pc,=__tx_prefetch_handler ; Prefetch exception handler + LDR pc,=__tx_abort_handler ; Abort exception handler + LDR pc,=__tx_reserved_handler ; Reserved exception handler + LDR pc,=__tx_irq_handler ; IRQ interrupt handler + LDR pc,=__tx_fiq_handler ; FIQ interrupt handler +; +; + EXPORT Reset_Vector +Reset_Vector + + IF {TARGET_FPU_VFP} = {TRUE} + MRC p15, 0, r1, c1, c0, 2 ; r1 = Access Control Register + ORR r1, r1, #(0xf << 20) ; Enable full access for p10,11 + MCR p15, 0, r1, c1, c0, 2 ; Access Control Register = r1 + MOV r1, #0 + MCR p15, 0, r1, c7, c5, 4 ; Flush prefetch buffer because of FMXR below and + ; CP 10 & 11 were only just enabled + MOV r0, #VFPEnable ; Enable VFP itself + FMXR FPEXC, r0 ; FPEXC = r0 + ENDIF + + B __main +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-A7/MMU/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + EXPORT _tx_initialize_low_level +_tx_initialize_low_level +; +; +; /****** NOTE ****** We must be in SVC MODE at this point. Some monitors +; enter this routine in USER mode and require a software interrupt to +; change into SVC mode. */ +; + + ; Set vector table. + LDR r0, = __vectors + MCR p15, 0, r0, c12, c0, 0 + + + LDR r1, =|Image$$ZI$$Limit| ; Get end of non-initialized RAM area + LDR r2, =HEAP_SIZE ; Pickup the heap size + ADD r1, r2, r1 ; Setup heap limit + ADD r1, r1, #4 ; Setup stack limit + MOV r3, lr ; Save LR + + LDR r2, =SYS_STACK_SIZE ; Pickup stack size + CPS #SYS_MODE ; Enter SYS mode + ADD r1, r1, r2 ; Calculate start of SYS stack + BIC r1, r1, #7 ; Ensure 8-byte alignment + MOV sp, r1 ; Setup SYS stack pointer + MOV lr, r3 ; Restore LR + + LDR r2, =SVC_STACK_SIZE ; Pickup SVC stack size + CPS #SVC_MODE ; Enter SVC mode + ADD r1, r1, r2 ; Calculate start of SVC stack + BIC r1, r1, #7 ; Ensure 8-byte alignment + MOV sp, r1 ; Setup SVC stack pointer + + LDR r2, =IRQ_STACK_SIZE ; Pickup IRQ stack size + CPS #IRQ_MODE ; Enter IRQ mode + ADD r1, r1, r2 ; Calculate start of IRQ stack + BIC r1, r1, #7 ; Ensure 8-byte alignment + MOV sp, r1 ; Setup IRQ stack pointer + + LDR r2, =FIQ_STACK_SIZE ; Pickup FIQ stack size + CPS #FIQ_MODE ; Enter FIQ mode + ADD r1, r1, r2 ; Calculate start of FIQ stack + BIC r1, r1, #7 ; Ensure 8-byte alignment + MOV sp, r1 ; Setup FIQ stack pointer + MOV sl, #0 ; Clear sl + MOV fp, #0 ; Clear fp + + LDR r2, =ABT_STACK_SIZE ; Pickup ABT stack size + CPS #ABT_MODE ; Enter ABT mode + ADD r1, r1, r2 ; Calculate start of ABT stack + BIC r1, r1, #7 ; Ensure 8-byte alignment + MOV sp, r1 ; Setup ABT stack pointer + + CPS #SYS_MODE ; Enter SYS mode +; +; /* Save the first available memory address. */ +; _tx_initialize_unused_memory = (VOID_PTR) |Image$$ZI$$Limit| + HEAP + SYS_STACK + SVC_STACK + IRQ_STACK + FIQ_STACK + ABT_STACK; +; + ADD r0, r1, #4 ; Increment to next free word + LDR r2, =_tx_initialize_unused_memory ; Pickup unused memory ptr address + STR r0, [r2, #0] ; Save first free memory address +; +; /* Setup Timer for periodic interrupts. */ +; + +GIC1_CPU_INTERFACE_BASE EQU 0x2C002000 +GIC1_DIST_INTERFACE_BASE EQU 0x2C001000 + + PUSH {r4-r12, lr} + ldr r2, =GIC1_CPU_INTERFACE_BASE + ldr r7, =GIC1_DIST_INTERFACE_BASE + ; Enable GIC + mov r3, #0x1 + str r3, [r2, #0x0000] + ; Enable GIC forwarding + str r3, [r7, #0x000] + ; Set Binary Point Register to 0 + eor r3, r3, r3 + str r3, [r2, #0x0008] + + ; At this point GIC is enabled + ; All INTS are disabled / not configured + + ; r0 - interrupt number + ; r1 - priority + ; r2 - interrupt type (edge / level trig.) + ldr r0, =34 + ldr r1, =0xF0 + ldr r2, =1 + + ldr r7, =GIC1_DIST_INTERFACE_BASE + + ; enable the interrupt in isenable register + mov r4, #0x100 ; ISEN REG offset base + mov r5, r0, LSR #5 ; Interrupt_Number DIV 5 + add r4, r4, r5, LSL #2 ; final offset from GIC DIST BASE + and r5, r0, #31 ; bit number + mov r8, #1 + + + ldr r6, [r7, r4] + orr r6, r6, r8, LSL r5 + str r6, [r7, r4] + + ; setup priority + mov r4, #0x400 + mov r5, r0, LSR #2 ; Interrupt_Number DIV 4 + add r4, r4, r5, LSL #2 ; final offset from GIC DIST BASE + and r5, r0, #3 ; Int_Num MOD 4 + lsl r5, #3 + lsl r1, r5 + + ldr r6, [r7, r4] + orr r1, r6, r1 + str r1, [r7, r4] + + ; set up processor target + mov r4, #0x800 + mov r5, r0, LSR #2 ; Interrupt_Number DIV 4 + add r4, r4, r5, LSL #2 ; final offset from GIC DIST BASE + and r5, r0, #3 ; Int_Num MOD 4 + lsl r5, #3 + mov r1, #0xff + lsl r1, r5 + + ldr r6, [r7, r4] + orr r1, r6, r1 + str r1, [r7, r4] + + ; set up interrupt type + mov r4, #0xC00 + mov r5, r0, LSR #4 + add r4, r4, r5, LSL #2 ; offset from base + + ; field + and r5, r0, #15 + lsl r5, #1 + lsl r2, r5 + + ldr r6, [r7, r4] + orr r2, r6, r2 + str r2, [r7, r4] + + ldr r2, =GIC1_CPU_INTERFACE_BASE + + ; set the interrupt id prio mask + ; Max Priorities = 32. + ; mask = (32 - 1) << 3 + mov r3, #0xF8 + str r3, [r2, #0x0004] + + CPSIE if + + ; Timer base + ldr r0, =0x1C110000 + + ; get the timer id + ldr r1, [r0, #0xfe0] + + ; set count value in load register + ldr r1, =0x00000020 + str r1, [r0, #00] + + ; enable the timer + ; periodic mode + mov r1, #0xe2 + str r1, [r0, #08] + + POP {r4-r12, lr} + + + + + + +; +; /* Done, return to caller. */ +; + BX lr ; Return to caller +;} +; +; +;/* Define initial heap/stack routine for the ARM RealView (and ADS) startup code. This +; routine will set the initial stack to use the ThreadX IRQ & FIQ & +; (optionally SYS) stack areas. */ +; + EXPORT __user_initial_stackheap +__user_initial_stackheap + LDR r0, =|Image$$ZI$$Limit| ; Get end of non-initialized RAM area + LDR r2, =HEAP_SIZE ; Pickup the heap size + ADD r2, r2, r0 ; Setup heap limit + ADD r3, r2, #4 ; Setup stack limit + MOV r1, r3 ; Setup start of stack + IF :DEF:TX_ENABLE_IRQ_NESTING + LDR r12, =SYS_STACK_SIZE ; Pickup IRQ system stack + ADD r1, r1, r12 ; Setup the return system stack + BIC r1, r1, #7 ; Ensure 8-byte alignment + ENDIF + LDR r12, =FIQ_STACK_SIZE ; Pickup FIQ stack size + ADD r1, r1, r12 ; Setup the return system stack + BIC r1, r1, #7 ; Ensure 8-byte alignment + LDR r12, =IRQ_STACK_SIZE ; Pickup IRQ system stack + ADD r1, r1, r12 ; Setup the return system stack + BIC r1, r1, #7 ; Ensure 8-byte alignment + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +; +;/* Define shells for each of the interrupt vectors. */ +; + EXPORT __tx_undefined +__tx_undefined + B __tx_undefined ; Undefined handler +; + EXPORT __tx_reserved_handler +__tx_reserved_handler + B __tx_reserved_handler ; Reserved exception handler +; +; + EXPORT __tx_irq_handler + EXPORT __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. In +; addition, IRQ interrupts may be re-enabled - with certain restrictions - +; if nested IRQ interrupts are desired. Interrupts may be re-enabled over +; small code sequences where lr is saved before enabling interrupts and +; restored after interrupts are again disabled. */ +; +; + BL _tx_timer_interrupt ; Timer interrupt handler + + ; clear timer interrupt + ldr r0, =0x1C110000 + eor r1, r1, r1 + str r1, [r0, #0x0C] + +_tx_not_timer_interrupt +; +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; from IRQ mode with interrupts disabled. This routine switches to the +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared +; prior to enabling nested IRQ interrupts. */ + IF :DEF:TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_start + ENDIF +; +; +; /* Application IRQ handlers can be called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_context_restore. +; This routine returns in processing in IRQ mode with interrupts disabled. */ + IF :DEF:TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_end + ENDIF +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore +; +; +; /* This is an example of a vectored IRQ handler. */ +; + EXPORT __tx_example_vectored_irq_handler +__tx_example_vectored_irq_handler +; +; +; /* Save initial context and call context save to prepare for +; vectored ISR execution. */ +; +; STMDB sp!, {r0-r3} ; Save some scratch registers +; MRS r0, SPSR ; Pickup saved SPSR +; SUB lr, lr, #4 ; Adjust point of interrupt +; STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers +; BL _tx_thread_vectored_context_save ; Vectored context save +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. In +; addition, IRQ interrupts may be re-enabled - with certain restrictions - +; if nested IRQ interrupts are desired. Interrupts may be re-enabled over +; small code sequences where lr is saved before enabling interrupts and +; restored after interrupts are again disabled. */ +; +; +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; from IRQ mode with interrupts disabled. This routine switches to the +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared +; prior to enabling nested IRQ interrupts. */ +; IF :DEF:TX_ENABLE_IRQ_NESTING +; BL _tx_thread_irq_nesting_start +; ENDIF +; +; /* Application IRQ handlers can be called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_context_restore. +; This routine returns in processing in IRQ mode with interrupts disabled. */ +; IF :DEF:TX_ENABLE_IRQ_NESTING +; BL _tx_thread_irq_nesting_end +; ENDIF +; +; /* Jump to context restore to restore system context. */ +; B _tx_thread_context_restore +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + EXPORT __tx_fiq_handler + EXPORT __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +; from FIQ mode with interrupts disabled. This routine switches to the +; system mode and returns with FIQ interrupts enabled. +; +; NOTE: It is very important to ensure all FIQ interrupts are cleared +; prior to enabling nested FIQ interrupts. */ + IF :DEF:TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_start + ENDIF +; +; /* Application FIQ handlers can be called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_fiq_context_restore. */ + IF :DEF:TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_end + ENDIF +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore +; +; + ELSE + EXPORT __tx_fiq_handler +__tx_fiq_handler + B __tx_fiq_handler ; FIQ interrupt handler + ENDIF + + + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* __tx_prefetch_handler & __tx_abort_handler Cortex-A7/MMU/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function handles MMU exceptions and fills the */ +;/* _txm_module_manager_memory_fault_info struct. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _txm_module_manager_memory_fault_handler */ +;/* _tx_execution_thread_exit */ +;/* _tx_thread_schedule */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* MMU exceptions */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ + +; ******************************************************************* +; MMU Exception Handling +; ******************************************************************* + EXTERN _tx_thread_system_state + EXTERN _txm_module_manager_memory_fault_info + EXTERN _tx_thread_current_ptr + EXTERN _txm_module_manager_memory_fault_handler + EXTERN _tx_execution_thread_exit + EXTERN _tx_thread_schedule + + EXPORT __tx_prefetch_handler + EXPORT __tx_abort_handler +__tx_prefetch_handler +__tx_abort_handler + STMDB sp!, {r0-r3} ; Save some working registers + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + SUB lr, lr, #4 ; Adjust point of exception +; +; /* Now pickup and store all the fault related information. */ +; + ; Pickup the memory fault info struct + LDR r3, =_txm_module_manager_memory_fault_info + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup the current thread pointer + STR r1, [r3, #0] ; Save current thread pointer + STR lr, [r3, #4] ; Save point of fault + MRC p15, 0, r0, c6, c0, 0 ; Read DFAR + STR r0, [r3, #8] ; Save DFAR + MRC p15, 0, r0, c5, c0, 0 ; Read DFSR + STR r0, [r3, #12] ; Save DFSR + MRC p15, 0, r0, c6, c0, 2 ; Read IFAR + STR r0, [r3, #16] ; Save IFAR + MRC p15, 0, r0, c5, c0, 1 ; Read IFSR + STR r0, [r3, #20] ; Save IFSR + + ; Save registers r0-r12 + POP {r0-r2} + STR r0, [r3, #28] ; Save r0 + STR r1, [r3, #32] ; Save r1 + STR r2, [r3, #36] ; Save r2 + POP {r0} + STR r0, [r3, #40] ; Save r3 + STR r4, [r3, #44] ; Save r4 + STR r5, [r3, #48] ; Save r5 + STR r6, [r3, #52] ; Save r6 + STR r7, [r3, #56] ; Save r7 + STR r8, [r3, #60] ; Save r8 + STR r9, [r3, #64] ; Save r9 + STR r10,[r3, #68] ; Save r10 + STR r11,[r3, #72] ; Save r11 + STR r12,[r3, #76] ; Save r12 + + CPS #SYS_MODE ; Enter SYS mode + MOV r0, lr ; Pickup lr + MOV r1, sp ; Pickup sp + CPS #ABT_MODE ; Back to ABT mode + STR r0, [r3, #80] ; Save lr + STR r1, [r3, #24] ; Save sp + MRS r0, SPSR ; Pickup SPSR + STR r0, [r3, #84] ; Save SPSR + ORR r0, r0, #SYS_MODE ; Return into SYS mode + BIC r0, r0, #THUMB_MASK ; Clear THUMB mode + MSR SPSR_c, r0 ; Save SPSR + + ; Call memory manager fault handler + BL _txm_module_manager_memory_fault_handler + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + BL _tx_execution_thread_exit ; Call the thread exit function + ENDIF + + LDR r0, =_tx_thread_system_state ; Pickup address of system state + LDR r1, [r0] ; Pickup system state + SUB r1, r1, #1 ; Decrement + STR r1, [r0] ; Store new system state + + MOV r1, #0 ; Build NULL value + LDR r0, =_tx_thread_current_ptr ; Pickup address of current thread pointer + STR r1, [r0] ; Clear current thread pointer + + ; Return from exception + LDR lr, =_tx_thread_schedule ; Load scheduler address + MOVS pc, lr ; Return to scheduler +; ******************************************************************* +; End of MMU exception handling. +; ******************************************************************* + +; +; /* Reference build options and version ID to ensure they come in. */ +; + LDR r2, =_tx_build_options ; Pickup build options variable address + LDR r0, [r2, #0] ; Pickup build options content + LDR r2, =_tx_version_id ; Pickup version ID variable address + LDR r0, [r2, #0] ; Pickup version ID content +; +; + END + diff --git a/ports_module/cortex-a7/ac5/example_build/txm_module_preamble.s b/ports_module/cortex-a7/ac5/example_build/txm_module_preamble.s new file mode 100644 index 00000000..168dad31 --- /dev/null +++ b/ports_module/cortex-a7/ac5/example_build/txm_module_preamble.s @@ -0,0 +1,64 @@ + AREA Init, CODE, READONLY + +; /* Define public symbols. */ + + EXPORT __txm_module_preamble + + +; /* Define application-specific start/stop entry points for the module. */ + + IMPORT demo_module_start + + +; /* Define common external refrences. */ + + IMPORT _txm_module_thread_shell_entry + IMPORT _txm_module_callback_request_thread_entry + IMPORT |Image$$ER_RO$$Length| + IMPORT |Image$$ER_RW$$Length| + + +__txm_module_preamble + DCD 0x4D4F4455 ; Module ID + DCD 0x6 ; Module Major Version + DCD 0x1 ; Module Minor Version + DCD 32 ; Module Preamble Size in 32-bit words + DCD 0x12345678 ; Module ID (application defined) + DCD 0x01000001 ; Module Properties where: + ; Bits 31-24: Compiler ID + ; 0 -> IAR + ; 1 -> RVDS + ; 2 -> GNU + ; Bits 23-1: Reserved + ; Bit 0: 0 -> Privileged mode execution (no MMU protection) + ; 1 -> User mode execution (MMU protection) + DCD _txm_module_thread_shell_entry - . + . ; Module Shell Entry Point + DCD demo_module_start - . + . ; Module Start Thread Entry Point + DCD 0 ; Module Stop Thread Entry Point + DCD 1 ; Module Start/Stop Thread Priority + DCD 2046 ; Module Start/Stop Thread Stack Size + DCD _txm_module_callback_request_thread_entry - . + . ; Module Callback Thread Entry + DCD 1 ; Module Callback Thread Priority + DCD 2046 ; Module Callback Thread Stack Size + DCD |Image$$ER_RO$$Length| + |Image$$ER_RW$$Length| ; Module Code Size + DCD 0x4000 ; Module Data Size - default to 16K (need to make sure this is large enough for module's data needs!) + DCD 0 ; Reserved 0 + DCD 0 ; Reserved 1 + DCD 0 ; Reserved 2 + DCD 0 ; Reserved 3 + DCD 0 ; Reserved 4 + DCD 0 ; Reserved 5 + DCD 0 ; Reserved 6 + DCD 0 ; Reserved 7 + DCD 0 ; Reserved 8 + DCD 0 ; Reserved 9 + DCD 0 ; Reserved 10 + DCD 0 ; Reserved 11 + DCD 0 ; Reserved 12 + DCD 0 ; Reserved 13 + DCD 0 ; Reserved 14 + DCD 0 ; Reserved 15 + + END + + diff --git a/ports_module/cortex-a7/ac5/inc/tx_port.h b/ports_module/cortex-a7/ac5/inc/tx_port.h new file mode 100644 index 00000000..d07741ca --- /dev/null +++ b/ports_module/cortex-a7/ac5/inc/tx_port.h @@ -0,0 +1,352 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A7/AC5 */ +/* 6.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ + VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef __thumb + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + b = (ULONG) __clz((unsigned int) m); \ + b = 31 - b; +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifndef __thumb + +#define TX_INTERRUPT_SAVE_AREA register unsigned int interrupt_save_disabled; + +#ifdef TX_ENABLE_FIQ_SUPPORT + +/* IRQ and FIQ support. */ + +#define TX_DISABLE __memory_changed(), interrupt_save_disabled = __disable_irq(); \ + __disable_fiq(); + +#define TX_RESTORE if (!interrupt_save_disabled) \ + { \ + __enable_irq(); \ + __enable_fiq(); \ + } + +#else + +#define TX_DISABLE __memory_changed(), interrupt_save_disabled = __disable_irq(); + +#define TX_RESTORE if (!interrupt_save_disabled) \ + { \ + __enable_irq(); \ + } +#endif + +#else + +unsigned int _tx_thread_interrupt_disable(void); +unsigned int _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); +#endif + + +/* Define VFP extension for the Cortex-A5. Each is assumed to be called in the context of the executing + thread. */ + +void tx_thread_vfp_enable(void); +void tx_thread_vfp_disable(void); + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/AC5 Version 6.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + diff --git a/ports_module/cortex-a7/ac5/inc/txm_module_port.h b/ports_module/cortex-a7/ac5/inc/txm_module_port.h new file mode 100644 index 00000000..fd534dc7 --- /dev/null +++ b/ports_module/cortex-a7/ac5/inc/txm_module_port.h @@ -0,0 +1,413 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Interface (API) */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* txm_module_port.h Cortex-A7/MMU/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the basic module constants, interface structures, */ +/* and function prototypes. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TXM_MODULE_PORT_H +#define TXM_MODULE_PORT_H + +/* It is assumed that the base ThreadX tx_port.h file has been modified to add the + following extensions to the ThreadX thread control block (this code should replace + the corresponding macro define in tx_port.h): + +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ + VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; + + +The following extensions must also be defined in tx_port.h: + +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); + +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); +*/ + +/* Define the kernel stack size for a module thread. */ +#ifndef TXM_MODULE_KERNEL_STACK_SIZE +#define TXM_MODULE_KERNEL_STACK_SIZE 512 +#endif + +/* Defined, this option enables the MMU hardware and requires memory protected + module objects to be allocated from the module manager object pool. + If this is undefined, module objects can be created in the module's data area + or in the module manager object pool. If this is not defined (MMU hardware + is disabled), a module requiring memory protection will not run (the load + functions will return a TXM_MODULE_INVALID_PROPERTIES error). + Default setting for this value is defined. */ +#define TXM_MODULE_MEMORY_PROTECTION_ENABLED + +/* Define constants specific to the tools the module can be built with for this particular modules port. */ + +#define TXM_MODULE_IAR_COMPILER 0x00000000 +#define TXM_MODULE_RVDS_COMPILER 0x01000000 +#define TXM_MODULE_GNU_COMPILER 0x02000000 +#define TXM_MODULE_COMPILER_MASK 0xFF000000 +#define TXM_MODULE_OPTIONS_MASK 0x000000FF + + +/* Define the properties for this particular module port. */ +#ifdef TXM_MODULE_MEMORY_PROTECTION_ENABLED +#define TXM_MODULE_MEMORY_PROTECTION 0x00000001 +#else +#define TXM_MODULE_MEMORY_PROTECTION 0x00000000 +#endif + +#define TXM_MODULE_USER_MODE 0x00000001 + +/* Define the supported options for this module. */ + +#define TXM_MODULE_MANAGER_SUPPORTED_OPTIONS (TXM_MODULE_MEMORY_PROTECTION) +#define TXM_MODULE_MANAGER_REQUIRED_OPTIONS 0 + + +/* Define offset adjustments according to the compiler used to build the module. */ + +#define TXM_MODULE_IAR_SHELL_ADJUST 24 +#define TXM_MODULE_IAR_START_ADJUST 28 +#define TXM_MODULE_IAR_STOP_ADJUST 32 +#define TXM_MODULE_IAR_CALLBACK_ADJUST 44 + +#define TXM_MODULE_RVDS_SHELL_ADJUST 0 +#define TXM_MODULE_RVDS_START_ADJUST 0 +#define TXM_MODULE_RVDS_STOP_ADJUST 0 +#define TXM_MODULE_RVDS_CALLBACK_ADJUST 0 + +#define TXM_MODULE_GNU_SHELL_ADJUST 24 +#define TXM_MODULE_GNU_START_ADJUST 28 +#define TXM_MODULE_GNU_STOP_ADJUST 32 +#define TXM_MODULE_GNU_CALLBACK_ADJUST 44 + + +/* Define other module port-specific constants. */ + +/* Define INLINE_DECLARE to whitespace for ARM compiler. */ +#define INLINE_DECLARE + +#define TXM_MAXIMUM_MODULES 16 +#define TXM_MODULE_LEVEL1_PAGE_TABLE_SIZE 32 +#define TXM_ASID_TABLE_LENGTH 256 + +#define TXM_MODULE_CODE_PAGE_TABLE_START_OFFSET (TXM_MAXIMUM_MODULES * 0) +#define TXM_MODULE_CODE_PAGE_TABLE_END_OFFSET (TXM_MAXIMUM_MODULES * 1) +#define TXM_MODULE_DATA_PAGE_TABLE_START_OFFSET (TXM_MAXIMUM_MODULES * 2) +#define TXM_MODULE_DATA_PAGE_TABLE_END_OFFSET (TXM_MAXIMUM_MODULES * 3) + +#define TXM_MASTER_PAGE_TABLE_INDEX 0 + +/* 1 entry per 1MB, so this covers 4G address space */ +#define TXM_MASTER_PAGE_TABLE_ENTRIES 4096 + +/* Smallest MMU page size is 4kB. */ +#define TXM_MODULE_MEMORY_ALIGNMENT 4096 +#define TXM_MMU_LEVEL1_PAGE_SHIFT 20 +#define TXM_MMU_LEVEL2_PAGE_SHIFT 12 +#define TXM_LEVEL_2_PAGE_TABLE_ENTRIES 256 + +/* Level 1 section base address mask. */ +#define TXM_MMU_LEVEL1_MASK 0xFFF00000 + +/* Level 2 section base address mask. */ +#define TXM_MMU_LEVEL2_MASK 0xFFFFF000 + +/* Non-global, outer & inner write-back, write-allocate, user read, no write. */ +#define TXM_MMU_LEVEL1_CODE_ATTRIBUTES 0x000219EE +/* Non-global, outer & inner write-back, write-allocate, user read, write, no-execute. */ +#define TXM_MMU_LEVEL1_DATA_ATTRIBUTES 0x00021DFE + +/* Level 1 "level 2 descriptor base address" mask. */ +#define TXM_MMU_LEVEL1_SECOND_MASK 0xFFFFFC00 + +/* Level 1 "level 2 descriptor" attributes. */ +#define TXM_MMU_LEVEL1_SECOND_ATTRIBUTES 0x0000001E1 + +/* Kernel level 2 attributes: global, outer & inner write-back, write-allocate, user read/write */ +#define TXM_MMU_KERNEL_LEVEL2_CODE_ATTRIBUTES 0x0000006E +#define TXM_MMU_KERNEL_LEVEL2_DATA_ATTRIBUTES 0x0000005E + +/* Module level 2 attributes: non-global, outer & inner write-back, write-allocate, user read, no write. */ +#define TXM_MMU_LEVEL2_CODE_ATTRIBUTES 0x0000086E +#define TXM_MMU_LEVEL2_DATA_ATTRIBUTES 0x0000087F + + +/* Settings the user can use to set up shared memory attributes. */ +#define TXM_MMU_ATTRIBUTE_XN 0x00000001 +#define TXM_MMU_ATTRIBUTE_B 0x00000002 +#define TXM_MMU_ATTRIBUTE_C 0x00000004 +#define TXM_MMU_ATTRIBUTE_AP 0x00000018 +#define TXM_MMU_ATTRIBUTE_TEX 0x000000E0 + +/* Masks for each attribute. */ +#define TXM_MMU_ATTRIBUTE_XN_MASK 0x00000001 +#define TXM_MMU_ATTRIBUTE_B_MASK 0x00000001 +#define TXM_MMU_ATTRIBUTE_C_MASK 0x00000001 +#define TXM_MMU_ATTRIBUTE_AP_MASK 0x00000003 +#define TXM_MMU_ATTRIBUTE_TEX_MASK 0x00000007 + +/* Shift amounts for bitfields above to correct register locations. */ +#define TXM_MMU_LEVEL1_USER_ATTRIBUTE_XN_SHIFT 4 +#define TXM_MMU_LEVEL1_USER_ATTRIBUTE_B_SHIFT 1 +#define TXM_MMU_LEVEL1_USER_ATTRIBUTE_C_SHIFT 1 +#define TXM_MMU_LEVEL1_USER_ATTRIBUTE_AP_SHIFT 7 +#define TXM_MMU_LEVEL1_USER_ATTRIBUTE_TEX_SHIFT 7 +#define TXM_MMU_LEVEL1_USER_ATTRIBUTE_BASE 0x000201E2 + +#define TXM_MMU_LEVEL2_USER_ATTRIBUTE_XN_SHIFT 0 +#define TXM_MMU_LEVEL2_USER_ATTRIBUTE_B_SHIFT 1 +#define TXM_MMU_LEVEL2_USER_ATTRIBUTE_C_SHIFT 1 +#define TXM_MMU_LEVEL2_USER_ATTRIBUTE_AP_SHIFT 1 +#define TXM_MMU_LEVEL2_USER_ATTRIBUTE_TEX_SHIFT 1 +#define TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE 0x00000802 + +/* Shift amounts from bit 0 position. */ +#define TXM_MMU_LEVEL1_ATTRIBUTE_XN_SHIFT 4 +#define TXM_MMU_LEVEL1_ATTRIBUTE_B_SHIFT 2 +#define TXM_MMU_LEVEL1_ATTRIBUTE_C_SHIFT 3 +#define TXM_MMU_LEVEL1_ATTRIBUTE_AP_SHIFT 10 +#define TXM_MMU_LEVEL1_ATTRIBUTE_TEX_SHIFT 12 + +#define TXM_MMU_LEVEL2_ATTRIBUTE_XN_SHIFT 0 +#define TXM_MMU_LEVEL2_ATTRIBUTE_B_SHIFT 2 +#define TXM_MMU_LEVEL2_ATTRIBUTE_C_SHIFT 3 +#define TXM_MMU_LEVEL2_ATTRIBUTE_AP_SHIFT 4 +#define TXM_MMU_LEVEL2_ATTRIBUTE_TEX_SHIFT 6 + +/* Masks for L1 page attributes. */ +#define TXM_MMU_LEVEL1_ATTRIBUTE_XN_MASK (TXM_MMU_ATTRIBUTE_XN_MASK << TXM_MMU_LEVEL1_ATTRIBUTE_XN_SHIFT) +#define TXM_MMU_LEVEL1_ATTRIBUTE_B_MASK (TXM_MMU_ATTRIBUTE_B_MASK << TXM_MMU_LEVEL1_ATTRIBUTE_B_SHIFT) +#define TXM_MMU_LEVEL1_ATTRIBUTE_C_MASK (TXM_MMU_ATTRIBUTE_C_MASK << TXM_MMU_LEVEL1_ATTRIBUTE_C_SHIFT) +#define TXM_MMU_LEVEL1_ATTRIBUTE_AP_MASK (TXM_MMU_ATTRIBUTE_AP_MASK << TXM_MMU_LEVEL1_ATTRIBUTE_AP_SHIFT) +#define TXM_MMU_LEVEL1_ATTRIBUTE_TEX_MASK (TXM_MMU_ATTRIBUTE_TEX_MASK << TXM_MMU_LEVEL1_ATTRIBUTE_TEX_SHIFT) + +/* Masks for L2 page attributes. */ +#define TXM_MMU_LEVEL2_ATTRIBUTE_XN_MASK (TXM_MMU_ATTRIBUTE_XN_MASK << TXM_MMU_LEVEL2_ATTRIBUTE_XN_SHIFT) +#define TXM_MMU_LEVEL2_ATTRIBUTE_B_MASK (TXM_MMU_ATTRIBUTE_B_MASK << TXM_MMU_LEVEL2_ATTRIBUTE_B_SHIFT) +#define TXM_MMU_LEVEL2_ATTRIBUTE_C_MASK (TXM_MMU_ATTRIBUTE_C_MASK << TXM_MMU_LEVEL2_ATTRIBUTE_C_SHIFT) +#define TXM_MMU_LEVEL2_ATTRIBUTE_AP_MASK (TXM_MMU_ATTRIBUTE_AP_MASK << TXM_MMU_LEVEL2_ATTRIBUTE_AP_SHIFT) +#define TXM_MMU_LEVEL2_ATTRIBUTE_TEX_MASK (TXM_MMU_ATTRIBUTE_TEX_MASK << TXM_MMU_LEVEL2_ATTRIBUTE_TEX_SHIFT) + +#define TXM_ADDRESS_TRANSLATION_FAULT_BIT 1 + +#define TXM_ASID_RESERVED 0xFFFFFFFF + +#define TXM_MODULE_ASID_ERROR 0xF6 +#define TXM_MODULE_EXTERNAL_MEMORY_ENABLE_ERROR 0xF7 + +/* Number of L2 pages each module can have. */ +#define TXM_MODULE_LEVEL2_EXTERNAL_PAGES 16 +/* Size, in pages, of the L2 page pool. */ +#define TXM_LEVEL2_EXTERNAL_POOL_PAGES (TXM_MODULE_LEVEL2_EXTERNAL_PAGES * TXM_MAXIMUM_MODULES) + + +/* Define the port-extensions to the module manager instance structure. */ + +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + ULONG txm_module_instance_asid; \ + ULONG *txm_external_page_table[TXM_MODULE_LEVEL2_EXTERNAL_PAGES]; + +/* Define the memory fault information structure that is populated when a memory fault occurs. */ + + +typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT +{ + TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr; + VOID *txm_module_manager_memory_fault_info_code_location; + ULONG txm_module_manager_memory_fault_info_dfar; + ULONG txm_module_manager_memory_fault_info_dfsr; + ULONG txm_module_manager_memory_fault_info_ifar; + ULONG txm_module_manager_memory_fault_info_ifsr; + ULONG txm_module_manager_memory_fault_info_sp; + ULONG txm_module_manager_memory_fault_info_r0; + ULONG txm_module_manager_memory_fault_info_r1; + ULONG txm_module_manager_memory_fault_info_r2; + ULONG txm_module_manager_memory_fault_info_r3; + ULONG txm_module_manager_memory_fault_info_r4; + ULONG txm_module_manager_memory_fault_info_r5; + ULONG txm_module_manager_memory_fault_info_r6; + ULONG txm_module_manager_memory_fault_info_r7; + ULONG txm_module_manager_memory_fault_info_r8; + ULONG txm_module_manager_memory_fault_info_r9; + ULONG txm_module_manager_memory_fault_info_r10; + ULONG txm_module_manager_memory_fault_info_r11; + ULONG txm_module_manager_memory_fault_info_r12; + ULONG txm_module_manager_memory_fault_info_lr; + ULONG txm_module_manager_memory_fault_info_cpsr; +} TXM_MODULE_MANAGER_MEMORY_FAULT_INFO; + + +#define TXM_MODULE_MANAGER_FAULT_INFO \ + TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info; + +/* Define the macro to check the stack available in dispatch. */ +#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE + + +/* Define the macro to check the code alignment. */ + +#define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment) \ + { \ + ULONG temp; \ + temp = (ULONG) module_location; \ + temp = temp & (TXM_MODULE_MEMORY_ALIGNMENT - 1); \ + if (temp) \ + { \ + _tx_mutex_put(&_txm_module_manager_mutex); \ + return(TXM_MODULE_ALIGNMENT_ERROR); \ + } \ + } + + +/* Define the macro to adjust the alignment and size for code/data areas. */ + +#define TXM_MODULE_MANAGER_ALIGNMENT_ADJUST(module_preamble, code_size, code_alignment, data_size, data_alignment) _txm_module_manager_alignment_adjust(module_preamble, &code_size, &code_alignment, &data_size, &data_alignment); + + +/* Define the macro to adjust the symbols in the module preamble. */ + +#define TXM_MODULE_MANAGER_CALCULATE_ADJUSTMENTS(properties, shell_function_adjust, start_function_adjust, stop_function_adjust, callback_function_adjust) \ + if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_IAR_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_IAR_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_IAR_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_IAR_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_IAR_CALLBACK_ADJUST; \ + } \ + else if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_RVDS_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_RVDS_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_RVDS_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_RVDS_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_RVDS_CALLBACK_ADJUST; \ + } \ + else \ + { \ + shell_function_adjust = TXM_MODULE_GNU_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_GNU_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_GNU_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_GNU_CALLBACK_ADJUST; \ + } + + +/* Define the macro to populate the thread control block with module port-specific information. */ + +#define TXM_MODULE_MANAGER_THREAD_SETUP(thread_ptr, module_instance) \ + thread_ptr -> tx_thread_module_current_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION; \ + thread_ptr -> tx_thread_module_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION; \ + if (thread_ptr -> tx_thread_module_user_mode) \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_user_mode_entry; \ + } \ + else \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_kernel_dispatch; \ + } + + +/* Define the macro to populate the module control block with module port-specific information. + If memory protection is enabled, set up the MMU registers. +*/ +#define TXM_MODULE_MANAGER_MODULE_SETUP(module_instance) \ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) \ + { \ + _txm_module_manager_mm_register_setup(module_instance); \ + } \ + else \ + { \ + /* Do nothing. */ \ + } + +/* Define the macro to perform port-specific functions when unloading the module. */ +#define TXM_MODULE_MANAGER_MODULE_UNLOAD(module_instance) \ + _txm_level2_page_clear(module_instance); \ + _txm_module_manager_remove_asid(module_instance); + +/* Define the macros to perform port-specific checks when passing pointers to the kernel. */ + +/* Define macro to make sure object is inside the module's data or shared memory. */ +#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ + _txm_module_manager_inside_data_check((ULONG) obj_ptr) + + +/* Define some internal prototypes to this module port. */ + +#ifndef TX_SOURCE_CODE +#define txm_module_manager_memory_fault_notify _txm_module_manager_memory_fault_notify +#define txm_module_manager_mm_initialize _txm_module_manager_mm_initialize +#endif + + +#define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES \ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment); \ +ULONG _txm_module_manager_data_pointer_check(ULONG pointer); \ +VOID _txm_module_manager_memory_fault_handler(VOID); \ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)); \ +UINT _txm_module_manager_mm_initialize(VOID); \ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \ +VOID _txm_level2_page_clear(TXM_MODULE_INSTANCE *module_instance); \ +VOID _txm_module_manager_remove_asid(TXM_MODULE_INSTANCE *module_instance); \ +UINT _txm_module_manager_inside_data_check(ULONG pointer); + +#define TXM_MODULE_MANAGER_VERSION_ID \ +CHAR _txm_module_manager_version_id[] = \ + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-A7/MMU/AC5 Version 6.1 *"; + +#endif + diff --git a/ports_module/cortex-a7/ac5/module_lib/src/txm_module_initialize.s b/ports_module/cortex-a7/ac5/module_lib/src/txm_module_initialize.s new file mode 100644 index 00000000..f0ea4f61 --- /dev/null +++ b/ports_module/cortex-a7/ac5/module_lib/src/txm_module_initialize.s @@ -0,0 +1,91 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Module */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +; + IMPORT __scatterload + + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _txm_module_initialize Cortex-A7/MMU/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function initializes the module c runtime. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* __scatterload Initialize C runtime */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _txm_module_thread_shell_entry Start module thread */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _txm_module_initialize(VOID) +;{ + EXPORT _txm_module_initialize +_txm_module_initialize + PUSH {r4-r12,lr} ; Save dregs and LR + + B __scatterload ; Call ARM func to initialize variables + +;/* Override __rt_exit function. */ + EXPORT __rt_exit +__rt_exit + + POP {r4-r12,lr} ; Restore dregs and LR + BX lr ; Return to caller +;} + + END + diff --git a/ports_module/cortex-a7/ac5/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex-a7/ac5/module_lib/src/txm_module_thread_shell_entry.c new file mode 100644 index 00000000..7504c7fe --- /dev/null +++ b/ports_module/cortex-a7/ac5/module_lib/src/txm_module_thread_shell_entry.c @@ -0,0 +1,175 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#ifndef TXM_MODULE +#define TXM_MODULE +#endif + +#ifndef TX_SOURCE_CODE +#define TX_SOURCE_CODE +#endif + + +/* Include necessary system files. */ + +#include "txm_module.h" + + +/* Define the global module entry pointer from the start thread of the module. */ + +TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; + + +/* Define the dispatch function pointer used in the module implementation. */ + +ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3); + + + +/* Define the RVDS startup code that clears the uninitialized global data and sets up the + preset global variables. */ +extern VOID _txm_module_initialize(VOID); +int main(VOID){return 0;} +VOID __user_setup_stackheap(VOID){return;} + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_thread_shell_entry Cortex-A7/MMU/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calls the specified entry function of the thread. It */ +/* also provides a place for the thread's entry function to return. */ +/* If the thread returns, this function places the thread in a */ +/* "COMPLETED" state. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to current thread */ +/* thread_info Pointer to thread entry info */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __rt_lib_init RVDS global init function */ +/* thread_entry Thread's entry function */ +/* tx_thread_resume Resume the module callback thread */ +/* txm_module_thread_system_suspend Module thread suspension routine */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) +{ + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + VOID (*entry_exit_notify)(TX_THREAD *, UINT); +#endif + + + /* Determine if this is the start thread. If so, we must prepare the module for + execution. If not, simply skip the C startup code. */ + if (thread_info -> txm_module_thread_entry_info_start_thread) + { + /* Initialize the RVDS C environment. */ + _txm_module_initialize(); + + /* Save the entry info pointer, for later use. */ + _txm_module_entry_info = thread_info; + + /* Save the kernel function dispatch address. This is used to make all resident calls from + the module. */ + _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; + + /* Ensure that we have a valid pointer. */ + while (!_txm_module_kernel_call_dispatcher) + { + /* Loop here, if an error is present getting the dispatch function pointer! + An error here typically indicates the resident portion of _tx_thread_schedule + is not supporting the trap to obtain the function pointer. */ + } + + /* Resume the module's callback thread, already created in the manager. */ + _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); + } + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has been entered! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_ENTRY); + } +#endif + + /* Call current thread's entry function. */ + (thread_info -> txm_module_thread_entry_info_entry) (thread_info -> txm_module_thread_entry_info_parameter); + + /* Suspend thread with a "completed" state. */ + + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine again. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has exited! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_EXIT); + } +#endif + + /* Call actual thread suspension routine. */ + _txm_module_thread_system_suspend(thread_ptr); + +#ifdef TX_SAFETY_CRITICAL + + /* If we ever get here, raise safety critical exception. */ + TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0); +#endif +} + diff --git a/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_context_restore.s new file mode 100644 index 00000000..f67f1f01 --- /dev/null +++ b/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_context_restore.s @@ -0,0 +1,260 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + +IRQ_MODE EQU 0x12 ; IRQ mode +SVC_MODE EQU 0x13 ; SVC mode +SYS_MODE EQU 0x1F ; SYS mode +THUMB_MASK EQU 0x20 ; Thumb bit mask + + IF :DEF:TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts + ELSE +DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts + ENDIF +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_execute_ptr + IMPORT _tx_timer_time_slice + IMPORT _tx_thread_schedule + IMPORT _tx_thread_preempt_disable + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_exit + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-A7/MMU/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + EXPORT _tx_thread_context_restore +_tx_thread_context_restore +; +; /* Lockout interrupts. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + BL _tx_execution_isr_exit ; Call the ISR exit function + ENDIF +; +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state) +; { +; + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + SUB r2, r2, #1 ; Decrement the counter + STR r2, [r3, #0] ; Store the counter + CMP r2, #0 ; Was this the first interrupt? + BEQ __tx_thread_not_nested_restore ; If so, not a nested restore +; +; /* Interrupts are nested. */ +; +; /* Just recover the saved registers and return to the point of +; interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +__tx_thread_not_nested_restore +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; || (_tx_thread_preempt_disable)) +; { +; + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup actual current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_restore ; Yes, idle system was interrupted +; + LDR r3, =_tx_thread_preempt_disable ; Pickup preempt disable address + LDR r2, [r3, #0] ; Pickup actual preempt disable flag + CMP r2, #0 ; Is it set? + BNE __tx_thread_no_preempt_restore ; Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr ; Pickup address of execute thread ptr + LDR r2, [r3, #0] ; Pickup actual execute thread pointer + CMP r0, r2 ; Is the same thread highest priority? + BNE __tx_thread_preempt_restore ; No, preemption needs to happen +; +; +__tx_thread_no_preempt_restore +; +; /* Restore interrupted thread or ISR. */ +; +; /* Pickup the saved stack pointer. */ +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; +; /* Recover the saved context and return to the point of interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +; else +; { +__tx_thread_preempt_restore +; + LDMIA sp!, {r3, r10, r12, lr} ; Recover temporarily saved registers + MOV r1, lr ; Save lr (point of interrupt) + CPS #SYS_MODE ; Enter SYS mode + STR r1, [sp, #-4]! ; Save point of interrupt on thread's stack + STMDB sp!, {r4-r12, lr} ; Save upper half of registers on thread's stack + MOV r4, r3 ; Save SPSR in r4 + CPS #IRQ_MODE ; Enter IRQ mode + LDMIA sp!, {r0-r3} ; Recover r0-r3 + CPS #SYS_MODE ; Enter SYS mode + STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + + IF {TARGET_FPU_VFP} = {TRUE} + LDR r2, [r0, #144] ; Pickup the VFP enabled flag + CMP r2, #0 ; Is the VFP enabled? + BEQ _tx_skip_irq_vfp_save ; No, skip VFP IRQ save + VMRS r2, FPSCR ; Pickup the FPSCR + STR r2, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D0-D15} ; Save D0-D15 +_tx_skip_irq_vfp_save + ENDIF + + MOV r3, #1 ; Build interrupt stack type + STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR + STR sp, [r0, #8] ; Save stack pointer in thread control + ; block +; +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup time-slice variable address + LDR r2, [r3, #0] ; Pickup time-slice + CMP r2, #0 ; Is it active? + BEQ __tx_thread_dont_save_ts ; No, don't save it +; +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r2, [r0, #24] ; Save thread's time-slice + MOV r2, #0 ; Clear value + STR r2, [r3, #0] ; Disable global time-slice flag +; +; } +__tx_thread_dont_save_ts +; +; +; /* Clear the current task pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + MOV r0, #0 ; NULL value + STR r0, [r1, #0] ; Clear current thread pointer +; +; /* Return to the scheduler. */ +; _tx_thread_schedule(); +; + CPS #IRQ_MODE ; Enter IRQ mode + MRS r1, SPSR ; Get SPSR + ORR r1, r1, #SYS_MODE ; Change to SYS Mode + BIC r1, r1, #THUMB_MASK ; Clear thumb bit + MSR SPSR_cxsf, r1 ; Put SYS Mode in SPSR + LDR lr, =_tx_thread_schedule ; Load scheduler address + MOVS pc, lr ; Return to scheduler +; } +; +__tx_thread_idle_system_restore +; +; /* Just return back to the scheduler! */ +; + LDR lr, =_tx_thread_schedule ; Load scheduler address + MOVS pc, lr ; Return to scheduler +;} +; + END + diff --git a/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_context_save.s b/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_context_save.s new file mode 100644 index 00000000..086437a3 --- /dev/null +++ b/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_context_save.s @@ -0,0 +1,199 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IMPORT __tx_irq_processing_return + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_enter + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-A7/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + EXPORT _tx_thread_context_save +_tx_thread_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + STMDB sp!, {r0-r3} ; Save some working registers + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable FIQ interrupts + ENDIF + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Save the rest of the scratch registers on the stack and return to the +; calling ISR. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + B __tx_irq_processing_return ; Continue IRQ processing +; +__tx_thread_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + ; scheduling loop - nothing needs saving! +; +; /* Save minimal context of interrupted thread. */ +; + MRS r2, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r2, r10, r12, lr} ; Store other registers +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + B __tx_irq_processing_return ; Continue IRQ processing +; +; } +; else +; { +; +__tx_thread_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; processing. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + ADD sp, sp, #16 ; Recover saved registers + B __tx_irq_processing_return ; Continue IRQ processing +; +; } +;} +; + END + diff --git a/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_fiq_context_restore.s b/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_fiq_context_restore.s new file mode 100644 index 00000000..9fba762b --- /dev/null +++ b/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_fiq_context_restore.s @@ -0,0 +1,258 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +SVC_MODE EQU 0xD3 ; SVC mode +FIQ_MODE EQU 0xD1 ; FIQ mode +MODE_MASK EQU 0x1F ; Mode mask +IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_system_stack_ptr + IMPORT _tx_thread_execute_ptr + IMPORT _tx_timer_time_slice + IMPORT _tx_thread_schedule + IMPORT _tx_thread_preempt_disable + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_exit + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_restore Cortex-A7/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the fiq interrupt context when processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* FIQ ISR Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_context_restore(VOID) +;{ + EXPORT _tx_thread_fiq_context_restore +_tx_thread_fiq_context_restore +; +; /* Lockout interrupts. */ +; + CPSID if ; Disable IRQ and FIQ interrupts + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + BL _tx_execution_isr_exit ; Call the ISR exit function + ENDIF +; +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state) +; { +; + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3] ; Pickup system state + SUB r2, r2, #1 ; Decrement the counter + STR r2, [r3] ; Store the counter + CMP r2, #0 ; Was this the first interrupt? + BEQ __tx_thread_fiq_not_nested_restore ; If so, not a nested restore +; +; /* Interrupts are nested. */ +; +; /* Just recover the saved registers and return to the point of +; interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +__tx_thread_fiq_not_nested_restore +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; || (_tx_thread_preempt_disable)) +; { +; + LDR r1, [sp] ; Pickup the saved SPSR + MOV r2, #MODE_MASK ; Build mask to isolate the interrupted mode + AND r1, r1, r2 ; Isolate mode bits + CMP r1, #IRQ_MODE_BITS ; Was an interrupt taken in IRQ mode before we + ; got to context save? */ + BEQ __tx_thread_fiq_no_preempt_restore ; Yes, just go back to point of interrupt + + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup actual current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_fiq_idle_system_restore ; Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable ; Pickup preempt disable address + LDR r2, [r3] ; Pickup actual preempt disable flag + CMP r2, #0 ; Is it set? + BNE __tx_thread_fiq_no_preempt_restore ; Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr ; Pickup address of execute thread ptr + LDR r2, [r3] ; Pickup actual execute thread pointer + CMP r0, r2 ; Is the same thread highest priority? + BNE __tx_thread_fiq_preempt_restore ; No, preemption needs to happen + + +__tx_thread_fiq_no_preempt_restore +; +; /* Restore interrupted thread or ISR. */ +; +; /* Pickup the saved stack pointer. */ +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; +; /* Recover the saved context and return to the point of interrupt. */ +; + LDMIA sp!, {r0, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +; else +; { +__tx_thread_fiq_preempt_restore +; + LDMIA sp!, {r3, lr} ; Recover temporarily saved registers + MOV r1, lr ; Save lr (point of interrupt) + MOV r2, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r2 ; Enter SVC mode + STR r1, [sp, #-4]! ; Save point of interrupt + STMDB sp!, {r4-r12, lr} ; Save upper half of registers + MOV r4, r3 ; Save SPSR in r4 + MOV r2, #FIQ_MODE ; Build FIQ mode CPSR + MSR CPSR_c, r2 ; Re-enter FIQ mode + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOV r5, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r5 ; Enter SVC mode + STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup current thread pointer + + IF {TARGET_FPU_VFP} = {TRUE} + LDR r2, [r0, #144] ; Pickup the VFP enabled flag + CMP r2, #0 ; Is the VFP enabled? + BEQ _tx_skip_fiq_vfp_save ; No, skip VFP FIQ save + VMRS r2, FPSCR ; Pickup the FPSCR + STR r2, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D0-D15} ; Save D0-D15 +_tx_skip_fiq_vfp_save + ENDIF + + MOV r3, #1 ; Build interrupt stack type + STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR + STR sp, [r0, #8] ; Save stack pointer in thread control + ; block +; +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup time-slice variable address + LDR r2, [r3] ; Pickup time-slice + CMP r2, #0 ; Is it active? + BEQ __tx_thread_fiq_dont_save_ts ; No, don't save it +; +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r2, [r0, #24] ; Save thread's time-slice + MOV r2, #0 ; Clear value + STR r2, [r3] ; Disable global time-slice flag +; +; } +__tx_thread_fiq_dont_save_ts +; +; +; /* Clear the current task pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + MOV r0, #0 ; NULL value + STR r0, [r1] ; Clear current thread pointer +; +; /* Return to the scheduler. */ +; _tx_thread_schedule(); +; + B _tx_thread_schedule ; Return to scheduler +; } +; +__tx_thread_fiq_idle_system_restore +; +; /* Just return back to the scheduler! */ +; + ADD sp, sp, #24 ; Recover FIQ stack space + MOV r3, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r3 ; Enter SVC mode + B _tx_thread_schedule ; Return to scheduler +; +;} +; + END + diff --git a/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_fiq_context_save.s b/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_fiq_context_save.s new file mode 100644 index 00000000..0ac665b1 --- /dev/null +++ b/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_fiq_context_save.s @@ -0,0 +1,203 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IMPORT __tx_fiq_processing_return + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_enter + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_save Cortex-A7/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +; VOID _tx_thread_fiq_context_save(VOID) +;{ + EXPORT _tx_thread_fiq_context_save +_tx_thread_fiq_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + STMDB sp!, {r0-r3} ; Save some working registers + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_fiq_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3] ; Store it back in the variable +; +; /* Save the rest of the scratch registers on the stack and return to the +; calling ISR. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + B __tx_fiq_processing_return ; Continue FIQ processing +; +__tx_thread_fiq_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in +; ; scheduling loop - nothing needs saving! +; +; /* Save minimal context of interrupted thread. */ +; + MRS r2, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r2, lr} ; Store other registers, Note that we don't +; ; need to save sl and ip since FIQ has +; ; copies of these registers. Nested +; ; interrupt processing does need to save +; ; these registers. +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + B __tx_fiq_processing_return ; Continue FIQ processing +; +; } +; else +; { +; +__tx_thread_fiq_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF +; +; /* Not much to do here, save the current SPSR and LR for possible +; use in IRQ interrupted in idle system conditions, and return to +; FIQ interrupt processing. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, lr} ; Store other registers that will get used +; ; or stripped off the stack in context +; ; restore + B __tx_fiq_processing_return ; Continue FIQ processing +; +; } +;} +; + END + diff --git a/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_fiq_nesting_end.s b/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_fiq_nesting_end.s new file mode 100644 index 00000000..f36c3d0f --- /dev/null +++ b/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_fiq_nesting_end.s @@ -0,0 +1,111 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts + ELSE +DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts + ENDIF +MODE_MASK EQU 0x1F ; Mode mask +FIQ_MODE_BITS EQU 0x11 ; FIQ mode bits +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_end Cortex-A7/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +;/* processing from system mode back to FIQ mode prior to the ISR */ +;/* calling _tx_thread_fiq_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_nesting_end(VOID) +;{ + EXPORT _tx_thread_fiq_nesting_end +_tx_thread_fiq_nesting_end + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value + MSR CPSR_c, r0 ; Disable interrupts + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + ; 8-byte alignment logic) + BIC r0, r0, #MODE_MASK ; Clear mode bits + ORR r0, r0, #FIQ_MODE_BITS ; Build IRQ mode CPSR + MSR CPSR_c, r0 ; Re-enter IRQ mode + IF {INTER} = {TRUE} + BX r3 ; Return to caller + ELSE + MOV pc, r3 ; Return to caller + ENDIF +;} +; + END + diff --git a/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_fiq_nesting_start.s b/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_fiq_nesting_start.s new file mode 100644 index 00000000..005e8bc2 --- /dev/null +++ b/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_fiq_nesting_start.s @@ -0,0 +1,104 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +FIQ_DISABLE EQU 0x40 ; FIQ disable bit +MODE_MASK EQU 0x1F ; Mode mask +SYS_MODE_BITS EQU 0x1F ; System mode bits +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_start Cortex-A7/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +;/* processing to the system mode so nested FIQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_nesting_start(VOID) +;{ + EXPORT _tx_thread_fiq_nesting_start +_tx_thread_fiq_nesting_start + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + BIC r0, r0, #MODE_MASK ; Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS ; Build system mode CPSR + MSR CPSR_c, r0 ; Enter system mode + STMDB sp!, {r1, lr} ; Push the system mode lr on the system mode stack + ; and push r1 just to keep 8-byte alignment + BIC r0, r0, #FIQ_DISABLE ; Build enable FIQ CPSR + MSR CPSR_c, r0 ; Enter system mode + IF {INTER} = {TRUE} + BX r3 ; Return to caller + ELSE + MOV pc, r3 ; Return to caller + ENDIF +;} +; + END + diff --git a/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..f219c40b --- /dev/null +++ b/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_interrupt_control.s @@ -0,0 +1,102 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT +INT_MASK EQU 0xC0 ; Interrupt bit mask + ELSE +INT_MASK EQU 0x80 ; Interrupt bit mask + ENDIF +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-A7/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + EXPORT _tx_thread_interrupt_control +_tx_thread_interrupt_control +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r3, CPSR ; Pickup current CPSR + BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits + ORR r1, r1, r0 ; Or-in new interrupt lockout bits +; +; /* Apply the new interrupt posture. */ +; + MSR CPSR_c, r1 ; Setup new CPSR + AND r0, r3, #INT_MASK ; Return previous interrupt mask + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +;} +; + END + diff --git a/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_interrupt_disable.s new file mode 100644 index 00000000..51f14717 --- /dev/null +++ b/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_interrupt_disable.s @@ -0,0 +1,95 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-A7/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_disable(void) +;{ + EXPORT _tx_thread_interrupt_disable +_tx_thread_interrupt_disable +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r0, CPSR ; Pickup current CPSR +; +; /* Mask interrupts. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ + ELSE + CPSID i ; Disable IRQ + ENDIF + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +;} +; + END + diff --git a/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_interrupt_restore.s new file mode 100644 index 00000000..b18323a3 --- /dev/null +++ b/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_interrupt_restore.s @@ -0,0 +1,87 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-A7/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for restoring interrupts to the state */ +;/* returned by a previous _tx_thread_interrupt_disable call. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_restore(UINT old_posture) +;{ + EXPORT _tx_thread_interrupt_restore +_tx_thread_interrupt_restore +; +; /* Apply the new interrupt posture. */ +; + MSR CPSR_c, r0 ; Setup new CPSR + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +;} +; + END + diff --git a/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_irq_nesting_end.s b/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_irq_nesting_end.s new file mode 100644 index 00000000..2c090601 --- /dev/null +++ b/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_irq_nesting_end.s @@ -0,0 +1,110 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts + ELSE +DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts + ENDIF +MODE_MASK EQU 0x1F ; Mode mask +IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end Cortex-A7/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_irq_nesting_end(VOID) +;{ + EXPORT _tx_thread_irq_nesting_end +_tx_thread_irq_nesting_end + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value + MSR CPSR_c, r0 ; Disable interrupts + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + ; 8-byte alignment logic) + BIC r0, r0, #MODE_MASK ; Clear mode bits + ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR + MSR CPSR_c, r0 ; Re-enter IRQ mode + IF {INTER} = {TRUE} + BX r3 ; Return to caller + ELSE + MOV pc, r3 ; Return to caller + ENDIF +;} + END + diff --git a/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_irq_nesting_start.s b/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_irq_nesting_start.s new file mode 100644 index 00000000..5f28f0b3 --- /dev/null +++ b/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_irq_nesting_start.s @@ -0,0 +1,104 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +IRQ_DISABLE EQU 0x80 ; IRQ disable bit +MODE_MASK EQU 0x1F ; Mode mask +SYS_MODE_BITS EQU 0x1F ; System mode bits +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start Cortex-A7/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_irq_nesting_start(VOID) +;{ + EXPORT _tx_thread_irq_nesting_start +_tx_thread_irq_nesting_start + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + BIC r0, r0, #MODE_MASK ; Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS ; Build system mode CPSR + MSR CPSR_c, r0 ; Enter system mode + STMDB sp!, {r1, lr} ; Push the system mode lr on the system mode stack + ; and push r1 just to keep 8-byte alignment + BIC r0, r0, #IRQ_DISABLE ; Build enable IRQ CPSR + MSR CPSR_c, r0 ; Enter system mode + IF {INTER} = {TRUE} + BX r3 ; Return to caller + ELSE + MOV pc, r3 ; Return to caller + ENDIF +;} +; + END + diff --git a/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_schedule.s b/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_schedule.s new file mode 100644 index 00000000..a9df5df8 --- /dev/null +++ b/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_schedule.s @@ -0,0 +1,458 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IMPORT _tx_thread_execute_ptr + IMPORT _tx_thread_current_ptr + IMPORT _tx_timer_time_slice + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_thread_enter + ENDIF + +IRQ_MODE EQU 0xD2 ; IRQ mode +USR_MODE EQU 0x10 ; USR mode +SVC_MODE EQU 0x13 ; SVC mode +SYS_MODE EQU 0x1F ; SYS mode + + IF :DEF:TX_ENABLE_FIQ_SUPPORT +ENABLE_INTS EQU 0xC0 ; IRQ & FIQ Interrupts enabled mask + ELSE +ENABLE_INTS EQU 0x80 ; IRQ Interrupts enabled mask + ENDIF + +MODE_MASK EQU 0x1F ; Mode mask +THUMB_MASK EQU 0x20 ; Thumb bit mask + + IMPORT _txm_system_mode_enter + IMPORT _txm_system_mode_exit + IMPORT _txm_ttbr1_page_table +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-A7/MMU/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + EXPORT _tx_thread_schedule +_tx_thread_schedule + + ; Enter the scheduler. + SVC 0 + + ; We should never get here - ever! +_tx_scheduler_fault__ + B _tx_scheduler_fault__ +;} +; **************************************************************************** + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; SWI_Handler +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + EXPORT __tx_swi_interrupt ; Software interrupt handler +__tx_swi_interrupt + + STMFD sp!, {r0-r3, r12, lr} ; Store the registers + MOV r1, sp ; Set pointer to parameters + MRS r0, spsr ; Get spsr + STMFD sp!, {r0, r3} ; Store spsr onto stack and another + ; register to maintain 8-byte-aligned stack + TST r0, #THUMB_MASK ; Occurred in Thumb state? + LDRNEH r0, [lr,#-2] ; Yes: Load halfword and... + BICNE r0, r0, #0xFF00 ; ...extract comment field + LDREQ r0, [lr,#-4] ; No: Load word and... + BICEQ r0, r0, #0xFF000000 ; ...extract comment field + + ; r0 now contains SVC number + ; r1 now contains pointer to stacked registers + + ; + ; The service call is handled here + ; + + CMP r0, #0 ; Is it a schedule request? + BEQ _tx_handler_svc_schedule ; Yes, go there + + CMP r0, #1 ; Is it a system mode enter request? + BEQ _tx_handler_svc_super_enter ; Yes, go there + + CMP r0, #2 ; Is it a system mode exit request? + BEQ _tx_handler_svc_super_exit ; Yes, go there + + LDR r2, =0x123456 + CMP r0, r2 ; Is it an ARM request? + BEQ _tx_handler_svc_arm ; Yes, go there + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Unknown SVC argument +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + ; Unrecognized service call +_tx_handler_svc_unrecognized + +_tx_handler_svc_unrecognized_loop ; We should never get here + B _tx_handler_svc_unrecognized_loop + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; SVC 1 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + ; At this point we have an SVC 1, which means we are entering the system mode to service a kernel call +_tx_handler_svc_super_enter + ; Make sure that we have been called from the system mode enter location (security) + LDR r2, =_txm_system_mode_enter ; Load the address of the known call point + SUB r1, lr, #4 ; Calculate the address of the actual call + CMP r1, r2 ; Did we come from txm_module_manager_user_mode_entry? + BNE _tx_handler_svc_unrecognized ; Return to where we came + + ; Clear the user mode flag in the thread structure + LDR r1, =_tx_thread_current_ptr ; Load the current thread pointer address + LDR r2, [r1] ; Load current thread location from the pointer (pointer indirection) + MOV r1, #0 ; Load the new user mode flag value (user mode flag clear -> not user mode -> system) + STR r1, [r2, #0x9C] ; Clear tx_thread_module_current_user_mode for thread + + ; Now we enter the system mode and return + LDMFD sp!, {r0, r3} ; Get spsr from the stack + BIC r0, r0, #MODE_MASK ; clear mode field + ORR r0, r0, #SYS_MODE ; system mode code + MSR SPSR_cxsf, r0 ; Restore the spsr + + LDR r1, [r2, #0xA8] ; Load the module kernel stack pointer + CPS #SYS_MODE ; Switch to SYS mode + MOV r3, sp ; Grab thread stack pointer + MOV sp, r1 ; Set SP to kernel stack pointer + CPS #SVC_MODE ; Switch back to SVC mode + STR r3, [r2, #0xB0] ; Save thread stack pointer + IF :DEF:TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + ELSE + LDR r3, [r2, #0xAC] ; Load the module kernel stack size + STR r3, [r2, #20] ; Set stack size + LDRD r0, r1, [r2, #0xA4] ; Load the module kernel stack start and end + STRD r0, r1, [r2, #0x0C] ; Set stack start and end + ENDIF + + LDMFD sp!, {r0-r3, r12, pc}^ ; Restore the registers and return + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; SVC 2 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + ; At this point we have an SVC 2, which means we are exiting the system mode after servicing a kernel call +_tx_handler_svc_super_exit + ; Make sure that we have been called from the system mode exit location (security) + LDR r2, =_txm_system_mode_exit ; Load the address of the known call point + SUB r1, lr, #4 ; Calculate the address of the actual call + CMP r1, r2 ; Did we come from txm_module_manager_user_mode_entry? + BNE _tx_handler_svc_unrecognized ; Return to where we came + + ; Set the user mode flag into the thread structure + LDR r1, =_tx_thread_current_ptr ; Load the current thread pointer address + LDR r2, [r1] ; Load the current thread location from the pointer (pointer indirection) + MOV r1, #1 ; Load the new user mode flag value (user mode enabled -> not system anymore) + STR r1, [r2, #0x9C] ; Set tx_thread_module_current_user_mode for thread + + ; Now we enter user mode (exit the system mode) and return + LDMFD sp!, {r0, r3} ; Get spsr from the stack + BIC r0, r0, #MODE_MASK ; clear mode field + ORR r0, r0, #USR_MODE ; user mode code + MSR SPSR_cxsf, r0 ; Restore the spsr + + LDR r1, [r2, #0xB0] ; Load the module thread stack pointer + CPS #SYS_MODE ; Switch to SYS mode + MOV r3, sp ; Grab kernel stack pointer + MOV sp, r1 ; Set SP back to thread stack pointer + CPS #SVC_MODE ; Switch back to SVC mode + IF :DEF:TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + ELSE + LDR r3, [r2, #0xBC] ; Load the module thread stack size + STR r3, [r2, #20] ; Set stack size + LDRD r0, r1, [r2, #0xB4] ; Load the module thread stack start and end + STRD r0, r1, [r2, #0x0C] ; Set stack start and end + ENDIF + LDMFD sp!, {r0-r3, r12, pc}^ ; Restore the registers and return + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; ARM Semihosting +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +_tx_handler_svc_arm + + ; *** TODO: handle semihosting requests or ARM angel requests *** + + ; just return + LDMFD sp!, {r0, r3} ; Get spsr from the stack + MSR SPSR_cxsf, r0 ; Restore the spsr + LDMFD sp!, {r0-r3, r12, pc}^ ; Restore the registers and return + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; SVC 0 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + ; At this point we have an SVC 0: enter the scheduler. +_tx_handler_svc_schedule + + LDMFD sp!, {r0, r3} ; Get spsr from stack + MSR SPSR_cxsf, r0 ; Restore spsr + LDMFD sp!, {r0-r3, r12, lr} ; Restore the registers + + ; This code waits for a thread control block pointer to appear in + ; the _tx_thread_execute_ptr variable. Once a thread pointer appears + ; in the variable, the corresponding thread is resumed. +; +; /* Enable interrupts. */ +; + MRS r2, CPSR ; Pickup CPSR + BIC r0, r2, #ENABLE_INTS ; Clear the disable bit(s) + MSR CPSR_cxsf, r0 ; Enable interrupts + +; +; /* Wait for a thread to execute. */ +; do +; { + LDR r1, =_tx_thread_execute_ptr ; Address of thread execute ptr +__tx_thread_schedule_loop + LDR r0, [r1, #0] ; Pickup next thread to execute + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_schedule_loop ; If so, keep looking for a thread +; } +; while(_tx_thread_execute_ptr == TX_NULL); + +; Yes! We have a thread to execute. Lockout interrupts and transfer control to it. + MSR CPSR_cxsf, r2 ; Disable interrupts +; +; /* Setup the current thread pointer. */ +; _tx_thread_current_ptr = _tx_thread_execute_ptr; +; + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread + STR r0, [r1, #0] ; Setup current thread pointer +; +; /* Increment the run count for this thread. */ +; _tx_thread_current_ptr -> tx_thread_run_count++; +; + LDR r2, [r0, #4] ; Pickup run counter + LDR r3, [r0, #24] ; Pickup time-slice for this thread + ADD r2, r2, #1 ; Increment thread run-counter + STR r2, [r0, #4] ; Store the new run counter +; +; /* Setup time-slice, if present. */ +; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; +; + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice variable + STR r3, [r2, #0] ; Setup time-slice + + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + MOV r5, r0 ; Save r0 + BL _tx_execution_thread_enter ; Call the thread execution enter function + MOV r0, r5 ; Restore r0 + ENDIF + + ; Determine if an interrupt frame or a synchronous task suspension frame is present. + CPS #SYS_MODE ; Enter SYS mode + LDR sp, [r0, #8] ; Switch to thread stack pointer + LDMIA sp!, {r4, r5} ; Pickup the stack type and saved CPSR + CPS #SVC_MODE ; Enter SVC mode + + ; ************************************************************************** + ; Set up MMU for module. + LDR r2, [r0, #0x94] ; Pickup the module pointer + CMP r2, #0 ; Valid module pointer? + LDRNE r2, [r2, #0x64] ; Load ASID + ; Otherwise, ASID 0 & master table will be loaded. + ; Is ASID already loaded? + MRC p15, 0, r1, c13, c0, 1 ; Read CONTEXTIDR into r1 + CMP r1, r2 + ; If so, skip MMU setup. + BEQ _tx_skip_mmu_update + ; New ASID & TTBR values to load + DSB + ISB + ; Load new ASID and TTBR + LDR r1, =_txm_ttbr1_page_table ; Load master TTBR + ORR r1, r1, #0x48 ; OR it with #TTBR0_ATTRIBUTES + MCR p15, 0, r1, c2, c0, 0 ; Change TTBR to master + ISB + DSB + MCR p15, 0, r2, c13, c0, 1 ; Change ASID to new value + ISB + ; Change TTBR to new value + MOV r3, #14 + ADD r1, r1, r2, LSL r3 + MCR p15, 0, r1, c2, c0, 0 ; Change TTBR to new value + + ; refresh TLB + MOV r2, #0 + DSB + MCR p15, 0, r2, c8, c7, 0 ; Invalidate entire unified TLB + MCR p15, 0, r2, c7, c5, 0 ; Invalidate all instruction caches to PoU + MCR p15, 0, r2, c7, c5, 6 ; Invalidate branch predictor + DSB + ISB + + ;test address translation + ;mcr p15, 0, r0, c7, c8, 0 + +_tx_skip_mmu_update + ; ************************************************************************** + + CMP r4, #0 ; Check for synchronous context switch + BEQ _tx_solicited_return + + MSR SPSR_cxsf, r5 ; Setup SPSR for return + LDR r1, [r0, #8] ; Get thread SP + LDR lr, [r1, #0x40] ; Get thread PC + CPS #SYS_MODE ; Enter SYS mode + + IF {TARGET_FPU_VFP} = {TRUE} + LDR r2, [r0, #144] ; Pickup the VFP enabled flag + CMP r2, #0 ; Is the VFP enabled? + BEQ _tx_skip_interrupt_vfp_restore ; No, skip VFP interrupt restore + VLDMIA sp!, {D0-D15} ; Recover D0-D15 + VLDMIA sp!, {D16-D31} ; Recover D16-D31 + LDR r4, [sp], #4 ; Pickup FPSCR + VMSR FPSCR, r4 ; Restore FPSCR + CPS #SVC_MODE ; Enter SVC mode + LDR lr, [r1, #0x144] ; Get thread PC + CPS #SYS_MODE ; Enter SYS mode +_tx_skip_interrupt_vfp_restore + ENDIF + + LDMIA sp!, {r0-r12, lr} ; Restore registers + ADD sp, sp, #4 ; Fix stack pointer + CPS #SVC_MODE ; Enter SVC mode + SUBS pc, lr, #0 ; Return to point of thread interrupt + +_tx_solicited_return + MOV r2, r5 ; Move CPSR to scratch register + CPS #SYS_MODE ; Enter SYS mode + + IF {TARGET_FPU_VFP} = {TRUE} + LDR r1, [r0, #144] ; Pickup the VFP enabled flag + CMP r1, #0 ; Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_restore ; No, skip VFP solicited restore + VLDMIA sp!, {D8-D15} ; Recover D8-D15 + VLDMIA sp!, {D16-D31} ; Recover D16-D31 + LDR r4, [sp], #4 ; Pickup FPSCR + VMSR FPSCR, r4 ; Restore FPSCR +_tx_skip_solicited_vfp_restore + ENDIF + + LDMIA sp!, {r4-r11, lr} ; Restore registers + MOV r1, lr ; Copy lr to r1 to preserve across mode change + CPS #SVC_MODE ; Enter SVC mode + MSR SPSR_cxsf, r2 ; Recover CPSR + MOV lr, r1 ; Deprecated return via r1, so copy r1 to lr and return via lr + SUBS pc, lr, #0 ; Return to thread synchronously + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; End __tx_handler_swi +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + IF {TARGET_FPU_VFP} = {TRUE} + EXPORT tx_thread_vfp_enable +tx_thread_vfp_enable + MRS r2, CPSR ; Pickup the CPSR + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup current thread pointer + CMP r1, #0 ; Check for NULL thread pointer + BEQ __tx_no_thread_to_enable ; If NULL, skip VFP enable + MOV r0, #1 ; Build enable value + STR r0, [r1, #144] ; Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_enable + MSR CPSR_cxsf, r2 ; Recover CPSR + BX LR ; Return to caller + + EXPORT tx_thread_vfp_disable +tx_thread_vfp_disable + MRS r2, CPSR ; Pickup the CPSR + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup current thread pointer + CMP r1, #0 ; Check for NULL thread pointer + BEQ __tx_no_thread_to_disable ; If NULL, skip VFP disable + MOV r0, #0 ; Build disable value + STR r0, [r1, #144] ; Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_disable + MSR CPSR_cxsf, r2 ; Recover CPSR + BX LR ; Return to caller + ENDIF + + END + diff --git a/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_stack_build.s new file mode 100644 index 00000000..212b51f2 --- /dev/null +++ b/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_stack_build.s @@ -0,0 +1,166 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +SVC_MODE EQU 0x13 ; SVC mode +SYS_MODE EQU 0x1F ; SYS mode + IF :DEF:TX_ENABLE_FIQ_SUPPORT +CPSR_MASK EQU 0xDF ; Mask initial CPSR, IRQ & FIQ ints enabled + ELSE +CPSR_MASK EQU 0x9F ; Mask initial CPSR, IRQ ints enabled + ENDIF + +THUMB_MASK EQU 0x20 ; Thumb bit (5) of CPSR/SPSR + +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-A7/MMU/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + EXPORT _tx_thread_stack_build +_tx_thread_stack_build +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-A7 should look like the following after it is built: +; +; Stack Top: 1 Interrupt stack frame type +; CPSR Initial value for CPSR +; a1 (r0) Initial value for a1 +; a2 (r1) Initial value for a2 +; a3 (r2) Initial value for a3 +; a4 (r3) Initial value for a4 +; v1 (r4) Initial value for v1 +; v2 (r5) Initial value for v2 +; v3 (r6) Initial value for v3 +; v4 (r7) Initial value for v4 +; v5 (r8) Initial value for v5 +; sb (r9) Initial value for sb +; sl (r10) Initial value for sl +; fp (r11) Initial value for fp +; ip (r12) Initial value for ip +; lr (r14) Initial value for lr +; pc (r15) Initial value for pc +; 0 For stack backtracing +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #7 ; Ensure 8-byte alignment + SUB r2, r2, #76 ; Allocate space for the stack frame +; +; /* Actually build the stack frame. */ +; + MOV r3, #1 ; Build interrupt stack type + STR r3, [r2, #0] ; Store stack type + MOV r3, #0 ; Build initial register value + STR r3, [r2, #8] ; Store initial r0 + STR r3, [r2, #12] ; Store initial r1 + STR r3, [r2, #16] ; Store initial r2 + STR r3, [r2, #20] ; Store initial r3 + STR r3, [r2, #24] ; Store initial r4 + STR r3, [r2, #28] ; Store initial r5 + STR r3, [r2, #32] ; Store initial r6 + STR r3, [r2, #36] ; Store initial r7 + STR r3, [r2, #40] ; Store initial r8 + STR r3, [r2, #44] ; Store initial r9 + LDR r3, [r0, #12] ; Pickup stack starting address + STR r3, [r2, #48] ; Store initial r10 (sl) + MOV r3, #0 ; Build initial register value + STR r3, [r2, #52] ; Store initial r11 + STR r3, [r2, #56] ; Store initial r12 + STR r3, [r2, #60] ; Store initial lr + STR r1, [r2, #64] ; Store initial pc + STR r3, [r2, #68] ; 0 for back-trace + + MRS r3, CPSR ; Pickup CPSR + BIC r3, r3, #CPSR_MASK ; Mask mode bits of CPSR + ORR r3, r3, #SYS_MODE ; Build CPSR, SYS mode, interrupts enabled + BIC r3, r3, #THUMB_MASK ; Clear Thumb bit by default + AND r1, r1, #1 ; Determine if the entry function is in Thumb mode + CMP r1, #1 ; Is the Thumb bit set? + ORREQ r3, r3, #THUMB_MASK ; Yes, set the Thumb bit + STR r3, [r2, #4] ; Store initial CPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF + +;} + END + diff --git a/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_system_return.s b/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_system_return.s new file mode 100644 index 00000000..e3029a13 --- /dev/null +++ b/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_system_return.s @@ -0,0 +1,159 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IMPORT _tx_thread_current_ptr + IMPORT _tx_timer_time_slice + IMPORT _tx_thread_schedule + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_thread_exit + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-A7/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + EXPORT _tx_thread_system_return +_tx_thread_system_return +; +; /* Save minimal context on the stack. */ +; + STMDB sp!, {r4-r11, lr} ; Save minimal context + LDR r5, =_tx_thread_current_ptr ; Pickup address of current ptr + LDR r6, [r5, #0] ; Pickup current thread pointer + + IF {TARGET_FPU_VFP} = {TRUE} + LDR r0, [r6, #144] ; Pickup the VFP enabled flag + CMP r0, #0 ; Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_save ; No, skip VFP solicited save + VMRS r4, FPSCR ; Pickup the FPSCR + STR r4, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D8-D15} ; Save D8-D15 +_tx_skip_solicited_vfp_save + ENDIF + + MOV r0, #0 ; Build a solicited stack type + MRS r1, CPSR ; Pickup the CPSR + STMDB sp!, {r0-r1} ; Save type and CPSR +; +; /* Lockout interrupts. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + BL _tx_execution_thread_exit ; Call the thread exit function + ENDIF + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + LDR r1, [r2, #0] ; Pickup current time slice +; +; /* Save current stack and switch to system stack. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; sp = _tx_thread_system_stack_ptr; +; + STR sp, [r6, #8] ; Save thread stack pointer +; +; /* Determine if the time-slice is active. */ +; if (_tx_timer_time_slice) +; { +; + MOV r4, #0 ; Build clear value + CMP r1, #0 ; Is a time-slice active? + BEQ __tx_thread_dont_save_ts ; No, don't save the time-slice +; +; /* Save the current remaining time-slice. */ +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r4, [r2, #0] ; Clear time-slice + STR r1, [r6, #24] ; Store current time-slice +; +; } +__tx_thread_dont_save_ts +; +; /* Clear the current thread pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + STR r4, [r5, #0] ; Clear current thread pointer + + B _tx_thread_schedule ; Jump to scheduler! +; +;} + END + diff --git a/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_vectored_context_save.s b/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_vectored_context_save.s new file mode 100644 index 00000000..9bae0304 --- /dev/null +++ b/ports_module/cortex-a7/ac5/module_manager/src/tx_thread_vectored_context_save.s @@ -0,0 +1,200 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_enter + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save Cortex-A7/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_vectored_context_save(VOID) +;{ + EXPORT _tx_thread_vectored_context_save +_tx_thread_vectored_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ENDIF + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Note: Minimal context of interrupted thread is already saved. */ +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +__tx_thread_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + ; scheduling loop - nothing needs saving! +; +; /* Note: Minimal context of interrupted thread is already saved. */ +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +; } +; else +; { +; +__tx_thread_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; processing. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + ADD sp, sp, #32 ; Recover saved registers + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +; } +;} +; + END + diff --git a/ports_module/cortex-a7/ac5/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex-a7/ac5/module_manager/src/tx_timer_interrupt.s new file mode 100644 index 00000000..c0c10196 --- /dev/null +++ b/ports_module/cortex-a7/ac5/module_manager/src/tx_timer_interrupt.s @@ -0,0 +1,258 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_timer.h" +;#include "tx_thread.h" +; +; +;Define Assembly language external references... +; + IMPORT _tx_timer_time_slice + IMPORT _tx_timer_system_clock + IMPORT _tx_timer_current_ptr + IMPORT _tx_timer_list_start + IMPORT _tx_timer_list_end + IMPORT _tx_timer_expired_time_slice + IMPORT _tx_timer_expired + IMPORT _tx_thread_time_slice + IMPORT _tx_timer_expiration_process +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-A7/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + EXPORT _tx_timer_interrupt +_tx_timer_interrupt +; +; /* Upon entry to this routine, it is assumed that context save has already +; been called, and therefore the compiler scratch registers are available +; for use. */ +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + LDR r1, =_tx_timer_system_clock ; Pickup address of system clock + LDR r0, [r1, #0] ; Pickup system clock + ADD r0, r0, #1 ; Increment system clock + STR r0, [r1, #0] ; Store new system clock +; +; /* Test for time-slice expiration. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r2, [r3, #0] ; Pickup time-slice + CMP r2, #0 ; Is it non-active? + BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing +; +; /* Decrement the time_slice. */ +; _tx_timer_time_slice--; +; + SUB r2, r2, #1 ; Decrement the time-slice + STR r2, [r3, #0] ; Store new time-slice value +; +; /* Check for expiration. */ +; if (__tx_timer_time_slice == 0) +; + CMP r2, #0 ; Has it expired? + BNE __tx_timer_no_time_slice ; No, skip expiration processing +; +; /* Set the time-slice expired flag. */ +; _tx_timer_expired_time_slice = TX_TRUE; +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup address of expired flag + MOV r0, #1 ; Build expired value + STR r0, [r3, #0] ; Set time-slice expiration flag +; +; } +; +__tx_timer_no_time_slice +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + LDR r1, =_tx_timer_current_ptr ; Pickup current timer pointer addr + LDR r0, [r1, #0] ; Pickup current timer + LDR r2, [r0, #0] ; Pickup timer list entry + CMP r2, #0 ; Is there anything in the list? + BEQ __tx_timer_no_timer ; No, just increment the timer +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + LDR r3, =_tx_timer_expired ; Pickup expiration flag address + MOV r2, #1 ; Build expired value + STR r2, [r3, #0] ; Set expired flag + B __tx_timer_done ; Finished timer processing +; +; } +; else +; { +__tx_timer_no_timer +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ADD r0, r0, #4 ; Move to next timer +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + LDR r3, =_tx_timer_list_end ; Pickup addr of timer list end + LDR r2, [r3, #0] ; Pickup list end + CMP r0, r2 ; Are we at list end? + BNE __tx_timer_skip_wrap ; No, skip wrap-around logic +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + LDR r3, =_tx_timer_list_start ; Pickup addr of timer list start + LDR r0, [r3, #0] ; Set current pointer to list start +; +__tx_timer_skip_wrap +; + STR r0, [r1, #0] ; Store new current timer pointer +; } +; +__tx_timer_done +; +; +; /* See if anything has expired. */ +; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of expired flag + LDR r2, [r3, #0] ; Pickup time-slice expired flag + CMP r2, #0 ; Did a time-slice expire? + BNE __tx_something_expired ; If non-zero, time-slice expired + LDR r1, =_tx_timer_expired ; Pickup addr of other expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Did a timer expire? + BEQ __tx_timer_nothing_expired ; No, nothing expired +; +__tx_something_expired +; +; + STMDB sp!, {r0, lr} ; Save the lr register on the stack + ; and save r0 just to keep 8-byte alignment +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + LDR r1, =_tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Check for timer expiration + BEQ __tx_timer_dont_activate ; If not set, skip timer activation +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + BL _tx_timer_expiration_process ; Call the timer expiration handling routine +; +; } +__tx_timer_dont_activate +; +; /* Did time slice expire? */ +; if (_tx_timer_expired_time_slice) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r2, [r3, #0] ; Pickup the actual flag + CMP r2, #0 ; See if the flag is set + BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing +; +; /* Time slice interrupted thread. */ +; _tx_thread_time_slice(); + + BL _tx_thread_time_slice ; Call time-slice processing +; +; } +; +__tx_timer_not_ts_expiration +; + LDMIA sp!, {r0, lr} ; Recover lr register (r0 is just there for + ; the 8-byte stack alignment +; +; } +; +__tx_timer_nothing_expired +; + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +;} + END + diff --git a/ports_module/cortex-a7/ac5/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex-a7/ac5/module_manager/src/txm_module_manager_alignment_adjust.c new file mode 100644 index 00000000..cc2842a6 --- /dev/null +++ b/ports_module/cortex-a7/ac5/module_manager/src/txm_module_manager_alignment_adjust.c @@ -0,0 +1,90 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_alignment_adjust Cortex-A7/MMU/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function adjusts the alignment and size of the code and data */ +/* section for a given module implementation. */ +/* */ +/* INPUT */ +/* */ +/* code_size Size of the code area (updated) */ +/* code_alignment Code area alignment (updated) */ +/* data_size Size of data area (updated) */ +/* data_alignment Data area alignment (updated) */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment) +{ + +ULONG local_code_size; +ULONG local_code_alignment; +ULONG local_data_size; +ULONG local_data_alignment; + + + /* Copy the input parameters into local variables for ease of use. */ + local_code_size = *code_size; + local_code_alignment = TXM_MODULE_MEMORY_ALIGNMENT; + local_data_size = *data_size; + local_data_alignment = TXM_MODULE_MEMORY_ALIGNMENT; + + /* Return all the information to the caller. */ + *code_size = ((local_code_size + TXM_MODULE_MEMORY_ALIGNMENT - 1)/TXM_MODULE_MEMORY_ALIGNMENT) * TXM_MODULE_MEMORY_ALIGNMENT; + *code_alignment = local_code_alignment; + *data_size = ((local_data_size + TXM_MODULE_MEMORY_ALIGNMENT - 1)/TXM_MODULE_MEMORY_ALIGNMENT) * TXM_MODULE_MEMORY_ALIGNMENT; + *data_alignment = local_data_alignment; +} diff --git a/ports_module/cortex-a7/ac5/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex-a7/ac5/module_manager/src/txm_module_manager_external_memory_enable.c new file mode 100644 index 00000000..6209a2ab --- /dev/null +++ b/ports_module/cortex-a7/ac5/module_manager/src/txm_module_manager_external_memory_enable.c @@ -0,0 +1,483 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_mutex.h" +#include "tx_queue.h" +#include "tx_thread.h" +#include "txm_module.h" + +/* External page tables. */ +extern ULONG _txm_level2_external_page_pool[TXM_LEVEL2_EXTERNAL_POOL_PAGES][TXM_LEVEL_2_PAGE_TABLE_ENTRIES]; +extern ULONG _txm_ttbr1_page_table[TXM_MAXIMUM_MODULES][TXM_MASTER_PAGE_TABLE_ENTRIES]; + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_level2_page_get Cortex-A7/MMU/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets an available L2 page table and places it in the */ +/* module external page table list. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* page_addr Address of L2 page */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_external_memory_enable */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_level2_page_get(TXM_MODULE_INSTANCE *module_instance, ULONG *page_addr) +{ + +UINT i; +UINT status; +UINT table_index; +UINT pool_index; + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Find first free table slot in module control block. */ + for(i = 0; i < TXM_MODULE_LEVEL2_EXTERNAL_PAGES; i++) + { + if(module_instance->txm_external_page_table[i] == TX_NULL) + { + table_index = i; + break; + } + } + + if(i >= TXM_MODULE_LEVEL2_EXTERNAL_PAGES) + { + status = TXM_MODULE_EXTERNAL_MEMORY_ENABLE_ERROR; + } + + else + { + /* Find first free table in pool. */ + for(i = 0; i < TXM_LEVEL2_EXTERNAL_POOL_PAGES; i++) + { + if(_txm_level2_external_page_pool[i][0] == (ULONG) TX_NULL) + { + pool_index = i; + break; + } + } + + if(i >= TXM_LEVEL2_EXTERNAL_POOL_PAGES) + { + status = TXM_MODULE_EXTERNAL_MEMORY_ENABLE_ERROR; + } + } + + + if(status == TX_SUCCESS) + { + /* Place page address in table slot. Return page address. */ + module_instance->txm_external_page_table[table_index] = _txm_level2_external_page_pool[pool_index]; + *page_addr = (ULONG)_txm_level2_external_page_pool[pool_index]; + } + + return(status); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_level2_page_clear Cortex-A7/MMU/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function clears the first entry in a L2 page table and clears */ +/* the table entry from the module external page table list. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* TXM_MODULE_MANAGER_MODULE_UNLOAD */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_level2_page_clear(TXM_MODULE_INSTANCE *module_instance) +{ +UINT i; + + /* Clear table slots and zero out L2 entry. */ + for(i = 0; i < TXM_MODULE_LEVEL2_EXTERNAL_PAGES; i++) + { + if(module_instance->txm_external_page_table[i]) + { + *(ULONG *)module_instance->txm_external_page_table[i] = (ULONG)TX_NULL; + module_instance->txm_external_page_table[i] = TX_NULL; + } + } +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_external_memory_enable Cortex-A7/MMU/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates an entry in the MMU table for a shared */ +/* memory space. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* start_address Start address of memory */ +/* length Length of external memory */ +/* attributes Memory attributes */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _tx_mutex_get Get protection mutex */ +/* _tx_mutex_put Release protection mutex */ +/* TX_MEMSET Fill memory with constant */ +/* _txm_level2_page_get Get L2 page table */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_external_memory_enable( TXM_MODULE_INSTANCE *module_instance, + VOID *start_address, + ULONG length, + UINT attributes) +{ + +ULONG start_addr = (ULONG) start_address; +ULONG end_addr; +ULONG mmu_l1_entries; +ULONG mmu_l2_entries = 0; +ULONG level1_index; +ULONG level2_index; +ULONG temp_index; +ULONG temp_addr; +ULONG page_addr; +ULONG asid; +ULONG level1_attributes; +ULONG level2_attributes; +UINT status; +UINT i; + + /* Determine if the module manager has not been initialized yet. */ + if (_txm_module_manager_ready != TX_TRUE) + { + /* Module manager has not been initialized. */ + return(TX_NOT_AVAILABLE); + } + + /* Determine if the module is valid. */ + if (module_instance == TX_NULL) + { + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Get module manager protection mutex. */ + _tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER); + + /* Determine if the module instance is valid. */ + if (module_instance -> txm_module_instance_id != TXM_MODULE_ID) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Determine if the module instance is in the loaded state. */ + if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if the module is not ready. */ + return(TX_START_ERROR); + } + + /* Determine if the module instance is memory protected. */ + if (module_instance -> txm_module_instance_asid == 0) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if the module is not protected. */ + return(TXM_MODULE_EXTERNAL_MEMORY_ENABLE_ERROR); + } + + /* Start address must be aligned to MMU block size (4 kB). + Length will be rounded up to 4 kB alignment. */ + if(start_addr & ~TXM_MMU_LEVEL2_MASK) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return alignment error. */ + return(TXM_MODULE_ALIGNMENT_ERROR); + } + + /**************************************************************************/ + /* At this point, we have a valid address. Set up MMU. */ + /**************************************************************************/ + + /* Round length up to 4 kB alignment. */ + if(length & ~TXM_MMU_LEVEL2_MASK) + { + length = ((length + TXM_MODULE_MEMORY_ALIGNMENT - 1)/TXM_MODULE_MEMORY_ALIGNMENT) * TXM_MODULE_MEMORY_ALIGNMENT; + } + + /* Get end address. */ + end_addr = start_addr + length - 1; + + /* How many level 1 table entries does data span? */ + mmu_l1_entries = (end_addr >> TXM_MMU_LEVEL1_PAGE_SHIFT) - (start_addr >> TXM_MMU_LEVEL1_PAGE_SHIFT) + 1; + + /* Add 1 to align. */ + end_addr++; + + /* How many level 2 table entries does data need? + * 0: start and end addresses both aligned. + * 1: either start or end address aligned. + * 2: start and end addresses both not aligned. */ + if(start_addr & ~TXM_MMU_LEVEL1_MASK) + { + /* If start address is not aligned, increment. */ + mmu_l2_entries++; + } + if(end_addr & ~TXM_MMU_LEVEL1_MASK) + { + /* If end address is not aligned, increment. */ + mmu_l2_entries++; + } + + /* Get index into L1 table. */ + level1_index = (start_addr >> TXM_MMU_LEVEL1_PAGE_SHIFT); + + /* Get module ASID. */ + asid = module_instance -> txm_module_instance_asid; + + /* Do start and end entries need level 2 pages? */ + if(mmu_l2_entries > 0) + { + /* Build L2 attributes. */ + level2_attributes = ((attributes & TXM_MMU_ATTRIBUTE_XN) << TXM_MMU_LEVEL2_USER_ATTRIBUTE_XN_SHIFT) | + ((attributes & TXM_MMU_ATTRIBUTE_B) << TXM_MMU_LEVEL2_USER_ATTRIBUTE_B_SHIFT) | + ((attributes & TXM_MMU_ATTRIBUTE_C) << TXM_MMU_LEVEL2_USER_ATTRIBUTE_C_SHIFT) | + ((attributes & TXM_MMU_ATTRIBUTE_AP) << TXM_MMU_LEVEL2_USER_ATTRIBUTE_AP_SHIFT) | + ((attributes & TXM_MMU_ATTRIBUTE_TEX) << TXM_MMU_LEVEL2_USER_ATTRIBUTE_TEX_SHIFT) | + TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE; + + /* If start_addr is not aligned, we need a L2 page. */ + if(start_addr & ~TXM_MMU_LEVEL1_MASK) + { + + /* Is there already an L2 page in the L1 table? */ + if((_txm_ttbr1_page_table[asid][level1_index] & ~TXM_MMU_LEVEL1_SECOND_MASK) == TXM_MMU_LEVEL1_SECOND_ATTRIBUTES) + { + page_addr = _txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_SECOND_MASK; + } + else + { + /* Get L2 table from pool. */ + status = _txm_level2_page_get(module_instance, &page_addr); + + if(status != TX_SUCCESS) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + return(TXM_MODULE_EXTERNAL_MEMORY_ENABLE_ERROR); + } + + /* Clear L2 table. */ + TX_MEMSET((void *)page_addr, 0, TXM_LEVEL_2_PAGE_TABLE_ENTRIES); + + /* Put L2 page in L1 table. */ + _txm_ttbr1_page_table[asid][level1_index] = (page_addr & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES; + } + + /* Decrement number of L1 entries remaining. */ + mmu_l1_entries--; + + /* Set up L2 start table. */ + /* Determine how many entries in L2 table. */ + if((end_addr >> TXM_MMU_LEVEL1_PAGE_SHIFT) - (start_addr >> TXM_MMU_LEVEL1_PAGE_SHIFT)) + { + /* End address goes to next L1 page (or beyond). */ + temp_addr = ((start_addr >> TXM_MMU_LEVEL1_PAGE_SHIFT) + 1) << (TXM_MMU_LEVEL1_PAGE_SHIFT); + mmu_l2_entries = (temp_addr - start_addr) >> TXM_MMU_LEVEL2_PAGE_SHIFT; + } + else + { + /* End address is on the same L1 page. */ + mmu_l2_entries = (end_addr >> TXM_MMU_LEVEL2_PAGE_SHIFT) - (start_addr >> TXM_MMU_LEVEL2_PAGE_SHIFT); + } + + /* Insert module settings into start table. */ + level2_index = ((start_addr & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT); + for(i = 0; i < mmu_l2_entries; i++, level2_index++) + { + ((ULONG *) page_addr)[level2_index] = (start_addr & TXM_MMU_LEVEL1_MASK) | (level2_index << TXM_MMU_LEVEL2_PAGE_SHIFT) | level2_attributes; + } + + level1_index++; + } + + /* Does last entry need a level 2 page? */ + /* If end_address is not aligned, we need a L2 page. */ + if((end_addr & ~TXM_MMU_LEVEL1_MASK) && (mmu_l1_entries != 0)) + { + /* Get index into L1 table. */ + temp_index = (end_addr >> TXM_MMU_LEVEL1_PAGE_SHIFT); + + /* Is there already an L2 page in the L1 table? */ + if((_txm_ttbr1_page_table[asid][temp_index] & ~TXM_MMU_LEVEL1_SECOND_MASK) == TXM_MMU_LEVEL1_SECOND_ATTRIBUTES) + { + page_addr = _txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_SECOND_MASK; + } + else + { + /* Get L2 table from pool. */ + status = _txm_level2_page_get(module_instance, &page_addr); + + if(status != TX_SUCCESS) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + return(TXM_MODULE_EXTERNAL_MEMORY_ENABLE_ERROR); + } + + /* Clear L2 table. */ + TX_MEMSET((void *)page_addr, 0, TXM_LEVEL_2_PAGE_TABLE_ENTRIES); + + /* Put L2 page in L1 table. */ + _txm_ttbr1_page_table[asid][temp_index] = (page_addr & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES; + } + + /* Decrement number of L1 entries remaining. */ + mmu_l1_entries--; + + /* Determine how many entries in L2 table. */ + mmu_l2_entries = ((end_addr & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT); + + /* Set up L2 end table. */ + for(i = 0; i < mmu_l2_entries; i++) + { + ((ULONG *) page_addr)[i] = (end_addr & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | level2_attributes; + } + } + } + + /* Fill any L1 entries between start and end pages of module data range. */ + for(i = 0; i < mmu_l1_entries; i++, level1_index++) + { + /* Build L1 attributes. */ + level1_attributes = ((attributes & TXM_MMU_ATTRIBUTE_XN) << TXM_MMU_LEVEL1_USER_ATTRIBUTE_XN_SHIFT) | + ((attributes & TXM_MMU_ATTRIBUTE_B) << TXM_MMU_LEVEL1_USER_ATTRIBUTE_B_SHIFT) | + ((attributes & TXM_MMU_ATTRIBUTE_C) << TXM_MMU_LEVEL1_USER_ATTRIBUTE_C_SHIFT) | + ((attributes & TXM_MMU_ATTRIBUTE_AP) << TXM_MMU_LEVEL1_USER_ATTRIBUTE_AP_SHIFT) | + ((attributes & TXM_MMU_ATTRIBUTE_TEX) << TXM_MMU_LEVEL1_USER_ATTRIBUTE_TEX_SHIFT) | + TXM_MMU_LEVEL1_USER_ATTRIBUTE_BASE; + + /* Place address and attributes in table. */ + _txm_ttbr1_page_table[asid][level1_index] = (level1_index << TXM_MMU_LEVEL1_PAGE_SHIFT) | level1_attributes; + } + + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/ports_module/cortex-a7/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex-a7/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c new file mode 100644 index 00000000..ad346533 --- /dev/null +++ b/ports_module/cortex-a7/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -0,0 +1,111 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + +/* Define a macro that can be used to allocate global variables useful to + store information about the last fault. This macro is defined in + txm_module_port.h and is usually populated in the assembly language + fault handling prior to the code calling _txm_module_manager_memory_fault_handler. */ + +TXM_MODULE_MANAGER_FAULT_INFO + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_handler Cortex-A7/MMU/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles a fault associated with a memory protected */ +/* module. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_terminate Terminate thread */ +/* */ +/* CALLED BY */ +/* */ +/* Fault handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_memory_fault_handler(VOID) +{ + +TXM_MODULE_INSTANCE *module_instance_ptr; +TX_THREAD *thread_ptr; + + + /* Pickup the current thread. */ + thread_ptr = _tx_thread_current_ptr; + + /* Initialize the module instance pointer to NULL. */ + module_instance_ptr = TX_NULL; + + /* Is there a thread? */ + if (thread_ptr) + { + /* Pickup the module instance. */ + module_instance_ptr = thread_ptr -> tx_thread_module_instance_ptr; + + /* Terminate the current thread. */ + _tx_thread_terminate(_tx_thread_current_ptr); + } + + /* Determine if there is a user memory fault notification callback. */ + if (_txm_module_manager_fault_notify) + { + /* Yes, call the user's notification memory fault callback. */ + (_txm_module_manager_fault_notify)(thread_ptr, module_instance_ptr); + } +} diff --git a/ports_module/cortex-a7/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex-a7/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c new file mode 100644 index 00000000..4af6367b --- /dev/null +++ b/ports_module/cortex-a7/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -0,0 +1,84 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the external user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_notify Cortex-A7/MMU/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application callback when/if a memory */ +/* fault occurs. The supplied thread is automatically terminated, but */ +/* any other threads in the same module may still execute. */ +/* */ +/* INPUT */ +/* */ +/* notify_function Memory fault notification */ +/* function, NULL disables. */ +/* */ +/* OUTPUT */ +/* */ +/* Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +{ + /* Setup notification function. */ + _txm_module_manager_fault_notify = notify_function; + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/ports_module/cortex-a7/ac5/module_manager/src/txm_module_manager_mm_initialize.c b/ports_module/cortex-a7/ac5/module_manager/src/txm_module_manager_mm_initialize.c new file mode 100644 index 00000000..eeeb0774 --- /dev/null +++ b/ports_module/cortex-a7/ac5/module_manager/src/txm_module_manager_mm_initialize.c @@ -0,0 +1,301 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + +#define CACHE_DISABLED 0x12 +#define SDRAM_START 0x00000000 +#define SDRAM_END 0x1fffffff +#define CACHE_WRITEBACK 0x1e + +#define SECTION_DESCRIPTOR 0x00000002 +#define DACR_CLIENT_MODE 0x55555555 + + +/*** Page table attributes TTBR0 *********************************************** +* IRGN = 01 - Normal memory, Inner Write-Back Write-Allocate Cacheable +* S - non-shareable +* RGN = 01 - Normal memory, Outer Write-Back Write-Allocate Cacheable +* NOS - outer-shareable +*******************************************************************************/ +#define TTBR0_ATTRIBUTES 0x48 + + + +/* ASID table, index is ASID number and contents hold pointer to module. */ +TXM_MODULE_INSTANCE *_txm_asid_table[TXM_ASID_TABLE_LENGTH]; + +/* Master page table, 2^14 (16kB) alignment. + * First table is the master level 1 table, the rest are for each module. */ +__align(16384) ULONG _txm_ttbr1_page_table[TXM_MAXIMUM_MODULES][TXM_MASTER_PAGE_TABLE_ENTRIES]; + +/* Module start and end level 2 page tables, 2^10 (1kB) alignment. + * First set of 4 tables are the master level 2 tables, the rest are for each module. + * Each module needs two L2 tables for code and two L2 tables for data. */ +__align(1024) ULONG _txm_level2_module_page_table[TXM_MAXIMUM_MODULES * 4][TXM_LEVEL_2_PAGE_TABLE_ENTRIES]; + +/* Module external memory level 2 page tables, 2^10 (1kB) alignment. */ +__align(1024) ULONG _txm_level2_external_page_pool[TXM_LEVEL2_EXTERNAL_POOL_PAGES][TXM_LEVEL_2_PAGE_TABLE_ENTRIES]; + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_mm_initialize Cortex-A7/MMU/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function performs the initial set up of the the A7 MMU. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_mm_initialize(VOID) +{ + +#ifdef TXM_MODULE_MEMORY_PROTECTION_ENABLED + UINT i; + ULONG cp15reg; + UINT user_mode_index; + UINT counter_limit; + + /* Clear ASID table. */ + for (i = 0; i < TXM_ASID_TABLE_LENGTH; i++) + { + _txm_asid_table[i] = 0; + } + _txm_asid_table[0] = (TXM_MODULE_INSTANCE *)TXM_ASID_RESERVED; + + + /********************************************************************************/ + /* This is an example showing how to set up the cache attributes. */ + /********************************************************************************/ + +/******************************************************************************* +* PAGE TABLE generation +* Generate the page tables +* Build a flat translation table for the whole address space. +* ie: Create 4096 1MB sections from 0x000xxxxx to 0xFFFxxxxx +* 31 20|19 18|17|16| 15|14 12|11 10|9|8 5|4 |3 2|1 0| +* |base address | 0 0|nG| S|AP2|TEX |AP |P|Domain|XN|CB |1 0| +* +* Bits[31:20] - Top 12 bits of VA is pointer into table +* nG[17]=0 - Non global, enables matching against ASID in the TLB when set. +* S[16]=0 - Indicates normal memory is shared when set. +* AP2[15]=0 +* TEX[14:12]=000 +* AP[11:10]=11 - Configure for full read/write access in all modes +* IMPP[9]=0 - Ignored +* Domain[5:8]=1111 - Set all pages to use domain 15 +* XN[4]=0 - Execute never disabled +* CB[3:2]= 00 - Set attributes to Strongly-ordered memory. +* (except for the descriptor where code segment is based, +* see below) +* Bits[1:0]=10 - Indicate entry is a 1MB section +*******************************************************************************/ + +/* ---- Parameter setting to level1 descriptor (bits 19:0) ---- */ +/* setting for Strongly-ordered memory + B-00000000000000000000010111100010 */ +#define TTB_PARA_STRGLY 0x05E2 + +/* setting for Outer and inner not cache normal memory + B-00000000000000000001010111100010 */ +#define TTB_PARA_NORMAL_NOT_CACHE 0x15E2 + +/* setting for Outer and inner write back, write allocate normal memory + (Cacheable) + B-00000000000000000001010111101110 */ +#define TTB_PARA_NORMAL_CACHE 0x15EE //0x15EE + +/* In this chip (RZA1) there are the following 12 sections with the defined memory size (MB) */ +#define M_SIZE_NOR 128 /* [Area00] CS0, CS1 area (for NOR flash) */ +#define M_SIZE_SDRAM 128 /* [Area01] CS2, CS3 area (for SDRAM) */ +#define M_SIZE_CS45 128 /* [Area02] CS4, CS5 area */ +#define M_SIZE_SPI 128 /* [Area03] SPI, SP2 area (for Serial flash) */ +#define M_SIZE_RAM 10 /* [Area04] Internal RAM */ +#define M_SIZE_IO_1 502 /* [Area05] I/O area 1 */ +#define M_SIZE_NOR_M 128 /* [Area06] CS0, CS1 area (for NOR flash) (mirror) */ +#define M_SIZE_SDRAM_M 128 /* [Area07] CS2, CS3 area (for SDRAM) (mirror) */ +#define M_SIZE_CS45_M 128 /* [Area08] CS4, CS5 area (mirror) */ +#define M_SIZE_SPI_M 128 /* [Area09] SPI, SP2 area (for Serial flash) (mirror) */ +#define M_SIZE_RAM_M 10 /* [Area10] Internal RAM (mirror) */ +#define M_SIZE_IO_2 2550 /* [Area11] I/O area 2 */ +/* Should add to: 4096 */ + + counter_limit = M_SIZE_NOR; + for (i = 0; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; + } + + counter_limit += M_SIZE_SDRAM; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; + } + + counter_limit += M_SIZE_CS45; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; + } + + counter_limit += M_SIZE_SPI; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; + } + + counter_limit += M_SIZE_RAM; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE; + } + + counter_limit += M_SIZE_IO_1; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; + } + + counter_limit += M_SIZE_NOR_M; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; + } + + counter_limit += M_SIZE_SDRAM_M; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; + } + + counter_limit += M_SIZE_CS45_M; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; + } + + counter_limit += M_SIZE_SPI_M; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; + } + + counter_limit += M_SIZE_RAM_M; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE; + } + + counter_limit += M_SIZE_IO_2; + for (; i < counter_limit; i++) + { + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY; + } + + /********************************************************************************/ + /* This is the end of the example showing how to set up the cache attributes. */ + /********************************************************************************/ + + + /* Clear ASID. */ + cp15reg = 0; + __asm("mcr p15, 0, cp15reg, c13, c0, 1"); + __asm("isb"); + + /* Put the page table address in TTBR. */ + cp15reg = (int)(VOID*)_txm_ttbr1_page_table; + cp15reg |= TTBR0_ATTRIBUTES; + __asm("mcr p15, 0, cp15reg, c2, c0, 0"); + + /* Set the domain to client mode. */ + cp15reg = DACR_CLIENT_MODE; + __asm("mcr p15, 0, cp15reg, c3, c0, 0"); + + +/* Level 2 small page attributes: normal memory, cache & buffer enabled, priviledged access. */ +#define TTB_LEVEL2_NORMAL_CACHE 0x05E + +/* Level 2 clear AP attributes mask. */ +#define TTB_LEVEL2_AP_CLEAR_MASK 0xFFFFFFCF + +/* Attributes for user mode table entry in level 2 table. */ +#define TTB_LEVEL2_USER_MODE_ENTRY 0x06E + + /* Set up Level 2 table for user to kernel mode entry trampoline. */ + /* Find which table entry _txm_module_manager_user_mode_entry is in. */ + user_mode_index = (ULONG)_txm_module_manager_user_mode_entry >> TXM_MMU_LEVEL1_PAGE_SHIFT; + /* Fill table. */ + for (i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = ((ULONG)_txm_module_manager_user_mode_entry & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | TTB_LEVEL2_NORMAL_CACHE; + } + + /* Enter Level 2 table in to master table. */ + _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][user_mode_index] = ((ULONG)_txm_level2_module_page_table & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES; + + /* Find level 2 entry that holds _txm_module_manager_user_mode_entry. */ + user_mode_index = ((ULONG)_txm_module_manager_user_mode_entry & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT; + + /* Set attribute bits for the user mode entry page. */ + _txm_level2_module_page_table[TXM_MASTER_PAGE_TABLE_INDEX][user_mode_index] = (_txm_level2_module_page_table[TXM_MASTER_PAGE_TABLE_INDEX][user_mode_index] & TTB_LEVEL2_AP_CLEAR_MASK) | TTB_LEVEL2_USER_MODE_ENTRY; + + /* Enable the MMU. */ + __asm("mrc p15, 0, cp15reg, c1, c0, 0"); + cp15reg |= 0x1; + __asm("mcr p15, 0, cp15reg, c1, c0, 0"); + + return(TX_SUCCESS); + +#else + return(TX_FEATURE_NOT_ENABLED); +#endif +} diff --git a/ports_module/cortex-a7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex-a7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c new file mode 100644 index 00000000..647efe2f --- /dev/null +++ b/ports_module/cortex-a7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c @@ -0,0 +1,589 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + + +extern TXM_MODULE_INSTANCE *_txm_asid_table[TXM_ASID_TABLE_LENGTH]; +extern ULONG _txm_level2_module_page_table[TXM_MAXIMUM_MODULES][TXM_LEVEL_2_PAGE_TABLE_ENTRIES]; +extern ULONG _txm_ttbr1_page_table[TXM_MAXIMUM_MODULES][TXM_MASTER_PAGE_TABLE_ENTRIES]; + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_inside_data_check Cortex-A7/MMU/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function determines if pointer is within the module's data or */ +/* shared memory. */ +/* */ +/* INPUT */ +/* */ +/* pointer Data pointer */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* TXM_MODULE_MANAGER_DATA_POINTER_CHECK */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_inside_data_check(ULONG pointer) +{ + +ULONG translation; + + /* ATS1CUR operation on address supplied in pointer, Stage 1 unprivileged read. */ + __asm("MCR p15, 0, pointer, c7, c8, 2"); + __asm("ISB"); /* Ensure completion of the MCR write to CP15. */ + __asm("MRC p15, 0, translation, c7, c4, 0"); /* Read result from 32-bit PAR into translation. */ + + if (translation & TXM_ADDRESS_TRANSLATION_FAULT_BIT) + { + return(TX_FALSE); + } + + return(TX_TRUE); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_assign_asid Cortex-A7/MMU/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function assigns an Application Specific ID (ASID) to a */ +/* module. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_assign_asid(TXM_MODULE_INSTANCE *module_instance) +{ +UINT i = 1; + + /* Find first non-zero ASID, starting at index 1. */ + while(i < TXM_ASID_TABLE_LENGTH) + { + if(_txm_asid_table[i] != 0) + { + i++; + } + else + { + module_instance -> txm_module_instance_asid = i; + _txm_asid_table[i] = module_instance; + return(TX_SUCCESS); + } + } + + return(TXM_MODULE_ASID_ERROR); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_remove_asid Cortex-A7/MMU/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function removes a module from the ASID list. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* TXM_MODULE_MANAGER_MODULE_UNLOAD */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_remove_asid(TXM_MODULE_INSTANCE *module_instance) +{ + if(module_instance -> txm_module_instance_asid) + { + _txm_asid_table[module_instance -> txm_module_instance_asid] = 0; + } +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_mm_register_setup Cortex-A7/MMU/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets up the Cortex-A7 MMU register definitions based */ +/* on the module's memory characteristics. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_manager_assign_asid */ +/* */ +/* CALLED BY */ +/* */ +/* TXM_MODULE_MANAGER_MODULE_SETUP */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) +{ +#ifdef TXM_MODULE_MEMORY_PROTECTION_ENABLED + +ULONG start_address; +ULONG end_address; +ULONG mmu_l1_entries; +ULONG mmu_l2_entries = 0; +ULONG level1_index; +ULONG level2_index; +ULONG temp_index; +ULONG temp_address; +ULONG l2_address; +ULONG attributes = 0; +ULONG asid; +UINT i; + + + /* Assign an ASID to this module. */ + _txm_module_manager_assign_asid(module_instance); + + asid = module_instance -> txm_module_instance_asid; + + /* Copy master level 1 page table to module's page table. */ + for(i = 0; i < TXM_MASTER_PAGE_TABLE_ENTRIES; i++) + { + _txm_ttbr1_page_table[asid][i] = _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i]; + } + + /* Clear level 2 tables. */ + for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_START_OFFSET][i] = 0; + _txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_END_OFFSET][i] = 0; + _txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_START_OFFSET][i] = 0; + _txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_END_OFFSET][i] = 0; + } + + /* Get code start and end addresses. */ + start_address = (ULONG)module_instance -> txm_module_instance_code_start; + /* Extend end address to end of page (TXM_MODULE_MEMORY_ALIGNMENT-1). */ + end_address = ((((ULONG)module_instance -> txm_module_instance_code_end) + TXM_MODULE_MEMORY_ALIGNMENT-1) & ~((ULONG)TXM_MODULE_MEMORY_ALIGNMENT-1)) - 1; + + /* How many level 1 table entries does code span? */ + mmu_l1_entries = (end_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) - (start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) + 1; + + /* Add 1 to align. */ + end_address++; + + /* How many level 2 table entries does code need? + * 0: start and end addresses both aligned. + * 1: either start or end address aligned. + * 2: start and end addresses both not aligned. */ + if(start_address & ~TXM_MMU_LEVEL1_MASK) + { + /* If start address is not aligned, increment. */ + mmu_l2_entries++; + } + if(end_address & ~TXM_MMU_LEVEL1_MASK) + { + /* If end address is not aligned, increment. */ + mmu_l2_entries++; + } + + /* Get index into L1 table. */ + level1_index = (start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT); + + /* Set up level 1 table. */ + /* Do start and end entries need level 2 pages? */ + if(mmu_l2_entries > 0) + { + /* If start_address is not aligned, we need a L2 page. */ + if(start_address & ~TXM_MMU_LEVEL1_MASK) + { + /* Is there already a pointer to an L2 page in the L1 table? If bit 0 is set, there is. */ + if(_txm_ttbr1_page_table[asid][level1_index] & 0x01) + { + /* Get L2 page address from L1 table. */ + l2_address = _txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_SECOND_MASK; + + /* Copy the existing L2 page into the module L2 page. */ + for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_START_OFFSET][i] = ((ULONG *) l2_address)[i] | TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE; + } + } + else + { + /* Translate attributes from L1 entry to an L2 entry. */ + attributes = (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_XN_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_XN_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_XN_SHIFT) | + (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_B_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_B_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_B_SHIFT) | + (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_C_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_C_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_C_SHIFT) | + (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_AP_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_AP_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_AP_SHIFT) | + (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_TEX_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_TEX_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_TEX_SHIFT) | + TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE; + + /* Build L2 page with attributes inherited from L1 entry. */ + for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_START_OFFSET][i] = ((ULONG)start_address & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | attributes; + } + } + + /* Put L2 page in L1 table. */ + _txm_ttbr1_page_table[asid][level1_index] = ((ULONG)_txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_START_OFFSET] & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES; + + /* Decrement number of L1 entries remaining. */ + mmu_l1_entries--; + + /* Set up L2 start table. */ + /* Determine how many entries in L2 table. */ + if((end_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) - (start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT)) + { + /* End address goes to next L1 page (or beyond). */ + temp_address = ((start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) + 1) << (TXM_MMU_LEVEL1_PAGE_SHIFT); + mmu_l2_entries = (temp_address - start_address) >> TXM_MMU_LEVEL2_PAGE_SHIFT; + } + else + { + /* End address is on the same L1 page. */ + mmu_l2_entries = (end_address >> TXM_MMU_LEVEL2_PAGE_SHIFT) - (start_address >> TXM_MMU_LEVEL2_PAGE_SHIFT); + } + + /* Insert module settings into start table. */ + level2_index = ((start_address & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT); + for(i = 0; i < mmu_l2_entries; i++, level2_index++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_START_OFFSET][level2_index] = ((ULONG)start_address & TXM_MMU_LEVEL1_MASK) | (level2_index << TXM_MMU_LEVEL2_PAGE_SHIFT) | TXM_MMU_LEVEL2_CODE_ATTRIBUTES; + } + + level1_index++; + } + + /* Does last entry need a level 2 page? */ + /* If end_address is not aligned, we need a L2 page. */ + if((end_address & ~TXM_MMU_LEVEL1_MASK) && (mmu_l1_entries != 0)) + { + /* Get index into L1 table. */ + temp_index = (end_address >> TXM_MMU_LEVEL1_PAGE_SHIFT); + + /* Is there already a pointer to an L2 page in the L1 table? If bit 0 is set, there is. */ + if(_txm_ttbr1_page_table[asid][temp_index] & 0x01) + { + /* Get L2 page address from L1 table. */ + l2_address = _txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_SECOND_MASK; + + /* Copy the existing L2 page into the module L2 page. */ + for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_END_OFFSET][i] = ((ULONG *) l2_address)[i] | TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE; + } + } + else + { + /* Translate attributes from L1 entry to an L2 entry. */ + attributes = (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_XN_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_XN_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_XN_SHIFT) | + (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_B_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_B_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_B_SHIFT) | + (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_C_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_C_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_C_SHIFT) | + (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_AP_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_AP_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_AP_SHIFT) | + (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_TEX_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_TEX_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_TEX_SHIFT) | + TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE; + + /* Build L2 page with attributes inherited from L1 entry. */ + for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_END_OFFSET][i] = ((ULONG)start_address & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | attributes; + } + } + + /* Put L2 page in L1 table. */ + _txm_ttbr1_page_table[asid][temp_index] = ((ULONG)_txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_END_OFFSET] & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES; + + /* Decrement number of L1 entries remaining. */ + mmu_l1_entries--; + + /* Determine how many entries in L2 table. */ + mmu_l2_entries = ((end_address & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT); + + /* Set up L2 end table. */ + for(i = 0; i < mmu_l2_entries; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_END_OFFSET][i] = ((ULONG)end_address & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | TXM_MMU_LEVEL2_CODE_ATTRIBUTES; + } + } + } + + /* Fill any L1 entries between start and end pages of module code range. */ + for(i = 0; i < mmu_l1_entries; i++, level1_index++) + { + /* Place address and attributes in table. */ + _txm_ttbr1_page_table[asid][level1_index] = (level1_index << TXM_MMU_LEVEL1_PAGE_SHIFT) | TXM_MMU_LEVEL1_CODE_ATTRIBUTES; + } + + /**************************************************************************/ + /* At this point, code protection is set up. */ + /* Data protection is set up below. */ + /**************************************************************************/ + + /* Get data start and end addresses. */ + start_address = (ULONG)module_instance -> txm_module_instance_data_start; + end_address = (ULONG)module_instance -> txm_module_instance_data_end; + + /* How many level 1 table entries does data span? */ + mmu_l1_entries = (end_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) - (start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) + 1; + + /* Add 1 to align. */ + end_address++; + + /* How many level 2 table entries does data need? + * 0: start and end addresses both aligned. + * 1: either start or end address aligned. + * 2: start and end addresses both not aligned. */ + if(start_address & ~TXM_MMU_LEVEL1_MASK) + { + /* If start address is not aligned, increment. */ + mmu_l2_entries++; + } + if(end_address & ~TXM_MMU_LEVEL1_MASK) + { + /* If end address is not aligned, increment. */ + mmu_l2_entries++; + } + + /* Get index into L1 table. */ + level1_index = (start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT); + + /* Set up level 1 table. */ + /* Do start and end entries need level 2 pages? */ + if(mmu_l2_entries > 0) + { + /* If start_address is not aligned, we need a L2 page. */ + if(start_address & ~TXM_MMU_LEVEL1_MASK) + { + /* Is there already a pointer to an L2 page in the L1 table? If bit 0 is set, there is. */ + if(_txm_ttbr1_page_table[asid][level1_index] & 0x01) + { + /* Get L2 page address from L1 table. */ + l2_address = _txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_SECOND_MASK; + + /* Copy the existing L2 page into the module L2 page. */ + for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_START_OFFSET][i] = ((ULONG *) l2_address)[i] | TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE; + } + } + else + { + /* Translate attributes from L1 entry to an L2 entry. */ + attributes = (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_XN_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_XN_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_XN_SHIFT) | + (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_B_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_B_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_B_SHIFT) | + (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_C_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_C_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_C_SHIFT) | + (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_AP_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_AP_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_AP_SHIFT) | + (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_TEX_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_TEX_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_TEX_SHIFT) | + TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE; + + /* Build L2 page with attributes inherited from L1 entry. */ + for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_START_OFFSET][i] = ((ULONG)start_address & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | attributes; + } + } + + /* Put L2 page in L1 table. */ + _txm_ttbr1_page_table[asid][level1_index] = ((ULONG)_txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_START_OFFSET] & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES; + + /* Decrement number of L1 entries remaining. */ + mmu_l1_entries--; + + /* Set up L2 start table. */ + /* Determine how many entries in L2 table. */ + if((end_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) - (start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT)) + { + /* End address goes to next L1 page (or beyond). */ + temp_address = ((start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) + 1) << (TXM_MMU_LEVEL1_PAGE_SHIFT); + mmu_l2_entries = (temp_address - start_address) >> TXM_MMU_LEVEL2_PAGE_SHIFT; + } + else + { + /* End address is on the same L1 page. */ + mmu_l2_entries = (end_address >> TXM_MMU_LEVEL2_PAGE_SHIFT) - (start_address >> TXM_MMU_LEVEL2_PAGE_SHIFT); + } + + /* Insert module settings into start table. */ + level2_index = ((start_address & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT); + for(i = 0; i < mmu_l2_entries; i++, level2_index++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_START_OFFSET][level2_index] = ((ULONG)start_address & TXM_MMU_LEVEL1_MASK) | (level2_index << TXM_MMU_LEVEL2_PAGE_SHIFT) | TXM_MMU_LEVEL2_DATA_ATTRIBUTES; + } + + level1_index++; + } + + /* Does last entry need a level 2 page? */ + /* If end_address is not aligned, we need a L2 page. */ + if((end_address & ~TXM_MMU_LEVEL1_MASK) && (mmu_l1_entries != 0)) + { + /* Get index into L1 table. */ + temp_index = (end_address >> TXM_MMU_LEVEL1_PAGE_SHIFT); + + /* Is there already a pointer to an L2 page in the L1 table? If bit 0 is set, there is. */ + if(_txm_ttbr1_page_table[asid][temp_index] & 0x01) + { + /* Get L2 page address from L1 table. */ + l2_address = _txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_SECOND_MASK; + + /* Copy the existing L2 page into the module L2 page. */ + for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_END_OFFSET][i] = ((ULONG *) l2_address)[i] | TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE; + } + } + else + { + /* Translate attributes from L1 entry to an L2 entry. */ + attributes = (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_XN_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_XN_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_XN_SHIFT) | + (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_B_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_B_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_B_SHIFT) | + (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_C_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_C_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_C_SHIFT) | + (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_AP_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_AP_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_AP_SHIFT) | + (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_TEX_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_TEX_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_TEX_SHIFT) | + TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE; + + /* Build L2 page with attributes inherited from L1 entry. */ + for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_END_OFFSET][i] = ((ULONG)start_address & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | attributes; + } + } + + /* Put L2 page in L1 table. */ + _txm_ttbr1_page_table[asid][temp_index] = ((ULONG)_txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_END_OFFSET] & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES; + + /* Decrement number of L1 entries remaining. */ + mmu_l1_entries--; + + /* Determine how many entries in L2 table. */ + mmu_l2_entries = ((end_address & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT); + + /* Set up L2 end table. */ + for(i = 0; i < mmu_l2_entries; i++) + { + _txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_END_OFFSET][i] = ((ULONG)end_address & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | TXM_MMU_LEVEL2_DATA_ATTRIBUTES; + } + } + } + + /* Fill any L1 entries between start and end pages of module data range. */ + for(i = 0; i < mmu_l1_entries; i++, level1_index++) + { + /* Place address and attributes in table. */ + _txm_ttbr1_page_table[asid][level1_index] = (level1_index << TXM_MMU_LEVEL1_PAGE_SHIFT) | TXM_MMU_LEVEL1_DATA_ATTRIBUTES; + } + +#endif +} diff --git a/ports_module/cortex-a7/ac5/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex-a7/ac5/module_manager/src/txm_module_manager_thread_stack_build.s new file mode 100644 index 00000000..ed02093e --- /dev/null +++ b/ports_module/cortex-a7/ac5/module_manager/src/txm_module_manager_thread_stack_build.s @@ -0,0 +1,160 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Module Manager */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +THUMB_MASK EQU 0x20 ; Thumb bit (5) of CPSR/SPSR +USR_MODE EQU 0x10 ; USR mode +SYS_MODE EQU 0x1F ; SYS mode + IF :DEF:TX_ENABLE_FIQ_SUPPORT +CPSR_MASK EQU 0xDF ; Mask initial CPSR, IRQ & FIQ ints enabled + ELSE +CPSR_MASK EQU 0x9F ; Mask initial CPSR, IRQ ints enabled + ENDIF +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _txm_module_manager_thread_stack_build Cortex-A7/MMU/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +;{ + EXPORT _txm_module_manager_thread_stack_build +_txm_module_manager_thread_stack_build +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-A7 should look like the following after it is built: +; +; Stack Top: 1 Interrupt stack frame type +; CPSR Initial value for CPSR +; r0 Initial value for r0 +; r1 Initial value for r1 +; r2 Initial value for r2 +; r3 Initial value for r3 +; r4 Initial value for r4 +; r5 Initial value for r5 +; r6 Initial value for r6 +; r7 Initial value for r7 +; r8 Initial value for r8 +; r9 Initial value for r9 +; r10 Initial value for r10 +; r11 Initial value for r11 +; r12 Initial value for r12 +; lr Initial value for lr (r14) +; pc Initial value for pc (r15) +; 0 For stack backtracing +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #7 ; Ensure 8-byte alignment + SUB r2, r2, #76 ; Allocate space for the stack frame +; +; /* Actually build the stack frame. */ +; + MOV r3, #1 ; Build interrupt stack type + STR r3, [r2, #0] ; Store stack type + STR r0, [r2, #8] ; Store initial r0 (thread pointer) + LDR r3, [r0, #8] ; Pickup thread info pointer (it's in the stack pointer location right now) + STR r3, [r2, #12] ; Store initial r1 + LDR r3, [r3, #8] ; Pickup data base register + STR r3, [r2, #44] ; Store initial r9 + MOV r3, #0 ; Build initial register value + STR r3, [r2, #16] ; Store initial r2 + STR r3, [r2, #20] ; Store initial r3 + STR r3, [r2, #24] ; Store initial r4 + STR r3, [r2, #28] ; Store initial r5 + STR r3, [r2, #32] ; Store initial r6 + STR r3, [r2, #36] ; Store initial r7 + STR r3, [r2, #40] ; Store initial r8 + LDR r3, [r0, #12] ; Pickup stack starting address + STR r3, [r2, #48] ; Store initial r10 (sl) + MOV r3, #0 ; Build initial register value + STR r3, [r2, #52] ; Store initial r11 + STR r3, [r2, #56] ; Store initial r12 + STR r3, [r2, #60] ; Store initial lr + STR r1, [r2, #64] ; Store initial pc + STR r3, [r2, #68] ; 0 for back-trace + MRS r3, CPSR ; Pickup CPSR + BIC r3, r3, #CPSR_MASK ; Mask mode bits of CPSR + TST r1, #1 ; Test if THUMB bit set in initial PC + ORRNE r3, r3, #THUMB_MASK ; Set T bit if set + LDR r1, [r0, #156] ; Load tx_thread_module_current_user_mode + TST r1, #1 ; Test if the flag is set + ORREQ r3, r3, #SYS_MODE ; Flag not set: Build CPSR, SYS mode, IRQ enabled + ORRNE r3, r3, #USR_MODE ; Flag set: Build CPSR, USR mode, IRQ enabled + STR r3, [r2, #4] ; Store initial CPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's control block + BX lr ; Return to caller +;} + END + diff --git a/ports_module/cortex-a7/ac5/module_manager/src/txm_module_manager_user_mode_entry.s b/ports_module/cortex-a7/ac5/module_manager/src/txm_module_manager_user_mode_entry.s new file mode 100644 index 00000000..66b6c4d0 --- /dev/null +++ b/ports_module/cortex-a7/ac5/module_manager/src/txm_module_manager_user_mode_entry.s @@ -0,0 +1,92 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Module Manager */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; + IMPORT _tx_thread_current_ptr + IMPORT _txm_module_manager_kernel_dispatch + + + AREA ||.text||, CODE, READONLY, ALIGN=12 + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _txm_module_manager_user_mode_entry Cortex-A7/MMU/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function allows modules to enter kernel mode. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* SVC 1 Enter kernel mode */ +;/* SVC 2 Exit kernel mode */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Modules in user mode */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ + EXPORT _txm_module_manager_user_mode_entry + EXPORT _txm_system_mode_enter +_txm_module_manager_user_mode_entry +_txm_system_mode_enter + SVC 1 ; Get out of user mode +_txm_module_priv + ; At this point, we are in system mode. + ; Save LR (and r3 for 8 byte aligned stack) and call the kernel dispatch function. + PUSH {r3, lr} + BL _txm_module_manager_kernel_dispatch + POP {r3, lr} + + EXPORT _txm_system_mode_exit +_txm_system_mode_exit + ; Trap to restore user mode while inside of ThreadX + SVC 2 + + BX lr ; Return to the caller + NOP + NOP + + ; Fill up 4kB page. + ALIGN 4096 +_txm_module_manager_user_mode_end + + END diff --git a/ports_module/cortex-m3/ac5/example_build/build.bat b/ports_module/cortex-m3/ac5/example_build/build.bat new file mode 100644 index 00000000..57eae574 --- /dev/null +++ b/ports_module/cortex-m3/ac5/example_build/build.bat @@ -0,0 +1,8 @@ +@ECHO OFF +ECHO Starting build... +CALL build_threadx.bat +CALL build_threadx_demo.bat +CALL build_threadx_module_library.bat +CALL build_threadx_module_demo.bat +CALL build_threadx_module_manager_demo.bat +ECHO Build finished. diff --git a/ports_module/cortex-m3/ac5/example_build/build_threadx.bat b/ports_module/cortex-m3/ac5/example_build/build_threadx.bat new file mode 100644 index 00000000..6bab0fa4 --- /dev/null +++ b/ports_module/cortex-m3/ac5/example_build/build_threadx.bat @@ -0,0 +1,240 @@ +del tx.a +armasm -g --cpu=cortex-m3 --apcs=/interwork tx_initialize_low_level.S +armasm -g --cpu=cortex-m3 --apcs=/interwork ../module_manager/src/tx_thread_stack_build.S +armasm -g --cpu=cortex-m3 --apcs=/interwork ../module_manager/src/tx_thread_schedule.S --diag_suppress=A1581W +armasm -g --cpu=cortex-m3 --apcs=/interwork ../module_manager/src/tx_thread_system_return.S +armasm -g --cpu=cortex-m3 --apcs=/interwork ../module_manager/src/tx_thread_context_save.S +armasm -g --cpu=cortex-m3 --apcs=/interwork ../module_manager/src/tx_thread_context_restore.S +armasm -g --cpu=cortex-m3 --apcs=/interwork ../module_manager/src/tx_thread_interrupt_control.S +armasm -g --cpu=cortex-m3 --apcs=/interwork ../module_manager/src/tx_timer_interrupt.S +armasm -g --cpu=cortex-m3 --apcs=/interwork ../module_manager/src/tx_thread_interrupt_disable.S +armasm -g --cpu=cortex-m3 --apcs=/interwork ../module_manager/src/tx_thread_interrupt_restore.S +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_allocate.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_cleanup.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_create.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_delete.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_info_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_initialize.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_performance_info_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_performance_system_info_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_prioritize.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_release.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_allocate.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_cleanup.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_create.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_delete.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_info_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_initialize.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_performance_info_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_prioritize.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_search.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_release.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_cleanup.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_create.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_delete.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_info_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_initialize.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_performance_info_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_performance_system_info_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_set.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_set_notify.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_initialize_high_level.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_initialize_kernel_enter.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_initialize_kernel_setup.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_cleanup.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_create.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_delete.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_info_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_initialize.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_performance_info_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_performance_system_info_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_prioritize.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_priority_change.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_put.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_cleanup.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_create.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_delete.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_flush.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_front_send.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_info_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_initialize.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_performance_info_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_performance_system_info_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_prioritize.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_receive.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_send.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_send_notify.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_ceiling_put.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_cleanup.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_create.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_delete.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_info_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_initialize.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_performance_info_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_performance_system_info_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_prioritize.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_put.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_put_notify.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_create.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_delete.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_entry_exit_notify.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_identify.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_info_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_initialize.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_performance_info_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_performance_system_info_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_preemption_change.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_priority_change.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_relinquish.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_reset.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_resume.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_shell_entry.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_sleep.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_stack_analyze.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_stack_error_handler.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_stack_error_notify.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_suspend.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_system_preempt_check.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_system_resume.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_system_suspend.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_terminate.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_time_slice.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_time_slice_change.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_timeout.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_wait_abort.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_time_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_time_set.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_activate.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_change.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_create.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_deactivate.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_delete.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_expiration_process.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_info_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_initialize.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_performance_info_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_performance_system_info_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_system_activate.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_system_deactivate.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_thread_entry.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_enable.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_disable.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_initialize.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_interrupt_control.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_isr_enter_insert.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_isr_exit_insert.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_object_register.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_object_unregister.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_user_event_insert.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_buffer_full_notify.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_event_filter.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_event_unfilter.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_block_allocate.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_block_pool_create.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_block_pool_delete.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_block_pool_info_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_block_pool_prioritize.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_block_release.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_allocate.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_pool_create.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_pool_delete.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_pool_info_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_pool_prioritize.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_release.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_create.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_delete.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_info_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_set.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_set_notify.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_create.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_delete.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_info_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_prioritize.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_put.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_create.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_delete.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_flush.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_front_send.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_info_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_prioritize.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_receive.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_send.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_send_notify.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_ceiling_put.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_create.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_delete.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_info_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_prioritize.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_put.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_put_notify.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_create.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_delete.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_entry_exit_notify.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_info_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_preemption_change.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_priority_change.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_relinquish.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_reset.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_resume.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_suspend.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_terminate.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_time_slice_change.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_wait_abort.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_activate.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_change.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_create.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_deactivate.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_delete.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_info_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_application_request.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_callback_request.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_event_flags_notify_trampoline.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_file_load.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_in_place_load.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_internal_load.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_initialize.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_kernel_dispatch.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_maximum_module_priority_set.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_memory_load.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_allocate.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_deallocate.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_pointer_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_pointer_get_extended.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_pool_create.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_properties_get.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_queue_notify_trampoline.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_semaphore_notify_trampoline.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_start.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_stop.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_thread_create.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_thread_notify_trampoline.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_thread_reset.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_timer_notify_trampoline.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_unload.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_util.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_alignment_adjust.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_external_memory_enable.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_memory_fault_handler.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_memory_fault_notify.c +armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_mm_register_setup.c +armasm -g --cpu=cortex-m3 --apcs=/interwork ../module_manager/src/txm_module_manager_thread_stack_build.S +armasm -g --cpu=cortex-m3 --apcs=/interwork ../module_manager/src/txm_module_manager_user_mode_entry.S + +armar --create tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o tx_initialize_low_level.o tx_thread_interrupt_disable.o tx_thread_interrupt_restore.o tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o + +armar -r tx.a tx_event_flags_performance_system_info_get.o tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o + +armar -r tx.a tx_semaphore_put_notify.o tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o + +armar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o + +armar -r tx.a txe_queue_prioritize.o txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o txm_module_manager_alignment_adjust.o txm_module_manager_application_request.o txm_module_manager_callback_request.o txm_module_manager_event_flags_notify_trampoline.o txm_module_manager_external_memory_enable.o txm_module_manager_file_load.o txm_module_manager_in_place_load.o + +armar -r tx.a txm_module_manager_initialize.o txm_module_manager_kernel_dispatch.o txm_module_manager_maximum_module_priority_set.o txm_module_manager_memory_fault_handler.o txm_module_manager_memory_fault_notify.o txm_module_manager_memory_load.o txm_module_manager_object_pointer_get.o txm_module_manager_object_pool_create.o txm_module_manager_queue_notify_trampoline.o txm_module_manager_semaphore_notify_trampoline.o txm_module_manager_mm_register_setup.o txm_module_manager_start.o txm_module_manager_stop.o txm_module_manager_thread_create.o txm_module_manager_thread_notify_trampoline.o txm_module_manager_thread_reset.o txm_module_manager_timer_notify_trampoline.o txm_module_manager_unload.o txm_module_manager_thread_stack_build.o txm_module_manager_internal_load.o txm_module_manager_object_allocate.o txm_module_manager_object_deallocate.o txm_module_manager_object_pointer_get_extended.o txm_module_manager_properties_get.o txm_module_manager_util.o txm_module_manager_user_mode_entry.o diff --git a/ports_module/cortex-m3/ac5/example_build/build_threadx_demo.bat b/ports_module/cortex-m3/ac5/example_build/build_threadx_demo.bat new file mode 100644 index 00000000..8db5bae0 --- /dev/null +++ b/ports_module/cortex-m3/ac5/example_build/build_threadx_demo.bat @@ -0,0 +1,4 @@ +armasm -g --cpu=cortex-m3 --apcs=interwork tx_initialize_low_level.S +armcc -c -g --cpu=cortex-m3 -O2 -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc sample_threadx.c +armlink -d -o sample_threadx.axf --elf --map --ro-base=0x00000000 --rw-base=0x20000000 --first __tx_vectors --datacompressor=off --inline --info=inline --callgraph --list sample_threadx.map tx_initialize_low_level.o sample_threadx.o tx.a + diff --git a/ports_module/cortex-m3/ac5/example_build/build_threadx_module_demo.bat b/ports_module/cortex-m3/ac5/example_build/build_threadx_module_demo.bat new file mode 100644 index 00000000..88d62cbe --- /dev/null +++ b/ports_module/cortex-m3/ac5/example_build/build_threadx_module_demo.bat @@ -0,0 +1,3 @@ +armasm -g --cpu=cortex-m3 --apcs=/interwork/ropi/rwpi txm_module_preamble.S +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi --lower_ropi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc sample_threadx_module.c +armlink -d -o sample_threadx_module.axf --elf --ro=0x30000 --rw=0x40000 --first txm_module_preamble.o(Init) --entry=_txm_module_thread_shell_entry --ropi --rwpi --remove --map --symbols --list sample_threadx_module.map txm_module_preamble.o sample_threadx_module.o txm.a diff --git a/ports_module/cortex-m3/ac5/example_build/build_threadx_module_library.bat b/ports_module/cortex-m3/ac5/example_build/build_threadx_module_library.bat new file mode 100644 index 00000000..e13ade8f --- /dev/null +++ b/ports_module/cortex-m3/ac5/example_build/build_threadx_module_library.bat @@ -0,0 +1,106 @@ +del txm.a + +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_allocate.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_pool_create.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_pool_delete.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_pool_info_get.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_pool_performance_info_get.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_pool_performance_system_info_get.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_pool_prioritize.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_release.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_allocate.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_pool_create.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_pool_delete.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_pool_info_get.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_pool_performance_info_get.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_pool_performance_system_info_get.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_pool_prioritize.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_release.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_create.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_delete.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_get.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_info_get.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_performance_info_get.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_performance_system_info_get.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_set.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_set_notify.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_module_application_request.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_module_callback_request_thread_entry.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_module_object_allocate.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_module_object_deallocate.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_module_object_pointer_get.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_module_thread_system_suspend.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_create.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_delete.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_get.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_info_get.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_performance_info_get.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_performance_system_info_get.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_prioritize.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_put.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_create.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_delete.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_flush.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_front_send.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_info_get.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_performance_info_get.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_performance_system_info_get.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_prioritize.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_receive.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_send.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_send_notify.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_ceiling_put.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_create.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_delete.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_get.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_info_get.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_performance_info_get.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_performance_system_info_get.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_prioritize.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_put.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_put_notify.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_create.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_delete.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_entry_exit_notify.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_identify.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_info_get.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_interrupt_control.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_performance_info_get.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_performance_system_info_get.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_preemption_change.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_priority_change.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_relinquish.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_reset.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_resume.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_sleep.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_stack_error_notify.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_suspend.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_terminate.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_time_slice_change.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_wait_abort.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_time_get.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_time_set.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_activate.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_change.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_create.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_deactivate.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_delete.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_info_get.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_performance_info_get.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_performance_system_info_get.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_buffer_full_notify.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_disable.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_enable.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_event_filter.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_event_unfilter.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_isr_enter_insert.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_isr_exit_insert.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_user_event_insert.c +armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ..//module_lib/src/txm_module_thread_shell_entry.c +armasm -g --cpu=cortex-m3 --apcs=/interwork/ropi/rwpi --cpreproc --cpreproc_opts=-D,TXM_ASSEMBLY --cpreproc_opts=-D,TXM_MODULE_HEAP_SIZE=512 -I../inc ../module_lib/src/txm_module_initialize.S + +armar --create txm.a txm_block_allocate.o txm_block_pool_create.o txm_block_pool_delete.o txm_block_pool_info_get.o txm_block_pool_performance_info_get.o txm_block_pool_performance_system_info_get.o txm_block_pool_prioritize.o txm_block_release.o txm_byte_allocate.o txm_byte_pool_create.o txm_byte_pool_delete.o txm_byte_pool_info_get.o txm_byte_pool_performance_info_get.o txm_byte_pool_performance_system_info_get.o txm_byte_pool_prioritize.o txm_byte_release.o txm_event_flags_create.o txm_event_flags_delete.o txm_event_flags_get.o txm_event_flags_info_get.o txm_event_flags_performance_info_get.o txm_event_flags_performance_system_info_get.o txm_event_flags_set.o txm_event_flags_set_notify.o txm_module_application_request.o txm_module_callback_request_thread_entry.o txm_module_initialize.o txm_module_object_allocate.o txm_module_object_deallocate.o txm_module_object_pointer_get.o txm_module_thread_shell_entry.o txm_module_thread_system_suspend.o txm_mutex_create.o txm_mutex_delete.o txm_mutex_get.o + +armar -r txm.a txm_mutex_info_get.o txm_mutex_performance_info_get.o txm_mutex_performance_system_info_get.o txm_mutex_prioritize.o txm_mutex_put.o txm_queue_create.o txm_queue_delete.o txm_queue_flush.o txm_queue_front_send.o txm_queue_info_get.o txm_queue_performance_info_get.o txm_queue_performance_system_info_get.o txm_queue_prioritize.o txm_queue_receive.o txm_queue_send.o txm_queue_send_notify.o txm_semaphore_ceiling_put.o txm_semaphore_create.o txm_semaphore_delete.o txm_semaphore_get.o txm_semaphore_info_get.o txm_semaphore_performance_info_get.o txm_semaphore_performance_system_info_get.o txm_semaphore_prioritize.o txm_semaphore_put.o txm_semaphore_put_notify.o txm_thread_create.o txm_thread_delete.o txm_thread_entry_exit_notify.o txm_thread_identify.o txm_thread_info_get.o txm_thread_interrupt_control.o txm_thread_performance_info_get.o txm_thread_performance_system_info_get.o txm_thread_preemption_change.o txm_thread_priority_change.o txm_thread_relinquish.o txm_thread_reset.o txm_thread_resume.o + +armar -r txm.a txm_thread_sleep.o txm_thread_stack_error_notify.o txm_thread_suspend.o txm_thread_terminate.o txm_thread_time_slice_change.o txm_thread_wait_abort.o txm_time_get.o txm_time_set.o txm_timer_activate.o txm_timer_change.o txm_timer_create.o txm_timer_deactivate.o txm_timer_delete.o txm_timer_info_get.o txm_timer_performance_info_get.o txm_timer_performance_system_info_get.o txm_trace_buffer_full_notify.o txm_trace_disable.o txm_trace_enable.o txm_trace_event_filter.o txm_trace_event_unfilter.o txm_trace_isr_enter_insert.o txm_trace_isr_exit_insert.o txm_trace_user_event_insert.o diff --git a/ports_module/cortex-m3/ac5/example_build/build_threadx_module_manager_demo.bat b/ports_module/cortex-m3/ac5/example_build/build_threadx_module_manager_demo.bat new file mode 100644 index 00000000..1f75dae8 --- /dev/null +++ b/ports_module/cortex-m3/ac5/example_build/build_threadx_module_manager_demo.bat @@ -0,0 +1,3 @@ +armasm -g --cpu=cortex-m3 --apcs=interwork tx_initialize_low_level.S +armcc -g --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc sample_threadx_module_manager.c +armlink -d -o sample_threadx_module_manager.axf --elf --ro 0x00000000 --first tx_initialize_low_level.o(RESET) --remove --map --symbols --list sample_threadx_module_manager.map tx_initialize_low_level.o sample_threadx_module_manager.o tx.a diff --git a/ports_module/cortex-m3/ac5/example_build/clean.bat b/ports_module/cortex-m3/ac5/example_build/clean.bat new file mode 100644 index 00000000..3217f01b --- /dev/null +++ b/ports_module/cortex-m3/ac5/example_build/clean.bat @@ -0,0 +1,2 @@ +@ECHO OFF +DEL *.o *.a *.axf *.map diff --git a/ports_module/cortex-m3/ac5/example_build/sample_threadx.c b/ports_module/cortex-m3/ac5/example_build/sample_threadx.c new file mode 100644 index 00000000..418ec634 --- /dev/null +++ b/ports_module/cortex-m3/ac5/example_build/sample_threadx.c @@ -0,0 +1,369 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports_module/cortex-m3/ac5/example_build/sample_threadx_module.c b/ports_module/cortex-m3/ac5/example_build/sample_threadx_module.c new file mode 100644 index 00000000..f2647144 --- /dev/null +++ b/ports_module/cortex-m3/ac5/example_build/sample_threadx_module.c @@ -0,0 +1,432 @@ +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, + event flags group, byte pool, and block pool. */ + +/* Specify that this is a module! */ + +#define TXM_MODULE + + +/* Include the ThreadX module definitions. */ + +#include "txm_module.h" + + +/* Define constants. */ + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the external memory area. */ + +#define EXTERNAL_MEMORY_SIZE (64 * 1024) +#define EXTERNAL_MEMORY (0x80000) + + +/* Define the pool space in the bss section of the module. ULONG is used to + get the word alignment. */ + +ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD *thread_0; +TX_THREAD *thread_1; +TX_THREAD *thread_2; +TX_THREAD *thread_3; +TX_THREAD *thread_4; +TX_THREAD *thread_5; +TX_THREAD *thread_6; +TX_THREAD *thread_7; +TX_QUEUE *queue_0; +TX_SEMAPHORE *semaphore_0; +TX_MUTEX *mutex_0; +TX_EVENT_FLAGS_GROUP *event_flags_0; +TX_BYTE_POOL *byte_pool_0; +TX_BLOCK_POOL *block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; +ULONG semaphore_0_puts; +ULONG event_0_sets; +ULONG queue_0_sends; + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + +void semaphore_0_notify(TX_SEMAPHORE *semaphore_ptr) +{ + + if (semaphore_ptr == semaphore_0) + semaphore_0_puts++; +} + + +void event_0_notify(TX_EVENT_FLAGS_GROUP *event_flag_group_ptr) +{ + + if (event_flag_group_ptr == event_flags_0) + event_0_sets++; +} + + +void queue_0_notify(TX_QUEUE *queue_ptr) +{ + + if (queue_ptr == queue_0) + queue_0_sends++; +} + + +/* Define the module start function. */ + +void demo_module_start(ULONG id) +{ + +CHAR *pointer; + + /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + the control block(s). */ + txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_2, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_3, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_4, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_5, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_6, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_7, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&queue_0, sizeof(TX_QUEUE)); + txm_module_object_allocate((void*)&semaphore_0, sizeof(TX_SEMAPHORE)); + txm_module_object_allocate((void*)&mutex_0, sizeof(TX_MUTEX)); + txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); + txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); + txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(queue_0, "module queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + tx_queue_send_notify(queue_0, queue_0_notify); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(semaphore_0, "module semaphore 0", 1); + + tx_semaphore_put_notify(semaphore_0, semaphore_0_notify); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(event_flags_0, "module event flags 0"); + + tx_event_flags_set_notify(event_flags_0, event_0_notify); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(mutex_0, "module mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(block_pool_0, "module block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + /* Test external memory sharing. */ + *(ULONG *)EXTERNAL_MEMORY = 0xABABABAB; + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + diff --git a/ports_module/cortex-m3/ac5/example_build/sample_threadx_module_manager.c b/ports_module/cortex-m3/ac5/example_build/sample_threadx_module_manager.c new file mode 100644 index 00000000..210f0be0 --- /dev/null +++ b/ports_module/cortex-m3/ac5/example_build/sample_threadx_module_manager.c @@ -0,0 +1,126 @@ +/* Small demonstration of the ThreadX module manager. */ + +#include "tx_api.h" +#include "txm_module.h" + + +#define DEMO_STACK_SIZE 1024 + +/* Define the ThreadX object control blocks... */ + +TX_THREAD module_manager; +TXM_MODULE_INSTANCE my_module; + + +/* Define the object pool area. */ + +UCHAR object_memory[16384]; + + +/* Define the module data pool area. */ + +#define MODULE_DATA_SIZE (256 * 1024) +#define MODULE_DATA (0x40000) + + +/* The module code should be loaded here. */ + +#define MODULE_CODE (0x30000) + + +/* Define the external memory area. */ + +#define EXTERNAL_MEMORY_SIZE (64 * 1024) +#define EXTERNAL_MEMORY (0x80000) + + +/* Define the count of memory faults. */ + +ULONG memory_faults; + + +/* Define thread prototypes. */ + +void module_manager_entry(ULONG thread_input); + + +/* Define fault handler. */ + +VOID module_fault_handler(TX_THREAD *thread, TXM_MODULE_INSTANCE *module) +{ + + /* Just increment the fault counter. */ + memory_faults++; +} + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = (CHAR*)first_unused_memory; + + + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + pointer = pointer + DEMO_STACK_SIZE; +} + + + + +/* Define the test threads. */ + +void module_manager_entry(ULONG thread_input) +{ + + /* Initialize the module manager. */ + txm_module_manager_initialize((void *) MODULE_DATA, MODULE_DATA_SIZE); + + txm_module_manager_object_pool_create(object_memory, sizeof(object_memory)); + + /* Register a fault handler. */ + txm_module_manager_memory_fault_notify(module_fault_handler); + + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ + txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE); + + /* Enable a read/write shared memory region. */ + txm_module_manager_external_memory_enable(&my_module, (void *) EXTERNAL_MEMORY, EXTERNAL_MEMORY_SIZE, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); + + /* Start the module. */ + txm_module_manager_start(&my_module); + + /* Sleep for a while.... */ + tx_thread_sleep(1000); + + /* Stop the module. */ + txm_module_manager_stop(&my_module); + + /* Unload the module. */ + txm_module_manager_unload(&my_module); + + /* Load the module that is already there. */ + txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE); + + /* Start the module again. */ + txm_module_manager_start(&my_module); + + /* Now just spin... */ + while(1) + { + + tx_thread_sleep(100); + } +} diff --git a/ports_module/cortex-m3/ac5/example_build/setenv.bat b/ports_module/cortex-m3/ac5/example_build/setenv.bat new file mode 100644 index 00000000..965f12f3 --- /dev/null +++ b/ports_module/cortex-m3/ac5/example_build/setenv.bat @@ -0,0 +1,13 @@ +@echo off + +REM *** ARM DS 2020 +REM SET PATH=%ProgramFiles%\Arm\Development Studio 2020.0\sw\ARMCompiler5.06u6\bin;%PATH% +REM SET ARMLMD_LICENSE_FILE=%APPDATA%\arm\ds\licenses +REM SET ARM_CONFIG_PATH=%APPDATA%\arm\ds\2020.0 +REM SET ARM_PRODUCT_DEF=%ProgramFiles%\Arm\Development Studio 2020.0\sw\mappings\gold.elmap + +REM *** legacy ARM DS 5 +SET PATH=%ProgramFiles%\DS-5 v5.29.3\sw\ARMCompiler5.06u6\bin;%PATH% +SET ARMLMD_LICENSE_FILE=%APPDATA%\ARM\DS-5\licenses +SET ARM_CONFIG_PATH=%APPDATA%\ARM\DS-5_v5.29.3 +SET ARM_PRODUCT_PATH=%ProgramFiles%\DS-5 v5.29.3\sw\mappings diff --git a/ports_module/cortex-m3/ac5/example_build/tx_initialize_low_level.S b/ports_module/cortex-m3/ac5/example_build/tx_initialize_low_level.S new file mode 100644 index 00000000..246c7010 --- /dev/null +++ b/ports_module/cortex-m3/ac5/example_build/tx_initialize_low_level.S @@ -0,0 +1,285 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_initialize.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IMPORT _tx_thread_system_stack_ptr + IMPORT _tx_initialize_unused_memory + IMPORT _tx_thread_context_save + IMPORT _tx_thread_context_restore + IMPORT _tx_timer_interrupt + IMPORT __main + IMPORT |Image$$RO$$Limit| + IMPORT |Image$$RW$$Base| + IMPORT |Image$$ZI$$Base| + IMPORT |Image$$ZI$$Limit| + IMPORT __tx_PendSVHandler + IMPORT __tx_SVCallHandler + IMPORT MemManage_Handler +; +; +SYSTEM_CLOCK EQU 6000000 +SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1) +; +; +;/* Setup the stack and heap areas. */ +; +STACK_SIZE EQU 0x00000400 +HEAP_SIZE EQU 0x00000000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +StackMem + SPACE STACK_SIZE +__initial_sp + + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +HeapMem + SPACE HEAP_SIZE +__heap_limit + + + AREA RESET, CODE, READONLY +; + EXPORT __tx_vectors + EXPORT __vector_table +__vector_table +__tx_vectors + DCD __initial_sp ; Reset and system stack ptr + DCD Reset_Handler ; Reset goes to startup function + DCD __tx_NMIHandler ; NMI + DCD __tx_BadHandler ; HardFault + DCD MemManage_Handler ; MemManage + DCD 0 ; BusFault + DCD 0 ; UsageFault + DCD 0 ; 7 + DCD 0 ; 8 + DCD 0 ; 9 + DCD 0 ; 10 + DCD __tx_SVCallHandler ; SVCall + DCD __tx_DBGHandler ; Monitor + DCD 0 ; 13 + DCD __tx_PendSVHandler ; PendSV + DCD __tx_SysTickHandler ; SysTick + DCD __tx_IntHandler ; Int 0 + DCD __tx_IntHandler ; Int 1 + DCD __tx_IntHandler ; Int 2 + DCD __tx_IntHandler ; Int 3 + +; +; + AREA ||.text||, CODE, READONLY + EXPORT Reset_Handler +Reset_Handler + CPSID i + IF {TARGET_FPU_VFP} = {TRUE} + LDR r0, =0xE000ED88 ; Pickup address of CPACR + LDR r1, [r0] ; Pickup CPACR + MOV32 r2, 0x00F00000 ; Build enable value + ORR r1, r1, r2 ; Or in enable value + STR r1, [r0] ; Setup CPACR + ENDIF + LDR r0, =__main + BX r0 + + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-M3/MPU/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + EXPORT _tx_initialize_low_level +_tx_initialize_low_level +; +; /* Disable interrupts during ThreadX initialization. */ +; + CPSID i +; +; /* Set base of available memory to end of non-initialised RAM area. */ +; + LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer + LDR r1, =|Image$$ZI$$Limit| ; Build first free address + ADD r1, r1, #4 ; + STR r1, [r0] ; Setup first unused memory pointer +; +; /* Setup Vector Table Offset Register. */ +; + MOV r0, #0xE000E000 ; Build address of NVIC registers + LDR r1, =__tx_vectors ; Pickup address of vector table + STR r1, [r0, #0xD08] ; Set vector table address +; +; /* Enable the cycle count register. */ +; +; LDR r0, =0xE0001000 ; Build address of DWT register +; LDR r1, [r0] ; Pickup the current value +; ORR r1, r1, #1 ; Set the CYCCNTENA bit +; STR r1, [r0] ; Enable the cycle count register +; +; /* Set system stack pointer from vector value. */ +; + LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer + LDR r1, =__tx_vectors ; Pickup address of vector table + LDR r1, [r1] ; Pickup reset stack pointer + STR r1, [r0] ; Save system stack pointer +; +; /* Configure SysTick. */ +; + MOV r0, #0xE000E000 ; Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] ; Setup SysTick Reload Value + MOV r1, #0x7 ; Build SysTick Control Enable Value + STR r1, [r0, #0x10] ; Setup SysTick Control +; +; /* Configure handler priorities. */ +; + LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] ; Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] ; Setup System Handlers 8-11 Priority Registers + ; Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] ; Setup System Handlers 12-15 Priority Registers + ; Note: PnSV must be lowest priority, which is 0xFF +; +; /* Return to caller. */ +; + BX lr +;} +; +; +;/* Define initial heap/stack routine for the ARM RVCT startup code. +; This routine will set the initial stack and heap locations */ +; + EXPORT __user_initial_stackheap +__user_initial_stackheap + LDR r0, =HeapMem + LDR r1, =(StackMem + STACK_SIZE) + LDR r2, =(HeapMem + HEAP_SIZE) + LDR r3, =StackMem + BX lr +; +; +;/* Define shells for each of the unused vectors. */ +; + EXPORT __tx_BadHandler +__tx_BadHandler + B __tx_BadHandler + +; EXPORT __tx_SVCallHandler +;__tx_SVCallHandler +; B __tx_SVCallHandler + + EXPORT __tx_IntHandler +__tx_IntHandler +; VOID InterruptHandler (VOID) +; { + PUSH {lr} + +; /* Do interrupt handler work here */ +; /* .... */ + + POP {lr} + BX LR +; } + + EXPORT __tx_SysTickHandler +__tx_SysTickHandler +; VOID TimerInterruptHandler (VOID) +; { +; + PUSH {lr} + BL _tx_timer_interrupt + POP {lr} + BX LR +; } + + EXPORT __tx_NMIHandler +__tx_NMIHandler + B __tx_NMIHandler + + EXPORT __tx_DBGHandler +__tx_DBGHandler + B __tx_DBGHandler + + EXPORT _tx_execution_thread_enter +_tx_execution_thread_enter + BX LR + + EXPORT _tx_execution_thread_exit +_tx_execution_thread_exit + BX LR + + ALIGN + LTORG + END + + diff --git a/ports_module/cortex-m3/ac5/example_build/txm_module_preamble.S b/ports_module/cortex-m3/ac5/example_build/txm_module_preamble.S new file mode 100644 index 00000000..1e7a1800 --- /dev/null +++ b/ports_module/cortex-m3/ac5/example_build/txm_module_preamble.S @@ -0,0 +1,69 @@ + AREA Init, CODE, READONLY + + PRESERVE8 + + ; Define public symbols + + EXPORT __txm_module_preamble + + + ; Define application-specific start/stop entry points for the module + + EXTERN demo_module_start + + + ; Define common external references + + IMPORT _txm_module_thread_shell_entry + IMPORT _txm_module_callback_request_thread_entry + IMPORT |Image$$ER_RO$$Length| + IMPORT |Image$$ER_RW$$Length| + IMPORT |Image$$ER_RW$$RW$$Length| + IMPORT |Image$$ER_RW$$ZI$$Length| + IMPORT |Image$$ER_ZI$$ZI$$Length| + +__txm_module_preamble + DCD 0x4D4F4455 ; Module ID + DCD 0x6 ; Module Major Version + DCD 0x1 ; Module Minor Version + DCD 32 ; Module Preamble Size in 32-bit words + DCD 0x12345678 ; Module ID (application defined) + DCD 0x01000007 ; Module Properties where: + ; Bits 31-24: Compiler ID + ; 0 -> IAR + ; 1 -> ARM + ; 2 -> GNU + ; Bit 0: 0 -> Privileged mode execution + ; 1 -> User mode execution + ; Bit 1: 0 -> No MPU protection + ; 1 -> MPU protection (must have user mode selected) + ; Bit 2: 0 -> Disable shared/external memory access + ; 1 -> Enable shared/external memory access + DCD _txm_module_thread_shell_entry - __txm_module_preamble ; Module Shell Entry Point + DCD demo_module_start - __txm_module_preamble ; Module Start Thread Entry Point + DCD 0 ; Module Stop Thread Entry Point + DCD 1 ; Module Start/Stop Thread Priority + DCD 1024 ; Module Start/Stop Thread Stack Size + DCD _txm_module_callback_request_thread_entry - __txm_module_preamble ; Module Callback Thread Entry + DCD 1 ; Module Callback Thread Priority + DCD 1024 ; Module Callback Thread Stack Size + DCD |Image$$ER_RO$$Length| + |Image$$ER_RW$$Length| ; Module Code Size + DCD |Image$$ER_RW$$Length| + |Image$$ER_ZI$$ZI$$Length| ; Module Data Size + DCD 0 ; Reserved 0 + DCD 0 ; Reserved 1 + DCD 0 ; Reserved 2 + DCD 0 ; Reserved 3 + DCD 0 ; Reserved 4 + DCD 0 ; Reserved 5 + DCD 0 ; Reserved 6 + DCD 0 ; Reserved 7 + DCD 0 ; Reserved 8 + DCD 0 ; Reserved 9 + DCD 0 ; Reserved 10 + DCD 0 ; Reserved 11 + DCD 0 ; Reserved 12 + DCD 0 ; Reserved 13 + DCD 0 ; Reserved 14 + DCD 0 ; Reserved 15 + + END diff --git a/ports_module/cortex-m3/ac5/inc/tx_port.h b/ports_module/cortex-m3/ac5/inc/tx_port.h new file mode 100644 index 00000000..47490dfa --- /dev/null +++ b/ports_module/cortex-m3/ac5/inc/tx_port.h @@ -0,0 +1,470 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-M3/AC5 */ +/* 6.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX Cortex-M3 port. */ + +#define TX_INT_DISABLE 1 /* Disable interrupts */ +#define TX_INT_ENABLE 0 /* Enable interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0 + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); + +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) + +#ifndef TX_MISRA_ENABLE +register unsigned int _ipsr __asm("ipsr"); +#endif + +#ifdef __TARGET_FPU_VFP + +#ifdef TX_MISRA_ENABLE + +ULONG _tx_misra_control_get(void); +void _tx_misra_control_set(ULONG value); +ULONG _tx_misra_fpccr_get(void); +void _tx_misra_vfp_touch(void); + +#else + +#ifdef TX_SOURCE_CODE + +register ULONG _control __asm("control"); + +#endif +#endif + +/* A completed thread falls into _thread_shell_entry and we can simply deactivate the FPU via CONTROL.FPCA + in order to ensure no lazy stacking will occur. */ + +#ifndef TX_MISRA_ENABLE + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _control; \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _control = _tx_vfp_state; \ + } +#else + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } + +#endif + + +/* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. + If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + the lazy FPU save, then restore the CONTROL.FPCA state. */ + +#ifndef TX_MISRA_ENABLE + +void _tx_vfp_access(void); + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _control; \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _control = _tx_vfp_state; \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = *((ULONG *) 0xE000EF34); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _control; \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + _tx_vfp_access(); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = _control; \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _control = _tx_vfp_state; \ + } \ + } \ + } \ + } +#else + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = _tx_misra_fpccr_get(); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + _tx_misra_vfp_touch(); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + } \ + } \ + } +#endif + +#else + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + +#endif + + + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define the get system state macro. */ + +#ifndef TX_THREAD_GET_SYSTEM_STATE +#ifndef TX_MISRA_ENABLE +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _ipsr) +#else +ULONG _tx_misra_ipsr_get(VOID); +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get()) +#endif +#endif + + +/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value + indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h + for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always + zero after initialization for Cortex-M ports. */ + +#ifndef TX_THREAD_SYSTEM_RETURN_CHECK +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#endif + + +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to + prevent early scheduling on Cortex-M parts. */ + +#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; + + +/* This ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); + +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifdef TX_DISABLE_INLINE + +UINT _tx_thread_interrupt_disable(VOID); +VOID _tx_thread_interrupt_restore(UINT previous_posture); + +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); + +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA unsigned int was_masked; +#define TX_DISABLE was_masked = __disable_irq(); +#define TX_RESTORE if (was_masked == 0) __enable_irq(); + +#define _tx_thread_system_return _tx_thread_system_return_inline + + +static void _tx_thread_system_return_inline(void) +{ +unsigned int was_masked; + + + /* Set PendSV to invoke ThreadX scheduler. */ + *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + if (_ipsr == 0) + { + was_masked = __disable_irq(); + __enable_irq(); + if (was_masked != 0) + __disable_irq(); + } +} +#endif + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/AC5 Version 6.1 *"; +#else +#ifdef TX_MISRA_ENABLE +extern CHAR _tx_version_id[100]; +#else +extern CHAR _tx_version_id[]; +#endif +#endif + + +#endif + + + + diff --git a/ports_module/cortex-m3/ac5/inc/txm_module_port.h b/ports_module/cortex-m3/ac5/inc/txm_module_port.h new file mode 100644 index 00000000..c61a9346 --- /dev/null +++ b/ports_module/cortex-m3/ac5/inc/txm_module_port.h @@ -0,0 +1,338 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* txm_module_port.h Cortex-M3/MPU/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the basic module constants, interface structures, */ +/* and function prototypes. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TXM_MODULE_PORT_H +#define TXM_MODULE_PORT_H + +/* Determine if the optional Modules user define file should be used. */ + +#ifdef TXM_MODULE_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in txm_module_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "txm_module_user.h" +#endif + +/* It is assumed that the base ThreadX tx_port.h file has been modified to add the + following extensions to the ThreadX thread control block (this code should replace + the corresponding macro define in tx_port.h): + +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; + +The following extensions must also be defined in tx_port.h: + +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); + +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); +*/ + + +/* Size of module heap. */ +#define TXM_MODULE_HEAP_SIZE 512 + + +/* Define the kernel stack size for a module thread. */ +#ifndef TXM_MODULE_KERNEL_STACK_SIZE +#define TXM_MODULE_KERNEL_STACK_SIZE 768 +#endif + +/* For the following 3 access control settings, change TEX and C, B, S (bits 21 through 16 of MPU_RASR) + * to reflect your system memory attributes (cache, shareable, memory type). */ +/* Code region access control: privileged read-only, outer & inner write-back, normal memory, shareable. */ +#define TXM_MODULE_MPU_CODE_ACCESS_CONTROL 0x06070000 +/* Data region access control: execute never, read/write, outer & inner write-back, normal memory, shareable. */ +#define TXM_MODULE_MPU_DATA_ACCESS_CONTROL 0x13070000 +/* Shared region access control: execute never, read-only, outer & inner write-back, normal memory, shareable. */ +#define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 + + +/* Define constants specific to the tools the module can be built with for this particular modules port. */ + +#define TXM_MODULE_IAR_COMPILER 0x00000000 +#define TXM_MODULE_RVDS_COMPILER 0x01000000 +#define TXM_MODULE_GNU_COMPILER 0x02000000 +#define TXM_MODULE_COMPILER_MASK 0xFF000000 +#define TXM_MODULE_OPTIONS_MASK 0x000000FF + + +/* Define the properties for this particular module port. */ + +#define TXM_MODULE_MEMORY_PROTECTION_ENABLED + +#ifdef TXM_MODULE_MEMORY_PROTECTION_ENABLED +#define TXM_MODULE_REQUIRE_ALLOCATED_OBJECT_MEMORY +#else +#define TXM_MODULE_REQUIRE_LOCAL_OBJECT_MEMORY +#endif + +#define TXM_MODULE_USER_MODE 0x00000001 +#define TXM_MODULE_MEMORY_PROTECTION 0x00000002 +#define TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS 0x00000004 + + +/* Define the supported options for this module. */ + +#define TXM_MODULE_MANAGER_SUPPORTED_OPTIONS (TXM_MODULE_USER_MODE | TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS) +#define TXM_MODULE_MANAGER_REQUIRED_OPTIONS 0 + + +/* Define offset adjustments according to the compiler used to build the module. */ + +#define TXM_MODULE_IAR_SHELL_ADJUST 24 +#define TXM_MODULE_IAR_START_ADJUST 28 +#define TXM_MODULE_IAR_STOP_ADJUST 32 +#define TXM_MODULE_IAR_CALLBACK_ADJUST 44 + +#define TXM_MODULE_RVDS_SHELL_ADJUST 0 +#define TXM_MODULE_RVDS_START_ADJUST 0 +#define TXM_MODULE_RVDS_STOP_ADJUST 0 +#define TXM_MODULE_RVDS_CALLBACK_ADJUST 0 + +#define TXM_MODULE_GNU_SHELL_ADJUST 24 +#define TXM_MODULE_GNU_START_ADJUST 28 +#define TXM_MODULE_GNU_STOP_ADJUST 32 +#define TXM_MODULE_GNU_CALLBACK_ADJUST 44 + + +/* Define other module port-specific constants. */ + +/* Define INLINE_DECLARE to inline for ARM compiler. */ + +#define INLINE_DECLARE inline + +/* Define the number of MPU entries assigned to the code and data sections. On Cortex-M parts, there can only be 7 total + entries, since ThreadX uses one for access to the kernel dispatch function. */ + +#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 +#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 +#define TXM_MODULE_MANAGER_SHARED_MPU_INDEX 8 +#define TXM_MODULE_MANAGER_SHARED_MPU_REGION 4 + +/* Shared memory region attributes. */ +#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 +#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 + +/* Define the port-extensions to the module manager instance structure. */ + +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + ULONG txm_module_instance_mpu_registers[16]; \ + ULONG txm_module_instance_shared_memory_address; \ + ULONG txm_module_instance_shared_memory_length; + + +/* Define the memory fault information structure that is populated when a memory fault occurs. */ + + +typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT +{ + TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr; + VOID *txm_module_manager_memory_fault_info_code_location; + ULONG txm_module_manager_memory_fault_info_shcsr; + ULONG txm_module_manager_memory_fault_info_cfsr; + ULONG txm_module_manager_memory_fault_info_mmfar; + ULONG txm_module_manager_memory_fault_info_bfar; + ULONG txm_module_manager_memory_fault_info_control; + ULONG txm_module_manager_memory_fault_info_sp; + ULONG txm_module_manager_memory_fault_info_r0; + ULONG txm_module_manager_memory_fault_info_r1; + ULONG txm_module_manager_memory_fault_info_r2; + ULONG txm_module_manager_memory_fault_info_r3; + ULONG txm_module_manager_memory_fault_info_r4; + ULONG txm_module_manager_memory_fault_info_r5; + ULONG txm_module_manager_memory_fault_info_r6; + ULONG txm_module_manager_memory_fault_info_r7; + ULONG txm_module_manager_memory_fault_info_r8; + ULONG txm_module_manager_memory_fault_info_r9; + ULONG txm_module_manager_memory_fault_info_r10; + ULONG txm_module_manager_memory_fault_info_r11; + ULONG txm_module_manager_memory_fault_info_r12; + ULONG txm_module_manager_memory_fault_info_lr; + ULONG txm_module_manager_memory_fault_info_xpsr; +} TXM_MODULE_MANAGER_MEMORY_FAULT_INFO; + + +#define TXM_MODULE_MANAGER_FAULT_INFO \ + TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info; + +/* Define the macro to check the code alignment. */ + +#define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment) \ + { \ + ULONG temp; \ + temp = (ULONG) module_location; \ + temp = temp & (code_alignment - 1); \ + if (temp) \ + { \ + _tx_mutex_put(&_txm_module_manager_mutex); \ + return(TXM_MODULE_ALIGNMENT_ERROR); \ + } \ + } + + +/* Define the macro to adjust the alignment and size for code/data areas. */ + +#define TXM_MODULE_MANAGER_ALIGNMENT_ADJUST(module_preamble, code_size, code_alignment, data_size, data_alignment) _txm_module_manager_alignment_adjust(module_preamble, &code_size, &code_alignment, &data_size, &data_alignment); + + +/* Define the macro to adjust the symbols in the module preamble. */ + +#define TXM_MODULE_MANAGER_CALCULATE_ADJUSTMENTS(properties, shell_function_adjust, start_function_adjust, stop_function_adjust, callback_function_adjust) \ + if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_IAR_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_IAR_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_IAR_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_IAR_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_IAR_CALLBACK_ADJUST; \ + } \ + else if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_RVDS_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_RVDS_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_RVDS_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_RVDS_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_RVDS_CALLBACK_ADJUST; \ + } \ + else \ + { \ + shell_function_adjust = TXM_MODULE_GNU_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_GNU_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_GNU_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_GNU_CALLBACK_ADJUST; \ + } + + +/* Define the macro to populate the thread control block with module port-specific information. + Check if the module is in user mode and set up txm_module_thread_entry_info_kernel_call_dispatcher accordingly. +*/ + +#define TXM_MODULE_MANAGER_THREAD_SETUP(thread_ptr, module_instance) \ + thread_ptr -> tx_thread_module_current_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \ + thread_ptr -> tx_thread_module_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \ + if (thread_ptr -> tx_thread_module_user_mode) \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_user_mode_entry; \ + } \ + else \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_kernel_dispatch; \ + } + + +/* Define the macro to populate the module control block with module port-specific information. + If memory protection is enabled, set up the MPU registers. +*/ +#define TXM_MODULE_MANAGER_MODULE_SETUP(module_instance) \ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE) \ + { \ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) \ + { \ + _txm_module_manager_mm_register_setup(module_instance); \ + } \ + } \ + else \ + { \ + /* Do nothing. */ \ + } + +/* Define the macro to perform port-specific functions when unloading the module. */ +/* Nothing needs to be done for this port. */ +#define TXM_MODULE_MANAGER_MODULE_UNLOAD(module_instance) + + +/* Define the macros to perform port-specific checks when passing pointers to the kernel. */ + +/* Define macro to make sure object is inside the module's data. */ +#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ + /* Check if it's inside module data. */ \ + ((((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && \ + (((obj_ptr) + (obj_size)) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) || \ + /* Check if it's inside shared memory. */ \ + (((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address) && \ + (((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (module_instance -> txm_module_instance_shared_memory_address + module_instance -> txm_module_instance_shared_memory_length)))) + + +/* Define some internal prototypes to this module port. */ + +#ifndef TX_SOURCE_CODE +#define txm_module_manager_memory_fault_notify _txm_module_manager_memory_fault_notify +#endif + + +#define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES \ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment); \ +VOID _txm_module_manager_memory_fault_handler(VOID); \ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)); \ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \ +ULONG _txm_power_of_two_block_size(ULONG size); \ +ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); \ +ULONG _txm_module_manager_region_size_get(ULONG block_size); + +#define TXM_MODULE_MANAGER_VERSION_ID \ +CHAR _txm_module_manager_version_id[] = \ + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3/MPU/AC5 Version 6.1 *"; + +#endif diff --git a/ports_module/cortex-m3/ac5/module_lib/src/txm_module_initialize.S b/ports_module/cortex-m3/ac5/module_lib/src/txm_module_initialize.S new file mode 100644 index 00000000..80137e06 --- /dev/null +++ b/ports_module/cortex-m3/ac5/module_lib/src/txm_module_initialize.S @@ -0,0 +1,112 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Module */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + IMPORT __use_two_region_memory + IMPORT __scatterload + IMPORT txm_heap + + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _txm_module_initialize Cortex-M3/MPU/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function initializes the module c runtime. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* __scatterload Initialize C runtime */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _txm_module_thread_shell_entry Start module thread */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _txm_module_initialize(VOID) + + EXPORT _txm_module_initialize +_txm_module_initialize + PUSH {r4-r12,lr} ; Save dregs and LR + + B __scatterload ; Call ARM func to initialize variables + +; +;/* Override __rt_exit function. */ +; + EXPORT __rt_exit +__rt_exit + + POP {r4-r12,lr} ; Restore dregs and LR + BX lr ; Return to caller +; +; +; + EXPORT __user_setup_stackheap + ; returns heap start address in R0 + ; returns heap end address in R2 + ; does not touch SP, it is already set up before the module runs + +__user_setup_stackheap + LDR r1, _tx_heap_offset ; load heap offset + ADD r0, r9, r1 ; calculate heap base address + MOV r2, #TXM_MODULE_HEAP_SIZE ; load heap size + ADD r2, r2, r0 ; calculate heap end address + BX lr + + ALIGN 4 +_tx_heap_offset + DCDO txm_heap + AREA ||.arm_vfe_header||, DATA, READONLY, NOALLOC, ALIGN=2 + + IMPORT txm_heap [DATA] + +; +; Dummy main function +; + AREA section_main, CODE, READONLY, ALIGN=2 + EXPORT main +main + BX lr + + END diff --git a/ports_module/cortex-m3/ac5/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex-m3/ac5/module_lib/src/txm_module_thread_shell_entry.c new file mode 100644 index 00000000..fdd17ff4 --- /dev/null +++ b/ports_module/cortex-m3/ac5/module_lib/src/txm_module_thread_shell_entry.c @@ -0,0 +1,173 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#ifndef TXM_MODULE +#define TXM_MODULE +#endif + +#ifndef TX_SOURCE_CODE +#define TX_SOURCE_CODE +#endif + + +/* Include necessary system files. */ + +#include "txm_module.h" +#include "tx_thread.h" + +/* Define the global module entry pointer from the start thread of the module. */ + +TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; + + +/* Define the dispatch function pointer used in the module implementation. */ + +ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3); + + +/* Define the ARM cstartup code. */ +extern VOID _txm_module_initialize(VOID); + +__align(8) UCHAR txm_heap[TXM_MODULE_HEAP_SIZE]; + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_thread_shell_entry Cortex-M3/MPU/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calls the specified entry function of the thread. It */ +/* also provides a place for the thread's entry function to return. */ +/* If the thread returns, this function places the thread in a */ +/* "COMPLETED" state. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to current thread */ +/* thread_info Pointer to thread entry info */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_initialize cstartup initialization */ +/* thread_entry Thread's entry function */ +/* tx_thread_resume Resume the module callback thread */ +/* _txm_module_thread_system_suspend Module thread suspension routine */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) +{ + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + VOID (*entry_exit_notify)(TX_THREAD *, UINT); +#endif + + + /* Determine if this is the start thread. If so, we must prepare the module for + execution. If not, simply skip the C startup code. */ + if (thread_info -> txm_module_thread_entry_info_start_thread) + { + /* Initialize the ARM C environment. */ + _txm_module_initialize(); + + /* Save the entry info pointer, for later use. */ + _txm_module_entry_info = thread_info; + + /* Save the kernel function dispatch address. This is used to make all resident calls from + the module. */ + _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; + + /* Ensure that we have a valid pointer. */ + while (!_txm_module_kernel_call_dispatcher) + { + /* Loop here, if an error is present getting the dispatch function pointer! + An error here typically indicates the resident portion of _tx_thread_schedule + is not supporting the trap to obtain the function pointer. */ + } + + /* Resume the module's callback thread, already created in the manager. */ + _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); + } + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has been entered! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_ENTRY); + } +#endif + + /* Call current thread's entry function. */ + (thread_info -> txm_module_thread_entry_info_entry) (thread_info -> txm_module_thread_entry_info_parameter); + + /* Suspend thread with a "completed" state. */ + + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine again. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has exited! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_EXIT); + } +#endif + + /* Call actual thread suspension routine. */ + _txm_module_thread_system_suspend(thread_ptr); + +#ifdef TX_SAFETY_CRITICAL + + /* If we ever get here, raise safety critical exception. */ + TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0); +#endif +} + diff --git a/ports_module/cortex-m3/ac5/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex-m3/ac5/module_manager/src/tx_thread_context_restore.S new file mode 100644 index 00000000..14b1da0e --- /dev/null +++ b/ports_module/cortex-m3/ac5/module_manager/src/tx_thread_context_restore.S @@ -0,0 +1,91 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_exit + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-M3/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + EXPORT _tx_thread_context_restore +_tx_thread_context_restore + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + PUSH {r0,lr} ; Save ISR lr + BL _tx_execution_isr_exit ; Call the ISR exit function + POP {r0,lr} ; Restore ISR lr + ENDIF +; + POP {lr} + BX lr +;} + ALIGN + LTORG + END diff --git a/ports_module/cortex-m3/ac5/module_manager/src/tx_thread_context_save.S b/ports_module/cortex-m3/ac5/module_manager/src/tx_thread_context_save.S new file mode 100644 index 00000000..ae21c768 --- /dev/null +++ b/ports_module/cortex-m3/ac5/module_manager/src/tx_thread_context_save.S @@ -0,0 +1,91 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_enter + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-M3/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + EXPORT _tx_thread_context_save +_tx_thread_context_save + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {r0, lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {r0, lr} ; Recover ISR lr + ENDIF +; +; /* Return to interrupt processing. */ +; + BX lr ; Return to interrupt processing caller +;} + ALIGN + LTORG + END diff --git a/ports_module/cortex-m3/ac5/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex-m3/ac5/module_manager/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..3c0f1768 --- /dev/null +++ b/ports_module/cortex-m3/ac5/module_manager/src/tx_thread_interrupt_control.S @@ -0,0 +1,76 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-M3/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + EXPORT _tx_thread_interrupt_control +_tx_thread_interrupt_control +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r1, PRIMASK + MSR PRIMASK, r0 + MOV r0, r1 + BX lr +; +;} + END diff --git a/ports_module/cortex-m3/ac5/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex-m3/ac5/module_manager/src/tx_thread_interrupt_disable.S new file mode 100644 index 00000000..d66a11f0 --- /dev/null +++ b/ports_module/cortex-m3/ac5/module_manager/src/tx_thread_interrupt_disable.S @@ -0,0 +1,75 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-M3/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts and returning */ +;/* the previous interrupt lockout posture. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_disable(UINT new_posture) +;{ + EXPORT _tx_thread_interrupt_disable +_tx_thread_interrupt_disable +; +; /* Return current interrupt lockout posture. */ +; + MRS r0, PRIMASK + CPSID i + BX lr +; +;} + END diff --git a/ports_module/cortex-m3/ac5/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex-m3/ac5/module_manager/src/tx_thread_interrupt_restore.S new file mode 100644 index 00000000..df65a539 --- /dev/null +++ b/ports_module/cortex-m3/ac5/module_manager/src/tx_thread_interrupt_restore.S @@ -0,0 +1,74 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-M3/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for restoring the previous */ +;/* interrupt lockout posture. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* previous_posture Previous interrupt posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_interrupt_restore(UINT new_posture) +;{ + EXPORT _tx_thread_interrupt_restore +_tx_thread_interrupt_restore +; +; /* Restore previous interrupt lockout posture. */ +; + MSR PRIMASK, r0 + BX lr +; +;} + END diff --git a/ports_module/cortex-m3/ac5/module_manager/src/tx_thread_schedule.S b/ports_module/cortex-m3/ac5/module_manager/src/tx_thread_schedule.S new file mode 100644 index 00000000..4194d69c --- /dev/null +++ b/ports_module/cortex-m3/ac5/module_manager/src/tx_thread_schedule.S @@ -0,0 +1,519 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_execute_ptr + IMPORT _tx_timer_time_slice + IMPORT _tx_thread_system_stack_ptr + IF :DEF: TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_thread_enter + IMPORT _tx_execution_thread_exit + ENDIF + IMPORT _tx_thread_preempt_disable + IMPORT _txm_module_manager_memory_fault_handler + IMPORT _txm_module_manager_memory_fault_info + IMPORT _txm_module_priv + IMPORT _txm_module_user_mode_exit +; +; + AREA ||.text||, CODE, READONLY + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-M3/MPU/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + EXPORT _tx_thread_schedule +_tx_thread_schedule +; +; /* This function should only ever be called on Cortex-M +; from the first schedule request. Subsequent scheduling occurs +; from the PendSV handling routines below. */ +; +; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ +; + MOV r0, #0 ; Build value for TX_FALSE + LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag + STR r0, [r2, #0] ; Clear preempt disable flag +; +; /* Clear CONTROL.FPCA bit so FPU registers aren't unnecessarily stacked. */ +; + IF :DEF: __ARMVFP__ + MRS r0, CONTROL ; Pickup current CONTROL register + BIC r0, r0, #4 ; Clear the FPCA bit + MSR CONTROL, r0 ; Setup new CONTROL register + ENDIF +; +; /* Enable memory fault registers. */ +; + LDR r0, =0xE000ED24 ; Build SHCSR address + LDR r1, =0x70000 ; Enable Usage, Bus, and MemManage faults + STR r1, [r0] ; +; +; /* Enable interrupts */ +; + CPSIE i +; +; /* Enter the scheduler for the first time. */ +; + MOV r0, #0x10000000 ; Load PENDSVSET bit + MOV r1, #0xE000E000 ; Load NVIC base + STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR + DSB ; Complete all memory accesses + ISB ; Flush pipeline + +; /* Wait here for the PendSV to take place. */ + +__tx_wait_here + B __tx_wait_here ; Wait for the PendSV to happen +;} +; + +; +; /* Memory Exception Handler. */ +; + EXPORT MemManage_Handler +MemManage_Handler +;{ + CPSID i ; Disable interrupts +; +; /* Now pickup and store all the fault related information. */ +; + LDR r12,=_txm_module_manager_memory_fault_info ; Pickup fault info struct + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup the current thread pointer + STR r1, [r12, #0] ; Save current thread pointer in fault info structure + LDR r0, =0xE000ED24 ; Build SHCSR address + LDR r1, [r0] ; Pickup SHCSR + STR r1, [r12, #8] ; Save SHCSR + LDR r0, =0xE000ED28 ; Build CFSR address + LDR r1, [r0] ; Pickup CFSR + STR r1, [r12, #12] ; Save CFSR + LDR r0, =0xE000ED34 ; Build MMFAR address + LDR r1, [r0] ; Pickup MMFAR + STR r1, [r12, #16] ; Save MMFAR + LDR r0, =0xE000ED38 ; Build BFAR address + LDR r1, [r0] ; Pickup BFAR + STR r1, [r12, #20] ; Save BFAR + MRS r0, CONTROL ; Pickup current CONTROL register + STR r0, [r12, #24] ; Save CONTROL + MRS r1, PSP ; Pickup thread stack pointer + STR r1, [r12, #28] ; Save thread stack pointer + LDR r0, [r1] ; Pickup saved r0 + STR r0, [r12, #32] ; Save r0 + LDR r0, [r1, #4] ; Pickup saved r1 + STR r0, [r12, #36] ; Save r1 + STR r2, [r12, #40] ; Save r2 + STR r3, [r12, #44] ; Save r3 + STR r4, [r12, #48] ; Save r4 + STR r5, [r12, #52] ; Save r5 + STR r6, [r12, #56] ; Save r6 + STR r7, [r12, #60] ; Save r7 + STR r8, [r12, #64] ; Save r8 + STR r9, [r12, #68] ; Save r9 + STR r10,[r12, #72] ; Save r10 + STR r11,[r12, #76] ; Save r11 + LDR r0, [r1, #16] ; Pickup saved r12 + STR r0, [r12, #80] ; Save r12 + LDR r0, [r1, #20] ; Pickup saved lr + STR r0, [r12, #84] ; Save lr + LDR r0, [r1, #24] ; Pickup instruction address at point of fault + STR r0, [r12, #4] ; Save point of fault + LDR r0, [r1, #28] ; Pickup xPSR + STR r0, [r12, #88] ; Save xPSR + + MRS r0, CONTROL ; Pickup current CONTROL register + BIC r0, r0, #1 ; Clear the UNPRIV bit + MSR CONTROL, r0 ; Setup new CONTROL register + + LDR r0, =0xE000ED28 ; Build the Memory Management Fault Status Register (MMFSR) + LDRB r1, [r0] ; Pickup the MMFSR, with the following bit definitions: + ; Bit 0 = 1 -> Instruction address violation + ; Bit 1 = 1 -> Load/store address violation + ; Bit 7 = 1 -> MMFAR is valid + STRB r1, [r0] ; Clear the MMFSR + + IF :DEF: __ARMVFP__ + LDR r0, =0xE000EF34 ; Cleanup FPU context: Load FPCCR address + LDR r1, [r0] ; Load FPCCR + BIC r1, r1, #1 ; Clear the lazy preservation active bit + STR r1, [r0] ; Store the value + ENDIF + + BL _txm_module_manager_memory_fault_handler ; Call memory manager fault handler + + IF :DEF: TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + CPSID i ; Disable interrupts + BL _tx_execution_thread_exit ; Call the thread exit function + CPSIE i ; Enable interrupts + ENDIF + + MOV r1, #0 ; Build NULL value + LDR r0, =_tx_thread_current_ptr ; Pickup address of current thread pointer + STR r1, [r0] ; Clear current thread pointer + + ; Return from MemManage_Handler exception + LDR r0, =0xE000ED04 ; Load ICSR + LDR r1, =0x10000000 ; Set PENDSVSET bit + STR r1, [r0] ; Store ICSR + DSB ; Wait for memory access to complete + CPSIE i ; Enable interrupts + MOV lr, #0xFFFFFFFD ; Load exception return code + BX lr ; Return from exception +;} + +; +; /* Generic context PendSV handler. */ +; + EXPORT PendSV_Handler + EXPORT __tx_PendSVHandler +PendSV_Handler +__tx_PendSVHandler +; +; /* Get current thread value and new thread pointer. */ +; +__tx_ts_handler + + IF :DEF: TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + CPSID i ; Disable interrupts + PUSH {r0, lr} ; Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit ; Call the thread exit function + POP {r0, lr} ; Recover LR + CPSIE i ; Enable interrupts + ENDIF + MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address + MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address + MOV r3, #0 ; Build NULL value + LDR r1, [r0] ; Pickup current thread pointer +; +; /* Determine if there is a current thread to finish preserving. */ +; + CBZ r1, __tx_ts_new ; If NULL, skip preservation +; +; /* Recover PSP and preserve current thread context. */ +; + STR r3, [r0] ; Set _tx_thread_current_ptr to NULL + MRS r12, PSP ; Pickup PSP pointer (thread's stack pointer) + STMDB r12!, {r4-r11} ; Save its remaining registers + IF :DEF: __ARMVFP__ + TST LR, #0x10 ; Determine if the VFP extended frame is present + BNE _skip_vfp_save + VSTMDB r12!,{s16-s31} ; Yes, save additional VFP registers +_skip_vfp_save + ENDIF + MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable + STMDB r12!, {LR} ; Save LR on the stack +; +; /* Determine if time-slice is active. If it isn't, skip time handling processing. */ +; + LDR r5, [r4] ; Pickup current time-slice + STR r12, [r1, #8] ; Save the thread stack pointer + CBZ r5, __tx_ts_new ; If not active, skip processing +; +; /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ +; + STR r5, [r1, #24] ; Save current time-slice +; +; /* Clear the global time-slice. */ +; + STR r3, [r4] ; Clear time-slice +; +; /* Executing thread is now completely preserved!!! */ +; +__tx_ts_new +; +; /* Now we are looking for a new thread to execute! */ +; + CPSID i ; Disable interrupts + LDR r1, [r2] ; Is there another thread ready to execute? + CBZ r1, __tx_ts_wait ; No, skip to the wait processing +; +; /* Yes, another thread is ready for else, make the current thread the new thread. */ +; + STR r1, [r0] ; Setup the current thread pointer to the new thread + CPSIE i ; Enable interrupts +; +; /* Increment the thread run count. */ +; +__tx_ts_restore + LDR r7, [r1, #4] ; Pickup the current thread run count + MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable + LDR r5, [r1, #24] ; Pickup thread's current time-slice + ADD r7, r7, #1 ; Increment the thread run count + STR r7, [r1, #4] ; Store the new run count +; +; /* Setup global time-slice with thread's current time-slice. */ +; + STR r5, [r4] ; Setup global time-slice + + IF :DEF: TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + PUSH {r0, r1} ; Save r0 and r1 + BL _tx_execution_thread_enter ; Call the thread execution enter function + POP {r0, r1} ; Recover r0 and r1 + ENDIF +; +; /* Restore the thread context and PSP. */ +; + LDR r12, [r1, #8] ; Pickup thread's stack pointer + + MRS r5, CONTROL ; Pickup current CONTROL register + LDR r4, [r1, #0x98] ; Pickup current user mode flag + BIC r5, r5, #1 ; Clear the UNPRIV bit + ORR r4, r4, r5 ; Build new CONTROL register + MSR CONTROL, r4 ; Setup new CONTROL register + + LDR r0, =0xE000ED94 ; Build MPU control reg address + MOV r3, #0 ; Build disable value + STR r3, [r0] ; Disable MPU + LDR r0, [r1, #0x90] ; Pickup the module instance pointer + CBZ r0, skip_mpu_setup ; Is this thread owned by a module? No, skip MPU setup + LDR r1, [r0, #0x64] ; Pickup MPU register[0] + CBZ r1, skip_mpu_setup ; Is protection required for this module? No, skip MPU setup + LDR r1, =0xE000ED9C ; Build address of MPU base register + + ; Use alias registers to quickly load MPU + ADD r0, r0, #100 ; Build address of MPU register start in thread control block + LDM r0!,{r2-r9} ; Load MPU regions 0-3 + STM r1,{r2-r9} ; Store MPU regions 0-3 + LDM r0!,{r2-r9} ; Load MPU regions 4-7 + STM r1,{r2-r9} ; Store MPU regions 4-7 + LDR r0, =0xE000ED94 ; Build MPU control reg address + MOV r1, #5 ; Build enable value with background region enabled + STR r1, [r0] ; Enable MPU +skip_mpu_setup + LDMIA r12!, {LR} ; Pickup LR + IF :DEF: __ARMVFP__ + TST LR, #0x10 ; Determine if the VFP extended frame is present + BNE _skip_vfp_restore ; If not, skip VFP restore + VLDMIA r12!, {s16-s31} ; Yes, restore additional VFP registers +_skip_vfp_restore + ENDIF + LDMIA r12!, {r4-r11} ; Recover thread's registers + MSR PSP, r12 ; Setup the thread's stack pointer +; +; /* Return to thread. */ +; + BX lr ; Return to thread! +; +; /* The following is the idle wait processing... in this case, no threads are ready for execution and the +; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +; are disabled to allow use of WFI for waiting for a thread to arrive. */ +; +__tx_ts_wait + CPSID i ; Disable interrupts + LDR r1, [r2] ; Pickup the next thread to execute pointer + STR r1, [r0] ; Store it in the current pointer + CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready! + IF :DEF:TX_ENABLE_WFI + DSB ; Ensure no outstanding memory transactions + WFI ; Wait for interrupt + ISB ; Ensure pipeline is flushed + ENDIF + CPSIE i ; Enable interrupts + B __tx_ts_wait ; Loop to continue waiting +; +; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +; already in the handler! */ +; +__tx_ts_ready + MOV r7, #0x08000000 ; Build clear PendSV value + MOV r8, #0xE000E000 ; Build base NVIC address + STR r7, [r8, #0xD04] ; Clear any PendSV +; +; /* Re-enable interrupts and restore new thread. */ +; + CPSIE i ; Enable interrupts + B __tx_ts_restore ; Restore the thread +;} + +; +; /* SVC Handler. */ +; + EXPORT SVC_Handler + EXPORT __tx_SVCallHandler +SVC_Handler +__tx_SVCallHandler +;{ + MRS r0, PSP ; Pickup the PSP stack + LDR r1, [r0, #24] ; Pickup the point of interrupt + LDRB r2, [r1, #-2] ; Pickup the SVC parameter + ; + ; Determine which SVC trap we are processing + ; + CMP r2, #1 ; Is it the entry into ThreadX? + BNE _tx_thread_user_return ; No, return to user mode + ; + ; At this point we have an SVC 1, which means we are entering the kernel from a module thread with user mode selected + ; + LDR r2, =_txm_module_priv ; Subtract 1 because of THUMB mode. + SUB r2, r2, #1 ; Temporary fix until ARM describes how to load label above correctly. + CMP r1, r2 ; Did we come from user_mode_entry? + IT NE ; If no (not equal), then... + BXNE lr ; return from where we came. + + LDR r3, [r0, #20] ; This is the saved LR + LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r2, [r1] ; Pickup current thread pointer + MOV r1, #0 ; Build clear value + STR r1, [r2, #0x98] ; Clear the current user mode selection for thread + STR r3, [r2, #0xA0] ; Save the original LR in thread control block + + ; If there is memory protection, use kernel stack + LDR r0, [r2, #0x90] ; Load the module instance ptr + LDR r0, [r0, #0x0C] ; Load the module property flags + TST r0, #2 ; Check if memory protected + BEQ _tx_skip_kernel_stack_enter + + ; Switch to the module thread's kernel stack + LDR r0, [r2, #0xA8] ; Load the module kernel stack end + IF :LNOT: :DEF: TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + LDR r1, [r2, #0xA4] ; Load the module kernel stack start + LDR r3, [r2, #0xAC] ; Load the module kernel stack size + STR r1, [r2, #12] ; Set stack start + STR r0, [r2, #16] ; Set stack end + STR r3, [r2, #20] ; Set stack size + ENDIF + + MRS r3, PSP ; Pickup thread stack pointer + STR r3, [r2, #0xB0] ; Save thread stack pointer + + ; Build kernel stack by copying thread stack two registers at a time + ADD r3, r3, #32 ; start at bottom of hardware stack + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + + MSR PSP, r0 ; Set kernel stack pointer + +_tx_skip_kernel_stack_enter + MRS r0, CONTROL ; Pickup current CONTROL register + BIC r0, r0, #1 ; Clear the UNPRIV bit + MSR CONTROL, r0 ; Setup new CONTROL register + BX lr ; Return to thread + +_tx_thread_user_return + LDR r2, =_txm_module_user_mode_exit ; Subtract 1 because of THUMB mode. + SUB r2, r2, #1 ; Temporary fix until ARM describes how to load label above correctly. + CMP r1, r2 ; Did we come from user_mode_exit? + IT NE ; If no (not equal), then... + BXNE lr ; return from where we came + + LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r2, [r1] ; Pickup current thread pointer + LDR r1, [r2, #0x9C] ; Pick up user mode + STR r1, [r2, #0x98] ; Set the current user mode selection for thread + + ; If there is memory protection, use kernel stack + LDR r0, [r2, #0x90] ; Load the module instance ptr + LDR r0, [r0, #0x0C] ; Load the module property flags + TST r0, #2 ; Check if memory protected + BEQ _tx_skip_kernel_stack_exit + + IF :LNOT: :DEF: TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + LDR r0, [r2, #0xB4] ; Load the module thread stack start + LDR r1, [r2, #0xB8] ; Load the module thread stack end + LDR r3, [r2, #0xBC] ; Load the module thread stack size + STR r0, [r2, #12] ; Set stack start + STR r1, [r2, #16] ; Set stack end + STR r3, [r2, #20] ; Set stack size + ENDIF + LDR r0, [r2, #0xB0] ; Load the module thread stack pointer + MRS r3, PSP ; Pickup kernel stack pointer + + ; Copy kernel hardware stack to module thread stack. + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + SUB r0, r0, #32 ; Subtract 32 to get back to top of stack + MSR PSP, r0 ; Set thread stack pointer + + LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r2, [r1] ; Pickup current thread pointer + LDR r1, [r2, #0x9C] ; Pick up user mode + +_tx_skip_kernel_stack_exit + MRS r0, CONTROL ; Pickup current CONTROL register + ORR r0, r0, r1 ; OR in the user mode bit + MSR CONTROL, r0 ; Setup new CONTROL register + BX lr ; Return to thread +;} + + ALIGN 4 + END diff --git a/ports_module/cortex-m3/ac5/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex-m3/ac5/module_manager/src/tx_thread_stack_build.S new file mode 100644 index 00000000..1382a9ba --- /dev/null +++ b/ports_module/cortex-m3/ac5/module_manager/src/tx_thread_stack_build.S @@ -0,0 +1,133 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-M3/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + EXPORT _tx_thread_stack_build +_tx_thread_stack_build +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-M3 should look like the following after it is built: +; +; Stack Top: +; LR Interrupted LR (LR at time of PENDSV) +; r4 Initial value for r4 +; r5 Initial value for r5 +; r6 Initial value for r6 +; r7 Initial value for r7 +; r8 Initial value for r8 +; r9 Initial value for r9 +; r10 Initial value for r10 +; r11 Initial value for r11 +; r0 Initial value for r0 (Hardware stack starts here!!) +; r1 Initial value for r1 +; r2 Initial value for r2 +; r3 Initial value for r3 +; r12 Initial value for r12 +; lr Initial value for lr +; pc Initial value for pc +; xPSR Initial value for xPSR +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #0x7 ; Align frame for 8-byte alignment + SUB r2, r2, #68 ; Subtract frame size + LDR r3, =0xFFFFFFFD ; Build initial LR value + STR r3, [r2, #0] ; Save on the stack +; +; /* Actually build the stack frame. */ +; + MOV r3, #0 ; Build initial register value + STR r3, [r2, #4] ; Store initial r4 + STR r3, [r2, #8] ; Store initial r5 + STR r3, [r2, #12] ; Store initial r6 + STR r3, [r2, #16] ; Store initial r7 + STR r3, [r2, #20] ; Store initial r8 + STR r3, [r2, #24] ; Store initial r9 + STR r3, [r2, #28] ; Store initial r10 + STR r3, [r2, #32] ; Store initial r11 +; +; /* Hardware stack follows. */ +; + STR r3, [r2, #36] ; Store initial r0 + STR r3, [r2, #40] ; Store initial r1 + STR r3, [r2, #44] ; Store initial r2 + STR r3, [r2, #48] ; Store initial r3 + STR r3, [r2, #52] ; Store initial r12 + MOV r3, #0xFFFFFFFF ; Poison EXC_RETURN value + STR r3, [r2, #56] ; Store initial lr + STR r1, [r2, #60] ; Store initial pc + MOV r3, #0x01000000 ; Only T-bit need be set + STR r3, [r2, #64] ; Store initial xPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block + BX lr ; Return to caller +;} + END diff --git a/ports_module/cortex-m3/ac5/module_manager/src/tx_thread_system_return.S b/ports_module/cortex-m3/ac5/module_manager/src/tx_thread_system_return.S new file mode 100644 index 00000000..c15ef851 --- /dev/null +++ b/ports_module/cortex-m3/ac5/module_manager/src/tx_thread_system_return.S @@ -0,0 +1,85 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-M3/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + EXPORT _tx_thread_system_return +_tx_thread_system_return +; +; /* Return to real scheduler via PendSV. Note that this routine is often +; replaced with in-line assembly in tx_port.h to improved performance. */ +; + MOV r0, #0x10000000 ; Load PENDSVSET bit + MOV r1, #0xE000E000 ; Load NVIC base + STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR + MRS r0, IPSR ; Pickup IPSR + CMP r0, #0 ; Is it a thread returning? + BNE _isr_context ; If ISR, skip interrupt enable + MRS r1, PRIMASK ; Thread context returning, pickup PRIMASK + CPSIE i ; Enable interrupts + MSR PRIMASK, r1 ; Restore original interrupt posture +_isr_context + BX lr ; Return to caller +;} + END diff --git a/ports_module/cortex-m3/ac5/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex-m3/ac5/module_manager/src/tx_timer_interrupt.S new file mode 100644 index 00000000..e80da8e2 --- /dev/null +++ b/ports_module/cortex-m3/ac5/module_manager/src/tx_timer_interrupt.S @@ -0,0 +1,259 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + IMPORT _tx_timer_time_slice + IMPORT _tx_timer_system_clock + IMPORT _tx_timer_current_ptr + IMPORT _tx_timer_list_start + IMPORT _tx_timer_list_end + IMPORT _tx_timer_expired_time_slice + IMPORT _tx_timer_expired + IMPORT _tx_thread_time_slice + IMPORT _tx_timer_expiration_process + IMPORT _tx_thread_preempt_disable + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_execute_ptr +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-M3/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + EXPORT _tx_timer_interrupt +_tx_timer_interrupt +; +; /* Upon entry to this routine, it is assumed that context save has already +; been called, and therefore the compiler scratch registers are available +; for use. */ +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + MOV32 r1, _tx_timer_system_clock ; Pickup address of system clock + LDR r0, [r1, #0] ; Pickup system clock + ADD r0, r0, #1 ; Increment system clock + STR r0, [r1, #0] ; Store new system clock +; +; /* Test for time-slice expiration. */ +; if (_tx_timer_time_slice) +; { +; + MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice + LDR r2, [r3, #0] ; Pickup time-slice + CBZ r2, __tx_timer_no_time_slice ; Is it non-active? + ; Yes, skip time-slice processing +; +; /* Decrement the time_slice. */ +; _tx_timer_time_slice--; +; + SUB r2, r2, #1 ; Decrement the time-slice + STR r2, [r3, #0] ; Store new time-slice value +; +; /* Check for expiration. */ +; if (__tx_timer_time_slice == 0) +; + CBNZ r2, __tx_timer_no_time_slice ; Has it expired? +; +; /* Set the time-slice expired flag. */ +; _tx_timer_expired_time_slice = TX_TRUE; +; + MOV32 r3, _tx_timer_expired_time_slice ; Pickup address of expired flag + MOV r0, #1 ; Build expired value + STR r0, [r3, #0] ; Set time-slice expiration flag +; +; } +; +__tx_timer_no_time_slice +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + MOV32 r1, _tx_timer_current_ptr ; Pickup current timer pointer address + LDR r0, [r1, #0] ; Pickup current timer + LDR r2, [r0, #0] ; Pickup timer list entry + CBZ r2, __tx_timer_no_timer ; Is there anything in the list? + ; No, just increment the timer +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + MOV32 r3, _tx_timer_expired ; Pickup expiration flag address + MOV r2, #1 ; Build expired value + STR r2, [r3, #0] ; Set expired flag + B __tx_timer_done ; Finished timer processing +; +; } +; else +; { +__tx_timer_no_timer +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ADD r0, r0, #4 ; Move to next timer +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + MOV32 r3, _tx_timer_list_end ; Pickup addr of timer list end + LDR r2, [r3, #0] ; Pickup list end + CMP r0, r2 ; Are we at list end? + BNE __tx_timer_skip_wrap ; No, skip wrap-around logic +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + MOV32 r3, _tx_timer_list_start ; Pickup addr of timer list start + LDR r0, [r3, #0] ; Set current pointer to list start +; +__tx_timer_skip_wrap +; + STR r0, [r1, #0] ; Store new current timer pointer +; } +; +__tx_timer_done +; +; +; /* See if anything has expired. */ +; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +; { +; + MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of expired flag + LDR r2, [r3, #0] ; Pickup time-slice expired flag + CBNZ r2, __tx_something_expired ; Did a time-slice expire? + ; If non-zero, time-slice expired + MOV32 r1, _tx_timer_expired ; Pickup addr of other expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CBZ r0, __tx_timer_nothing_expired ; Did a timer expire? + ; No, nothing expired +; +__tx_something_expired +; +; + STMDB sp!, {r0, lr} ; Save the lr register on the stack + ; and save r0 just to keep 8-byte alignment +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + MOV32 r1, _tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CBZ r0, __tx_timer_dont_activate ; Check for timer expiration + ; If not set, skip timer activation +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + BL _tx_timer_expiration_process ; Call the timer expiration handling routine +; +; } +__tx_timer_dont_activate +; +; /* Did time slice expire? */ +; if (_tx_timer_expired_time_slice) +; { +; + MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r2, [r3, #0] ; Pickup the actual flag + CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set + ; No, skip time-slice processing +; +; /* Time slice interrupted thread. */ +; _tx_thread_time_slice(); + + BL _tx_thread_time_slice ; Call time-slice processing + MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag + LDR r1, [r0] ; Is the preempt disable flag set? + CBNZ r1, __tx_timer_skip_time_slice ; Yes, skip the PendSV logic + MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup the current thread pointer + MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address + LDR r3, [r2] ; Pickup the execute thread pointer + MOV32 r0, 0xE000ED04 ; Build address of control register + MOV32 r2, 0x10000000 ; Build value for PendSV bit + CMP r1, r3 ; Are they the same? + BEQ __tx_timer_skip_time_slice ; If the same, there was no time-slice performed + STR r2, [r0] ; Not the same, issue the PendSV for preemption +__tx_timer_skip_time_slice +; +; } +; +__tx_timer_not_ts_expiration +; + LDMIA sp!, {r0, lr} ; Recover lr register (r0 is just there for +; +; } +; +__tx_timer_nothing_expired + + DSB ; Complete all memory access + BX lr ; Return to caller +; +;} + ALIGN + LTORG + END diff --git a/ports_module/cortex-m3/ac5/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex-m3/ac5/module_manager/src/txm_module_manager_alignment_adjust.c new file mode 100644 index 00000000..dffb6197 --- /dev/null +++ b/ports_module/cortex-m3/ac5/module_manager/src/txm_module_manager_alignment_adjust.c @@ -0,0 +1,399 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_power_of_two_block_size Cortex-M3/MPU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calculates a power of two size at or immediately above*/ +/* the input size and returns it to the caller. */ +/* */ +/* INPUT */ +/* */ +/* size Block size */ +/* */ +/* OUTPUT */ +/* */ +/* calculated size Rounded up to power of two */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_power_of_two_block_size(ULONG size) +{ + /* Check for 0 size. */ + if(size == 0) + return 0; + + /* Minimum MPU block size is 32. */ + if(size <= 32) + return 32; + + /* Bit twiddling trick to round to next high power of 2 + (if original size is power of 2, it will return original size. Perfect!) */ + size--; + size |= size >> 1; + size |= size >> 2; + size |= size >> 4; + size |= size >> 8; + size |= size >> 16; + size++; + + /* Return a power of 2 size at or above the input size. */ + return(size); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_alignment_adjust Cortex-M3/MPU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function adjusts the alignment and size of the code and data */ +/* section for a given module implementation. */ +/* */ +/* INPUT */ +/* */ +/* module_preamble Pointer to module preamble */ +/* code_size Size of the code area (updated) */ +/* code_alignment Code area alignment (updated) */ +/* data_size Size of data area (updated) */ +/* data_alignment Data area alignment (updated) */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_power_of_two_block_size Calculate power of two size */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, + ULONG *code_size, + ULONG *code_alignment, + ULONG *data_size, + ULONG *data_alignment) +{ + +ULONG local_code_size; +ULONG local_code_alignment; +ULONG local_data_size; +ULONG local_data_alignment; +ULONG code_block_size; +ULONG data_block_size; +ULONG code_size_accum; +ULONG data_size_accum; + + /* Copy the input parameters into local variables for ease of use. */ + local_code_size = *code_size; + local_code_alignment = *code_alignment; + local_data_size = *data_size; + local_data_alignment = *data_alignment; + + + /* Test for external memory enabled in preamble. */ + if(module_preamble -> txm_module_preamble_property_flags & TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS) + { + /* External/shared memory enabled. TXM_MODULE_MANAGER_CODE_MPU_ENTRIES-1 code entries will be used. */ + if (local_code_size <= (32*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 32 is best. */ + code_block_size = 32; + } + else if (local_code_size <= (64*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 64 is best. */ + code_block_size = 64; + } + else if (local_code_size <= (128*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 128 is best. */ + code_block_size = 128; + } + else if (local_code_size <= (256*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 256 is best. */ + code_block_size = 256; + } + else if (local_code_size <= (512*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 512 is best. */ + code_block_size = 512; + } + else if (local_code_size <= (1024*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 1024 is best. */ + code_block_size = 1024; + } + else if (local_code_size <= (2048*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 2048 is best. */ + code_block_size = 2048; + } + else if (local_code_size <= (4096*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 4096 is best. */ + code_block_size = 4096; + } + else if (local_code_size <= (8192*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 8192 is best. */ + code_block_size = 8192; + } + else if (local_code_size <= (16384*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 16384 is best. */ + code_block_size = 16384; + } + else if (local_code_size <= (32768*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 32768 is best. */ + code_block_size = 32768; + } + else if (local_code_size <= (65536*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 65536 is best. */ + code_block_size = 65536; + } + else if (local_code_size <= (131072*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 131072 is best. */ + code_block_size = 131072; + } + else if (local_code_size <= (262144*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 262144 is best. */ + code_block_size = 262144; + } + else if (local_code_size <= (524288*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 524288 is best. */ + code_block_size = 524288; + } + else if (local_code_size <= (1048576*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 1048576 is best. */ + code_block_size = 1048576; + } + else if (local_code_size <= (2097152*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 2097152 is best. */ + code_block_size = 2097152; + } + else if (local_code_size <= (4194304*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 4194304 is best. */ + code_block_size = 4194304; + } + else + { + /* Just set block size to 32MB just to create an allocation error! */ + code_block_size = 33554432; + } + + /* Calculate the new code size. */ + local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); + + /* Determine if the code block size is greater than the current alignment. If so, use block size + as the alignment. */ + if (code_block_size > local_code_alignment) + local_code_alignment = code_block_size; + + } + else + { + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + local_code_alignment = _txm_power_of_two_block_size(local_code_size) >> 2; + code_size_accum = local_code_alignment + local_code_alignment; + code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); + code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); + local_code_size = code_size_accum; + } + + /* Determine the best data block size, which in our case is the minimal alignment. */ + if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 32 is best. */ + data_block_size = 32; + } + else if (local_data_size <= (64*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 64 is best. */ + data_block_size = 64; + } + else if (local_data_size <= (128*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 128 is best. */ + data_block_size = 128; + } + else if (local_data_size <= (256*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 256 is best. */ + data_block_size = 256; + } + else if (local_data_size <= (512*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 512 is best. */ + data_block_size = 512; + } + else if (local_data_size <= (1024*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 1024 is best. */ + data_block_size = 1024; + } + else if (local_data_size <= (2048*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 2048 is best. */ + data_block_size = 2048; + } + else if (local_data_size <= (4096*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 4096 is best. */ + data_block_size = 4096; + } + else if (local_data_size <= (8192*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 8192 is best. */ + data_block_size = 8192; + } + else if (local_data_size <= (16384*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 16384 is best. */ + data_block_size = 16384; + } + else if (local_data_size <= (32768*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 32768 is best. */ + data_block_size = 32768; + } + else if (local_data_size <= (65536*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 65536 is best. */ + data_block_size = 65536; + } + else if (local_data_size <= (131072*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 131072 is best. */ + data_block_size = 131072; + } + else if (local_data_size <= (262144*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 262144 is best. */ + data_block_size = 262144; + } + else if (local_data_size <= (524288*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 524288 is best. */ + data_block_size = 524288; + } + else if (local_data_size <= (1048576*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 1048576 is best. */ + data_block_size = 1048576; + } + else if (local_data_size <= (2097152*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 2097152 is best. */ + data_block_size = 2097152; + } + else if (local_data_size <= (4194304*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 4194304 is best. */ + data_block_size = 4194304; + } + else + { + /* Just set data block size to 32MB just to create an allocation error! */ + data_block_size = 33554432; + } + + /* Calculate the new data size. */ + data_size_accum = data_block_size; + while(data_size_accum < local_data_size) + { + data_size_accum += data_block_size; + } + local_data_size = data_size_accum; + + /* Determine if the data block size is greater than the current alignment. If so, use block size + as the alignment. */ + if (data_block_size > local_data_alignment) + { + local_data_alignment = data_block_size; + } + + /* Return all the information to the caller. */ + *code_size = local_code_size; + *code_alignment = local_code_alignment; + *data_size = local_data_size; + *data_alignment = local_data_alignment; +} diff --git a/ports_module/cortex-m3/ac5/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex-m3/ac5/module_manager/src/txm_module_manager_external_memory_enable.c new file mode 100644 index 00000000..7efbf2df --- /dev/null +++ b/ports_module/cortex-m3/ac5/module_manager/src/txm_module_manager_external_memory_enable.c @@ -0,0 +1,182 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_mutex.h" +#include "tx_queue.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_external_memory_enable Cortex-M3/MPU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates an entry in the MPU table for a shared */ +/* memory space. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* start_address Start address of memory */ +/* length Length of external memory */ +/* attributes Memory attributes (r/w) */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_mutex_get Get protection mutex */ +/* _tx_mutex_put Release protection mutex */ +/* _txm_power_of_two_block_size Round length to power of two */ +/* _txm_module_manager_mm_register_setup Reconfigure MPU registers */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, + VOID *start_address, + ULONG length, + UINT attributes) +{ + +ULONG block_size; +ULONG region_size; +ULONG subregion_bits; +ULONG address; +UINT attributes_check = 0; +TXM_MODULE_PREAMBLE *module_preamble; + + /* Determine if the module manager has not been initialized yet. */ + if (_txm_module_manager_ready != TX_TRUE) + { + /* Module manager has not been initialized. */ + return(TX_NOT_AVAILABLE); + } + + /* Determine if the module is valid. */ + if (module_instance == TX_NULL) + { + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Get module manager protection mutex. */ + _tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER); + + /* Determine if the module instance is valid. */ + if (module_instance -> txm_module_instance_id != TXM_MODULE_ID) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Determine if the module instance is in the loaded state. */ + if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if the module is not ready. */ + return(TX_START_ERROR); + } + + /* Check if preamble shared mem and mem protection property bits are set. */ + module_preamble = module_instance -> txm_module_instance_preamble_ptr; + if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) + != (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if bit not set. */ + return(TXM_MODULE_INVALID_PROPERTIES); + } + + /* Start address and length must adhere to Cortex-M MPU. + The address must align with the block size. */ + + block_size = _txm_power_of_two_block_size(length); + address = (ULONG) start_address; + if(address != (address & ~(block_size - 1))) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return alignment error. */ + return(TXM_MODULE_ALIGNMENT_ERROR); + } + + /* At this point, we have a valid address and block size. + Set up MPU registers. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | 0x10; + + /* Calculate the region size. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + /* Calculate the subregion bits. */ + subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); + + /* Check for valid attributes. */ + if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) + { + attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; + } + + /* Build register with attributes. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX+1] = region_size | subregion_bits | attributes_check | 0x12070001; + + /* Keep track of shared memory address and length in module instance. */ + module_instance -> txm_module_instance_shared_memory_address = address; + module_instance -> txm_module_instance_shared_memory_length = length; + + /* Recalculate MPU settings. */ + _txm_module_manager_mm_register_setup(module_instance); + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/ports_module/cortex-m3/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex-m3/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c new file mode 100644 index 00000000..c670a087 --- /dev/null +++ b/ports_module/cortex-m3/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -0,0 +1,110 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + +/* Define a macro that can be used to allocate global variables useful to + store information about the last fault. This macro is defined in + txm_module_port.h and is usually populated in the assembly language + fault handling prior to the code calling _txm_module_manager_memory_fault_handler. */ + +TXM_MODULE_MANAGER_FAULT_INFO + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_handler Cortex-M3/MPU/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles a fault associated with a memory protected */ +/* module. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_terminate Terminate thread */ +/* */ +/* CALLED BY */ +/* */ +/* Fault handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_memory_fault_handler(VOID) +{ + +TXM_MODULE_INSTANCE *module_instance_ptr; +TX_THREAD *thread_ptr; + + /* Pickup the current thread. */ + thread_ptr = _tx_thread_current_ptr; + + /* Initialize the module instance pointer to NULL. */ + module_instance_ptr = TX_NULL; + + /* Is there a thread? */ + if (thread_ptr) + { + /* Pickup the module instance. */ + module_instance_ptr = thread_ptr -> tx_thread_module_instance_ptr; + + /* Terminate the current thread. */ + _tx_thread_terminate(_tx_thread_current_ptr); + } + + /* Determine if there is a user memory fault notification callback. */ + if (_txm_module_manager_fault_notify) + { + /* Yes, call the user's notification memory fault callback. */ + (_txm_module_manager_fault_notify)(thread_ptr, module_instance_ptr); + } +} diff --git a/ports_module/cortex-m3/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex-m3/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c new file mode 100644 index 00000000..2b757ddd --- /dev/null +++ b/ports_module/cortex-m3/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -0,0 +1,84 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the external user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_notify Cortex-M3/MPU/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application callback when/if a memory */ +/* fault occurs. The supplied thread is automatically terminated, but */ +/* any other threads in the same module may still execute. */ +/* */ +/* INPUT */ +/* */ +/* notify_function Memory fault notification */ +/* function, NULL disables. */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +{ + /* Setup notification function. */ + _txm_module_manager_fault_notify = notify_function; + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/ports_module/cortex-m3/ac5/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex-m3/ac5/module_manager/src/txm_module_manager_mm_register_setup.c new file mode 100644 index 00000000..7d60aefc --- /dev/null +++ b/ports_module/cortex-m3/ac5/module_manager/src/txm_module_manager_mm_register_setup.c @@ -0,0 +1,512 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_region_size_get Cortex-M3/MPU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function converts the region size in bytes to the block size */ +/* for the Cortex-M3 MPU specification. */ +/* */ +/* INPUT */ +/* */ +/* block_size Size of the block in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* MPU size specification */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_module_manager_region_size_get(ULONG block_size) +{ + +ULONG return_value; + + /* Process relative to the input block size. */ + if (block_size == 32) + { + return_value = 0x04; + } + else if (block_size == 64) + { + return_value = 0x05; + } + else if (block_size == 128) + { + return_value = 0x06; + } + else if (block_size == 256) + { + return_value = 0x07; + } + else if (block_size == 512) + { + return_value = 0x08; + } + else if (block_size == 1024) + { + return_value = 0x09; + } + else if (block_size == 2048) + { + return_value = 0x0A; + } + else if (block_size == 4096) + { + return_value = 0x0B; + } + else if (block_size == 8192) + { + return_value = 0x0C; + } + else if (block_size == 16384) + { + return_value = 0x0D; + } + else if (block_size == 32768) + { + return_value = 0x0E; + } + else if (block_size == 65536) + { + return_value = 0x0F; + } + else if (block_size == 131072) + { + return_value = 0x10; + } + else if (block_size == 262144) + { + return_value = 0x11; + } + else if (block_size == 524288) + { + return_value = 0x12; + } + else if (block_size == 1048576) + { + return_value = 0x13; + } + else if (block_size == 2097152) + { + return_value = 0x14; + } + else + { + /* Max 4MB MPU pages for modules. */ + return_value = 0x15; + } + + return(return_value); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_calculate_srd_bits Cortex-M3/MPU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calculates the SRD bits that need to be set to */ +/* protect "length" bytes in a block. */ +/* */ +/* INPUT */ +/* */ +/* block_size Size of the block in bytes */ +/* length Actual length in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* SRD bits to be OR'ed with region attribute register. */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) +{ + +ULONG srd_bits = 0; +UINT srd_bit_index; + + /* length is smaller than block_size, set SRD bits if block_size is 256 or more. */ + if((block_size >= 256) && (length < block_size)) + { + /* Divide block_size by 8 by shifting right 3. Result is size of subregion. */ + block_size = block_size >> 3; + + /* Set SRD index into attribute register. */ + srd_bit_index = 8; + + /* If subregion overlaps length, move to the next subregion. */ + while(length > block_size) + { + length = length - block_size; + srd_bit_index++; + } + /* Check for a portion of code remaining. */ + if(length) + { + srd_bit_index++; + } + + /* Set unused subregion bits. */ + while(srd_bit_index < 16) + { + srd_bits = srd_bits | (0x1 << srd_bit_index); + srd_bit_index++; + } + } + + return(srd_bits); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_mm_register_setup Cortex-M3/MPU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets up the Cortex-M3 MPU register definitions based */ +/* on the module's memory characteristics. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* */ +/* OUTPUT */ +/* */ +/* MPU specifications for module in module_instance */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_manager_region_size_get */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_thread_create */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) +{ + +ULONG code_address; +ULONG code_size; +ULONG data_address; +ULONG data_size; +ULONG start_stop_stack_size; +ULONG callback_stack_size; +ULONG block_size; +ULONG base_address_register; +ULONG base_attribute_register; +ULONG region_size; +ULONG srd_bits = 0; +UINT mpu_register = 0; +UINT mpu_table_index; +UINT i; + + + /* Setup the first region for the ThreadX trampoline code. */ + /* Set base register to user mode entry, which is guaranteed to be at least 32-byte aligned. */ + base_address_register = (ULONG) _txm_module_manager_user_mode_entry; + + /* Mask address to proper range, region 0, set Valid bit. */ + base_address_register = (base_address_register & 0xFFFFFFE0) | mpu_register | 0x10; + module_instance -> txm_module_instance_mpu_registers[0] = base_address_register; + + /* Attributes: read only, write-back, shareable, size 32 bytes, region enabled. */ + module_instance -> txm_module_instance_mpu_registers[1] = 0x06070009; + + /* Initialize the MPU register. */ + mpu_register = 1; + + /* Initialize the MPU table index. */ + mpu_table_index = 2; + + /* Setup values for code area. */ + code_address = (ULONG) module_instance -> txm_module_instance_code_start; + code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; + + /* Check if shared memory was set up. If so, only 3 entries are available for + code protection. If not set up, 4 code entries are available. */ + if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] == 0) + { + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + + /* Now loop through to setup MPU protection for the code area. */ + for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES; i++) + { + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + if (i < 2) + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + } + + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ + else if (i == 2) + { + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size) >> 1; + } + + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + else + { + /* Calculate remaining space. */ + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + + /* Build the base address register. */ + base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Build the base attribute register. */ + base_attribute_register = region_size | srd_bits | 0x06070001; + + /* Setup the MPU Base Address Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; + + /* Setup the MPU Base Attribute Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; + + /* Adjust the code address. */ + code_address = code_address + block_size; + + /* Move MPU table index. */ + mpu_table_index = mpu_table_index + 2; + + /* Increment the MPU register index. */ + mpu_register++; + } + } + + /* Only 3 code entries available. */ + else + { + /* Calculate block size, one code entry taken up by shared memory. */ + block_size = _txm_power_of_two_block_size(code_size / (TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)); + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Now loop through to setup MPU protection for the code area. */ + for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) + { + /* Build the base address register. */ + base_address_register = code_address & ~(block_size - 1) | mpu_register | 0x10; + + /* Check if SRD bits need to be set. */ + if (code_size < block_size) + { + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + + /* Build the base attribute register. */ + base_attribute_register = region_size | srd_bits | 0x06070000; + + /* Is there still some code? If so set the region enable bit. */ + if (code_size) + { + /* Set the region enable bit. */ + base_attribute_register = base_attribute_register | 0x1; + } + /* Setup the MPU Base Address Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; + + /* Setup the MPU Base Attribute Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; + + /* Adjust the code address. */ + code_address = code_address + block_size; + + /* Decrement the code size. */ + if (code_size > block_size) + { + code_size = code_size - block_size; + } + else + { + code_size = 0; + } + + /* Move MPU table index. */ + mpu_table_index = mpu_table_index + 2; + + /* Increment the MPU register index. */ + mpu_register++; + } + + /* Adjust indeces to pass over the shared memory entry. */ + /* Move MPU table index. */ + mpu_table_index = mpu_table_index + 2; + + /* Increment the MPU register index. */ + mpu_register++; + } + + /* Setup values for data area. */ + data_address = (ULONG) module_instance -> txm_module_instance_data_start; + + /* Adjust the size of the module elements to be aligned to the default alignment. We do this + so that when we partition the allocated memory, we can simply place these regions right beside + each other without having to align their pointers. Note this only works when they all have + the same alignment. */ + + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; + start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; + callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; + + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + /* Update the data size to include thread stacks. */ + data_size = data_size + start_stop_stack_size + callback_stack_size; + + block_size = _txm_power_of_two_block_size(data_size / TXM_MODULE_MANAGER_DATA_MPU_ENTRIES); + + /* Reset SRD bitfield. */ + srd_bits = 0; + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Now loop through to setup MPU protection for the data area. */ + for (i = 0; i < TXM_MODULE_MANAGER_DATA_MPU_ENTRIES; i++) + { + /* Build the base address register. */ + base_address_register = (data_address & ~(block_size - 1)) | mpu_register | 0x10; + + /* Check if SRD bits need to be set. */ + if (data_size < block_size) + { + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + } + + /* Build the base attribute register. */ + base_attribute_register = region_size | srd_bits | 0x13070000; + + /* Is there still some data? If so set the region enable bit. */ + if (data_size) + { + /* Set the region enable bit. */ + base_attribute_register = base_attribute_register | 0x1; + } + + /* Setup the MPU Base Address Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; + + /* Setup the MPU Base Attribute Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; + + /* Adjust the data address. */ + data_address = data_address + block_size; + + /* Decrement the data size. */ + if (data_size > block_size) + { + data_size = data_size - block_size; + } + else + { + data_size = 0; + } + + /* Move MPU table index. */ + mpu_table_index = mpu_table_index + 2; + + /* Increment the MPU register index. */ + mpu_register++; + } +} diff --git a/ports_module/cortex-m3/ac5/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex-m3/ac5/module_manager/src/txm_module_manager_thread_stack_build.S new file mode 100644 index 00000000..aaefebd7 --- /dev/null +++ b/ports_module/cortex-m3/ac5/module_manager/src/txm_module_manager_thread_stack_build.S @@ -0,0 +1,141 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Module Manager */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + AREA ||.text||, CODE, READONLY + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _txm_module_manager_thread_stack_build Cortex-M3/MPU/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread */ +;/* function_ptr Pointer to shell function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +;{ + EXPORT _txm_module_manager_thread_stack_build +_txm_module_manager_thread_stack_build +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-M should look like the following after it is built: +; +; Stack Top: +; LR Interrupted LR (LR at time of PENDSV) +; r4 Initial value for r4 +; r5 Initial value for r5 +; r6 Initial value for r6 +; r7 Initial value for r7 +; r8 Initial value for r8 +; r9 Initial value for r9 +; r10 Initial value for r10 +; r11 Initial value for r11 +; r0 Initial value for r0 (Hardware stack starts here!!) +; r1 Initial value for r1 +; r2 Initial value for r2 +; r3 Initial value for r3 +; r12 Initial value for r12 +; lr Initial value for lr +; pc Initial value for pc +; xPSR Initial value for xPSR +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #0x7 ; Align frame + SUB r2, r2, #68 ; Subtract frame size + LDR r3, =0xFFFFFFFD ; Build initial LR value + STR r3, [r2, #0] ; Save on the stack +; +; /* Actually build the stack frame. */ +; + MOV r3, #0 ; Build initial register value + STR r3, [r2, #4] ; Store initial r4 + STR r3, [r2, #8] ; Store initial r5 + STR r3, [r2, #12] ; Store initial r6 + STR r3, [r2, #16] ; Store initial r7 + STR r3, [r2, #20] ; Store initial r8 + STR r3, [r2, #28] ; Store initial r10 + STR r3, [r2, #32] ; Store initial r11 +; +; /* Hardware stack follows. */ +; + STR r0, [r2, #36] ; Store initial r0, which is the thread control block + + LDR r3, [r0, #8] ; Pickup thread entry info pointer,which is in the stack pointer position of the thread control block. + ; It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this + ; function with the actual, initial stack pointer. + STR r3, [r2, #40] ; Store initial r1, which is the module entry information. + LDR r3, [r3, #8] ; Pickup data base register from the module information + STR r3, [r2, #24] ; Store initial r9 (data base register) + MOV r3, #0 ; Clear r3 again + + STR r3, [r2, #44] ; Store initial r2 + STR r3, [r2, #48] ; Store initial r3 + STR r3, [r2, #52] ; Store initial r12 + MOV r3, #0xFFFFFFFF ; Poison EXC_RETURN value + STR r3, [r2, #56] ; Store initial lr + STR r1, [r2, #60] ; Store initial pc + MOV r3, #0x01000000 ; Only T-bit need be set + STR r3, [r2, #64] ; Store initial xPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's control block + BX lr ; Return to caller +;} + END + diff --git a/ports_module/cortex-m3/ac5/module_manager/src/txm_module_manager_user_mode_entry.S b/ports_module/cortex-m3/ac5/module_manager/src/txm_module_manager_user_mode_entry.S new file mode 100644 index 00000000..83c9bd4c --- /dev/null +++ b/ports_module/cortex-m3/ac5/module_manager/src/txm_module_manager_user_mode_entry.S @@ -0,0 +1,88 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Module Manager */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; + IMPORT _txm_module_manager_kernel_dispatch + IMPORT _tx_thread_current_ptr +; + AREA ||.text||, CODE, READONLY, ALIGN=5 + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _txm_module_manager_user_mode_entry Cortex-M3/MPU/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function allows modules to enter kernel mode. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* SVC 1 Enter kernel mode */ +;/* SVC 2 Exit kernel mode */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Modules in user mode */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/; +;VOID _txm_module_manager_user_mode_entry(VOID) +;{ + EXPORT _txm_module_manager_user_mode_entry +_txm_module_manager_user_mode_entry + SVC 1 ; Enter kernel + EXPORT _txm_module_priv +_txm_module_priv + ; At this point, we are out of user mode. The original LR has been saved in the + ; thread control block. Simply call the kernel dispatch function. + BL _txm_module_manager_kernel_dispatch + + ; Pickup the original LR value while still in privileged mode + LDR r2, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r3, [r2] ; Pickup current thread pointer + LDR lr, [r3, #0xA0] ; Pickup saved LR from original call + + SVC 2 ; Exit kernel and return to user mode + EXPORT _txm_module_user_mode_exit +_txm_module_user_mode_exit + BX lr ; Return to the caller +;} + ALIGN 32 + END diff --git a/ports_module/cortex-m3/ac6/example_build/all.bat b/ports_module/cortex-m3/ac6/example_build/all.bat new file mode 100644 index 00000000..748e5743 --- /dev/null +++ b/ports_module/cortex-m3/ac6/example_build/all.bat @@ -0,0 +1,5 @@ +@ECHO OFF +CALL clean.bat +CALL setenv.bat +CALL initws.bat +CALL build.bat diff --git a/ports_module/cortex-m3/ac6/example_build/build.bat b/ports_module/cortex-m3/ac6/example_build/build.bat new file mode 100644 index 00000000..6ebdf460 --- /dev/null +++ b/ports_module/cortex-m3/ac6/example_build/build.bat @@ -0,0 +1,24 @@ +@ECHO OFF + +ECHO Build starting... + +SETLOCAL ENABLEEXTENSIONS + +IF DEFINED ARMDSIDEC GOTO IARBUILD_DEFINED +ECHO ERROR: please set ARMDSIDEC to the path of the ARM Developer Studio eclipsec.exe program +EXIT /B 2 +:IARBUILD_DEFINED + +IF EXIST %ARMDSIDEC% GOTO ARMDSIDEC_FOUND +ECHO ERROR: the command ARMDSIDEC doesn't exist: %ARMDSIDEC% +EXIT /B 2 +:ARMDSIDEC_FOUND + +%ARMDSIDEC% -nosplash -application org.eclipse.cdt.managedbuilder.core.headlessbuild -data .\workspace -build all +IF %ERRORLEVEL% EQU 0 GOTO BUILD_OK +ECHO ERROR: build failed. +EXIT /B 1 +:BUILD_OK + +ECHO Build completed without errors. +EXIT /B 0 diff --git a/ports_module/cortex-m3/ac6/example_build/clean.bat b/ports_module/cortex-m3/ac6/example_build/clean.bat new file mode 100644 index 00000000..8a48e5c9 --- /dev/null +++ b/ports_module/cortex-m3/ac6/example_build/clean.bat @@ -0,0 +1,4 @@ +@ECHO OFF +ECHO Cleaning... +RMDIR /Q /S workspace +ECHO Done. diff --git a/ports_module/cortex-m3/ac6/example_build/initws.bat b/ports_module/cortex-m3/ac6/example_build/initws.bat new file mode 100644 index 00000000..62806594 --- /dev/null +++ b/ports_module/cortex-m3/ac6/example_build/initws.bat @@ -0,0 +1,14 @@ +@ECHO OFF + +ECHO Initializing the workspace... + +SETLOCAL ENABLEEXTENSIONS + +%ARMDSIDEC% -nosplash -application org.eclipse.cdt.managedbuilder.core.headlessbuild -data .\workspace -import .\tx -import .\txm -import .\sample_threadx -import .\sample_threadx_module -import .\sample_threadx_module_manager +IF %ERRORLEVEL% EQU 0 GOTO WS_INITIALIZED +ECHO ERROR: failed to initialize the workspace +EXIT /B 2 + +:WS_INITIALIZED +echo Workspace initialized. +EXIT /B 0 diff --git a/ports_module/cortex-m3/ac6/example_build/sample_threadx/.cproject b/ports_module/cortex-m3/ac6/example_build/sample_threadx/.cproject new file mode 100644 index 00000000..774d26ab --- /dev/null +++ b/ports_module/cortex-m3/ac6/example_build/sample_threadx/.cproject @@ -0,0 +1,192 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_module/cortex-m3/ac6/example_build/sample_threadx/.project b/ports_module/cortex-m3/ac6/example_build/sample_threadx/.project new file mode 100644 index 00000000..2a6b3cb1 --- /dev/null +++ b/ports_module/cortex-m3/ac6/example_build/sample_threadx/.project @@ -0,0 +1,28 @@ + + + sample_threadx + + + tx + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.arm.debug.ds.nature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/ports_module/cortex-m3/ac6/example_build/sample_threadx/exceptions.c b/ports_module/cortex-m3/ac6/example_build/sample_threadx/exceptions.c new file mode 100644 index 00000000..01dd0b27 --- /dev/null +++ b/ports_module/cortex-m3/ac6/example_build/sample_threadx/exceptions.c @@ -0,0 +1,96 @@ +/* +** Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. +** Use, modification and redistribution of this file is subject to your possession of a +** valid End User License Agreement for the Arm Product of which these examples are part of +** and your compliance with all applicable terms and conditions of such licence agreement. +*/ + +/* This file contains the default exception handlers and vector table. +All exceptions are handled in Handler mode. Processor state is automatically +pushed onto the stack when an exception occurs, and popped from the stack at +the end of the handler */ + + +/* Exception Handlers */ +/* Marking as __attribute__((interrupt)) avoids them being accidentally called from elsewhere */ + +__attribute__((interrupt)) void NMIException(void) +{ while(1); } + +__attribute__((interrupt)) void HardFaultException(void) +{ while(1); } + +__attribute__((interrupt)) void MemManageException(void) +{ while(1); } + +__attribute__((interrupt)) void BusFaultException(void) +{ while(1); } + +__attribute__((interrupt)) void UsageFaultException(void) +{ while(1); } + +void __tx_SVCallHandler(void); + +__attribute__((interrupt)) void DebugMonitor(void) +{ while(1); } + +void __tx_PendSVHandler(void); + +void __tx_SysTickHandler(void); + +__attribute__((interrupt)) void InterruptHandler(void) +{ while(1); } + + +/* typedef for the function pointers in the vector table */ +typedef void(* const ExecFuncPtr)(void) __attribute__((interrupt)); + +/* Linker-generated Stack Base address */ +#ifdef TWO_REGION +extern unsigned int Image$$ARM_LIB_STACK$$ZI$$Limit; /* for Two Region model */ +#else +extern unsigned int Image$$ARM_LIB_STACKHEAP$$ZI$$Limit; /* for (default) One Region model */ +#endif + +/* Entry point for C run-time initialization */ +extern int __main(void); + + +/* Vector table +Create a named ELF section for the vector table that can be placed in a scatter file. +The first two entries are: + Initial SP = |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit| for (default) One Region model + or |Image$$ARM_LIB_STACK$$ZI$$Limit| for Two Region model + Initial PC= &__main (with LSB set to indicate Thumb) +*/ + +ExecFuncPtr vector_table[] __attribute__((section("vectors"))) = { + /* Configure Initial Stack Pointer using linker-generated symbol */ +#ifdef TWO_REGION + #pragma import(__use_two_region_memory) + (ExecFuncPtr)&Image$$ARM_LIB_STACK$$ZI$$Limit, +#else /* (default) One Region model */ + (ExecFuncPtr)&Image$$ARM_LIB_STACKHEAP$$ZI$$Limit, +#endif + (ExecFuncPtr)__main, /* Initial PC, set to entry point */ + NMIException, + HardFaultException, + MemManageException, + BusFaultException, + UsageFaultException, + 0, 0, 0, 0, /* Reserved */ + __tx_SVCallHandler, + DebugMonitor, + 0, /* Reserved */ + __tx_PendSVHandler, + __tx_SysTickHandler, + + /* Add up to 240 interrupt handlers, starting here... */ + InterruptHandler, + InterruptHandler, /* Some dummy interrupt handlers */ + InterruptHandler + /* + : + */ +}; + diff --git a/ports_module/cortex-m3/ac6/example_build/sample_threadx/sample_threadx.c b/ports_module/cortex-m3/ac6/example_build/sample_threadx/sample_threadx.c new file mode 100644 index 00000000..597f373c --- /dev/null +++ b/ports_module/cortex-m3/ac6/example_build/sample_threadx/sample_threadx.c @@ -0,0 +1,370 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; +UCHAR memory_area[DEMO_BYTE_POOL_SIZE]; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports_module/cortex-m3/ac6/example_build/sample_threadx/sample_threadx.launch b/ports_module/cortex-m3/ac6/example_build/sample_threadx/sample_threadx.launch new file mode 100644 index 00000000..d2582f5b --- /dev/null +++ b/ports_module/cortex-m3/ac6/example_build/sample_threadx/sample_threadx.launch @@ -0,0 +1,204 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_module/cortex-m3/ac6/example_build/sample_threadx/sample_threadx.scat b/ports_module/cortex-m3/ac6/example_build/sample_threadx/sample_threadx.scat new file mode 100644 index 00000000..f093ce05 --- /dev/null +++ b/ports_module/cortex-m3/ac6/example_build/sample_threadx/sample_threadx.scat @@ -0,0 +1,44 @@ +;******************************************************* +; Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. +; Use, modification and redistribution of this file is subject to your possession of a +; valid End User License Agreement for the Arm Product of which these examples are part of +; and your compliance with all applicable terms and conditions of such licence agreement. +;******************************************************* + +; Scatter-file for Cortex-M3 bare-metal example + +; This scatter-file places the vector table, application code, data, stacks and heap at suitable addresses in the memory map. + +; The vector table is placed first at the start of the image. +; Code starts after the last entry in the vector table. +; Data is placed at an address that must correspond to RAM. +; Stack and Heap are placed using ARM_LIB_STACKHEAP, to eliminate the need to set stack-base or heap-base in the debugger. +; System Control Space registers appear at their architecturally-defined addresses, based at 0xE000E000. + + +LOAD_REGION 0x00000000 +{ + VECTORS +0 0xC0 ; 16 exceptions + up to 32 interrupts, 4 bytes each entry == 0xC0 + { + exceptions.o (vectors, +FIRST) ; from exceptions.c + } + + ; Code is placed immediately (+0) after the previous root region + ; (so code region will also be a root region) + CODE +0 + { + * (+RO) ; All program code, including library code + } + + DATA +0 + { + * (+RW, +ZI) ; All RW and ZI data + } + + ; Heap grows upwards from start of this region and + ; Stack grows downwards from end of this region + ; The Main Stack Pointer is initialized on reset to the top addresses of this region + ARM_LIB_STACKHEAP +0 EMPTY 0x1000 + { + } +} diff --git a/ports_module/cortex-m3/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports_module/cortex-m3/ac6/example_build/sample_threadx/tx_initialize_low_level.S new file mode 100644 index 00000000..08da7236 --- /dev/null +++ b/ports_module/cortex-m3/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -0,0 +1,231 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global _tx_timer_interrupt + .global __main + .global __tx_NMIHandler // NMI + .global __tx_BadHandler // HardFault + .global __tx_SVCallHandler // SVCall + .global __tx_DBGHandler // Monitor + .global __tx_PendSVHandler // PendSV + .global __tx_SysTickHandler // SysTick + .global __tx_IntHandler // Int 0 + + +SYSTEM_CLOCK = 6000000 +SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) + + + .text 32 + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-M3/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_initialize_low_level(VOID) +// { + .global _tx_initialize_low_level + .thumb_func +_tx_initialize_low_level: + + /* Disable interrupts during ThreadX initialization. */ + + CPSID i + + /* Set base of available memory to end of non-initialised RAM area. */ + + LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer + LDR r1, =Image$$ARM_LIB_STACKHEAP$$ZI$$Limit // Build first free address + ADD r1, r1, #4 // + STR r1, [r0] // Setup first unused memory pointer + + /* Setup Vector Table Offset Register. */ + + MOV r0, #0xE000E000 // Build address of NVIC registers + LDR r1, =vector_table // Pickup address of vector table + STR r1, [r0, #0xD08] // Set vector table address + + /* Set system stack pointer from vector value. */ + + LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer + LDR r1, =vector_table // Pickup address of vector table + LDR r1, [r1] // Pickup reset stack pointer + STR r1, [r0] // Save system stack pointer + + /* Enable the cycle count register. */ + + LDR r0, =0xE0001000 // Build address of DWT register + LDR r1, [r0] // Pickup the current value + ORR r1, r1, #1 // Set the CYCCNTENA bit + STR r1, [r0] // Enable the cycle count register + + /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ + + MOV r0, #0xE000E000 // Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] // Setup SysTick Reload Value + MOV r1, #0x7 // Build SysTick Control Enable Value + STR r1, [r0, #0x10] // Setup SysTick Control + + /* Configure handler priorities. */ + + LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] // Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] // Setup System Handlers 8-11 Priority Registers + // Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] // Setup System Handlers 12-15 Priority Registers + // Note: PnSV must be lowest priority, which is 0xFF + + /* Return to caller. */ + + BX lr +// } + + +/* Define shells for each of the unused vectors. */ + + .global __tx_BadHandler + .thumb_func +__tx_BadHandler: + B __tx_BadHandler + +/* added to catch the hardfault */ + + .global __tx_HardfaultHandler + .thumb_func +__tx_HardfaultHandler: + B __tx_HardfaultHandler + +/* Generic interrupt handler template */ + .global __tx_IntHandler + .thumb_func +__tx_IntHandler: +// VOID InterruptHandler (VOID) +// { + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter // Call the ISR enter function +#endif + + /* Do interrupt handler work here */ + /* BL .... */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit // Call the ISR exit function +#endif + POP {r0, lr} + BX LR +// } + +/* System Tick timer interrupt handler */ + .global __tx_SysTickHandler + .global SysTick_Handler + .thumb_func +__tx_SysTickHandler: + .thumb_func +SysTick_Handler: +// VOID TimerInterruptHandler (VOID) +// { + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter // Call the ISR enter function +#endif + BL _tx_timer_interrupt +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit // Call the ISR exit function +#endif + POP {r0, lr} + BX LR +// } + + +/* NMI, DBG handlers */ + .global __tx_NMIHandler + .thumb_func +__tx_NMIHandler: + B __tx_NMIHandler + + .global __tx_DBGHandler + .thumb_func +__tx_DBGHandler: + B __tx_DBGHandler + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +/* Execution change notify functions */ + .global _tx_execution_isr_enter + .thumb_func +_tx_execution_isr_enter: + BX LR +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +/* Execution change notify functions */ + .global _tx_execution_isr_exit + .thumb_func +_tx_execution_isr_exit: + BX LR +#endif diff --git a/ports_module/cortex-m3/ac6/example_build/sample_threadx_module/.cproject b/ports_module/cortex-m3/ac6/example_build/sample_threadx_module/.cproject new file mode 100644 index 00000000..35a2d603 --- /dev/null +++ b/ports_module/cortex-m3/ac6/example_build/sample_threadx_module/.cproject @@ -0,0 +1,250 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_module/cortex-m3/ac6/example_build/sample_threadx_module/.project b/ports_module/cortex-m3/ac6/example_build/sample_threadx_module/.project new file mode 100644 index 00000000..5f1f1fa6 --- /dev/null +++ b/ports_module/cortex-m3/ac6/example_build/sample_threadx_module/.project @@ -0,0 +1,28 @@ + + + sample_threadx_module + + + txm + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.arm.debug.ds.nature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/ports_module/cortex-m3/ac6/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex-m3/ac6/example_build/sample_threadx_module/sample_threadx_module.c new file mode 100644 index 00000000..f2647144 --- /dev/null +++ b/ports_module/cortex-m3/ac6/example_build/sample_threadx_module/sample_threadx_module.c @@ -0,0 +1,432 @@ +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, + event flags group, byte pool, and block pool. */ + +/* Specify that this is a module! */ + +#define TXM_MODULE + + +/* Include the ThreadX module definitions. */ + +#include "txm_module.h" + + +/* Define constants. */ + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the external memory area. */ + +#define EXTERNAL_MEMORY_SIZE (64 * 1024) +#define EXTERNAL_MEMORY (0x80000) + + +/* Define the pool space in the bss section of the module. ULONG is used to + get the word alignment. */ + +ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD *thread_0; +TX_THREAD *thread_1; +TX_THREAD *thread_2; +TX_THREAD *thread_3; +TX_THREAD *thread_4; +TX_THREAD *thread_5; +TX_THREAD *thread_6; +TX_THREAD *thread_7; +TX_QUEUE *queue_0; +TX_SEMAPHORE *semaphore_0; +TX_MUTEX *mutex_0; +TX_EVENT_FLAGS_GROUP *event_flags_0; +TX_BYTE_POOL *byte_pool_0; +TX_BLOCK_POOL *block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; +ULONG semaphore_0_puts; +ULONG event_0_sets; +ULONG queue_0_sends; + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + +void semaphore_0_notify(TX_SEMAPHORE *semaphore_ptr) +{ + + if (semaphore_ptr == semaphore_0) + semaphore_0_puts++; +} + + +void event_0_notify(TX_EVENT_FLAGS_GROUP *event_flag_group_ptr) +{ + + if (event_flag_group_ptr == event_flags_0) + event_0_sets++; +} + + +void queue_0_notify(TX_QUEUE *queue_ptr) +{ + + if (queue_ptr == queue_0) + queue_0_sends++; +} + + +/* Define the module start function. */ + +void demo_module_start(ULONG id) +{ + +CHAR *pointer; + + /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + the control block(s). */ + txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_2, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_3, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_4, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_5, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_6, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_7, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&queue_0, sizeof(TX_QUEUE)); + txm_module_object_allocate((void*)&semaphore_0, sizeof(TX_SEMAPHORE)); + txm_module_object_allocate((void*)&mutex_0, sizeof(TX_MUTEX)); + txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); + txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); + txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(queue_0, "module queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + tx_queue_send_notify(queue_0, queue_0_notify); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(semaphore_0, "module semaphore 0", 1); + + tx_semaphore_put_notify(semaphore_0, semaphore_0_notify); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(event_flags_0, "module event flags 0"); + + tx_event_flags_set_notify(event_flags_0, event_0_notify); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(mutex_0, "module mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(block_pool_0, "module block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + /* Test external memory sharing. */ + *(ULONG *)EXTERNAL_MEMORY = 0xABABABAB; + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + diff --git a/ports_module/cortex-m3/ac6/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex-m3/ac6/example_build/sample_threadx_module/txm_module_preamble.S new file mode 100644 index 00000000..1fcc5d15 --- /dev/null +++ b/ports_module/cortex-m3/ac6/example_build/sample_threadx_module/txm_module_preamble.S @@ -0,0 +1,62 @@ + .text + .align 4 + .syntax unified + .section Init + + // Define public symbols + .global __txm_module_preamble + + // Define application-specific start/stop entry points for the module + .global demo_module_start + + // Define common external references + .global _txm_module_thread_shell_entry + .global _txm_module_callback_request_thread_entry + + .eabi_attribute Tag_ABI_PCS_RO_data, 1 + .eabi_attribute Tag_ABI_PCS_R9_use, 1 + .eabi_attribute Tag_ABI_PCS_RW_data, 2 + +__txm_module_preamble: + .dc.l 0x4D4F4455 // Module ID + .dc.l 0x6 // Module Major Version + .dc.l 0x1 // Module Minor Version + .dc.l 32 // Module Preamble Size in 32-bit words + .dc.l 0x12345678 // Module ID (application defined) + .dc.l 0x01000007 // Module Properties where: + // Bits 31-24: Compiler ID + // 0 -> IAR + // 1 -> ARM + // 2 -> GNU + // Bit 0: 0 -> Privileged mode execution + // 1 -> User mode execution + // Bit 1: 0 -> No MPU protection + // 1 -> MPU protection (must have user mode selected) + // Bit 2: 0 -> Disable shared/external memory access + // 1 -> Enable shared/external memory access + .dc.l _txm_module_thread_shell_entry - __txm_module_preamble // Module Shell Entry Point + .dc.l demo_module_start - __txm_module_preamble // Module Start Thread Entry Point + .dc.l 0 // Module Stop Thread Entry Point + .dc.l 1 // Module Start/Stop Thread Priority + .dc.l 1024 // Module Start/Stop Thread Stack Size + .dc.l _txm_module_callback_request_thread_entry - __txm_module_preamble // Module Callback Thread Entry + .dc.l 1 // Module Callback Thread Priority + .dc.l 1024 // Module Callback Thread Stack Size + .dc.l 0x10000 // Module Code Size + .dc.l 0x10000 // Module Data Size + .dc.l 0 // Reserved 0 + .dc.l 0 // Reserved 1 + .dc.l 0 // Reserved 2 + .dc.l 0 // Reserved 3 + .dc.l 0 // Reserved 4 + .dc.l 0 // Reserved 5 + .dc.l 0 // Reserved 6 + .dc.l 0 // Reserved 7 + .dc.l 0 // Reserved 8 + .dc.l 0 // Reserved 9 + .dc.l 0 // Reserved 10 + .dc.l 0 // Reserved 11 + .dc.l 0 // Reserved 12 + .dc.l 0 // Reserved 13 + .dc.l 0 // Reserved 14 + .dc.l 0 // Reserved 15 diff --git a/ports_module/cortex-m3/ac6/example_build/sample_threadx_module_manager/.cproject b/ports_module/cortex-m3/ac6/example_build/sample_threadx_module_manager/.cproject new file mode 100644 index 00000000..670dd435 --- /dev/null +++ b/ports_module/cortex-m3/ac6/example_build/sample_threadx_module_manager/.cproject @@ -0,0 +1,196 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_module/cortex-m3/ac6/example_build/sample_threadx_module_manager/.project b/ports_module/cortex-m3/ac6/example_build/sample_threadx_module_manager/.project new file mode 100644 index 00000000..bddfb9ee --- /dev/null +++ b/ports_module/cortex-m3/ac6/example_build/sample_threadx_module_manager/.project @@ -0,0 +1,29 @@ + + + sample_threadx_module_manager + + + sample_threadx_module + tx + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.arm.debug.ds.nature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/ports_module/cortex-m3/ac6/example_build/sample_threadx_module_manager/exceptions.c b/ports_module/cortex-m3/ac6/example_build/sample_threadx_module_manager/exceptions.c new file mode 100644 index 00000000..0cef25ce --- /dev/null +++ b/ports_module/cortex-m3/ac6/example_build/sample_threadx_module_manager/exceptions.c @@ -0,0 +1,93 @@ +/* +** Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. +** Use, modification and redistribution of this file is subject to your possession of a +** valid End User License Agreement for the Arm Product of which these examples are part of +** and your compliance with all applicable terms and conditions of such licence agreement. +*/ + +/* This file contains the default exception handlers and vector table. +All exceptions are handled in Handler mode. Processor state is automatically +pushed onto the stack when an exception occurs, and popped from the stack at +the end of the handler */ + + +/* Exception Handlers */ +/* Marking as __attribute__((interrupt)) avoids them being accidentally called from elsewhere */ + +__attribute__((interrupt)) void NMIException(void) +{ while(1); } + +__attribute__((interrupt)) void HardFaultException(void) +{ while(1); } + +void MemManage_Handler(void); + +void BusFault_Handler(void); + +void UsageFault_Handler(void); + +void __tx_SVCallHandler(void); + +__attribute__((interrupt)) void DebugMonitor(void) +{ while(1); } + +void __tx_PendSVHandler(void); + +void __tx_SysTickHandler(void); + +__attribute__((interrupt)) void InterruptHandler(void) +{ while(1); } + + +/* typedef for the function pointers in the vector table */ +typedef void(* const ExecFuncPtr)(void) __attribute__((interrupt)); + +/* Linker-generated Stack Base address */ +#ifdef TWO_REGION +extern unsigned int Image$$ARM_LIB_STACK$$ZI$$Limit; /* for Two Region model */ +#else +extern unsigned int Image$$ARM_LIB_STACKHEAP$$ZI$$Limit; /* for (default) One Region model */ +#endif + +/* Entry point for C run-time initialization */ +extern int __main(void); + + +/* Vector table +Create a named ELF section for the vector table that can be placed in a scatter file. +The first two entries are: + Initial SP = |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit| for (default) One Region model + or |Image$$ARM_LIB_STACK$$ZI$$Limit| for Two Region model + Initial PC= &__main (with LSB set to indicate Thumb) +*/ + +ExecFuncPtr vector_table[] __attribute__((section("vectors"))) = { + /* Configure Initial Stack Pointer using linker-generated symbol */ +#ifdef TWO_REGION + #pragma import(__use_two_region_memory) + (ExecFuncPtr)&Image$$ARM_LIB_STACK$$ZI$$Limit, +#else /* (default) One Region model */ + (ExecFuncPtr)&Image$$ARM_LIB_STACKHEAP$$ZI$$Limit, +#endif + (ExecFuncPtr)__main, /* Initial PC, set to entry point */ + NMIException, + HardFaultException, + MemManage_Handler, + BusFault_Handler, + UsageFault_Handler, + 0, 0, 0, 0, /* Reserved */ + __tx_SVCallHandler, + DebugMonitor, + 0, /* Reserved */ + __tx_PendSVHandler, + __tx_SysTickHandler, + + /* Add up to 240 interrupt handlers, starting here... */ + InterruptHandler, + InterruptHandler, /* Some dummy interrupt handlers */ + InterruptHandler + /* + : + */ +}; + diff --git a/ports_module/cortex-m3/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat b/ports_module/cortex-m3/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat new file mode 100644 index 00000000..f093ce05 --- /dev/null +++ b/ports_module/cortex-m3/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat @@ -0,0 +1,44 @@ +;******************************************************* +; Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. +; Use, modification and redistribution of this file is subject to your possession of a +; valid End User License Agreement for the Arm Product of which these examples are part of +; and your compliance with all applicable terms and conditions of such licence agreement. +;******************************************************* + +; Scatter-file for Cortex-M3 bare-metal example + +; This scatter-file places the vector table, application code, data, stacks and heap at suitable addresses in the memory map. + +; The vector table is placed first at the start of the image. +; Code starts after the last entry in the vector table. +; Data is placed at an address that must correspond to RAM. +; Stack and Heap are placed using ARM_LIB_STACKHEAP, to eliminate the need to set stack-base or heap-base in the debugger. +; System Control Space registers appear at their architecturally-defined addresses, based at 0xE000E000. + + +LOAD_REGION 0x00000000 +{ + VECTORS +0 0xC0 ; 16 exceptions + up to 32 interrupts, 4 bytes each entry == 0xC0 + { + exceptions.o (vectors, +FIRST) ; from exceptions.c + } + + ; Code is placed immediately (+0) after the previous root region + ; (so code region will also be a root region) + CODE +0 + { + * (+RO) ; All program code, including library code + } + + DATA +0 + { + * (+RW, +ZI) ; All RW and ZI data + } + + ; Heap grows upwards from start of this region and + ; Stack grows downwards from end of this region + ; The Main Stack Pointer is initialized on reset to the top addresses of this region + ARM_LIB_STACKHEAP +0 EMPTY 0x1000 + { + } +} diff --git a/ports_module/cortex-m3/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c b/ports_module/cortex-m3/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c new file mode 100644 index 00000000..210f0be0 --- /dev/null +++ b/ports_module/cortex-m3/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c @@ -0,0 +1,126 @@ +/* Small demonstration of the ThreadX module manager. */ + +#include "tx_api.h" +#include "txm_module.h" + + +#define DEMO_STACK_SIZE 1024 + +/* Define the ThreadX object control blocks... */ + +TX_THREAD module_manager; +TXM_MODULE_INSTANCE my_module; + + +/* Define the object pool area. */ + +UCHAR object_memory[16384]; + + +/* Define the module data pool area. */ + +#define MODULE_DATA_SIZE (256 * 1024) +#define MODULE_DATA (0x40000) + + +/* The module code should be loaded here. */ + +#define MODULE_CODE (0x30000) + + +/* Define the external memory area. */ + +#define EXTERNAL_MEMORY_SIZE (64 * 1024) +#define EXTERNAL_MEMORY (0x80000) + + +/* Define the count of memory faults. */ + +ULONG memory_faults; + + +/* Define thread prototypes. */ + +void module_manager_entry(ULONG thread_input); + + +/* Define fault handler. */ + +VOID module_fault_handler(TX_THREAD *thread, TXM_MODULE_INSTANCE *module) +{ + + /* Just increment the fault counter. */ + memory_faults++; +} + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = (CHAR*)first_unused_memory; + + + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + pointer = pointer + DEMO_STACK_SIZE; +} + + + + +/* Define the test threads. */ + +void module_manager_entry(ULONG thread_input) +{ + + /* Initialize the module manager. */ + txm_module_manager_initialize((void *) MODULE_DATA, MODULE_DATA_SIZE); + + txm_module_manager_object_pool_create(object_memory, sizeof(object_memory)); + + /* Register a fault handler. */ + txm_module_manager_memory_fault_notify(module_fault_handler); + + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ + txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE); + + /* Enable a read/write shared memory region. */ + txm_module_manager_external_memory_enable(&my_module, (void *) EXTERNAL_MEMORY, EXTERNAL_MEMORY_SIZE, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); + + /* Start the module. */ + txm_module_manager_start(&my_module); + + /* Sleep for a while.... */ + tx_thread_sleep(1000); + + /* Stop the module. */ + txm_module_manager_stop(&my_module); + + /* Unload the module. */ + txm_module_manager_unload(&my_module); + + /* Load the module that is already there. */ + txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE); + + /* Start the module again. */ + txm_module_manager_start(&my_module); + + /* Now just spin... */ + while(1) + { + + tx_thread_sleep(100); + } +} diff --git a/ports_module/cortex-m3/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.ds b/ports_module/cortex-m3/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.ds new file mode 100644 index 00000000..b1993316 --- /dev/null +++ b/ports_module/cortex-m3/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.ds @@ -0,0 +1,3 @@ +wait +load ..\sample_threadx_module\Debug\sample_threadx_module.axf +wait diff --git a/ports_module/cortex-m3/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.launch b/ports_module/cortex-m3/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.launch new file mode 100644 index 00000000..d6a65114 --- /dev/null +++ b/ports_module/cortex-m3/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.launch @@ -0,0 +1,226 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_module/cortex-m3/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager_debug.ds b/ports_module/cortex-m3/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager_debug.ds new file mode 100644 index 00000000..fc83a4f2 --- /dev/null +++ b/ports_module/cortex-m3/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager_debug.ds @@ -0,0 +1,3 @@ +wait +add-symbol-file ..\sample_threadx_module\Debug\sample_threadx_module.axf +wait diff --git a/ports_module/cortex-m3/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S b/ports_module/cortex-m3/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S new file mode 100644 index 00000000..3e4c786e --- /dev/null +++ b/ports_module/cortex-m3/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S @@ -0,0 +1,231 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global _tx_timer_interrupt + .global __main + .global __tx_NMIHandler // NMI + .global __tx_BadHandler // HardFault + .global __tx_SVCallHandler // SVCall + .global __tx_DBGHandler // Monitor + .global __tx_PendSVHandler // PendSV + .global __tx_SysTickHandler // SysTick + .global __tx_IntHandler // Int 0 + + +SYSTEM_CLOCK = 6000000 +SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) + + + .text 32 + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-M3/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_initialize_low_level(VOID) +// { + .global _tx_initialize_low_level + .thumb_func +_tx_initialize_low_level: + + /* Disable interrupts during ThreadX initialization. */ + + CPSID i + + /* Set base of available memory to end of non-initialised RAM area. */ + + LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer + LDR r1, =Image$$ARM_LIB_STACKHEAP$$ZI$$Limit // Build first free address + ADD r1, r1, #4 // + STR r1, [r0] // Setup first unused memory pointer + + /* Setup Vector Table Offset Register. */ + + MOV r0, #0xE000E000 // Build address of NVIC registers + LDR r1, =vector_table // Pickup address of vector table + STR r1, [r0, #0xD08] // Set vector table address + + /* Set system stack pointer from vector value. */ + + LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer + LDR r1, =vector_table // Pickup address of vector table + LDR r1, [r1] // Pickup reset stack pointer + STR r1, [r0] // Save system stack pointer + + /* Enable the cycle count register. */ + + LDR r0, =0xE0001000 // Build address of DWT register + LDR r1, [r0] // Pickup the current value + ORR r1, r1, #1 // Set the CYCCNTENA bit + STR r1, [r0] // Enable the cycle count register + + /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ + + MOV r0, #0xE000E000 // Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] // Setup SysTick Reload Value + MOV r1, #0x7 // Build SysTick Control Enable Value + STR r1, [r0, #0x10] // Setup SysTick Control + + /* Configure handler priorities. */ + + LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] // Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] // Setup System Handlers 8-11 Priority Registers + // Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] // Setup System Handlers 12-15 Priority Registers + // Note: PnSV must be lowest priority, which is 0xFF + + /* Return to caller. */ + + BX lr +// } + + +/* Define shells for each of the unused vectors. */ + + .global __tx_BadHandler + .thumb_func +__tx_BadHandler: + B __tx_BadHandler + +/* added to catch the hardfault */ + + .global __tx_HardfaultHandler + .thumb_func +__tx_HardfaultHandler: + B __tx_HardfaultHandler + +/* Generic interrupt handler template */ + .global __tx_IntHandler + .thumb_func +__tx_IntHandler: +// VOID InterruptHandler (VOID) +// { + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter // Call the ISR enter function +#endif + + /* Do interrupt handler work here */ + /* BL .... */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit // Call the ISR exit function +#endif + POP {r0, lr} + BX LR +// } + +/* System Tick timer interrupt handler */ + .global __tx_SysTickHandler + .global SysTick_Handler + .thumb_func +__tx_SysTickHandler: + .thumb_func +SysTick_Handler: +// VOID TimerInterruptHandler (VOID) +// { + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter // Call the ISR enter function +#endif + BL _tx_timer_interrupt +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit // Call the ISR exit function +#endif + POP {r0, lr} + BX LR +// } + + +/* NMI, DBG handlers */ + .global __tx_NMIHandler + .thumb_func +__tx_NMIHandler: + B __tx_NMIHandler + + .global __tx_DBGHandler + .thumb_func +__tx_DBGHandler: + B __tx_DBGHandler + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +/* Execution change notify functions */ + .global _tx_execution_isr_enter + .thumb_func +_tx_execution_isr_enter: + BX LR +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +/* Execution change notify functions */ + .global _tx_execution_isr_exit + .thumb_func +_tx_execution_isr_exit: + BX LR +#endif diff --git a/ports_module/cortex-m3/ac6/example_build/setenv.bat b/ports_module/cortex-m3/ac6/example_build/setenv.bat new file mode 100644 index 00000000..27fecdfc --- /dev/null +++ b/ports_module/cortex-m3/ac6/example_build/setenv.bat @@ -0,0 +1,16 @@ +@ECHO OFF + +SET ARMDSDIR="C:\Program Files\Arm\Development Studio 2020.0" +IF EXIST %ARMDSDIR% GOTO FOUND_ARMDS +ECHO ARM Development Studio not found. +EXIT /B 1 + +:FOUND_ARMDS +SET ARMDSIDEC=%ARMDSDIR%\bin\armds_idec.exe +IF EXIST %ARMDSIDEC% GOTO FOUND_ARMDS_IDEC +ECHO armds_idec.exe not found. +EXIT /B 1 + +:FOUND_ARMDS_IDEC +ECHO armds_idec.exe found at %ARMDSIDEC% +EXIT /B 0 diff --git a/ports_module/cortex-m3/ac6/example_build/tx/.cproject b/ports_module/cortex-m3/ac6/example_build/tx/.cproject new file mode 100644 index 00000000..06929bd2 --- /dev/null +++ b/ports_module/cortex-m3/ac6/example_build/tx/.cproject @@ -0,0 +1,162 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_module/cortex-m3/ac6/example_build/tx/.project b/ports_module/cortex-m3/ac6/example_build/tx/.project new file mode 100644 index 00000000..207f353b --- /dev/null +++ b/ports_module/cortex-m3/ac6/example_build/tx/.project @@ -0,0 +1,63 @@ + + + tx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + inc_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/inc + + + inc_generic_module_manager + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common_modules/module_manager/inc + + + inc_generic_modules + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common_modules/inc + + + inc_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/inc + + + src_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/src + + + src_generic_module_manager + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common_modules/module_manager/src + + + src_port_module_manager + 2 + $%7BPARENT-2-PROJECT_LOC%7D/module_manager/src + + + diff --git a/ports_module/cortex-m3/ac6/example_build/txm/.cproject b/ports_module/cortex-m3/ac6/example_build/txm/.cproject new file mode 100644 index 00000000..dd64d0bf --- /dev/null +++ b/ports_module/cortex-m3/ac6/example_build/txm/.cproject @@ -0,0 +1,184 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_module/cortex-m3/ac6/example_build/txm/.project b/ports_module/cortex-m3/ac6/example_build/txm/.project new file mode 100644 index 00000000..8b510516 --- /dev/null +++ b/ports_module/cortex-m3/ac6/example_build/txm/.project @@ -0,0 +1,58 @@ + + + txm + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + inc_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/inc + + + inc_generic_module_manager + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common_modules/module_manager/inc + + + inc_generic_modules + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common_modules/inc + + + inc_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/inc + + + src_generic_module_lib + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common_modules/module_lib/src + + + src_port_module_lib + 2 + $%7BPARENT-2-PROJECT_LOC%7D/module_lib/src + + + diff --git a/ports_module/cortex-m3/ac6/inc/tx_port.h b/ports_module/cortex-m3/ac6/inc/tx_port.h new file mode 100644 index 00000000..27f69bbf --- /dev/null +++ b/ports_module/cortex-m3/ac6/inc/tx_port.h @@ -0,0 +1,378 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-M3/AC6 */ +/* 6.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX Cortex-M3 port. */ + +#define TX_INT_DISABLE 1 /* Disable interrupts */ +#define TX_INT_ENABLE 0 /* Enable interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0 + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); + +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define the get system state macro. */ + +#ifndef TX_THREAD_GET_SYSTEM_STATE +#ifndef TX_MISRA_ENABLE + +__attribute__( ( always_inline ) ) static inline unsigned int __get_ipsr_value(void) +{ + +unsigned int ipsr_value; + + __asm__ volatile (" MRS %0,IPSR ": "=r" (ipsr_value) ); + return(ipsr_value); +} + + +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | __get_ipsr_value()) +#else +ULONG _tx_misra_ipsr_get(VOID); +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get()) +#endif +#endif + + +/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value + indicates that _tx_thread_system_return should not be called. */ + +#ifndef TX_THREAD_SYSTEM_RETURN_CHECK +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#endif + +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to + prevent early scheduling on Cortex-M parts. */ + +#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; + + +/* This ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + +#endif + + +#ifndef TX_DISABLE_INLINE + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + + +__attribute__( ( always_inline ) ) static inline unsigned int __disable_interrupts(void) +{ + +unsigned int primask_value; + + __asm__ volatile (" MRS %0,PRIMASK ": "=r" (primask_value) ); + __asm__ volatile (" CPSID i" : : : "memory" ); + return(primask_value); +} + +__attribute__( ( always_inline ) ) static inline void __restore_interrupts(unsigned int primask_value) +{ + + __asm__ volatile (" MSR PRIMASK,%0": : "r" (primask_value): "memory" ); +} + +__attribute__( ( always_inline ) ) static inline unsigned int __get_primask_value(void) +{ + +unsigned int primask_value; + + __asm__ volatile (" MRS %0,PRIMASK ": "=r" (primask_value) ); + return(primask_value); +} + +__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void) +{ + + __asm__ volatile (" CPSIE i": : : "memory" ); +} + + +__attribute__( ( always_inline ) ) static inline void _tx_thread_system_return_inline(void) +{ +unsigned int interrupt_save; + + *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + if (__get_ipsr_value() == 0) + { + interrupt_save = __get_primask_value(); + __enable_interrupts(); + __restore_interrupts(interrupt_save); + } +} + + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = __disable_interrupts(); +#define TX_RESTORE __restore_interrupts(interrupt_save); + + +/* Redefine _tx_thread_system_return for improved performance. */ + +#define _tx_thread_system_return _tx_thread_system_return_inline + + +#else + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); +#define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); +#endif + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/AC6 Version 6.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif diff --git a/ports_module/cortex-m3/ac6/inc/txm_module_port.h b/ports_module/cortex-m3/ac6/inc/txm_module_port.h new file mode 100644 index 00000000..139ed25a --- /dev/null +++ b/ports_module/cortex-m3/ac6/inc/txm_module_port.h @@ -0,0 +1,345 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* txm_module_port.h Cortex-M3/MPU/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the basic module constants, interface structures, */ +/* and function prototypes. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Andres Mlinar Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TXM_MODULE_PORT_H +#define TXM_MODULE_PORT_H + +/* Determine if the optional Modules user define file should be used. */ + +#ifdef TXM_MODULE_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in txm_module_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "txm_module_user.h" +#endif + +/* It is assumed that the base ThreadX tx_port.h file has been modified to add the + following extensions to the ThreadX thread control block (this code should replace + the corresponding macro define in tx_port.h): + +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; + +The following extensions must also be defined in tx_port.h: + +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); + +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); +*/ + +/* Define the kernel stack size for a module thread. */ +#ifndef TXM_MODULE_KERNEL_STACK_SIZE +#define TXM_MODULE_KERNEL_STACK_SIZE 768 +#endif + +/* For the following 3 access control settings, change TEX and C, B, S (bits 21 through 16 of MPU_RASR) + * to reflect your system memory attributes (cache, shareable, memory type). */ +/* Code region access control: privileged read-only, outer & inner write-back, normal memory, shareable. */ +#define TXM_MODULE_MPU_CODE_ACCESS_CONTROL 0x06070000 +/* Data region access control: execute never, read/write, outer & inner write-back, normal memory, shareable. */ +#define TXM_MODULE_MPU_DATA_ACCESS_CONTROL 0x13070000 +/* Shared region access control: execute never, read-only, outer & inner write-back, normal memory, shareable. */ +#define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 + + +/* Define constants specific to the tools the module can be built with for this particular modules port. */ + +#define TXM_MODULE_IAR_COMPILER 0x00000000 +#define TXM_MODULE_RVDS_COMPILER 0x01000000 +#define TXM_MODULE_GNU_COMPILER 0x02000000 +#define TXM_MODULE_COMPILER_MASK 0xFF000000 +#define TXM_MODULE_OPTIONS_MASK 0x000000FF + + +/* Define the properties for this particular module port. */ + +#define TXM_MODULE_MEMORY_PROTECTION_ENABLED + +#ifdef TXM_MODULE_MEMORY_PROTECTION_ENABLED +#define TXM_MODULE_REQUIRE_ALLOCATED_OBJECT_MEMORY +#else +#define TXM_MODULE_REQUIRE_LOCAL_OBJECT_MEMORY +#endif + +#define TXM_MODULE_USER_MODE 0x00000001 +#define TXM_MODULE_MEMORY_PROTECTION 0x00000002 +#define TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS 0x00000004 + + +/* Define the supported options for this module. */ + +#define TXM_MODULE_MANAGER_SUPPORTED_OPTIONS (TXM_MODULE_USER_MODE | TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS) +#define TXM_MODULE_MANAGER_REQUIRED_OPTIONS 0 + + +/* Define offset adjustments according to the compiler used to build the module. */ + +#define TXM_MODULE_IAR_SHELL_ADJUST 24 +#define TXM_MODULE_IAR_START_ADJUST 28 +#define TXM_MODULE_IAR_STOP_ADJUST 32 +#define TXM_MODULE_IAR_CALLBACK_ADJUST 44 + +#define TXM_MODULE_RVDS_SHELL_ADJUST 0 +#define TXM_MODULE_RVDS_START_ADJUST 0 +#define TXM_MODULE_RVDS_STOP_ADJUST 0 +#define TXM_MODULE_RVDS_CALLBACK_ADJUST 0 + +#define TXM_MODULE_GNU_SHELL_ADJUST 24 +#define TXM_MODULE_GNU_START_ADJUST 28 +#define TXM_MODULE_GNU_STOP_ADJUST 32 +#define TXM_MODULE_GNU_CALLBACK_ADJUST 44 + + +/* Define other module port-specific constants. */ + +/* Define INLINE_DECLARE to inline for ARM compiler. */ + +#define INLINE_DECLARE inline + +/* Define the number of MPU entries assigned to the code and data sections. On Cortex-M parts, there can only be 7 total + entries, since ThreadX uses one for access to the kernel dispatch function. */ + +#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 +#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 +#define TXM_MODULE_MANAGER_SHARED_MPU_INDEX 8 +#define TXM_MODULE_MANAGER_SHARED_MPU_REGION 4 + +/* Shared memory region attributes. */ +#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 +#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 + +/* Define the port-extensions to the module manager instance structure. */ + +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + ULONG txm_module_instance_mpu_registers[16]; \ + ULONG txm_module_instance_shared_memory_address; \ + ULONG txm_module_instance_shared_memory_length; + + +/* Define the memory fault information structure that is populated when a memory fault occurs. */ + + +typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT +{ + TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr; + VOID *txm_module_manager_memory_fault_info_code_location; + ULONG txm_module_manager_memory_fault_info_shcsr; + ULONG txm_module_manager_memory_fault_info_cfsr; + ULONG txm_module_manager_memory_fault_info_mmfar; + ULONG txm_module_manager_memory_fault_info_bfar; + ULONG txm_module_manager_memory_fault_info_control; + ULONG txm_module_manager_memory_fault_info_sp; + ULONG txm_module_manager_memory_fault_info_r0; + ULONG txm_module_manager_memory_fault_info_r1; + ULONG txm_module_manager_memory_fault_info_r2; + ULONG txm_module_manager_memory_fault_info_r3; + ULONG txm_module_manager_memory_fault_info_r4; + ULONG txm_module_manager_memory_fault_info_r5; + ULONG txm_module_manager_memory_fault_info_r6; + ULONG txm_module_manager_memory_fault_info_r7; + ULONG txm_module_manager_memory_fault_info_r8; + ULONG txm_module_manager_memory_fault_info_r9; + ULONG txm_module_manager_memory_fault_info_r10; + ULONG txm_module_manager_memory_fault_info_r11; + ULONG txm_module_manager_memory_fault_info_r12; + ULONG txm_module_manager_memory_fault_info_lr; + ULONG txm_module_manager_memory_fault_info_xpsr; +} TXM_MODULE_MANAGER_MEMORY_FAULT_INFO; + + +#define TXM_MODULE_MANAGER_FAULT_INFO \ + TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info; + +/* Define the macro to check the stack available in dispatch. */ +#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE \ + ULONG stack_available; \ + __asm("MOV %0, SP" : "=r"(stack_available)); \ + stack_available -= (ULONG)_tx_thread_current_ptr->tx_thread_stack_start; \ + if((stack_available < TXM_MODULE_MINIMUM_STACK_AVAILABLE) || \ + (stack_available > _tx_thread_current_ptr->tx_thread_stack_size)) \ + { \ + return(TX_SIZE_ERROR); \ + } + + +/* Define the macro to check the code alignment. */ + +#define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment) \ + { \ + ULONG temp; \ + temp = (ULONG) module_location; \ + temp = temp & (code_alignment - 1); \ + if (temp) \ + { \ + _tx_mutex_put(&_txm_module_manager_mutex); \ + return(TXM_MODULE_ALIGNMENT_ERROR); \ + } \ + } + + +/* Define the macro to adjust the alignment and size for code/data areas. */ + +#define TXM_MODULE_MANAGER_ALIGNMENT_ADJUST(module_preamble, code_size, code_alignment, data_size, data_alignment) _txm_module_manager_alignment_adjust(module_preamble, &code_size, &code_alignment, &data_size, &data_alignment); + + +/* Define the macro to adjust the symbols in the module preamble. */ + +#define TXM_MODULE_MANAGER_CALCULATE_ADJUSTMENTS(properties, shell_function_adjust, start_function_adjust, stop_function_adjust, callback_function_adjust) \ + if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_IAR_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_IAR_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_IAR_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_IAR_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_IAR_CALLBACK_ADJUST; \ + } \ + else if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_RVDS_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_RVDS_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_RVDS_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_RVDS_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_RVDS_CALLBACK_ADJUST; \ + } \ + else \ + { \ + shell_function_adjust = TXM_MODULE_GNU_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_GNU_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_GNU_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_GNU_CALLBACK_ADJUST; \ + } + + +/* Define the macro to populate the thread control block with module port-specific information. + Check if the module is in user mode and set up txm_module_thread_entry_info_kernel_call_dispatcher accordingly. +*/ + +#define TXM_MODULE_MANAGER_THREAD_SETUP(thread_ptr, module_instance) \ + thread_ptr -> tx_thread_module_current_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \ + thread_ptr -> tx_thread_module_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \ + if (thread_ptr -> tx_thread_module_user_mode) \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_user_mode_entry; \ + } \ + else \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_kernel_dispatch; \ + } + + +/* Define the macro to populate the module control block with module port-specific information. + If memory protection is enabled, set up the MPU registers. +*/ +#define TXM_MODULE_MANAGER_MODULE_SETUP(module_instance) \ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE) \ + { \ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) \ + { \ + _txm_module_manager_mm_register_setup(module_instance); \ + } \ + } \ + else \ + { \ + /* Do nothing. */ \ + } + +/* Define the macro to perform port-specific functions when unloading the module. */ +/* Nothing needs to be done for this port. */ +#define TXM_MODULE_MANAGER_MODULE_UNLOAD(module_instance) + + +/* Define the macros to perform port-specific checks when passing pointers to the kernel. */ + +/* Define macro to make sure object is inside the module's data. */ +#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ + /* Check if it's inside module data. */ \ + ((((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && \ + (((obj_ptr) + (obj_size)) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) || \ + /* Check if it's inside shared memory. */ \ + (((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address) && \ + (((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (module_instance -> txm_module_instance_shared_memory_address + module_instance -> txm_module_instance_shared_memory_length)))) + + +/* Define some internal prototypes to this module port. */ + +#ifndef TX_SOURCE_CODE +#define txm_module_manager_memory_fault_notify _txm_module_manager_memory_fault_notify +#endif + + +#define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES \ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment); \ +VOID _txm_module_manager_memory_fault_handler(VOID); \ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)); \ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \ +ULONG _txm_power_of_two_block_size(ULONG size); \ +ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); \ +ULONG _txm_module_manager_region_size_get(ULONG block_size); + +#define TXM_MODULE_MANAGER_VERSION_ID \ +CHAR _txm_module_manager_version_id[] = \ + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3/MPU/AC6 Version 6.1 *"; + +#endif diff --git a/ports_module/cortex-m3/ac6/module_lib/src/txm_module_initialize.S b/ports_module/cortex-m3/ac6/module_lib/src/txm_module_initialize.S new file mode 100644 index 00000000..455e86b5 --- /dev/null +++ b/ports_module/cortex-m3/ac6/module_lib/src/txm_module_initialize.S @@ -0,0 +1,104 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .global __use_two_region_memory + .global __scatterload + + + .eabi_attribute Tag_ABI_PCS_RO_data, 1 + .eabi_attribute Tag_ABI_PCS_R9_use, 1 + .eabi_attribute Tag_ABI_PCS_RW_data, 2 + + .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_initialize Cortex-M4/MPU/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes the module c runtime. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __scatterload Initialize C runtime */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_thread_shell_entry Start module thread */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Andres Mlinar Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _txm_module_initialize(VOID) + .global _txm_module_initialize + .thumb_func +_txm_module_initialize: + PUSH {r4-r12,lr} // Save dregs and LR + //B __scatterload // Call ARM func to initialize variables + +// Override the __rt_exit function. + .global __rt_exit + .thumb_func +__rt_exit: + POP {r4-r12,lr} // Restore dregs and LR + BX lr // Return to caller + +#define TXM_MODULE_HEAP_SIZE 512 + +// returns heap start address in R0 +// returns heap end address in R2 +// does not touch SP, it is already set up before the module runs + .global __user_setup_stackheap + .thumb_func +__user_setup_stackheap: + LDR r1, _txm_heap // load heap offset + MOV r2, TXM_MODULE_HEAP_SIZE // load heap size + ADD r2, r2, r0 // calculate heap end address + BX lr + +// dummy main function + .global main + .thumb_func +main: + BX lr + + .align 8 +_txm_heap: + .zero TXM_MODULE_HEAP_SIZE diff --git a/ports_module/cortex-m3/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex-m3/ac6/module_lib/src/txm_module_thread_shell_entry.c new file mode 100644 index 00000000..34ec131d --- /dev/null +++ b/ports_module/cortex-m3/ac6/module_lib/src/txm_module_thread_shell_entry.c @@ -0,0 +1,172 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#ifndef TXM_MODULE +#define TXM_MODULE +#endif + +#ifndef TX_SOURCE_CODE +#define TX_SOURCE_CODE +#endif + + +/* Include necessary system files. */ + +#include "txm_module.h" +#include "tx_thread.h" + +/* Define the global module entry pointer from the start thread of the module. */ + +TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; + + +/* Define the dispatch function pointer used in the module implementation. */ + +ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3); + + +/* Define the ARM cstartup code. */ +extern VOID _txm_module_initialize(VOID); + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_thread_shell_entry Cortex-M3/MPU/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calls the specified entry function of the thread. It */ +/* also provides a place for the thread's entry function to return. */ +/* If the thread returns, this function places the thread in a */ +/* "COMPLETED" state. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to current thread */ +/* thread_info Pointer to thread entry info */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_initialize cstartup initialization */ +/* thread_entry Thread's entry function */ +/* tx_thread_resume Resume the module callback thread */ +/* _txm_module_thread_system_suspend Module thread suspension routine */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) +{ + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + VOID (*entry_exit_notify)(TX_THREAD *, UINT); +#endif + + + /* Determine if this is the start thread. If so, we must prepare the module for + execution. If not, simply skip the C startup code. */ + if (thread_info -> txm_module_thread_entry_info_start_thread) + { + /* Initialize the ARM C environment. */ + _txm_module_initialize(); + + /* Save the entry info pointer, for later use. */ + _txm_module_entry_info = thread_info; + + /* Save the kernel function dispatch address. This is used to make all resident calls from + the module. */ + _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; + + /* Ensure that we have a valid pointer. */ + while (!_txm_module_kernel_call_dispatcher) + { + /* Loop here, if an error is present getting the dispatch function pointer! + An error here typically indicates the resident portion of _tx_thread_schedule + is not supporting the trap to obtain the function pointer. */ + } + + /* Resume the module's callback thread, already created in the manager. */ + _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); + } + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has been entered! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_ENTRY); + } +#endif + + /* Call current thread's entry function. */ + (thread_info -> txm_module_thread_entry_info_entry) (thread_info -> txm_module_thread_entry_info_parameter); + + /* Suspend thread with a "completed" state. */ + + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine again. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has exited! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_EXIT); + } +#endif + + /* Call actual thread suspension routine. */ + _txm_module_thread_system_suspend(thread_ptr); + +#ifdef TX_SAFETY_CRITICAL + + /* If we ever get here, raise safety critical exception. */ + TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0); +#endif +} + diff --git a/ports_module/cortex-m3/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex-m3/ac6/module_manager/src/tx_thread_context_restore.S new file mode 100644 index 00000000..da83909f --- /dev/null +++ b/ports_module/cortex-m3/ac6/module_manager/src/tx_thread_context_restore.S @@ -0,0 +1,76 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .text + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore Cortex-M3/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is only needed for legacy applications and it should */ +/* not be called in any new development on a Cortex-M. */ +/* This function restores the interrupt context if it is processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_context_restore(VOID) +// { + .global _tx_thread_context_restore + .thumb_func +_tx_thread_context_restore: + /* Not needed for this port - just return! */ + BX lr +// } diff --git a/ports_module/cortex-m3/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex-m3/ac6/module_manager/src/tx_thread_context_save.S new file mode 100644 index 00000000..e48108d5 --- /dev/null +++ b/ports_module/cortex-m3/ac6/module_manager/src/tx_thread_context_save.S @@ -0,0 +1,75 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .text + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save Cortex-M3/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is only needed for legacy applications and it should */ +/* not be called in any new development on a Cortex-M. */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_context_save(VOID) +// { + .global _tx_thread_context_save + .thumb_func +_tx_thread_context_save: + /* Not needed for this port - just return! */ + BX lr +// } diff --git a/ports_module/cortex-m3/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex-m3/ac6/module_manager/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..7336051f --- /dev/null +++ b/ports_module/cortex-m3/ac6/module_manager/src/tx_thread_interrupt_control.S @@ -0,0 +1,80 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text 32 + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +@/* _tx_thread_interrupt_control Cortex-M3/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_interrupt_control(UINT new_posture) +// { + .global _tx_thread_interrupt_control + .thumb_func +_tx_thread_interrupt_control: + + // Pickup current interrupt lockout posture. + + MRS r1, PRIMASK // Pickup current interrupt lockout + + // Apply the new interrupt posture. + + MSR PRIMASK, r0 // Apply the new interrupt lockout + MOV r0, r1 // Transfer old to return register + BX lr // Return to caller + +// } diff --git a/ports_module/cortex-m3/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex-m3/ac6/module_manager/src/tx_thread_schedule.S new file mode 100644 index 00000000..b7615814 --- /dev/null +++ b/ports_module/cortex-m3/ac6/module_manager/src/tx_thread_schedule.S @@ -0,0 +1,524 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .global _tx_thread_current_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_system_stack_ptr + .global _tx_thread_preempt_disable + .global _txm_module_manager_memory_fault_handler + .global _txm_module_manager_memory_fault_info +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + .global _tx_execution_thread_enter + .global _tx_execution_thread_exit +#endif + + .text + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule Cortex-M3/MPU/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* _tx_thread_context_restore Restore thread's context */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_schedule(VOID) +// { + .global _tx_thread_schedule + .thumb_func +_tx_thread_schedule: + + /* This function should only ever be called on Cortex-M + from the first schedule request. Subsequent scheduling occurs + from the PendSV handling routines below. */ + + /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ + + MOV r0, #0 // Build value for TX_FALSE + LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag + STR r0, [r2, #0] // Clear preempt disable flag + + /* Enable memory fault registers. */ + + LDR r0, =0xE000ED24 // Build SHCSR address + LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults + STR r1, [r0] // + + /* Enable interrupts */ + + CPSIE i + + /* Enter the scheduler for the first time. */ + + MOV r0, #0x10000000 // Load PENDSVSET bit + MOV r1, #0xE000E000 // Load NVIC base + STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + DSB // Complete all memory accesses + ISB // Flush pipeline + + /* Wait here for the PendSV to take place. */ + +__tx_wait_here: + B __tx_wait_here // Wait for the PendSV to happen +// } + + + /* Memory Exception Handler. */ + .global MemManage_Handler + .global BusFault_Handler + .global UsageFault_Handler + .thumb_func +MemManage_Handler: + .thumb_func +BusFault_Handler: + .thumb_func +UsageFault_Handler: + + CPSID i // Disable interrupts + + /* Now pickup and store all the fault related information. */ + + LDR r12,=_txm_module_manager_memory_fault_info // Pickup fault info struct + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r0] // Pickup the current thread pointer + STR r1, [r12, #0] // Save current thread pointer in fault info structure + LDR r0, =0xE000ED24 // Build SHCSR address + LDR r1, [r0] // Pickup SHCSR + STR r1, [r12, #8] // Save SHCSR + LDR r0, =0xE000ED28 // Build CFSR address + LDR r1, [r0] // Pickup CFSR + STR r1, [r12, #12] // Save CFSR + LDR r0, =0xE000ED34 // Build MMFAR address + LDR r1, [r0] // Pickup MMFAR + STR r1, [r12, #16] // Save MMFAR + LDR r0, =0xE000ED38 // Build BFAR address + LDR r1, [r0] // Pickup BFAR + STR r1, [r12, #20] // Save BFAR + MRS r0, CONTROL // Pickup current CONTROL register + STR r0, [r12, #24] // Save CONTROL + MRS r1, PSP // Pickup thread stack pointer + STR r1, [r12, #28] // Save thread stack pointer + LDR r0, [r1] // Pickup saved r0 + STR r0, [r12, #32] // Save r0 + LDR r0, [r1, #4] // Pickup saved r1 + STR r0, [r12, #36] // Save r1 + STR r2, [r12, #40] // Save r2 + STR r3, [r12, #44] // Save r3 + STR r4, [r12, #48] // Save r4 + STR r5, [r12, #52] // Save r5 + STR r6, [r12, #56] // Save r6 + STR r7, [r12, #60] // Save r7 + STR r8, [r12, #64] // Save r8 + STR r9, [r12, #68] // Save r9 + STR r10,[r12, #72] // Save r10 + STR r11,[r12, #76] // Save r11 + LDR r0, [r1, #16] // Pickup saved r12 + STR r0, [r12, #80] // Save r12 + LDR r0, [r1, #20] // Pickup saved lr + STR r0, [r12, #84] // Save lr + LDR r0, [r1, #24] // Pickup instruction address at point of fault + STR r0, [r12, #4] // Save point of fault + LDR r0, [r1, #28] // Pickup xPSR + STR r0, [r12, #88] // Save xPSR + + MRS r0, CONTROL // Pickup current CONTROL register + BIC r0, r0, #1 // Clear the UNPRIV bit + MSR CONTROL, r0 // Setup new CONTROL register + + LDR r0, =0xE000ED28 // Build the Memory Management Fault Status Register (MMFSR) + LDRB r1, [r0] // Pickup the MMFSR, with the following bit definitions: + // Bit 0 = 1 -> Instruction address violation + // Bit 1 = 1 -> Load/store address violation + // Bit 7 = 1 -> MMFAR is valid + STRB r1, [r0] // Clear the MMFSR + + BL _txm_module_manager_memory_fault_handler // Call memory manager fault handler + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread exit function to indicate the thread is no longer executing. */ + + CPSID i // Disable interrupts + BL _tx_execution_thread_exit // Call the thread exit function + CPSIE i // Enable interrupts +#endif + + MOV r1, #0 // Build NULL value + LDR r0, =_tx_thread_current_ptr // Pickup address of current thread pointer + STR r1, [r0] // Clear current thread pointer + + // Return from MemManage_Handler exception + LDR r0, =0xE000ED04 // Load ICSR + LDR r1, =0x10000000 // Set PENDSVSET bit + STR r1, [r0] // Store ICSR + DSB // Wait for memory access to complete + CPSIE i // Enable interrupts + MOV lr, #0xFFFFFFFD // Load exception return code + BX lr // Return from exception + + + /* Generic context PendSV handler. */ + + .global PendSV_Handler + .thumb_func +PendSV_Handler: + .global __tx_PendSVHandler + .thumb_func +__tx_PendSVHandler: + + /* Get current thread value and new thread pointer. */ + +__tx_ts_handler: + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread exit function to indicate the thread is no longer executing. */ + + CPSID i // Disable interrupts + PUSH {r0, lr} // Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit // Call the thread exit function + POP {r0, lr} // Recover LR + CPSIE i // Enable interrupts +#endif + + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address + MOV r3, #0 // Build NULL value + LDR r1, [r0] // Pickup current thread pointer + + /* Determine if there is a current thread to finish preserving. */ + + CBZ r1, __tx_ts_new // If NULL, skip preservation + + /* Recover PSP and preserve current thread context. */ + + STR r3, [r0] // Set _tx_thread_current_ptr to NULL + MRS r12, PSP // Pickup PSP pointer (thread's stack pointer) + STMDB r12!, {r4-r11} // Save its remaining registers + LDR r4, =_tx_timer_time_slice // Build address of time-slice variable + STMDB r12!, {LR} // Save LR on the stack + + /* Determine if time-slice is active. If it isn't, skip time handling processing. */ + + LDR r5, [r4] // Pickup current time-slice + STR r12, [r1, #8] // Save the thread stack pointer + CBZ r5, __tx_ts_new // If not active, skip processing + + /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ + + STR r5, [r1, #24] // Save current time-slice + + /* Clear the global time-slice. */ + + STR r3, [r4] // Clear time-slice + + /* Executing thread is now completely preserved!!! */ + +__tx_ts_new: + + /* Now we are looking for a new thread to execute! */ + + CPSID i // Disable interrupts + LDR r1, [r2] // Is there another thread ready to execute? + CBZ r1, __tx_ts_wait // No, skip to the wait processing + + /* Yes, another thread is ready for else, make the current thread the new thread. */ + + STR r1, [r0] // Setup the current thread pointer to the new thread + CPSIE i // Enable interrupts + + /* Increment the thread run count. */ + +__tx_ts_restore: + LDR r7, [r1, #4] // Pickup the current thread run count + LDR r4, =_tx_timer_time_slice // Build address of time-slice variable + LDR r5, [r1, #24] // Pickup thread's current time-slice + ADD r7, r7, #1 // Increment the thread run count + STR r7, [r1, #4] // Store the new run count + + /* Setup global time-slice with thread's current time-slice. */ + + STR r5, [r4] // Setup global time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread entry function to indicate the thread is executing. */ + + PUSH {r0, r1} // Save r0 and r1 + BL _tx_execution_thread_enter // Call the thread execution enter function + POP {r0, r1} // Recover r0 and r1 +#endif + + /* Restore the thread context and PSP. */ + + LDR r12, [r1, #8] // Pickup thread's stack pointer + + MRS r5, CONTROL // Pickup current CONTROL register + LDR r4, [r1, #0x98] // Pickup current user mode flag + BIC r5, r5, #1 // Clear the UNPRIV bit + ORR r4, r4, r5 // Build new CONTROL register + MSR CONTROL, r4 // Setup new CONTROL register + + LDR r0, =0xE000ED94 // Build MPU control reg address + MOV r3, #0 // Build disable value + STR r3, [r0] // Disable MPU + LDR r0, [r1, #0x90] // Pickup the module instance pointer + CBZ r0, skip_mpu_setup // Is this thread owned by a module? No, skip MPU setup + LDR r1, [r0, #0x64] // Pickup MPU register[0] + CBZ r1, skip_mpu_setup // Is protection required for this module? No, skip MPU setup + LDR r1, =0xE000ED9C // Build address of MPU base register + + // Use alias registers to quickly load MPU + ADD r0, r0, #100 // Build address of MPU register start in thread control block + LDM r0!,{r2-r9} // Load MPU regions 0-3 + STM r1,{r2-r9} // Store MPU regions 0-3 + LDM r0!,{r2-r9} // Load MPU regions 4-7 + STM r1,{r2-r9} // Store MPU regions 4-7 + LDR r0, =0xE000ED94 // Build MPU control reg address + MOV r1, #5 // Build enable value with background region enabled + STR r1, [r0] // Enable MPU +skip_mpu_setup: + LDMIA r12!, {LR} // Pickup LR + LDMIA r12!, {r4-r11} // Recover thread's registers + MSR PSP, r12 // Setup the thread's stack pointer + + /* Return to thread. */ + + BX lr // Return to thread! + + /* The following is the idle wait processing... in this case, no threads are ready for execution and the + system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts + are disabled to allow use of WFI for waiting for a thread to arrive. */ + +__tx_ts_wait: + CPSID i // Disable interrupts + LDR r1, [r2] // Pickup the next thread to execute pointer + STR r1, [r0] // Store it in the current pointer + CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! +#ifdef TX_ENABLE_WFI + DSB // Ensure no outstanding memory transactions + WFI // Wait for interrupt + ISB // Ensure pipeline is flushed +#endif + CPSIE i // Enable interrupts + B __tx_ts_wait // Loop to continue waiting + + /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are + already in the handler! */ + +__tx_ts_ready: + MOV r7, #0x08000000 // Build clear PendSV value + MOV r8, #0xE000E000 // Build base NVIC address + STR r7, [r8, #0xD04] // Clear any PendSV + + /* Re-enable interrupts and restore new thread. */ + + CPSIE i // Enable interrupts + B __tx_ts_restore // Restore the thread + + + /* SVC Handler. */ + + .global SVC_Handler + .thumb_func +SVC_Handler: + .global __tx_SVCallHandler + .thumb_func +__tx_SVCallHandler: + + MRS r0, PSP // Pickup the PSP stack + LDR r1, [r0, #24] // Pickup the point of interrupt + LDRB r2, [r1, #-2] // Pickup the SVC parameter + + /* Determine which SVC trap we are processing */ + + CMP r2, #1 // Is it the entry into ThreadX? + BNE _tx_thread_user_return // No, return to user mode + + /* At this point we have an SVC 1, which means we are entering + the kernel from a module thread with user mode selected. */ + + LDR r2, =_txm_module_priv // Load address of where we should have come from + CMP r1, r2 // Did we come from user_mode_entry? + IT NE // If no (not equal), then... + BXNE lr // return from where we came. + + LDR r3, [r0, #20] // This is the saved LR + LDR r1, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, [r1] // Pickup current thread pointer + MOV r1, #0 // Build clear value + STR r1, [r2, #0x98] // Clear the current user mode selection for thread + STR r3, [r2, #0xA0] // Save the original LR in thread control block + + /* If there is memory protection, use kernel stack */ + LDR r0, [r2, #0x90] // Load the module instance ptr + LDR r0, [r0, #0x0C] // Load the module property flags + TST r0, #2 // Check if memory protected + BEQ _tx_skip_kernel_stack_enter + + /* Switch to the module thread's kernel stack */ + LDR r0, [r2, #0xA8] // Load the module kernel stack end +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + LDR r1, [r2, #0xA4] // Load the module kernel stack start + LDR r3, [r2, #0xAC] // Load the module kernel stack size + STR r1, [r2, #12] // Set stack start + STR r0, [r2, #16] // Set stack end + STR r3, [r2, #20] // Set stack size +#endif + + MRS r3, PSP // Pickup thread stack pointer + STR r3, [r2, #0xB0] // Save thread stack pointer + + /* Build kernel stack by copying thread stack two registers at a time */ + ADD r3, r3, #32 // Start at bottom of hardware stack + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + + MSR PSP, r0 // Set kernel stack pointer + +_tx_skip_kernel_stack_enter: + MRS r0, CONTROL // Pickup current CONTROL register + BIC r0, r0, #1 // Clear the UNPRIV bit + MSR CONTROL, r0 // Setup new CONTROL register + BX lr // Return to thread + +_tx_thread_user_return: + LDR r2, =_txm_module_user_mode_exit // Load address of where we should have come from + CMP r1, r2 // Did we come from user_mode_exit? + IT NE // If no (not equal), then... + BXNE lr // return from where we came + + LDR r1, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, [r1] // Pickup current thread pointer + LDR r1, [r2, #0x9C] // Pick up user mode + STR r1, [r2, #0x98] // Set the current user mode selection for thread + + /* If there is memory protection, use kernel stack */ + LDR r0, [r2, #0x90] // Load the module instance ptr + LDR r0, [r0, #0x0C] // Load the module property flags + TST r0, #2 // Check if memory protected + BEQ _tx_skip_kernel_stack_exit + +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + LDR r0, [r2, #0xB4] // Load the module thread stack start + LDR r1, [r2, #0xB8] // Load the module thread stack end + LDR r3, [r2, #0xBC] // Load the module thread stack size + STR r0, [r2, #12] // Set stack start + STR r1, [r2, #16] // Set stack end + STR r3, [r2, #20] // Set stack size +#endif + LDR r0, [r2, #0xB0] // Load the module thread stack pointer + MRS r3, PSP // Pickup kernel stack pointer + + /* Copy kernel hardware stack to module thread stack. */ + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + SUB r0, r0, #32 // Subtract 32 to get back to top of stack + MSR PSP, r0 // Set thread stack pointer + + LDR r1, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, [r1] // Pickup current thread pointer + LDR r1, [r2, #0x9C] // Pick up user mode + +_tx_skip_kernel_stack_exit: + MRS r0, CONTROL // Pickup current CONTROL register + ORR r0, r0, r1 // OR in the user mode bit + MSR CONTROL, r0 // Setup new CONTROL register + BX lr // Return to thread + + + /* Kernel entry function from user mode. */ + + .global _txm_module_manager_kernel_dispatch + .align 5 + .syntax unified +// VOID _txm_module_manager_user_mode_entry(VOID) +// { + .global _txm_module_manager_user_mode_entry + .thumb_func +_txm_module_manager_user_mode_entry: + SVC 1 // Enter kernel +_txm_module_priv: + /* At this point, we are out of user mode. The original LR has been saved in the + thread control block. Simply call the kernel dispatch function. */ + BL _txm_module_manager_kernel_dispatch + + /* Pickup the original LR value while still in privileged mode */ + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r3, [r2] // Pickup current thread pointer + LDR lr, [r3, #0xA0] // Pickup saved LR from original call + + SVC 2 // Exit kernel and return to user mode +_txm_module_user_mode_exit: + BX lr // Return to the caller + NOP + NOP + NOP + NOP +// } diff --git a/ports_module/cortex-m3/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex-m3/ac6/module_manager/src/tx_thread_stack_build.S new file mode 100644 index 00000000..548fe34a --- /dev/null +++ b/ports_module/cortex-m3/ac6/module_manager/src/tx_thread_stack_build.S @@ -0,0 +1,135 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .text + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build Cortex-M3/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +// { + .global _tx_thread_stack_build + .thumb_func +_tx_thread_stack_build: + + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-M should look like the following after it is built: + + Stack Top: + LR Interrupted LR (LR at time of PENDSV) + r4 Initial value for r4 + r5 Initial value for r5 + r6 Initial value for r6 + r7 Initial value for r7 + r8 Initial value for r8 + r9 Initial value for r9 + r10 Initial value for r10 + r11 Initial value for r11 + r0 Initial value for r0 (Hardware stack starts here!!) + r1 Initial value for r1 + r2 Initial value for r2 + r3 Initial value for r3 + r12 Initial value for r12 + lr Initial value for lr + pc Initial value for pc + xPSR Initial value for xPSR + + Stack Bottom: (higher memory address) */ + + LDR r2, [r0, #16] // Pickup end of stack area + BIC r2, r2, #0x7 // Align frame + SUB r2, r2, #68 // Subtract frame size + LDR r3, =0xFFFFFFFD // Build initial LR value + STR r3, [r2, #0] // Save on the stack + + /* Actually build the stack frame. */ + + MOV r3, #0 // Build initial register value + STR r3, [r2, #4] // Store initial r4 + STR r3, [r2, #8] // Store initial r5 + STR r3, [r2, #12] // Store initial r6 + STR r3, [r2, #16] // Store initial r7 + STR r3, [r2, #20] // Store initial r8 + STR r3, [r2, #24] // Store initial r9 + STR r3, [r2, #28] // Store initial r10 + STR r3, [r2, #32] // Store initial r11 + + /* Hardware stack follows. */ + + STR r3, [r2, #36] // Store initial r0 + STR r3, [r2, #40] // Store initial r1 + STR r3, [r2, #44] // Store initial r2 + STR r3, [r2, #48] // Store initial r3 + STR r3, [r2, #52] // Store initial r12 + MOV r3, #0xFFFFFFFF // Poison EXC_RETURN value + STR r3, [r2, #56] // Store initial lr + STR r1, [r2, #60] // Store initial pc + MOV r3, #0x01000000 // Only T-bit need be set + STR r3, [r2, #64] // Store initial xPSR + + /* Setup stack pointer. */ + // thread_ptr -> tx_thread_stack_ptr = r2; + + STR r2, [r0, #8] // Save stack pointer in thread's + // control block + BX lr // Return to caller +// } diff --git a/ports_module/cortex-m3/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex-m3/ac6/module_manager/src/tx_thread_system_return.S new file mode 100644 index 00000000..1639bbf2 --- /dev/null +++ b/ports_module/cortex-m3/ac6/module_manager/src/tx_thread_system_return.S @@ -0,0 +1,88 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .text 32 + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return Cortex-M3/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the ThreadX system. Only a */ +/* minimal context is saved since the compiler assumes temp registers */ +/* are going to get slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_system_return(VOID) +// { + .thumb_func + .global _tx_thread_system_return +_tx_thread_system_return: + + /* Return to real scheduler via PendSV. Note that this routine is often + replaced with in-line assembly in tx_port.h to improved performance. */ + + MOV r0, #0x10000000 // Load PENDSVSET bit + MOV r1, #0xE000E000 // Load NVIC base + STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + MRS r0, IPSR // Pickup IPSR + CMP r0, #0 // Is it a thread returning? + BNE _isr_context // If ISR, skip interrupt enable + MRS r1, PRIMASK // Thread context returning, pickup PRIMASK + CPSIE i // Enable interrupts + MSR PRIMASK, r1 // Restore original interrupt posture +_isr_context: + BX lr // Return to caller + +// } diff --git a/ports_module/cortex-m3/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex-m3/ac6/module_manager/src/tx_timer_interrupt.S new file mode 100644 index 00000000..2cbef75d --- /dev/null +++ b/ports_module/cortex-m3/ac6/module_manager/src/tx_timer_interrupt.S @@ -0,0 +1,257 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .global _tx_timer_time_slice + .global _tx_timer_system_clock + .global _tx_timer_current_ptr + .global _tx_timer_list_start + .global _tx_timer_list_end + .global _tx_timer_expired_time_slice + .global _tx_timer_expired + .global _tx_thread_time_slice + .global _tx_timer_expiration_process + + + .text + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt Cortex-M3/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_timer_interrupt(VOID) +// { + .global _tx_timer_interrupt + .thumb_func +_tx_timer_interrupt: + + /* Upon entry to this routine, it is assumed that context save has already + been called, and therefore the compiler scratch registers are available + for use. */ + + /* Increment the system clock. */ + // _tx_timer_system_clock++; + + LDR r1, =_tx_timer_system_clock // Pickup address of system clock + LDR r0, [r1, #0] // Pickup system clock + ADD r0, r0, #1 // Increment system clock + STR r0, [r1, #0] // Store new system clock + + /* Test for time-slice expiration. */ + // if (_tx_timer_time_slice) + // { + + LDR r3, =_tx_timer_time_slice // Pickup address of time-slice + LDR r2, [r3, #0] // Pickup time-slice + CBZ r2, __tx_timer_no_time_slice // Is it non-active? + // Yes, skip time-slice processing + + /* Decrement the time_slice. */ + // _tx_timer_time_slice--; + + SUB r2, r2, #1 // Decrement the time-slice + STR r2, [r3, #0] // Store new time-slice value + + /* Check for expiration. */ + // if (__tx_timer_time_slice == 0) + + CBNZ r2, __tx_timer_no_time_slice // Has it expired? + // No, skip expiration processing + + /* Set the time-slice expired flag. */ + // _tx_timer_expired_time_slice = TX_TRUE; + + LDR r3, =_tx_timer_expired_time_slice // Pickup address of expired flag + MOV r0, #1 // Build expired value + STR r0, [r3, #0] // Set time-slice expiration flag + + // } + +__tx_timer_no_time_slice: + + /* Test for timer expiration. */ + // if (*_tx_timer_current_ptr) + // { + + LDR r1, =_tx_timer_current_ptr // Pickup current timer pointer address + LDR r0, [r1, #0] // Pickup current timer + LDR r2, [r0, #0] // Pickup timer list entry + CBZ r2, __tx_timer_no_timer // Is there anything in the list? + // No, just increment the timer + + /* Set expiration flag. */ + // _tx_timer_expired = TX_TRUE; + + LDR r3, =_tx_timer_expired // Pickup expiration flag address + MOV r2, #1 // Build expired value + STR r2, [r3, #0] // Set expired flag + B __tx_timer_done // Finished timer processing + + // } + // else + // { +__tx_timer_no_timer: + + /* No timer expired, increment the timer pointer. */ + // _tx_timer_current_ptr++; + + ADD r0, r0, #4 // Move to next timer + + /* Check for wrap-around. */ + // if (_tx_timer_current_ptr == _tx_timer_list_end) + + LDR r3, =_tx_timer_list_end // Pickup addr of timer list end + LDR r2, [r3, #0] // Pickup list end + CMP r0, r2 // Are we at list end? + BNE __tx_timer_skip_wrap // No, skip wrap-around logic + + /* Wrap to beginning of list. */ + // _tx_timer_current_ptr = _tx_timer_list_start; + + LDR r3, =_tx_timer_list_start // Pickup addr of timer list start + LDR r0, [r3, #0] // Set current pointer to list start + +__tx_timer_skip_wrap: + + STR r0, [r1, #0] // Store new current timer pointer + // } + +__tx_timer_done: + + + /* See if anything has expired. */ + // if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) + // { + + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of expired flag + LDR r2, [r3, #0] // Pickup time-slice expired flag + CBNZ r2, __tx_something_expired // Did a time-slice expire? + // If non-zero, time-slice expired + LDR r1, =_tx_timer_expired // Pickup addr of other expired flag + LDR r0, [r1, #0] // Pickup timer expired flag + CBZ r0, __tx_timer_nothing_expired // Did a timer expire? + // No, nothing expired + +__tx_something_expired: + + + STMDB sp!, {r0, lr} // Save the lr register on the stack + // and save r0 just to keep 8-byte alignment + + /* Did a timer expire? */ + // if (_tx_timer_expired) + // { + + LDR r1, =_tx_timer_expired // Pickup addr of expired flag + LDR r0, [r1, #0] // Pickup timer expired flag + CBZ r0, __tx_timer_dont_activate // Check for timer expiration + // If not set, skip timer activation + + /* Process timer expiration. */ + // _tx_timer_expiration_process(); + + BL _tx_timer_expiration_process // Call the timer expiration handling routine + + // } +__tx_timer_dont_activate: + + /* Did time slice expire? */ + // if (_tx_timer_expired_time_slice) + // { + + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of time-slice expired + LDR r2, [r3, #0] // Pickup the actual flag + CBZ r2, __tx_timer_not_ts_expiration // See if the flag is set + // No, skip time-slice processing + + /* Time slice interrupted thread. */ + // _tx_thread_time_slice(); + + BL _tx_thread_time_slice // Call time-slice processing + LDR r0, =_tx_thread_preempt_disable // Build address of preempt disable flag + LDR r1, [r0] // Is the preempt disable flag set? + CBNZ r1, __tx_timer_skip_time_slice // Yes, skip the PendSV logic + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r0] // Pickup the current thread pointer + LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address + LDR r3, [r2] // Pickup the execute thread pointer + LDR r0, =0xE000ED04 // Build address of control register + LDR r2, =0x10000000 // Build value for PendSV bit + CMP r1, r3 // Are they the same? + BEQ __tx_timer_skip_time_slice // If the same, there was no time-slice performed + STR r2, [r0] // Not the same, issue the PendSV for preemption +__tx_timer_skip_time_slice: + + // } + +__tx_timer_not_ts_expiration: + + LDMIA sp!, {r0, lr} // Recover lr register (r0 is just there for + // the 8-byte stack alignment + + // } + +__tx_timer_nothing_expired: + + DSB // Complete all memory access + BX lr // Return to caller + +// } diff --git a/ports_module/cortex-m3/ac6/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex-m3/ac6/module_manager/src/txm_module_manager_alignment_adjust.c new file mode 100644 index 00000000..59be7606 --- /dev/null +++ b/ports_module/cortex-m3/ac6/module_manager/src/txm_module_manager_alignment_adjust.c @@ -0,0 +1,399 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_power_of_two_block_size Cortex-M3/MPU/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calculates a power of two size at or immediately above*/ +/* the input size and returns it to the caller. */ +/* */ +/* INPUT */ +/* */ +/* size Block size */ +/* */ +/* OUTPUT */ +/* */ +/* calculated size Rounded up to power of two */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_power_of_two_block_size(ULONG size) +{ + /* Check for 0 size. */ + if(size == 0) + return 0; + + /* Minimum MPU block size is 32. */ + if(size <= 32) + return 32; + + /* Bit twiddling trick to round to next high power of 2 + (if original size is power of 2, it will return original size. Perfect!) */ + size--; + size |= size >> 1; + size |= size >> 2; + size |= size >> 4; + size |= size >> 8; + size |= size >> 16; + size++; + + /* Return a power of 2 size at or above the input size. */ + return(size); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_alignment_adjust Cortex-M3/MPU/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function adjusts the alignment and size of the code and data */ +/* section for a given module implementation. */ +/* */ +/* INPUT */ +/* */ +/* module_preamble Pointer to module preamble */ +/* code_size Size of the code area (updated) */ +/* code_alignment Code area alignment (updated) */ +/* data_size Size of data area (updated) */ +/* data_alignment Data area alignment (updated) */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_power_of_two_block_size Calculate power of two size */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, + ULONG *code_size, + ULONG *code_alignment, + ULONG *data_size, + ULONG *data_alignment) +{ + +ULONG local_code_size; +ULONG local_code_alignment; +ULONG local_data_size; +ULONG local_data_alignment; +ULONG code_block_size; +ULONG data_block_size; +ULONG code_size_accum; +ULONG data_size_accum; + + /* Copy the input parameters into local variables for ease of use. */ + local_code_size = *code_size; + local_code_alignment = *code_alignment; + local_data_size = *data_size; + local_data_alignment = *data_alignment; + + + /* Test for external memory enabled in preamble. */ + if(module_preamble -> txm_module_preamble_property_flags & TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS) + { + /* External/shared memory enabled. TXM_MODULE_MANAGER_CODE_MPU_ENTRIES-1 code entries will be used. */ + if (local_code_size <= (32*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 32 is best. */ + code_block_size = 32; + } + else if (local_code_size <= (64*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 64 is best. */ + code_block_size = 64; + } + else if (local_code_size <= (128*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 128 is best. */ + code_block_size = 128; + } + else if (local_code_size <= (256*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 256 is best. */ + code_block_size = 256; + } + else if (local_code_size <= (512*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 512 is best. */ + code_block_size = 512; + } + else if (local_code_size <= (1024*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 1024 is best. */ + code_block_size = 1024; + } + else if (local_code_size <= (2048*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 2048 is best. */ + code_block_size = 2048; + } + else if (local_code_size <= (4096*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 4096 is best. */ + code_block_size = 4096; + } + else if (local_code_size <= (8192*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 8192 is best. */ + code_block_size = 8192; + } + else if (local_code_size <= (16384*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 16384 is best. */ + code_block_size = 16384; + } + else if (local_code_size <= (32768*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 32768 is best. */ + code_block_size = 32768; + } + else if (local_code_size <= (65536*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 65536 is best. */ + code_block_size = 65536; + } + else if (local_code_size <= (131072*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 131072 is best. */ + code_block_size = 131072; + } + else if (local_code_size <= (262144*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 262144 is best. */ + code_block_size = 262144; + } + else if (local_code_size <= (524288*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 524288 is best. */ + code_block_size = 524288; + } + else if (local_code_size <= (1048576*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 1048576 is best. */ + code_block_size = 1048576; + } + else if (local_code_size <= (2097152*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 2097152 is best. */ + code_block_size = 2097152; + } + else if (local_code_size <= (4194304*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 4194304 is best. */ + code_block_size = 4194304; + } + else + { + /* Just set block size to 32MB just to create an allocation error! */ + code_block_size = 33554432; + } + + /* Calculate the new code size. */ + local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); + + /* Determine if the code block size is greater than the current alignment. If so, use block size + as the alignment. */ + if (code_block_size > local_code_alignment) + local_code_alignment = code_block_size; + + } + else + { + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + local_code_alignment = _txm_power_of_two_block_size(local_code_size) >> 2; + code_size_accum = local_code_alignment + local_code_alignment; + code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); + code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); + local_code_size = code_size_accum; + } + + /* Determine the best data block size, which in our case is the minimal alignment. */ + if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 32 is best. */ + data_block_size = 32; + } + else if (local_data_size <= (64*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 64 is best. */ + data_block_size = 64; + } + else if (local_data_size <= (128*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 128 is best. */ + data_block_size = 128; + } + else if (local_data_size <= (256*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 256 is best. */ + data_block_size = 256; + } + else if (local_data_size <= (512*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 512 is best. */ + data_block_size = 512; + } + else if (local_data_size <= (1024*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 1024 is best. */ + data_block_size = 1024; + } + else if (local_data_size <= (2048*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 2048 is best. */ + data_block_size = 2048; + } + else if (local_data_size <= (4096*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 4096 is best. */ + data_block_size = 4096; + } + else if (local_data_size <= (8192*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 8192 is best. */ + data_block_size = 8192; + } + else if (local_data_size <= (16384*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 16384 is best. */ + data_block_size = 16384; + } + else if (local_data_size <= (32768*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 32768 is best. */ + data_block_size = 32768; + } + else if (local_data_size <= (65536*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 65536 is best. */ + data_block_size = 65536; + } + else if (local_data_size <= (131072*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 131072 is best. */ + data_block_size = 131072; + } + else if (local_data_size <= (262144*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 262144 is best. */ + data_block_size = 262144; + } + else if (local_data_size <= (524288*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 524288 is best. */ + data_block_size = 524288; + } + else if (local_data_size <= (1048576*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 1048576 is best. */ + data_block_size = 1048576; + } + else if (local_data_size <= (2097152*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 2097152 is best. */ + data_block_size = 2097152; + } + else if (local_data_size <= (4194304*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 4194304 is best. */ + data_block_size = 4194304; + } + else + { + /* Just set data block size to 32MB just to create an allocation error! */ + data_block_size = 33554432; + } + + /* Calculate the new data size. */ + data_size_accum = data_block_size; + while(data_size_accum < local_data_size) + { + data_size_accum += data_block_size; + } + local_data_size = data_size_accum; + + /* Determine if the data block size is greater than the current alignment. If so, use block size + as the alignment. */ + if (data_block_size > local_data_alignment) + { + local_data_alignment = data_block_size; + } + + /* Return all the information to the caller. */ + *code_size = local_code_size; + *code_alignment = local_code_alignment; + *data_size = local_data_size; + *data_alignment = local_data_alignment; +} diff --git a/ports_module/cortex-m3/ac6/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex-m3/ac6/module_manager/src/txm_module_manager_external_memory_enable.c new file mode 100644 index 00000000..475fc5a2 --- /dev/null +++ b/ports_module/cortex-m3/ac6/module_manager/src/txm_module_manager_external_memory_enable.c @@ -0,0 +1,182 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_mutex.h" +#include "tx_queue.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_external_memory_enable Cortex-M3/MPU/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates an entry in the MPU table for a shared */ +/* memory space. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* start_address Start address of memory */ +/* length Length of external memory */ +/* attributes Memory attributes (r/w) */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_mutex_get Get protection mutex */ +/* _tx_mutex_put Release protection mutex */ +/* _txm_power_of_two_block_size Round length to power of two */ +/* _txm_module_manager_mm_register_setup Reconfigure MPU registers */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, + VOID *start_address, + ULONG length, + UINT attributes) +{ + +ULONG block_size; +ULONG region_size; +ULONG subregion_bits; +ULONG address; +UINT attributes_check = 0; +TXM_MODULE_PREAMBLE *module_preamble; + + /* Determine if the module manager has not been initialized yet. */ + if (_txm_module_manager_ready != TX_TRUE) + { + /* Module manager has not been initialized. */ + return(TX_NOT_AVAILABLE); + } + + /* Determine if the module is valid. */ + if (module_instance == TX_NULL) + { + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Get module manager protection mutex. */ + _tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER); + + /* Determine if the module instance is valid. */ + if (module_instance -> txm_module_instance_id != TXM_MODULE_ID) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Determine if the module instance is in the loaded state. */ + if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if the module is not ready. */ + return(TX_START_ERROR); + } + + /* Check if preamble shared mem and mem protection property bits are set. */ + module_preamble = module_instance -> txm_module_instance_preamble_ptr; + if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) + != (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if bit not set. */ + return(TXM_MODULE_INVALID_PROPERTIES); + } + + /* Start address and length must adhere to Cortex-M MPU. + The address must align with the block size. */ + + block_size = _txm_power_of_two_block_size(length); + address = (ULONG) start_address; + if(address != (address & ~(block_size - 1))) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return alignment error. */ + return(TXM_MODULE_ALIGNMENT_ERROR); + } + + /* At this point, we have a valid address and block size. + Set up MPU registers. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | 0x10; + + /* Calculate the region size. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + /* Calculate the subregion bits. */ + subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); + + /* Check for valid attributes. */ + if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) + { + attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; + } + + /* Build register with attributes. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX+1] = region_size | subregion_bits | attributes_check | 0x12070001; + + /* Keep track of shared memory address and length in module instance. */ + module_instance -> txm_module_instance_shared_memory_address = address; + module_instance -> txm_module_instance_shared_memory_length = length; + + /* Recalculate MPU settings. */ + _txm_module_manager_mm_register_setup(module_instance); + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/ports_module/cortex-m3/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex-m3/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c new file mode 100644 index 00000000..c670a087 --- /dev/null +++ b/ports_module/cortex-m3/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -0,0 +1,110 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + +/* Define a macro that can be used to allocate global variables useful to + store information about the last fault. This macro is defined in + txm_module_port.h and is usually populated in the assembly language + fault handling prior to the code calling _txm_module_manager_memory_fault_handler. */ + +TXM_MODULE_MANAGER_FAULT_INFO + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_handler Cortex-M3/MPU/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles a fault associated with a memory protected */ +/* module. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_terminate Terminate thread */ +/* */ +/* CALLED BY */ +/* */ +/* Fault handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_memory_fault_handler(VOID) +{ + +TXM_MODULE_INSTANCE *module_instance_ptr; +TX_THREAD *thread_ptr; + + /* Pickup the current thread. */ + thread_ptr = _tx_thread_current_ptr; + + /* Initialize the module instance pointer to NULL. */ + module_instance_ptr = TX_NULL; + + /* Is there a thread? */ + if (thread_ptr) + { + /* Pickup the module instance. */ + module_instance_ptr = thread_ptr -> tx_thread_module_instance_ptr; + + /* Terminate the current thread. */ + _tx_thread_terminate(_tx_thread_current_ptr); + } + + /* Determine if there is a user memory fault notification callback. */ + if (_txm_module_manager_fault_notify) + { + /* Yes, call the user's notification memory fault callback. */ + (_txm_module_manager_fault_notify)(thread_ptr, module_instance_ptr); + } +} diff --git a/ports_module/cortex-m3/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex-m3/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c new file mode 100644 index 00000000..5249a938 --- /dev/null +++ b/ports_module/cortex-m3/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -0,0 +1,84 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the external user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_notify Cortex-M3/MPU/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application callback when/if a memory */ +/* fault occurs. The supplied thread is automatically terminated, but */ +/* any other threads in the same module may still execute. */ +/* */ +/* INPUT */ +/* */ +/* notify_function Memory fault notification */ +/* function, NULL disables. */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +{ + /* Setup notification function. */ + _txm_module_manager_fault_notify = notify_function; + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/ports_module/cortex-m3/ac6/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex-m3/ac6/module_manager/src/txm_module_manager_mm_register_setup.c new file mode 100644 index 00000000..df21aab9 --- /dev/null +++ b/ports_module/cortex-m3/ac6/module_manager/src/txm_module_manager_mm_register_setup.c @@ -0,0 +1,512 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_region_size_get Cortex-M3/MPU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function converts the region size in bytes to the block size */ +/* for the Cortex-M3 MPU specification. */ +/* */ +/* INPUT */ +/* */ +/* block_size Size of the block in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* MPU size specification */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_module_manager_region_size_get(ULONG block_size) +{ + +ULONG return_value; + + /* Process relative to the input block size. */ + if (block_size == 32) + { + return_value = 0x04; + } + else if (block_size == 64) + { + return_value = 0x05; + } + else if (block_size == 128) + { + return_value = 0x06; + } + else if (block_size == 256) + { + return_value = 0x07; + } + else if (block_size == 512) + { + return_value = 0x08; + } + else if (block_size == 1024) + { + return_value = 0x09; + } + else if (block_size == 2048) + { + return_value = 0x0A; + } + else if (block_size == 4096) + { + return_value = 0x0B; + } + else if (block_size == 8192) + { + return_value = 0x0C; + } + else if (block_size == 16384) + { + return_value = 0x0D; + } + else if (block_size == 32768) + { + return_value = 0x0E; + } + else if (block_size == 65536) + { + return_value = 0x0F; + } + else if (block_size == 131072) + { + return_value = 0x10; + } + else if (block_size == 262144) + { + return_value = 0x11; + } + else if (block_size == 524288) + { + return_value = 0x12; + } + else if (block_size == 1048576) + { + return_value = 0x13; + } + else if (block_size == 2097152) + { + return_value = 0x14; + } + else + { + /* Max 4MB MPU pages for modules. */ + return_value = 0x15; + } + + return(return_value); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_calculate_srd_bits Cortex-M3/MPU/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calculates the SRD bits that need to be set to */ +/* protect "length" bytes in a block. */ +/* */ +/* INPUT */ +/* */ +/* block_size Size of the block in bytes */ +/* length Actual length in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* SRD bits to be OR'ed with region attribute register. */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) +{ + +ULONG srd_bits = 0; +UINT srd_bit_index; + + /* length is smaller than block_size, set SRD bits if block_size is 256 or more. */ + if((block_size >= 256) && (length < block_size)) + { + /* Divide block_size by 8 by shifting right 3. Result is size of subregion. */ + block_size = block_size >> 3; + + /* Set SRD index into attribute register. */ + srd_bit_index = 8; + + /* If subregion overlaps length, move to the next subregion. */ + while(length > block_size) + { + length = length - block_size; + srd_bit_index++; + } + /* Check for a portion of code remaining. */ + if(length) + { + srd_bit_index++; + } + + /* Set unused subregion bits. */ + while(srd_bit_index < 16) + { + srd_bits = srd_bits | (0x1 << srd_bit_index); + srd_bit_index++; + } + } + + return(srd_bits); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_mm_register_setup Cortex-M3/MPU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets up the Cortex-M3 MPU register definitions based */ +/* on the module's memory characteristics. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* */ +/* OUTPUT */ +/* */ +/* MPU specifications for module in module_instance */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_manager_region_size_get */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_thread_create */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) +{ + +ULONG code_address; +ULONG code_size; +ULONG data_address; +ULONG data_size; +ULONG start_stop_stack_size; +ULONG callback_stack_size; +ULONG block_size; +ULONG base_address_register; +ULONG base_attribute_register; +ULONG region_size; +ULONG srd_bits = 0; +UINT mpu_register = 0; +UINT mpu_table_index; +UINT i; + + + /* Setup the first region for the ThreadX trampoline code. */ + /* Set base register to user mode entry, which is guaranteed to be at least 32-byte aligned. */ + base_address_register = (ULONG) _txm_module_manager_user_mode_entry; + + /* Mask address to proper range, region 0, set Valid bit. */ + base_address_register = (base_address_register & 0xFFFFFFE0) | mpu_register | 0x10; + module_instance -> txm_module_instance_mpu_registers[0] = base_address_register; + + /* Attributes: read only, write-back, shareable, size 32 bytes, region enabled. */ + module_instance -> txm_module_instance_mpu_registers[1] = 0x06070009; + + /* Initialize the MPU register. */ + mpu_register = 1; + + /* Initialize the MPU table index. */ + mpu_table_index = 2; + + /* Setup values for code area. */ + code_address = (ULONG) module_instance -> txm_module_instance_code_start; + code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; + + /* Check if shared memory was set up. If so, only 3 entries are available for + code protection. If not set up, 4 code entries are available. */ + if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] == 0) + { + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + + /* Now loop through to setup MPU protection for the code area. */ + for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES; i++) + { + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + if (i < 2) + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + } + + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ + else if (i == 2) + { + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size) >> 1; + } + + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + else + { + /* Calculate remaining space. */ + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + + /* Build the base address register. */ + base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Build the base attribute register. */ + base_attribute_register = region_size | srd_bits | 0x06070001; + + /* Setup the MPU Base Address Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; + + /* Setup the MPU Base Attribute Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; + + /* Adjust the code address. */ + code_address = code_address + block_size; + + /* Move MPU table index. */ + mpu_table_index = mpu_table_index + 2; + + /* Increment the MPU register index. */ + mpu_register++; + } + } + + /* Only 3 code entries available. */ + else + { + /* Calculate block size, one code entry taken up by shared memory. */ + block_size = _txm_power_of_two_block_size(code_size / (TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)); + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Now loop through to setup MPU protection for the code area. */ + for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) + { + /* Build the base address register. */ + base_address_register = code_address & ~(block_size - 1) | mpu_register | 0x10; + + /* Check if SRD bits need to be set. */ + if (code_size < block_size) + { + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + + /* Build the base attribute register. */ + base_attribute_register = region_size | srd_bits | 0x06070000; + + /* Is there still some code? If so set the region enable bit. */ + if (code_size) + { + /* Set the region enable bit. */ + base_attribute_register = base_attribute_register | 0x1; + } + /* Setup the MPU Base Address Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; + + /* Setup the MPU Base Attribute Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; + + /* Adjust the code address. */ + code_address = code_address + block_size; + + /* Decrement the code size. */ + if (code_size > block_size) + { + code_size = code_size - block_size; + } + else + { + code_size = 0; + } + + /* Move MPU table index. */ + mpu_table_index = mpu_table_index + 2; + + /* Increment the MPU register index. */ + mpu_register++; + } + + /* Adjust indeces to pass over the shared memory entry. */ + /* Move MPU table index. */ + mpu_table_index = mpu_table_index + 2; + + /* Increment the MPU register index. */ + mpu_register++; + } + + /* Setup values for data area. */ + data_address = (ULONG) module_instance -> txm_module_instance_data_start; + + /* Adjust the size of the module elements to be aligned to the default alignment. We do this + so that when we partition the allocated memory, we can simply place these regions right beside + each other without having to align their pointers. Note this only works when they all have + the same alignment. */ + + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; + start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; + callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; + + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + /* Update the data size to include thread stacks. */ + data_size = data_size + start_stop_stack_size + callback_stack_size; + + block_size = _txm_power_of_two_block_size(data_size / TXM_MODULE_MANAGER_DATA_MPU_ENTRIES); + + /* Reset SRD bitfield. */ + srd_bits = 0; + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Now loop through to setup MPU protection for the data area. */ + for (i = 0; i < TXM_MODULE_MANAGER_DATA_MPU_ENTRIES; i++) + { + /* Build the base address register. */ + base_address_register = (data_address & ~(block_size - 1)) | mpu_register | 0x10; + + /* Check if SRD bits need to be set. */ + if (data_size < block_size) + { + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + } + + /* Build the base attribute register. */ + base_attribute_register = region_size | srd_bits | 0x13070000; + + /* Is there still some data? If so set the region enable bit. */ + if (data_size) + { + /* Set the region enable bit. */ + base_attribute_register = base_attribute_register | 0x1; + } + + /* Setup the MPU Base Address Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; + + /* Setup the MPU Base Attribute Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; + + /* Adjust the data address. */ + data_address = data_address + block_size; + + /* Decrement the data size. */ + if (data_size > block_size) + { + data_size = data_size - block_size; + } + else + { + data_size = 0; + } + + /* Move MPU table index. */ + mpu_table_index = mpu_table_index + 2; + + /* Increment the MPU register index. */ + mpu_register++; + } +} diff --git a/ports_module/cortex-m3/ac6/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex-m3/ac6/module_manager/src/txm_module_manager_thread_stack_build.S new file mode 100644 index 00000000..98982a1f --- /dev/null +++ b/ports_module/cortex-m3/ac6/module_manager/src/txm_module_manager_thread_stack_build.S @@ -0,0 +1,141 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .align 4 + .syntax unified + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_thread_stack_build Cortex-M3/MPU/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread */ +/* function_ptr Pointer to shell function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +// { + .global _txm_module_manager_thread_stack_build + .thumb_func +_txm_module_manager_thread_stack_build: + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-M should look like the following after it is built: + + Stack Top: + LR Interrupted LR (LR at time of PENDSV) + r4 Initial value for r4 + r5 Initial value for r5 + r6 Initial value for r6 + r7 Initial value for r7 + r8 Initial value for r8 + r9 Initial value for r9 + r10 Initial value for r10 + r11 Initial value for r11 + r0 Initial value for r0 (Hardware stack starts here!!) + r1 Initial value for r1 + r2 Initial value for r2 + r3 Initial value for r3 + r12 Initial value for r12 + lr Initial value for lr + pc Initial value for pc + xPSR Initial value for xPSR + + Stack Bottom: (higher memory address) */ + + LDR r2, [r0, #16] // Pickup end of stack area + BIC r2, r2, #0x7 // Align frame + SUB r2, r2, #68 // Subtract frame size + LDR r3, =0xFFFFFFFD // Build initial LR value + STR r3, [r2, #0] // Save on the stack + + /* Actually build the stack frame. */ + + MOV r3, #0 // Build initial register value + STR r3, [r2, #4] // Store initial r4 + STR r3, [r2, #8] // Store initial r5 + STR r3, [r2, #12] // Store initial r6 + STR r3, [r2, #16] // Store initial r7 + STR r3, [r2, #20] // Store initial r8 + STR r3, [r2, #28] // Store initial r10 + STR r3, [r2, #32] // Store initial r11 + + /* Hardware stack follows. */ + + STR r0, [r2, #36] // Store initial r0, which is the thread control block + + LDR r3, [r0, #8] // Pickup thread entry info pointer,which is in the stack pointer position of the thread control block. + // It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this + // function with the actual, initial stack pointer. + STR r3, [r2, #40] // Store initial r1, which is the module entry information. + LDR r3, [r3, #8] // Pickup data base register from the module information + STR r3, [r2, #24] // Store initial r9 (data base register) + MOV r3, #0 // Clear r3 again + + STR r3, [r2, #44] // Store initial r2 + STR r3, [r2, #48] // Store initial r3 + STR r3, [r2, #52] // Store initial r12 + MOV r3, #0xFFFFFFFF // Poison EXC_RETURN value + STR r3, [r2, #56] // Store initial lr + STR r1, [r2, #60] // Store initial pc + MOV r3, #0x01000000 // Only T-bit need be set + STR r3, [r2, #64] // Store initial xPSR + + /* Setup stack pointer. */ + // thread_ptr -> tx_thread_stack_ptr = r2; + + STR r2, [r0, #8] // Save stack pointer in thread's control block + BX lr // Return to caller +// } + diff --git a/ports_module/cortex-m3/gnu/example_build/build_all.bat b/ports_module/cortex-m3/gnu/example_build/build_all.bat new file mode 100644 index 00000000..70c43ec3 --- /dev/null +++ b/ports_module/cortex-m3/gnu/example_build/build_all.bat @@ -0,0 +1,5 @@ + +call build_threadx.bat +call build_threadx_module_library.bat +call build_threadx_module_sample.bat +call build_threadx_module_manager_sample.bat \ No newline at end of file diff --git a/ports_module/cortex-m3/gnu/example_build/build_threadx.bat b/ports_module/cortex-m3/gnu/example_build/build_threadx.bat new file mode 100644 index 00000000..9bc2956c --- /dev/null +++ b/ports_module/cortex-m3/gnu/example_build/build_threadx.bat @@ -0,0 +1,280 @@ +del tx.a +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb tx_initialize_low_level.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb ..\module_manager\src\tx_thread_stack_build.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb ..\module_manager\src\tx_thread_schedule.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb ..\module_manager\src\tx_thread_system_return.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb ..\module_manager\src\tx_thread_context_save.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb ..\module_manager\src\tx_thread_context_restore.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb ..\module_manager\src\tx_thread_interrupt_control.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb ..\module_manager\src\tx_timer_interrupt.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb ..\module_manager\src\txm_module_manager_thread_stack_build.S + +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_pool_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_pool_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_pool_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_pool_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_pool_search.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_event_flags_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_event_flags_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_event_flags_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_event_flags_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_event_flags_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc 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+arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_semaphore_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_semaphore_put_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_thread_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_thread_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_thread_entry_exit_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_thread_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_thread_preemption_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_thread_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_thread_relinquish.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_thread_reset.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_thread_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_thread_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_thread_terminate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_thread_time_slice_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_thread_wait_abort.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_timer_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_timer_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_timer_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_timer_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_timer_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_timer_info_get.c + +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\module_manager\src\txm_module_manager_alignment_adjust.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_application_request.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_callback_request.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_event_flags_notify_trampoline.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\module_manager\src\txm_module_manager_external_memory_enable.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_file_load.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_in_place_load.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_internal_load.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_kernel_dispatch.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_maximum_module_priority_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\module_manager\src\txm_module_manager_memory_fault_handler.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\module_manager\src\txm_module_manager_memory_fault_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_memory_load.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_object_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_object_deallocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_object_pointer_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_object_pointer_get_extended.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_object_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_properties_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_queue_notify_trampoline.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_semaphore_notify_trampoline.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\module_manager\src\txm_module_manager_mm_register_setup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_start.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_stop.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_thread_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_thread_notify_trampoline.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_thread_reset.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_timer_notify_trampoline.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_unload.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_util.c + + +arm-none-eabi-ar -r tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o +arm-none-eabi-ar -r tx.a tx_thread_interrupt_control.o tx_initialize_low_level.o +arm-none-eabi-ar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o +arm-none-eabi-ar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o +arm-none-eabi-ar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o +arm-none-eabi-ar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o +arm-none-eabi-ar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o +arm-none-eabi-ar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o +arm-none-eabi-ar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o +arm-none-eabi-ar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o +arm-none-eabi-ar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o +arm-none-eabi-ar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o +arm-none-eabi-ar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o +arm-none-eabi-ar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o +arm-none-eabi-ar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o +arm-none-eabi-ar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o +arm-none-eabi-ar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o +arm-none-eabi-ar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o +arm-none-eabi-ar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o +arm-none-eabi-ar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o +arm-none-eabi-ar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o +arm-none-eabi-ar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o +arm-none-eabi-ar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o +arm-none-eabi-ar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o +arm-none-eabi-ar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o +arm-none-eabi-ar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o +arm-none-eabi-ar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o +arm-none-eabi-ar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o +arm-none-eabi-ar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o +arm-none-eabi-ar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o +arm-none-eabi-ar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o +arm-none-eabi-ar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o +arm-none-eabi-ar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o +arm-none-eabi-ar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o +arm-none-eabi-ar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o + +arm-none-eabi-ar -r tx.a txm_module_manager_alignment_adjust.o txm_module_manager_application_request.o txm_module_manager_callback_request.o +arm-none-eabi-ar -r tx.a txm_module_manager_event_flags_notify_trampoline.o txm_module_manager_external_memory_enable.o txm_module_manager_file_load.o +arm-none-eabi-ar -r tx.a txm_module_manager_in_place_load.o txm_module_manager_initialize.o +arm-none-eabi-ar -r tx.a txm_module_manager_kernel_dispatch.o txm_module_manager_maximum_module_priority_set.o txm_module_manager_memory_fault_handler.o +arm-none-eabi-ar -r tx.a txm_module_manager_memory_fault_notify.o txm_module_manager_memory_load.o txm_module_manager_object_pointer_get.o +arm-none-eabi-ar -r tx.a txm_module_manager_object_pool_create.o txm_module_manager_queue_notify_trampoline.o txm_module_manager_semaphore_notify_trampoline.o +arm-none-eabi-ar -r tx.a txm_module_manager_mm_register_setup.o txm_module_manager_start.o txm_module_manager_stop.o +arm-none-eabi-ar -r tx.a txm_module_manager_thread_create.o txm_module_manager_thread_notify_trampoline.o txm_module_manager_thread_reset.o +arm-none-eabi-ar -r tx.a txm_module_manager_timer_notify_trampoline.o txm_module_manager_unload.o txm_module_manager_thread_stack_build.o +arm-none-eabi-ar -r tx.a txm_module_manager_internal_load.o +arm-none-eabi-ar -r tx.a txm_module_manager_object_allocate.o +arm-none-eabi-ar -r tx.a txm_module_manager_object_deallocate.o +arm-none-eabi-ar -r tx.a txm_module_manager_object_pointer_get_extended.o +arm-none-eabi-ar -r tx.a txm_module_manager_properties_get.o +arm-none-eabi-ar -r tx.a txm_module_manager_util.o \ No newline at end of file diff --git a/ports_module/cortex-m3/gnu/example_build/build_threadx_module_library.bat b/ports_module/cortex-m3/gnu/example_build/build_threadx_module_library.bat new file mode 100644 index 00000000..d0bbae23 --- /dev/null +++ b/ports_module/cortex-m3/gnu/example_build/build_threadx_module_library.bat @@ -0,0 +1,118 @@ +del txm.a + +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_set_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_application_request.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_callback_request_thread_entry.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_object_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_object_deallocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_object_pointer_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\module_lib\src\txm_module_thread_shell_entry.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_thread_system_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_flush.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_front_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_receive.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_send_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_ceiling_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_put_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_entry_exit_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_identify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_interrupt_control.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_preemption_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_relinquish.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_reset.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_sleep.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_stack_error_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_terminate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_time_slice_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_wait_abort.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_time_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_time_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_buffer_full_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_disable.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_enable.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_event_filter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_event_unfilter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_isr_enter_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_isr_exit_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_user_event_insert.c + +arm-none-eabi-ar -r txm.a txm_block_allocate.o txm_block_pool_create.o txm_block_pool_delete.o txm_block_pool_info_get.o txm_block_pool_performance_info_get.o txm_block_pool_performance_system_info_get.o +arm-none-eabi-ar -r txm.a txm_block_pool_prioritize.o txm_block_release.o +arm-none-eabi-ar -r txm.a txm_byte_allocate.o txm_byte_pool_create.o txm_byte_pool_delete.o txm_byte_pool_info_get.o txm_byte_pool_performance_info_get.o txm_byte_pool_performance_system_info_get.o +arm-none-eabi-ar -r txm.a txm_byte_pool_prioritize.o txm_byte_release.o +arm-none-eabi-ar -r txm.a txm_event_flags_create.o txm_event_flags_delete.o txm_event_flags_get.o txm_event_flags_info_get.o txm_event_flags_performance_info_get.o txm_event_flags_performance_system_info_get.o +arm-none-eabi-ar -r txm.a txm_event_flags_set.o txm_event_flags_set_notify.o +arm-none-eabi-ar -r txm.a txm_module_application_request.o txm_module_callback_request_thread_entry.o txm_module_object_allocate.o txm_module_object_deallocate.o txm_module_object_pointer_get.o txm_module_thread_shell_entry.o txm_module_thread_system_suspend.o +arm-none-eabi-ar -r txm.a txm_mutex_create.o txm_mutex_delete.o txm_mutex_get.o txm_mutex_info_get.o txm_mutex_performance_info_get.o txm_mutex_performance_system_info_get.o txm_mutex_prioritize.o txm_mutex_put.o +arm-none-eabi-ar -r txm.a txm_queue_create.o txm_queue_delete.o txm_queue_flush.o txm_queue_front_send.o txm_queue_info_get.o txm_queue_performance_info_get.o txm_queue_performance_system_info_get.o +arm-none-eabi-ar -r txm.a txm_queue_prioritize.o txm_queue_receive.o txm_queue_send.o txm_queue_send_notify.o +arm-none-eabi-ar -r txm.a txm_semaphore_ceiling_put.o txm_semaphore_create.o txm_semaphore_delete.o txm_semaphore_get.o txm_semaphore_info_get.o txm_semaphore_performance_info_get.o txm_semaphore_performance_system_info_get.o +arm-none-eabi-ar -r txm.a txm_semaphore_prioritize.o txm_semaphore_put.o txm_semaphore_put_notify.o +arm-none-eabi-ar -r txm.a txm_thread_create.o txm_thread_delete.o txm_thread_entry_exit_notify.o txm_thread_identify.o txm_thread_info_get.o txm_thread_interrupt_control.o txm_thread_performance_info_get.o +arm-none-eabi-ar -r txm.a txm_thread_performance_system_info_get.o txm_thread_preemption_change.o txm_thread_priority_change.o txm_thread_relinquish.o txm_thread_reset.o txm_thread_resume.o +arm-none-eabi-ar -r txm.a txm_thread_sleep.o txm_thread_stack_error_notify.o txm_thread_suspend.o txm_thread_terminate.o txm_thread_time_slice_change.o txm_thread_wait_abort.o +arm-none-eabi-ar -r txm.a txm_time_get.o txm_time_set.o +arm-none-eabi-ar -r txm.a txm_timer_activate.o txm_timer_change.o txm_timer_create.o txm_timer_deactivate.o txm_timer_delete.o txm_timer_info_get.o txm_timer_performance_info_get.o txm_timer_performance_system_info_get.o +arm-none-eabi-ar -r txm.a txm_trace_buffer_full_notify.o txm_trace_disable.o txm_trace_enable.o txm_trace_event_filter.o txm_trace_event_unfilter.o txm_trace_isr_enter_insert.o txm_trace_isr_exit_insert.o txm_trace_user_event_insert.o diff --git a/ports_module/cortex-m3/gnu/example_build/build_threadx_module_manager_sample.bat b/ports_module/cortex-m3/gnu/example_build/build_threadx_module_manager_sample.bat new file mode 100644 index 00000000..f2a5a9ba --- /dev/null +++ b/ports_module/cortex-m3/gnu/example_build/build_threadx_module_manager_sample.bat @@ -0,0 +1,4 @@ +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc sample_threadx_module_manager.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb tx_simulator_startup.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb cortexm_crt0.S +arm-none-eabi-ld -A cortex-m3 -ereset_handler -T sample_threadx.ld tx_simulator_startup.o cortexm_crt0.o sample_threadx_module_manager.o tx.a libc.a -o sample_threadx_module_manager.axf -M > sample_threadx_module_manager.map diff --git a/ports_module/cortex-m3/gnu/example_build/build_threadx_module_sample.bat b/ports_module/cortex-m3/gnu/example_build/build_threadx_module_sample.bat new file mode 100644 index 00000000..75214cdf --- /dev/null +++ b/ports_module/cortex-m3/gnu/example_build/build_threadx_module_sample.bat @@ -0,0 +1,5 @@ +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -fpie -fno-plt -mpic-data-is-text-relative -msingle-pic-base txm_module_preamble.s +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -fpie -fno-plt -mpic-data-is-text-relative -msingle-pic-base gcc_setup.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -fpie -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc sample_threadx_module.c +arm-none-eabi-ld -A cortex-m3 -T sample_threadx_module.ld txm_module_preamble.o gcc_setup.o sample_threadx_module.o -e _txm_module_thread_shell_entry txm.a -o sample_threadx_module.axf -M > sample_threadx_module.map + diff --git a/ports_module/cortex-m3/gnu/example_build/cortexm_crt0.s b/ports_module/cortex-m3/gnu/example_build/cortexm_crt0.s new file mode 100644 index 00000000..d4cb1636 --- /dev/null +++ b/ports_module/cortex-m3/gnu/example_build/cortexm_crt0.s @@ -0,0 +1,127 @@ + .global _start + .extern main + + + .section .init, "ax" + .code 16 + .align 2 + .thumb_func + + +_start: + CPSID i + ldr r1, =__stack_end__ + mov sp, r1 + + + /* Copy initialised sections into RAM if required. */ + ldr r0, =__data_load_start__ + ldr r1, =__data_start__ + ldr r2, =__data_end__ + bl crt0_memory_copy + ldr r0, =__text_load_start__ + ldr r1, =__text_start__ + ldr r2, =__text_end__ + bl crt0_memory_copy + ldr r0, =__fast_load_start__ + ldr r1, =__fast_start__ + ldr r2, =__fast_end__ + bl crt0_memory_copy + ldr r0, =__ctors_load_start__ + ldr r1, =__ctors_start__ + ldr r2, =__ctors_end__ + bl crt0_memory_copy + ldr r0, =__dtors_load_start__ + ldr r1, =__dtors_start__ + ldr r2, =__dtors_end__ + bl crt0_memory_copy + ldr r0, =__rodata_load_start__ + ldr r1, =__rodata_start__ + ldr r2, =__rodata_end__ + bl crt0_memory_copy + + + /* Zero bss. */ + ldr r0, =__bss_start__ + ldr r1, =__bss_end__ + mov r2, #0 + bl crt0_memory_set + + + /* Setup heap - not recommended for Threadx but here for compatibility reasons */ + ldr r0, = __heap_start__ + ldr r1, = __heap_end__ + sub r1, r1, r0 + mov r2, #0 + str r2, [r0] + add r0, r0, #4 + str r1, [r0] + + + /* constructors in case of using C++ */ + ldr r0, =__ctors_start__ + ldr r1, =__ctors_end__ +crt0_ctor_loop: + cmp r0, r1 + beq crt0_ctor_end + ldr r2, [r0] + add r0, #4 + push {r0-r1} + blx r2 + pop {r0-r1} + b crt0_ctor_loop +crt0_ctor_end: + + + /* Setup call frame for main() */ + mov r0, #0 + mov lr, r0 + mov r12, sp + + +start: + /* Jump to main() */ + mov r0, #0 + mov r1, #0 + ldr r2, =main + blx r2 + /* when main returns, loop forever. */ +crt0_exit_loop: + b crt0_exit_loop + + + + /* Startup helper functions. */ + + +crt0_memory_copy: + cmp r0, r1 + beq memory_copy_done + sub r2, r2, r1 + beq memory_copy_done +memory_copy_loop: + ldrb r3, [r0] + add r0, r0, #1 + strb r3, [r1] + add r1, r1, #1 + sub r2, r2, #1 + bne memory_copy_loop +memory_copy_done: + bx lr + + +crt0_memory_set: + cmp r0, r1 + beq memory_set_done + strb r2, [r0] + add r0, r0, #1 + b crt0_memory_set +memory_set_done: + bx lr + + + /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */ + .section .stack, "wa", %nobits + .section .stack_process, "wa", %nobits + .section .heap, "wa", %nobits + \ No newline at end of file diff --git a/ports_module/cortex-m3/gnu/example_build/gcc_setup.s b/ports_module/cortex-m3/gnu/example_build/gcc_setup.s new file mode 100644 index 00000000..d7c61892 --- /dev/null +++ b/ports_module/cortex-m3/gnu/example_build/gcc_setup.s @@ -0,0 +1,127 @@ + + .text + .align 4 + .syntax unified + + .global _gcc_setup + .thumb_func +_gcc_setup: + + STMDB sp!, {r3, r4, r5, r6, r7, lr} // Store other preserved registers + + ldr r3, =__FLASH_segment_start__ + ldr r4, =__RAM_segment_start__ + mov r5,r0 + + /* Copy GOT table. */ + + ldr r0, =__got_load_start__ + sub r0,r0,r3 + add r0,r0,r5 + ldr r1, =__new_got_start__ + sub r1,r1, r4 + add r1,r1,r9 + ldr r2, =__new_got_end__ + sub r2,r2,r4 + add r2,r2,r9 + +new_got_setup: + cmp r1, r2 // See if there are more GOT entries + beq got_setup_done // No, done with GOT setup + ldr r6, [r0] // Pickup current GOT entry + cmp r6, #0 // Is it 0? + beq address_built // Yes, just skip the adjustment + cmp r6, r4 // Is it in the code or data area? + blt flash_area // If less than, it is a code address + sub r6, r6, r4 // Compute offset of data area + add r6, r6, r9 // Build address based on the loaded data address + b address_built // Finished building address +flash_area: + sub r6, r6, r3 // Compute offset of code area + add r6, r6, r5 // Build address based on the loaded code address +address_built: + str r6, [r1] // Store in new GOT table + add r0, r0, #4 // Move to next entry + add r1, r1, #4 // + b new_got_setup // Continue at the top of the loop +got_setup_done: + + + /* Copy initialised sections into RAM if required. */ + + ldr r0, =__data_load_start__ + sub r0,r0,r3 + add r0,r0,r5 + ldr r1, =__data_start__ + sub r1,r1, r4 + add r1,r1,r9 + ldr r2, =__data_end__ + sub r2,r2,r4 + add r2,r2,r9 + bl crt0_memory_copy + + /* Zero bss. */ + + ldr r0, =__bss_start__ + sub r0,r0,r4 + add r0,r0,r9 + ldr r1, =__bss_end__ + sub r1,r1,r4 + add r1,r1,r9 + mov r2, #0 + bl crt0_memory_set + + + /* Setup heap - not recommended for Threadx but here for compatibility reasons */ + + ldr r0, =__heap_start__ + sub r0,r0,r4 + add r0,r0,r9 + ldr r1, =__heap_end__ + sub r1,r1,r4 + add r1,r1,r9 + sub r1,r1,r0 + mov r2, #0 + str r2, [r0] + add r0, r0, #4 + str r1, [r0] + + LDMIA sp!, {r3, r4, r5, r6, r7, lr} // Store other preserved registers + bx lr // Return to caller + + .align 4 + + /* Startup helper functions. */ + + .thumb_func +crt0_memory_copy: + + cmp r0, r1 + beq memory_copy_done + cmp r2, r1 + beq memory_copy_done + sub r2, r2, r1 +memory_copy_loop: + ldrb r3, [r0] + add r0, r0, #1 + strb r3, [r1] + add r1, r1, #1 + sub r2, r2, #1 + cmp r2, #0 + bne memory_copy_loop +memory_copy_done: + bx lr + + .thumb_func +crt0_memory_set: + cmp r0, r1 + beq memory_set_done + strb r2, [r0] + add r0, r0, #1 + b crt0_memory_set +memory_set_done: + bx lr + + /* Setup attibutes of heap section so it doesn't take up room in the elf file */ + .section .heap, "wa", %nobits + \ No newline at end of file diff --git a/ports_module/cortex-m3/gnu/example_build/sample_threadx.ld b/ports_module/cortex-m3/gnu/example_build/sample_threadx.ld new file mode 100644 index 00000000..4a7ce31d --- /dev/null +++ b/ports_module/cortex-m3/gnu/example_build/sample_threadx.ld @@ -0,0 +1,206 @@ +MEMORY +{ + UNPLACED_SECTIONS (wx) : ORIGIN = 0x100000000, LENGTH = 0 + CM3_System_Control_Space (wx) : ORIGIN = 0xe000e000, LENGTH = 0x00001000 + AHB_Peripherals (wx) : ORIGIN = 0x50000000, LENGTH = 0x00200000 + APB1_Peripherals (wx) : ORIGIN = 0x40080000, LENGTH = 0x00080000 + APB0_Peripherals (wx) : ORIGIN = 0x40000000, LENGTH = 0x00080000 + GPIO (wx) : ORIGIN = 0x2009c000, LENGTH = 0x00004000 + AHBSRAM1 (wx) : ORIGIN = 0x20080000, LENGTH = 0x00004000 + AHBSRAM0 (wx) : ORIGIN = 0x2007c000, LENGTH = 0x00004000 + RAM (wx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 +} + + +SECTIONS +{ + __CM3_System_Control_Space_segment_start__ = 0xe000e000; + __CM3_System_Control_Space_segment_end__ = 0xe000f000; + __AHB_Peripherals_segment_start__ = 0x50000000; + __AHB_Peripherals_segment_end__ = 0x50200000; + __APB1_Peripherals_segment_start__ = 0x40080000; + __APB1_Peripherals_segment_end__ = 0x40100000; + __APB0_Peripherals_segment_start__ = 0x40000000; + __APB0_Peripherals_segment_end__ = 0x40080000; + __GPIO_segment_start__ = 0x2009c000; + __GPIO_segment_end__ = 0x200a0000; + __AHBSRAM1_segment_start__ = 0x20080000; + __AHBSRAM1_segment_end__ = 0x20084000; + __AHBSRAM0_segment_start__ = 0x2007c000; + __AHBSRAM0_segment_end__ = 0x20080000; + __RAM_segment_start__ = 0x20000000; + __RAM_segment_end__ = 0x20008000; + __FLASH_segment_start__ = 0x00000000; + __FLASH_segment_end__ = 0x00030000; + + __STACKSIZE__ = 1024; + __STACKSIZE_PROCESS__ = 0; + __STACKSIZE_IRQ__ = 0; + __STACKSIZE_FIQ__ = 0; + __STACKSIZE_SVC__ = 0; + __STACKSIZE_ABT__ = 0; + __STACKSIZE_UND__ = 0; + __HEAPSIZE__ = 128; + + __vectors_load_start__ = __FLASH_segment_start__; + .vectors __FLASH_segment_start__ : AT(__FLASH_segment_start__) + { + __vectors_start__ = .; + *(.vectors .vectors.*) + } + __vectors_end__ = __vectors_start__ + SIZEOF(.vectors); + + . = ASSERT(__vectors_end__ >= __FLASH_segment_start__ && __vectors_end__ <= (__FLASH_segment_start__ + 0x00030000) , "error: .vectors is too large to fit in FLASH memory segment"); + + __init_load_start__ = ALIGN(__vectors_end__ , 4); + .init ALIGN(__vectors_end__ , 4) : AT(ALIGN(__vectors_end__ , 4)) + { + __init_start__ = .; + *(.init .init.*) + } + __init_end__ = __init_start__ + SIZEOF(.init); + + . = ASSERT(__init_end__ >= __FLASH_segment_start__ && __init_end__ <= (__FLASH_segment_start__ + 0x00030000) , "error: .init is too large to fit in FLASH memory segment"); + + __text_load_start__ = ALIGN(__init_end__ , 4); + .text ALIGN(__init_end__ , 4) : AT(ALIGN(__init_end__ , 4)) + { + __text_start__ = .; + *(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table) + } + __text_end__ = __text_start__ + SIZEOF(.text); + + . = ASSERT(__text_end__ >= __FLASH_segment_start__ && __text_end__ <= (__FLASH_segment_start__ + 0x00030000) , "error: .text is too large to fit in FLASH memory segment"); + + __dtors_load_start__ = ALIGN(__text_end__ , 4); + .dtors ALIGN(__text_end__ , 4) : AT(ALIGN(__text_end__ , 4)) + { + __dtors_start__ = .; + KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) + } + __dtors_end__ = __dtors_start__ + SIZEOF(.dtors); + + . = ASSERT(__dtors_end__ >= __FLASH_segment_start__ && __dtors_end__ <= (__FLASH_segment_start__ + 0x00030000) , "error: .dtors is too large to fit in FLASH memory segment"); + + __ctors_load_start__ = ALIGN(__dtors_end__ , 4); + .ctors ALIGN(__dtors_end__ , 4) : AT(ALIGN(__dtors_end__ , 4)) + { + __ctors_start__ = .; + KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) + } + __ctors_end__ = __ctors_start__ + SIZEOF(.ctors); + + . = ASSERT(__ctors_end__ >= __FLASH_segment_start__ && __ctors_end__ <= (__FLASH_segment_start__ + 0x00030000) , "error: .ctors is too large to fit in FLASH memory segment"); + + __rodata_load_start__ = ALIGN(__ctors_end__ , 4); + .rodata ALIGN(__ctors_end__ , 4) : AT(ALIGN(__ctors_end__ , 4)) + { + __rodata_start__ = .; + *(.rodata .rodata.* .gnu.linkonce.r.*) + } + __rodata_end__ = __rodata_start__ + SIZEOF(.rodata); + + . = ASSERT(__rodata_end__ >= __FLASH_segment_start__ && __rodata_end__ <= (__FLASH_segment_start__ + 0x00030000) , "error: .rodata is too large to fit in FLASH memory segment"); + + __fast_load_start__ = ALIGN(__rodata_end__ , 4); + .fast ALIGN(__RAM_segment_start__ , 4) : AT(ALIGN(__rodata_end__ , 4)) + { + __fast_start__ = .; + *(.fast .fast.*) + } + __fast_end__ = __fast_start__ + SIZEOF(.fast); + + __fast_load_end__ = __fast_load_start__ + SIZEOF(.fast); + + . = ASSERT((__fast_load_start__ + SIZEOF(.fast)) >= __FLASH_segment_start__ && (__fast_load_start__ + SIZEOF(.fast)) <= (__FLASH_segment_start__ + 0x00030000) , "error: .fast is too large to fit in FLASH memory segment"); + + .fast_run ALIGN(__RAM_segment_start__ , 4) (NOLOAD) : + { + __fast_run_start__ = .; + . = MAX(__fast_run_start__ + SIZEOF(.fast), .); + } + __fast_run_end__ = __fast_run_start__ + SIZEOF(.fast_run); + + . = ASSERT(__fast_run_end__ >= __RAM_segment_start__ && __fast_run_end__ <= (__RAM_segment_start__ + 0x00020000) , "error: .fast_run is too large to fit in RAM memory segment"); + + __data_load_start__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4); + .data ALIGN(__fast_run_end__ , 4) : AT(ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4)) + { + __data_start__ = .; + *(.data .data.* .gnu.linkonce.d.*) + } + __data_end__ = __data_start__ + SIZEOF(.data); + + __data_load_end__ = __data_load_start__ + SIZEOF(.data); + + __FLASH_segment_used_end__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4) + SIZEOF(.data); + + . = ASSERT((__data_load_start__ + SIZEOF(.data)) >= __FLASH_segment_start__ && (__data_load_start__ + SIZEOF(.data)) <= (__FLASH_segment_start__ + 0x00030000) , "error: .data is too large to fit in FLASH memory segment"); + + .data_run ALIGN(__fast_run_end__ , 4) (NOLOAD) : + { + __data_run_start__ = .; + . = MAX(__data_run_start__ + SIZEOF(.data), .); + } + __data_run_end__ = __data_run_start__ + SIZEOF(.data_run); + + . = ASSERT(__data_run_end__ >= __RAM_segment_start__ && __data_run_end__ <= (__RAM_segment_start__ + 0x00020000) , "error: .data_run is too large to fit in RAM memory segment"); + + __bss_load_start__ = ALIGN(__data_run_end__ , 4); + .bss ALIGN(__data_run_end__ , 4) (NOLOAD) : AT(ALIGN(__data_run_end__ , 4)) + { + __bss_start__ = .; + *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON) + } + __bss_end__ = __bss_start__ + SIZEOF(.bss); + + . = ASSERT(__bss_end__ >= __RAM_segment_start__ && __bss_end__ <= (__RAM_segment_start__ + 0x00020000) , "error: .bss is too large to fit in RAM memory segment"); + + __non_init_load_start__ = ALIGN(__bss_end__ , 4); + .non_init ALIGN(__bss_end__ , 4) (NOLOAD) : AT(ALIGN(__bss_end__ , 4)) + { + __non_init_start__ = .; + *(.non_init .non_init.*) + } + __non_init_end__ = __non_init_start__ + SIZEOF(.non_init); + + . = ASSERT(__non_init_end__ >= __RAM_segment_start__ && __non_init_end__ <= (__RAM_segment_start__ + 0x00020000) , "error: .non_init is too large to fit in RAM memory segment"); + + __heap_load_start__ = ALIGN(__non_init_end__ , 4); + .heap ALIGN(__non_init_end__ , 4) (NOLOAD) : AT(ALIGN(__non_init_end__ , 4)) + { + __heap_start__ = .; + *(.heap) + . = ALIGN(MAX(__heap_start__ + __HEAPSIZE__ , .), 4); + } + __heap_end__ = __heap_start__ + SIZEOF(.heap); + + . = ASSERT(__heap_end__ >= __RAM_segment_start__ && __heap_end__ <= (__RAM_segment_start__ + 0x00020000) , "error: .heap is too large to fit in RAM memory segment"); + + __stack_load_start__ = ALIGN(__heap_end__ , 4); + .stack ALIGN(__heap_end__ , 4) (NOLOAD) : AT(ALIGN(__heap_end__ , 4)) + { + __stack_start__ = .; + *(.stack) + . = ALIGN(MAX(__stack_start__ + __STACKSIZE__ , .), 4); + } + __stack_end__ = __stack_start__ + SIZEOF(.stack); + + . = ASSERT(__stack_end__ >= __RAM_segment_start__ && __stack_end__ <= (__RAM_segment_start__ + 0x00020000) , "error: .stack is too large to fit in RAM memory segment"); + + __stack_process_load_start__ = ALIGN(__stack_end__ , 4); + .stack_process ALIGN(__stack_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_end__ , 4)) + { + __stack_process_start__ = .; + *(.stack_process) + . = ALIGN(MAX(__stack_process_start__ + __STACKSIZE_PROCESS__ , .), 4); + } + __stack_process_end__ = __stack_process_start__ + SIZEOF(.stack_process); + + __RAM_segment_used_end__ = ALIGN(__stack_end__ , 4) + SIZEOF(.stack_process); + + . = ASSERT(__stack_process_end__ >= __RAM_segment_start__ && __stack_process_end__ <= (__RAM_segment_start__ + 0x00020000) , "error: .stack_process is too large to fit in RAM memory segment"); + +} + diff --git a/ports_module/cortex-m3/gnu/example_build/sample_threadx_module.c b/ports_module/cortex-m3/gnu/example_build/sample_threadx_module.c new file mode 100644 index 00000000..52557312 --- /dev/null +++ b/ports_module/cortex-m3/gnu/example_build/sample_threadx_module.c @@ -0,0 +1,428 @@ +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, + event flags group, byte pool, and block pool. */ + +/* Specify that this is a module! */ + +#define TXM_MODULE + + +/* Include the ThreadX module definitions. */ + +#include "txm_module.h" + + +/* Define constants. */ + +#define DEMO_STACK_SIZE 512 +#define DEMO_BYTE_POOL_SIZE 6000 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the pool space in the bss section of the module. ULONG is used to + get the word alignment. */ + +ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD *thread_0; +TX_THREAD *thread_1; +TX_THREAD *thread_2; +TX_THREAD *thread_3; +TX_THREAD *thread_4; +TX_THREAD *thread_5; +TX_THREAD *thread_6; +TX_THREAD *thread_7; +TX_QUEUE *queue_0; +TX_SEMAPHORE *semaphore_0; +TX_MUTEX *mutex_0; +TX_EVENT_FLAGS_GROUP *event_flags_0; +TX_BYTE_POOL *byte_pool_0; +TX_BLOCK_POOL *block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; +ULONG semaphore_0_puts; +ULONG event_0_sets; +ULONG queue_0_sends; + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + +void semaphore_0_notify(TX_SEMAPHORE *semaphore_ptr) +{ + + if (semaphore_ptr == semaphore_0) + semaphore_0_puts++; +} + + +void event_0_notify(TX_EVENT_FLAGS_GROUP *event_flag_group_ptr) +{ + + if (event_flag_group_ptr == event_flags_0) + event_0_sets++; +} + + +void queue_0_notify(TX_QUEUE *queue_ptr) +{ + + if (queue_ptr == queue_0) + queue_0_sends++; +} + + +/* Define the module start function. */ + +void demo_module_start(ULONG id) +{ + +CHAR *pointer; + + /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + the control block(s). */ + txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_2, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_3, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_4, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_5, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_6, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_7, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&queue_0, sizeof(TX_QUEUE)); + txm_module_object_allocate((void*)&semaphore_0, sizeof(TX_SEMAPHORE)); + txm_module_object_allocate((void*)&mutex_0, sizeof(TX_MUTEX)); + txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); + txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); + txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(byte_pool_0, "module byte pool 0", (UCHAR*)demo_module_pool_space, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(queue_0, "module queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + tx_queue_send_notify(queue_0, queue_0_notify); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(semaphore_0, "module semaphore 0", 1); + + tx_semaphore_put_notify(semaphore_0, semaphore_0_notify); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(event_flags_0, "module event flags 0"); + + tx_event_flags_set_notify(event_flags_0, event_0_notify); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(mutex_0, "module mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(block_pool_0, "module block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + /* Test memory handler. */ + *(ULONG *)0x20010000 = 0xCDCDCDCD; + + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + diff --git a/ports_module/cortex-m3/gnu/example_build/sample_threadx_module.ld b/ports_module/cortex-m3/gnu/example_build/sample_threadx_module.ld new file mode 100644 index 00000000..a33fbfeb --- /dev/null +++ b/ports_module/cortex-m3/gnu/example_build/sample_threadx_module.ld @@ -0,0 +1,210 @@ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00030000, LENGTH = 0x00010000 + RAM (wx) : ORIGIN = 0, LENGTH = 0x00100000 +} + + +SECTIONS +{ + __FLASH_segment_start__ = 0x00030000; + __FLASH_segment_end__ = 0x00040000; + __RAM_segment_start__ = 0; + __RAM_segment_end__ = 0x8000; + + __HEAPSIZE__ = 128; + + __preamble_load_start__ = __FLASH_segment_start__; + .preamble __FLASH_segment_start__ : AT(__FLASH_segment_start__) + { + __preamble_start__ = .; + *(.preamble .preamble.*) + } + __preamble_end__ = __preamble_start__ + SIZEOF(.preamble); + + __dynsym_load_start__ = ALIGN(__preamble_end__ , 4); + .dynsym ALIGN(__dynsym_load_start__ , 4) : AT(ALIGN(__dynsym_load_start__ , 4)) + { + . = ALIGN(4); + KEEP (*(.dynsym)) + KEEP (*(.dynsym*)) + . = ALIGN(4); + } + __dynsym_end__ = __dynsym_load_start__ + SIZEOF(.dynsym); + + __dynstr_load_start__ = ALIGN(__dynsym_end__ , 4); + .dynstr ALIGN(__dynstr_load_start__ , 4) : AT(ALIGN(__dynstr_load_start__, 4)) + { + . = ALIGN(4); + KEEP (*(.dynstr)) + KEEP (*(.dynstr*)) + . = ALIGN(4); + } + __dynstr_end__ = __dynstr_load_start__ + SIZEOF(.dynstr); + + __reldyn_load_start__ = ALIGN(__dynstr_end__ , 4); + .rel.dyn ALIGN(__reldyn_load_start__ , 4) : AT(ALIGN(__reldyn_load_start__ , 4)) + { + . = ALIGN(4); + KEEP (*(.rel.dyn)) + KEEP (*(.rel.dyn*)) + . = ALIGN(4); + } + __reldyn_end__ = __reldyn_load_start__ + SIZEOF(.rel.dyn); + + __relplt_load_start__ = ALIGN(__reldyn_end__ , 4); + .rel.plt ALIGN(__relplt_load_start__ , 4) : AT(ALIGN(__relplt_load_start__ , 4)) + { + . = ALIGN(4); + KEEP (*(.rel.plt)) + KEEP (*(.rel.plt*)) + . = ALIGN(4); + } + __relplt_end__ = __relplt_load_start__ + SIZEOF(.rel.plt); + + __plt_load_start__ = ALIGN(__relplt_end__ , 4); + .plt ALIGN(__plt_load_start__ , 4) : AT(ALIGN(__plt_load_start__ , 4)) + { + . = ALIGN(4); + KEEP (*(.plt)) + KEEP (*(.plt*)) + . = ALIGN(4); + } + __plt_end__ = __plt_load_start__ + SIZEOF(.plt); + + __interp_load_start__ = ALIGN(__plt_end__ , 4); + .interp ALIGN(__interp_load_start__ , 4) : AT(ALIGN(__interp_load_start__ , 4)) + { + . = ALIGN(4); + KEEP (*(.interp)) + KEEP (*(.interp*)) + . = ALIGN(4); + } + __interp_end__ = __interp_load_start__ + SIZEOF(.interp); + + __hash_load_start__ = ALIGN(__interp_end__ , 4); + .hash ALIGN(__hash_load_start__ , 4) : AT(ALIGN(__hash_load_start__, 4)) + { + . = ALIGN(4); + KEEP (*(.hash)) + KEEP (*(.hash*)) + . = ALIGN(4); + } + __hash_end__ = __hash_load_start__ + SIZEOF(.hash); + + __text_load_start__ = ALIGN(__hash_end__ , 4); + .text ALIGN(__text_load_start__ , 4) : AT(ALIGN(__text_load_start__, 4)) + { + __text_start__ = .; + *(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table ) + } + __text_end__ = __text_start__ + SIZEOF(.text); + + __dtors_load_start__ = ALIGN(__text_end__ , 4); + .dtors ALIGN(__text_end__ , 4) : AT(ALIGN(__text_end__ , 4)) + { + __dtors_start__ = .; + KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) + } + __dtors_end__ = __dtors_start__ + SIZEOF(.dtors); + + __ctors_load_start__ = ALIGN(__dtors_end__ , 4); + .ctors ALIGN(__dtors_end__ , 4) : AT(ALIGN(__dtors_end__ , 4)) + { + __ctors_start__ = .; + KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) + } + __ctors_end__ = __ctors_start__ + SIZEOF(.ctors); + + __got_load_start__ = ALIGN(__ctors_end__ , 4); + .got ALIGN(__ctors_end__ , 4) : AT(ALIGN(__ctors_end__ , 4)) + { + . = ALIGN(4); + _sgot = .; + KEEP (*(.got)) + KEEP (*(.got*)) + . = ALIGN(4); + _egot = .; + } + __got_end__ = __got_load_start__ + SIZEOF(.got); + + __rodata_load_start__ = ALIGN(__got_end__ , 4); + .rodata ALIGN(__got_end__ , 4) : AT(ALIGN(__got_end__ , 4)) + { + __rodata_start__ = .; + *(.rodata .rodata.* .gnu.linkonce.r.*) + } + __rodata_end__ = __rodata_start__ + SIZEOF(.rodata); + + __code_size__ = __rodata_end__ - __FLASH_segment_start__; + + __fast_load_start__ = ALIGN(__rodata_end__ , 4); + + __fast_load_end__ = __fast_load_start__ + SIZEOF(.fast); + + __new_got_start__ = ALIGN(__RAM_segment_start__ , 4); + + __new_got_end__ = __new_got_start__ + SIZEOF(.got); + + .fast ALIGN(__new_got_end__ , 4) : AT(ALIGN(__rodata_end__ , 4)) + { + __fast_start__ = .; + *(.fast .fast.*) + } + __fast_end__ = __fast_start__ + SIZEOF(.fast); + + .fast_run ALIGN(__fast_end__ , 4) (NOLOAD) : + { + __fast_run_start__ = .; + . = MAX(__fast_run_start__ + SIZEOF(.fast), .); + } + __fast_run_end__ = __fast_run_start__ + SIZEOF(.fast_run); + + __data_load_start__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4); + .data ALIGN(__fast_run_end__ , 4) : AT(ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4)) + { + __data_start__ = .; + *(.data .data.* .gnu.linkonce.d.*) + } + __data_end__ = __data_start__ + SIZEOF(.data); + + __data_load_end__ = __data_load_start__ + SIZEOF(.data); + + __FLASH_segment_used_end__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4) + SIZEOF(.data); + + .data_run ALIGN(__fast_run_end__ , 4) (NOLOAD) : + { + __data_run_start__ = .; + . = MAX(__data_run_start__ + SIZEOF(.data), .); + } + __data_run_end__ = __data_run_start__ + SIZEOF(.data_run); + + __bss_load_start__ = ALIGN(__data_run_end__ , 4); + .bss ALIGN(__data_run_end__ , 4) (NOLOAD) : AT(ALIGN(__data_run_end__ , 4)) + { + __bss_start__ = .; + *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON) + } + __bss_end__ = __bss_start__ + SIZEOF(.bss); + + __non_init_load_start__ = ALIGN(__bss_end__ , 4); + .non_init ALIGN(__bss_end__ , 4) (NOLOAD) : AT(ALIGN(__bss_end__ , 4)) + { + __non_init_start__ = .; + *(.non_init .non_init.*) + } + __non_init_end__ = __non_init_start__ + SIZEOF(.non_init); + + __heap_load_start__ = ALIGN(__non_init_end__ , 4); + .heap ALIGN(__non_init_end__ , 4) (NOLOAD) : AT(ALIGN(__non_init_end__ , 4)) + { + __heap_start__ = .; + *(.heap) + . = ALIGN(MAX(__heap_start__ + __HEAPSIZE__ , .), 4); + } + __heap_end__ = __heap_start__ + SIZEOF(.heap); + + __data_size__ = __heap_end__ - __RAM_segment_start__; + +} + diff --git a/ports_module/cortex-m3/gnu/example_build/sample_threadx_module_manager.c b/ports_module/cortex-m3/gnu/example_build/sample_threadx_module_manager.c new file mode 100644 index 00000000..203223be --- /dev/null +++ b/ports_module/cortex-m3/gnu/example_build/sample_threadx_module_manager.c @@ -0,0 +1,109 @@ +/* Small demonstration of the ThreadX module manager. */ + +#include "tx_api.h" +#include "txm_module.h" + + +#define DEMO_STACK_SIZE 1024 + +/* Define the ThreadX object control blocks... */ + +TX_THREAD module_manager; +TXM_MODULE_INSTANCE my_module; + + +/* Define the object pool area. */ + +UCHAR object_memory[16384]; +UCHAR module_ram[32768]; + +/* Define the count of memory faults. */ + +ULONG memory_faults; + + +/* Define thread prototypes. */ + +void module_manager_entry(ULONG thread_input); + + +/* Define fault handler. */ + +VOID module_fault_handler(TX_THREAD *thread, TXM_MODULE_INSTANCE *module) +{ + + /* Just increment the fault counter. */ + memory_faults++; +} + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = (CHAR*)first_unused_memory; + + + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + pointer = pointer + DEMO_STACK_SIZE; +} + + + + +/* Define the test threads. */ + +void module_manager_entry(ULONG thread_input) +{ + + /* Initialize the module manager. */ + txm_module_manager_initialize((VOID *) module_ram, 32768); + + txm_module_manager_object_pool_create(object_memory, sizeof(object_memory)); + + /* Register a fault handler. */ + txm_module_manager_memory_fault_notify(module_fault_handler); + + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ + txm_module_manager_memory_load(&my_module, "my module", (VOID *) 0x00030000); + + /* Enable 128 byte read/write shared memory region at 0x20010000. */ + txm_module_manager_external_memory_enable(&my_module, (void *) 0x20010000, 128, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); + + /* Start the module. */ + txm_module_manager_start(&my_module); + + /* Sleep for a while.... */ + tx_thread_sleep(1000); + + /* Stop the module. */ + txm_module_manager_stop(&my_module); + + /* Unload the module. */ + txm_module_manager_unload(&my_module); + + /* Load the module that is already there. */ + txm_module_manager_in_place_load(&my_module, "my module", (VOID *) 0x00030000); + + /* Start the module again. */ + txm_module_manager_start(&my_module); + + /* Now just spin... */ + while(1) + { + + tx_thread_sleep(100); + } +} diff --git a/ports_module/cortex-m3/gnu/example_build/tx_initialize_low_level.S b/ports_module/cortex-m3/gnu/example_build/tx_initialize_low_level.S new file mode 100644 index 00000000..37c959bd --- /dev/null +++ b/ports_module/cortex-m3/gnu/example_build/tx_initialize_low_level.S @@ -0,0 +1,209 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global __RAM_segment_used_end__ + .global _tx_timer_interrupt + .global __main + .global _vectors + .global __tx_NMIHandler @ NMI + .global __tx_BadHandler @ HardFault + .global __tx_DBGHandler @ Monitor + .global __tx_PendSVHandler @ PendSV + .global __tx_SysTickHandler @ SysTick + .global __tx_IntHandler @ Int 0 + +SYSTEM_CLOCK = 6000000 +SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) + + .text 32 + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-M3/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +//VOID _tx_initialize_low_level(VOID) +//{ + .global _tx_initialize_low_level + .thumb_func +_tx_initialize_low_level: + + /* Disable interrupts during ThreadX initialization. */ + CPSID i + + /* Set base of available memory to end of non-initialised RAM area. */ + LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer + LDR r1, =__RAM_segment_used_end__ @ Build first free address + ADD r1, r1, #4 @ + STR r1, [r0] @ Setup first unused memory pointer + + /* Setup Vector Table Offset Register. */ + MOV r0, #0xE000E000 @ Build address of NVIC registers + LDR r1, =_vectors @ Pickup address of vector table + STR r1, [r0, #0xD08] @ Set vector table address + + /* Set system stack pointer from vector value. */ + LDR r0, =_tx_thread_system_stack_ptr @ Build address of system stack pointer + LDR r1, =_vectors @ Pickup address of vector table + LDR r1, [r1] @ Pickup reset stack pointer + STR r1, [r0] @ Save system stack pointer + + /* Enable the cycle count register. */ + LDR r0, =0xE0001000 @ Build address of DWT register + LDR r1, [r0] @ Pickup the current value + ORR r1, r1, #1 @ Set the CYCCNTENA bit + STR r1, [r0] @ Enable the cycle count register + + /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ + MOV r0, #0xE000E000 @ Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] @ Setup SysTick Reload Value + MOV r1, #0x7 @ Build SysTick Control Enable Value + STR r1, [r0, #0x10] @ Setup SysTick Control + + /* Configure handler priorities. */ + LDR r1, =0x00000000 @ Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] @ Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 @ SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] @ Setup System Handlers 8-11 Priority Registers + @ Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] @ Setup System Handlers 12-15 Priority Registers + @ Note: PnSV must be lowest priority, which is 0xFF + + + /* Return to caller. */ + BX lr +//} + + +/* Define shells for each of the unused vectors. */ + + .global __tx_BadHandler + .thumb_func +__tx_BadHandler: + B __tx_BadHandler + +/* added to catch the hardfault */ + + .global __tx_HardfaultHandler + .thumb_func +__tx_HardfaultHandler: + B __tx_HardfaultHandler + +/* Generic interrupt handler template */ + .global __tx_IntHandler + .thumb_func +__tx_IntHandler: +// VOID InterruptHandler (VOID) +// { + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter // Call the ISR enter function +#endif + + /* Do interrupt handler work here */ + /* BL .... */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit // Call the ISR exit function +#endif + POP {r0, lr} + BX LR +// } + +/* System Tick timer interrupt handler */ + .global __tx_SysTickHandler + .global SysTick_Handler + .thumb_func +__tx_SysTickHandler: + .thumb_func +SysTick_Handler: +// VOID TimerInterruptHandler (VOID) +// { + + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter // Call the ISR enter function +#endif + BL _tx_timer_interrupt +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit // Call the ISR exit function +#endif + POP {r0, lr} + BX LR +// } + + +/* NMI, DBG handlers */ + .global __tx_NMIHandler + .thumb_func +__tx_NMIHandler: + B __tx_NMIHandler + + .global __tx_DBGHandler + .thumb_func +__tx_DBGHandler: + B __tx_DBGHandler + diff --git a/ports_module/cortex-m3/gnu/example_build/tx_simulator_startup.s b/ports_module/cortex-m3/gnu/example_build/tx_simulator_startup.s new file mode 100644 index 00000000..73692924 --- /dev/null +++ b/ports_module/cortex-m3/gnu/example_build/tx_simulator_startup.s @@ -0,0 +1,73 @@ + + .syntax unified + .section .vectors, "ax" + .code 16 + .align 0 + .global _vectors + +_vectors: + .word __stack_end__ + .word reset_handler + .word __tx_NMIHandler + .word __tx_HardfaultHandler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word __tx_SVCallHandler //_SVC_Handler - used by Threadx scheduler // + .word __tx_DBGHandler + .word 0 // Reserved + .word __tx_PendSVHandler + .word __tx_SysTickHandler // Used by Threadx timer functionality + .word __tx_BadHandler // Populate with user Interrupt handler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + + + + .section .init, "ax" + .global reset_handler + .thumb_func +reset_handler: + +// low level hardware config, such as PLL setup goes here + + b _start + + + diff --git a/ports_module/cortex-m3/gnu/example_build/txm_module_preamble.S b/ports_module/cortex-m3/gnu/example_build/txm_module_preamble.S new file mode 100644 index 00000000..e2df9b29 --- /dev/null +++ b/ports_module/cortex-m3/gnu/example_build/txm_module_preamble.S @@ -0,0 +1,58 @@ + .text + .align 4 + .syntax unified + + /* Define public symbols. */ + .global __txm_module_preamble + + /* Define application-specific start/stop entry points for the module. */ + .global demo_module_start + + /* Define common external refrences. */ + .global _txm_module_thread_shell_entry + .global _txm_module_callback_request_thread_entry + +__txm_module_preamble: + .dc.l 0x4D4F4455 // Module ID + .dc.l 0x6 // Module Major Version + .dc.l 0x1 // Module Minor Version + .dc.l 32 // Module Preamble Size in 32-bit words + .dc.l 0x12345678 // Module ID (application defined) + .dc.l 0x02000007 // Module Properties where: + // Bits 31-24: Compiler ID + // 0 -> IAR + // 1 -> RVDS + // 2 -> GNU + // Bits 23-3: Reserved + // Bit 2: 0 -> Disable shared/external memory access + // 1 -> Enable shared/external memory access + // Bit 1: 0 -> No MPU protection + // 1 -> MPU protection (must have user mode selected - bit 0 set) + // Bit 0: 0 -> Privileged mode execution + // 1 -> User mode execution + .dc.l _txm_module_thread_shell_entry - . - 0 // Module Shell Entry Point + .dc.l demo_module_start - . - 0 // Module Start Thread Entry Point + .dc.l 0 // Module Stop Thread Entry Point + .dc.l 1 // Module Start/Stop Thread Priority + .dc.l 1024 // Module Start/Stop Thread Stack Size + .dc.l _txm_module_callback_request_thread_entry - . - 0 // Module Callback Thread Entry + .dc.l 1 // Module Callback Thread Priority + .dc.l 1024 // Module Callback Thread Stack Size + .dc.l __code_size__ // Module Code Size + .dc.l __data_size__ // Module Data Size + .dc.l 0 // Reserved 0 + .dc.l 0 // Reserved 1 + .dc.l 0 // Reserved 2 + .dc.l 0 // Reserved 3 + .dc.l 0 // Reserved 4 + .dc.l 0 // Reserved 5 + .dc.l 0 // Reserved 6 + .dc.l 0 // Reserved 7 + .dc.l 0 // Reserved 8 + .dc.l 0 // Reserved 9 + .dc.l 0 // Reserved 10 + .dc.l 0 // Reserved 11 + .dc.l 0 // Reserved 12 + .dc.l 0 // Reserved 13 + .dc.l 0 // Reserved 14 + .dc.l 0 // Reserved 15 diff --git a/ports_module/cortex-m3/gnu/inc/tx_port.h b/ports_module/cortex-m3/gnu/inc/tx_port.h new file mode 100644 index 00000000..18624cbd --- /dev/null +++ b/ports_module/cortex-m3/gnu/inc/tx_port.h @@ -0,0 +1,376 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-M3/GNU */ +/* 6.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX Cortex-M7 port. */ + +#define TX_INT_DISABLE 1 /* Disable interrupts */ +#define TX_INT_ENABLE 0 /* Enable interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0 + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); + +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define the get system state macro. */ + +#ifndef TX_THREAD_GET_SYSTEM_STATE +#ifndef TX_MISRA_ENABLE + +__attribute__( ( always_inline ) ) static inline unsigned int __get_ipsr_value(void) +{ + +unsigned int ipsr_value; + + __asm__ volatile (" MRS %0,IPSR ": "=r" (ipsr_value) ); + return(ipsr_value); +} + + +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | __get_ipsr_value()) +#else +ULONG _tx_misra_ipsr_get(VOID); +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get()) +#endif +#endif + + +/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value + indicates that _tx_thread_system_return should not be called. */ + +#ifndef TX_THREAD_SYSTEM_RETURN_CHECK +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#endif + +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to + prevent early scheduling on Cortex-M parts. */ + +#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; + + +/* This ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + +#endif + + +#ifndef TX_DISABLE_INLINE + +/* Define GNU specific macros, with in-line assembly for performance. */ + +__attribute__( ( always_inline ) ) static inline unsigned int __disable_interrupts(void) +{ + +unsigned int primask_value; + + __asm__ volatile (" MRS %0,PRIMASK ": "=r" (primask_value) ); + __asm__ volatile (" CPSID i" : : : "memory" ); + return(primask_value); +} + +__attribute__( ( always_inline ) ) static inline void __restore_interrupts(unsigned int primask_value) +{ + + __asm__ volatile (" MSR PRIMASK,%0": : "r" (primask_value): "memory" ); +} + +__attribute__( ( always_inline ) ) static inline unsigned int __get_primask_value(void) +{ + +unsigned int primask_value; + + __asm__ volatile (" MRS %0,PRIMASK ": "=r" (primask_value) ); + return(primask_value); +} + +__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void) +{ + + __asm__ volatile (" CPSIE i": : : "memory" ); +} + + +__attribute__( ( always_inline ) ) static inline void _tx_thread_system_return_inline(void) +{ +unsigned int interrupt_save; + + *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + if (__get_ipsr_value() == 0) + { + interrupt_save = __get_primask_value(); + __enable_interrupts(); + __restore_interrupts(interrupt_save); + } +} + + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = __disable_interrupts(); +#define TX_RESTORE __restore_interrupts(interrupt_save); + + +/* Redefine _tx_thread_system_return for improved performance. */ + +#define _tx_thread_system_return _tx_thread_system_return_inline + + +#else + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); +#define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); +#endif + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/GNU Version 6.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + + + + + diff --git a/ports_module/cortex-m3/gnu/inc/txm_module_port.h b/ports_module/cortex-m3/gnu/inc/txm_module_port.h new file mode 100644 index 00000000..68632492 --- /dev/null +++ b/ports_module/cortex-m3/gnu/inc/txm_module_port.h @@ -0,0 +1,323 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* txm_module_port.h Cortex-M3/MPU/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the basic module constants, interface structures, */ +/* and function prototypes. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TXM_MODULE_PORT_H +#define TXM_MODULE_PORT_H + +/* Determine if the optional Modules user define file should be used. */ + +#ifdef TXM_MODULE_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in txm_module_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "txm_module_user.h" +#endif + +/* It is assumed that the base ThreadX tx_port.h file has been modified to add the + following extensions to the ThreadX thread control block (this code should replace + the corresponding macro define in tx_port.h): + +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; + +The following extensions must also be defined in tx_port.h: + +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); + +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); +*/ + +/* Define the kernel stack size for a module thread. */ +#ifndef TXM_MODULE_KERNEL_STACK_SIZE +#define TXM_MODULE_KERNEL_STACK_SIZE 768 +#endif + +/* Define constants specific to the tools the module can be built with for this particular modules port. */ + +#define TXM_MODULE_IAR_COMPILER 0x00000000 +#define TXM_MODULE_RVDS_COMPILER 0x01000000 +#define TXM_MODULE_GNU_COMPILER 0x02000000 +#define TXM_MODULE_COMPILER_MASK 0xFF000000 +#define TXM_MODULE_OPTIONS_MASK 0x000000FF + + +/* Define the properties for this particular module port. */ + +#define TXM_MODULE_MEMORY_PROTECTION_ENABLED + +#ifdef TXM_MODULE_MEMORY_PROTECTION_ENABLED +#define TXM_MODULE_REQUIRE_ALLOCATED_OBJECT_MEMORY +#else +#define TXM_MODULE_REQUIRE_LOCAL_OBJECT_MEMORY +#endif + +#define TXM_MODULE_USER_MODE 0x00000001 +#define TXM_MODULE_MEMORY_PROTECTION 0x00000002 +#define TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS 0x00000004 + + +/* Define the supported options for this module. */ + +#define TXM_MODULE_MANAGER_SUPPORTED_OPTIONS (TXM_MODULE_USER_MODE | TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS) +#define TXM_MODULE_MANAGER_REQUIRED_OPTIONS 0 + + +/* Define offset adjustments according to the compiler used to build the module. */ + +#define TXM_MODULE_IAR_SHELL_ADJUST 24 +#define TXM_MODULE_IAR_START_ADJUST 28 +#define TXM_MODULE_IAR_STOP_ADJUST 32 +#define TXM_MODULE_IAR_CALLBACK_ADJUST 44 + +#define TXM_MODULE_RVDS_SHELL_ADJUST 0 +#define TXM_MODULE_RVDS_START_ADJUST 0 +#define TXM_MODULE_RVDS_STOP_ADJUST 0 +#define TXM_MODULE_RVDS_CALLBACK_ADJUST 0 + +#define TXM_MODULE_GNU_SHELL_ADJUST 24 +#define TXM_MODULE_GNU_START_ADJUST 28 +#define TXM_MODULE_GNU_STOP_ADJUST 32 +#define TXM_MODULE_GNU_CALLBACK_ADJUST 44 + + +/* Define other module port-specific constants. */ + +/* Define INLINE_DECLARE to inline for GNU compiler. */ + +#define INLINE_DECLARE inline + +/* Define the number of MPU entries assigned to the code and data sections. On Cortex-M parts, there can only be 7 total + entries, since ThreadX uses one for access to the kernel dispatch function. */ + +#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 +#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 +#define TXM_MODULE_MANAGER_SHARED_MPU_INDEX 8 +#define TXM_MODULE_MANAGER_SHARED_MPU_REGION 4 + +/* Shared memory region attributes. */ +#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 +#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 + +/* Define the port-extensions to the module manager instance structure. */ + +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + ULONG txm_module_instance_mpu_registers[16]; \ + ULONG txm_module_instance_shared_memory_address; \ + ULONG txm_module_instance_shared_memory_length; + + +/* Define the memory fault information structure that is populated when a memory fault occurs. */ + + +typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT +{ + TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr; + VOID *txm_module_manager_memory_fault_info_code_location; + ULONG txm_module_manager_memory_fault_info_shcsr; + ULONG txm_module_manager_memory_fault_info_cfsr; + ULONG txm_module_manager_memory_fault_info_mmfar; + ULONG txm_module_manager_memory_fault_info_bfar; + ULONG txm_module_manager_memory_fault_info_control; + ULONG txm_module_manager_memory_fault_info_sp; + ULONG txm_module_manager_memory_fault_info_r0; + ULONG txm_module_manager_memory_fault_info_r1; + ULONG txm_module_manager_memory_fault_info_r2; + ULONG txm_module_manager_memory_fault_info_r3; + ULONG txm_module_manager_memory_fault_info_r4; + ULONG txm_module_manager_memory_fault_info_r5; + ULONG txm_module_manager_memory_fault_info_r6; + ULONG txm_module_manager_memory_fault_info_r7; + ULONG txm_module_manager_memory_fault_info_r8; + ULONG txm_module_manager_memory_fault_info_r9; + ULONG txm_module_manager_memory_fault_info_r10; + ULONG txm_module_manager_memory_fault_info_r11; + ULONG txm_module_manager_memory_fault_info_r12; + ULONG txm_module_manager_memory_fault_info_lr; + ULONG txm_module_manager_memory_fault_info_xpsr; +} TXM_MODULE_MANAGER_MEMORY_FAULT_INFO; + + +#define TXM_MODULE_MANAGER_FAULT_INFO \ + TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info; + +/* Define the macro to check the code alignment. */ + +#define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment) \ + { \ + ULONG temp; \ + temp = (ULONG) module_location; \ + temp = temp & (code_alignment - 1); \ + if (temp) \ + { \ + _tx_mutex_put(&_txm_module_manager_mutex); \ + return(TXM_MODULE_ALIGNMENT_ERROR); \ + } \ + } + + +/* Define the macro to adjust the alignment and size for code/data areas. */ + +#define TXM_MODULE_MANAGER_ALIGNMENT_ADJUST(module_preamble, code_size, code_alignment, data_size, data_alignment) _txm_module_manager_alignment_adjust(module_preamble, &code_size, &code_alignment, &data_size, &data_alignment); + + +/* Define the macro to adjust the symbols in the module preamble. */ + +#define TXM_MODULE_MANAGER_CALCULATE_ADJUSTMENTS(properties, shell_function_adjust, start_function_adjust, stop_function_adjust, callback_function_adjust) \ + if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_IAR_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_IAR_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_IAR_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_IAR_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_IAR_CALLBACK_ADJUST; \ + } \ + else if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_RVDS_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_RVDS_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_RVDS_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_RVDS_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_RVDS_CALLBACK_ADJUST; \ + } \ + else \ + { \ + shell_function_adjust = TXM_MODULE_GNU_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_GNU_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_GNU_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_GNU_CALLBACK_ADJUST; \ + } + + +/* Define the macro to populate the thread control block with module port-specific information. + Check if the module is in user mode and set up txm_module_thread_entry_info_kernel_call_dispatcher accordingly. +*/ + +#define TXM_MODULE_MANAGER_THREAD_SETUP(thread_ptr, module_instance) \ + thread_ptr -> tx_thread_module_current_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \ + thread_ptr -> tx_thread_module_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \ + if (thread_ptr -> tx_thread_module_user_mode) \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_user_mode_entry; \ + } \ + else \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_kernel_dispatch; \ + } + + +/* Define the macro to populate the module control block with module port-specific information. + If memory protection is enabled, set up the MPU registers. +*/ +#define TXM_MODULE_MANAGER_MODULE_SETUP(module_instance) \ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE) \ + { \ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) \ + { \ + _txm_module_manager_mm_register_setup(module_instance); \ + } \ + } \ + else \ + { \ + /* Do nothing. */ \ + } + +/* Define the macro to perform port-specific functions when unloading the module. */ +/* Nothing needs to be done for this port. */ +#define TXM_MODULE_MANAGER_MODULE_UNLOAD(module_instance) + + +/* Define the macros to perform port-specific checks when passing pointers to the kernel. */ + +/* Define macro to make sure object is inside the module's data. */ +#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ + /* Check if it's inside module data. */ \ + ((((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && \ + (((obj_ptr) + (obj_size)) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) || \ + /* Check if it's inside shared memory. */ \ + (((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address) && \ + (((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (module_instance -> txm_module_instance_shared_memory_address + module_instance -> txm_module_instance_shared_memory_length)))) + + +/* Define some internal prototypes to this module port. */ + +#ifndef TX_SOURCE_CODE +#define txm_module_manager_memory_fault_notify _txm_module_manager_memory_fault_notify +#endif + + +#define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES \ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment); \ +VOID _txm_module_manager_memory_fault_handler(VOID); \ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)); \ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \ +ULONG _txm_power_of_two_block_size(ULONG size); \ +ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); \ +ULONG _txm_module_manager_region_size_get(ULONG block_size); + +#define TXM_MODULE_MANAGER_VERSION_ID \ +CHAR _txm_module_manager_version_id[] = \ + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3/MPU/GNU Version 6.1 *"; + +#endif diff --git a/ports_module/cortex-m3/gnu/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex-m3/gnu/module_lib/src/txm_module_thread_shell_entry.c new file mode 100644 index 00000000..a20983fa --- /dev/null +++ b/ports_module/cortex-m3/gnu/module_lib/src/txm_module_thread_shell_entry.c @@ -0,0 +1,174 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#ifndef TXM_MODULE +#define TXM_MODULE +#endif + +#ifndef TX_SOURCE_CODE +#define TX_SOURCE_CODE +#endif + + +/* Include necessary system files. */ + +#include "txm_module.h" +#include "tx_thread.h" + +/* Define the global module entry pointer from the start thread of the module. */ + +TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; + + +/* Define the dispatch function pointer used in the module implementation. */ + +ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3); + + +/* Define the GCC startup code that clears the uninitialized global data and sets up the + preset global variables. */ + +extern VOID _gcc_setup(TXM_MODULE_INSTANCE *); + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_thread_shell_entry Cortex-M3/MPU/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calls the specified entry function of the thread. It */ +/* also provides a place for the thread's entry function to return. */ +/* If the thread returns, this function places the thread in a */ +/* "COMPLETED" state. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to current thread */ +/* thread_info Pointer to thread entry info */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _gcc_setup GNU global init function */ +/* thread_entry Thread's entry function */ +/* tx_thread_resume Resume the module callback thread */ +/* _txm_module_thread_system_suspend Module thread suspension routine */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) +{ + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + VOID (*entry_exit_notify)(TX_THREAD *, UINT); +#endif + + + /* Determine if this is the start thread. If so, we must prepare the module for + execution. If not, simply skip the C startup code. */ + if (thread_info -> txm_module_thread_entry_info_start_thread) + { + /* Initialize the GNU C environment. */ + _gcc_setup(thread_info -> txm_module_thread_entry_info_code_base_address); + + /* Save the entry info pointer, for later use. */ + _txm_module_entry_info = thread_info; + + /* Save the kernel function dispatch address. This is used to make all resident calls from + the module. */ + _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; + + /* Ensure that we have a valid pointer. */ + while (!_txm_module_kernel_call_dispatcher) + { + /* Loop here, if an error is present getting the dispatch function pointer! + An error here typically indicates the resident portion of _tx_thread_schedule + is not supporting the trap to obtain the function pointer. */ + } + + /* Resume the module's callback thread, already created in the manager. */ + _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); + } + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has been entered! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_ENTRY); + } +#endif + + /* Call current thread's entry function. */ + (thread_info -> txm_module_thread_entry_info_entry) (thread_info -> txm_module_thread_entry_info_parameter); + + /* Suspend thread with a "completed" state. */ + + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine again. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has exited! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_EXIT); + } +#endif + + /* Call actual thread suspension routine. */ + _txm_module_thread_system_suspend(thread_ptr); + +#ifdef TX_SAFETY_CRITICAL + + /* If we ever get here, raise safety critical exception. */ + TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0); +#endif +} + diff --git a/ports_module/cortex-m3/gnu/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex-m3/gnu/module_manager/src/tx_thread_context_restore.S new file mode 100644 index 00000000..d279e33e --- /dev/null +++ b/ports_module/cortex-m3/gnu/module_manager/src/tx_thread_context_restore.S @@ -0,0 +1,87 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_system_stack_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable + .global _tx_execution_isr_exit +@ +@ + .text + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_restore Cortex-M3/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is only needed for legacy applications and it should */ +@/* not be called in any new development on a Cortex-M. */ +@/* This function restores the interrupt context if it is processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs Interrupt Service Routines */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_restore(VOID) +@{ + .global _tx_thread_context_restore + .thumb_func +_tx_thread_context_restore: +@ +@ /* Not needed for this port - just return! */ + BX lr +@} diff --git a/ports_module/cortex-m3/gnu/module_manager/src/tx_thread_context_save.S b/ports_module/cortex-m3/gnu/module_manager/src/tx_thread_context_save.S new file mode 100644 index 00000000..357f633a --- /dev/null +++ b/ports_module/cortex-m3/gnu/module_manager/src/tx_thread_context_save.S @@ -0,0 +1,81 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_execution_isr_enter +@ +@ + .text + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_save Cortex-M3/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is only needed for legacy applications and it should */ +@/* not be called in any new development on a Cortex-M. */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_save(VOID) +@{ + .global _tx_thread_context_save + .thumb_func +_tx_thread_context_save: +@ +@ /* Not needed for this port - just return! */ + BX lr +@} diff --git a/ports_module/cortex-m3/gnu/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex-m3/gnu/module_manager/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..22331e70 --- /dev/null +++ b/ports_module/cortex-m3/gnu/module_manager/src/tx_thread_interrupt_control.S @@ -0,0 +1,81 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ + + +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ + + + .text 32 + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_control Cortex-M3/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for changing the interrupt lockout */ +@/* posture of the system. */ +@/* */ +@/* INPUT */ +@/* */ +@/* new_posture New interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@/* UINT _tx_thread_interrupt_control(UINT new_posture) +{ */ + .global _tx_thread_interrupt_control + .thumb_func +_tx_thread_interrupt_control: + +@/* Pickup current interrupt lockout posture. */ + + MRS r1, PRIMASK @ Pickup current interrupt lockout + +@/* Apply the new interrupt posture. */ + + MSR PRIMASK, r0 @ Apply the new interrupt lockout + MOV r0, r1 @ Transfer old to return register + BX lr @ Return to caller + +@/* } */ diff --git a/ports_module/cortex-m3/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex-m3/gnu/module_manager/src/tx_thread_schedule.S new file mode 100644 index 00000000..643243d5 --- /dev/null +++ b/ports_module/cortex-m3/gnu/module_manager/src/tx_thread_schedule.S @@ -0,0 +1,524 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .global _tx_thread_current_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_system_stack_ptr + .global _tx_execution_thread_enter + .global _tx_execution_thread_exit + .global _tx_thread_preempt_disable + .global _txm_module_manager_memory_fault_handler + .global _txm_module_manager_memory_fault_info + + .text + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule Cortex-M3/MPU/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* _tx_thread_context_restore Restore thread's context */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_schedule(VOID) +// { + .global _tx_thread_schedule + .thumb_func +_tx_thread_schedule: + + /* This function should only ever be called on Cortex-M + from the first schedule request. Subsequent scheduling occurs + from the PendSV handling routines below. */ + + /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ + + MOV r0, #0 // Build value for TX_FALSE + LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag + STR r0, [r2, #0] // Clear preempt disable flag + + /* Enable memory fault registers. */ + + LDR r0, =0xE000ED24 // Build SHCSR address + LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults + STR r1, [r0] // + + /* Enable interrupts */ + + CPSIE i + + /* Enter the scheduler for the first time. */ + + MOV r0, #0x10000000 // Load PENDSVSET bit + MOV r1, #0xE000E000 // Load NVIC base + STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + DSB // Complete all memory accesses + ISB // Flush pipeline + + /* Wait here for the PendSV to take place. */ + +__tx_wait_here: + B __tx_wait_here // Wait for the PendSV to happen +// } + + + /* Memory Exception Handler. */ + .global MemManage_Handler + .global BusFault_Handler + .global UsageFault_Handler + .thumb_func +MemManage_Handler: + .thumb_func +BusFault_Handler: + .thumb_func +UsageFault_Handler: + + CPSID i // Disable interrupts + + /* Now pickup and store all the fault related information. */ + + LDR r12,=_txm_module_manager_memory_fault_info // Pickup fault info struct + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r0] // Pickup the current thread pointer + STR r1, [r12, #0] // Save current thread pointer in fault info structure + LDR r0, =0xE000ED24 // Build SHCSR address + LDR r1, [r0] // Pickup SHCSR + STR r1, [r12, #8] // Save SHCSR + LDR r0, =0xE000ED28 // Build CFSR address + LDR r1, [r0] // Pickup CFSR + STR r1, [r12, #12] // Save CFSR + LDR r0, =0xE000ED34 // Build MMFAR address + LDR r1, [r0] // Pickup MMFAR + STR r1, [r12, #16] // Save MMFAR + LDR r0, =0xE000ED38 // Build BFAR address + LDR r1, [r0] // Pickup BFAR + STR r1, [r12, #20] // Save BFAR + MRS r0, CONTROL // Pickup current CONTROL register + STR r0, [r12, #24] // Save CONTROL + MRS r1, PSP // Pickup thread stack pointer + STR r1, [r12, #28] // Save thread stack pointer + LDR r0, [r1] // Pickup saved r0 + STR r0, [r12, #32] // Save r0 + LDR r0, [r1, #4] // Pickup saved r1 + STR r0, [r12, #36] // Save r1 + STR r2, [r12, #40] // Save r2 + STR r3, [r12, #44] // Save r3 + STR r4, [r12, #48] // Save r4 + STR r5, [r12, #52] // Save r5 + STR r6, [r12, #56] // Save r6 + STR r7, [r12, #60] // Save r7 + STR r8, [r12, #64] // Save r8 + STR r9, [r12, #68] // Save r9 + STR r10,[r12, #72] // Save r10 + STR r11,[r12, #76] // Save r11 + LDR r0, [r1, #16] // Pickup saved r12 + STR r0, [r12, #80] // Save r12 + LDR r0, [r1, #20] // Pickup saved lr + STR r0, [r12, #84] // Save lr + LDR r0, [r1, #24] // Pickup instruction address at point of fault + STR r0, [r12, #4] // Save point of fault + LDR r0, [r1, #28] // Pickup xPSR + STR r0, [r12, #88] // Save xPSR + + MRS r0, CONTROL // Pickup current CONTROL register + BIC r0, r0, #1 // Clear the UNPRIV bit + MSR CONTROL, r0 // Setup new CONTROL register + + LDR r0, =0xE000ED28 // Build the Memory Management Fault Status Register (MMFSR) + LDRB r1, [r0] // Pickup the MMFSR, with the following bit definitions: + // Bit 0 = 1 -> Instruction address violation + // Bit 1 = 1 -> Load/store address violation + // Bit 7 = 1 -> MMFAR is valid + STRB r1, [r0] // Clear the MMFSR + + BL _txm_module_manager_memory_fault_handler // Call memory manager fault handler + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread exit function to indicate the thread is no longer executing. */ + + CPSID i // Disable interrupts + BL _tx_execution_thread_exit // Call the thread exit function + CPSIE i // Enable interrupts +#endif + + MOV r1, #0 // Build NULL value + LDR r0, =_tx_thread_current_ptr // Pickup address of current thread pointer + STR r1, [r0] // Clear current thread pointer + + // Return from MemManage_Handler exception + LDR r0, =0xE000ED04 // Load ICSR + LDR r1, =0x10000000 // Set PENDSVSET bit + STR r1, [r0] // Store ICSR + DSB // Wait for memory access to complete + CPSIE i // Enable interrupts + MOV lr, #0xFFFFFFFD // Load exception return code + BX lr // Return from exception + + + /* Generic context PendSV handler. */ + + .global PendSV_Handler + .global __tx_PendSVHandler + .syntax unified + .thumb_func +PendSV_Handler: + .thumb_func +__tx_PendSVHandler: + + /* Get current thread value and new thread pointer. */ + +__tx_ts_handler: + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread exit function to indicate the thread is no longer executing. */ + + CPSID i // Disable interrupts + PUSH {r0, lr} // Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit // Call the thread exit function + POP {r0, lr} // Recover LR + CPSIE i // Enable interrupts +#endif + + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address + MOV r3, #0 // Build NULL value + LDR r1, [r0] // Pickup current thread pointer + + /* Determine if there is a current thread to finish preserving. */ + + CBZ r1, __tx_ts_new // If NULL, skip preservation + + /* Recover PSP and preserve current thread context. */ + + STR r3, [r0] // Set _tx_thread_current_ptr to NULL + MRS r12, PSP // Pickup PSP pointer (thread's stack pointer) + STMDB r12!, {r4-r11} // Save its remaining registers + LDR r4, =_tx_timer_time_slice // Build address of time-slice variable + STMDB r12!, {LR} // Save LR on the stack + + /* Determine if time-slice is active. If it isn't, skip time handling processing. */ + + LDR r5, [r4] // Pickup current time-slice + STR r12, [r1, #8] // Save the thread stack pointer + CBZ r5, __tx_ts_new // If not active, skip processing + + /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ + + STR r5, [r1, #24] // Save current time-slice + + /* Clear the global time-slice. */ + + STR r3, [r4] // Clear time-slice + + /* Executing thread is now completely preserved!!! */ + +__tx_ts_new: + + /* Now we are looking for a new thread to execute! */ + + CPSID i // Disable interrupts + LDR r1, [r2] // Is there another thread ready to execute? + CBZ r1, __tx_ts_wait // No, skip to the wait processing + + /* Yes, another thread is ready for else, make the current thread the new thread. */ + + STR r1, [r0] // Setup the current thread pointer to the new thread + CPSIE i // Enable interrupts + + /* Increment the thread run count. */ + +__tx_ts_restore: + LDR r7, [r1, #4] // Pickup the current thread run count + LDR r4, =_tx_timer_time_slice // Build address of time-slice variable + LDR r5, [r1, #24] // Pickup thread's current time-slice + ADD r7, r7, #1 // Increment the thread run count + STR r7, [r1, #4] // Store the new run count + + /* Setup global time-slice with thread's current time-slice. */ + + STR r5, [r4] // Setup global time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread entry function to indicate the thread is executing. */ + + PUSH {r0, r1} // Save r0 and r1 + BL _tx_execution_thread_enter // Call the thread execution enter function + POP {r0, r1} // Recover r0 and r1 +#endif + + /* Restore the thread context and PSP. */ + + LDR r12, [r1, #8] // Pickup thread's stack pointer + + MRS r5, CONTROL // Pickup current CONTROL register + LDR r4, [r1, #0x98] // Pickup current user mode flag + BIC r5, r5, #1 // Clear the UNPRIV bit + ORR r4, r4, r5 // Build new CONTROL register + MSR CONTROL, r4 // Setup new CONTROL register + + LDR r0, =0xE000ED94 // Build MPU control reg address + MOV r3, #0 // Build disable value + STR r3, [r0] // Disable MPU + LDR r0, [r1, #0x90] // Pickup the module instance pointer + CBZ r0, skip_mpu_setup // Is this thread owned by a module? No, skip MPU setup + LDR r1, [r0, #0x64] // Pickup MPU register[0] + CBZ r1, skip_mpu_setup // Is protection required for this module? No, skip MPU setup + LDR r1, =0xE000ED9C // Build address of MPU base register + + // Use alias registers to quickly load MPU + ADD r0, r0, #100 // Build address of MPU register start in thread control block + LDM r0!,{r2-r9} // Load first four MPU regions + STM r1,{r2-r9} // Store first four MPU regions + LDM r0,{r2-r9} // Load second four MPU regions + STM r1,{r2-r9} // Store second four MPU regions + LDR r0, =0xE000ED94 // Build MPU control reg address + MOV r1, #5 // Build enable value with background region enabled + STR r1, [r0] // Enable MPU +skip_mpu_setup: + LDMIA r12!, {LR} // Pickup LR + LDMIA r12!, {r4-r11} // Recover thread's registers + MSR PSP, r12 // Setup the thread's stack pointer + + /* Return to thread. */ + + BX lr // Return to thread! + + /* The following is the idle wait processing... in this case, no threads are ready for execution and the + system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts + are disabled to allow use of WFI for waiting for a thread to arrive. */ + +__tx_ts_wait: + CPSID i // Disable interrupts + LDR r1, [r2] // Pickup the next thread to execute pointer + STR r1, [r0] // Store it in the current pointer + CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! +#ifdef TX_ENABLE_WFI + DSB // Ensure no outstanding memory transactions + WFI // Wait for interrupt + ISB // Ensure pipeline is flushed +#endif + CPSIE i // Enable interrupts + B __tx_ts_wait // Loop to continue waiting + + /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are + already in the handler! */ + +__tx_ts_ready: + MOV r7, #0x08000000 // Build clear PendSV value + MOV r8, #0xE000E000 // Build base NVIC address + STR r7, [r8, #0xD04] // Clear any PendSV + + /* Re-enable interrupts and restore new thread. */ + + CPSIE i // Enable interrupts + B __tx_ts_restore // Restore the thread + + + /* SVC Handler. */ + + .global SVC_Handler + .global __tx_SVCallHandler + .syntax unified + .thumb_func +SVC_Handler: + .thumb_func +__tx_SVCallHandler: + + MRS r0, PSP // Pickup the PSP stack + LDR r1, [r0, #24] // Pickup the point of interrupt + LDRB r2, [r1, #-2] // Pickup the SVC parameter + + /* Determine which SVC trap we are processing */ + + CMP r2, #1 // Is it the entry into ThreadX? + BNE _tx_thread_user_return // No, return to user mode + + /* At this point we have an SVC 1, which means we are entering + the kernel from a module thread with user mode selected. */ + + LDR r2, =_txm_module_priv // Load address of where we should have come from + CMP r1, r2 // Did we come from user_mode_entry? + IT NE // If no (not equal), then... + BXNE lr // return from where we came. + + LDR r3, [r0, #20] // This is the saved LR + LDR r1, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, [r1] // Pickup current thread pointer + MOV r1, #0 // Build clear value + STR r1, [r2, #0x98] // Clear the current user mode selection for thread + STR r3, [r2, #0xA0] // Save the original LR in thread control block + + /* If there is memory protection, use kernel stack */ + LDR r0, [r2, #0x90] // Load the module instance ptr + LDR r0, [r0, #0x0C] // Load the module property flags + TST r0, #2 // Check if memory protected + BEQ _tx_skip_kernel_stack_enter + + /* Switch to the module thread's kernel stack */ + LDR r0, [r2, #0xA8] // Load the module kernel stack end +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + LDR r1, [r2, #0xA4] // Load the module kernel stack start + LDR r3, [r2, #0xAC] // Load the module kernel stack size + STR r1, [r2, #12] // Set stack start + STR r0, [r2, #16] // Set stack end + STR r3, [r2, #20] // Set stack size +#endif + + MRS r3, PSP // Pickup thread stack pointer + STR r3, [r2, #0xB0] // Save thread stack pointer + + /* Build kernel stack by copying thread stack two registers at a time */ + ADD r3, r3, #32 // Start at bottom of hardware stack + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + + MSR PSP, r0 // Set kernel stack pointer + +_tx_skip_kernel_stack_enter: + MRS r0, CONTROL // Pickup current CONTROL register + BIC r0, r0, #1 // Clear the UNPRIV bit + MSR CONTROL, r0 // Setup new CONTROL register + BX lr // Return to thread + +_tx_thread_user_return: + LDR r2, =_txm_module_user_mode_exit // Load address of where we should have come from + CMP r1, r2 // Did we come from user_mode_exit? + IT NE // If no (not equal), then... + BXNE lr // return from where we came + + LDR r1, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, [r1] // Pickup current thread pointer + LDR r1, [r2, #0x9C] // Pick up user mode + STR r1, [r2, #0x98] // Set the current user mode selection for thread + + /* If there is memory protection, use kernel stack */ + LDR r0, [r2, #0x90] // Load the module instance ptr + LDR r0, [r0, #0x0C] // Load the module property flags + TST r0, #2 // Check if memory protected + BEQ _tx_skip_kernel_stack_exit + +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + LDR r0, [r2, #0xB4] // Load the module thread stack start + LDR r1, [r2, #0xB8] // Load the module thread stack end + LDR r3, [r2, #0xBC] // Load the module thread stack size + STR r0, [r2, #12] // Set stack start + STR r1, [r2, #16] // Set stack end + STR r3, [r2, #20] // Set stack size +#endif + LDR r0, [r2, #0xB0] // Load the module thread stack pointer + MRS r3, PSP // Pickup kernel stack pointer + + /* Copy kernel hardware stack to module thread stack. */ + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + SUB r0, r0, #32 // Subtract 32 to get back to top of stack + MSR PSP, r0 // Set thread stack pointer + + LDR r1, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, [r1] // Pickup current thread pointer + LDR r1, [r2, #0x9C] // Pick up user mode + +_tx_skip_kernel_stack_exit: + MRS r0, CONTROL // Pickup current CONTROL register + ORR r0, r0, r1 // OR in the user mode bit + MSR CONTROL, r0 // Setup new CONTROL register + BX lr // Return to thread + + + /* Kernel entry function from user mode. */ + + .global _txm_module_manager_kernel_dispatch + .align 5 + .syntax unified +// VOID _txm_module_manager_user_mode_entry(VOID) +// { + .global _txm_module_manager_user_mode_entry + .thumb_func +_txm_module_manager_user_mode_entry: + SVC 1 // Enter kernel +_txm_module_priv: + /* At this point, we are out of user mode. The original LR has been saved in the + thread control block. Simply call the kernel dispatch function. */ + BL _txm_module_manager_kernel_dispatch + + /* Pickup the original LR value while still in privileged mode */ + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r3, [r2] // Pickup current thread pointer + LDR lr, [r3, #0xA0] // Pickup saved LR from original call + + SVC 2 // Exit kernel and return to user mode +_txm_module_user_mode_exit: + BX lr // Return to the caller + NOP + NOP + NOP + NOP +// } diff --git a/ports_module/cortex-m3/gnu/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex-m3/gnu/module_manager/src/tx_thread_stack_build.S new file mode 100644 index 00000000..05a03d86 --- /dev/null +++ b/ports_module/cortex-m3/gnu/module_manager/src/tx_thread_stack_build.S @@ -0,0 +1,135 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ + .text + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_stack_build Cortex-M3/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function builds a stack frame on the supplied thread's stack. */ +@/* The stack frame results in a fake interrupt return to the supplied */ +@/* function pointer. */ +@/* */ +@/* INPUT */ +@/* */ +@/* thread_ptr Pointer to thread control blk */ +@/* function_ptr Pointer to return function */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_thread_create Create thread service */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +@{ + .global _tx_thread_stack_build + .thumb_func +_tx_thread_stack_build: +@ +@ +@ /* Build a fake interrupt frame. The form of the fake interrupt stack +@ on the Cortex-M3 should look like the following after it is built: +@ +@ Stack Top: +@ LR Interrupted LR (LR at time of PENDSV) +@ r4 Initial value for r4 +@ r5 Initial value for r5 +@ r6 Initial value for r6 +@ r7 Initial value for r7 +@ r8 Initial value for r8 +@ r9 Initial value for r9 +@ r10 Initial value for r10 +@ r11 Initial value for r11 +@ r0 Initial value for r0 (Hardware stack starts here!!) +@ r1 Initial value for r1 +@ r2 Initial value for r2 +@ r3 Initial value for r3 +@ r12 Initial value for r12 +@ lr Initial value for lr +@ pc Initial value for pc +@ xPSR Initial value for xPSR +@ +@ Stack Bottom: (higher memory address) */ +@ + LDR r2, [r0, #16] @ Pickup end of stack area + BIC r2, r2, #0x7 @ Align frame + SUB r2, r2, #68 @ Subtract frame size + LDR r3, =0xFFFFFFFD @ Build initial LR value + STR r3, [r2, #0] @ Save on the stack +@ +@ /* Actually build the stack frame. */ +@ + MOV r3, #0 @ Build initial register value + STR r3, [r2, #4] @ Store initial r4 + STR r3, [r2, #8] @ Store initial r5 + STR r3, [r2, #12] @ Store initial r6 + STR r3, [r2, #16] @ Store initial r7 + STR r3, [r2, #20] @ Store initial r8 + STR r3, [r2, #24] @ Store initial r9 + STR r3, [r2, #28] @ Store initial r10 + STR r3, [r2, #32] @ Store initial r11 +@ +@ /* Hardware stack follows. */ +@ + STR r3, [r2, #36] @ Store initial r0 + STR r3, [r2, #40] @ Store initial r1 + STR r3, [r2, #44] @ Store initial r2 + STR r3, [r2, #48] @ Store initial r3 + STR r3, [r2, #52] @ Store initial r12 + MOV r3, #0xFFFFFFFF @ Poison EXC_RETURN value + STR r3, [r2, #56] @ Store initial lr + STR r1, [r2, #60] @ Store initial pc + MOV r3, #0x01000000 @ Only T-bit need be set + STR r3, [r2, #64] @ Store initial xPSR +@ +@ /* Setup stack pointer. */ +@ thread_ptr -> tx_thread_stack_ptr = r2; +@ + STR r2, [r0, #8] @ Save stack pointer in thread's + @ control block + BX lr @ Return to caller +@} diff --git a/ports_module/cortex-m3/gnu/module_manager/src/tx_thread_system_return.S b/ports_module/cortex-m3/gnu/module_manager/src/tx_thread_system_return.S new file mode 100644 index 00000000..7804a65c --- /dev/null +++ b/ports_module/cortex-m3/gnu/module_manager/src/tx_thread_system_return.S @@ -0,0 +1,88 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ + + + .text 32 + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_system_return Cortex-M3/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is target processor specific. It is used to transfer */ +@/* control from a thread back to the ThreadX system. Only a */ +@/* minimal context is saved since the compiler assumes temp registers */ +@/* are going to get slicked by a function call anyway. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling loop */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX components */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@/* VOID _tx_thread_system_return(VOID) +@{ */ + .thumb_func + .global _tx_thread_system_return +_tx_thread_system_return: +@ +@ /* Return to real scheduler via PendSV. Note that this routine is often +@ replaced with in-line assembly in tx_port.h to improved performance. */ +@ + MOV r0, #0x10000000 @ Load PENDSVSET bit + MOV r1, #0xE000E000 @ Load NVIC base + STR r0, [r1, #0xD04] @ Set PENDSVBIT in ICSR + MRS r0, IPSR @ Pickup IPSR + CMP r0, #0 @ Is it a thread returning? + BNE _isr_context @ If ISR, skip interrupt enable + MRS r1, PRIMASK @ Thread context returning, pickup PRIMASK + CPSIE i @ Enable interrupts + MSR PRIMASK, r1 @ Restore original interrupt posture +_isr_context: + BX lr @ Return to caller + +@/* } */ diff --git a/ports_module/cortex-m3/gnu/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex-m3/gnu/module_manager/src/tx_timer_interrupt.S new file mode 100644 index 00000000..39721ec6 --- /dev/null +++ b/ports_module/cortex-m3/gnu/module_manager/src/tx_timer_interrupt.S @@ -0,0 +1,257 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Timer */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ + .global _tx_timer_time_slice + .global _tx_timer_system_clock + .global _tx_timer_current_ptr + .global _tx_timer_list_start + .global _tx_timer_list_end + .global _tx_timer_expired_time_slice + .global _tx_timer_expired + .global _tx_thread_time_slice + .global _tx_timer_expiration_process +@ +@ + .text + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_timer_interrupt Cortex-M3/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function processes the hardware timer interrupt. This */ +@/* processing includes incrementing the system clock and checking for */ +@/* time slice and/or timer expiration. If either is found, the */ +@/* interrupt context save/restore functions are called along with the */ +@/* expiration functions. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_timer_expiration_process Timer expiration processing */ +@/* _tx_thread_time_slice Time slice interrupted thread */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* interrupt vector */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_timer_interrupt(VOID) +@{ + .global _tx_timer_interrupt + .thumb_func +_tx_timer_interrupt: +@ +@ /* Upon entry to this routine, it is assumed that context save has already +@ been called, and therefore the compiler scratch registers are available +@ for use. */ +@ +@ /* Increment the system clock. */ +@ _tx_timer_system_clock++; +@ + LDR r1, =_tx_timer_system_clock @ Pickup address of system clock + LDR r0, [r1, #0] @ Pickup system clock + ADD r0, r0, #1 @ Increment system clock + STR r0, [r1, #0] @ Store new system clock +@ +@ /* Test for time-slice expiration. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice + LDR r2, [r3, #0] @ Pickup time-slice + CMP r2, #0 @ Is it non-active? + BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing +@ +@ /* Decrement the time_slice. */ +@ _tx_timer_time_slice--; +@ + SUB r2, r2, #1 @ Decrement the time-slice + STR r2, [r3, #0] @ Store new time-slice value +@ +@ /* Check for expiration. */ +@ if (__tx_timer_time_slice == 0) +@ + CMP r2, #0 @ Has it expired? + BNE __tx_timer_no_time_slice @ No, skip expiration processing +@ +@ /* Set the time-slice expired flag. */ +@ _tx_timer_expired_time_slice = TX_TRUE; +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of expired flag + MOV r0, #1 @ Build expired value + STR r0, [r3, #0] @ Set time-slice expiration flag +@ +@ } +@ +__tx_timer_no_time_slice: +@ +@ /* Test for timer expiration. */ +@ if (*_tx_timer_current_ptr) +@ { +@ + LDR r1, =_tx_timer_current_ptr @ Pickup current timer pointer address + LDR r0, [r1, #0] @ Pickup current timer + LDR r2, [r0, #0] @ Pickup timer list entry + CMP r2, #0 @ Is there anything in the list? + BEQ __tx_timer_no_timer @ No, just increment the timer +@ +@ /* Set expiration flag. */ +@ _tx_timer_expired = TX_TRUE; +@ + LDR r3, =_tx_timer_expired @ Pickup expiration flag address + MOV r2, #1 @ Build expired value + STR r2, [r3, #0] @ Set expired flag + B __tx_timer_done @ Finished timer processing +@ +@ } +@ else +@ { +__tx_timer_no_timer: +@ +@ /* No timer expired, increment the timer pointer. */ +@ _tx_timer_current_ptr++; +@ + ADD r0, r0, #4 @ Move to next timer +@ +@ /* Check for wrap-around. */ +@ if (_tx_timer_current_ptr == _tx_timer_list_end) +@ + LDR r3, =_tx_timer_list_end @ Pickup addr of timer list end + LDR r2, [r3, #0] @ Pickup list end + CMP r0, r2 @ Are we at list end? + BNE __tx_timer_skip_wrap @ No, skip wrap-around logic +@ +@ /* Wrap to beginning of list. */ +@ _tx_timer_current_ptr = _tx_timer_list_start; +@ + LDR r3, =_tx_timer_list_start @ Pickup addr of timer list start + LDR r0, [r3, #0] @ Set current pointer to list start +@ +__tx_timer_skip_wrap: +@ + STR r0, [r1, #0] @ Store new current timer pointer +@ } +@ +__tx_timer_done: +@ +@ +@ /* See if anything has expired. */ +@ if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +@ { +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of expired flag + LDR r2, [r3, #0] @ Pickup time-slice expired flag + CMP r2, #0 @ Did a time-slice expire? + BNE __tx_something_expired @ If non-zero, time-slice expired + LDR r1, =_tx_timer_expired @ Pickup addr of other expired flag + LDR r0, [r1, #0] @ Pickup timer expired flag + CMP r0, #0 @ Did a timer expire? + BEQ __tx_timer_nothing_expired @ No, nothing expired +@ +__tx_something_expired: +@ +@ + STMDB sp!, {r0, lr} @ Save the lr register on the stack + @ and save r0 just to keep 8-byte alignment +@ +@ /* Did a timer expire? */ +@ if (_tx_timer_expired) +@ { +@ + LDR r1, =_tx_timer_expired @ Pickup addr of expired flag + LDR r0, [r1, #0] @ Pickup timer expired flag + CMP r0, #0 @ Check for timer expiration + BEQ __tx_timer_dont_activate @ If not set, skip timer activation +@ +@ /* Process timer expiration. */ +@ _tx_timer_expiration_process(); +@ + BL _tx_timer_expiration_process @ Call the timer expiration handling routine +@ +@ } +__tx_timer_dont_activate: +@ +@ /* Did time slice expire? */ +@ if (_tx_timer_expired_time_slice) +@ { +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired + LDR r2, [r3, #0] @ Pickup the actual flag + CMP r2, #0 @ See if the flag is set + BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing +@ +@ /* Time slice interrupted thread. */ +@ _tx_thread_time_slice(); +@ + BL _tx_thread_time_slice @ Call time-slice processing + LDR r0, =_tx_thread_preempt_disable @ Build address of preempt disable flag + LDR r1, [r0] @ Is the preempt disable flag set? + CBNZ r1, __tx_timer_skip_time_slice @ Yes, skip the PendSV logic + LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address + LDR r1, [r0] @ Pickup the current thread pointer + LDR r2, =_tx_thread_execute_ptr @ Build execute thread pointer address + LDR r3, [r2] @ Pickup the execute thread pointer + LDR r0, =0xE000ED04 @ Build address of control register + LDR r2, =0x10000000 @ Build value for PendSV bit + CMP r1, r3 @ Are they the same? + BEQ __tx_timer_skip_time_slice @ If the same, there was no time-slice performed + STR r2, [r0] @ Not the same, issue the PendSV for preemption +__tx_timer_skip_time_slice: +@ +@ } +@ +__tx_timer_not_ts_expiration: +@ + LDMIA sp!, {r0, lr} @ Recover lr register (r0 is just there for + @ the 8-byte stack alignment +@ +@ } +@ +__tx_timer_nothing_expired: + + DSB @ Complete all memory access + BX lr @ Return to caller +@ +@} diff --git a/ports_module/cortex-m3/gnu/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex-m3/gnu/module_manager/src/txm_module_manager_alignment_adjust.c new file mode 100644 index 00000000..28486298 --- /dev/null +++ b/ports_module/cortex-m3/gnu/module_manager/src/txm_module_manager_alignment_adjust.c @@ -0,0 +1,399 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_power_of_two_block_size Cortex-M3/MPU/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calculates a power of two size at or immediately above*/ +/* the input size and returns it to the caller. */ +/* */ +/* INPUT */ +/* */ +/* size Block size */ +/* */ +/* OUTPUT */ +/* */ +/* calculated size Rounded up to power of two */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_power_of_two_block_size(ULONG size) +{ + /* Check for 0 size. */ + if(size == 0) + return 0; + + /* Minimum MPU block size is 32. */ + if(size <= 32) + return 32; + + /* Bit twiddling trick to round to next high power of 2 + (if original size is power of 2, it will return original size. Perfect!) */ + size--; + size |= size >> 1; + size |= size >> 2; + size |= size >> 4; + size |= size >> 8; + size |= size >> 16; + size++; + + /* Return a power of 2 size at or above the input size. */ + return(size); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_alignment_adjust Cortex-M3/MPU/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function adjusts the alignment and size of the code and data */ +/* section for a given module implementation. */ +/* */ +/* INPUT */ +/* */ +/* module_preamble Pointer to module preamble */ +/* code_size Size of the code area (updated) */ +/* code_alignment Code area alignment (updated) */ +/* data_size Size of data area (updated) */ +/* data_alignment Data area alignment (updated) */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_power_of_two_block_size Calculate power of two size */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, + ULONG *code_size, + ULONG *code_alignment, + ULONG *data_size, + ULONG *data_alignment) +{ + +ULONG local_code_size; +ULONG local_code_alignment; +ULONG local_data_size; +ULONG local_data_alignment; +ULONG code_block_size; +ULONG data_block_size; +ULONG code_size_accum; +ULONG data_size_accum; + + /* Copy the input parameters into local variables for ease of use. */ + local_code_size = *code_size; + local_code_alignment = *code_alignment; + local_data_size = *data_size; + local_data_alignment = *data_alignment; + + + /* Test for external memory enabled in preamble. */ + if(module_preamble -> txm_module_preamble_property_flags & TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS) + { + /* External/shared memory enabled. TXM_MODULE_MANAGER_CODE_MPU_ENTRIES-1 code entries will be used. */ + if (local_code_size <= (32*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 32 is best. */ + code_block_size = 32; + } + else if (local_code_size <= (64*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 64 is best. */ + code_block_size = 64; + } + else if (local_code_size <= (128*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 128 is best. */ + code_block_size = 128; + } + else if (local_code_size <= (256*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 256 is best. */ + code_block_size = 256; + } + else if (local_code_size <= (512*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 512 is best. */ + code_block_size = 512; + } + else if (local_code_size <= (1024*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 1024 is best. */ + code_block_size = 1024; + } + else if (local_code_size <= (2048*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 2048 is best. */ + code_block_size = 2048; + } + else if (local_code_size <= (4096*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 4096 is best. */ + code_block_size = 4096; + } + else if (local_code_size <= (8192*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 8192 is best. */ + code_block_size = 8192; + } + else if (local_code_size <= (16384*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 16384 is best. */ + code_block_size = 16384; + } + else if (local_code_size <= (32768*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 32768 is best. */ + code_block_size = 32768; + } + else if (local_code_size <= (65536*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 65536 is best. */ + code_block_size = 65536; + } + else if (local_code_size <= (131072*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 131072 is best. */ + code_block_size = 131072; + } + else if (local_code_size <= (262144*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 262144 is best. */ + code_block_size = 262144; + } + else if (local_code_size <= (524288*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 524288 is best. */ + code_block_size = 524288; + } + else if (local_code_size <= (1048576*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 1048576 is best. */ + code_block_size = 1048576; + } + else if (local_code_size <= (2097152*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 2097152 is best. */ + code_block_size = 2097152; + } + else if (local_code_size <= (4194304*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 4194304 is best. */ + code_block_size = 4194304; + } + else + { + /* Just set block size to 32MB just to create an allocation error! */ + code_block_size = 33554432; + } + + /* Calculate the new code size. */ + local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); + + /* Determine if the code block size is greater than the current alignment. If so, use block size + as the alignment. */ + if (code_block_size > local_code_alignment) + local_code_alignment = code_block_size; + + } + else + { + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + local_code_alignment = _txm_power_of_two_block_size(local_code_size) >> 2; + code_size_accum = local_code_alignment + local_code_alignment; + code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); + code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); + local_code_size = code_size_accum; + } + + /* Determine the best data block size, which in our case is the minimal alignment. */ + if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 32 is best. */ + data_block_size = 32; + } + else if (local_data_size <= (64*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 64 is best. */ + data_block_size = 64; + } + else if (local_data_size <= (128*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 128 is best. */ + data_block_size = 128; + } + else if (local_data_size <= (256*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 256 is best. */ + data_block_size = 256; + } + else if (local_data_size <= (512*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 512 is best. */ + data_block_size = 512; + } + else if (local_data_size <= (1024*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 1024 is best. */ + data_block_size = 1024; + } + else if (local_data_size <= (2048*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 2048 is best. */ + data_block_size = 2048; + } + else if (local_data_size <= (4096*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 4096 is best. */ + data_block_size = 4096; + } + else if (local_data_size <= (8192*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 8192 is best. */ + data_block_size = 8192; + } + else if (local_data_size <= (16384*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 16384 is best. */ + data_block_size = 16384; + } + else if (local_data_size <= (32768*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 32768 is best. */ + data_block_size = 32768; + } + else if (local_data_size <= (65536*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 65536 is best. */ + data_block_size = 65536; + } + else if (local_data_size <= (131072*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 131072 is best. */ + data_block_size = 131072; + } + else if (local_data_size <= (262144*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 262144 is best. */ + data_block_size = 262144; + } + else if (local_data_size <= (524288*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 524288 is best. */ + data_block_size = 524288; + } + else if (local_data_size <= (1048576*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 1048576 is best. */ + data_block_size = 1048576; + } + else if (local_data_size <= (2097152*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 2097152 is best. */ + data_block_size = 2097152; + } + else if (local_data_size <= (4194304*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 4194304 is best. */ + data_block_size = 4194304; + } + else + { + /* Just set data block size to 32MB just to create an allocation error! */ + data_block_size = 33554432; + } + + /* Calculate the new data size. */ + data_size_accum = data_block_size; + while(data_size_accum < local_data_size) + { + data_size_accum += data_block_size; + } + local_data_size = data_size_accum; + + /* Determine if the data block size is greater than the current alignment. If so, use block size + as the alignment. */ + if (data_block_size > local_data_alignment) + { + local_data_alignment = data_block_size; + } + + /* Return all the information to the caller. */ + *code_size = local_code_size; + *code_alignment = local_code_alignment; + *data_size = local_data_size; + *data_alignment = local_data_alignment; +} diff --git a/ports_module/cortex-m3/gnu/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex-m3/gnu/module_manager/src/txm_module_manager_external_memory_enable.c new file mode 100644 index 00000000..4647d857 --- /dev/null +++ b/ports_module/cortex-m3/gnu/module_manager/src/txm_module_manager_external_memory_enable.c @@ -0,0 +1,182 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_mutex.h" +#include "tx_queue.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_external_memory_enable Cortex-M3/MPU/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates an entry in the MPU table for a shared */ +/* memory space. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* start_address Start address of memory */ +/* length Length of external memory */ +/* attributes Memory attributes (r/w) */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_mutex_get Get protection mutex */ +/* _tx_mutex_put Release protection mutex */ +/* _txm_power_of_two_block_size Round length to power of two */ +/* _txm_module_manager_mm_register_setup Reconfigure MPU registers */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, + VOID *start_address, + ULONG length, + UINT attributes) +{ + +ULONG block_size; +ULONG region_size; +ULONG subregion_bits; +ULONG address; +UINT attributes_check = 0; +TXM_MODULE_PREAMBLE *module_preamble; + + /* Determine if the module manager has not been initialized yet. */ + if (_txm_module_manager_ready != TX_TRUE) + { + /* Module manager has not been initialized. */ + return(TX_NOT_AVAILABLE); + } + + /* Determine if the module is valid. */ + if (module_instance == TX_NULL) + { + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Get module manager protection mutex. */ + _tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER); + + /* Determine if the module instance is valid. */ + if (module_instance -> txm_module_instance_id != TXM_MODULE_ID) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Determine if the module instance is in the loaded state. */ + if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if the module is not ready. */ + return(TX_START_ERROR); + } + + /* Check if preamble shared mem and mem protection property bits are set. */ + module_preamble = module_instance -> txm_module_instance_preamble_ptr; + if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) + != (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if bit not set. */ + return(TXM_MODULE_INVALID_PROPERTIES); + } + + /* Start address and length must adhere to Cortex-M MPU. + The address must align with the block size. */ + + block_size = _txm_power_of_two_block_size(length); + address = (ULONG) start_address; + if(address != (address & ~(block_size - 1))) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return alignment error. */ + return(TXM_MODULE_ALIGNMENT_ERROR); + } + + /* At this point, we have a valid address and block size. + Set up MPU registers. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | 0x10; + + /* Calculate the region size. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + /* Calculate the subregion bits. */ + subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); + + /* Check for valid attributes. */ + if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) + { + attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; + } + + /* Build register with attributes. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX+1] = region_size | subregion_bits | attributes_check | 0x12070001; + + /* Keep track of shared memory address and length in module instance. */ + module_instance -> txm_module_instance_shared_memory_address = address; + module_instance -> txm_module_instance_shared_memory_length = length; + + /* Recalculate MPU settings. */ + _txm_module_manager_mm_register_setup(module_instance); + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/ports_module/cortex-m3/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex-m3/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c new file mode 100644 index 00000000..316b9cb9 --- /dev/null +++ b/ports_module/cortex-m3/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -0,0 +1,110 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + +/* Define a macro that can be used to allocate global variables useful to + store information about the last fault. This macro is defined in + txm_module_port.h and is usually populated in the assembly language + fault handling prior to the code calling _txm_module_manager_memory_fault_handler. */ + +TXM_MODULE_MANAGER_FAULT_INFO + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_handler Cortex-M3/MPU/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles a fault associated with a memory protected */ +/* module. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_terminate Terminate thread */ +/* */ +/* CALLED BY */ +/* */ +/* Fault handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_memory_fault_handler(VOID) +{ + +TXM_MODULE_INSTANCE *module_instance_ptr; +TX_THREAD *thread_ptr; + + /* Pickup the current thread. */ + thread_ptr = _tx_thread_current_ptr; + + /* Initialize the module instance pointer to NULL. */ + module_instance_ptr = TX_NULL; + + /* Is there a thread? */ + if (thread_ptr) + { + /* Pickup the module instance. */ + module_instance_ptr = thread_ptr -> tx_thread_module_instance_ptr; + + /* Terminate the current thread. */ + _tx_thread_terminate(_tx_thread_current_ptr); + } + + /* Determine if there is a user memory fault notification callback. */ + if (_txm_module_manager_fault_notify) + { + /* Yes, call the user's notification memory fault callback. */ + (_txm_module_manager_fault_notify)(thread_ptr, module_instance_ptr); + } +} diff --git a/ports_module/cortex-m3/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex-m3/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c new file mode 100644 index 00000000..75099528 --- /dev/null +++ b/ports_module/cortex-m3/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -0,0 +1,84 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the external user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_notify Cortex-M3/MPU/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application callback when/if a memory */ +/* fault occurs. The supplied thread is automatically terminated, but */ +/* any other threads in the same module may still execute. */ +/* */ +/* INPUT */ +/* */ +/* notify_function Memory fault notification */ +/* function, NULL disables. */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +{ + /* Setup notification function. */ + _txm_module_manager_fault_notify = notify_function; + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/ports_module/cortex-m3/gnu/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex-m3/gnu/module_manager/src/txm_module_manager_mm_register_setup.c new file mode 100644 index 00000000..24679cef --- /dev/null +++ b/ports_module/cortex-m3/gnu/module_manager/src/txm_module_manager_mm_register_setup.c @@ -0,0 +1,512 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_region_size_get Cortex-M3/MPU/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function converts the region size in bytes to the block size */ +/* for the Cortex-M3 MPU specification. */ +/* */ +/* INPUT */ +/* */ +/* block_size Size of the block in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* MPU size specification */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_module_manager_region_size_get(ULONG block_size) +{ + +ULONG return_value; + + /* Process relative to the input block size. */ + if (block_size == 32) + { + return_value = 0x04; + } + else if (block_size == 64) + { + return_value = 0x05; + } + else if (block_size == 128) + { + return_value = 0x06; + } + else if (block_size == 256) + { + return_value = 0x07; + } + else if (block_size == 512) + { + return_value = 0x08; + } + else if (block_size == 1024) + { + return_value = 0x09; + } + else if (block_size == 2048) + { + return_value = 0x0A; + } + else if (block_size == 4096) + { + return_value = 0x0B; + } + else if (block_size == 8192) + { + return_value = 0x0C; + } + else if (block_size == 16384) + { + return_value = 0x0D; + } + else if (block_size == 32768) + { + return_value = 0x0E; + } + else if (block_size == 65536) + { + return_value = 0x0F; + } + else if (block_size == 131072) + { + return_value = 0x10; + } + else if (block_size == 262144) + { + return_value = 0x11; + } + else if (block_size == 524288) + { + return_value = 0x12; + } + else if (block_size == 1048576) + { + return_value = 0x13; + } + else if (block_size == 2097152) + { + return_value = 0x14; + } + else + { + /* Max 4MB MPU pages for modules. */ + return_value = 0x15; + } + + return(return_value); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_calculate_srd_bits Cortex-M3/MPU/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calculates the SRD bits that need to be set to */ +/* protect "length" bytes in a block. */ +/* */ +/* INPUT */ +/* */ +/* block_size Size of the block in bytes */ +/* length Actual length in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* SRD bits to be OR'ed with region attribute register. */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) +{ + +ULONG srd_bits = 0; +UINT srd_bit_index; + + /* length is smaller than block_size, set SRD bits if block_size is 256 or more. */ + if((block_size >= 256) && (length < block_size)) + { + /* Divide block_size by 8 by shifting right 3. Result is size of subregion. */ + block_size = block_size >> 3; + + /* Set SRD index into attribute register. */ + srd_bit_index = 8; + + /* If subregion overlaps length, move to the next subregion. */ + while(length > block_size) + { + length = length - block_size; + srd_bit_index++; + } + /* Check for a portion of code remaining. */ + if(length) + { + srd_bit_index++; + } + + /* Set unused subregion bits. */ + while(srd_bit_index < 16) + { + srd_bits = srd_bits | (0x1 << srd_bit_index); + srd_bit_index++; + } + } + + return(srd_bits); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_mm_register_setup Cortex-M3/MPU/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets up the Cortex-M3 MPU register definitions based */ +/* on the module's memory characteristics. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* */ +/* OUTPUT */ +/* */ +/* MPU specifications for module in module_instance */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_manager_region_size_get */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_thread_create */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) +{ + +ULONG code_address; +ULONG code_size; +ULONG data_address; +ULONG data_size; +ULONG start_stop_stack_size; +ULONG callback_stack_size; +ULONG block_size; +ULONG base_address_register; +ULONG base_attribute_register; +ULONG region_size; +ULONG srd_bits = 0; +UINT mpu_register = 0; +UINT mpu_table_index; +UINT i; + + + /* Setup the first region for the ThreadX trampoline code. */ + /* Set base register to user mode entry, which is guaranteed to be at least 32-byte aligned. */ + base_address_register = (ULONG) _txm_module_manager_user_mode_entry; + + /* Mask address to proper range, region 0, set Valid bit. */ + base_address_register = (base_address_register & 0xFFFFFFE0) | mpu_register | 0x10; + module_instance -> txm_module_instance_mpu_registers[0] = base_address_register; + + /* Attributes: read only, write-back, shareable, size 32 bytes, region enabled. */ + module_instance -> txm_module_instance_mpu_registers[1] = 0x06070009; + + /* Initialize the MPU register. */ + mpu_register = 1; + + /* Initialize the MPU table index. */ + mpu_table_index = 2; + + /* Setup values for code area. */ + code_address = (ULONG) module_instance -> txm_module_instance_code_start; + code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; + + /* Check if shared memory was set up. If so, only 3 entries are available for + code protection. If not set up, 4 code entries are available. */ + if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] == 0) + { + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + + /* Now loop through to setup MPU protection for the code area. */ + for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES; i++) + { + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + if (i < 2) + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + } + + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ + else if (i == 2) + { + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size) >> 1; + } + + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + else + { + /* Calculate remaining space. */ + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + + /* Build the base address register. */ + base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Build the base attribute register. */ + base_attribute_register = region_size | srd_bits | 0x06070001; + + /* Setup the MPU Base Address Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; + + /* Setup the MPU Base Attribute Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; + + /* Adjust the code address. */ + code_address = code_address + block_size; + + /* Move MPU table index. */ + mpu_table_index = mpu_table_index + 2; + + /* Increment the MPU register index. */ + mpu_register++; + } + } + + /* Only 3 code entries available. */ + else + { + /* Calculate block size, one code entry taken up by shared memory. */ + block_size = _txm_power_of_two_block_size(code_size / (TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)); + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Now loop through to setup MPU protection for the code area. */ + for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) + { + /* Build the base address register. */ + base_address_register = code_address & ~(block_size - 1) | mpu_register | 0x10; + + /* Check if SRD bits need to be set. */ + if (code_size < block_size) + { + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + + /* Build the base attribute register. */ + base_attribute_register = region_size | srd_bits | 0x06070000; + + /* Is there still some code? If so set the region enable bit. */ + if (code_size) + { + /* Set the region enable bit. */ + base_attribute_register = base_attribute_register | 0x1; + } + /* Setup the MPU Base Address Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; + + /* Setup the MPU Base Attribute Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; + + /* Adjust the code address. */ + code_address = code_address + block_size; + + /* Decrement the code size. */ + if (code_size > block_size) + { + code_size = code_size - block_size; + } + else + { + code_size = 0; + } + + /* Move MPU table index. */ + mpu_table_index = mpu_table_index + 2; + + /* Increment the MPU register index. */ + mpu_register++; + } + + /* Adjust indeces to pass over the shared memory entry. */ + /* Move MPU table index. */ + mpu_table_index = mpu_table_index + 2; + + /* Increment the MPU register index. */ + mpu_register++; + } + + /* Setup values for data area. */ + data_address = (ULONG) module_instance -> txm_module_instance_data_start; + + /* Adjust the size of the module elements to be aligned to the default alignment. We do this + so that when we partition the allocated memory, we can simply place these regions right beside + each other without having to align their pointers. Note this only works when they all have + the same alignment. */ + + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; + start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; + callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; + + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + /* Update the data size to include thread stacks. */ + data_size = data_size + start_stop_stack_size + callback_stack_size; + + block_size = _txm_power_of_two_block_size(data_size / TXM_MODULE_MANAGER_DATA_MPU_ENTRIES); + + /* Reset SRD bitfield. */ + srd_bits = 0; + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Now loop through to setup MPU protection for the data area. */ + for (i = 0; i < TXM_MODULE_MANAGER_DATA_MPU_ENTRIES; i++) + { + /* Build the base address register. */ + base_address_register = (data_address & ~(block_size - 1)) | mpu_register | 0x10; + + /* Check if SRD bits need to be set. */ + if (data_size < block_size) + { + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + } + + /* Build the base attribute register. */ + base_attribute_register = region_size | srd_bits | 0x13070000; + + /* Is there still some data? If so set the region enable bit. */ + if (data_size) + { + /* Set the region enable bit. */ + base_attribute_register = base_attribute_register | 0x1; + } + + /* Setup the MPU Base Address Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; + + /* Setup the MPU Base Attribute Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; + + /* Adjust the data address. */ + data_address = data_address + block_size; + + /* Decrement the data size. */ + if (data_size > block_size) + { + data_size = data_size - block_size; + } + else + { + data_size = 0; + } + + /* Move MPU table index. */ + mpu_table_index = mpu_table_index + 2; + + /* Increment the MPU register index. */ + mpu_register++; + } +} diff --git a/ports_module/cortex-m3/gnu/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex-m3/gnu/module_manager/src/txm_module_manager_thread_stack_build.s new file mode 100644 index 00000000..9dff891d --- /dev/null +++ b/ports_module/cortex-m3/gnu/module_manager/src/txm_module_manager_thread_stack_build.s @@ -0,0 +1,139 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .align 4 + .syntax unified + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_thread_stack_build Cortex-M3/MPU/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread */ +/* function_ptr Pointer to shell function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +// { + .global _txm_module_manager_thread_stack_build + .thumb_func +_txm_module_manager_thread_stack_build: + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-M should look like the following after it is built: + + Stack Top: + LR Interrupted LR (LR at time of PENDSV) + r4 Initial value for r4 + r5 Initial value for r5 + r6 Initial value for r6 + r7 Initial value for r7 + r8 Initial value for r8 + r9 Initial value for r9 + r10 Initial value for r10 + r11 Initial value for r11 + r0 Initial value for r0 (Hardware stack starts here!!) + r1 Initial value for r1 + r2 Initial value for r2 + r3 Initial value for r3 + r12 Initial value for r12 + lr Initial value for lr + pc Initial value for pc + xPSR Initial value for xPSR + + Stack Bottom: (higher memory address) */ + + LDR r2, [r0, #16] // Pickup end of stack area + BIC r2, r2, #0x7 // Align frame + SUB r2, r2, #68 // Subtract frame size + LDR r3, =0xFFFFFFFD // Build initial LR value + STR r3, [r2, #0] // Save on the stack + + /* Actually build the stack frame. */ + + MOV r3, #0 // Build initial register value + STR r3, [r2, #4] // Store initial r4 + STR r3, [r2, #8] // Store initial r5 + STR r3, [r2, #12] // Store initial r6 + STR r3, [r2, #16] // Store initial r7 + STR r3, [r2, #20] // Store initial r8 + STR r3, [r2, #28] // Store initial r10 + STR r3, [r2, #32] // Store initial r11 + + /* Hardware stack follows. */ + + STR r0, [r2, #36] // Store initial r0, which is the thread control block + + LDR r3, [r0, #8] // Pickup thread entry info pointer,which is in the stack pointer position of the thread control block. + // It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this + // function with the actual, initial stack pointer. + STR r3, [r2, #40] // Store initial r1, which is the module entry information. + LDR r3, [r3, #8] // Pickup data base register from the module information + STR r3, [r2, #24] // Store initial r9 (data base register) + MOV r3, #0 // Clear r3 again + + STR r3, [r2, #44] // Store initial r2 + STR r3, [r2, #48] // Store initial r3 + STR r3, [r2, #52] // Store initial r12 + MOV r3, #0xFFFFFFFF // Poison EXC_RETURN value + STR r3, [r2, #56] // Store initial lr + STR r1, [r2, #60] // Store initial pc + MOV r3, #0x01000000 // Only T-bit need be set + STR r3, [r2, #64] // Store initial xPSR + + /* Setup stack pointer. */ + // thread_ptr -> tx_thread_stack_ptr = r2; + + STR r2, [r0, #8] // Save stack pointer in thread's control block + BX lr // Return to caller diff --git a/ports_module/cortex-m3/iar/example_build/sample_threadx.ewp b/ports_module/cortex-m3/iar/example_build/sample_threadx.ewp index dc053857..76441f03 100644 --- a/ports_module/cortex-m3/iar/example_build/sample_threadx.ewp +++ b/ports_module/cortex-m3/iar/example_build/sample_threadx.ewp @@ -349,11 +349,8 @@ @@ -657,7 +657,7 @@ @@ -2147,7 +2147,7 @@ $PROJ_DIR$\..\..\..\..\common\inc\tx_mutex.h - $PROJ_DIR$\..\module_common\inc\tx_port.h + $PROJ_DIR$\..\inc\tx_port.h $PROJ_DIR$\..\..\..\..\common\inc\tx_queue.h @@ -2168,7 +2168,7 @@ $PROJ_DIR$\..\..\..\..\common\inc\tx_user_sample.h - $PROJ_DIR$\..\..\..\..\common_modules\module_common\inc\txm_module.h + $PROJ_DIR$\..\..\..\..\common_modules\inc\txm_module.h $PROJ_DIR$\..\..\..\..\common_modules\module_manager\inc\txm_module_manager_dispatch.h @@ -2177,10 +2177,10 @@ $PROJ_DIR$\..\..\..\..\common_modules\module_manager\inc\txm_module_manager_util.h - $PROJ_DIR$\..\module_common\inc\txm_module_port.h + $PROJ_DIR$\..\inc\txm_module_port.h - $PROJ_DIR$\..\..\..\..\common_modules\module_common\inc\txm_module_user.h + $PROJ_DIR$\..\..\..\..\common_modules\inc\txm_module_user.h diff --git a/ports_module/cortex-m3/iar/example_build/tx_initialize_low_level.s b/ports_module/cortex-m3/iar/example_build/tx_initialize_low_level.s index ab6a346c..31d96174 100644 --- a/ports_module/cortex-m3/iar/example_build/tx_initialize_low_level.s +++ b/ports_module/cortex-m3/iar/example_build/tx_initialize_low_level.s @@ -55,7 +55,7 @@ __tx_free_memory_start ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level Cortex-M3/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -88,7 +88,7 @@ __tx_free_memory_start ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports_module/cortex-m3/iar/example_build/txm.ewp b/ports_module/cortex-m3/iar/example_build/txm.ewp index bb4b8745..7fa9f6c9 100644 --- a/ports_module/cortex-m3/iar/example_build/txm.ewp +++ b/ports_module/cortex-m3/iar/example_build/txm.ewp @@ -349,9 +349,9 @@ diff --git a/ports_module/cortex-m3/iar/example_build/txm_module_preamble.s b/ports_module/cortex-m3/iar/example_build/txm_module_preamble.s index 3dd55a1f..5488df2a 100644 --- a/ports_module/cortex-m3/iar/example_build/txm_module_preamble.s +++ b/ports_module/cortex-m3/iar/example_build/txm_module_preamble.s @@ -1,7 +1,7 @@ SECTION .text:CODE - AAPCS INTERWORK, ROPI, RWPI_COMPATIBLE, VFP_COMPATIBLE - PRESERVE8 + AAPCS INTERWORK, ROPI, RWPI_COMPATIBLE, VFP_COMPATIBLE + PRESERVE8 /* Define public symbols. */ @@ -15,59 +15,55 @@ /* Define common external refrences. */ - EXTERN _txm_module_thread_shell_entry - EXTERN _txm_module_callback_request_thread_entry - EXTERN ROPI$$Length - EXTERN RWPI$$Length + EXTERN _txm_module_thread_shell_entry + EXTERN _txm_module_callback_request_thread_entry + EXTERN ROPI$$Length + EXTERN RWPI$$Length - DATA + DATA __txm_module_preamble: - DC32 0x4D4F4455 ; Module ID - DC32 0x5 ; Module Major Version - DC32 0x6 ; Module Minor Version - DC32 32 ; Module Preamble Size in 32-bit words - DC32 0x12345678 ; Module ID (application defined) - DC32 0x00000007 ; Module Properties where: - ; Bits 31-24: Compiler ID - ; 0 -> IAR - ; 1 -> RVDS - ; 2 -> GNU - ; Bits 23-3: Reserved - ; Bit 2: 0 -> Disable shared/external memory access - ; 1 -> Enable shared/external memory access - ; Bit 1: 0 -> No MPU protection - ; 1 -> MPU protection (must have user mode selected - bit 0 set) - ; Bit 0: 0 -> Privileged mode execution - ; 1 -> User mode execution - - - DC32 _txm_module_thread_shell_entry - . - 0 ; Module Shell Entry Point - DC32 demo_module_start - . - 0 ; Module Start Thread Entry Point - DC32 0 ; Module Stop Thread Entry Point - DC32 1 ; Module Start/Stop Thread Priority - DC32 1022 ; Module Start/Stop Thread Stack Size - DC32 _txm_module_callback_request_thread_entry - . - 0 ; Module Callback Thread Entry - DC32 1 ; Module Callback Thread Priority - DC32 1022 ; Module Callback Thread Stack Size - DC32 ROPI$$Length ; Module Code Size - DC32 RWPI$$Length ; Module Data Size - DC32 0 ; Reserved 0 - DC32 0 ; Reserved 1 - DC32 0 ; Reserved 2 - DC32 0 ; Reserved 3 - DC32 0 ; Reserved 4 - DC32 0 ; Reserved 5 - DC32 0 ; Reserved 6 - DC32 0 ; Reserved 7 - DC32 0 ; Reserved 8 - DC32 0 ; Reserved 9 - DC32 0 ; Reserved 10 - DC32 0 ; Reserved 11 - DC32 0 ; Reserved 12 - DC32 0 ; Reserved 13 - DC32 0 ; Reserved 14 - DC32 0 ; Reserved 15 - - END - + DC32 0x4D4F4455 ; Module ID + DC32 0x6 ; Module Major Version + DC32 0x1 ; Module Minor Version + DC32 32 ; Module Preamble Size in 32-bit words + DC32 0x12345678 ; Module ID (application defined) + DC32 0x00000007 ; Module Properties where: + ; Bits 31-24: Compiler ID + ; 0 -> IAR + ; 1 -> RVDS + ; 2 -> GNU + ; Bits 23-3: Reserved + ; Bit 2: 0 -> Disable shared/external memory access + ; 1 -> Enable shared/external memory access + ; Bit 1: 0 -> No MPU protection + ; 1 -> MPU protection (must have user mode selected - bit 0 set) + ; Bit 0: 0 -> Privileged mode execution + ; 1 -> User mode execution + DC32 _txm_module_thread_shell_entry - . - 0 ; Module Shell Entry Point + DC32 demo_module_start - . - 0 ; Module Start Thread Entry Point + DC32 0 ; Module Stop Thread Entry Point + DC32 1 ; Module Start/Stop Thread Priority + DC32 1024 ; Module Start/Stop Thread Stack Size + DC32 _txm_module_callback_request_thread_entry - . - 0 ; Module Callback Thread Entry + DC32 1 ; Module Callback Thread Priority + DC32 1024 ; Module Callback Thread Stack Size + DC32 ROPI$$Length ; Module Code Size + DC32 RWPI$$Length ; Module Data Size + DC32 0 ; Reserved 0 + DC32 0 ; Reserved 1 + DC32 0 ; Reserved 2 + DC32 0 ; Reserved 3 + DC32 0 ; Reserved 4 + DC32 0 ; Reserved 5 + DC32 0 ; Reserved 6 + DC32 0 ; Reserved 7 + DC32 0 ; Reserved 8 + DC32 0 ; Reserved 9 + DC32 0 ; Reserved 10 + DC32 0 ; Reserved 11 + DC32 0 ; Reserved 12 + DC32 0 ; Reserved 13 + DC32 0 ; Reserved 14 + DC32 0 ; Reserved 15 + END diff --git a/ports_module/cortex-m3/iar/inc/tx_port.h b/ports_module/cortex-m3/iar/inc/tx_port.h index c4fa27a5..83017f77 100644 --- a/ports_module/cortex-m3/iar/inc/tx_port.h +++ b/ports_module/cortex-m3/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M3/IAR */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -386,7 +386,7 @@ __istate_t interrupt_save; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/IAR Version 6.0.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/IAR Version 6.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex-m3/iar/inc/txm_module_port.h b/ports_module/cortex-m3/iar/inc/txm_module_port.h index 87ea62fb..6e228d4d 100644 --- a/ports_module/cortex-m3/iar/inc/txm_module_port.h +++ b/ports_module/cortex-m3/iar/inc/txm_module_port.h @@ -10,44 +10,55 @@ /**************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ -/**************************************************************************/ -/* */ -/* APPLICATION INTERFACE DEFINITION RELEASE */ -/* */ -/* txm_module_port.h Cortex-M3/MPU/IAR */ -/* 6.0.1 */ +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* txm_module_port.h Cortex-M3/MPU/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This file defines the basic module constants, interface structures, */ -/* and function prototypes. */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the basic module constants, interface structures, */ +/* and function prototypes. */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H #define TXM_MODULE_PORT_H -/* It is assumed that the base ThreadX tx_port.h file has been modified to add the +/* Determine if the optional Modules user define file should be used. */ + +#ifdef TXM_MODULE_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in txm_module_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "txm_module_user.h" +#endif + +/* It is assumed that the base ThreadX tx_port.h file has been modified to add the following extensions to the ThreadX thread control block (this code should replace the corresponding macro define in tx_port.h): @@ -81,23 +92,11 @@ The following extensions must also be defined in tx_port.h: VOID (*tx_timer_module_expiration_function)(ULONG id); */ -#define TXM_MODULE_THREAD_ENTRY_INFO_USER_EXTENSION - -/**************************************************************************/ -/* User-adjustable constants */ -/**************************************************************************/ - /* Define the kernel stack size for a module thread. */ #ifndef TXM_MODULE_KERNEL_STACK_SIZE #define TXM_MODULE_KERNEL_STACK_SIZE 512 #endif -/**************************************************************************/ -/* End of user-adjustable constants */ -/**************************************************************************/ - - - /* Define constants specific to the tools the module can be built with for this particular modules port. */ #define TXM_MODULE_IAR_COMPILER 0x00000000 @@ -152,7 +151,7 @@ The following extensions must also be defined in tx_port.h: #define INLINE_DECLARE inline -/* Define the number of MPU entries assigned to the code and data sections. On Cortex-M parts, there can only be 7 total +/* Define the number of MPU entries assigned to the code and data sections. On Cortex-M parts, there can only be 7 total entries, since ThreadX uses one for access to the kernel dispatch function. */ #define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 @@ -180,8 +179,9 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr; VOID *txm_module_manager_memory_fault_info_code_location; ULONG txm_module_manager_memory_fault_info_shcsr; - ULONG txm_module_manager_memory_fault_info_mmfsr; + ULONG txm_module_manager_memory_fault_info_cfsr; ULONG txm_module_manager_memory_fault_info_mmfar; + ULONG txm_module_manager_memory_fault_info_bfar; ULONG txm_module_manager_memory_fault_info_control; ULONG txm_module_manager_memory_fault_info_sp; ULONG txm_module_manager_memory_fault_info_r0; @@ -205,10 +205,6 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT #define TXM_MODULE_MANAGER_FAULT_INFO \ TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info; -/* Define the macro to check the stack available in dispatch. */ -#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE - - /* Define the macro to check the code alignment. */ #define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment) \ @@ -293,30 +289,16 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT #define TXM_MODULE_MANAGER_MODULE_UNLOAD(module_instance) -/* Define the macro to perform port-specific functions when passing pointer to kernel. */ -/* Determine if the pointer is within the module's data or shared memory. */ -#define TXM_MODULE_MANAGER_CHECK_DATA_POINTER(module_instance, pointer) \ - if ((pointer < (ULONG) module_instance -> txm_module_instance_data_start) || \ - ((pointer+sizeof(pointer)) > (ULONG) module_instance -> txm_module_instance_data_end)) \ - { \ - if((pointer < module_instance -> txm_module_instance_shared_memory_address) || \ - ((pointer+sizeof(pointer)) > module_instance -> txm_module_instance_shared_memory_address \ - + module_instance -> txm_module_instance_shared_memory_length)) \ - { \ - return(TXM_MODULE_INVALID_MEMORY); \ - } \ - } - -/* Define the macro to perform port-specific functions when passing function pointer to kernel. */ -/* Determine if the pointer is within the module's code memory. */ -#define TXM_MODULE_MANAGER_CHECK_FUNCTION_POINTER(module_instance, pointer) \ - if (((pointer < sizeof(TXM_MODULE_PREAMBLE) + (ULONG) module_instance -> txm_module_instance_code_start) || \ - ((pointer+sizeof(pointer)) > (ULONG) module_instance -> txm_module_instance_code_end)) \ - && (pointer != (ULONG) TX_NULL)) \ - { \ - return(TX_PTR_ERROR); \ - } +/* Define the macros to perform port-specific checks when passing pointers to the kernel. */ +/* Define macro to make sure object is inside the module's data. */ +#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ + /* Check if it's inside module data. */ \ + ((((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && \ + (((obj_ptr) + (obj_size)) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) || \ + /* Check if it's inside shared memory. */ \ + (((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address) && \ + (((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (module_instance -> txm_module_instance_shared_memory_address + module_instance -> txm_module_instance_shared_memory_length)))) /* Define some internal prototypes to this module port. */ @@ -326,21 +308,17 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT #endif -#define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES \ +#define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES \ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment); \ -VOID _txm_module_manager_memory_fault_handler(VOID); \ -UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)); \ -VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \ -ULONG _txm_power_of_two_block_size(ULONG size); \ -ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); \ -ULONG _txm_module_manager_region_size_get(ULONG block_size); \ -UCHAR _txm_module_manager_shared_memory_check_outside(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size); \ -UCHAR _txm_module_manager_shared_memory_check_inside(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size); \ -UCHAR _txm_module_manager_shared_memory_check_inside_byte(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr); +VOID _txm_module_manager_memory_fault_handler(VOID); \ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)); \ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \ +ULONG _txm_power_of_two_block_size(ULONG size); \ +ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); \ +ULONG _txm_module_manager_region_size_get(ULONG block_size); #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3/MPU/IAR Version 6.0.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3/MPU/IAR Version 6.1 *"; #endif - diff --git a/ports_module/cortex-m3/iar/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex-m3/iar/module_lib/src/txm_module_thread_shell_entry.c index 3db7757a..bac4233a 100644 --- a/ports_module/cortex-m3/iar/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex-m3/iar/module_lib/src/txm_module_thread_shell_entry.c @@ -10,15 +10,15 @@ /**************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #ifndef TXM_MODULE #define TXM_MODULE @@ -44,54 +44,54 @@ TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3); -/* Define the IAR startup code that clears the uninitialized global data and sets up the +/* Define the IAR startup code that clears the uninitialized global data and sets up the preset global variables. */ extern VOID __iar_data_init3(VOID); -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_thread_shell_entry Cortex-M3/MPU/IAR */ -/* 6.0.1 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_thread_shell_entry Cortex-M3/MPU/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function calls the specified entry function of the thread. It */ -/* also provides a place for the thread's entry function to return. */ -/* If the thread returns, this function places the thread in a */ -/* "COMPLETED" state. */ -/* */ -/* INPUT */ -/* */ -/* thread_ptr Pointer to current thread */ -/* thread_info Pointer to thread entry info */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* __iar_data_init3 IAR global initialization function*/ -/* thread_entry Thread's entry function */ -/* tx_thread_resume Resume the module callback thread */ -/* _txm_module_thread_system_suspend Module thread suspension routine */ -/* */ -/* CALLED BY */ -/* */ -/* Initial thread stack frame */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function calls the specified entry function of the thread. It */ +/* also provides a place for the thread's entry function to return. */ +/* If the thread returns, this function places the thread in a */ +/* "COMPLETED" state. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to current thread */ +/* thread_info Pointer to thread entry info */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __iar_data_init3 IAR global initialization function*/ +/* thread_entry Thread's entry function */ +/* tx_thread_resume Resume the module callback thread */ +/* _txm_module_thread_system_suspend Module thread suspension routine */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) @@ -102,25 +102,23 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN #endif - /* Determine if this is the start thread. If so, we must prepare the module for + /* Determine if this is the start thread. If so, we must prepare the module for execution. If not, simply skip the C startup code. */ if (thread_info -> txm_module_thread_entry_info_start_thread) { - /* Initialize the IAR C environment. */ __iar_data_init3(); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - - /* Save the kernel function dispatch address. This is used to make all resident calls from + + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { - /* Loop here, if an error is present getting the dispatch function pointer! An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ @@ -165,7 +163,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN #endif /* Call actual thread suspension routine. */ - _txm_module_thread_system_suspend(thread_ptr); + _txm_module_thread_system_suspend(thread_ptr); #ifdef TX_SAFETY_CRITICAL diff --git a/ports_module/cortex-m3/iar/module_manager/src/tx_misra.s b/ports_module/cortex-m3/iar/module_manager/src/tx_misra.s index f6a6c3a5..a999ea98 100644 --- a/ports_module/cortex-m3/iar/module_manager/src/tx_misra.s +++ b/ports_module/cortex-m3/iar/module_manager/src/tx_misra.s @@ -101,7 +101,7 @@ SECTION `.data`:DATA:REORDER:NOROOT(2) DATA -// 51 CHAR _tx_version_id[100] = "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX 6.0.1 MISRA C Compliant *"; +// 51 CHAR _tx_version_id[100] = "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX 6.1 MISRA C Compliant *"; _tx_version_id: DC8 43H, 6FH, 70H, 79H, 72H, 69H, 67H, 68H DC8 74H, 20H, 28H, 63H, 29H, 20H, 31H, 39H diff --git a/ports_module/cortex-m3/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex-m3/iar/module_manager/src/tx_thread_context_restore.s index e3e42286..9842f8ce 100644 --- a/ports_module/cortex-m3/iar/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex-m3/iar/module_manager/src/tx_thread_context_restore.s @@ -21,33 +21,25 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE + EXTERN _tx_execution_isr_exit ; ; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; - EXTERN _tx_execution_isr_exit -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore Cortex-M3/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ ;/* This function restores the interrupt context if it is processing a */ ;/* nested interrupt. If not, it returns to the interrupt thread if no */ ;/* preemption is necessary. Otherwise, if preemption is necessary or */ @@ -73,7 +65,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) @@ -94,4 +86,4 @@ _tx_thread_context_restore: BX lr ; ;} - END + END diff --git a/ports_module/cortex-m3/iar/module_manager/src/tx_thread_context_save.s b/ports_module/cortex-m3/iar/module_manager/src/tx_thread_context_save.s index 49e11d68..23462fdc 100644 --- a/ports_module/cortex-m3/iar/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex-m3/iar/module_manager/src/tx_thread_context_save.s @@ -21,33 +21,25 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE + EXTERN _tx_execution_isr_enter ; ; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; - EXTERN _tx_execution_isr_enter -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save Cortex-M3/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ ;/* This function saves the context of an executing thread in the */ ;/* beginning of interrupt processing. The function also ensures that */ ;/* the system stack is used upon return to the calling ISR. */ @@ -72,7 +64,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -82,7 +74,7 @@ _tx_thread_context_save: #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY ; ; /* Call the ISR enter function to indicate an ISR is starting. */ -; +; PUSH {r0, lr} ; Save return address BL _tx_execution_isr_enter ; Call the ISR enter function POP {r0, lr} ; Recover return address @@ -93,4 +85,3 @@ _tx_thread_context_save: BX lr ;} END - diff --git a/ports_module/cortex-m3/iar/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex-m3/iar/module_manager/src/tx_thread_interrupt_control.s index d956fd6d..2c8bf932 100644 --- a/ports_module/cortex-m3/iar/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex-m3/iar/module_manager/src/tx_thread_interrupt_control.s @@ -20,23 +20,15 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE ; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control Cortex-M3/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -66,7 +58,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) @@ -83,4 +75,3 @@ _tx_thread_interrupt_control: ; ;} END - diff --git a/ports_module/cortex-m3/iar/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex-m3/iar/module_manager/src/tx_thread_interrupt_disable.s index 38a2083d..af919f6f 100644 --- a/ports_module/cortex-m3/iar/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex-m3/iar/module_manager/src/tx_thread_interrupt_disable.s @@ -20,23 +20,15 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE ; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-M3/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -66,7 +58,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(UINT new_posture) diff --git a/ports_module/cortex-m3/iar/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex-m3/iar/module_manager/src/tx_thread_interrupt_restore.s index 356c8aac..a10b571f 100644 --- a/ports_module/cortex-m3/iar/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex-m3/iar/module_manager/src/tx_thread_interrupt_restore.s @@ -20,23 +20,15 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE ; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-M3/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -66,7 +58,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_interrupt_restore(UINT new_posture) diff --git a/ports_module/cortex-m3/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex-m3/iar/module_manager/src/tx_thread_schedule.s index 20ce37cc..7d212b73 100644 --- a/ports_module/cortex-m3/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex-m3/iar/module_manager/src/tx_thread_schedule.s @@ -12,8 +12,8 @@ ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -21,67 +21,58 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_execution_thread_enter + EXTERN _tx_execution_thread_exit + EXTERN _tx_thread_preempt_disable + EXTERN _txm_module_manager_memory_fault_handler + EXTERN _txm_module_manager_memory_fault_info ; ; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; - EXTERN _tx_thread_current_ptr - EXTERN _tx_thread_execute_ptr - EXTERN _tx_timer_time_slice - EXTERN _tx_thread_system_stack_ptr - EXTERN _tx_execution_thread_enter - EXTERN _tx_execution_thread_exit - EXTERN _tx_thread_preempt_disable - EXTERN _txm_module_manager_memory_fault_handler - EXTERN _txm_module_manager_memory_fault_info -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_schedule Cortex-M3/MPU/IAR */ -;/* 6.0.1 */ + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-M3/MPU/IAR */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ ;/* None */ -;/* */ -;/* CALLS */ -;/* */ +;/* */ +;/* OUTPUT */ +;/* */ ;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -94,7 +85,7 @@ _tx_thread_schedule: ; from the PendSV handling routines below. */ ; ; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ -; +; MOV r0, #0 ; Build value for TX_FALSE LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag STR r0, [r2, #0] ; Clear preempt disable flag @@ -103,26 +94,24 @@ _tx_thread_schedule: ; LDR r0, =0xE000ED24 ; Build SHCSR address LDR r1, =0x70000 ; Enable Usage, Bus, and MemManage faults - STR r1, [r0] ; + STR r1, [r0] ; ; ; /* Enable interrupts */ ; CPSIE i -; +; ; /* Enter the scheduler for the first time. */ ; MOV r0, #0x10000000 ; Load PENDSVSET bit MOV r1, #0xE000E000 ; Load NVIC base STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR - NOP ; - NOP ; - NOP ; - NOP ; -; -; /* We should never get here - ever! */ -; - BKPT 0xEF ; Setup error conditions - BX lr ; + DSB ; Complete all memory accesses + ISB ; Flush pipeline + +; /* Wait here for the PendSV to take place. */ + +__tx_wait_here: + B __tx_wait_here ; Wait for the PendSV to happen ;} ; @@ -130,7 +119,11 @@ _tx_thread_schedule: ; /* Memory Exception Handler. */ ; PUBLIC MemManage_Handler + PUBLIC BusFault_Handler + PUBLIC UsageFault_Handler MemManage_Handler: +BusFault_Handler: +UsageFault_Handler: ;{ CPSID i ; Disable interrupts ; @@ -143,41 +136,44 @@ MemManage_Handler: LDR r0, =0xE000ED24 ; Build SHCSR address LDR r1, [r0] ; Pickup SHCSR STR r1, [r12, #8] ; Save SHCSR - LDR r0, =0xE000ED28 ; Build MMFSR address - LDR r1, [r0] ; Pickup MMFSR (and other fault status too!) - STR r1, [r12, #12] ; Save MMFSR + LDR r0, =0xE000ED28 ; Build CFSR address + LDR r1, [r0] ; Pickup CFSR + STR r1, [r12, #12] ; Save CFSR LDR r0, =0xE000ED34 ; Build MMFAR address LDR r1, [r0] ; Pickup MMFAR STR r1, [r12, #16] ; Save MMFAR + LDR r0, =0xE000ED38 ; Build BFAR address + LDR r1, [r0] ; Pickup BFAR + STR r1, [r12, #20] ; Save BFAR MRS r0, CONTROL ; Pickup current CONTROL register - STR r0, [r12, #20] ; Save CONTROL + STR r0, [r12, #24] ; Save CONTROL MRS r1, PSP ; Pickup thread stack pointer - STR r1, [r12, #24] ; Save thread stack pointer + STR r1, [r12, #28] ; Save thread stack pointer LDR r0, [r1] ; Pickup saved r0 - STR r0, [r12, #28] ; Save r0 + STR r0, [r12, #32] ; Save r0 LDR r0, [r1, #4] ; Pickup saved r1 - STR r0, [r12, #32] ; Save r1 - STR r2, [r12, #36] ; Save r2 - STR r3, [r12, #40] ; Save r3 - STR r4, [r12, #44] ; Save r4 - STR r5, [r12, #48] ; Save r5 - STR r6, [r12, #52] ; Save r6 - STR r7, [r12, #56] ; Save r7 - STR r8, [r12, #60] ; Save r8 - STR r9, [r12, #64] ; Save r9 - STR r10,[r12, #68] ; Save r10 - STR r11,[r12, #72] ; Save r11 + STR r0, [r12, #36] ; Save r1 + STR r2, [r12, #40] ; Save r2 + STR r3, [r12, #44] ; Save r3 + STR r4, [r12, #48] ; Save r4 + STR r5, [r12, #52] ; Save r5 + STR r6, [r12, #56] ; Save r6 + STR r7, [r12, #60] ; Save r7 + STR r8, [r12, #64] ; Save r8 + STR r9, [r12, #68] ; Save r9 + STR r10,[r12, #72] ; Save r10 + STR r11,[r12, #76] ; Save r11 LDR r0, [r1, #16] ; Pickup saved r12 - STR r0, [r12, #76] ; Save r12 + STR r0, [r12, #80] ; Save r12 LDR r0, [r1, #20] ; Pickup saved lr - STR r0, [r12, #80] ; Save lr + STR r0, [r12, #84] ; Save lr LDR r0, [r1, #24] ; Pickup instruction address at point of fault STR r0, [r12, #4] ; Save point of fault LDR r0, [r1, #28] ; Pickup xPSR - STR r0, [r12, #84] ; Save xPSR + STR r0, [r12, #88] ; Save xPSR MRS r0, CONTROL ; Pickup current CONTROL register - BIC r0, r0, #1 ; Clear the UNPRIV bit + BIC r0, r0, #1 ; Clear the UNPRIV bit MSR CONTROL, r0 ; Setup new CONTROL register LDR r0, =0xE000ED28 ; Build the Memory Management Fault Status Register (MMFSR) @@ -214,15 +210,15 @@ MemManage_Handler: ; ; /* Generic context PendSV handler. */ -; +; PUBLIC PendSV_Handler PUBLIC __tx_PendSVHandler PendSV_Handler: __tx_PendSVHandler: ; ; /* Get current thread value and new thread pointer. */ -; -__tx_ts_handler: +; +__tx_ts_handler: #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY ; @@ -240,7 +236,7 @@ __tx_ts_handler: LDR r1, [r0] ; Pickup current thread pointer ; ; /* Determine if there is a current thread to finish preserving. */ -; +; CBZ r1, __tx_ts_new ; If NULL, skip preservation ; ; /* Recover PSP and preserve current thread context. */ @@ -309,7 +305,7 @@ __tx_ts_restore: MRS r5, CONTROL ; Pickup current CONTROL register LDR r4, [r1, #0x98] ; Pickup current user mode flag - BIC r5, r5, #1 ; Clear the UNPRIV bit + BIC r5, r5, #1 ; Clear the UNPRIV bit ORR r4, r4, r5 ; Build new CONTROL register MSR CONTROL, r4 ; Setup new CONTROL register @@ -318,7 +314,7 @@ __tx_ts_restore: STR r3, [r0] ; Disable MPU LDR r0, [r1, #0x90] ; Pickup the module instance pointer CBZ r0, skip_mpu_setup ; Is this thread owned by a module? No, skip MPU setup - LDR r1, [r0, #0x64] ; Pickup MPU register[0] + LDR r1, [r0, #0x64] ; Pickup MPU register[0] CBZ r1, skip_mpu_setup ; Is protection required for this module? No, skip MPU setup LDR r1, =0xE000ED9C ; Build address of MPU base register @@ -329,7 +325,7 @@ __tx_ts_restore: LDM r0,{r2-r9} ; Load second four MPU regions STM r1,{r2-r9} ; Store second four MPU regions LDR r0, =0xE000ED94 ; Build MPU control reg address - MOV r1, #5 ; Build enable value + MOV r1, #5 ; Build enable value with background region enabled STR r1, [r0] ; Enable MPU skip_mpu_setup: LDMIA r12!, {LR} ; Pickup LR @@ -337,11 +333,11 @@ skip_mpu_setup: MSR PSP, r12 ; Setup the thread's stack pointer ; ; /* Return to thread. */ -; +; BX lr ; Return to thread! ; ; /* The following is the idle wait processing... in this case, no threads are ready for execution and the -; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts ; are disabled to allow use of WFI for waiting for a thread to arrive. */ ; __tx_ts_wait: @@ -357,16 +353,16 @@ __tx_ts_wait: CPSIE i ; Enable interrupts B __tx_ts_wait ; Loop to continue waiting ; -; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are ; already in the handler! */ ; __tx_ts_ready: MOV r7, #0x08000000 ; Build clear PendSV value MOV r8, #0xE000E000 ; Build base NVIC address - STR r7, [r8, #0xD04] ; Clear any PendSV + STR r7, [r8, #0xD04] ; Clear any PendSV ; ; /* Re-enable interrupts and restore new thread. */ -; +; CPSIE i ; Enable interrupts B __tx_ts_restore ; Restore the thread ;} @@ -394,7 +390,7 @@ __tx_SVCallHandler: CMP r1, r2 ; Did we come from user_mode_entry? IT NE ; If no (not equal), then... BXNE lr ; return from where we came. - + LDR r3, [r0, #20] ; This is the saved LR LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address LDR r2, [r1] ; Pickup current thread pointer @@ -403,73 +399,72 @@ __tx_SVCallHandler: STR r3, [r2, #0xA0] ; Save the original LR in thread control block ; If there is memory protection, use kernel stack - LDR r0, [r2, #0x90] ; Load the module instance ptr - LDR r0, [r0, #0x0C] ; Load the module property flags - TST r0, #2 ; Check if memory protected + LDR r0, [r2, #0x90] ; Load the module instance ptr + LDR r0, [r0, #0x0C] ; Load the module property flags + TST r0, #2 ; Check if memory protected BEQ _tx_skip_kernel_stack_enter ; Switch to the module thread's kernel stack - LDR r0, [r2, #0xA8] ; Load the module kernel stack end + LDR r0, [r2, #0xA8] ; Load the module kernel stack end #ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE - LDR r1, [r2, #0xA4] ; Load the module kernel stack start - LDR r3, [r2, #0xAC] ; Load the module kernel stack size - STR r1, [r2, #12] ; Set stack start - STR r0, [r2, #16] ; Set stack end - STR r3, [r2, #20] ; Set stack size + LDR r1, [r2, #0xA4] ; Load the module kernel stack start + LDR r3, [r2, #0xAC] ; Load the module kernel stack size + STR r1, [r2, #12] ; Set stack start + STR r0, [r2, #16] ; Set stack end + STR r3, [r2, #20] ; Set stack size #endif - MRS r3, PSP ; Pickup thread stack pointer - STR r3, [r2, #0xB0] ; Save thread stack pointer + MRS r3, PSP ; Pickup thread stack pointer + STR r3, [r2, #0xB0] ; Save thread stack pointer ; Build kernel stack by copying thread stack two registers at a time - ADD r3, r3, #32 ; start at bottom of hardware stack - LDMDB r3!,{r1-r2} ; - STMDB r0!,{r1-r2} ; - LDMDB r3!,{r1-r2} ; - STMDB r0!,{r1-r2} ; - LDMDB r3!,{r1-r2} ; - STMDB r0!,{r1-r2} ; - LDMDB r3!,{r1-r2} ; - STMDB r0!,{r1-r2} ; + ADD r3, r3, #32 ; start at bottom of hardware stack + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} - MSR PSP, r0 ; Set kernel stack pointer - -_tx_skip_kernel_stack_enter: + MSR PSP, r0 ; Set kernel stack pointer + +_tx_skip_kernel_stack_enter: MRS r0, CONTROL ; Pickup current CONTROL register - BIC r0, r0, #1 ; Clear the UNPRIV bit + BIC r0, r0, #1 ; Clear the UNPRIV bit MSR CONTROL, r0 ; Setup new CONTROL register BX lr ; Return to thread _tx_thread_user_return: - LDR r2, =_txm_module_user_mode_exit-1 ; Subtract 1 because of THUMB mode. CMP r1, r2 ; Did we come from user_mode_exit? IT NE ; If no (not equal), then... BXNE lr ; return from where we came - + LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address LDR r2, [r1] ; Pickup current thread pointer LDR r1, [r2, #0x9C] ; Pick up user mode STR r1, [r2, #0x98] ; Set the current user mode selection for thread ; If there is memory protection, use kernel stack - LDR r0, [r2, #0x90] ; Load the module instance ptr - LDR r0, [r0, #0x0C] ; Load the module property flags - TST r0, #2 ; Check if memory protected + LDR r0, [r2, #0x90] ; Load the module instance ptr + LDR r0, [r0, #0x0C] ; Load the module property flags + TST r0, #2 ; Check if memory protected BEQ _tx_skip_kernel_stack_exit - -#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE - LDR r0, [r2, #0xB4] ; Load the module thread stack start - LDR r1, [r2, #0xB8] ; Load the module thread stack end - LDR r3, [r2, #0xBC] ; Load the module thread stack size - STR r0, [r2, #12] ; Set stack start - STR r1, [r2, #16] ; Set stack end - STR r3, [r2, #20] ; Set stack size -#endif - LDR r0, [r2, #0xB0] ; Load the module thread stack pointer - MRS r3, PSP ; Pickup kernel stack pointer - ; Copy kernel hardware stack to module thread stack. +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + LDR r0, [r2, #0xB4] ; Load the module thread stack start + LDR r1, [r2, #0xB8] ; Load the module thread stack end + LDR r3, [r2, #0xBC] ; Load the module thread stack size + STR r0, [r2, #12] ; Set stack start + STR r1, [r2, #16] ; Set stack end + STR r3, [r2, #20] ; Set stack size +#endif + LDR r0, [r2, #0xB0] ; Load the module thread stack pointer + MRS r3, PSP ; Pickup kernel stack pointer + + ; Copy kernel hardware stack to module thread stack. LDM r3!,{r1-r2} STM r0!,{r1-r2} LDM r3!,{r1-r2} @@ -478,13 +473,13 @@ _tx_thread_user_return: STM r0!,{r1-r2} LDM r3!,{r1-r2} STM r0!,{r1-r2} - SUB r0, r0, #32 ; Subtract 32 to get back to top of stack - MSR PSP, r0 ; Set thread stack pointer + SUB r0, r0, #32 ; Subtract 32 to get back to top of stack + MSR PSP, r0 ; Set thread stack pointer LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address LDR r2, [r1] ; Pickup current thread pointer LDR r1, [r2, #0x9C] ; Pick up user mode - + _tx_skip_kernel_stack_exit: MRS r0, CONTROL ; Pickup current CONTROL register ORR r0, r0, r1 ; OR in the user mode bit @@ -509,7 +504,7 @@ _txm_module_priv: ; At this point, we are out of user mode. The original LR has been saved in the ; thread control block. Simply call the kernel dispatch function. BL _txm_module_manager_kernel_dispatch - + ; Pickup the original LR value while still in privileged mode LDR r2, =_tx_thread_current_ptr ; Build current thread pointer address LDR r3, [r2] ; Pickup current thread pointer @@ -517,7 +512,7 @@ _txm_module_priv: SVC 2 ; Exit kernel and return to user mode _txm_module_user_mode_exit: - BX lr ; Return to the caller + BX lr ; Return to the caller NOP NOP NOP diff --git a/ports_module/cortex-m3/iar/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex-m3/iar/module_manager/src/tx_thread_stack_build.s index 86734467..e5f23bc5 100644 --- a/ports_module/cortex-m3/iar/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex-m3/iar/module_manager/src/tx_thread_stack_build.s @@ -21,14 +21,14 @@ ;/**************************************************************************/ ; ; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build Cortex-M3/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -60,7 +60,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -68,11 +68,11 @@ PUBLIC _tx_thread_stack_build _tx_thread_stack_build: ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-M should look like the following after it is built: -; -; Stack Top: +; +; Stack Top: ; LR Interrupted LR (LR at time of PENDSV) ; r4 Initial value for r4 ; r5 Initial value for r5 @@ -132,4 +132,3 @@ _tx_thread_stack_build: BX lr ; Return to caller ;} END - diff --git a/ports_module/cortex-m3/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex-m3/iar/module_manager/src/tx_thread_system_return.s index fa0ef7a3..38fb892b 100644 --- a/ports_module/cortex-m3/iar/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex-m3/iar/module_manager/src/tx_thread_system_return.s @@ -20,25 +20,15 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE ; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return Cortex-M3/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -70,7 +60,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -79,9 +69,9 @@ _tx_thread_system_return??rA: _tx_thread_system_return: ; -; /* Return to real scheduler via PendSV. Note that this routine is often +; /* Return to real scheduler via PendSV. Note that this routine is often ; replaced with in-line assembly in tx_port.h to improved performance. */ -; +; MOV r0, #0x10000000 ; Load PENDSVSET bit MOV r1, #0xE000E000 ; Load NVIC base STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR @@ -92,7 +82,6 @@ _tx_thread_system_return: CPSIE i ; Enable interrupts MSR PRIMASK, r1 ; Restore original interrupt posture _isr_context: - BX lr ; Return to caller + BX lr ; Return to caller ;} - END - + END diff --git a/ports_module/cortex-m3/iar/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex-m3/iar/module_manager/src/tx_timer_interrupt.s index 94af5d87..58303af0 100644 --- a/ports_module/cortex-m3/iar/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex-m3/iar/module_manager/src/tx_timer_interrupt.s @@ -20,17 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_timer.h" -;#include "tx_thread.h" -; -; -;Define Assembly language external references... ; EXTERN _tx_timer_time_slice EXTERN _tx_timer_system_clock @@ -46,14 +35,14 @@ EXTERN _tx_thread_preempt_disable ; ; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt Cortex-M3/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -86,7 +75,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -109,7 +98,7 @@ _tx_timer_interrupt: ; if (_tx_timer_time_slice) ; { ; - MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice + MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CBZ r2, __tx_timer_no_time_slice ; Is it non-active? ; Yes, skip time-slice processing @@ -226,13 +215,13 @@ __tx_timer_dont_activate: ; if (_tx_timer_expired_time_slice) ; { ; - MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired + MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag @@ -265,4 +254,3 @@ __tx_timer_nothing_expired: ; ;} END - diff --git a/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_alignment_adjust.c index 553949ee..fab10684 100644 --- a/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_alignment_adjust.c @@ -10,15 +10,15 @@ /**************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #define TX_SOURCE_CODE @@ -26,42 +26,42 @@ #include "txm_module.h" -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_power_of_two_block_size Cortex-M3/MPU/IAR */ -/* 6.0.1 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_power_of_two_block_size Cortex-M3/MPU/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function calculates a power of two size at or immediately above*/ -/* the input size and returns it to the caller. */ -/* */ -/* INPUT */ -/* */ -/* size Block size */ -/* */ -/* OUTPUT */ -/* */ -/* calculated size Rounded up to power of two */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function calculates a power of two size at or immediately above*/ +/* the input size and returns it to the caller. */ +/* */ +/* INPUT */ +/* */ +/* size Block size */ +/* */ +/* OUTPUT */ +/* */ +/* calculated size Rounded up to power of two */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) @@ -89,52 +89,52 @@ ULONG _txm_power_of_two_block_size(ULONG size) } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_alignment_adjust Cortex-M3/MPU/IAR */ -/* 6.0.1 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_alignment_adjust Cortex-M3/MPU/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function adjusts the alignment and size of the code and data */ -/* section for a given module implementation. */ -/* */ -/* INPUT */ -/* */ -/* module_preamble Pointer to module preamble */ -/* code_size Size of the code area (updated) */ -/* code_alignment Code area alignment (updated) */ -/* data_size Size of data area (updated) */ -/* data_alignment Data area alignment (updated) */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* _txm_power_of_two_block_size Calculate power of two size */ -/* */ -/* CALLED BY */ -/* */ -/* Initial thread stack frame */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function adjusts the alignment and size of the code and data */ +/* section for a given module implementation. */ +/* */ +/* INPUT */ +/* */ +/* module_preamble Pointer to module preamble */ +/* code_size Size of the code area (updated) */ +/* code_alignment Code area alignment (updated) */ +/* data_size Size of data area (updated) */ +/* data_alignment Data area alignment (updated) */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_power_of_two_block_size Calculate power of two size */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, - ULONG *code_size, - ULONG *code_alignment, - ULONG *data_size, +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, + ULONG *code_size, + ULONG *code_alignment, + ULONG *data_size, ULONG *data_alignment) { @@ -265,7 +265,6 @@ ULONG data_size_accum; } else { - /* Determine code block sizes. Minimize the alignment requirement. There are 4 MPU code entries available. The following is how the code size will be distributed: @@ -283,7 +282,6 @@ ULONG data_size_accum; /* Determine the best data block size, which in our case is the minimal alignment. */ if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) { - /* Block size of 32 is best. */ data_block_size = 32; } @@ -374,7 +372,6 @@ ULONG data_size_accum; } else { - /* Just set data block size to 32MB just to create an allocation error! */ data_block_size = 33554432; } @@ -386,14 +383,16 @@ ULONG data_size_accum; data_size_accum += data_block_size; } local_data_size = data_size_accum; - + /* Determine if the data block size is greater than the current alignment. If so, use block size as the alignment. */ if (data_block_size > local_data_alignment) + { local_data_alignment = data_block_size; + } /* Return all the information to the caller. */ - *code_size = local_code_size; + *code_size = local_code_size; *code_alignment = local_code_alignment; *data_size = local_data_size; *data_alignment = local_data_alignment; diff --git a/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_external_memory_enable.c index 8da1ae7b..7eaa53df 100644 --- a/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -10,15 +10,15 @@ /**************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #define TX_SOURCE_CODE @@ -29,52 +29,53 @@ #include "txm_module.h" -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_external_memory_enable Cortex-M3/MPU/IAR */ -/* 6.0.1 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_external_memory_enable Cortex-M3/MPU/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function creates an entry in the MPU table for a shared */ -/* memory space. */ -/* */ -/* INPUT */ -/* */ -/* module_instance Module instance pointer */ -/* start_address Start address of memory */ -/* length Length of external memory */ -/* attributes Memory attributes (r/w) */ -/* */ -/* OUTPUT */ -/* */ -/* status Completion status */ -/* */ -/* CALLS */ -/* */ -/* _tx_mutex_get Get protection mutex */ -/* _tx_mutex_put Release protection mutex */ -/* _txm_power_of_two_block_size Round length to power of two */ -/* */ -/* CALLED BY */ -/* */ -/* Application code */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function creates an entry in the MPU table for a shared */ +/* memory space. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* start_address Start address of memory */ +/* length Length of external memory */ +/* attributes Memory attributes (r/w) */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_mutex_get Get protection mutex */ +/* _tx_mutex_put Release protection mutex */ +/* _txm_power_of_two_block_size Round length to power of two */ +/* _txm_module_manager_mm_register_setup Reconfigure MPU registers */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, - VOID *start_address, - ULONG length, +UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, + VOID *start_address, + ULONG length, UINT attributes) { @@ -88,15 +89,13 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Determine if the module manager has not been initialized yet. */ if (_txm_module_manager_ready != TX_TRUE) { - /* Module manager has not been initialized. */ - return(TX_NOT_AVAILABLE); + return(TX_NOT_AVAILABLE); } /* Determine if the module is valid. */ if (module_instance == TX_NULL) { - /* Invalid module pointer. */ return(TX_PTR_ERROR); } @@ -107,7 +106,6 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Determine if the module instance is valid. */ if (module_instance -> txm_module_instance_id != TXM_MODULE_ID) { - /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); @@ -118,7 +116,6 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { - /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); @@ -138,7 +135,7 @@ TXM_MODULE_PREAMBLE *module_preamble; return(TXM_MODULE_INVALID_PROPERTIES); } - /* Start address and length must adhere to Cortex-M MPU. + /* Start address and length must adhere to Cortex-M MPU. The address must align with the block size. */ block_size = _txm_power_of_two_block_size(length); @@ -183,4 +180,3 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return success. */ return(TX_SUCCESS); } - diff --git a/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_memory_fault_handler.c index 96045103..e516ffc4 100644 --- a/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -10,15 +10,15 @@ /**************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #define TX_SOURCE_CODE @@ -33,50 +33,50 @@ VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); -/* Define a macro that can be used to allocate global variables useful to - store information about the last fault. This macro is defined in +/* Define a macro that can be used to allocate global variables useful to + store information about the last fault. This macro is defined in txm_module_port.h and is usually populated in the assembly language fault handling prior to the code calling _txm_module_manager_memory_fault_handler. */ TXM_MODULE_MANAGER_FAULT_INFO -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_memory_fault_handler Cortex-M3/MPU/IAR */ -/* 6.0.1 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_handler Cortex-M3/MPU/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function handles a fault associated with a memory protected */ -/* module. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* _tx_thread_terminate Terminate thread */ -/* */ -/* CALLED BY */ -/* */ -/* Fault handler */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function handles a fault associated with a memory protected */ +/* module. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_terminate Terminate thread */ +/* */ +/* CALLED BY */ +/* */ +/* Fault handler */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) @@ -85,7 +85,6 @@ VOID _txm_module_manager_memory_fault_handler(VOID) TXM_MODULE_INSTANCE *module_instance_ptr; TX_THREAD *thread_ptr; - /* Pickup the current thread. */ thread_ptr = _tx_thread_current_ptr; @@ -95,7 +94,6 @@ TX_THREAD *thread_ptr; /* Is there a thread? */ if (thread_ptr) { - /* Pickup the module instance. */ module_instance_ptr = thread_ptr -> tx_thread_module_instance_ptr; @@ -106,9 +104,7 @@ TX_THREAD *thread_ptr; /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { - /* Yes, call the user's notification memory fault callback. */ (_txm_module_manager_fault_notify)(thread_ptr, module_instance_ptr); } } - diff --git a/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_memory_fault_notify.c index afc2be47..ac9d7dd7 100644 --- a/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -10,15 +10,15 @@ /**************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #define TX_SOURCE_CODE @@ -34,53 +34,51 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_memory_fault_notify Cortex-M3/MPU/IAR */ -/* 6.0.1 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_notify Cortex-M3/MPU/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function registers an application callback when/if a memory */ -/* fault occurs. The supplied thread is automatically terminated, but */ -/* any other threads in the same module may still execute. */ -/* */ -/* INPUT */ -/* */ -/* notify_function Memory fault notification */ -/* function, NULL disables. */ -/* */ -/* OUTPUT */ -/* */ -/* status Completion status */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application callback when/if a memory */ +/* fault occurs. The supplied thread is automatically terminated, but */ +/* any other threads in the same module may still execute. */ +/* */ +/* INPUT */ +/* */ +/* notify_function Memory fault notification */ +/* function, NULL disables. */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { - /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; /* Return success. */ return(TX_SUCCESS); } - diff --git a/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_mm_register_setup.c index c3118c14..83aad68f 100644 --- a/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -10,59 +10,58 @@ /**************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #define TX_SOURCE_CODE #include "tx_api.h" #include "txm_module.h" -#include "txm_module_manager_util.h" -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_region_size_get Cortex-M3/MPU/IAR */ -/* 6.0.1 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_region_size_get Cortex-M3/MPU/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function converts the region size in bytes to the block size */ -/* for the Cortex-M3 MPU specification. */ -/* */ -/* INPUT */ -/* */ -/* block_size Size of the block in bytes */ -/* */ -/* OUTPUT */ -/* */ -/* MPU size specification */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _txm_module_manager_mm_register_setup */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function converts the region size in bytes to the block size */ +/* for the Cortex-M3 MPU specification. */ +/* */ +/* INPUT */ +/* */ +/* block_size Size of the block in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* MPU size specification */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) @@ -70,7 +69,6 @@ ULONG _txm_module_manager_region_size_get(ULONG block_size) ULONG return_value; - /* Process relative to the input block size. */ if (block_size == 32) { @@ -140,7 +138,7 @@ ULONG return_value; { return_value = 0x14; } - else + else { /* Max 4MB MPU pages for modules. */ return_value = 0x15; @@ -150,45 +148,43 @@ ULONG return_value; } - - -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_calculate_srd_bits Cortex-M3/MPU/IAR */ -/* 6.0.1 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_calculate_srd_bits Cortex-M3/MPU/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function calculates the SRD bits that need to be set to */ -/* protect "length" bytes in a block. */ -/* */ -/* INPUT */ -/* */ -/* block_size Size of the block in bytes */ -/* length Actual length in bytes */ -/* */ -/* OUTPUT */ -/* */ -/* SRD bits to be OR'ed with region attribute register. */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _txm_module_manager_mm_register_setup */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function calculates the SRD bits that need to be set to */ +/* protect "length" bytes in a block. */ +/* */ +/* INPUT */ +/* */ +/* block_size Size of the block in bytes */ +/* length Actual length in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* SRD bits to be OR'ed with region attribute register. */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) @@ -230,43 +226,42 @@ UINT srd_bit_index; } - -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_mm_register_setup Cortex-M3/MPU/IAR */ -/* 6.0.1 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_mm_register_setup Cortex-M3/MPU/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function sets up the Cortex-M3 MPU register definitions based */ -/* on the module's memory characteristics. */ -/* */ -/* INPUT */ -/* */ -/* module_instance Pointer to module instance */ -/* */ -/* OUTPUT */ -/* */ -/* MPU specifications for module in module_instance */ -/* */ -/* CALLS */ -/* */ -/* _txm_module_manager_region_size_get */ -/* */ -/* CALLED BY */ -/* */ -/* _txm_module_manager_thread_create */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function sets up the Cortex-M3 MPU register definitions based */ +/* on the module's memory characteristics. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* */ +/* OUTPUT */ +/* */ +/* MPU specifications for module in module_instance */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_manager_region_size_get */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_thread_create */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) @@ -291,9 +286,11 @@ UINT i; /* Setup the first region for the ThreadX trampoline code. */ /* Set base register to user mode entry, which is guaranteed to be at least 32-byte aligned. */ base_address_register = (ULONG) _txm_module_manager_user_mode_entry; + /* Mask address to proper range, region 0, set Valid bit. */ base_address_register = (base_address_register & 0xFFFFFFE0) | mpu_register | 0x10; module_instance -> txm_module_instance_mpu_registers[0] = base_address_register; + /* Attributes: read only, write-back, shareable, size 32 bytes, region enabled. */ module_instance -> txm_module_instance_mpu_registers[1] = 0x06070009; @@ -304,11 +301,10 @@ UINT i; mpu_table_index = 2; /* Setup values for code area. */ - code_address = (ULONG) module_instance -> txm_module_instance_code_start; + code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - - /* Check if shared memory was set up. If so, only 3 entries are available for + /* Check if shared memory was set up. If so, only 3 entries are available for code protection. If not set up, 4 code entries are available. */ if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] == 0) { @@ -352,7 +348,7 @@ UINT i; /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Build the base attribute register. */ base_attribute_register = region_size | srd_bits | 0x06070001; @@ -385,7 +381,6 @@ UINT i; /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) { - /* Build the base address register. */ base_address_register = code_address & ~(block_size - 1) | mpu_register | 0x10; @@ -405,7 +400,7 @@ UINT i; base_attribute_register = base_attribute_register | 0x1; } /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; + module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; /* Setup the MPU Base Attribute Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; @@ -415,9 +410,13 @@ UINT i; /* Decrement the code size. */ if (code_size > block_size) + { code_size = code_size - block_size; + } else + { code_size = 0; + } /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; @@ -435,7 +434,7 @@ UINT i; } /* Setup values for data area. */ - data_address = (ULONG) module_instance -> txm_module_instance_data_start; + data_address = (ULONG) module_instance -> txm_module_instance_data_start; /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside @@ -455,8 +454,7 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - - block_size = _txm_power_of_two_block_size(data_size / TXM_MODULE_MANAGER_DATA_MPU_ENTRIES); + block_size = _txm_power_of_two_block_size(data_size / TXM_MODULE_MANAGER_DATA_MPU_ENTRIES); /* Reset SRD bitfield. */ srd_bits = 0; @@ -467,7 +465,6 @@ UINT i; /* Now loop through to setup MPU protection for the data area. */ for (i = 0; i < TXM_MODULE_MANAGER_DATA_MPU_ENTRIES; i++) { - /* Build the base address register. */ base_address_register = (data_address & ~(block_size - 1)) | mpu_register | 0x10; @@ -475,11 +472,11 @@ UINT i; if (data_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); - } + } /* Build the base attribute register. */ base_attribute_register = region_size | srd_bits | 0x13070000; - + /* Is there still some data? If so set the region enable bit. */ if (data_size) { @@ -488,7 +485,7 @@ UINT i; } /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; + module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; /* Setup the MPU Base Attribute Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; @@ -498,9 +495,13 @@ UINT i; /* Decrement the data size. */ if (data_size > block_size) + { data_size = data_size - block_size; + } else + { data_size = 0; + } /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; @@ -508,176 +509,4 @@ UINT i; /* Increment the MPU register index. */ mpu_register++; } - -} - -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_shared_memory_check_outside */ -/* Cortex-M3/MPU/IAR */ -/* 6.0.1 */ -/* AUTHOR */ -/* */ -/* Scott Larson, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function checks if the specified object is outside shared */ -/* memory. */ -/* */ -/* INPUT */ -/* */ -/* module_instance Pointer to module instance */ -/* obj_ptr Pointer to the object */ -/* obj_size Size of the object */ -/* */ -/* OUTPUT */ -/* */ -/* Whether the object is outside the shared memory region. */ -/* */ -/* CALLS */ -/* */ -/* N/A */ -/* */ -/* CALLED BY */ -/* */ -/* Module dispatch check functions */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ -/* */ -/**************************************************************************/ -UCHAR _txm_module_manager_shared_memory_check_outside(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) -{ - -ALIGN_TYPE shared_memory_start; -ALIGN_TYPE shared_memory_end; - - shared_memory_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address; - shared_memory_end = shared_memory_start + module_instance -> txm_module_instance_shared_memory_length; - - if (TXM_MODULE_MANAGER_CHECK_OUTSIDE_RANGE_EXCLUSIVE(shared_memory_start, shared_memory_end, - obj_ptr, obj_size)) - { - return(TX_TRUE); - } - return(TX_FALSE); -} - -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_shared_memory_check_inside Cortex-M3/MPU/IAR */ -/* 6.0.1 */ -/* AUTHOR */ -/* */ -/* Scott Larson, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function checks if the specified object is inside shared */ -/* memory. */ -/* */ -/* INPUT */ -/* */ -/* module_instance Pointer to module instance */ -/* obj_ptr Pointer to the object */ -/* obj_size Size of the object */ -/* */ -/* OUTPUT */ -/* */ -/* Whether the object is inside the shared memory region. */ -/* */ -/* CALLS */ -/* */ -/* N/A */ -/* */ -/* CALLED BY */ -/* */ -/* Module dispatch check functions */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ -/* */ -/**************************************************************************/ -UCHAR _txm_module_manager_shared_memory_check_inside(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) -{ - -ALIGN_TYPE shared_memory_start; -ALIGN_TYPE shared_memory_end; - - shared_memory_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address; - shared_memory_end = shared_memory_start + module_instance -> txm_module_instance_shared_memory_length; - - if (TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_EXCLUSIVE(shared_memory_start, shared_memory_end, - obj_ptr, obj_size)) - { - return(TX_TRUE); - } - return(TX_FALSE); -} - -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_shared_memory_check_inside_byte */ -/* Cortex-M3/MPU/IAR */ -/* 6.0.1 */ -/* AUTHOR */ -/* */ -/* Scott Larson, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function checks if the specified byte is inside shared memory. */ -/* */ -/* INPUT */ -/* */ -/* module_instance Pointer to module instance */ -/* byte_ptr Pointer to the byte */ -/* */ -/* OUTPUT */ -/* */ -/* Whether the byte is inside the shared memory region. */ -/* */ -/* CALLS */ -/* */ -/* N/A */ -/* */ -/* CALLED BY */ -/* */ -/* Module dispatch check functions */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ -/* */ -/**************************************************************************/ -UCHAR _txm_module_manager_shared_memory_check_inside_byte(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE byte_ptr) -{ - -ALIGN_TYPE shared_memory_start; -ALIGN_TYPE shared_memory_end; - - shared_memory_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address; - shared_memory_end = shared_memory_start + module_instance -> txm_module_instance_shared_memory_length; - - if (TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_EXCLUSIVE_BYTE(shared_memory_start, shared_memory_end, - byte_ptr)) - { - return(TX_TRUE); - } - return(TX_FALSE); } diff --git a/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_thread_stack_build.s index f3fbd758..2158c319 100644 --- a/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_thread_stack_build.s @@ -10,66 +10,57 @@ ;/**************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Module Manager */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Module Manager */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _txm_module_manager_thread_stack_build Cortex-M3/MPU/IAR */ -;/* 6.0.1 */ + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _txm_module_manager_thread_stack_build Cortex-M3/MPU/IAR */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function builds a stack frame on the supplied thread's stack. */ -;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ -;/* thread_ptr Pointer to thread */ -;/* function_ptr Pointer to shell function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread */ +;/* function_ptr Pointer to shell function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) @@ -77,11 +68,11 @@ PUBLIC _txm_module_manager_thread_stack_build _txm_module_manager_thread_stack_build: ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-M should look like the following after it is built: -; -; Stack Top: +; +; Stack Top: ; LR Interrupted LR (LR at time of PENDSV) ; r4 Initial value for r4 ; r5 Initial value for r5 @@ -89,7 +80,7 @@ _txm_module_manager_thread_stack_build: ; r7 Initial value for r7 ; r8 Initial value for r8 ; r9 Initial value for r9 -; r10 (sl) Initial value for r10 (sl) +; r10 Initial value for r10 ; r11 Initial value for r11 ; r0 Initial value for r0 (Hardware stack starts here!!) ; r1 Initial value for r1 @@ -116,17 +107,15 @@ _txm_module_manager_thread_stack_build: STR r3, [r2, #12] ; Store initial r6 STR r3, [r2, #16] ; Store initial r7 STR r3, [r2, #20] ; Store initial r8 - LDR r3, [r0, #12] ; Pickup stack starting address - STR r3, [r2, #28] ; Store initial r10 (sl) - MOV r3, #0 ; Build initial register value + STR r3, [r2, #28] ; Store initial r10 STR r3, [r2, #32] ; Store initial r11 ; -; /* Hardware stack follows. / +; /* Hardware stack follows. */ ; STR r0, [r2, #36] ; Store initial r0, which is the thread control block LDR r3, [r0, #8] ; Pickup thread entry info pointer,which is in the stack pointer position of the thread control block. - ; It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this + ; It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this ; function with the actual, initial stack pointer. STR r3, [r2, #40] ; Store initial r1, which is the module entry information. LDR r3, [r3, #8] ; Pickup data base register from the module information @@ -145,8 +134,7 @@ _txm_module_manager_thread_stack_build: ; /* Setup stack pointer. */ ; thread_ptr -> tx_thread_stack_ptr = r2; ; - STR r2, [r0, #8] ; Save stack pointer in thread's - ; control block + STR r2, [r0, #8] ; Save stack pointer in thread's control block BX lr ; Return to caller ;} END diff --git a/ports_module/cortex-m4/ac5/example_build/build.bat b/ports_module/cortex-m4/ac5/example_build/build.bat new file mode 100644 index 00000000..57eae574 --- /dev/null +++ b/ports_module/cortex-m4/ac5/example_build/build.bat @@ -0,0 +1,8 @@ +@ECHO OFF +ECHO Starting build... +CALL build_threadx.bat +CALL build_threadx_demo.bat +CALL build_threadx_module_library.bat +CALL build_threadx_module_demo.bat +CALL build_threadx_module_manager_demo.bat +ECHO Build finished. diff --git a/ports_module/cortex-m4/ac5/example_build/build_threadx.bat b/ports_module/cortex-m4/ac5/example_build/build_threadx.bat new file mode 100644 index 00000000..add2c03f --- /dev/null +++ b/ports_module/cortex-m4/ac5/example_build/build_threadx.bat @@ -0,0 +1,240 @@ +del tx.a +armasm -g --cpu=cortex-m4 --fpu=softvfp --apcs=/interwork tx_initialize_low_level.S +armasm -g --cpu=cortex-m4 --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_stack_build.S +armasm -g --cpu=cortex-m4 --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_schedule.S --diag_suppress=A1581W +armasm -g --cpu=cortex-m4 --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_system_return.S +armasm -g --cpu=cortex-m4 --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_context_save.S +armasm -g --cpu=cortex-m4 --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_context_restore.S +armasm -g --cpu=cortex-m4 --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_interrupt_control.S +armasm -g --cpu=cortex-m4 --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_timer_interrupt.S +armasm -g --cpu=cortex-m4 --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_interrupt_disable.S +armasm -g --cpu=cortex-m4 --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_interrupt_restore.S +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_allocate.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_cleanup.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_create.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_delete.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_info_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_initialize.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_performance_info_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_performance_system_info_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_prioritize.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_release.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_allocate.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_cleanup.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_create.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_delete.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_info_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_initialize.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_performance_info_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_prioritize.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_search.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_release.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_cleanup.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_create.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_delete.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_info_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_initialize.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_performance_info_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_performance_system_info_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_set.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_set_notify.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_initialize_high_level.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_initialize_kernel_enter.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_initialize_kernel_setup.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_cleanup.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_create.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_delete.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_info_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_initialize.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_performance_info_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_performance_system_info_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_prioritize.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_priority_change.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_put.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_cleanup.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_create.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_delete.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_flush.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_front_send.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_info_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_initialize.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_performance_info_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_performance_system_info_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_prioritize.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_receive.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_send.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_send_notify.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_ceiling_put.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_cleanup.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_create.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_delete.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_info_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_initialize.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_performance_info_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_performance_system_info_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_prioritize.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_put.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_put_notify.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_create.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_delete.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_entry_exit_notify.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_identify.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_info_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_initialize.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_performance_info_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_performance_system_info_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_preemption_change.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_priority_change.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_relinquish.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_reset.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_resume.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_shell_entry.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_sleep.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_stack_analyze.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_stack_error_handler.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_stack_error_notify.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_suspend.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_system_preempt_check.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_system_resume.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_system_suspend.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_terminate.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_time_slice.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_time_slice_change.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_timeout.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_wait_abort.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_time_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_time_set.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_activate.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_change.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_create.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_deactivate.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_delete.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_expiration_process.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_info_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_initialize.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_performance_info_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_performance_system_info_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_system_activate.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_system_deactivate.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_thread_entry.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_enable.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_disable.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_initialize.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_interrupt_control.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_isr_enter_insert.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_isr_exit_insert.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_object_register.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_object_unregister.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_user_event_insert.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_buffer_full_notify.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_event_filter.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_event_unfilter.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_block_allocate.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_block_pool_create.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_block_pool_delete.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_block_pool_info_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_block_pool_prioritize.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_block_release.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_allocate.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_pool_create.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_pool_delete.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_pool_info_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_pool_prioritize.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_release.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_create.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_delete.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_info_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_set.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_set_notify.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_create.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_delete.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_info_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_prioritize.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_put.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_create.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_delete.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_flush.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_front_send.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_info_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_prioritize.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_receive.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_send.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_send_notify.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_ceiling_put.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_create.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_delete.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_info_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_prioritize.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_put.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_put_notify.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_create.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_delete.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_entry_exit_notify.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_info_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_preemption_change.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_priority_change.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_relinquish.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_reset.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_resume.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_suspend.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_terminate.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_time_slice_change.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_wait_abort.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_activate.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_change.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_create.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_deactivate.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_delete.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_info_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_application_request.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_callback_request.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_event_flags_notify_trampoline.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_file_load.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_in_place_load.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_internal_load.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_initialize.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_kernel_dispatch.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_maximum_module_priority_set.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_memory_load.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_allocate.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_deallocate.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_pointer_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_pointer_get_extended.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_pool_create.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_properties_get.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_queue_notify_trampoline.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_semaphore_notify_trampoline.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_start.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_stop.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_thread_create.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_thread_notify_trampoline.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_thread_reset.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_timer_notify_trampoline.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_unload.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_util.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_alignment_adjust.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_external_memory_enable.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_memory_fault_handler.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_memory_fault_notify.c +armcc -g -O0 --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_mm_register_setup.c +armasm -g --cpu=cortex-m4 --fpu=softvfp --apcs=/interwork ../module_manager/src/txm_module_manager_thread_stack_build.S +armasm -g --cpu=cortex-m4 --fpu=softvfp --apcs=/interwork ../module_manager/src/txm_module_manager_user_mode_entry.S + +armar --create tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o tx_initialize_low_level.o tx_thread_interrupt_disable.o tx_thread_interrupt_restore.o tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o + +armar -r tx.a tx_event_flags_performance_system_info_get.o tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o + +armar -r tx.a tx_semaphore_put_notify.o tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o + +armar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o + +armar -r tx.a txe_queue_prioritize.o txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o txm_module_manager_alignment_adjust.o txm_module_manager_application_request.o txm_module_manager_callback_request.o txm_module_manager_event_flags_notify_trampoline.o txm_module_manager_external_memory_enable.o txm_module_manager_file_load.o txm_module_manager_in_place_load.o + +armar -r tx.a txm_module_manager_initialize.o txm_module_manager_kernel_dispatch.o txm_module_manager_maximum_module_priority_set.o txm_module_manager_memory_fault_handler.o txm_module_manager_memory_fault_notify.o txm_module_manager_memory_load.o txm_module_manager_object_pointer_get.o txm_module_manager_object_pool_create.o txm_module_manager_queue_notify_trampoline.o txm_module_manager_semaphore_notify_trampoline.o txm_module_manager_mm_register_setup.o txm_module_manager_start.o txm_module_manager_stop.o txm_module_manager_thread_create.o txm_module_manager_thread_notify_trampoline.o txm_module_manager_thread_reset.o txm_module_manager_timer_notify_trampoline.o txm_module_manager_unload.o txm_module_manager_thread_stack_build.o txm_module_manager_internal_load.o txm_module_manager_object_allocate.o txm_module_manager_object_deallocate.o txm_module_manager_object_pointer_get_extended.o txm_module_manager_properties_get.o txm_module_manager_util.o txm_module_manager_user_mode_entry.o diff --git a/ports_module/cortex-m4/ac5/example_build/build_threadx_demo.bat b/ports_module/cortex-m4/ac5/example_build/build_threadx_demo.bat new file mode 100644 index 00000000..101e70c1 --- /dev/null +++ b/ports_module/cortex-m4/ac5/example_build/build_threadx_demo.bat @@ -0,0 +1,4 @@ +armasm -g --cpu=cortex-m4 --apcs=interwork tx_initialize_low_level.S +armcc -c -g --cpu=cortex-m4 -O2 -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc sample_threadx.c +armlink -d -o sample_threadx.axf --elf --map --ro-base=0x00000000 --rw-base=0x20000000 --first __tx_vectors --datacompressor=off --inline --info=inline --callgraph --list sample_threadx.map tx_initialize_low_level.o sample_threadx.o tx.a + diff --git a/ports_module/cortex-m4/ac5/example_build/build_threadx_module_demo.bat b/ports_module/cortex-m4/ac5/example_build/build_threadx_module_demo.bat new file mode 100644 index 00000000..f7206706 --- /dev/null +++ b/ports_module/cortex-m4/ac5/example_build/build_threadx_module_demo.bat @@ -0,0 +1,3 @@ +armasm -g --cpu=cortex-m4 --fpu=softvfp --apcs=/interwork/ropi/rwpi txm_module_preamble.S +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi --lower_ropi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc sample_threadx_module.c +armlink -d -o sample_threadx_module.axf --elf --ro=0x30000 --rw=0x40000 --first txm_module_preamble.o(Init) --entry=_txm_module_thread_shell_entry --ropi --rwpi --remove --map --symbols --list sample_threadx_module.map txm_module_preamble.o sample_threadx_module.o txm.a diff --git a/ports_module/cortex-m4/ac5/example_build/build_threadx_module_library.bat b/ports_module/cortex-m4/ac5/example_build/build_threadx_module_library.bat new file mode 100644 index 00000000..0c44afbc --- /dev/null +++ b/ports_module/cortex-m4/ac5/example_build/build_threadx_module_library.bat @@ -0,0 +1,106 @@ +del txm.a + +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_allocate.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_pool_create.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_pool_delete.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_pool_info_get.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_pool_performance_info_get.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_pool_performance_system_info_get.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_pool_prioritize.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_release.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_allocate.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_pool_create.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_pool_delete.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_pool_info_get.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_pool_performance_info_get.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_pool_performance_system_info_get.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_pool_prioritize.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_release.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_create.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_delete.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_get.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_info_get.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_performance_info_get.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_performance_system_info_get.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_set.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_set_notify.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_module_application_request.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_module_callback_request_thread_entry.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_module_object_allocate.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_module_object_deallocate.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_module_object_pointer_get.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_module_thread_system_suspend.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_create.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_delete.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_get.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_info_get.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_performance_info_get.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_performance_system_info_get.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_prioritize.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_put.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_create.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_delete.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_flush.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_front_send.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_info_get.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_performance_info_get.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_performance_system_info_get.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_prioritize.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_receive.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_send.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_send_notify.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_ceiling_put.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_create.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_delete.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_get.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_info_get.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_performance_info_get.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_performance_system_info_get.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_prioritize.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_put.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_put_notify.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_create.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_delete.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_entry_exit_notify.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_identify.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_info_get.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_interrupt_control.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_performance_info_get.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_performance_system_info_get.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_preemption_change.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_priority_change.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_relinquish.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_reset.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_resume.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_sleep.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_stack_error_notify.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_suspend.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_terminate.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_time_slice_change.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_wait_abort.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_time_get.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_time_set.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_activate.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_change.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_create.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_deactivate.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_delete.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_info_get.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_performance_info_get.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_performance_system_info_get.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_buffer_full_notify.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_disable.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_enable.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_event_filter.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_event_unfilter.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_isr_enter_insert.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_isr_exit_insert.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_user_event_insert.c +armcc -g --cpu=cortex-m4 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ..//module_lib/src/txm_module_thread_shell_entry.c +armasm -g --cpu=cortex-m4 --fpu=softvfp --apcs=/interwork/ropi/rwpi --cpreproc --cpreproc_opts=-D,TXM_ASSEMBLY --cpreproc_opts=-D,TXM_MODULE_HEAP_SIZE=512 -I../inc ../module_lib/src/txm_module_initialize.S + +armar --create txm.a txm_block_allocate.o txm_block_pool_create.o txm_block_pool_delete.o txm_block_pool_info_get.o txm_block_pool_performance_info_get.o txm_block_pool_performance_system_info_get.o txm_block_pool_prioritize.o txm_block_release.o txm_byte_allocate.o txm_byte_pool_create.o txm_byte_pool_delete.o txm_byte_pool_info_get.o txm_byte_pool_performance_info_get.o txm_byte_pool_performance_system_info_get.o txm_byte_pool_prioritize.o txm_byte_release.o txm_event_flags_create.o txm_event_flags_delete.o txm_event_flags_get.o txm_event_flags_info_get.o txm_event_flags_performance_info_get.o txm_event_flags_performance_system_info_get.o txm_event_flags_set.o txm_event_flags_set_notify.o txm_module_application_request.o txm_module_callback_request_thread_entry.o txm_module_initialize.o txm_module_object_allocate.o txm_module_object_deallocate.o txm_module_object_pointer_get.o txm_module_thread_shell_entry.o txm_module_thread_system_suspend.o txm_mutex_create.o txm_mutex_delete.o txm_mutex_get.o + +armar -r txm.a txm_mutex_info_get.o txm_mutex_performance_info_get.o txm_mutex_performance_system_info_get.o txm_mutex_prioritize.o txm_mutex_put.o txm_queue_create.o txm_queue_delete.o txm_queue_flush.o txm_queue_front_send.o txm_queue_info_get.o txm_queue_performance_info_get.o txm_queue_performance_system_info_get.o txm_queue_prioritize.o txm_queue_receive.o txm_queue_send.o txm_queue_send_notify.o txm_semaphore_ceiling_put.o txm_semaphore_create.o txm_semaphore_delete.o txm_semaphore_get.o txm_semaphore_info_get.o txm_semaphore_performance_info_get.o txm_semaphore_performance_system_info_get.o txm_semaphore_prioritize.o txm_semaphore_put.o txm_semaphore_put_notify.o txm_thread_create.o txm_thread_delete.o txm_thread_entry_exit_notify.o txm_thread_identify.o txm_thread_info_get.o txm_thread_interrupt_control.o txm_thread_performance_info_get.o txm_thread_performance_system_info_get.o txm_thread_preemption_change.o txm_thread_priority_change.o txm_thread_relinquish.o txm_thread_reset.o txm_thread_resume.o + +armar -r txm.a txm_thread_sleep.o txm_thread_stack_error_notify.o txm_thread_suspend.o txm_thread_terminate.o txm_thread_time_slice_change.o txm_thread_wait_abort.o txm_time_get.o txm_time_set.o txm_timer_activate.o txm_timer_change.o txm_timer_create.o txm_timer_deactivate.o txm_timer_delete.o txm_timer_info_get.o txm_timer_performance_info_get.o txm_timer_performance_system_info_get.o txm_trace_buffer_full_notify.o txm_trace_disable.o txm_trace_enable.o txm_trace_event_filter.o txm_trace_event_unfilter.o txm_trace_isr_enter_insert.o txm_trace_isr_exit_insert.o txm_trace_user_event_insert.o diff --git a/ports_module/cortex-m4/ac5/example_build/build_threadx_module_manager_demo.bat b/ports_module/cortex-m4/ac5/example_build/build_threadx_module_manager_demo.bat new file mode 100644 index 00000000..7b247801 --- /dev/null +++ b/ports_module/cortex-m4/ac5/example_build/build_threadx_module_manager_demo.bat @@ -0,0 +1,3 @@ +armasm -g --cpu=cortex-m4 --fpu=softvfp --apcs=interwork tx_initialize_low_level.S +armcc -g --cpu=cortex-m4 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc sample_threadx_module_manager.c +armlink -d -o sample_threadx_module_manager.axf --elf --ro 0x00000000 --first tx_initialize_low_level.o(RESET) --remove --map --symbols --list sample_threadx_module_manager.map tx_initialize_low_level.o sample_threadx_module_manager.o tx.a diff --git a/ports_module/cortex-m4/ac5/example_build/clean.bat b/ports_module/cortex-m4/ac5/example_build/clean.bat new file mode 100644 index 00000000..3217f01b --- /dev/null +++ b/ports_module/cortex-m4/ac5/example_build/clean.bat @@ -0,0 +1,2 @@ +@ECHO OFF +DEL *.o *.a *.axf *.map diff --git a/ports_module/cortex-m4/ac5/example_build/sample_threadx.c b/ports_module/cortex-m4/ac5/example_build/sample_threadx.c new file mode 100644 index 00000000..418ec634 --- /dev/null +++ b/ports_module/cortex-m4/ac5/example_build/sample_threadx.c @@ -0,0 +1,369 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports_module/cortex-m4/ac5/example_build/sample_threadx_module.c b/ports_module/cortex-m4/ac5/example_build/sample_threadx_module.c new file mode 100644 index 00000000..f2647144 --- /dev/null +++ b/ports_module/cortex-m4/ac5/example_build/sample_threadx_module.c @@ -0,0 +1,432 @@ +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, + event flags group, byte pool, and block pool. */ + +/* Specify that this is a module! */ + +#define TXM_MODULE + + +/* Include the ThreadX module definitions. */ + +#include "txm_module.h" + + +/* Define constants. */ + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the external memory area. */ + +#define EXTERNAL_MEMORY_SIZE (64 * 1024) +#define EXTERNAL_MEMORY (0x80000) + + +/* Define the pool space in the bss section of the module. ULONG is used to + get the word alignment. */ + +ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD *thread_0; +TX_THREAD *thread_1; +TX_THREAD *thread_2; +TX_THREAD *thread_3; +TX_THREAD *thread_4; +TX_THREAD *thread_5; +TX_THREAD *thread_6; +TX_THREAD *thread_7; +TX_QUEUE *queue_0; +TX_SEMAPHORE *semaphore_0; +TX_MUTEX *mutex_0; +TX_EVENT_FLAGS_GROUP *event_flags_0; +TX_BYTE_POOL *byte_pool_0; +TX_BLOCK_POOL *block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; +ULONG semaphore_0_puts; +ULONG event_0_sets; +ULONG queue_0_sends; + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + +void semaphore_0_notify(TX_SEMAPHORE *semaphore_ptr) +{ + + if (semaphore_ptr == semaphore_0) + semaphore_0_puts++; +} + + +void event_0_notify(TX_EVENT_FLAGS_GROUP *event_flag_group_ptr) +{ + + if (event_flag_group_ptr == event_flags_0) + event_0_sets++; +} + + +void queue_0_notify(TX_QUEUE *queue_ptr) +{ + + if (queue_ptr == queue_0) + queue_0_sends++; +} + + +/* Define the module start function. */ + +void demo_module_start(ULONG id) +{ + +CHAR *pointer; + + /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + the control block(s). */ + txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_2, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_3, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_4, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_5, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_6, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_7, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&queue_0, sizeof(TX_QUEUE)); + txm_module_object_allocate((void*)&semaphore_0, sizeof(TX_SEMAPHORE)); + txm_module_object_allocate((void*)&mutex_0, sizeof(TX_MUTEX)); + txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); + txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); + txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(queue_0, "module queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + tx_queue_send_notify(queue_0, queue_0_notify); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(semaphore_0, "module semaphore 0", 1); + + tx_semaphore_put_notify(semaphore_0, semaphore_0_notify); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(event_flags_0, "module event flags 0"); + + tx_event_flags_set_notify(event_flags_0, event_0_notify); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(mutex_0, "module mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(block_pool_0, "module block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + /* Test external memory sharing. */ + *(ULONG *)EXTERNAL_MEMORY = 0xABABABAB; + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + diff --git a/ports_module/cortex-m4/ac5/example_build/sample_threadx_module_manager.c b/ports_module/cortex-m4/ac5/example_build/sample_threadx_module_manager.c new file mode 100644 index 00000000..210f0be0 --- /dev/null +++ b/ports_module/cortex-m4/ac5/example_build/sample_threadx_module_manager.c @@ -0,0 +1,126 @@ +/* Small demonstration of the ThreadX module manager. */ + +#include "tx_api.h" +#include "txm_module.h" + + +#define DEMO_STACK_SIZE 1024 + +/* Define the ThreadX object control blocks... */ + +TX_THREAD module_manager; +TXM_MODULE_INSTANCE my_module; + + +/* Define the object pool area. */ + +UCHAR object_memory[16384]; + + +/* Define the module data pool area. */ + +#define MODULE_DATA_SIZE (256 * 1024) +#define MODULE_DATA (0x40000) + + +/* The module code should be loaded here. */ + +#define MODULE_CODE (0x30000) + + +/* Define the external memory area. */ + +#define EXTERNAL_MEMORY_SIZE (64 * 1024) +#define EXTERNAL_MEMORY (0x80000) + + +/* Define the count of memory faults. */ + +ULONG memory_faults; + + +/* Define thread prototypes. */ + +void module_manager_entry(ULONG thread_input); + + +/* Define fault handler. */ + +VOID module_fault_handler(TX_THREAD *thread, TXM_MODULE_INSTANCE *module) +{ + + /* Just increment the fault counter. */ + memory_faults++; +} + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = (CHAR*)first_unused_memory; + + + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + pointer = pointer + DEMO_STACK_SIZE; +} + + + + +/* Define the test threads. */ + +void module_manager_entry(ULONG thread_input) +{ + + /* Initialize the module manager. */ + txm_module_manager_initialize((void *) MODULE_DATA, MODULE_DATA_SIZE); + + txm_module_manager_object_pool_create(object_memory, sizeof(object_memory)); + + /* Register a fault handler. */ + txm_module_manager_memory_fault_notify(module_fault_handler); + + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ + txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE); + + /* Enable a read/write shared memory region. */ + txm_module_manager_external_memory_enable(&my_module, (void *) EXTERNAL_MEMORY, EXTERNAL_MEMORY_SIZE, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); + + /* Start the module. */ + txm_module_manager_start(&my_module); + + /* Sleep for a while.... */ + tx_thread_sleep(1000); + + /* Stop the module. */ + txm_module_manager_stop(&my_module); + + /* Unload the module. */ + txm_module_manager_unload(&my_module); + + /* Load the module that is already there. */ + txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE); + + /* Start the module again. */ + txm_module_manager_start(&my_module); + + /* Now just spin... */ + while(1) + { + + tx_thread_sleep(100); + } +} diff --git a/ports_module/cortex-m4/ac5/example_build/setenv.bat b/ports_module/cortex-m4/ac5/example_build/setenv.bat new file mode 100644 index 00000000..965f12f3 --- /dev/null +++ b/ports_module/cortex-m4/ac5/example_build/setenv.bat @@ -0,0 +1,13 @@ +@echo off + +REM *** ARM DS 2020 +REM SET PATH=%ProgramFiles%\Arm\Development Studio 2020.0\sw\ARMCompiler5.06u6\bin;%PATH% +REM SET ARMLMD_LICENSE_FILE=%APPDATA%\arm\ds\licenses +REM SET ARM_CONFIG_PATH=%APPDATA%\arm\ds\2020.0 +REM SET ARM_PRODUCT_DEF=%ProgramFiles%\Arm\Development Studio 2020.0\sw\mappings\gold.elmap + +REM *** legacy ARM DS 5 +SET PATH=%ProgramFiles%\DS-5 v5.29.3\sw\ARMCompiler5.06u6\bin;%PATH% +SET ARMLMD_LICENSE_FILE=%APPDATA%\ARM\DS-5\licenses +SET ARM_CONFIG_PATH=%APPDATA%\ARM\DS-5_v5.29.3 +SET ARM_PRODUCT_PATH=%ProgramFiles%\DS-5 v5.29.3\sw\mappings diff --git a/ports_module/cortex-m4/ac5/example_build/tx_initialize_low_level.S b/ports_module/cortex-m4/ac5/example_build/tx_initialize_low_level.S new file mode 100644 index 00000000..f4210fe4 --- /dev/null +++ b/ports_module/cortex-m4/ac5/example_build/tx_initialize_low_level.S @@ -0,0 +1,285 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_initialize.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IMPORT _tx_thread_system_stack_ptr + IMPORT _tx_initialize_unused_memory + IMPORT _tx_thread_context_save + IMPORT _tx_thread_context_restore + IMPORT _tx_timer_interrupt + IMPORT __main + IMPORT |Image$$RO$$Limit| + IMPORT |Image$$RW$$Base| + IMPORT |Image$$ZI$$Base| + IMPORT |Image$$ZI$$Limit| + IMPORT __tx_PendSVHandler + IMPORT __tx_SVCallHandler + IMPORT MemManage_Handler +; +; +SYSTEM_CLOCK EQU 6000000 +SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1) +; +; +;/* Setup the stack and heap areas. */ +; +STACK_SIZE EQU 0x00000400 +HEAP_SIZE EQU 0x00000000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +StackMem + SPACE STACK_SIZE +__initial_sp + + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +HeapMem + SPACE HEAP_SIZE +__heap_limit + + + AREA RESET, CODE, READONLY +; + EXPORT __tx_vectors + EXPORT __vector_table +__vector_table +__tx_vectors + DCD __initial_sp ; Reset and system stack ptr + DCD Reset_Handler ; Reset goes to startup function + DCD __tx_NMIHandler ; NMI + DCD __tx_BadHandler ; HardFault + DCD MemManage_Handler ; MemManage + DCD 0 ; BusFault + DCD 0 ; UsageFault + DCD 0 ; 7 + DCD 0 ; 8 + DCD 0 ; 9 + DCD 0 ; 10 + DCD __tx_SVCallHandler ; SVCall + DCD __tx_DBGHandler ; Monitor + DCD 0 ; 13 + DCD __tx_PendSVHandler ; PendSV + DCD __tx_SysTickHandler ; SysTick + DCD __tx_IntHandler ; Int 0 + DCD __tx_IntHandler ; Int 1 + DCD __tx_IntHandler ; Int 2 + DCD __tx_IntHandler ; Int 3 + +; +; + AREA ||.text||, CODE, READONLY + EXPORT Reset_Handler +Reset_Handler + CPSID i + IF {TARGET_FPU_VFP} = {TRUE} + LDR r0, =0xE000ED88 ; Pickup address of CPACR + LDR r1, [r0] ; Pickup CPACR + MOV32 r2, 0x00F00000 ; Build enable value + ORR r1, r1, r2 ; Or in enable value + STR r1, [r0] ; Setup CPACR + ENDIF + LDR r0, =__main + BX r0 + + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-M4/MPU/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + EXPORT _tx_initialize_low_level +_tx_initialize_low_level +; +; /* Disable interrupts during ThreadX initialization. */ +; + CPSID i +; +; /* Set base of available memory to end of non-initialised RAM area. */ +; + LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer + LDR r1, =|Image$$ZI$$Limit| ; Build first free address + ADD r1, r1, #4 ; + STR r1, [r0] ; Setup first unused memory pointer +; +; /* Setup Vector Table Offset Register. */ +; + MOV r0, #0xE000E000 ; Build address of NVIC registers + LDR r1, =__tx_vectors ; Pickup address of vector table + STR r1, [r0, #0xD08] ; Set vector table address +; +; /* Enable the cycle count register. */ +; +; LDR r0, =0xE0001000 ; Build address of DWT register +; LDR r1, [r0] ; Pickup the current value +; ORR r1, r1, #1 ; Set the CYCCNTENA bit +; STR r1, [r0] ; Enable the cycle count register +; +; /* Set system stack pointer from vector value. */ +; + LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer + LDR r1, =__tx_vectors ; Pickup address of vector table + LDR r1, [r1] ; Pickup reset stack pointer + STR r1, [r0] ; Save system stack pointer +; +; /* Configure SysTick. */ +; + MOV r0, #0xE000E000 ; Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] ; Setup SysTick Reload Value + MOV r1, #0x7 ; Build SysTick Control Enable Value + STR r1, [r0, #0x10] ; Setup SysTick Control +; +; /* Configure handler priorities. */ +; + LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] ; Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] ; Setup System Handlers 8-11 Priority Registers + ; Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] ; Setup System Handlers 12-15 Priority Registers + ; Note: PnSV must be lowest priority, which is 0xFF +; +; /* Return to caller. */ +; + BX lr +;} +; +; +;/* Define initial heap/stack routine for the ARM RVCT startup code. +; This routine will set the initial stack and heap locations */ +; + EXPORT __user_initial_stackheap +__user_initial_stackheap + LDR r0, =HeapMem + LDR r1, =(StackMem + STACK_SIZE) + LDR r2, =(HeapMem + HEAP_SIZE) + LDR r3, =StackMem + BX lr +; +; +;/* Define shells for each of the unused vectors. */ +; + EXPORT __tx_BadHandler +__tx_BadHandler + B __tx_BadHandler + +; EXPORT __tx_SVCallHandler +;__tx_SVCallHandler +; B __tx_SVCallHandler + + EXPORT __tx_IntHandler +__tx_IntHandler +; VOID InterruptHandler (VOID) +; { + PUSH {lr} + +; /* Do interrupt handler work here */ +; /* .... */ + + POP {lr} + BX LR +; } + + EXPORT __tx_SysTickHandler +__tx_SysTickHandler +; VOID TimerInterruptHandler (VOID) +; { +; + PUSH {lr} + BL _tx_timer_interrupt + POP {lr} + BX LR +; } + + EXPORT __tx_NMIHandler +__tx_NMIHandler + B __tx_NMIHandler + + EXPORT __tx_DBGHandler +__tx_DBGHandler + B __tx_DBGHandler + + EXPORT _tx_execution_thread_enter +_tx_execution_thread_enter + BX LR + + EXPORT _tx_execution_thread_exit +_tx_execution_thread_exit + BX LR + + ALIGN + LTORG + END + + diff --git a/ports_module/cortex-m4/ac5/example_build/txm_module_preamble.S b/ports_module/cortex-m4/ac5/example_build/txm_module_preamble.S new file mode 100644 index 00000000..1e7a1800 --- /dev/null +++ b/ports_module/cortex-m4/ac5/example_build/txm_module_preamble.S @@ -0,0 +1,69 @@ + AREA Init, CODE, READONLY + + PRESERVE8 + + ; Define public symbols + + EXPORT __txm_module_preamble + + + ; Define application-specific start/stop entry points for the module + + EXTERN demo_module_start + + + ; Define common external references + + IMPORT _txm_module_thread_shell_entry + IMPORT _txm_module_callback_request_thread_entry + IMPORT |Image$$ER_RO$$Length| + IMPORT |Image$$ER_RW$$Length| + IMPORT |Image$$ER_RW$$RW$$Length| + IMPORT |Image$$ER_RW$$ZI$$Length| + IMPORT |Image$$ER_ZI$$ZI$$Length| + +__txm_module_preamble + DCD 0x4D4F4455 ; Module ID + DCD 0x6 ; Module Major Version + DCD 0x1 ; Module Minor Version + DCD 32 ; Module Preamble Size in 32-bit words + DCD 0x12345678 ; Module ID (application defined) + DCD 0x01000007 ; Module Properties where: + ; Bits 31-24: Compiler ID + ; 0 -> IAR + ; 1 -> ARM + ; 2 -> GNU + ; Bit 0: 0 -> Privileged mode execution + ; 1 -> User mode execution + ; Bit 1: 0 -> No MPU protection + ; 1 -> MPU protection (must have user mode selected) + ; Bit 2: 0 -> Disable shared/external memory access + ; 1 -> Enable shared/external memory access + DCD _txm_module_thread_shell_entry - __txm_module_preamble ; Module Shell Entry Point + DCD demo_module_start - __txm_module_preamble ; Module Start Thread Entry Point + DCD 0 ; Module Stop Thread Entry Point + DCD 1 ; Module Start/Stop Thread Priority + DCD 1024 ; Module Start/Stop Thread Stack Size + DCD _txm_module_callback_request_thread_entry - __txm_module_preamble ; Module Callback Thread Entry + DCD 1 ; Module Callback Thread Priority + DCD 1024 ; Module Callback Thread Stack Size + DCD |Image$$ER_RO$$Length| + |Image$$ER_RW$$Length| ; Module Code Size + DCD |Image$$ER_RW$$Length| + |Image$$ER_ZI$$ZI$$Length| ; Module Data Size + DCD 0 ; Reserved 0 + DCD 0 ; Reserved 1 + DCD 0 ; Reserved 2 + DCD 0 ; Reserved 3 + DCD 0 ; Reserved 4 + DCD 0 ; Reserved 5 + DCD 0 ; Reserved 6 + DCD 0 ; Reserved 7 + DCD 0 ; Reserved 8 + DCD 0 ; Reserved 9 + DCD 0 ; Reserved 10 + DCD 0 ; Reserved 11 + DCD 0 ; Reserved 12 + DCD 0 ; Reserved 13 + DCD 0 ; Reserved 14 + DCD 0 ; Reserved 15 + + END diff --git a/ports_module/cortex-m4/ac5/inc/tx_port.h b/ports_module/cortex-m4/ac5/inc/tx_port.h new file mode 100644 index 00000000..07d26e6a --- /dev/null +++ b/ports_module/cortex-m4/ac5/inc/tx_port.h @@ -0,0 +1,477 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-M4/AC5 */ +/* 6.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX Cortex-M4 port. */ + +#define TX_INT_DISABLE 1 /* Disable interrupts */ +#define TX_INT_ENABLE 0 /* Enable interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0 + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); + +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) + +#ifndef TX_MISRA_ENABLE +register unsigned int _ipsr __asm("ipsr"); +#endif + +#ifdef __TARGET_FPU_VFP + +#ifdef TX_MISRA_ENABLE + +ULONG _tx_misra_control_get(void); +void _tx_misra_control_set(ULONG value); +ULONG _tx_misra_fpccr_get(void); +void _tx_misra_vfp_touch(void); + +#else + +#ifdef TX_SOURCE_CODE + +register ULONG _control __asm("control"); + +#endif +#endif + +/* A completed thread falls into _thread_shell_entry and we can simply deactivate the FPU via CONTROL.FPCA + in order to ensure no lazy stacking will occur. */ + +#ifndef TX_MISRA_ENABLE + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _control; \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _control = _tx_vfp_state; \ + } +#else + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } + +#endif + + +/* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. + If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + the lazy FPU save, then restore the CONTROL.FPCA state. */ + +#ifndef TX_MISRA_ENABLE + +void _tx_vfp_access(void); + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _control; \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _control = _tx_vfp_state; \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = *((ULONG *) 0xE000EF34); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _control; \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + _tx_vfp_access(); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = _control; \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _control = _tx_vfp_state; \ + } \ + } \ + } \ + } +#else + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = _tx_misra_fpccr_get(); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + _tx_misra_vfp_touch(); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + } \ + } \ + } +#endif + +#else + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + +#endif + + + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define the get system state macro. */ + +#ifndef TX_THREAD_GET_SYSTEM_STATE +#ifndef TX_MISRA_ENABLE +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _ipsr) +#else +ULONG _tx_misra_ipsr_get(VOID); +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get()) +#endif +#endif + + +/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value + indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h + for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always + zero after initialization for Cortex-M ports. */ + +#ifndef TX_THREAD_SYSTEM_RETURN_CHECK +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#endif + + +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to + prevent early scheduling on Cortex-M parts. */ + +#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; + + +/* This ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); + +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifdef TX_DISABLE_INLINE + +UINT _tx_thread_interrupt_disable(VOID); +VOID _tx_thread_interrupt_restore(UINT previous_posture); + +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); + +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA unsigned int was_masked; +#define TX_DISABLE was_masked = __disable_irq(); +#define TX_RESTORE if (was_masked == 0) __enable_irq(); + +#define _tx_thread_system_return _tx_thread_system_return_inline + + +static void _tx_thread_system_return_inline(void) +{ +unsigned int was_masked; + + + /* Set PendSV to invoke ThreadX scheduler. */ + *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + if (_ipsr == 0) + { + was_masked = __disable_irq(); + __enable_irq(); + if (was_masked != 0) + __disable_irq(); + } +} +#endif + + +/* Define FPU extension for the Cortex-M4. Each is assumed to be called in the context of the executing + thread. These are no longer needed, but are preserved for backward compatibility only. */ + +void tx_thread_fpu_enable(void); +void tx_thread_fpu_disable(void); + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/AC5 Version 6.1 *"; +#else +#ifdef TX_MISRA_ENABLE +extern CHAR _tx_version_id[100]; +#else +extern CHAR _tx_version_id[]; +#endif +#endif + + +#endif + + + + diff --git a/ports_module/cortex-m4/ac5/inc/txm_module_port.h b/ports_module/cortex-m4/ac5/inc/txm_module_port.h new file mode 100644 index 00000000..c720ab37 --- /dev/null +++ b/ports_module/cortex-m4/ac5/inc/txm_module_port.h @@ -0,0 +1,338 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* txm_module_port.h Cortex-M4/MPU/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the basic module constants, interface structures, */ +/* and function prototypes. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TXM_MODULE_PORT_H +#define TXM_MODULE_PORT_H + +/* Determine if the optional Modules user define file should be used. */ + +#ifdef TXM_MODULE_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in txm_module_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "txm_module_user.h" +#endif + +/* It is assumed that the base ThreadX tx_port.h file has been modified to add the + following extensions to the ThreadX thread control block (this code should replace + the corresponding macro define in tx_port.h): + +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; + +The following extensions must also be defined in tx_port.h: + +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); + +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); +*/ + + +/* Size of module heap. */ +#define TXM_MODULE_HEAP_SIZE 512 + + +/* Define the kernel stack size for a module thread. */ +#ifndef TXM_MODULE_KERNEL_STACK_SIZE +#define TXM_MODULE_KERNEL_STACK_SIZE 512 +#endif + +/* For the following 3 access control settings, change TEX and C, B, S (bits 21 through 16 of MPU_RASR) + * to reflect your system memory attributes (cache, shareable, memory type). */ +/* Code region access control: privileged read-only, outer & inner write-back, normal memory, shareable. */ +#define TXM_MODULE_MPU_CODE_ACCESS_CONTROL 0x06070000 +/* Data region access control: execute never, read/write, outer & inner write-back, normal memory, shareable. */ +#define TXM_MODULE_MPU_DATA_ACCESS_CONTROL 0x13070000 +/* Shared region access control: execute never, read-only, outer & inner write-back, normal memory, shareable. */ +#define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 + + +/* Define constants specific to the tools the module can be built with for this particular modules port. */ + +#define TXM_MODULE_IAR_COMPILER 0x00000000 +#define TXM_MODULE_RVDS_COMPILER 0x01000000 +#define TXM_MODULE_GNU_COMPILER 0x02000000 +#define TXM_MODULE_COMPILER_MASK 0xFF000000 +#define TXM_MODULE_OPTIONS_MASK 0x000000FF + + +/* Define the properties for this particular module port. */ + +#define TXM_MODULE_MEMORY_PROTECTION_ENABLED + +#ifdef TXM_MODULE_MEMORY_PROTECTION_ENABLED +#define TXM_MODULE_REQUIRE_ALLOCATED_OBJECT_MEMORY +#else +#define TXM_MODULE_REQUIRE_LOCAL_OBJECT_MEMORY +#endif + +#define TXM_MODULE_USER_MODE 0x00000001 +#define TXM_MODULE_MEMORY_PROTECTION 0x00000002 +#define TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS 0x00000004 + + +/* Define the supported options for this module. */ + +#define TXM_MODULE_MANAGER_SUPPORTED_OPTIONS (TXM_MODULE_USER_MODE | TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS) +#define TXM_MODULE_MANAGER_REQUIRED_OPTIONS 0 + + +/* Define offset adjustments according to the compiler used to build the module. */ + +#define TXM_MODULE_IAR_SHELL_ADJUST 24 +#define TXM_MODULE_IAR_START_ADJUST 28 +#define TXM_MODULE_IAR_STOP_ADJUST 32 +#define TXM_MODULE_IAR_CALLBACK_ADJUST 44 + +#define TXM_MODULE_RVDS_SHELL_ADJUST 0 +#define TXM_MODULE_RVDS_START_ADJUST 0 +#define TXM_MODULE_RVDS_STOP_ADJUST 0 +#define TXM_MODULE_RVDS_CALLBACK_ADJUST 0 + +#define TXM_MODULE_GNU_SHELL_ADJUST 24 +#define TXM_MODULE_GNU_START_ADJUST 28 +#define TXM_MODULE_GNU_STOP_ADJUST 32 +#define TXM_MODULE_GNU_CALLBACK_ADJUST 44 + + +/* Define other module port-specific constants. */ + +/* Define INLINE_DECLARE to inline for ARM compiler. */ + +#define INLINE_DECLARE inline + +/* Define the number of MPU entries assigned to the code and data sections. On Cortex-M parts, there can only be 7 total + entries, since ThreadX uses one for access to the kernel dispatch function. */ + +#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 +#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 +#define TXM_MODULE_MANAGER_SHARED_MPU_INDEX 8 +#define TXM_MODULE_MANAGER_SHARED_MPU_REGION 4 + +/* Shared memory region attributes. */ +#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 +#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 + +/* Define the port-extensions to the module manager instance structure. */ + +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + ULONG txm_module_instance_mpu_registers[16]; \ + ULONG txm_module_instance_shared_memory_address; \ + ULONG txm_module_instance_shared_memory_length; + + +/* Define the memory fault information structure that is populated when a memory fault occurs. */ + + +typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT +{ + TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr; + VOID *txm_module_manager_memory_fault_info_code_location; + ULONG txm_module_manager_memory_fault_info_shcsr; + ULONG txm_module_manager_memory_fault_info_cfsr; + ULONG txm_module_manager_memory_fault_info_mmfar; + ULONG txm_module_manager_memory_fault_info_bfar; + ULONG txm_module_manager_memory_fault_info_control; + ULONG txm_module_manager_memory_fault_info_sp; + ULONG txm_module_manager_memory_fault_info_r0; + ULONG txm_module_manager_memory_fault_info_r1; + ULONG txm_module_manager_memory_fault_info_r2; + ULONG txm_module_manager_memory_fault_info_r3; + ULONG txm_module_manager_memory_fault_info_r4; + ULONG txm_module_manager_memory_fault_info_r5; + ULONG txm_module_manager_memory_fault_info_r6; + ULONG txm_module_manager_memory_fault_info_r7; + ULONG txm_module_manager_memory_fault_info_r8; + ULONG txm_module_manager_memory_fault_info_r9; + ULONG txm_module_manager_memory_fault_info_r10; + ULONG txm_module_manager_memory_fault_info_r11; + ULONG txm_module_manager_memory_fault_info_r12; + ULONG txm_module_manager_memory_fault_info_lr; + ULONG txm_module_manager_memory_fault_info_xpsr; +} TXM_MODULE_MANAGER_MEMORY_FAULT_INFO; + + +#define TXM_MODULE_MANAGER_FAULT_INFO \ + TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info; + +/* Define the macro to check the code alignment. */ + +#define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment) \ + { \ + ULONG temp; \ + temp = (ULONG) module_location; \ + temp = temp & (code_alignment - 1); \ + if (temp) \ + { \ + _tx_mutex_put(&_txm_module_manager_mutex); \ + return(TXM_MODULE_ALIGNMENT_ERROR); \ + } \ + } + + +/* Define the macro to adjust the alignment and size for code/data areas. */ + +#define TXM_MODULE_MANAGER_ALIGNMENT_ADJUST(module_preamble, code_size, code_alignment, data_size, data_alignment) _txm_module_manager_alignment_adjust(module_preamble, &code_size, &code_alignment, &data_size, &data_alignment); + + +/* Define the macro to adjust the symbols in the module preamble. */ + +#define TXM_MODULE_MANAGER_CALCULATE_ADJUSTMENTS(properties, shell_function_adjust, start_function_adjust, stop_function_adjust, callback_function_adjust) \ + if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_IAR_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_IAR_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_IAR_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_IAR_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_IAR_CALLBACK_ADJUST; \ + } \ + else if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_RVDS_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_RVDS_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_RVDS_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_RVDS_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_RVDS_CALLBACK_ADJUST; \ + } \ + else \ + { \ + shell_function_adjust = TXM_MODULE_GNU_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_GNU_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_GNU_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_GNU_CALLBACK_ADJUST; \ + } + + +/* Define the macro to populate the thread control block with module port-specific information. + Check if the module is in user mode and set up txm_module_thread_entry_info_kernel_call_dispatcher accordingly. +*/ + +#define TXM_MODULE_MANAGER_THREAD_SETUP(thread_ptr, module_instance) \ + thread_ptr -> tx_thread_module_current_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \ + thread_ptr -> tx_thread_module_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \ + if (thread_ptr -> tx_thread_module_user_mode) \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_user_mode_entry; \ + } \ + else \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_kernel_dispatch; \ + } + + +/* Define the macro to populate the module control block with module port-specific information. + If memory protection is enabled, set up the MPU registers. +*/ +#define TXM_MODULE_MANAGER_MODULE_SETUP(module_instance) \ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE) \ + { \ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) \ + { \ + _txm_module_manager_mm_register_setup(module_instance); \ + } \ + } \ + else \ + { \ + /* Do nothing. */ \ + } + +/* Define the macro to perform port-specific functions when unloading the module. */ +/* Nothing needs to be done for this port. */ +#define TXM_MODULE_MANAGER_MODULE_UNLOAD(module_instance) + + +/* Define the macros to perform port-specific checks when passing pointers to the kernel. */ + +/* Define macro to make sure object is inside the module's data. */ +#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ + /* Check if it's inside module data. */ \ + ((((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && \ + (((obj_ptr) + (obj_size)) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) || \ + /* Check if it's inside shared memory. */ \ + (((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address) && \ + (((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (module_instance -> txm_module_instance_shared_memory_address + module_instance -> txm_module_instance_shared_memory_length)))) + + +/* Define some internal prototypes to this module port. */ + +#ifndef TX_SOURCE_CODE +#define txm_module_manager_memory_fault_notify _txm_module_manager_memory_fault_notify +#endif + + +#define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES \ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment); \ +VOID _txm_module_manager_memory_fault_handler(VOID); \ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)); \ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \ +ULONG _txm_power_of_two_block_size(ULONG size); \ +ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); \ +ULONG _txm_module_manager_region_size_get(ULONG block_size); + +#define TXM_MODULE_MANAGER_VERSION_ID \ +CHAR _txm_module_manager_version_id[] = \ + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/MPU/AC5 Version 6.1 *"; + +#endif diff --git a/ports_module/cortex-m4/ac5/module_lib/src/txm_module_initialize.S b/ports_module/cortex-m4/ac5/module_lib/src/txm_module_initialize.S new file mode 100644 index 00000000..f0c5ee68 --- /dev/null +++ b/ports_module/cortex-m4/ac5/module_lib/src/txm_module_initialize.S @@ -0,0 +1,112 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Module */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + IMPORT __use_two_region_memory + IMPORT __scatterload + IMPORT txm_heap + + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _txm_module_initialize Cortex-M4/MPU/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function initializes the module c runtime. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* __scatterload Initialize C runtime */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _txm_module_thread_shell_entry Start module thread */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _txm_module_initialize(VOID) + + EXPORT _txm_module_initialize +_txm_module_initialize + PUSH {r4-r12,lr} ; Save dregs and LR + + B __scatterload ; Call ARM func to initialize variables + +; +;/* Override __rt_exit function. */ +; + EXPORT __rt_exit +__rt_exit + + POP {r4-r12,lr} ; Restore dregs and LR + BX lr ; Return to caller +; +; +; + EXPORT __user_setup_stackheap + ; returns heap start address in R0 + ; returns heap end address in R2 + ; does not touch SP, it is already set up before the module runs + +__user_setup_stackheap + LDR r1, _tx_heap_offset ; load heap offset + ADD r0, r9, r1 ; calculate heap base address + MOV r2, #TXM_MODULE_HEAP_SIZE ; load heap size + ADD r2, r2, r0 ; calculate heap end address + BX lr + + ALIGN 4 +_tx_heap_offset + DCDO txm_heap + AREA ||.arm_vfe_header||, DATA, READONLY, NOALLOC, ALIGN=2 + + IMPORT txm_heap [DATA] + +; +; Dummy main function +; + AREA section_main, CODE, READONLY, ALIGN=2 + EXPORT main +main + BX lr + + END diff --git a/ports_module/cortex-m4/ac5/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex-m4/ac5/module_lib/src/txm_module_thread_shell_entry.c new file mode 100644 index 00000000..490b35db --- /dev/null +++ b/ports_module/cortex-m4/ac5/module_lib/src/txm_module_thread_shell_entry.c @@ -0,0 +1,173 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#ifndef TXM_MODULE +#define TXM_MODULE +#endif + +#ifndef TX_SOURCE_CODE +#define TX_SOURCE_CODE +#endif + + +/* Include necessary system files. */ + +#include "txm_module.h" +#include "tx_thread.h" + +/* Define the global module entry pointer from the start thread of the module. */ + +TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; + + +/* Define the dispatch function pointer used in the module implementation. */ + +ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3); + + +/* Define the ARM cstartup code. */ +extern VOID _txm_module_initialize(VOID); + +__align(8) UCHAR txm_heap[TXM_MODULE_HEAP_SIZE]; + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_thread_shell_entry Cortex-M4/MPU/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calls the specified entry function of the thread. It */ +/* also provides a place for the thread's entry function to return. */ +/* If the thread returns, this function places the thread in a */ +/* "COMPLETED" state. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to current thread */ +/* thread_info Pointer to thread entry info */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_initialize cstartup initialization */ +/* thread_entry Thread's entry function */ +/* tx_thread_resume Resume the module callback thread */ +/* _txm_module_thread_system_suspend Module thread suspension routine */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) +{ + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + VOID (*entry_exit_notify)(TX_THREAD *, UINT); +#endif + + + /* Determine if this is the start thread. If so, we must prepare the module for + execution. If not, simply skip the C startup code. */ + if (thread_info -> txm_module_thread_entry_info_start_thread) + { + /* Initialize the ARM C environment. */ + _txm_module_initialize(); + + /* Save the entry info pointer, for later use. */ + _txm_module_entry_info = thread_info; + + /* Save the kernel function dispatch address. This is used to make all resident calls from + the module. */ + _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; + + /* Ensure that we have a valid pointer. */ + while (!_txm_module_kernel_call_dispatcher) + { + /* Loop here, if an error is present getting the dispatch function pointer! + An error here typically indicates the resident portion of _tx_thread_schedule + is not supporting the trap to obtain the function pointer. */ + } + + /* Resume the module's callback thread, already created in the manager. */ + _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); + } + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has been entered! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_ENTRY); + } +#endif + + /* Call current thread's entry function. */ + (thread_info -> txm_module_thread_entry_info_entry) (thread_info -> txm_module_thread_entry_info_parameter); + + /* Suspend thread with a "completed" state. */ + + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine again. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has exited! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_EXIT); + } +#endif + + /* Call actual thread suspension routine. */ + _txm_module_thread_system_suspend(thread_ptr); + +#ifdef TX_SAFETY_CRITICAL + + /* If we ever get here, raise safety critical exception. */ + TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0); +#endif +} + diff --git a/ports_module/cortex-m4/ac5/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex-m4/ac5/module_manager/src/tx_thread_context_restore.S new file mode 100644 index 00000000..0ed36142 --- /dev/null +++ b/ports_module/cortex-m4/ac5/module_manager/src/tx_thread_context_restore.S @@ -0,0 +1,91 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_exit + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-M4/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + EXPORT _tx_thread_context_restore +_tx_thread_context_restore + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + PUSH {r0,lr} ; Save ISR lr + BL _tx_execution_isr_exit ; Call the ISR exit function + POP {r0,lr} ; Restore ISR lr + ENDIF +; + POP {lr} + BX lr +;} + ALIGN + LTORG + END diff --git a/ports_module/cortex-m4/ac5/module_manager/src/tx_thread_context_save.S b/ports_module/cortex-m4/ac5/module_manager/src/tx_thread_context_save.S new file mode 100644 index 00000000..a6827883 --- /dev/null +++ b/ports_module/cortex-m4/ac5/module_manager/src/tx_thread_context_save.S @@ -0,0 +1,91 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_enter + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-M4/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + EXPORT _tx_thread_context_save +_tx_thread_context_save + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {r0, lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {r0, lr} ; Recover ISR lr + ENDIF +; +; /* Return to interrupt processing. */ +; + BX lr ; Return to interrupt processing caller +;} + ALIGN + LTORG + END diff --git a/ports_module/cortex-m4/ac5/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex-m4/ac5/module_manager/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..ef983f17 --- /dev/null +++ b/ports_module/cortex-m4/ac5/module_manager/src/tx_thread_interrupt_control.S @@ -0,0 +1,76 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-M4/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + EXPORT _tx_thread_interrupt_control +_tx_thread_interrupt_control +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r1, PRIMASK + MSR PRIMASK, r0 + MOV r0, r1 + BX lr +; +;} + END diff --git a/ports_module/cortex-m4/ac5/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex-m4/ac5/module_manager/src/tx_thread_interrupt_disable.S new file mode 100644 index 00000000..6d11e5b8 --- /dev/null +++ b/ports_module/cortex-m4/ac5/module_manager/src/tx_thread_interrupt_disable.S @@ -0,0 +1,75 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-M4/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts and returning */ +;/* the previous interrupt lockout posture. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_disable(UINT new_posture) +;{ + EXPORT _tx_thread_interrupt_disable +_tx_thread_interrupt_disable +; +; /* Return current interrupt lockout posture. */ +; + MRS r0, PRIMASK + CPSID i + BX lr +; +;} + END diff --git a/ports_module/cortex-m4/ac5/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex-m4/ac5/module_manager/src/tx_thread_interrupt_restore.S new file mode 100644 index 00000000..0f52527b --- /dev/null +++ b/ports_module/cortex-m4/ac5/module_manager/src/tx_thread_interrupt_restore.S @@ -0,0 +1,74 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-M4/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for restoring the previous */ +;/* interrupt lockout posture. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* previous_posture Previous interrupt posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_interrupt_restore(UINT new_posture) +;{ + EXPORT _tx_thread_interrupt_restore +_tx_thread_interrupt_restore +; +; /* Restore previous interrupt lockout posture. */ +; + MSR PRIMASK, r0 + BX lr +; +;} + END diff --git a/ports_module/cortex-m4/ac5/module_manager/src/tx_thread_schedule.S b/ports_module/cortex-m4/ac5/module_manager/src/tx_thread_schedule.S new file mode 100644 index 00000000..820c5758 --- /dev/null +++ b/ports_module/cortex-m4/ac5/module_manager/src/tx_thread_schedule.S @@ -0,0 +1,539 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_execute_ptr + IMPORT _tx_timer_time_slice + IMPORT _tx_thread_system_stack_ptr + IF :DEF: TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_thread_enter + IMPORT _tx_execution_thread_exit + ENDIF + IMPORT _tx_thread_preempt_disable + IMPORT _txm_module_manager_memory_fault_handler + IMPORT _txm_module_manager_memory_fault_info + IMPORT _txm_module_priv + IMPORT _txm_module_user_mode_exit +; +; + AREA ||.text||, CODE, READONLY + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-M4/MPU/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + EXPORT _tx_thread_schedule +_tx_thread_schedule +; +; /* This function should only ever be called on Cortex-M +; from the first schedule request. Subsequent scheduling occurs +; from the PendSV handling routines below. */ +; +; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ +; + MOV r0, #0 ; Build value for TX_FALSE + LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag + STR r0, [r2, #0] ; Clear preempt disable flag +; +; /* Clear CONTROL.FPCA bit so FPU registers aren't unnecessarily stacked. */ +; + IF :DEF: __ARMVFP__ + MRS r0, CONTROL ; Pickup current CONTROL register + BIC r0, r0, #4 ; Clear the FPCA bit + MSR CONTROL, r0 ; Setup new CONTROL register + ENDIF +; +; /* Enable memory fault registers. */ +; + LDR r0, =0xE000ED24 ; Build SHCSR address + LDR r1, =0x70000 ; Enable Usage, Bus, and MemManage faults + STR r1, [r0] ; +; +; /* Enable interrupts */ +; + CPSIE i +; +; /* Enter the scheduler for the first time. */ +; + MOV r0, #0x10000000 ; Load PENDSVSET bit + MOV r1, #0xE000E000 ; Load NVIC base + STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR + DSB ; Complete all memory accesses + ISB ; Flush pipeline + +; /* Wait here for the PendSV to take place. */ + +__tx_wait_here + B __tx_wait_here ; Wait for the PendSV to happen +;} +; + +; +; /* Memory Exception Handler. */ +; + EXPORT MemManage_Handler +MemManage_Handler +;{ + CPSID i ; Disable interrupts +; +; /* Now pickup and store all the fault related information. */ +; + LDR r12,=_txm_module_manager_memory_fault_info ; Pickup fault info struct + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup the current thread pointer + STR r1, [r12, #0] ; Save current thread pointer in fault info structure + LDR r0, =0xE000ED24 ; Build SHCSR address + LDR r1, [r0] ; Pickup SHCSR + STR r1, [r12, #8] ; Save SHCSR + LDR r0, =0xE000ED28 ; Build CFSR address + LDR r1, [r0] ; Pickup CFSR + STR r1, [r12, #12] ; Save CFSR + LDR r0, =0xE000ED34 ; Build MMFAR address + LDR r1, [r0] ; Pickup MMFAR + STR r1, [r12, #16] ; Save MMFAR + LDR r0, =0xE000ED38 ; Build BFAR address + LDR r1, [r0] ; Pickup BFAR + STR r1, [r12, #20] ; Save BFAR + MRS r0, CONTROL ; Pickup current CONTROL register + STR r0, [r12, #24] ; Save CONTROL + MRS r1, PSP ; Pickup thread stack pointer + STR r1, [r12, #28] ; Save thread stack pointer + LDR r0, [r1] ; Pickup saved r0 + STR r0, [r12, #32] ; Save r0 + LDR r0, [r1, #4] ; Pickup saved r1 + STR r0, [r12, #36] ; Save r1 + STR r2, [r12, #40] ; Save r2 + STR r3, [r12, #44] ; Save r3 + STR r4, [r12, #48] ; Save r4 + STR r5, [r12, #52] ; Save r5 + STR r6, [r12, #56] ; Save r6 + STR r7, [r12, #60] ; Save r7 + STR r8, [r12, #64] ; Save r8 + STR r9, [r12, #68] ; Save r9 + STR r10,[r12, #72] ; Save r10 + STR r11,[r12, #76] ; Save r11 + LDR r0, [r1, #16] ; Pickup saved r12 + STR r0, [r12, #80] ; Save r12 + LDR r0, [r1, #20] ; Pickup saved lr + STR r0, [r12, #84] ; Save lr + LDR r0, [r1, #24] ; Pickup instruction address at point of fault + STR r0, [r12, #4] ; Save point of fault + LDR r0, [r1, #28] ; Pickup xPSR + STR r0, [r12, #88] ; Save xPSR + + MRS r0, CONTROL ; Pickup current CONTROL register + BIC r0, r0, #1 ; Clear the UNPRIV bit + MSR CONTROL, r0 ; Setup new CONTROL register + + LDR r0, =0xE000ED28 ; Build the Memory Management Fault Status Register (MMFSR) + LDRB r1, [r0] ; Pickup the MMFSR, with the following bit definitions: + ; Bit 0 = 1 -> Instruction address violation + ; Bit 1 = 1 -> Load/store address violation + ; Bit 7 = 1 -> MMFAR is valid + STRB r1, [r0] ; Clear the MMFSR + + IF :DEF: __ARMVFP__ + LDR r0, =0xE000EF34 ; Cleanup FPU context: Load FPCCR address + LDR r1, [r0] ; Load FPCCR + BIC r1, r1, #1 ; Clear the lazy preservation active bit + STR r1, [r0] ; Store the value + ENDIF + + BL _txm_module_manager_memory_fault_handler ; Call memory manager fault handler + + IF :DEF: TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + CPSID i ; Disable interrupts + BL _tx_execution_thread_exit ; Call the thread exit function + CPSIE i ; Enable interrupts + ENDIF + + MOV r1, #0 ; Build NULL value + LDR r0, =_tx_thread_current_ptr ; Pickup address of current thread pointer + STR r1, [r0] ; Clear current thread pointer + + ; Return from MemManage_Handler exception + LDR r0, =0xE000ED04 ; Load ICSR + LDR r1, =0x10000000 ; Set PENDSVSET bit + STR r1, [r0] ; Store ICSR + DSB ; Wait for memory access to complete + CPSIE i ; Enable interrupts + MOV lr, #0xFFFFFFFD ; Load exception return code + BX lr ; Return from exception +;} + +; +; /* Generic context PendSV handler. */ +; + EXPORT PendSV_Handler + EXPORT __tx_PendSVHandler +PendSV_Handler +__tx_PendSVHandler +; +; /* Get current thread value and new thread pointer. */ +; +__tx_ts_handler + + IF :DEF: TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + CPSID i ; Disable interrupts + PUSH {r0, lr} ; Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit ; Call the thread exit function + POP {r0, lr} ; Recover LR + CPSIE i ; Enable interrupts + ENDIF + MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address + MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address + MOV r3, #0 ; Build NULL value + LDR r1, [r0] ; Pickup current thread pointer +; +; /* Determine if there is a current thread to finish preserving. */ +; + CBZ r1, __tx_ts_new ; If NULL, skip preservation +; +; /* Recover PSP and preserve current thread context. */ +; + STR r3, [r0] ; Set _tx_thread_current_ptr to NULL + MRS r12, PSP ; Pickup PSP pointer (thread's stack pointer) + STMDB r12!, {r4-r11} ; Save its remaining registers + IF :DEF: __ARMVFP__ + TST LR, #0x10 ; Determine if the VFP extended frame is present + BNE _skip_vfp_save + VSTMDB r12!,{s16-s31} ; Yes, save additional VFP registers +_skip_vfp_save + ENDIF + MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable + STMDB r12!, {LR} ; Save LR on the stack +; +; /* Determine if time-slice is active. If it isn't, skip time handling processing. */ +; + LDR r5, [r4] ; Pickup current time-slice + STR r12, [r1, #8] ; Save the thread stack pointer + CBZ r5, __tx_ts_new ; If not active, skip processing +; +; /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ +; + STR r5, [r1, #24] ; Save current time-slice +; +; /* Clear the global time-slice. */ +; + STR r3, [r4] ; Clear time-slice +; +; /* Executing thread is now completely preserved!!! */ +; +__tx_ts_new +; +; /* Now we are looking for a new thread to execute! */ +; + CPSID i ; Disable interrupts + LDR r1, [r2] ; Is there another thread ready to execute? + CBZ r1, __tx_ts_wait ; No, skip to the wait processing +; +; /* Yes, another thread is ready for else, make the current thread the new thread. */ +; + STR r1, [r0] ; Setup the current thread pointer to the new thread + CPSIE i ; Enable interrupts +; +; /* Increment the thread run count. */ +; +__tx_ts_restore + LDR r7, [r1, #4] ; Pickup the current thread run count + MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable + LDR r5, [r1, #24] ; Pickup thread's current time-slice + ADD r7, r7, #1 ; Increment the thread run count + STR r7, [r1, #4] ; Store the new run count +; +; /* Setup global time-slice with thread's current time-slice. */ +; + STR r5, [r4] ; Setup global time-slice + + IF :DEF: TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + PUSH {r0, r1} ; Save r0 and r1 + BL _tx_execution_thread_enter ; Call the thread execution enter function + POP {r0, r1} ; Recover r0 and r1 + ENDIF +; +; /* Restore the thread context and PSP. */ +; + LDR r12, [r1, #8] ; Pickup thread's stack pointer + + MRS r5, CONTROL ; Pickup current CONTROL register + LDR r4, [r1, #0x98] ; Pickup current user mode flag + BIC r5, r5, #1 ; Clear the UNPRIV bit + ORR r4, r4, r5 ; Build new CONTROL register + MSR CONTROL, r4 ; Setup new CONTROL register + + LDR r0, =0xE000ED94 ; Build MPU control reg address + MOV r3, #0 ; Build disable value + STR r3, [r0] ; Disable MPU + LDR r0, [r1, #0x90] ; Pickup the module instance pointer + CBZ r0, skip_mpu_setup ; Is this thread owned by a module? No, skip MPU setup + LDR r1, [r0, #0x64] ; Pickup MPU register[0] + CBZ r1, skip_mpu_setup ; Is protection required for this module? No, skip MPU setup + LDR r1, =0xE000ED9C ; Build address of MPU base register + + ; Use alias registers to quickly load MPU + ADD r0, r0, #100 ; Build address of MPU register start in thread control block + LDM r0!,{r2-r9} ; Load MPU regions 0-3 + STM r1,{r2-r9} ; Store MPU regions 0-3 + LDM r0!,{r2-r9} ; Load MPU regions 4-7 + STM r1,{r2-r9} ; Store MPU regions 4-7 + LDR r0, =0xE000ED94 ; Build MPU control reg address + MOV r1, #5 ; Build enable value with background region enabled + STR r1, [r0] ; Enable MPU +skip_mpu_setup + LDMIA r12!, {LR} ; Pickup LR + IF :DEF: __ARMVFP__ + TST LR, #0x10 ; Determine if the VFP extended frame is present + BNE _skip_vfp_restore ; If not, skip VFP restore + VLDMIA r12!, {s16-s31} ; Yes, restore additional VFP registers +_skip_vfp_restore + ENDIF + LDMIA r12!, {r4-r11} ; Recover thread's registers + MSR PSP, r12 ; Setup the thread's stack pointer +; +; /* Return to thread. */ +; + BX lr ; Return to thread! +; +; /* The following is the idle wait processing... in this case, no threads are ready for execution and the +; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +; are disabled to allow use of WFI for waiting for a thread to arrive. */ +; +__tx_ts_wait + CPSID i ; Disable interrupts + LDR r1, [r2] ; Pickup the next thread to execute pointer + STR r1, [r0] ; Store it in the current pointer + CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready! + IF :DEF:TX_ENABLE_WFI + DSB ; Ensure no outstanding memory transactions + WFI ; Wait for interrupt + ISB ; Ensure pipeline is flushed + ENDIF + CPSIE i ; Enable interrupts + B __tx_ts_wait ; Loop to continue waiting +; +; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +; already in the handler! */ +; +__tx_ts_ready + MOV r7, #0x08000000 ; Build clear PendSV value + MOV r8, #0xE000E000 ; Build base NVIC address + STR r7, [r8, #0xD04] ; Clear any PendSV +; +; /* Re-enable interrupts and restore new thread. */ +; + CPSIE i ; Enable interrupts + B __tx_ts_restore ; Restore the thread +;} + +; +; /* SVC Handler. */ +; + EXPORT SVC_Handler + EXPORT __tx_SVCallHandler +SVC_Handler +__tx_SVCallHandler +;{ + MRS r0, PSP ; Pickup the PSP stack + LDR r1, [r0, #24] ; Pickup the point of interrupt + LDRB r2, [r1, #-2] ; Pickup the SVC parameter + ; + ; Determine which SVC trap we are processing + ; + CMP r2, #1 ; Is it the entry into ThreadX? + BNE _tx_thread_user_return ; No, return to user mode + ; + ; At this point we have an SVC 1, which means we are entering the kernel from a module thread with user mode selected + ; + LDR r2, =_txm_module_priv ; Subtract 1 because of THUMB mode. + SUB r2, r2, #1 ; Temporary fix until ARM describes how to load label above correctly. + CMP r1, r2 ; Did we come from user_mode_entry? + IT NE ; If no (not equal), then... + BXNE lr ; return from where we came. + + LDR r3, [r0, #20] ; This is the saved LR + LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r2, [r1] ; Pickup current thread pointer + MOV r1, #0 ; Build clear value + STR r1, [r2, #0x98] ; Clear the current user mode selection for thread + STR r3, [r2, #0xA0] ; Save the original LR in thread control block + + ; If there is memory protection, use kernel stack + LDR r0, [r2, #0x90] ; Load the module instance ptr + LDR r0, [r0, #0x0C] ; Load the module property flags + TST r0, #2 ; Check if memory protected + BEQ _tx_skip_kernel_stack_enter + + ; Switch to the module thread's kernel stack + LDR r0, [r2, #0xA8] ; Load the module kernel stack end + IF :LNOT: :DEF: TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + LDR r1, [r2, #0xA4] ; Load the module kernel stack start + LDR r3, [r2, #0xAC] ; Load the module kernel stack size + STR r1, [r2, #12] ; Set stack start + STR r0, [r2, #16] ; Set stack end + STR r3, [r2, #20] ; Set stack size + ENDIF + + MRS r3, PSP ; Pickup thread stack pointer + STR r3, [r2, #0xB0] ; Save thread stack pointer + + ; Build kernel stack by copying thread stack two registers at a time + ADD r3, r3, #32 ; start at bottom of hardware stack + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + + MSR PSP, r0 ; Set kernel stack pointer + +_tx_skip_kernel_stack_enter + MRS r0, CONTROL ; Pickup current CONTROL register + BIC r0, r0, #1 ; Clear the UNPRIV bit + MSR CONTROL, r0 ; Setup new CONTROL register + BX lr ; Return to thread + +_tx_thread_user_return + LDR r2, =_txm_module_user_mode_exit ; Subtract 1 because of THUMB mode. + SUB r2, r2, #1 ; Temporary fix until ARM describes how to load label above correctly. + CMP r1, r2 ; Did we come from user_mode_exit? + IT NE ; If no (not equal), then... + BXNE lr ; return from where we came + + LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r2, [r1] ; Pickup current thread pointer + LDR r1, [r2, #0x9C] ; Pick up user mode + STR r1, [r2, #0x98] ; Set the current user mode selection for thread + + ; If there is memory protection, use kernel stack + LDR r0, [r2, #0x90] ; Load the module instance ptr + LDR r0, [r0, #0x0C] ; Load the module property flags + TST r0, #2 ; Check if memory protected + BEQ _tx_skip_kernel_stack_exit + + IF :LNOT: :DEF: TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + LDR r0, [r2, #0xB4] ; Load the module thread stack start + LDR r1, [r2, #0xB8] ; Load the module thread stack end + LDR r3, [r2, #0xBC] ; Load the module thread stack size + STR r0, [r2, #12] ; Set stack start + STR r1, [r2, #16] ; Set stack end + STR r3, [r2, #20] ; Set stack size + ENDIF + LDR r0, [r2, #0xB0] ; Load the module thread stack pointer + MRS r3, PSP ; Pickup kernel stack pointer + + ; Copy kernel hardware stack to module thread stack. + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + SUB r0, r0, #32 ; Subtract 32 to get back to top of stack + MSR PSP, r0 ; Set thread stack pointer + + LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r2, [r1] ; Pickup current thread pointer + LDR r1, [r2, #0x9C] ; Pick up user mode + +_tx_skip_kernel_stack_exit + MRS r0, CONTROL ; Pickup current CONTROL register + ORR r0, r0, r1 ; OR in the user mode bit + MSR CONTROL, r0 ; Setup new CONTROL register + BX lr ; Return to thread +;} + + IF :DEF: __ARMVFP__ + EXPORT tx_thread_fpu_enable +tx_thread_fpu_enable +; +; /* Automatic VPF logic is supported, this function is present only for +; backward compatibility purposes and therefore simply returns. */ +; + BX LR ; Return to caller + ENDIF + + IF :DEF: __ARMVFP__ + EXPORT tx_thread_fpu_disable +tx_thread_fpu_disable +; +; /* Automatic VPF logic is supported, this function is present only for +; backward compatibility purposes and therefore simply returns. */ +; + BX LR ; Return to caller + ENDIF + + ALIGN 4 + END diff --git a/ports_module/cortex-m4/ac5/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex-m4/ac5/module_manager/src/tx_thread_stack_build.S new file mode 100644 index 00000000..f548938b --- /dev/null +++ b/ports_module/cortex-m4/ac5/module_manager/src/tx_thread_stack_build.S @@ -0,0 +1,133 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-M4/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + EXPORT _tx_thread_stack_build +_tx_thread_stack_build +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-M4 should look like the following after it is built: +; +; Stack Top: +; LR Interrupted LR (LR at time of PENDSV) +; r4 Initial value for r4 +; r5 Initial value for r5 +; r6 Initial value for r6 +; r7 Initial value for r7 +; r8 Initial value for r8 +; r9 Initial value for r9 +; r10 Initial value for r10 +; r11 Initial value for r11 +; r0 Initial value for r0 (Hardware stack starts here!!) +; r1 Initial value for r1 +; r2 Initial value for r2 +; r3 Initial value for r3 +; r12 Initial value for r12 +; lr Initial value for lr +; pc Initial value for pc +; xPSR Initial value for xPSR +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #0x7 ; Align frame for 8-byte alignment + SUB r2, r2, #68 ; Subtract frame size + LDR r3, =0xFFFFFFFD ; Build initial LR value + STR r3, [r2, #0] ; Save on the stack +; +; /* Actually build the stack frame. */ +; + MOV r3, #0 ; Build initial register value + STR r3, [r2, #4] ; Store initial r4 + STR r3, [r2, #8] ; Store initial r5 + STR r3, [r2, #12] ; Store initial r6 + STR r3, [r2, #16] ; Store initial r7 + STR r3, [r2, #20] ; Store initial r8 + STR r3, [r2, #24] ; Store initial r9 + STR r3, [r2, #28] ; Store initial r10 + STR r3, [r2, #32] ; Store initial r11 +; +; /* Hardware stack follows. */ +; + STR r3, [r2, #36] ; Store initial r0 + STR r3, [r2, #40] ; Store initial r1 + STR r3, [r2, #44] ; Store initial r2 + STR r3, [r2, #48] ; Store initial r3 + STR r3, [r2, #52] ; Store initial r12 + MOV r3, #0xFFFFFFFF ; Poison EXC_RETURN value + STR r3, [r2, #56] ; Store initial lr + STR r1, [r2, #60] ; Store initial pc + MOV r3, #0x01000000 ; Only T-bit need be set + STR r3, [r2, #64] ; Store initial xPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block + BX lr ; Return to caller +;} + END diff --git a/ports_module/cortex-m4/ac5/module_manager/src/tx_thread_system_return.S b/ports_module/cortex-m4/ac5/module_manager/src/tx_thread_system_return.S new file mode 100644 index 00000000..9c453e61 --- /dev/null +++ b/ports_module/cortex-m4/ac5/module_manager/src/tx_thread_system_return.S @@ -0,0 +1,85 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-M4/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + EXPORT _tx_thread_system_return +_tx_thread_system_return +; +; /* Return to real scheduler via PendSV. Note that this routine is often +; replaced with in-line assembly in tx_port.h to improved performance. */ +; + MOV r0, #0x10000000 ; Load PENDSVSET bit + MOV r1, #0xE000E000 ; Load NVIC base + STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR + MRS r0, IPSR ; Pickup IPSR + CMP r0, #0 ; Is it a thread returning? + BNE _isr_context ; If ISR, skip interrupt enable + MRS r1, PRIMASK ; Thread context returning, pickup PRIMASK + CPSIE i ; Enable interrupts + MSR PRIMASK, r1 ; Restore original interrupt posture +_isr_context + BX lr ; Return to caller +;} + END diff --git a/ports_module/cortex-m4/ac5/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex-m4/ac5/module_manager/src/tx_timer_interrupt.S new file mode 100644 index 00000000..f5160174 --- /dev/null +++ b/ports_module/cortex-m4/ac5/module_manager/src/tx_timer_interrupt.S @@ -0,0 +1,259 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + IMPORT _tx_timer_time_slice + IMPORT _tx_timer_system_clock + IMPORT _tx_timer_current_ptr + IMPORT _tx_timer_list_start + IMPORT _tx_timer_list_end + IMPORT _tx_timer_expired_time_slice + IMPORT _tx_timer_expired + IMPORT _tx_thread_time_slice + IMPORT _tx_timer_expiration_process + IMPORT _tx_thread_preempt_disable + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_execute_ptr +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-M4/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + EXPORT _tx_timer_interrupt +_tx_timer_interrupt +; +; /* Upon entry to this routine, it is assumed that context save has already +; been called, and therefore the compiler scratch registers are available +; for use. */ +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + MOV32 r1, _tx_timer_system_clock ; Pickup address of system clock + LDR r0, [r1, #0] ; Pickup system clock + ADD r0, r0, #1 ; Increment system clock + STR r0, [r1, #0] ; Store new system clock +; +; /* Test for time-slice expiration. */ +; if (_tx_timer_time_slice) +; { +; + MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice + LDR r2, [r3, #0] ; Pickup time-slice + CBZ r2, __tx_timer_no_time_slice ; Is it non-active? + ; Yes, skip time-slice processing +; +; /* Decrement the time_slice. */ +; _tx_timer_time_slice--; +; + SUB r2, r2, #1 ; Decrement the time-slice + STR r2, [r3, #0] ; Store new time-slice value +; +; /* Check for expiration. */ +; if (__tx_timer_time_slice == 0) +; + CBNZ r2, __tx_timer_no_time_slice ; Has it expired? +; +; /* Set the time-slice expired flag. */ +; _tx_timer_expired_time_slice = TX_TRUE; +; + MOV32 r3, _tx_timer_expired_time_slice ; Pickup address of expired flag + MOV r0, #1 ; Build expired value + STR r0, [r3, #0] ; Set time-slice expiration flag +; +; } +; +__tx_timer_no_time_slice +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + MOV32 r1, _tx_timer_current_ptr ; Pickup current timer pointer address + LDR r0, [r1, #0] ; Pickup current timer + LDR r2, [r0, #0] ; Pickup timer list entry + CBZ r2, __tx_timer_no_timer ; Is there anything in the list? + ; No, just increment the timer +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + MOV32 r3, _tx_timer_expired ; Pickup expiration flag address + MOV r2, #1 ; Build expired value + STR r2, [r3, #0] ; Set expired flag + B __tx_timer_done ; Finished timer processing +; +; } +; else +; { +__tx_timer_no_timer +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ADD r0, r0, #4 ; Move to next timer +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + MOV32 r3, _tx_timer_list_end ; Pickup addr of timer list end + LDR r2, [r3, #0] ; Pickup list end + CMP r0, r2 ; Are we at list end? + BNE __tx_timer_skip_wrap ; No, skip wrap-around logic +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + MOV32 r3, _tx_timer_list_start ; Pickup addr of timer list start + LDR r0, [r3, #0] ; Set current pointer to list start +; +__tx_timer_skip_wrap +; + STR r0, [r1, #0] ; Store new current timer pointer +; } +; +__tx_timer_done +; +; +; /* See if anything has expired. */ +; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +; { +; + MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of expired flag + LDR r2, [r3, #0] ; Pickup time-slice expired flag + CBNZ r2, __tx_something_expired ; Did a time-slice expire? + ; If non-zero, time-slice expired + MOV32 r1, _tx_timer_expired ; Pickup addr of other expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CBZ r0, __tx_timer_nothing_expired ; Did a timer expire? + ; No, nothing expired +; +__tx_something_expired +; +; + STMDB sp!, {r0, lr} ; Save the lr register on the stack + ; and save r0 just to keep 8-byte alignment +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + MOV32 r1, _tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CBZ r0, __tx_timer_dont_activate ; Check for timer expiration + ; If not set, skip timer activation +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + BL _tx_timer_expiration_process ; Call the timer expiration handling routine +; +; } +__tx_timer_dont_activate +; +; /* Did time slice expire? */ +; if (_tx_timer_expired_time_slice) +; { +; + MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r2, [r3, #0] ; Pickup the actual flag + CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set + ; No, skip time-slice processing +; +; /* Time slice interrupted thread. */ +; _tx_thread_time_slice(); + + BL _tx_thread_time_slice ; Call time-slice processing + MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag + LDR r1, [r0] ; Is the preempt disable flag set? + CBNZ r1, __tx_timer_skip_time_slice ; Yes, skip the PendSV logic + MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup the current thread pointer + MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address + LDR r3, [r2] ; Pickup the execute thread pointer + MOV32 r0, 0xE000ED04 ; Build address of control register + MOV32 r2, 0x10000000 ; Build value for PendSV bit + CMP r1, r3 ; Are they the same? + BEQ __tx_timer_skip_time_slice ; If the same, there was no time-slice performed + STR r2, [r0] ; Not the same, issue the PendSV for preemption +__tx_timer_skip_time_slice +; +; } +; +__tx_timer_not_ts_expiration +; + LDMIA sp!, {r0, lr} ; Recover lr register (r0 is just there for +; +; } +; +__tx_timer_nothing_expired + + DSB ; Complete all memory access + BX lr ; Return to caller +; +;} + ALIGN + LTORG + END diff --git a/ports_module/cortex-m4/ac5/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex-m4/ac5/module_manager/src/txm_module_manager_alignment_adjust.c new file mode 100644 index 00000000..2f945552 --- /dev/null +++ b/ports_module/cortex-m4/ac5/module_manager/src/txm_module_manager_alignment_adjust.c @@ -0,0 +1,399 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_power_of_two_block_size Cortex-M4/MPU/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calculates a power of two size at or immediately above*/ +/* the input size and returns it to the caller. */ +/* */ +/* INPUT */ +/* */ +/* size Block size */ +/* */ +/* OUTPUT */ +/* */ +/* calculated size Rounded up to power of two */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_power_of_two_block_size(ULONG size) +{ + /* Check for 0 size. */ + if(size == 0) + return 0; + + /* Minimum MPU block size is 32. */ + if(size <= 32) + return 32; + + /* Bit twiddling trick to round to next high power of 2 + (if original size is power of 2, it will return original size. Perfect!) */ + size--; + size |= size >> 1; + size |= size >> 2; + size |= size >> 4; + size |= size >> 8; + size |= size >> 16; + size++; + + /* Return a power of 2 size at or above the input size. */ + return(size); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_alignment_adjust Cortex-M4/MPU/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function adjusts the alignment and size of the code and data */ +/* section for a given module implementation. */ +/* */ +/* INPUT */ +/* */ +/* module_preamble Pointer to module preamble */ +/* code_size Size of the code area (updated) */ +/* code_alignment Code area alignment (updated) */ +/* data_size Size of data area (updated) */ +/* data_alignment Data area alignment (updated) */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_power_of_two_block_size Calculate power of two size */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, + ULONG *code_size, + ULONG *code_alignment, + ULONG *data_size, + ULONG *data_alignment) +{ + +ULONG local_code_size; +ULONG local_code_alignment; +ULONG local_data_size; +ULONG local_data_alignment; +ULONG code_block_size; +ULONG data_block_size; +ULONG code_size_accum; +ULONG data_size_accum; + + /* Copy the input parameters into local variables for ease of use. */ + local_code_size = *code_size; + local_code_alignment = *code_alignment; + local_data_size = *data_size; + local_data_alignment = *data_alignment; + + + /* Test for external memory enabled in preamble. */ + if(module_preamble -> txm_module_preamble_property_flags & TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS) + { + /* External/shared memory enabled. TXM_MODULE_MANAGER_CODE_MPU_ENTRIES-1 code entries will be used. */ + if (local_code_size <= (32*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 32 is best. */ + code_block_size = 32; + } + else if (local_code_size <= (64*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 64 is best. */ + code_block_size = 64; + } + else if (local_code_size <= (128*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 128 is best. */ + code_block_size = 128; + } + else if (local_code_size <= (256*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 256 is best. */ + code_block_size = 256; + } + else if (local_code_size <= (512*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 512 is best. */ + code_block_size = 512; + } + else if (local_code_size <= (1024*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 1024 is best. */ + code_block_size = 1024; + } + else if (local_code_size <= (2048*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 2048 is best. */ + code_block_size = 2048; + } + else if (local_code_size <= (4096*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 4096 is best. */ + code_block_size = 4096; + } + else if (local_code_size <= (8192*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 8192 is best. */ + code_block_size = 8192; + } + else if (local_code_size <= (16384*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 16384 is best. */ + code_block_size = 16384; + } + else if (local_code_size <= (32768*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 32768 is best. */ + code_block_size = 32768; + } + else if (local_code_size <= (65536*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 65536 is best. */ + code_block_size = 65536; + } + else if (local_code_size <= (131072*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 131072 is best. */ + code_block_size = 131072; + } + else if (local_code_size <= (262144*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 262144 is best. */ + code_block_size = 262144; + } + else if (local_code_size <= (524288*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 524288 is best. */ + code_block_size = 524288; + } + else if (local_code_size <= (1048576*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 1048576 is best. */ + code_block_size = 1048576; + } + else if (local_code_size <= (2097152*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 2097152 is best. */ + code_block_size = 2097152; + } + else if (local_code_size <= (4194304*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 4194304 is best. */ + code_block_size = 4194304; + } + else + { + /* Just set block size to 32MB just to create an allocation error! */ + code_block_size = 33554432; + } + + /* Calculate the new code size. */ + local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); + + /* Determine if the code block size is greater than the current alignment. If so, use block size + as the alignment. */ + if (code_block_size > local_code_alignment) + local_code_alignment = code_block_size; + + } + else + { + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + local_code_alignment = _txm_power_of_two_block_size(local_code_size) >> 2; + code_size_accum = local_code_alignment + local_code_alignment; + code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); + code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); + local_code_size = code_size_accum; + } + + /* Determine the best data block size, which in our case is the minimal alignment. */ + if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 32 is best. */ + data_block_size = 32; + } + else if (local_data_size <= (64*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 64 is best. */ + data_block_size = 64; + } + else if (local_data_size <= (128*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 128 is best. */ + data_block_size = 128; + } + else if (local_data_size <= (256*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 256 is best. */ + data_block_size = 256; + } + else if (local_data_size <= (512*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 512 is best. */ + data_block_size = 512; + } + else if (local_data_size <= (1024*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 1024 is best. */ + data_block_size = 1024; + } + else if (local_data_size <= (2048*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 2048 is best. */ + data_block_size = 2048; + } + else if (local_data_size <= (4096*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 4096 is best. */ + data_block_size = 4096; + } + else if (local_data_size <= (8192*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 8192 is best. */ + data_block_size = 8192; + } + else if (local_data_size <= (16384*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 16384 is best. */ + data_block_size = 16384; + } + else if (local_data_size <= (32768*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 32768 is best. */ + data_block_size = 32768; + } + else if (local_data_size <= (65536*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 65536 is best. */ + data_block_size = 65536; + } + else if (local_data_size <= (131072*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 131072 is best. */ + data_block_size = 131072; + } + else if (local_data_size <= (262144*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 262144 is best. */ + data_block_size = 262144; + } + else if (local_data_size <= (524288*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 524288 is best. */ + data_block_size = 524288; + } + else if (local_data_size <= (1048576*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 1048576 is best. */ + data_block_size = 1048576; + } + else if (local_data_size <= (2097152*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 2097152 is best. */ + data_block_size = 2097152; + } + else if (local_data_size <= (4194304*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 4194304 is best. */ + data_block_size = 4194304; + } + else + { + /* Just set data block size to 32MB just to create an allocation error! */ + data_block_size = 33554432; + } + + /* Calculate the new data size. */ + data_size_accum = data_block_size; + while(data_size_accum < local_data_size) + { + data_size_accum += data_block_size; + } + local_data_size = data_size_accum; + + /* Determine if the data block size is greater than the current alignment. If so, use block size + as the alignment. */ + if (data_block_size > local_data_alignment) + { + local_data_alignment = data_block_size; + } + + /* Return all the information to the caller. */ + *code_size = local_code_size; + *code_alignment = local_code_alignment; + *data_size = local_data_size; + *data_alignment = local_data_alignment; +} diff --git a/ports_module/cortex-m4/ac5/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex-m4/ac5/module_manager/src/txm_module_manager_external_memory_enable.c new file mode 100644 index 00000000..3eed0481 --- /dev/null +++ b/ports_module/cortex-m4/ac5/module_manager/src/txm_module_manager_external_memory_enable.c @@ -0,0 +1,182 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_mutex.h" +#include "tx_queue.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_external_memory_enable Cortex-M4/MPU/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates an entry in the MPU table for a shared */ +/* memory space. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* start_address Start address of memory */ +/* length Length of external memory */ +/* attributes Memory attributes (r/w) */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_mutex_get Get protection mutex */ +/* _tx_mutex_put Release protection mutex */ +/* _txm_power_of_two_block_size Round length to power of two */ +/* _txm_module_manager_mm_register_setup Reconfigure MPU registers */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, + VOID *start_address, + ULONG length, + UINT attributes) +{ + +ULONG block_size; +ULONG region_size; +ULONG subregion_bits; +ULONG address; +UINT attributes_check = 0; +TXM_MODULE_PREAMBLE *module_preamble; + + /* Determine if the module manager has not been initialized yet. */ + if (_txm_module_manager_ready != TX_TRUE) + { + /* Module manager has not been initialized. */ + return(TX_NOT_AVAILABLE); + } + + /* Determine if the module is valid. */ + if (module_instance == TX_NULL) + { + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Get module manager protection mutex. */ + _tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER); + + /* Determine if the module instance is valid. */ + if (module_instance -> txm_module_instance_id != TXM_MODULE_ID) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Determine if the module instance is in the loaded state. */ + if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if the module is not ready. */ + return(TX_START_ERROR); + } + + /* Check if preamble shared mem and mem protection property bits are set. */ + module_preamble = module_instance -> txm_module_instance_preamble_ptr; + if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) + != (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if bit not set. */ + return(TXM_MODULE_INVALID_PROPERTIES); + } + + /* Start address and length must adhere to Cortex-M MPU. + The address must align with the block size. */ + + block_size = _txm_power_of_two_block_size(length); + address = (ULONG) start_address; + if(address != (address & ~(block_size - 1))) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return alignment error. */ + return(TXM_MODULE_ALIGNMENT_ERROR); + } + + /* At this point, we have a valid address and block size. + Set up MPU registers. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | 0x10; + + /* Calculate the region size. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + /* Calculate the subregion bits. */ + subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); + + /* Check for valid attributes. */ + if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) + { + attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; + } + + /* Build register with attributes. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX+1] = region_size | subregion_bits | attributes_check | 0x12070001; + + /* Keep track of shared memory address and length in module instance. */ + module_instance -> txm_module_instance_shared_memory_address = address; + module_instance -> txm_module_instance_shared_memory_length = length; + + /* Recalculate MPU settings. */ + _txm_module_manager_mm_register_setup(module_instance); + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/ports_module/cortex-m4/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex-m4/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c new file mode 100644 index 00000000..9efd8bdc --- /dev/null +++ b/ports_module/cortex-m4/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -0,0 +1,110 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + +/* Define a macro that can be used to allocate global variables useful to + store information about the last fault. This macro is defined in + txm_module_port.h and is usually populated in the assembly language + fault handling prior to the code calling _txm_module_manager_memory_fault_handler. */ + +TXM_MODULE_MANAGER_FAULT_INFO + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_handler Cortex-M4/MPU/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles a fault associated with a memory protected */ +/* module. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_terminate Terminate thread */ +/* */ +/* CALLED BY */ +/* */ +/* Fault handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_memory_fault_handler(VOID) +{ + +TXM_MODULE_INSTANCE *module_instance_ptr; +TX_THREAD *thread_ptr; + + /* Pickup the current thread. */ + thread_ptr = _tx_thread_current_ptr; + + /* Initialize the module instance pointer to NULL. */ + module_instance_ptr = TX_NULL; + + /* Is there a thread? */ + if (thread_ptr) + { + /* Pickup the module instance. */ + module_instance_ptr = thread_ptr -> tx_thread_module_instance_ptr; + + /* Terminate the current thread. */ + _tx_thread_terminate(_tx_thread_current_ptr); + } + + /* Determine if there is a user memory fault notification callback. */ + if (_txm_module_manager_fault_notify) + { + /* Yes, call the user's notification memory fault callback. */ + (_txm_module_manager_fault_notify)(thread_ptr, module_instance_ptr); + } +} diff --git a/ports_module/cortex-m4/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex-m4/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c new file mode 100644 index 00000000..43a782f1 --- /dev/null +++ b/ports_module/cortex-m4/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -0,0 +1,84 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the external user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_notify Cortex-M4/MPU/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application callback when/if a memory */ +/* fault occurs. The supplied thread is automatically terminated, but */ +/* any other threads in the same module may still execute. */ +/* */ +/* INPUT */ +/* */ +/* notify_function Memory fault notification */ +/* function, NULL disables. */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +{ + /* Setup notification function. */ + _txm_module_manager_fault_notify = notify_function; + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/ports_module/cortex-m4/ac5/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex-m4/ac5/module_manager/src/txm_module_manager_mm_register_setup.c new file mode 100644 index 00000000..b48dada5 --- /dev/null +++ b/ports_module/cortex-m4/ac5/module_manager/src/txm_module_manager_mm_register_setup.c @@ -0,0 +1,512 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_region_size_get Cortex-M4/MPU/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function converts the region size in bytes to the block size */ +/* for the Cortex-M4 MPU specification. */ +/* */ +/* INPUT */ +/* */ +/* block_size Size of the block in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* MPU size specification */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_module_manager_region_size_get(ULONG block_size) +{ + +ULONG return_value; + + /* Process relative to the input block size. */ + if (block_size == 32) + { + return_value = 0x04; + } + else if (block_size == 64) + { + return_value = 0x05; + } + else if (block_size == 128) + { + return_value = 0x06; + } + else if (block_size == 256) + { + return_value = 0x07; + } + else if (block_size == 512) + { + return_value = 0x08; + } + else if (block_size == 1024) + { + return_value = 0x09; + } + else if (block_size == 2048) + { + return_value = 0x0A; + } + else if (block_size == 4096) + { + return_value = 0x0B; + } + else if (block_size == 8192) + { + return_value = 0x0C; + } + else if (block_size == 16384) + { + return_value = 0x0D; + } + else if (block_size == 32768) + { + return_value = 0x0E; + } + else if (block_size == 65536) + { + return_value = 0x0F; + } + else if (block_size == 131072) + { + return_value = 0x10; + } + else if (block_size == 262144) + { + return_value = 0x11; + } + else if (block_size == 524288) + { + return_value = 0x12; + } + else if (block_size == 1048576) + { + return_value = 0x13; + } + else if (block_size == 2097152) + { + return_value = 0x14; + } + else + { + /* Max 4MB MPU pages for modules. */ + return_value = 0x15; + } + + return(return_value); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_calculate_srd_bits Cortex-M4/MPU/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calculates the SRD bits that need to be set to */ +/* protect "length" bytes in a block. */ +/* */ +/* INPUT */ +/* */ +/* block_size Size of the block in bytes */ +/* length Actual length in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* SRD bits to be OR'ed with region attribute register. */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) +{ + +ULONG srd_bits = 0; +UINT srd_bit_index; + + /* length is smaller than block_size, set SRD bits if block_size is 256 or more. */ + if((block_size >= 256) && (length < block_size)) + { + /* Divide block_size by 8 by shifting right 3. Result is size of subregion. */ + block_size = block_size >> 3; + + /* Set SRD index into attribute register. */ + srd_bit_index = 8; + + /* If subregion overlaps length, move to the next subregion. */ + while(length > block_size) + { + length = length - block_size; + srd_bit_index++; + } + /* Check for a portion of code remaining. */ + if(length) + { + srd_bit_index++; + } + + /* Set unused subregion bits. */ + while(srd_bit_index < 16) + { + srd_bits = srd_bits | (0x1 << srd_bit_index); + srd_bit_index++; + } + } + + return(srd_bits); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_mm_register_setup Cortex-M4/MPU/AC5 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets up the Cortex-M4 MPU register definitions based */ +/* on the module's memory characteristics. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* */ +/* OUTPUT */ +/* */ +/* MPU specifications for module in module_instance */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_manager_region_size_get */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_thread_create */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) +{ + +ULONG code_address; +ULONG code_size; +ULONG data_address; +ULONG data_size; +ULONG start_stop_stack_size; +ULONG callback_stack_size; +ULONG block_size; +ULONG base_address_register; +ULONG base_attribute_register; +ULONG region_size; +ULONG srd_bits = 0; +UINT mpu_register = 0; +UINT mpu_table_index; +UINT i; + + + /* Setup the first region for the ThreadX trampoline code. */ + /* Set base register to user mode entry, which is guaranteed to be at least 32-byte aligned. */ + base_address_register = (ULONG) _txm_module_manager_user_mode_entry; + + /* Mask address to proper range, region 0, set Valid bit. */ + base_address_register = (base_address_register & 0xFFFFFFE0) | mpu_register | 0x10; + module_instance -> txm_module_instance_mpu_registers[0] = base_address_register; + + /* Attributes: read only, write-back, shareable, size 32 bytes, region enabled. */ + module_instance -> txm_module_instance_mpu_registers[1] = 0x06070009; + + /* Initialize the MPU register. */ + mpu_register = 1; + + /* Initialize the MPU table index. */ + mpu_table_index = 2; + + /* Setup values for code area. */ + code_address = (ULONG) module_instance -> txm_module_instance_code_start; + code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; + + /* Check if shared memory was set up. If so, only 3 entries are available for + code protection. If not set up, 4 code entries are available. */ + if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] == 0) + { + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + + /* Now loop through to setup MPU protection for the code area. */ + for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES; i++) + { + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + if (i < 2) + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + } + + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ + else if (i == 2) + { + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size) >> 1; + } + + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + else + { + /* Calculate remaining space. */ + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + + /* Build the base address register. */ + base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Build the base attribute register. */ + base_attribute_register = region_size | srd_bits | 0x06070001; + + /* Setup the MPU Base Address Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; + + /* Setup the MPU Base Attribute Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; + + /* Adjust the code address. */ + code_address = code_address + block_size; + + /* Move MPU table index. */ + mpu_table_index = mpu_table_index + 2; + + /* Increment the MPU register index. */ + mpu_register++; + } + } + + /* Only 3 code entries available. */ + else + { + /* Calculate block size, one code entry taken up by shared memory. */ + block_size = _txm_power_of_two_block_size(code_size / (TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)); + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Now loop through to setup MPU protection for the code area. */ + for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) + { + /* Build the base address register. */ + base_address_register = code_address & ~(block_size - 1) | mpu_register | 0x10; + + /* Check if SRD bits need to be set. */ + if (code_size < block_size) + { + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + + /* Build the base attribute register. */ + base_attribute_register = region_size | srd_bits | 0x06070000; + + /* Is there still some code? If so set the region enable bit. */ + if (code_size) + { + /* Set the region enable bit. */ + base_attribute_register = base_attribute_register | 0x1; + } + /* Setup the MPU Base Address Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; + + /* Setup the MPU Base Attribute Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; + + /* Adjust the code address. */ + code_address = code_address + block_size; + + /* Decrement the code size. */ + if (code_size > block_size) + { + code_size = code_size - block_size; + } + else + { + code_size = 0; + } + + /* Move MPU table index. */ + mpu_table_index = mpu_table_index + 2; + + /* Increment the MPU register index. */ + mpu_register++; + } + + /* Adjust indeces to pass over the shared memory entry. */ + /* Move MPU table index. */ + mpu_table_index = mpu_table_index + 2; + + /* Increment the MPU register index. */ + mpu_register++; + } + + /* Setup values for data area. */ + data_address = (ULONG) module_instance -> txm_module_instance_data_start; + + /* Adjust the size of the module elements to be aligned to the default alignment. We do this + so that when we partition the allocated memory, we can simply place these regions right beside + each other without having to align their pointers. Note this only works when they all have + the same alignment. */ + + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; + start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; + callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; + + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + /* Update the data size to include thread stacks. */ + data_size = data_size + start_stop_stack_size + callback_stack_size; + + block_size = _txm_power_of_two_block_size(data_size / TXM_MODULE_MANAGER_DATA_MPU_ENTRIES); + + /* Reset SRD bitfield. */ + srd_bits = 0; + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Now loop through to setup MPU protection for the data area. */ + for (i = 0; i < TXM_MODULE_MANAGER_DATA_MPU_ENTRIES; i++) + { + /* Build the base address register. */ + base_address_register = (data_address & ~(block_size - 1)) | mpu_register | 0x10; + + /* Check if SRD bits need to be set. */ + if (data_size < block_size) + { + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + } + + /* Build the base attribute register. */ + base_attribute_register = region_size | srd_bits | 0x13070000; + + /* Is there still some data? If so set the region enable bit. */ + if (data_size) + { + /* Set the region enable bit. */ + base_attribute_register = base_attribute_register | 0x1; + } + + /* Setup the MPU Base Address Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; + + /* Setup the MPU Base Attribute Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; + + /* Adjust the data address. */ + data_address = data_address + block_size; + + /* Decrement the data size. */ + if (data_size > block_size) + { + data_size = data_size - block_size; + } + else + { + data_size = 0; + } + + /* Move MPU table index. */ + mpu_table_index = mpu_table_index + 2; + + /* Increment the MPU register index. */ + mpu_register++; + } +} diff --git a/ports_module/cortex-m4/ac5/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex-m4/ac5/module_manager/src/txm_module_manager_thread_stack_build.S new file mode 100644 index 00000000..ec7f5f97 --- /dev/null +++ b/ports_module/cortex-m4/ac5/module_manager/src/txm_module_manager_thread_stack_build.S @@ -0,0 +1,141 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Module Manager */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + AREA ||.text||, CODE, READONLY + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _txm_module_manager_thread_stack_build Cortex-M4/MPU/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread */ +;/* function_ptr Pointer to shell function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +;{ + EXPORT _txm_module_manager_thread_stack_build +_txm_module_manager_thread_stack_build +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-M should look like the following after it is built: +; +; Stack Top: +; LR Interrupted LR (LR at time of PENDSV) +; r4 Initial value for r4 +; r5 Initial value for r5 +; r6 Initial value for r6 +; r7 Initial value for r7 +; r8 Initial value for r8 +; r9 Initial value for r9 +; r10 Initial value for r10 +; r11 Initial value for r11 +; r0 Initial value for r0 (Hardware stack starts here!!) +; r1 Initial value for r1 +; r2 Initial value for r2 +; r3 Initial value for r3 +; r12 Initial value for r12 +; lr Initial value for lr +; pc Initial value for pc +; xPSR Initial value for xPSR +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #0x7 ; Align frame + SUB r2, r2, #68 ; Subtract frame size + LDR r3, =0xFFFFFFFD ; Build initial LR value + STR r3, [r2, #0] ; Save on the stack +; +; /* Actually build the stack frame. */ +; + MOV r3, #0 ; Build initial register value + STR r3, [r2, #4] ; Store initial r4 + STR r3, [r2, #8] ; Store initial r5 + STR r3, [r2, #12] ; Store initial r6 + STR r3, [r2, #16] ; Store initial r7 + STR r3, [r2, #20] ; Store initial r8 + STR r3, [r2, #28] ; Store initial r10 + STR r3, [r2, #32] ; Store initial r11 +; +; /* Hardware stack follows. */ +; + STR r0, [r2, #36] ; Store initial r0, which is the thread control block + + LDR r3, [r0, #8] ; Pickup thread entry info pointer,which is in the stack pointer position of the thread control block. + ; It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this + ; function with the actual, initial stack pointer. + STR r3, [r2, #40] ; Store initial r1, which is the module entry information. + LDR r3, [r3, #8] ; Pickup data base register from the module information + STR r3, [r2, #24] ; Store initial r9 (data base register) + MOV r3, #0 ; Clear r3 again + + STR r3, [r2, #44] ; Store initial r2 + STR r3, [r2, #48] ; Store initial r3 + STR r3, [r2, #52] ; Store initial r12 + MOV r3, #0xFFFFFFFF ; Poison EXC_RETURN value + STR r3, [r2, #56] ; Store initial lr + STR r1, [r2, #60] ; Store initial pc + MOV r3, #0x01000000 ; Only T-bit need be set + STR r3, [r2, #64] ; Store initial xPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's control block + BX lr ; Return to caller +;} + END + diff --git a/ports_module/cortex-m4/ac5/module_manager/src/txm_module_manager_user_mode_entry.S b/ports_module/cortex-m4/ac5/module_manager/src/txm_module_manager_user_mode_entry.S new file mode 100644 index 00000000..28ffe970 --- /dev/null +++ b/ports_module/cortex-m4/ac5/module_manager/src/txm_module_manager_user_mode_entry.S @@ -0,0 +1,88 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Module Manager */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; + IMPORT _txm_module_manager_kernel_dispatch + IMPORT _tx_thread_current_ptr +; + AREA ||.text||, CODE, READONLY, ALIGN=5 + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _txm_module_manager_user_mode_entry Cortex-M4/MPU/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function allows modules to enter kernel mode. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* SVC 1 Enter kernel mode */ +;/* SVC 2 Exit kernel mode */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Modules in user mode */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/; +;VOID _txm_module_manager_user_mode_entry(VOID) +;{ + EXPORT _txm_module_manager_user_mode_entry +_txm_module_manager_user_mode_entry + SVC 1 ; Enter kernel + EXPORT _txm_module_priv +_txm_module_priv + ; At this point, we are out of user mode. The original LR has been saved in the + ; thread control block. Simply call the kernel dispatch function. + BL _txm_module_manager_kernel_dispatch + + ; Pickup the original LR value while still in privileged mode + LDR r2, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r3, [r2] ; Pickup current thread pointer + LDR lr, [r3, #0xA0] ; Pickup saved LR from original call + + SVC 2 ; Exit kernel and return to user mode + EXPORT _txm_module_user_mode_exit +_txm_module_user_mode_exit + BX lr ; Return to the caller +;} + ALIGN 32 + END diff --git a/ports_module/cortex-m4/ac6/example_build/all.bat b/ports_module/cortex-m4/ac6/example_build/all.bat new file mode 100644 index 00000000..748e5743 --- /dev/null +++ b/ports_module/cortex-m4/ac6/example_build/all.bat @@ -0,0 +1,5 @@ +@ECHO OFF +CALL clean.bat +CALL setenv.bat +CALL initws.bat +CALL build.bat diff --git a/ports_module/cortex-m4/ac6/example_build/build.bat b/ports_module/cortex-m4/ac6/example_build/build.bat new file mode 100644 index 00000000..6ebdf460 --- /dev/null +++ b/ports_module/cortex-m4/ac6/example_build/build.bat @@ -0,0 +1,24 @@ +@ECHO OFF + +ECHO Build starting... + +SETLOCAL ENABLEEXTENSIONS + +IF DEFINED ARMDSIDEC GOTO IARBUILD_DEFINED +ECHO ERROR: please set ARMDSIDEC to the path of the ARM Developer Studio eclipsec.exe program +EXIT /B 2 +:IARBUILD_DEFINED + +IF EXIST %ARMDSIDEC% GOTO ARMDSIDEC_FOUND +ECHO ERROR: the command ARMDSIDEC doesn't exist: %ARMDSIDEC% +EXIT /B 2 +:ARMDSIDEC_FOUND + +%ARMDSIDEC% -nosplash -application org.eclipse.cdt.managedbuilder.core.headlessbuild -data .\workspace -build all +IF %ERRORLEVEL% EQU 0 GOTO BUILD_OK +ECHO ERROR: build failed. +EXIT /B 1 +:BUILD_OK + +ECHO Build completed without errors. +EXIT /B 0 diff --git a/ports_module/cortex-m4/ac6/example_build/clean.bat b/ports_module/cortex-m4/ac6/example_build/clean.bat new file mode 100644 index 00000000..8a48e5c9 --- /dev/null +++ b/ports_module/cortex-m4/ac6/example_build/clean.bat @@ -0,0 +1,4 @@ +@ECHO OFF +ECHO Cleaning... +RMDIR /Q /S workspace +ECHO Done. diff --git a/ports_module/cortex-m4/ac6/example_build/initws.bat b/ports_module/cortex-m4/ac6/example_build/initws.bat new file mode 100644 index 00000000..62806594 --- /dev/null +++ b/ports_module/cortex-m4/ac6/example_build/initws.bat @@ -0,0 +1,14 @@ +@ECHO OFF + +ECHO Initializing the workspace... + +SETLOCAL ENABLEEXTENSIONS + +%ARMDSIDEC% -nosplash -application org.eclipse.cdt.managedbuilder.core.headlessbuild -data .\workspace -import .\tx -import .\txm -import .\sample_threadx -import .\sample_threadx_module -import .\sample_threadx_module_manager +IF %ERRORLEVEL% EQU 0 GOTO WS_INITIALIZED +ECHO ERROR: failed to initialize the workspace +EXIT /B 2 + +:WS_INITIALIZED +echo Workspace initialized. +EXIT /B 0 diff --git a/ports_module/cortex-m4/ac6/example_build/sample_threadx/.cproject b/ports_module/cortex-m4/ac6/example_build/sample_threadx/.cproject new file mode 100644 index 00000000..1772051b --- /dev/null +++ b/ports_module/cortex-m4/ac6/example_build/sample_threadx/.cproject @@ -0,0 +1,192 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_module/cortex-m4/ac6/example_build/sample_threadx/.project b/ports_module/cortex-m4/ac6/example_build/sample_threadx/.project new file mode 100644 index 00000000..2a6b3cb1 --- /dev/null +++ b/ports_module/cortex-m4/ac6/example_build/sample_threadx/.project @@ -0,0 +1,28 @@ + + + sample_threadx + + + tx + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.arm.debug.ds.nature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/ports_module/cortex-m4/ac6/example_build/sample_threadx/exceptions.c b/ports_module/cortex-m4/ac6/example_build/sample_threadx/exceptions.c new file mode 100644 index 00000000..01dd0b27 --- /dev/null +++ b/ports_module/cortex-m4/ac6/example_build/sample_threadx/exceptions.c @@ -0,0 +1,96 @@ +/* +** Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. +** Use, modification and redistribution of this file is subject to your possession of a +** valid End User License Agreement for the Arm Product of which these examples are part of +** and your compliance with all applicable terms and conditions of such licence agreement. +*/ + +/* This file contains the default exception handlers and vector table. +All exceptions are handled in Handler mode. Processor state is automatically +pushed onto the stack when an exception occurs, and popped from the stack at +the end of the handler */ + + +/* Exception Handlers */ +/* Marking as __attribute__((interrupt)) avoids them being accidentally called from elsewhere */ + +__attribute__((interrupt)) void NMIException(void) +{ while(1); } + +__attribute__((interrupt)) void HardFaultException(void) +{ while(1); } + +__attribute__((interrupt)) void MemManageException(void) +{ while(1); } + +__attribute__((interrupt)) void BusFaultException(void) +{ while(1); } + +__attribute__((interrupt)) void UsageFaultException(void) +{ while(1); } + +void __tx_SVCallHandler(void); + +__attribute__((interrupt)) void DebugMonitor(void) +{ while(1); } + +void __tx_PendSVHandler(void); + +void __tx_SysTickHandler(void); + +__attribute__((interrupt)) void InterruptHandler(void) +{ while(1); } + + +/* typedef for the function pointers in the vector table */ +typedef void(* const ExecFuncPtr)(void) __attribute__((interrupt)); + +/* Linker-generated Stack Base address */ +#ifdef TWO_REGION +extern unsigned int Image$$ARM_LIB_STACK$$ZI$$Limit; /* for Two Region model */ +#else +extern unsigned int Image$$ARM_LIB_STACKHEAP$$ZI$$Limit; /* for (default) One Region model */ +#endif + +/* Entry point for C run-time initialization */ +extern int __main(void); + + +/* Vector table +Create a named ELF section for the vector table that can be placed in a scatter file. +The first two entries are: + Initial SP = |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit| for (default) One Region model + or |Image$$ARM_LIB_STACK$$ZI$$Limit| for Two Region model + Initial PC= &__main (with LSB set to indicate Thumb) +*/ + +ExecFuncPtr vector_table[] __attribute__((section("vectors"))) = { + /* Configure Initial Stack Pointer using linker-generated symbol */ +#ifdef TWO_REGION + #pragma import(__use_two_region_memory) + (ExecFuncPtr)&Image$$ARM_LIB_STACK$$ZI$$Limit, +#else /* (default) One Region model */ + (ExecFuncPtr)&Image$$ARM_LIB_STACKHEAP$$ZI$$Limit, +#endif + (ExecFuncPtr)__main, /* Initial PC, set to entry point */ + NMIException, + HardFaultException, + MemManageException, + BusFaultException, + UsageFaultException, + 0, 0, 0, 0, /* Reserved */ + __tx_SVCallHandler, + DebugMonitor, + 0, /* Reserved */ + __tx_PendSVHandler, + __tx_SysTickHandler, + + /* Add up to 240 interrupt handlers, starting here... */ + InterruptHandler, + InterruptHandler, /* Some dummy interrupt handlers */ + InterruptHandler + /* + : + */ +}; + diff --git a/ports_module/cortex-m4/ac6/example_build/sample_threadx/sample_threadx.c b/ports_module/cortex-m4/ac6/example_build/sample_threadx/sample_threadx.c new file mode 100644 index 00000000..597f373c --- /dev/null +++ b/ports_module/cortex-m4/ac6/example_build/sample_threadx/sample_threadx.c @@ -0,0 +1,370 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; +UCHAR memory_area[DEMO_BYTE_POOL_SIZE]; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports_module/cortex-m4/ac6/example_build/sample_threadx/sample_threadx.launch b/ports_module/cortex-m4/ac6/example_build/sample_threadx/sample_threadx.launch new file mode 100644 index 00000000..44324fe3 --- /dev/null +++ b/ports_module/cortex-m4/ac6/example_build/sample_threadx/sample_threadx.launch @@ -0,0 +1,204 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_module/cortex-m4/ac6/example_build/sample_threadx/sample_threadx.scat b/ports_module/cortex-m4/ac6/example_build/sample_threadx/sample_threadx.scat new file mode 100644 index 00000000..eb8e0c23 --- /dev/null +++ b/ports_module/cortex-m4/ac6/example_build/sample_threadx/sample_threadx.scat @@ -0,0 +1,44 @@ +;******************************************************* +; Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. +; Use, modification and redistribution of this file is subject to your possession of a +; valid End User License Agreement for the Arm Product of which these examples are part of +; and your compliance with all applicable terms and conditions of such licence agreement. +;******************************************************* + +; Scatter-file for Cortex-M4 bare-metal example + +; This scatter-file places the vector table, application code, data, stacks and heap at suitable addresses in the memory map. + +; The vector table is placed first at the start of the image. +; Code starts after the last entry in the vector table. +; Data is placed at an address that must correspond to RAM. +; Stack and Heap are placed using ARM_LIB_STACKHEAP, to eliminate the need to set stack-base or heap-base in the debugger. +; System Control Space registers appear at their architecturally-defined addresses, based at 0xE000E000. + + +LOAD_REGION 0x00000000 +{ + VECTORS +0 0xC0 ; 16 exceptions + up to 32 interrupts, 4 bytes each entry == 0xC0 + { + exceptions.o (vectors, +FIRST) ; from exceptions.c + } + + ; Code is placed immediately (+0) after the previous root region + ; (so code region will also be a root region) + CODE +0 + { + * (+RO) ; All program code, including library code + } + + DATA +0 + { + * (+RW, +ZI) ; All RW and ZI data + } + + ; Heap grows upwards from start of this region and + ; Stack grows downwards from end of this region + ; The Main Stack Pointer is initialized on reset to the top addresses of this region + ARM_LIB_STACKHEAP +0 EMPTY 0x1000 + { + } +} diff --git a/ports_module/cortex-m4/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports_module/cortex-m4/ac6/example_build/sample_threadx/tx_initialize_low_level.S new file mode 100644 index 00000000..aba34291 --- /dev/null +++ b/ports_module/cortex-m4/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -0,0 +1,231 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global _tx_timer_interrupt + .global __main + .global __tx_NMIHandler // NMI + .global __tx_BadHandler // HardFault + .global __tx_SVCallHandler // SVCall + .global __tx_DBGHandler // Monitor + .global __tx_PendSVHandler // PendSV + .global __tx_SysTickHandler // SysTick + .global __tx_IntHandler // Int 0 + + +SYSTEM_CLOCK = 6000000 +SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) + + + .text 32 + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-M4/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_initialize_low_level(VOID) +// { + .global _tx_initialize_low_level + .thumb_func +_tx_initialize_low_level: + + /* Disable interrupts during ThreadX initialization. */ + + CPSID i + + /* Set base of available memory to end of non-initialised RAM area. */ + + LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer + LDR r1, =Image$$ARM_LIB_STACKHEAP$$ZI$$Limit // Build first free address + ADD r1, r1, #4 // + STR r1, [r0] // Setup first unused memory pointer + + /* Setup Vector Table Offset Register. */ + + MOV r0, #0xE000E000 // Build address of NVIC registers + LDR r1, =vector_table // Pickup address of vector table + STR r1, [r0, #0xD08] // Set vector table address + + /* Set system stack pointer from vector value. */ + + LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer + LDR r1, =vector_table // Pickup address of vector table + LDR r1, [r1] // Pickup reset stack pointer + STR r1, [r0] // Save system stack pointer + + /* Enable the cycle count register. */ + + LDR r0, =0xE0001000 // Build address of DWT register + LDR r1, [r0] // Pickup the current value + ORR r1, r1, #1 // Set the CYCCNTENA bit + STR r1, [r0] // Enable the cycle count register + + /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ + + MOV r0, #0xE000E000 // Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] // Setup SysTick Reload Value + MOV r1, #0x7 // Build SysTick Control Enable Value + STR r1, [r0, #0x10] // Setup SysTick Control + + /* Configure handler priorities. */ + + LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] // Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] // Setup System Handlers 8-11 Priority Registers + // Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] // Setup System Handlers 12-15 Priority Registers + // Note: PnSV must be lowest priority, which is 0xFF + + /* Return to caller. */ + + BX lr +// } + + +/* Define shells for each of the unused vectors. */ + + .global __tx_BadHandler + .thumb_func +__tx_BadHandler: + B __tx_BadHandler + +/* added to catch the hardfault */ + + .global __tx_HardfaultHandler + .thumb_func +__tx_HardfaultHandler: + B __tx_HardfaultHandler + +/* Generic interrupt handler template */ + .global __tx_IntHandler + .thumb_func +__tx_IntHandler: +// VOID InterruptHandler (VOID) +// { + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter // Call the ISR enter function +#endif + + /* Do interrupt handler work here */ + /* BL .... */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit // Call the ISR exit function +#endif + POP {r0, lr} + BX LR +// } + +/* System Tick timer interrupt handler */ + .global __tx_SysTickHandler + .global SysTick_Handler + .thumb_func +__tx_SysTickHandler: + .thumb_func +SysTick_Handler: +// VOID TimerInterruptHandler (VOID) +// { + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter // Call the ISR enter function +#endif + BL _tx_timer_interrupt +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit // Call the ISR exit function +#endif + POP {r0, lr} + BX LR +// } + + +/* NMI, DBG handlers */ + .global __tx_NMIHandler + .thumb_func +__tx_NMIHandler: + B __tx_NMIHandler + + .global __tx_DBGHandler + .thumb_func +__tx_DBGHandler: + B __tx_DBGHandler + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +/* Execution change notify functions */ + .global _tx_execution_isr_enter + .thumb_func +_tx_execution_isr_enter: + BX LR +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +/* Execution change notify functions */ + .global _tx_execution_isr_exit + .thumb_func +_tx_execution_isr_exit: + BX LR +#endif diff --git a/ports_module/cortex-m4/ac6/example_build/sample_threadx_module/.cproject b/ports_module/cortex-m4/ac6/example_build/sample_threadx_module/.cproject new file mode 100644 index 00000000..1dbc5a70 --- /dev/null +++ b/ports_module/cortex-m4/ac6/example_build/sample_threadx_module/.cproject @@ -0,0 +1,250 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_module/cortex-m4/ac6/example_build/sample_threadx_module/.project b/ports_module/cortex-m4/ac6/example_build/sample_threadx_module/.project new file mode 100644 index 00000000..5f1f1fa6 --- /dev/null +++ b/ports_module/cortex-m4/ac6/example_build/sample_threadx_module/.project @@ -0,0 +1,28 @@ + + + sample_threadx_module + + + txm + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.arm.debug.ds.nature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/ports_module/cortex-m4/ac6/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex-m4/ac6/example_build/sample_threadx_module/sample_threadx_module.c new file mode 100644 index 00000000..f2647144 --- /dev/null +++ b/ports_module/cortex-m4/ac6/example_build/sample_threadx_module/sample_threadx_module.c @@ -0,0 +1,432 @@ +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, + event flags group, byte pool, and block pool. */ + +/* Specify that this is a module! */ + +#define TXM_MODULE + + +/* Include the ThreadX module definitions. */ + +#include "txm_module.h" + + +/* Define constants. */ + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the external memory area. */ + +#define EXTERNAL_MEMORY_SIZE (64 * 1024) +#define EXTERNAL_MEMORY (0x80000) + + +/* Define the pool space in the bss section of the module. ULONG is used to + get the word alignment. */ + +ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD *thread_0; +TX_THREAD *thread_1; +TX_THREAD *thread_2; +TX_THREAD *thread_3; +TX_THREAD *thread_4; +TX_THREAD *thread_5; +TX_THREAD *thread_6; +TX_THREAD *thread_7; +TX_QUEUE *queue_0; +TX_SEMAPHORE *semaphore_0; +TX_MUTEX *mutex_0; +TX_EVENT_FLAGS_GROUP *event_flags_0; +TX_BYTE_POOL *byte_pool_0; +TX_BLOCK_POOL *block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; +ULONG semaphore_0_puts; +ULONG event_0_sets; +ULONG queue_0_sends; + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + +void semaphore_0_notify(TX_SEMAPHORE *semaphore_ptr) +{ + + if (semaphore_ptr == semaphore_0) + semaphore_0_puts++; +} + + +void event_0_notify(TX_EVENT_FLAGS_GROUP *event_flag_group_ptr) +{ + + if (event_flag_group_ptr == event_flags_0) + event_0_sets++; +} + + +void queue_0_notify(TX_QUEUE *queue_ptr) +{ + + if (queue_ptr == queue_0) + queue_0_sends++; +} + + +/* Define the module start function. */ + +void demo_module_start(ULONG id) +{ + +CHAR *pointer; + + /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + the control block(s). */ + txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_2, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_3, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_4, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_5, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_6, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_7, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&queue_0, sizeof(TX_QUEUE)); + txm_module_object_allocate((void*)&semaphore_0, sizeof(TX_SEMAPHORE)); + txm_module_object_allocate((void*)&mutex_0, sizeof(TX_MUTEX)); + txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); + txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); + txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(queue_0, "module queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + tx_queue_send_notify(queue_0, queue_0_notify); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(semaphore_0, "module semaphore 0", 1); + + tx_semaphore_put_notify(semaphore_0, semaphore_0_notify); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(event_flags_0, "module event flags 0"); + + tx_event_flags_set_notify(event_flags_0, event_0_notify); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(mutex_0, "module mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(block_pool_0, "module block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + /* Test external memory sharing. */ + *(ULONG *)EXTERNAL_MEMORY = 0xABABABAB; + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + diff --git a/ports_module/cortex-m4/ac6/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex-m4/ac6/example_build/sample_threadx_module/txm_module_preamble.S new file mode 100644 index 00000000..1fcc5d15 --- /dev/null +++ b/ports_module/cortex-m4/ac6/example_build/sample_threadx_module/txm_module_preamble.S @@ -0,0 +1,62 @@ + .text + .align 4 + .syntax unified + .section Init + + // Define public symbols + .global __txm_module_preamble + + // Define application-specific start/stop entry points for the module + .global demo_module_start + + // Define common external references + .global _txm_module_thread_shell_entry + .global _txm_module_callback_request_thread_entry + + .eabi_attribute Tag_ABI_PCS_RO_data, 1 + .eabi_attribute Tag_ABI_PCS_R9_use, 1 + .eabi_attribute Tag_ABI_PCS_RW_data, 2 + +__txm_module_preamble: + .dc.l 0x4D4F4455 // Module ID + .dc.l 0x6 // Module Major Version + .dc.l 0x1 // Module Minor Version + .dc.l 32 // Module Preamble Size in 32-bit words + .dc.l 0x12345678 // Module ID (application defined) + .dc.l 0x01000007 // Module Properties where: + // Bits 31-24: Compiler ID + // 0 -> IAR + // 1 -> ARM + // 2 -> GNU + // Bit 0: 0 -> Privileged mode execution + // 1 -> User mode execution + // Bit 1: 0 -> No MPU protection + // 1 -> MPU protection (must have user mode selected) + // Bit 2: 0 -> Disable shared/external memory access + // 1 -> Enable shared/external memory access + .dc.l _txm_module_thread_shell_entry - __txm_module_preamble // Module Shell Entry Point + .dc.l demo_module_start - __txm_module_preamble // Module Start Thread Entry Point + .dc.l 0 // Module Stop Thread Entry Point + .dc.l 1 // Module Start/Stop Thread Priority + .dc.l 1024 // Module Start/Stop Thread Stack Size + .dc.l _txm_module_callback_request_thread_entry - __txm_module_preamble // Module Callback Thread Entry + .dc.l 1 // Module Callback Thread Priority + .dc.l 1024 // Module Callback Thread Stack Size + .dc.l 0x10000 // Module Code Size + .dc.l 0x10000 // Module Data Size + .dc.l 0 // Reserved 0 + .dc.l 0 // Reserved 1 + .dc.l 0 // Reserved 2 + .dc.l 0 // Reserved 3 + .dc.l 0 // Reserved 4 + .dc.l 0 // Reserved 5 + .dc.l 0 // Reserved 6 + .dc.l 0 // Reserved 7 + .dc.l 0 // Reserved 8 + .dc.l 0 // Reserved 9 + .dc.l 0 // Reserved 10 + .dc.l 0 // Reserved 11 + .dc.l 0 // Reserved 12 + .dc.l 0 // Reserved 13 + .dc.l 0 // Reserved 14 + .dc.l 0 // Reserved 15 diff --git a/ports_module/cortex-m4/ac6/example_build/sample_threadx_module_manager/.cproject b/ports_module/cortex-m4/ac6/example_build/sample_threadx_module_manager/.cproject new file mode 100644 index 00000000..1f055e15 --- /dev/null +++ b/ports_module/cortex-m4/ac6/example_build/sample_threadx_module_manager/.cproject @@ -0,0 +1,196 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_module/cortex-m4/ac6/example_build/sample_threadx_module_manager/.project b/ports_module/cortex-m4/ac6/example_build/sample_threadx_module_manager/.project new file mode 100644 index 00000000..bddfb9ee --- /dev/null +++ b/ports_module/cortex-m4/ac6/example_build/sample_threadx_module_manager/.project @@ -0,0 +1,29 @@ + + + sample_threadx_module_manager + + + sample_threadx_module + tx + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.arm.debug.ds.nature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/ports_module/cortex-m4/ac6/example_build/sample_threadx_module_manager/exceptions.c b/ports_module/cortex-m4/ac6/example_build/sample_threadx_module_manager/exceptions.c new file mode 100644 index 00000000..0cef25ce --- /dev/null +++ b/ports_module/cortex-m4/ac6/example_build/sample_threadx_module_manager/exceptions.c @@ -0,0 +1,93 @@ +/* +** Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. +** Use, modification and redistribution of this file is subject to your possession of a +** valid End User License Agreement for the Arm Product of which these examples are part of +** and your compliance with all applicable terms and conditions of such licence agreement. +*/ + +/* This file contains the default exception handlers and vector table. +All exceptions are handled in Handler mode. Processor state is automatically +pushed onto the stack when an exception occurs, and popped from the stack at +the end of the handler */ + + +/* Exception Handlers */ +/* Marking as __attribute__((interrupt)) avoids them being accidentally called from elsewhere */ + +__attribute__((interrupt)) void NMIException(void) +{ while(1); } + +__attribute__((interrupt)) void HardFaultException(void) +{ while(1); } + +void MemManage_Handler(void); + +void BusFault_Handler(void); + +void UsageFault_Handler(void); + +void __tx_SVCallHandler(void); + +__attribute__((interrupt)) void DebugMonitor(void) +{ while(1); } + +void __tx_PendSVHandler(void); + +void __tx_SysTickHandler(void); + +__attribute__((interrupt)) void InterruptHandler(void) +{ while(1); } + + +/* typedef for the function pointers in the vector table */ +typedef void(* const ExecFuncPtr)(void) __attribute__((interrupt)); + +/* Linker-generated Stack Base address */ +#ifdef TWO_REGION +extern unsigned int Image$$ARM_LIB_STACK$$ZI$$Limit; /* for Two Region model */ +#else +extern unsigned int Image$$ARM_LIB_STACKHEAP$$ZI$$Limit; /* for (default) One Region model */ +#endif + +/* Entry point for C run-time initialization */ +extern int __main(void); + + +/* Vector table +Create a named ELF section for the vector table that can be placed in a scatter file. +The first two entries are: + Initial SP = |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit| for (default) One Region model + or |Image$$ARM_LIB_STACK$$ZI$$Limit| for Two Region model + Initial PC= &__main (with LSB set to indicate Thumb) +*/ + +ExecFuncPtr vector_table[] __attribute__((section("vectors"))) = { + /* Configure Initial Stack Pointer using linker-generated symbol */ +#ifdef TWO_REGION + #pragma import(__use_two_region_memory) + (ExecFuncPtr)&Image$$ARM_LIB_STACK$$ZI$$Limit, +#else /* (default) One Region model */ + (ExecFuncPtr)&Image$$ARM_LIB_STACKHEAP$$ZI$$Limit, +#endif + (ExecFuncPtr)__main, /* Initial PC, set to entry point */ + NMIException, + HardFaultException, + MemManage_Handler, + BusFault_Handler, + UsageFault_Handler, + 0, 0, 0, 0, /* Reserved */ + __tx_SVCallHandler, + DebugMonitor, + 0, /* Reserved */ + __tx_PendSVHandler, + __tx_SysTickHandler, + + /* Add up to 240 interrupt handlers, starting here... */ + InterruptHandler, + InterruptHandler, /* Some dummy interrupt handlers */ + InterruptHandler + /* + : + */ +}; + diff --git a/ports_module/cortex-m4/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat b/ports_module/cortex-m4/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat new file mode 100644 index 00000000..eb8e0c23 --- /dev/null +++ b/ports_module/cortex-m4/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat @@ -0,0 +1,44 @@ +;******************************************************* +; Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. +; Use, modification and redistribution of this file is subject to your possession of a +; valid End User License Agreement for the Arm Product of which these examples are part of +; and your compliance with all applicable terms and conditions of such licence agreement. +;******************************************************* + +; Scatter-file for Cortex-M4 bare-metal example + +; This scatter-file places the vector table, application code, data, stacks and heap at suitable addresses in the memory map. + +; The vector table is placed first at the start of the image. +; Code starts after the last entry in the vector table. +; Data is placed at an address that must correspond to RAM. +; Stack and Heap are placed using ARM_LIB_STACKHEAP, to eliminate the need to set stack-base or heap-base in the debugger. +; System Control Space registers appear at their architecturally-defined addresses, based at 0xE000E000. + + +LOAD_REGION 0x00000000 +{ + VECTORS +0 0xC0 ; 16 exceptions + up to 32 interrupts, 4 bytes each entry == 0xC0 + { + exceptions.o (vectors, +FIRST) ; from exceptions.c + } + + ; Code is placed immediately (+0) after the previous root region + ; (so code region will also be a root region) + CODE +0 + { + * (+RO) ; All program code, including library code + } + + DATA +0 + { + * (+RW, +ZI) ; All RW and ZI data + } + + ; Heap grows upwards from start of this region and + ; Stack grows downwards from end of this region + ; The Main Stack Pointer is initialized on reset to the top addresses of this region + ARM_LIB_STACKHEAP +0 EMPTY 0x1000 + { + } +} diff --git a/ports_module/cortex-m4/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c b/ports_module/cortex-m4/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c new file mode 100644 index 00000000..210f0be0 --- /dev/null +++ b/ports_module/cortex-m4/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c @@ -0,0 +1,126 @@ +/* Small demonstration of the ThreadX module manager. */ + +#include "tx_api.h" +#include "txm_module.h" + + +#define DEMO_STACK_SIZE 1024 + +/* Define the ThreadX object control blocks... */ + +TX_THREAD module_manager; +TXM_MODULE_INSTANCE my_module; + + +/* Define the object pool area. */ + +UCHAR object_memory[16384]; + + +/* Define the module data pool area. */ + +#define MODULE_DATA_SIZE (256 * 1024) +#define MODULE_DATA (0x40000) + + +/* The module code should be loaded here. */ + +#define MODULE_CODE (0x30000) + + +/* Define the external memory area. */ + +#define EXTERNAL_MEMORY_SIZE (64 * 1024) +#define EXTERNAL_MEMORY (0x80000) + + +/* Define the count of memory faults. */ + +ULONG memory_faults; + + +/* Define thread prototypes. */ + +void module_manager_entry(ULONG thread_input); + + +/* Define fault handler. */ + +VOID module_fault_handler(TX_THREAD *thread, TXM_MODULE_INSTANCE *module) +{ + + /* Just increment the fault counter. */ + memory_faults++; +} + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = (CHAR*)first_unused_memory; + + + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + pointer = pointer + DEMO_STACK_SIZE; +} + + + + +/* Define the test threads. */ + +void module_manager_entry(ULONG thread_input) +{ + + /* Initialize the module manager. */ + txm_module_manager_initialize((void *) MODULE_DATA, MODULE_DATA_SIZE); + + txm_module_manager_object_pool_create(object_memory, sizeof(object_memory)); + + /* Register a fault handler. */ + txm_module_manager_memory_fault_notify(module_fault_handler); + + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ + txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE); + + /* Enable a read/write shared memory region. */ + txm_module_manager_external_memory_enable(&my_module, (void *) EXTERNAL_MEMORY, EXTERNAL_MEMORY_SIZE, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); + + /* Start the module. */ + txm_module_manager_start(&my_module); + + /* Sleep for a while.... */ + tx_thread_sleep(1000); + + /* Stop the module. */ + txm_module_manager_stop(&my_module); + + /* Unload the module. */ + txm_module_manager_unload(&my_module); + + /* Load the module that is already there. */ + txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE); + + /* Start the module again. */ + txm_module_manager_start(&my_module); + + /* Now just spin... */ + while(1) + { + + tx_thread_sleep(100); + } +} diff --git a/ports_module/cortex-m4/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.ds b/ports_module/cortex-m4/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.ds new file mode 100644 index 00000000..b1993316 --- /dev/null +++ b/ports_module/cortex-m4/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.ds @@ -0,0 +1,3 @@ +wait +load ..\sample_threadx_module\Debug\sample_threadx_module.axf +wait diff --git a/ports_module/cortex-m4/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.launch b/ports_module/cortex-m4/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.launch new file mode 100644 index 00000000..56780d71 --- /dev/null +++ b/ports_module/cortex-m4/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.launch @@ -0,0 +1,227 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_module/cortex-m4/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager_debug.ds b/ports_module/cortex-m4/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager_debug.ds new file mode 100644 index 00000000..fc83a4f2 --- /dev/null +++ b/ports_module/cortex-m4/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager_debug.ds @@ -0,0 +1,3 @@ +wait +add-symbol-file ..\sample_threadx_module\Debug\sample_threadx_module.axf +wait diff --git a/ports_module/cortex-m4/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S b/ports_module/cortex-m4/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S new file mode 100644 index 00000000..5dda196d --- /dev/null +++ b/ports_module/cortex-m4/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S @@ -0,0 +1,231 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global _tx_timer_interrupt + .global __main + .global __tx_NMIHandler // NMI + .global __tx_BadHandler // HardFault + .global __tx_SVCallHandler // SVCall + .global __tx_DBGHandler // Monitor + .global __tx_PendSVHandler // PendSV + .global __tx_SysTickHandler // SysTick + .global __tx_IntHandler // Int 0 + + +SYSTEM_CLOCK = 6000000 +SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) + + + .text 32 + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-M4/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_initialize_low_level(VOID) +// { + .global _tx_initialize_low_level + .thumb_func +_tx_initialize_low_level: + + /* Disable interrupts during ThreadX initialization. */ + + CPSID i + + /* Set base of available memory to end of non-initialised RAM area. */ + + LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer + LDR r1, =Image$$ARM_LIB_STACKHEAP$$ZI$$Limit // Build first free address + ADD r1, r1, #4 // + STR r1, [r0] // Setup first unused memory pointer + + /* Setup Vector Table Offset Register. */ + + MOV r0, #0xE000E000 // Build address of NVIC registers + LDR r1, =vector_table // Pickup address of vector table + STR r1, [r0, #0xD08] // Set vector table address + + /* Set system stack pointer from vector value. */ + + LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer + LDR r1, =vector_table // Pickup address of vector table + LDR r1, [r1] // Pickup reset stack pointer + STR r1, [r0] // Save system stack pointer + + /* Enable the cycle count register. */ + + LDR r0, =0xE0001000 // Build address of DWT register + LDR r1, [r0] // Pickup the current value + ORR r1, r1, #1 // Set the CYCCNTENA bit + STR r1, [r0] // Enable the cycle count register + + /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ + + MOV r0, #0xE000E000 // Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] // Setup SysTick Reload Value + MOV r1, #0x7 // Build SysTick Control Enable Value + STR r1, [r0, #0x10] // Setup SysTick Control + + /* Configure handler priorities. */ + + LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] // Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] // Setup System Handlers 8-11 Priority Registers + // Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] // Setup System Handlers 12-15 Priority Registers + // Note: PnSV must be lowest priority, which is 0xFF + + /* Return to caller. */ + + BX lr +// } + + +/* Define shells for each of the unused vectors. */ + + .global __tx_BadHandler + .thumb_func +__tx_BadHandler: + B __tx_BadHandler + +/* added to catch the hardfault */ + + .global __tx_HardfaultHandler + .thumb_func +__tx_HardfaultHandler: + B __tx_HardfaultHandler + +/* Generic interrupt handler template */ + .global __tx_IntHandler + .thumb_func +__tx_IntHandler: +// VOID InterruptHandler (VOID) +// { + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter // Call the ISR enter function +#endif + + /* Do interrupt handler work here */ + /* BL .... */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit // Call the ISR exit function +#endif + POP {r0, lr} + BX LR +// } + +/* System Tick timer interrupt handler */ + .global __tx_SysTickHandler + .global SysTick_Handler + .thumb_func +__tx_SysTickHandler: + .thumb_func +SysTick_Handler: +// VOID TimerInterruptHandler (VOID) +// { + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter // Call the ISR enter function +#endif + BL _tx_timer_interrupt +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit // Call the ISR exit function +#endif + POP {r0, lr} + BX LR +// } + + +/* NMI, DBG handlers */ + .global __tx_NMIHandler + .thumb_func +__tx_NMIHandler: + B __tx_NMIHandler + + .global __tx_DBGHandler + .thumb_func +__tx_DBGHandler: + B __tx_DBGHandler + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +/* Execution change notify functions */ + .global _tx_execution_isr_enter + .thumb_func +_tx_execution_isr_enter: + BX LR +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +/* Execution change notify functions */ + .global _tx_execution_isr_exit + .thumb_func +_tx_execution_isr_exit: + BX LR +#endif diff --git a/ports_module/cortex-m4/ac6/example_build/setenv.bat b/ports_module/cortex-m4/ac6/example_build/setenv.bat new file mode 100644 index 00000000..27fecdfc --- /dev/null +++ b/ports_module/cortex-m4/ac6/example_build/setenv.bat @@ -0,0 +1,16 @@ +@ECHO OFF + +SET ARMDSDIR="C:\Program Files\Arm\Development Studio 2020.0" +IF EXIST %ARMDSDIR% GOTO FOUND_ARMDS +ECHO ARM Development Studio not found. +EXIT /B 1 + +:FOUND_ARMDS +SET ARMDSIDEC=%ARMDSDIR%\bin\armds_idec.exe +IF EXIST %ARMDSIDEC% GOTO FOUND_ARMDS_IDEC +ECHO armds_idec.exe not found. +EXIT /B 1 + +:FOUND_ARMDS_IDEC +ECHO armds_idec.exe found at %ARMDSIDEC% +EXIT /B 0 diff --git a/ports_module/cortex-m4/ac6/example_build/tx/.cproject b/ports_module/cortex-m4/ac6/example_build/tx/.cproject new file mode 100644 index 00000000..945d3c88 --- /dev/null +++ b/ports_module/cortex-m4/ac6/example_build/tx/.cproject @@ -0,0 +1,162 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_module/cortex-m4/ac6/example_build/tx/.project b/ports_module/cortex-m4/ac6/example_build/tx/.project new file mode 100644 index 00000000..207f353b --- /dev/null +++ b/ports_module/cortex-m4/ac6/example_build/tx/.project @@ -0,0 +1,63 @@ + + + tx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + inc_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/inc + + + inc_generic_module_manager + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common_modules/module_manager/inc + + + inc_generic_modules + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common_modules/inc + + + inc_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/inc + + + src_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/src + + + src_generic_module_manager + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common_modules/module_manager/src + + + src_port_module_manager + 2 + $%7BPARENT-2-PROJECT_LOC%7D/module_manager/src + + + diff --git a/ports_module/cortex-m4/ac6/example_build/txm/.cproject b/ports_module/cortex-m4/ac6/example_build/txm/.cproject new file mode 100644 index 00000000..2ba3d353 --- /dev/null +++ b/ports_module/cortex-m4/ac6/example_build/txm/.cproject @@ -0,0 +1,184 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_module/cortex-m4/ac6/example_build/txm/.project b/ports_module/cortex-m4/ac6/example_build/txm/.project new file mode 100644 index 00000000..8b510516 --- /dev/null +++ b/ports_module/cortex-m4/ac6/example_build/txm/.project @@ -0,0 +1,58 @@ + + + txm + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + inc_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/inc + + + inc_generic_module_manager + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common_modules/module_manager/inc + + + inc_generic_modules + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common_modules/inc + + + inc_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/inc + + + src_generic_module_lib + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common_modules/module_lib/src + + + src_port_module_lib + 2 + $%7BPARENT-2-PROJECT_LOC%7D/module_lib/src + + + diff --git a/ports_module/cortex-m4/ac6/inc/tx_port.h b/ports_module/cortex-m4/ac6/inc/tx_port.h new file mode 100644 index 00000000..38d00353 --- /dev/null +++ b/ports_module/cortex-m4/ac6/inc/tx_port.h @@ -0,0 +1,516 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-M4/AC6 */ +/* 6.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX Cortex-M4 port. */ + +#define TX_INT_DISABLE 1 /* Disable interrupts */ +#define TX_INT_ENABLE 0 /* Enable interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0 + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); + +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) + +#ifdef TX_ENABLE_FPU_SUPPORT + + +#ifdef TX_MISRA_ENABLE + +ULONG _tx_misra_control_get(void); +void _tx_misra_control_set(ULONG value); +ULONG _tx_misra_fpccr_get(void); +void _tx_misra_vfp_touch(void); + +#else + +__attribute__( ( always_inline ) ) static inline ULONG __get_control(void) +{ + +ULONG control_value; + + __asm__ volatile (" MRS %0,CONTROL ": "=r" (control_value) ); + return(control_value); +} + + +__attribute__( ( always_inline ) ) static inline void __set_control(ULONG control_value) +{ + + __asm__ volatile (" MSR CONTROL,%0": : "r" (control_value): "memory" ); +} + + +#endif + + +/* A completed thread falls into _thread_shell_entry and we can simply deactivate the FPU via CONTROL.FPCA + in order to ensure no lazy stacking will occur. */ + +#ifndef TX_MISRA_ENABLE + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_control(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_control(_tx_vfp_state); \ + } +#else + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } + +#endif + + +/* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. + If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + the lazy FPU save, then restore the CONTROL.FPCA state. */ + +#ifndef TX_MISRA_ENABLE + + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_control(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_control(_tx_vfp_state); \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = *((ULONG *) 0xE000EF34); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_control(); \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + __asm__ volatile ("vmov.f32 s0, s0"); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = __get_control(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_control(_tx_vfp_state); \ + } \ + } \ + } \ + } +#else + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = _tx_misra_fpccr_get(); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + _tx_misra_vfp_touch(); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + } \ + } \ + } +#endif + +#else + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + +#endif + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define the get system state macro. */ + +#ifndef TX_THREAD_GET_SYSTEM_STATE +#ifndef TX_MISRA_ENABLE + +__attribute__( ( always_inline ) ) static inline unsigned int __get_ipsr_value(void) +{ + +unsigned int ipsr_value; + + __asm__ volatile (" MRS %0,IPSR ": "=r" (ipsr_value) ); + return(ipsr_value); +} + + +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | __get_ipsr_value()) +#else +ULONG _tx_misra_ipsr_get(VOID); +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get()) +#endif +#endif + + +/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value + indicates that _tx_thread_system_return should not be called. */ + +#ifndef TX_THREAD_SYSTEM_RETURN_CHECK +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#endif + +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to + prevent early scheduling on Cortex-M parts. */ + +#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; + + +/* This ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + +#endif + + +#ifndef TX_DISABLE_INLINE + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + + +__attribute__( ( always_inline ) ) static inline unsigned int __disable_interrupts(void) +{ + +unsigned int primask_value; + + __asm__ volatile (" MRS %0,PRIMASK ": "=r" (primask_value) ); + __asm__ volatile (" CPSID i" : : : "memory" ); + return(primask_value); +} + +__attribute__( ( always_inline ) ) static inline void __restore_interrupts(unsigned int primask_value) +{ + + __asm__ volatile (" MSR PRIMASK,%0": : "r" (primask_value): "memory" ); +} + +__attribute__( ( always_inline ) ) static inline unsigned int __get_primask_value(void) +{ + +unsigned int primask_value; + + __asm__ volatile (" MRS %0,PRIMASK ": "=r" (primask_value) ); + return(primask_value); +} + +__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void) +{ + + __asm__ volatile (" CPSIE i": : : "memory" ); +} + + +__attribute__( ( always_inline ) ) static inline void _tx_thread_system_return_inline(void) +{ +unsigned int interrupt_save; + + *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + if (__get_ipsr_value() == 0) + { + interrupt_save = __get_primask_value(); + __enable_interrupts(); + __restore_interrupts(interrupt_save); + } +} + + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = __disable_interrupts(); +#define TX_RESTORE __restore_interrupts(interrupt_save); + + +/* Redefine _tx_thread_system_return for improved performance. */ + +#define _tx_thread_system_return _tx_thread_system_return_inline + + +#else + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); +#define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); +#endif + + +/* Define FPU extension for the Cortex-M4. Each is assumed to be called in the context of the executing + thread. These are no longer needed, but are preserved for backward compatibility only. */ + +void tx_thread_fpu_enable(void); +void tx_thread_fpu_disable(void); + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/AC6 Version 6.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif diff --git a/ports_module/cortex-m4/ac6/inc/txm_module_port.h b/ports_module/cortex-m4/ac6/inc/txm_module_port.h new file mode 100644 index 00000000..26b99ba7 --- /dev/null +++ b/ports_module/cortex-m4/ac6/inc/txm_module_port.h @@ -0,0 +1,345 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* txm_module_port.h Cortex-M4/MPU/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the basic module constants, interface structures, */ +/* and function prototypes. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Andres Mlinar Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TXM_MODULE_PORT_H +#define TXM_MODULE_PORT_H + +/* Determine if the optional Modules user define file should be used. */ + +#ifdef TXM_MODULE_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in txm_module_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "txm_module_user.h" +#endif + +/* It is assumed that the base ThreadX tx_port.h file has been modified to add the + following extensions to the ThreadX thread control block (this code should replace + the corresponding macro define in tx_port.h): + +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; + +The following extensions must also be defined in tx_port.h: + +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); + +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); +*/ + +/* Define the kernel stack size for a module thread. */ +#ifndef TXM_MODULE_KERNEL_STACK_SIZE +#define TXM_MODULE_KERNEL_STACK_SIZE 768 +#endif + +/* For the following 3 access control settings, change TEX and C, B, S (bits 21 through 16 of MPU_RASR) + * to reflect your system memory attributes (cache, shareable, memory type). */ +/* Code region access control: privileged read-only, outer & inner write-back, normal memory, shareable. */ +#define TXM_MODULE_MPU_CODE_ACCESS_CONTROL 0x06070000 +/* Data region access control: execute never, read/write, outer & inner write-back, normal memory, shareable. */ +#define TXM_MODULE_MPU_DATA_ACCESS_CONTROL 0x13070000 +/* Shared region access control: execute never, read-only, outer & inner write-back, normal memory, shareable. */ +#define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 + + +/* Define constants specific to the tools the module can be built with for this particular modules port. */ + +#define TXM_MODULE_IAR_COMPILER 0x00000000 +#define TXM_MODULE_RVDS_COMPILER 0x01000000 +#define TXM_MODULE_GNU_COMPILER 0x02000000 +#define TXM_MODULE_COMPILER_MASK 0xFF000000 +#define TXM_MODULE_OPTIONS_MASK 0x000000FF + + +/* Define the properties for this particular module port. */ + +#define TXM_MODULE_MEMORY_PROTECTION_ENABLED + +#ifdef TXM_MODULE_MEMORY_PROTECTION_ENABLED +#define TXM_MODULE_REQUIRE_ALLOCATED_OBJECT_MEMORY +#else +#define TXM_MODULE_REQUIRE_LOCAL_OBJECT_MEMORY +#endif + +#define TXM_MODULE_USER_MODE 0x00000001 +#define TXM_MODULE_MEMORY_PROTECTION 0x00000002 +#define TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS 0x00000004 + + +/* Define the supported options for this module. */ + +#define TXM_MODULE_MANAGER_SUPPORTED_OPTIONS (TXM_MODULE_USER_MODE | TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS) +#define TXM_MODULE_MANAGER_REQUIRED_OPTIONS 0 + + +/* Define offset adjustments according to the compiler used to build the module. */ + +#define TXM_MODULE_IAR_SHELL_ADJUST 24 +#define TXM_MODULE_IAR_START_ADJUST 28 +#define TXM_MODULE_IAR_STOP_ADJUST 32 +#define TXM_MODULE_IAR_CALLBACK_ADJUST 44 + +#define TXM_MODULE_RVDS_SHELL_ADJUST 0 +#define TXM_MODULE_RVDS_START_ADJUST 0 +#define TXM_MODULE_RVDS_STOP_ADJUST 0 +#define TXM_MODULE_RVDS_CALLBACK_ADJUST 0 + +#define TXM_MODULE_GNU_SHELL_ADJUST 24 +#define TXM_MODULE_GNU_START_ADJUST 28 +#define TXM_MODULE_GNU_STOP_ADJUST 32 +#define TXM_MODULE_GNU_CALLBACK_ADJUST 44 + + +/* Define other module port-specific constants. */ + +/* Define INLINE_DECLARE to inline for ARM compiler. */ + +#define INLINE_DECLARE inline + +/* Define the number of MPU entries assigned to the code and data sections. On Cortex-M parts, there can only be 7 total + entries, since ThreadX uses one for access to the kernel dispatch function. */ + +#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 +#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 +#define TXM_MODULE_MANAGER_SHARED_MPU_INDEX 8 +#define TXM_MODULE_MANAGER_SHARED_MPU_REGION 4 + +/* Shared memory region attributes. */ +#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 +#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 + +/* Define the port-extensions to the module manager instance structure. */ + +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + ULONG txm_module_instance_mpu_registers[16]; \ + ULONG txm_module_instance_shared_memory_address; \ + ULONG txm_module_instance_shared_memory_length; + + +/* Define the memory fault information structure that is populated when a memory fault occurs. */ + + +typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT +{ + TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr; + VOID *txm_module_manager_memory_fault_info_code_location; + ULONG txm_module_manager_memory_fault_info_shcsr; + ULONG txm_module_manager_memory_fault_info_cfsr; + ULONG txm_module_manager_memory_fault_info_mmfar; + ULONG txm_module_manager_memory_fault_info_bfar; + ULONG txm_module_manager_memory_fault_info_control; + ULONG txm_module_manager_memory_fault_info_sp; + ULONG txm_module_manager_memory_fault_info_r0; + ULONG txm_module_manager_memory_fault_info_r1; + ULONG txm_module_manager_memory_fault_info_r2; + ULONG txm_module_manager_memory_fault_info_r3; + ULONG txm_module_manager_memory_fault_info_r4; + ULONG txm_module_manager_memory_fault_info_r5; + ULONG txm_module_manager_memory_fault_info_r6; + ULONG txm_module_manager_memory_fault_info_r7; + ULONG txm_module_manager_memory_fault_info_r8; + ULONG txm_module_manager_memory_fault_info_r9; + ULONG txm_module_manager_memory_fault_info_r10; + ULONG txm_module_manager_memory_fault_info_r11; + ULONG txm_module_manager_memory_fault_info_r12; + ULONG txm_module_manager_memory_fault_info_lr; + ULONG txm_module_manager_memory_fault_info_xpsr; +} TXM_MODULE_MANAGER_MEMORY_FAULT_INFO; + + +#define TXM_MODULE_MANAGER_FAULT_INFO \ + TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info; + +/* Define the macro to check the stack available in dispatch. */ +#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE \ + ULONG stack_available; \ + __asm("MOV %0, SP" : "=r"(stack_available)); \ + stack_available -= (ULONG)_tx_thread_current_ptr->tx_thread_stack_start; \ + if((stack_available < TXM_MODULE_MINIMUM_STACK_AVAILABLE) || \ + (stack_available > _tx_thread_current_ptr->tx_thread_stack_size)) \ + { \ + return(TX_SIZE_ERROR); \ + } + + +/* Define the macro to check the code alignment. */ + +#define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment) \ + { \ + ULONG temp; \ + temp = (ULONG) module_location; \ + temp = temp & (code_alignment - 1); \ + if (temp) \ + { \ + _tx_mutex_put(&_txm_module_manager_mutex); \ + return(TXM_MODULE_ALIGNMENT_ERROR); \ + } \ + } + + +/* Define the macro to adjust the alignment and size for code/data areas. */ + +#define TXM_MODULE_MANAGER_ALIGNMENT_ADJUST(module_preamble, code_size, code_alignment, data_size, data_alignment) _txm_module_manager_alignment_adjust(module_preamble, &code_size, &code_alignment, &data_size, &data_alignment); + + +/* Define the macro to adjust the symbols in the module preamble. */ + +#define TXM_MODULE_MANAGER_CALCULATE_ADJUSTMENTS(properties, shell_function_adjust, start_function_adjust, stop_function_adjust, callback_function_adjust) \ + if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_IAR_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_IAR_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_IAR_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_IAR_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_IAR_CALLBACK_ADJUST; \ + } \ + else if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_RVDS_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_RVDS_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_RVDS_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_RVDS_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_RVDS_CALLBACK_ADJUST; \ + } \ + else \ + { \ + shell_function_adjust = TXM_MODULE_GNU_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_GNU_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_GNU_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_GNU_CALLBACK_ADJUST; \ + } + + +/* Define the macro to populate the thread control block with module port-specific information. + Check if the module is in user mode and set up txm_module_thread_entry_info_kernel_call_dispatcher accordingly. +*/ + +#define TXM_MODULE_MANAGER_THREAD_SETUP(thread_ptr, module_instance) \ + thread_ptr -> tx_thread_module_current_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \ + thread_ptr -> tx_thread_module_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \ + if (thread_ptr -> tx_thread_module_user_mode) \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_user_mode_entry; \ + } \ + else \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_kernel_dispatch; \ + } + + +/* Define the macro to populate the module control block with module port-specific information. + If memory protection is enabled, set up the MPU registers. +*/ +#define TXM_MODULE_MANAGER_MODULE_SETUP(module_instance) \ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE) \ + { \ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) \ + { \ + _txm_module_manager_mm_register_setup(module_instance); \ + } \ + } \ + else \ + { \ + /* Do nothing. */ \ + } + +/* Define the macro to perform port-specific functions when unloading the module. */ +/* Nothing needs to be done for this port. */ +#define TXM_MODULE_MANAGER_MODULE_UNLOAD(module_instance) + + +/* Define the macros to perform port-specific checks when passing pointers to the kernel. */ + +/* Define macro to make sure object is inside the module's data. */ +#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ + /* Check if it's inside module data. */ \ + ((((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && \ + (((obj_ptr) + (obj_size)) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) || \ + /* Check if it's inside shared memory. */ \ + (((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address) && \ + (((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (module_instance -> txm_module_instance_shared_memory_address + module_instance -> txm_module_instance_shared_memory_length)))) + + +/* Define some internal prototypes to this module port. */ + +#ifndef TX_SOURCE_CODE +#define txm_module_manager_memory_fault_notify _txm_module_manager_memory_fault_notify +#endif + + +#define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES \ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment); \ +VOID _txm_module_manager_memory_fault_handler(VOID); \ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)); \ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \ +ULONG _txm_power_of_two_block_size(ULONG size); \ +ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); \ +ULONG _txm_module_manager_region_size_get(ULONG block_size); + +#define TXM_MODULE_MANAGER_VERSION_ID \ +CHAR _txm_module_manager_version_id[] = \ + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/MPU/AC6 Version 6.1 *"; + +#endif diff --git a/ports_module/cortex-m4/ac6/module_lib/src/txm_module_initialize.S b/ports_module/cortex-m4/ac6/module_lib/src/txm_module_initialize.S new file mode 100644 index 00000000..455e86b5 --- /dev/null +++ b/ports_module/cortex-m4/ac6/module_lib/src/txm_module_initialize.S @@ -0,0 +1,104 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .global __use_two_region_memory + .global __scatterload + + + .eabi_attribute Tag_ABI_PCS_RO_data, 1 + .eabi_attribute Tag_ABI_PCS_R9_use, 1 + .eabi_attribute Tag_ABI_PCS_RW_data, 2 + + .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_initialize Cortex-M4/MPU/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes the module c runtime. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __scatterload Initialize C runtime */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_thread_shell_entry Start module thread */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Andres Mlinar Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _txm_module_initialize(VOID) + .global _txm_module_initialize + .thumb_func +_txm_module_initialize: + PUSH {r4-r12,lr} // Save dregs and LR + //B __scatterload // Call ARM func to initialize variables + +// Override the __rt_exit function. + .global __rt_exit + .thumb_func +__rt_exit: + POP {r4-r12,lr} // Restore dregs and LR + BX lr // Return to caller + +#define TXM_MODULE_HEAP_SIZE 512 + +// returns heap start address in R0 +// returns heap end address in R2 +// does not touch SP, it is already set up before the module runs + .global __user_setup_stackheap + .thumb_func +__user_setup_stackheap: + LDR r1, _txm_heap // load heap offset + MOV r2, TXM_MODULE_HEAP_SIZE // load heap size + ADD r2, r2, r0 // calculate heap end address + BX lr + +// dummy main function + .global main + .thumb_func +main: + BX lr + + .align 8 +_txm_heap: + .zero TXM_MODULE_HEAP_SIZE diff --git a/ports_module/cortex-m4/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex-m4/ac6/module_lib/src/txm_module_thread_shell_entry.c new file mode 100644 index 00000000..0f99ad4a --- /dev/null +++ b/ports_module/cortex-m4/ac6/module_lib/src/txm_module_thread_shell_entry.c @@ -0,0 +1,172 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#ifndef TXM_MODULE +#define TXM_MODULE +#endif + +#ifndef TX_SOURCE_CODE +#define TX_SOURCE_CODE +#endif + + +/* Include necessary system files. */ + +#include "txm_module.h" +#include "tx_thread.h" + +/* Define the global module entry pointer from the start thread of the module. */ + +TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; + + +/* Define the dispatch function pointer used in the module implementation. */ + +ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3); + + +/* Define the ARM cstartup code. */ +extern VOID _txm_module_initialize(VOID); + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_thread_shell_entry Cortex-M4/MPU/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calls the specified entry function of the thread. It */ +/* also provides a place for the thread's entry function to return. */ +/* If the thread returns, this function places the thread in a */ +/* "COMPLETED" state. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to current thread */ +/* thread_info Pointer to thread entry info */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_initialize cstartup initialization */ +/* thread_entry Thread's entry function */ +/* tx_thread_resume Resume the module callback thread */ +/* _txm_module_thread_system_suspend Module thread suspension routine */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) +{ + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + VOID (*entry_exit_notify)(TX_THREAD *, UINT); +#endif + + + /* Determine if this is the start thread. If so, we must prepare the module for + execution. If not, simply skip the C startup code. */ + if (thread_info -> txm_module_thread_entry_info_start_thread) + { + /* Initialize the ARM C environment. */ + _txm_module_initialize(); + + /* Save the entry info pointer, for later use. */ + _txm_module_entry_info = thread_info; + + /* Save the kernel function dispatch address. This is used to make all resident calls from + the module. */ + _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; + + /* Ensure that we have a valid pointer. */ + while (!_txm_module_kernel_call_dispatcher) + { + /* Loop here, if an error is present getting the dispatch function pointer! + An error here typically indicates the resident portion of _tx_thread_schedule + is not supporting the trap to obtain the function pointer. */ + } + + /* Resume the module's callback thread, already created in the manager. */ + _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); + } + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has been entered! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_ENTRY); + } +#endif + + /* Call current thread's entry function. */ + (thread_info -> txm_module_thread_entry_info_entry) (thread_info -> txm_module_thread_entry_info_parameter); + + /* Suspend thread with a "completed" state. */ + + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine again. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has exited! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_EXIT); + } +#endif + + /* Call actual thread suspension routine. */ + _txm_module_thread_system_suspend(thread_ptr); + +#ifdef TX_SAFETY_CRITICAL + + /* If we ever get here, raise safety critical exception. */ + TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0); +#endif +} + diff --git a/ports_module/cortex-m4/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex-m4/ac6/module_manager/src/tx_thread_context_restore.S new file mode 100644 index 00000000..f6b24290 --- /dev/null +++ b/ports_module/cortex-m4/ac6/module_manager/src/tx_thread_context_restore.S @@ -0,0 +1,76 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .text + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore Cortex-M4/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is only needed for legacy applications and it should */ +/* not be called in any new development on a Cortex-M. */ +/* This function restores the interrupt context if it is processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_context_restore(VOID) +// { + .global _tx_thread_context_restore + .thumb_func +_tx_thread_context_restore: + /* Not needed for this port - just return! */ + BX lr +// } diff --git a/ports_module/cortex-m4/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex-m4/ac6/module_manager/src/tx_thread_context_save.S new file mode 100644 index 00000000..b5f1d070 --- /dev/null +++ b/ports_module/cortex-m4/ac6/module_manager/src/tx_thread_context_save.S @@ -0,0 +1,75 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .text + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save Cortex-M4/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is only needed for legacy applications and it should */ +/* not be called in any new development on a Cortex-M. */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_context_save(VOID) +// { + .global _tx_thread_context_save + .thumb_func +_tx_thread_context_save: + /* Not needed for this port - just return! */ + BX lr +// } diff --git a/ports_module/cortex-m4/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex-m4/ac6/module_manager/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..d8bde055 --- /dev/null +++ b/ports_module/cortex-m4/ac6/module_manager/src/tx_thread_interrupt_control.S @@ -0,0 +1,80 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text 32 + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control Cortex-M4/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_interrupt_control(UINT new_posture) +// { + .global _tx_thread_interrupt_control + .thumb_func +_tx_thread_interrupt_control: + + // Pickup current interrupt lockout posture. + + MRS r1, PRIMASK // Pickup current interrupt lockout + + // Apply the new interrupt posture. + + MSR PRIMASK, r0 // Apply the new interrupt lockout + MOV r0, r1 // Transfer old to return register + BX lr // Return to caller + +// } diff --git a/ports_module/cortex-m4/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex-m4/ac6/module_manager/src/tx_thread_schedule.S new file mode 100644 index 00000000..0bf01024 --- /dev/null +++ b/ports_module/cortex-m4/ac6/module_manager/src/tx_thread_schedule.S @@ -0,0 +1,569 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .global _tx_thread_current_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_system_stack_ptr + .global _tx_thread_preempt_disable + .global _txm_module_manager_memory_fault_handler + .global _txm_module_manager_memory_fault_info +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + .global _tx_execution_thread_enter + .global _tx_execution_thread_exit +#endif + + .text + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule Cortex-M4/MPU/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* _tx_thread_context_restore Restore thread's context */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_schedule(VOID) +// { + .global _tx_thread_schedule + .thumb_func +_tx_thread_schedule: + + /* This function should only ever be called on Cortex-M + from the first schedule request. Subsequent scheduling occurs + from the PendSV handling routines below. */ + + /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ + + MOV r0, #0 // Build value for TX_FALSE + LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag + STR r0, [r2, #0] // Clear preempt disable flag + + /* Clear CONTROL.FPCA bit so FPU registers aren't unnecessarily stacked. */ + +#ifdef __ARMVFP__ + MRS r0, CONTROL // Pickup current CONTROL register + BIC r0, r0, #4 // Clear the FPCA bit + MSR CONTROL, r0 // Setup new CONTROL register +#endif + + /* Enable memory fault registers. */ + + LDR r0, =0xE000ED24 // Build SHCSR address + LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults + STR r1, [r0] // + + /* Enable interrupts */ + + CPSIE i + + /* Enter the scheduler for the first time. */ + + MOV r0, #0x10000000 // Load PENDSVSET bit + MOV r1, #0xE000E000 // Load NVIC base + STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + DSB // Complete all memory accesses + ISB // Flush pipeline + + /* Wait here for the PendSV to take place. */ + +__tx_wait_here: + B __tx_wait_here // Wait for the PendSV to happen +// } + + + /* Memory Exception Handler. */ + .global MemManage_Handler + .global BusFault_Handler + .global UsageFault_Handler + .thumb_func +MemManage_Handler: + .thumb_func +BusFault_Handler: + .thumb_func +UsageFault_Handler: + + CPSID i // Disable interrupts + + /* Now pickup and store all the fault related information. */ + + LDR r12,=_txm_module_manager_memory_fault_info // Pickup fault info struct + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r0] // Pickup the current thread pointer + STR r1, [r12, #0] // Save current thread pointer in fault info structure + LDR r0, =0xE000ED24 // Build SHCSR address + LDR r1, [r0] // Pickup SHCSR + STR r1, [r12, #8] // Save SHCSR + LDR r0, =0xE000ED28 // Build CFSR address + LDR r1, [r0] // Pickup CFSR + STR r1, [r12, #12] // Save CFSR + LDR r0, =0xE000ED34 // Build MMFAR address + LDR r1, [r0] // Pickup MMFAR + STR r1, [r12, #16] // Save MMFAR + LDR r0, =0xE000ED38 // Build BFAR address + LDR r1, [r0] // Pickup BFAR + STR r1, [r12, #20] // Save BFAR + MRS r0, CONTROL // Pickup current CONTROL register + STR r0, [r12, #24] // Save CONTROL + MRS r1, PSP // Pickup thread stack pointer + STR r1, [r12, #28] // Save thread stack pointer + LDR r0, [r1] // Pickup saved r0 + STR r0, [r12, #32] // Save r0 + LDR r0, [r1, #4] // Pickup saved r1 + STR r0, [r12, #36] // Save r1 + STR r2, [r12, #40] // Save r2 + STR r3, [r12, #44] // Save r3 + STR r4, [r12, #48] // Save r4 + STR r5, [r12, #52] // Save r5 + STR r6, [r12, #56] // Save r6 + STR r7, [r12, #60] // Save r7 + STR r8, [r12, #64] // Save r8 + STR r9, [r12, #68] // Save r9 + STR r10,[r12, #72] // Save r10 + STR r11,[r12, #76] // Save r11 + LDR r0, [r1, #16] // Pickup saved r12 + STR r0, [r12, #80] // Save r12 + LDR r0, [r1, #20] // Pickup saved lr + STR r0, [r12, #84] // Save lr + LDR r0, [r1, #24] // Pickup instruction address at point of fault + STR r0, [r12, #4] // Save point of fault + LDR r0, [r1, #28] // Pickup xPSR + STR r0, [r12, #88] // Save xPSR + + MRS r0, CONTROL // Pickup current CONTROL register + BIC r0, r0, #1 // Clear the UNPRIV bit + MSR CONTROL, r0 // Setup new CONTROL register + + LDR r0, =0xE000ED28 // Build the Memory Management Fault Status Register (MMFSR) + LDRB r1, [r0] // Pickup the MMFSR, with the following bit definitions: + // Bit 0 = 1 -> Instruction address violation + // Bit 1 = 1 -> Load/store address violation + // Bit 7 = 1 -> MMFAR is valid + STRB r1, [r0] // Clear the MMFSR + +#ifdef __ARMVFP__ + LDR r0, =0xE000EF34 // Cleanup FPU context: Load FPCCR address + LDR r1, [r0] // Load FPCCR + BIC r1, r1, #1 // Clear the lazy preservation active bit + STR r1, [r0] // Store the value +#endif + + BL _txm_module_manager_memory_fault_handler // Call memory manager fault handler + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread exit function to indicate the thread is no longer executing. */ + + CPSID i // Disable interrupts + BL _tx_execution_thread_exit // Call the thread exit function + CPSIE i // Enable interrupts +#endif + + MOV r1, #0 // Build NULL value + LDR r0, =_tx_thread_current_ptr // Pickup address of current thread pointer + STR r1, [r0] // Clear current thread pointer + + // Return from MemManage_Handler exception + LDR r0, =0xE000ED04 // Load ICSR + LDR r1, =0x10000000 // Set PENDSVSET bit + STR r1, [r0] // Store ICSR + DSB // Wait for memory access to complete + CPSIE i // Enable interrupts + MOV lr, #0xFFFFFFFD // Load exception return code + BX lr // Return from exception + + + /* Generic context PendSV handler. */ + + .global PendSV_Handler + .thumb_func +PendSV_Handler: + .global __tx_PendSVHandler + .thumb_func +__tx_PendSVHandler: + + /* Get current thread value and new thread pointer. */ + +__tx_ts_handler: + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread exit function to indicate the thread is no longer executing. */ + + CPSID i // Disable interrupts + PUSH {r0, lr} // Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit // Call the thread exit function + POP {r0, lr} // Recover LR + CPSIE i // Enable interrupts +#endif + + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address + MOV r3, #0 // Build NULL value + LDR r1, [r0] // Pickup current thread pointer + + /* Determine if there is a current thread to finish preserving. */ + + CBZ r1, __tx_ts_new // If NULL, skip preservation + + /* Recover PSP and preserve current thread context. */ + + STR r3, [r0] // Set _tx_thread_current_ptr to NULL + MRS r12, PSP // Pickup PSP pointer (thread's stack pointer) + STMDB r12!, {r4-r11} // Save its remaining registers +#ifdef __ARMVFP__ + TST LR, #0x10 // Determine if the VFP extended frame is present + BNE _skip_vfp_save + VSTMDB r12!,{s16-s31} // Yes, save additional VFP registers +_skip_vfp_save: +#endif + LDR r4, =_tx_timer_time_slice // Build address of time-slice variable + STMDB r12!, {LR} // Save LR on the stack + + /* Determine if time-slice is active. If it isn't, skip time handling processing. */ + + LDR r5, [r4] // Pickup current time-slice + STR r12, [r1, #8] // Save the thread stack pointer + CBZ r5, __tx_ts_new // If not active, skip processing + + /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ + + STR r5, [r1, #24] // Save current time-slice + + /* Clear the global time-slice. */ + + STR r3, [r4] // Clear time-slice + + /* Executing thread is now completely preserved!!! */ + +__tx_ts_new: + + /* Now we are looking for a new thread to execute! */ + + CPSID i // Disable interrupts + LDR r1, [r2] // Is there another thread ready to execute? + CBZ r1, __tx_ts_wait // No, skip to the wait processing + + /* Yes, another thread is ready for else, make the current thread the new thread. */ + + STR r1, [r0] // Setup the current thread pointer to the new thread + CPSIE i // Enable interrupts + + /* Increment the thread run count. */ + +__tx_ts_restore: + LDR r7, [r1, #4] // Pickup the current thread run count + LDR r4, =_tx_timer_time_slice // Build address of time-slice variable + LDR r5, [r1, #24] // Pickup thread's current time-slice + ADD r7, r7, #1 // Increment the thread run count + STR r7, [r1, #4] // Store the new run count + + /* Setup global time-slice with thread's current time-slice. */ + + STR r5, [r4] // Setup global time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread entry function to indicate the thread is executing. */ + + PUSH {r0, r1} // Save r0 and r1 + BL _tx_execution_thread_enter // Call the thread execution enter function + POP {r0, r1} // Recover r0 and r1 +#endif + + /* Restore the thread context and PSP. */ + + LDR r12, [r1, #8] // Pickup thread's stack pointer + + MRS r5, CONTROL // Pickup current CONTROL register + LDR r4, [r1, #0x98] // Pickup current user mode flag + BIC r5, r5, #1 // Clear the UNPRIV bit + ORR r4, r4, r5 // Build new CONTROL register + MSR CONTROL, r4 // Setup new CONTROL register + + LDR r0, =0xE000ED94 // Build MPU control reg address + MOV r3, #0 // Build disable value + STR r3, [r0] // Disable MPU + LDR r0, [r1, #0x90] // Pickup the module instance pointer + CBZ r0, skip_mpu_setup // Is this thread owned by a module? No, skip MPU setup + LDR r1, [r0, #0x64] // Pickup MPU register[0] + CBZ r1, skip_mpu_setup // Is protection required for this module? No, skip MPU setup + LDR r1, =0xE000ED9C // Build address of MPU base register + + // Use alias registers to quickly load MPU + ADD r0, r0, #100 // Build address of MPU register start in thread control block + LDM r0!,{r2-r9} // Load MPU regions 0-3 + STM r1,{r2-r9} // Store MPU regions 0-3 + LDM r0!,{r2-r9} // Load MPU regions 4-7 + STM r1,{r2-r9} // Store MPU regions 4-7 + LDR r0, =0xE000ED94 // Build MPU control reg address + MOV r1, #5 // Build enable value with background region enabled + STR r1, [r0] // Enable MPU +skip_mpu_setup: + LDMIA r12!, {LR} // Pickup LR +#ifdef __ARMVFP__ + TST LR, #0x10 // Determine if the VFP extended frame is present + BNE _skip_vfp_restore // If not, skip VFP restore + VLDMIA r12!, {s16-s31} // Yes, restore additional VFP registers +_skip_vfp_restore: +#endif + LDMIA r12!, {r4-r11} // Recover thread's registers + MSR PSP, r12 // Setup the thread's stack pointer + + /* Return to thread. */ + + BX lr // Return to thread! + + /* The following is the idle wait processing... in this case, no threads are ready for execution and the + system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts + are disabled to allow use of WFI for waiting for a thread to arrive. */ + +__tx_ts_wait: + CPSID i // Disable interrupts + LDR r1, [r2] // Pickup the next thread to execute pointer + STR r1, [r0] // Store it in the current pointer + CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! +#ifdef TX_ENABLE_WFI + DSB // Ensure no outstanding memory transactions + WFI // Wait for interrupt + ISB // Ensure pipeline is flushed +#endif + CPSIE i // Enable interrupts + B __tx_ts_wait // Loop to continue waiting + + /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are + already in the handler! */ + +__tx_ts_ready: + MOV r7, #0x08000000 // Build clear PendSV value + MOV r8, #0xE000E000 // Build base NVIC address + STR r7, [r8, #0xD04] // Clear any PendSV + + /* Re-enable interrupts and restore new thread. */ + + CPSIE i // Enable interrupts + B __tx_ts_restore // Restore the thread + + + /* SVC Handler. */ + + .global SVC_Handler + .thumb_func +SVC_Handler: + .global __tx_SVCallHandler + .thumb_func +__tx_SVCallHandler: + + MRS r0, PSP // Pickup the PSP stack + LDR r1, [r0, #24] // Pickup the point of interrupt + LDRB r2, [r1, #-2] // Pickup the SVC parameter + + /* Determine which SVC trap we are processing */ + + CMP r2, #1 // Is it the entry into ThreadX? + BNE _tx_thread_user_return // No, return to user mode + + /* At this point we have an SVC 1, which means we are entering + the kernel from a module thread with user mode selected. */ + + LDR r2, =_txm_module_priv // Load address of where we should have come from + CMP r1, r2 // Did we come from user_mode_entry? + IT NE // If no (not equal), then... + BXNE lr // return from where we came. + + LDR r3, [r0, #20] // This is the saved LR + LDR r1, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, [r1] // Pickup current thread pointer + MOV r1, #0 // Build clear value + STR r1, [r2, #0x98] // Clear the current user mode selection for thread + STR r3, [r2, #0xA0] // Save the original LR in thread control block + + /* If there is memory protection, use kernel stack */ + LDR r0, [r2, #0x90] // Load the module instance ptr + LDR r0, [r0, #0x0C] // Load the module property flags + TST r0, #2 // Check if memory protected + BEQ _tx_skip_kernel_stack_enter + + /* Switch to the module thread's kernel stack */ + LDR r0, [r2, #0xA8] // Load the module kernel stack end +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + LDR r1, [r2, #0xA4] // Load the module kernel stack start + LDR r3, [r2, #0xAC] // Load the module kernel stack size + STR r1, [r2, #12] // Set stack start + STR r0, [r2, #16] // Set stack end + STR r3, [r2, #20] // Set stack size +#endif + + MRS r3, PSP // Pickup thread stack pointer + STR r3, [r2, #0xB0] // Save thread stack pointer + + /* Build kernel stack by copying thread stack two registers at a time */ + ADD r3, r3, #32 // Start at bottom of hardware stack + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + + MSR PSP, r0 // Set kernel stack pointer + +_tx_skip_kernel_stack_enter: + MRS r0, CONTROL // Pickup current CONTROL register + BIC r0, r0, #1 // Clear the UNPRIV bit + MSR CONTROL, r0 // Setup new CONTROL register + BX lr // Return to thread + +_tx_thread_user_return: + LDR r2, =_txm_module_user_mode_exit // Load address of where we should have come from + CMP r1, r2 // Did we come from user_mode_exit? + IT NE // If no (not equal), then... + BXNE lr // return from where we came + + LDR r1, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, [r1] // Pickup current thread pointer + LDR r1, [r2, #0x9C] // Pick up user mode + STR r1, [r2, #0x98] // Set the current user mode selection for thread + + /* If there is memory protection, use kernel stack */ + LDR r0, [r2, #0x90] // Load the module instance ptr + LDR r0, [r0, #0x0C] // Load the module property flags + TST r0, #2 // Check if memory protected + BEQ _tx_skip_kernel_stack_exit + +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + LDR r0, [r2, #0xB4] // Load the module thread stack start + LDR r1, [r2, #0xB8] // Load the module thread stack end + LDR r3, [r2, #0xBC] // Load the module thread stack size + STR r0, [r2, #12] // Set stack start + STR r1, [r2, #16] // Set stack end + STR r3, [r2, #20] // Set stack size +#endif + LDR r0, [r2, #0xB0] // Load the module thread stack pointer + MRS r3, PSP // Pickup kernel stack pointer + + /* Copy kernel hardware stack to module thread stack. */ + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + SUB r0, r0, #32 // Subtract 32 to get back to top of stack + MSR PSP, r0 // Set thread stack pointer + + LDR r1, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, [r1] // Pickup current thread pointer + LDR r1, [r2, #0x9C] // Pick up user mode + +_tx_skip_kernel_stack_exit: + MRS r0, CONTROL // Pickup current CONTROL register + ORR r0, r0, r1 // OR in the user mode bit + MSR CONTROL, r0 // Setup new CONTROL register + BX lr // Return to thread + + + /* Kernel entry function from user mode. */ + + .global _txm_module_manager_kernel_dispatch + .align 5 + .syntax unified +// VOID _txm_module_manager_user_mode_entry(VOID) +// { + .global _txm_module_manager_user_mode_entry + .thumb_func +_txm_module_manager_user_mode_entry: + SVC 1 // Enter kernel +_txm_module_priv: + /* At this point, we are out of user mode. The original LR has been saved in the + thread control block. Simply call the kernel dispatch function. */ + BL _txm_module_manager_kernel_dispatch + + /* Pickup the original LR value while still in privileged mode */ + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r3, [r2] // Pickup current thread pointer + LDR lr, [r3, #0xA0] // Pickup saved LR from original call + + SVC 2 // Exit kernel and return to user mode +_txm_module_user_mode_exit: + BX lr // Return to the caller + NOP + NOP + NOP + NOP +// } + +#ifdef TX_ENABLE_FPU_SUPPORT + + .global tx_thread_fpu_enable + .thumb_func +tx_thread_fpu_enable: + /* Automatic VPF logic is supported, this function is present only for + backward compatibility purposes and therefore simply returns. */ + BX LR // Return to caller + + .global tx_thread_fpu_disable + .thumb_func +tx_thread_fpu_disable: + /* Automatic VPF logic is supported, this function is present only for + backward compatibility purposes and therefore simply returns. */ + BX LR // Return to caller +#endif + diff --git a/ports_module/cortex-m4/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex-m4/ac6/module_manager/src/tx_thread_stack_build.S new file mode 100644 index 00000000..1f006f32 --- /dev/null +++ b/ports_module/cortex-m4/ac6/module_manager/src/tx_thread_stack_build.S @@ -0,0 +1,135 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .text + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build Cortex-M4/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +// { + .global _tx_thread_stack_build + .thumb_func +_tx_thread_stack_build: + + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-M should look like the following after it is built: + + Stack Top: + LR Interrupted LR (LR at time of PENDSV) + r4 Initial value for r4 + r5 Initial value for r5 + r6 Initial value for r6 + r7 Initial value for r7 + r8 Initial value for r8 + r9 Initial value for r9 + r10 Initial value for r10 + r11 Initial value for r11 + r0 Initial value for r0 (Hardware stack starts here!!) + r1 Initial value for r1 + r2 Initial value for r2 + r3 Initial value for r3 + r12 Initial value for r12 + lr Initial value for lr + pc Initial value for pc + xPSR Initial value for xPSR + + Stack Bottom: (higher memory address) */ + + LDR r2, [r0, #16] // Pickup end of stack area + BIC r2, r2, #0x7 // Align frame + SUB r2, r2, #68 // Subtract frame size + LDR r3, =0xFFFFFFFD // Build initial LR value + STR r3, [r2, #0] // Save on the stack + + /* Actually build the stack frame. */ + + MOV r3, #0 // Build initial register value + STR r3, [r2, #4] // Store initial r4 + STR r3, [r2, #8] // Store initial r5 + STR r3, [r2, #12] // Store initial r6 + STR r3, [r2, #16] // Store initial r7 + STR r3, [r2, #20] // Store initial r8 + STR r3, [r2, #24] // Store initial r9 + STR r3, [r2, #28] // Store initial r10 + STR r3, [r2, #32] // Store initial r11 + + /* Hardware stack follows. */ + + STR r3, [r2, #36] // Store initial r0 + STR r3, [r2, #40] // Store initial r1 + STR r3, [r2, #44] // Store initial r2 + STR r3, [r2, #48] // Store initial r3 + STR r3, [r2, #52] // Store initial r12 + MOV r3, #0xFFFFFFFF // Poison EXC_RETURN value + STR r3, [r2, #56] // Store initial lr + STR r1, [r2, #60] // Store initial pc + MOV r3, #0x01000000 // Only T-bit need be set + STR r3, [r2, #64] // Store initial xPSR + + /* Setup stack pointer. */ + // thread_ptr -> tx_thread_stack_ptr = r2; + + STR r2, [r0, #8] // Save stack pointer in thread's + // control block + BX lr // Return to caller +// } diff --git a/ports_module/cortex-m4/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex-m4/ac6/module_manager/src/tx_thread_system_return.S new file mode 100644 index 00000000..48f8bfd6 --- /dev/null +++ b/ports_module/cortex-m4/ac6/module_manager/src/tx_thread_system_return.S @@ -0,0 +1,88 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .text 32 + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return Cortex-M4/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the ThreadX system. Only a */ +/* minimal context is saved since the compiler assumes temp registers */ +/* are going to get slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_system_return(VOID) +// { + .thumb_func + .global _tx_thread_system_return +_tx_thread_system_return: + + /* Return to real scheduler via PendSV. Note that this routine is often + replaced with in-line assembly in tx_port.h to improved performance. */ + + MOV r0, #0x10000000 // Load PENDSVSET bit + MOV r1, #0xE000E000 // Load NVIC base + STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + MRS r0, IPSR // Pickup IPSR + CMP r0, #0 // Is it a thread returning? + BNE _isr_context // If ISR, skip interrupt enable + MRS r1, PRIMASK // Thread context returning, pickup PRIMASK + CPSIE i // Enable interrupts + MSR PRIMASK, r1 // Restore original interrupt posture +_isr_context: + BX lr // Return to caller + +// } diff --git a/ports_module/cortex-m4/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex-m4/ac6/module_manager/src/tx_timer_interrupt.S new file mode 100644 index 00000000..0fceccd6 --- /dev/null +++ b/ports_module/cortex-m4/ac6/module_manager/src/tx_timer_interrupt.S @@ -0,0 +1,257 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .global _tx_timer_time_slice + .global _tx_timer_system_clock + .global _tx_timer_current_ptr + .global _tx_timer_list_start + .global _tx_timer_list_end + .global _tx_timer_expired_time_slice + .global _tx_timer_expired + .global _tx_thread_time_slice + .global _tx_timer_expiration_process + + + .text + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt Cortex-M4/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_timer_interrupt(VOID) +// { + .global _tx_timer_interrupt + .thumb_func +_tx_timer_interrupt: + + /* Upon entry to this routine, it is assumed that context save has already + been called, and therefore the compiler scratch registers are available + for use. */ + + /* Increment the system clock. */ + // _tx_timer_system_clock++; + + LDR r1, =_tx_timer_system_clock // Pickup address of system clock + LDR r0, [r1, #0] // Pickup system clock + ADD r0, r0, #1 // Increment system clock + STR r0, [r1, #0] // Store new system clock + + /* Test for time-slice expiration. */ + // if (_tx_timer_time_slice) + // { + + LDR r3, =_tx_timer_time_slice // Pickup address of time-slice + LDR r2, [r3, #0] // Pickup time-slice + CBZ r2, __tx_timer_no_time_slice // Is it non-active? + // Yes, skip time-slice processing + + /* Decrement the time_slice. */ + // _tx_timer_time_slice--; + + SUB r2, r2, #1 // Decrement the time-slice + STR r2, [r3, #0] // Store new time-slice value + + /* Check for expiration. */ + // if (__tx_timer_time_slice == 0) + + CBNZ r2, __tx_timer_no_time_slice // Has it expired? + // No, skip expiration processing + + /* Set the time-slice expired flag. */ + // _tx_timer_expired_time_slice = TX_TRUE; + + LDR r3, =_tx_timer_expired_time_slice // Pickup address of expired flag + MOV r0, #1 // Build expired value + STR r0, [r3, #0] // Set time-slice expiration flag + + // } + +__tx_timer_no_time_slice: + + /* Test for timer expiration. */ + // if (*_tx_timer_current_ptr) + // { + + LDR r1, =_tx_timer_current_ptr // Pickup current timer pointer address + LDR r0, [r1, #0] // Pickup current timer + LDR r2, [r0, #0] // Pickup timer list entry + CBZ r2, __tx_timer_no_timer // Is there anything in the list? + // No, just increment the timer + + /* Set expiration flag. */ + // _tx_timer_expired = TX_TRUE; + + LDR r3, =_tx_timer_expired // Pickup expiration flag address + MOV r2, #1 // Build expired value + STR r2, [r3, #0] // Set expired flag + B __tx_timer_done // Finished timer processing + + // } + // else + // { +__tx_timer_no_timer: + + /* No timer expired, increment the timer pointer. */ + // _tx_timer_current_ptr++; + + ADD r0, r0, #4 // Move to next timer + + /* Check for wrap-around. */ + // if (_tx_timer_current_ptr == _tx_timer_list_end) + + LDR r3, =_tx_timer_list_end // Pickup addr of timer list end + LDR r2, [r3, #0] // Pickup list end + CMP r0, r2 // Are we at list end? + BNE __tx_timer_skip_wrap // No, skip wrap-around logic + + /* Wrap to beginning of list. */ + // _tx_timer_current_ptr = _tx_timer_list_start; + + LDR r3, =_tx_timer_list_start // Pickup addr of timer list start + LDR r0, [r3, #0] // Set current pointer to list start + +__tx_timer_skip_wrap: + + STR r0, [r1, #0] // Store new current timer pointer + // } + +__tx_timer_done: + + + /* See if anything has expired. */ + // if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) + // { + + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of expired flag + LDR r2, [r3, #0] // Pickup time-slice expired flag + CBNZ r2, __tx_something_expired // Did a time-slice expire? + // If non-zero, time-slice expired + LDR r1, =_tx_timer_expired // Pickup addr of other expired flag + LDR r0, [r1, #0] // Pickup timer expired flag + CBZ r0, __tx_timer_nothing_expired // Did a timer expire? + // No, nothing expired + +__tx_something_expired: + + + STMDB sp!, {r0, lr} // Save the lr register on the stack + // and save r0 just to keep 8-byte alignment + + /* Did a timer expire? */ + // if (_tx_timer_expired) + // { + + LDR r1, =_tx_timer_expired // Pickup addr of expired flag + LDR r0, [r1, #0] // Pickup timer expired flag + CBZ r0, __tx_timer_dont_activate // Check for timer expiration + // If not set, skip timer activation + + /* Process timer expiration. */ + // _tx_timer_expiration_process(); + + BL _tx_timer_expiration_process // Call the timer expiration handling routine + + // } +__tx_timer_dont_activate: + + /* Did time slice expire? */ + // if (_tx_timer_expired_time_slice) + // { + + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of time-slice expired + LDR r2, [r3, #0] // Pickup the actual flag + CBZ r2, __tx_timer_not_ts_expiration // See if the flag is set + // No, skip time-slice processing + + /* Time slice interrupted thread. */ + // _tx_thread_time_slice(); + + BL _tx_thread_time_slice // Call time-slice processing + LDR r0, =_tx_thread_preempt_disable // Build address of preempt disable flag + LDR r1, [r0] // Is the preempt disable flag set? + CBNZ r1, __tx_timer_skip_time_slice // Yes, skip the PendSV logic + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r0] // Pickup the current thread pointer + LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address + LDR r3, [r2] // Pickup the execute thread pointer + LDR r0, =0xE000ED04 // Build address of control register + LDR r2, =0x10000000 // Build value for PendSV bit + CMP r1, r3 // Are they the same? + BEQ __tx_timer_skip_time_slice // If the same, there was no time-slice performed + STR r2, [r0] // Not the same, issue the PendSV for preemption +__tx_timer_skip_time_slice: + + // } + +__tx_timer_not_ts_expiration: + + LDMIA sp!, {r0, lr} // Recover lr register (r0 is just there for + // the 8-byte stack alignment + + // } + +__tx_timer_nothing_expired: + + DSB // Complete all memory access + BX lr // Return to caller + +// } diff --git a/ports_module/cortex-m4/ac6/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex-m4/ac6/module_manager/src/txm_module_manager_alignment_adjust.c new file mode 100644 index 00000000..10319892 --- /dev/null +++ b/ports_module/cortex-m4/ac6/module_manager/src/txm_module_manager_alignment_adjust.c @@ -0,0 +1,399 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_power_of_two_block_size Cortex-M4/MPU/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calculates a power of two size at or immediately above*/ +/* the input size and returns it to the caller. */ +/* */ +/* INPUT */ +/* */ +/* size Block size */ +/* */ +/* OUTPUT */ +/* */ +/* calculated size Rounded up to power of two */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_power_of_two_block_size(ULONG size) +{ + /* Check for 0 size. */ + if(size == 0) + return 0; + + /* Minimum MPU block size is 32. */ + if(size <= 32) + return 32; + + /* Bit twiddling trick to round to next high power of 2 + (if original size is power of 2, it will return original size. Perfect!) */ + size--; + size |= size >> 1; + size |= size >> 2; + size |= size >> 4; + size |= size >> 8; + size |= size >> 16; + size++; + + /* Return a power of 2 size at or above the input size. */ + return(size); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_alignment_adjust Cortex-M4/MPU/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function adjusts the alignment and size of the code and data */ +/* section for a given module implementation. */ +/* */ +/* INPUT */ +/* */ +/* module_preamble Pointer to module preamble */ +/* code_size Size of the code area (updated) */ +/* code_alignment Code area alignment (updated) */ +/* data_size Size of data area (updated) */ +/* data_alignment Data area alignment (updated) */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_power_of_two_block_size Calculate power of two size */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, + ULONG *code_size, + ULONG *code_alignment, + ULONG *data_size, + ULONG *data_alignment) +{ + +ULONG local_code_size; +ULONG local_code_alignment; +ULONG local_data_size; +ULONG local_data_alignment; +ULONG code_block_size; +ULONG data_block_size; +ULONG code_size_accum; +ULONG data_size_accum; + + /* Copy the input parameters into local variables for ease of use. */ + local_code_size = *code_size; + local_code_alignment = *code_alignment; + local_data_size = *data_size; + local_data_alignment = *data_alignment; + + + /* Test for external memory enabled in preamble. */ + if(module_preamble -> txm_module_preamble_property_flags & TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS) + { + /* External/shared memory enabled. TXM_MODULE_MANAGER_CODE_MPU_ENTRIES-1 code entries will be used. */ + if (local_code_size <= (32*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 32 is best. */ + code_block_size = 32; + } + else if (local_code_size <= (64*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 64 is best. */ + code_block_size = 64; + } + else if (local_code_size <= (128*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 128 is best. */ + code_block_size = 128; + } + else if (local_code_size <= (256*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 256 is best. */ + code_block_size = 256; + } + else if (local_code_size <= (512*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 512 is best. */ + code_block_size = 512; + } + else if (local_code_size <= (1024*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 1024 is best. */ + code_block_size = 1024; + } + else if (local_code_size <= (2048*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 2048 is best. */ + code_block_size = 2048; + } + else if (local_code_size <= (4096*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 4096 is best. */ + code_block_size = 4096; + } + else if (local_code_size <= (8192*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 8192 is best. */ + code_block_size = 8192; + } + else if (local_code_size <= (16384*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 16384 is best. */ + code_block_size = 16384; + } + else if (local_code_size <= (32768*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 32768 is best. */ + code_block_size = 32768; + } + else if (local_code_size <= (65536*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 65536 is best. */ + code_block_size = 65536; + } + else if (local_code_size <= (131072*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 131072 is best. */ + code_block_size = 131072; + } + else if (local_code_size <= (262144*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 262144 is best. */ + code_block_size = 262144; + } + else if (local_code_size <= (524288*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 524288 is best. */ + code_block_size = 524288; + } + else if (local_code_size <= (1048576*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 1048576 is best. */ + code_block_size = 1048576; + } + else if (local_code_size <= (2097152*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 2097152 is best. */ + code_block_size = 2097152; + } + else if (local_code_size <= (4194304*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 4194304 is best. */ + code_block_size = 4194304; + } + else + { + /* Just set block size to 32MB just to create an allocation error! */ + code_block_size = 33554432; + } + + /* Calculate the new code size. */ + local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); + + /* Determine if the code block size is greater than the current alignment. If so, use block size + as the alignment. */ + if (code_block_size > local_code_alignment) + local_code_alignment = code_block_size; + + } + else + { + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + local_code_alignment = _txm_power_of_two_block_size(local_code_size) >> 2; + code_size_accum = local_code_alignment + local_code_alignment; + code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); + code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); + local_code_size = code_size_accum; + } + + /* Determine the best data block size, which in our case is the minimal alignment. */ + if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 32 is best. */ + data_block_size = 32; + } + else if (local_data_size <= (64*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 64 is best. */ + data_block_size = 64; + } + else if (local_data_size <= (128*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 128 is best. */ + data_block_size = 128; + } + else if (local_data_size <= (256*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 256 is best. */ + data_block_size = 256; + } + else if (local_data_size <= (512*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 512 is best. */ + data_block_size = 512; + } + else if (local_data_size <= (1024*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 1024 is best. */ + data_block_size = 1024; + } + else if (local_data_size <= (2048*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 2048 is best. */ + data_block_size = 2048; + } + else if (local_data_size <= (4096*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 4096 is best. */ + data_block_size = 4096; + } + else if (local_data_size <= (8192*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 8192 is best. */ + data_block_size = 8192; + } + else if (local_data_size <= (16384*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 16384 is best. */ + data_block_size = 16384; + } + else if (local_data_size <= (32768*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 32768 is best. */ + data_block_size = 32768; + } + else if (local_data_size <= (65536*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 65536 is best. */ + data_block_size = 65536; + } + else if (local_data_size <= (131072*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 131072 is best. */ + data_block_size = 131072; + } + else if (local_data_size <= (262144*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 262144 is best. */ + data_block_size = 262144; + } + else if (local_data_size <= (524288*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 524288 is best. */ + data_block_size = 524288; + } + else if (local_data_size <= (1048576*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 1048576 is best. */ + data_block_size = 1048576; + } + else if (local_data_size <= (2097152*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 2097152 is best. */ + data_block_size = 2097152; + } + else if (local_data_size <= (4194304*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 4194304 is best. */ + data_block_size = 4194304; + } + else + { + /* Just set data block size to 32MB just to create an allocation error! */ + data_block_size = 33554432; + } + + /* Calculate the new data size. */ + data_size_accum = data_block_size; + while(data_size_accum < local_data_size) + { + data_size_accum += data_block_size; + } + local_data_size = data_size_accum; + + /* Determine if the data block size is greater than the current alignment. If so, use block size + as the alignment. */ + if (data_block_size > local_data_alignment) + { + local_data_alignment = data_block_size; + } + + /* Return all the information to the caller. */ + *code_size = local_code_size; + *code_alignment = local_code_alignment; + *data_size = local_data_size; + *data_alignment = local_data_alignment; +} diff --git a/ports_module/cortex-m4/ac6/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex-m4/ac6/module_manager/src/txm_module_manager_external_memory_enable.c new file mode 100644 index 00000000..d0f2240b --- /dev/null +++ b/ports_module/cortex-m4/ac6/module_manager/src/txm_module_manager_external_memory_enable.c @@ -0,0 +1,182 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_mutex.h" +#include "tx_queue.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_external_memory_enable Cortex-M4/MPU/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates an entry in the MPU table for a shared */ +/* memory space. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* start_address Start address of memory */ +/* length Length of external memory */ +/* attributes Memory attributes (r/w) */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_mutex_get Get protection mutex */ +/* _tx_mutex_put Release protection mutex */ +/* _txm_power_of_two_block_size Round length to power of two */ +/* _txm_module_manager_mm_register_setup Reconfigure MPU registers */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, + VOID *start_address, + ULONG length, + UINT attributes) +{ + +ULONG block_size; +ULONG region_size; +ULONG subregion_bits; +ULONG address; +UINT attributes_check = 0; +TXM_MODULE_PREAMBLE *module_preamble; + + /* Determine if the module manager has not been initialized yet. */ + if (_txm_module_manager_ready != TX_TRUE) + { + /* Module manager has not been initialized. */ + return(TX_NOT_AVAILABLE); + } + + /* Determine if the module is valid. */ + if (module_instance == TX_NULL) + { + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Get module manager protection mutex. */ + _tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER); + + /* Determine if the module instance is valid. */ + if (module_instance -> txm_module_instance_id != TXM_MODULE_ID) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Determine if the module instance is in the loaded state. */ + if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if the module is not ready. */ + return(TX_START_ERROR); + } + + /* Check if preamble shared mem and mem protection property bits are set. */ + module_preamble = module_instance -> txm_module_instance_preamble_ptr; + if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) + != (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if bit not set. */ + return(TXM_MODULE_INVALID_PROPERTIES); + } + + /* Start address and length must adhere to Cortex-M MPU. + The address must align with the block size. */ + + block_size = _txm_power_of_two_block_size(length); + address = (ULONG) start_address; + if(address != (address & ~(block_size - 1))) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return alignment error. */ + return(TXM_MODULE_ALIGNMENT_ERROR); + } + + /* At this point, we have a valid address and block size. + Set up MPU registers. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | 0x10; + + /* Calculate the region size. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + /* Calculate the subregion bits. */ + subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); + + /* Check for valid attributes. */ + if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) + { + attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; + } + + /* Build register with attributes. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX+1] = region_size | subregion_bits | attributes_check | 0x12070001; + + /* Keep track of shared memory address and length in module instance. */ + module_instance -> txm_module_instance_shared_memory_address = address; + module_instance -> txm_module_instance_shared_memory_length = length; + + /* Recalculate MPU settings. */ + _txm_module_manager_mm_register_setup(module_instance); + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/ports_module/cortex-m4/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex-m4/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c new file mode 100644 index 00000000..58c4a1be --- /dev/null +++ b/ports_module/cortex-m4/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -0,0 +1,110 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + +/* Define a macro that can be used to allocate global variables useful to + store information about the last fault. This macro is defined in + txm_module_port.h and is usually populated in the assembly language + fault handling prior to the code calling _txm_module_manager_memory_fault_handler. */ + +TXM_MODULE_MANAGER_FAULT_INFO + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_handler Cortex-M4/MPU/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles a fault associated with a memory protected */ +/* module. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_terminate Terminate thread */ +/* */ +/* CALLED BY */ +/* */ +/* Fault handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_memory_fault_handler(VOID) +{ + +TXM_MODULE_INSTANCE *module_instance_ptr; +TX_THREAD *thread_ptr; + + /* Pickup the current thread. */ + thread_ptr = _tx_thread_current_ptr; + + /* Initialize the module instance pointer to NULL. */ + module_instance_ptr = TX_NULL; + + /* Is there a thread? */ + if (thread_ptr) + { + /* Pickup the module instance. */ + module_instance_ptr = thread_ptr -> tx_thread_module_instance_ptr; + + /* Terminate the current thread. */ + _tx_thread_terminate(_tx_thread_current_ptr); + } + + /* Determine if there is a user memory fault notification callback. */ + if (_txm_module_manager_fault_notify) + { + /* Yes, call the user's notification memory fault callback. */ + (_txm_module_manager_fault_notify)(thread_ptr, module_instance_ptr); + } +} diff --git a/ports_module/cortex-m4/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex-m4/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c new file mode 100644 index 00000000..649b1ad2 --- /dev/null +++ b/ports_module/cortex-m4/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -0,0 +1,84 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the external user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_notify Cortex-M4/MPU/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application callback when/if a memory */ +/* fault occurs. The supplied thread is automatically terminated, but */ +/* any other threads in the same module may still execute. */ +/* */ +/* INPUT */ +/* */ +/* notify_function Memory fault notification */ +/* function, NULL disables. */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +{ + /* Setup notification function. */ + _txm_module_manager_fault_notify = notify_function; + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/ports_module/cortex-m4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex-m4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c new file mode 100644 index 00000000..8861ab56 --- /dev/null +++ b/ports_module/cortex-m4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c @@ -0,0 +1,512 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_region_size_get Cortex-M4/MPU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function converts the region size in bytes to the block size */ +/* for the Cortex-M4 MPU specification. */ +/* */ +/* INPUT */ +/* */ +/* block_size Size of the block in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* MPU size specification */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_module_manager_region_size_get(ULONG block_size) +{ + +ULONG return_value; + + /* Process relative to the input block size. */ + if (block_size == 32) + { + return_value = 0x04; + } + else if (block_size == 64) + { + return_value = 0x05; + } + else if (block_size == 128) + { + return_value = 0x06; + } + else if (block_size == 256) + { + return_value = 0x07; + } + else if (block_size == 512) + { + return_value = 0x08; + } + else if (block_size == 1024) + { + return_value = 0x09; + } + else if (block_size == 2048) + { + return_value = 0x0A; + } + else if (block_size == 4096) + { + return_value = 0x0B; + } + else if (block_size == 8192) + { + return_value = 0x0C; + } + else if (block_size == 16384) + { + return_value = 0x0D; + } + else if (block_size == 32768) + { + return_value = 0x0E; + } + else if (block_size == 65536) + { + return_value = 0x0F; + } + else if (block_size == 131072) + { + return_value = 0x10; + } + else if (block_size == 262144) + { + return_value = 0x11; + } + else if (block_size == 524288) + { + return_value = 0x12; + } + else if (block_size == 1048576) + { + return_value = 0x13; + } + else if (block_size == 2097152) + { + return_value = 0x14; + } + else + { + /* Max 4MB MPU pages for modules. */ + return_value = 0x15; + } + + return(return_value); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_calculate_srd_bits Cortex-M4/MPU/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calculates the SRD bits that need to be set to */ +/* protect "length" bytes in a block. */ +/* */ +/* INPUT */ +/* */ +/* block_size Size of the block in bytes */ +/* length Actual length in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* SRD bits to be OR'ed with region attribute register. */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) +{ + +ULONG srd_bits = 0; +UINT srd_bit_index; + + /* length is smaller than block_size, set SRD bits if block_size is 256 or more. */ + if((block_size >= 256) && (length < block_size)) + { + /* Divide block_size by 8 by shifting right 3. Result is size of subregion. */ + block_size = block_size >> 3; + + /* Set SRD index into attribute register. */ + srd_bit_index = 8; + + /* If subregion overlaps length, move to the next subregion. */ + while(length > block_size) + { + length = length - block_size; + srd_bit_index++; + } + /* Check for a portion of code remaining. */ + if(length) + { + srd_bit_index++; + } + + /* Set unused subregion bits. */ + while(srd_bit_index < 16) + { + srd_bits = srd_bits | (0x1 << srd_bit_index); + srd_bit_index++; + } + } + + return(srd_bits); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_mm_register_setup Cortex-M4/MPU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets up the Cortex-M4 MPU register definitions based */ +/* on the module's memory characteristics. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* */ +/* OUTPUT */ +/* */ +/* MPU specifications for module in module_instance */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_manager_region_size_get */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_thread_create */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) +{ + +ULONG code_address; +ULONG code_size; +ULONG data_address; +ULONG data_size; +ULONG start_stop_stack_size; +ULONG callback_stack_size; +ULONG block_size; +ULONG base_address_register; +ULONG base_attribute_register; +ULONG region_size; +ULONG srd_bits = 0; +UINT mpu_register = 0; +UINT mpu_table_index; +UINT i; + + + /* Setup the first region for the ThreadX trampoline code. */ + /* Set base register to user mode entry, which is guaranteed to be at least 32-byte aligned. */ + base_address_register = (ULONG) _txm_module_manager_user_mode_entry; + + /* Mask address to proper range, region 0, set Valid bit. */ + base_address_register = (base_address_register & 0xFFFFFFE0) | mpu_register | 0x10; + module_instance -> txm_module_instance_mpu_registers[0] = base_address_register; + + /* Attributes: read only, write-back, shareable, size 32 bytes, region enabled. */ + module_instance -> txm_module_instance_mpu_registers[1] = 0x06070009; + + /* Initialize the MPU register. */ + mpu_register = 1; + + /* Initialize the MPU table index. */ + mpu_table_index = 2; + + /* Setup values for code area. */ + code_address = (ULONG) module_instance -> txm_module_instance_code_start; + code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; + + /* Check if shared memory was set up. If so, only 3 entries are available for + code protection. If not set up, 4 code entries are available. */ + if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] == 0) + { + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + + /* Now loop through to setup MPU protection for the code area. */ + for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES; i++) + { + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + if (i < 2) + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + } + + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ + else if (i == 2) + { + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size) >> 1; + } + + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + else + { + /* Calculate remaining space. */ + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + + /* Build the base address register. */ + base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Build the base attribute register. */ + base_attribute_register = region_size | srd_bits | 0x06070001; + + /* Setup the MPU Base Address Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; + + /* Setup the MPU Base Attribute Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; + + /* Adjust the code address. */ + code_address = code_address + block_size; + + /* Move MPU table index. */ + mpu_table_index = mpu_table_index + 2; + + /* Increment the MPU register index. */ + mpu_register++; + } + } + + /* Only 3 code entries available. */ + else + { + /* Calculate block size, one code entry taken up by shared memory. */ + block_size = _txm_power_of_two_block_size(code_size / (TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)); + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Now loop through to setup MPU protection for the code area. */ + for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) + { + /* Build the base address register. */ + base_address_register = code_address & ~(block_size - 1) | mpu_register | 0x10; + + /* Check if SRD bits need to be set. */ + if (code_size < block_size) + { + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + + /* Build the base attribute register. */ + base_attribute_register = region_size | srd_bits | 0x06070000; + + /* Is there still some code? If so set the region enable bit. */ + if (code_size) + { + /* Set the region enable bit. */ + base_attribute_register = base_attribute_register | 0x1; + } + /* Setup the MPU Base Address Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; + + /* Setup the MPU Base Attribute Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; + + /* Adjust the code address. */ + code_address = code_address + block_size; + + /* Decrement the code size. */ + if (code_size > block_size) + { + code_size = code_size - block_size; + } + else + { + code_size = 0; + } + + /* Move MPU table index. */ + mpu_table_index = mpu_table_index + 2; + + /* Increment the MPU register index. */ + mpu_register++; + } + + /* Adjust indeces to pass over the shared memory entry. */ + /* Move MPU table index. */ + mpu_table_index = mpu_table_index + 2; + + /* Increment the MPU register index. */ + mpu_register++; + } + + /* Setup values for data area. */ + data_address = (ULONG) module_instance -> txm_module_instance_data_start; + + /* Adjust the size of the module elements to be aligned to the default alignment. We do this + so that when we partition the allocated memory, we can simply place these regions right beside + each other without having to align their pointers. Note this only works when they all have + the same alignment. */ + + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; + start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; + callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; + + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + /* Update the data size to include thread stacks. */ + data_size = data_size + start_stop_stack_size + callback_stack_size; + + block_size = _txm_power_of_two_block_size(data_size / TXM_MODULE_MANAGER_DATA_MPU_ENTRIES); + + /* Reset SRD bitfield. */ + srd_bits = 0; + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Now loop through to setup MPU protection for the data area. */ + for (i = 0; i < TXM_MODULE_MANAGER_DATA_MPU_ENTRIES; i++) + { + /* Build the base address register. */ + base_address_register = (data_address & ~(block_size - 1)) | mpu_register | 0x10; + + /* Check if SRD bits need to be set. */ + if (data_size < block_size) + { + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + } + + /* Build the base attribute register. */ + base_attribute_register = region_size | srd_bits | 0x13070000; + + /* Is there still some data? If so set the region enable bit. */ + if (data_size) + { + /* Set the region enable bit. */ + base_attribute_register = base_attribute_register | 0x1; + } + + /* Setup the MPU Base Address Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; + + /* Setup the MPU Base Attribute Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; + + /* Adjust the data address. */ + data_address = data_address + block_size; + + /* Decrement the data size. */ + if (data_size > block_size) + { + data_size = data_size - block_size; + } + else + { + data_size = 0; + } + + /* Move MPU table index. */ + mpu_table_index = mpu_table_index + 2; + + /* Increment the MPU register index. */ + mpu_register++; + } +} diff --git a/ports_module/cortex-m4/ac6/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex-m4/ac6/module_manager/src/txm_module_manager_thread_stack_build.S new file mode 100644 index 00000000..73c5793c --- /dev/null +++ b/ports_module/cortex-m4/ac6/module_manager/src/txm_module_manager_thread_stack_build.S @@ -0,0 +1,141 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .align 4 + .syntax unified + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_thread_stack_build Cortex-M4/MPU/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread */ +/* function_ptr Pointer to shell function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +// { + .global _txm_module_manager_thread_stack_build + .thumb_func +_txm_module_manager_thread_stack_build: + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-M should look like the following after it is built: + + Stack Top: + LR Interrupted LR (LR at time of PENDSV) + r4 Initial value for r4 + r5 Initial value for r5 + r6 Initial value for r6 + r7 Initial value for r7 + r8 Initial value for r8 + r9 Initial value for r9 + r10 Initial value for r10 + r11 Initial value for r11 + r0 Initial value for r0 (Hardware stack starts here!!) + r1 Initial value for r1 + r2 Initial value for r2 + r3 Initial value for r3 + r12 Initial value for r12 + lr Initial value for lr + pc Initial value for pc + xPSR Initial value for xPSR + + Stack Bottom: (higher memory address) */ + + LDR r2, [r0, #16] // Pickup end of stack area + BIC r2, r2, #0x7 // Align frame + SUB r2, r2, #68 // Subtract frame size + LDR r3, =0xFFFFFFFD // Build initial LR value + STR r3, [r2, #0] // Save on the stack + + /* Actually build the stack frame. */ + + MOV r3, #0 // Build initial register value + STR r3, [r2, #4] // Store initial r4 + STR r3, [r2, #8] // Store initial r5 + STR r3, [r2, #12] // Store initial r6 + STR r3, [r2, #16] // Store initial r7 + STR r3, [r2, #20] // Store initial r8 + STR r3, [r2, #28] // Store initial r10 + STR r3, [r2, #32] // Store initial r11 + + /* Hardware stack follows. */ + + STR r0, [r2, #36] // Store initial r0, which is the thread control block + + LDR r3, [r0, #8] // Pickup thread entry info pointer,which is in the stack pointer position of the thread control block. + // It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this + // function with the actual, initial stack pointer. + STR r3, [r2, #40] // Store initial r1, which is the module entry information. + LDR r3, [r3, #8] // Pickup data base register from the module information + STR r3, [r2, #24] // Store initial r9 (data base register) + MOV r3, #0 // Clear r3 again + + STR r3, [r2, #44] // Store initial r2 + STR r3, [r2, #48] // Store initial r3 + STR r3, [r2, #52] // Store initial r12 + MOV r3, #0xFFFFFFFF // Poison EXC_RETURN value + STR r3, [r2, #56] // Store initial lr + STR r1, [r2, #60] // Store initial pc + MOV r3, #0x01000000 // Only T-bit need be set + STR r3, [r2, #64] // Store initial xPSR + + /* Setup stack pointer. */ + // thread_ptr -> tx_thread_stack_ptr = r2; + + STR r2, [r0, #8] // Save stack pointer in thread's control block + BX lr // Return to caller +// } + diff --git a/ports_module/cortex-m4/gnu/example_build/build_all.bat b/ports_module/cortex-m4/gnu/example_build/build_all.bat new file mode 100644 index 00000000..70c43ec3 --- /dev/null +++ b/ports_module/cortex-m4/gnu/example_build/build_all.bat @@ -0,0 +1,5 @@ + +call build_threadx.bat +call build_threadx_module_library.bat +call build_threadx_module_sample.bat +call build_threadx_module_manager_sample.bat \ No newline at end of file diff --git a/ports_module/cortex-m4/gnu/example_build/build_threadx.bat b/ports_module/cortex-m4/gnu/example_build/build_threadx.bat new file mode 100644 index 00000000..7d3e2b9b --- /dev/null +++ b/ports_module/cortex-m4/gnu/example_build/build_threadx.bat @@ -0,0 +1,280 @@ +del tx.a +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb tx_initialize_low_level.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb ..\module_manager\src\tx_thread_stack_build.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb ..\module_manager\src\tx_thread_schedule.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb ..\module_manager\src\tx_thread_system_return.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb ..\module_manager\src\tx_thread_context_save.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb ..\module_manager\src\tx_thread_context_restore.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb ..\module_manager\src\tx_thread_interrupt_control.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb ..\module_manager\src\tx_timer_interrupt.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb ..\module_manager\src\txm_module_manager_thread_stack_build.S + +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_pool_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_pool_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_pool_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_pool_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_pool_search.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_event_flags_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_event_flags_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_event_flags_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_event_flags_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_event_flags_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc 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+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_semaphore_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_semaphore_put_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_thread_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_thread_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_thread_entry_exit_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_thread_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_thread_preemption_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_thread_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_thread_relinquish.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_thread_reset.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_thread_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_thread_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_thread_terminate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_thread_time_slice_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_thread_wait_abort.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_timer_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_timer_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_timer_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_timer_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_timer_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\txe_timer_info_get.c + +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\module_manager\src\txm_module_manager_alignment_adjust.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_application_request.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_callback_request.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_event_flags_notify_trampoline.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\module_manager\src\txm_module_manager_external_memory_enable.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_file_load.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_in_place_load.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_internal_load.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_kernel_dispatch.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_maximum_module_priority_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\module_manager\src\txm_module_manager_memory_fault_handler.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\module_manager\src\txm_module_manager_memory_fault_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_memory_load.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_object_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_object_deallocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_object_pointer_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_object_pointer_get_extended.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_object_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_properties_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_queue_notify_trampoline.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_semaphore_notify_trampoline.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\module_manager\src\txm_module_manager_mm_register_setup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_start.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_stop.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_thread_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_thread_notify_trampoline.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_thread_reset.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_timer_notify_trampoline.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_unload.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_util.c + + +arm-none-eabi-ar -r tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o +arm-none-eabi-ar -r tx.a tx_thread_interrupt_control.o tx_initialize_low_level.o +arm-none-eabi-ar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o +arm-none-eabi-ar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o +arm-none-eabi-ar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o +arm-none-eabi-ar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o +arm-none-eabi-ar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o +arm-none-eabi-ar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o +arm-none-eabi-ar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o +arm-none-eabi-ar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o +arm-none-eabi-ar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o +arm-none-eabi-ar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o +arm-none-eabi-ar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o +arm-none-eabi-ar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o +arm-none-eabi-ar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o +arm-none-eabi-ar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o +arm-none-eabi-ar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o +arm-none-eabi-ar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o +arm-none-eabi-ar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o +arm-none-eabi-ar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o +arm-none-eabi-ar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o +arm-none-eabi-ar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o +arm-none-eabi-ar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o +arm-none-eabi-ar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o +arm-none-eabi-ar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o +arm-none-eabi-ar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o +arm-none-eabi-ar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o +arm-none-eabi-ar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o +arm-none-eabi-ar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o +arm-none-eabi-ar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o +arm-none-eabi-ar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o +arm-none-eabi-ar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o +arm-none-eabi-ar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o +arm-none-eabi-ar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o +arm-none-eabi-ar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o + +arm-none-eabi-ar -r tx.a txm_module_manager_alignment_adjust.o txm_module_manager_application_request.o txm_module_manager_callback_request.o +arm-none-eabi-ar -r tx.a txm_module_manager_event_flags_notify_trampoline.o txm_module_manager_external_memory_enable.o txm_module_manager_file_load.o +arm-none-eabi-ar -r tx.a txm_module_manager_in_place_load.o txm_module_manager_initialize.o +arm-none-eabi-ar -r tx.a txm_module_manager_kernel_dispatch.o txm_module_manager_maximum_module_priority_set.o txm_module_manager_memory_fault_handler.o +arm-none-eabi-ar -r tx.a txm_module_manager_memory_fault_notify.o txm_module_manager_memory_load.o txm_module_manager_object_pointer_get.o +arm-none-eabi-ar -r tx.a txm_module_manager_object_pool_create.o txm_module_manager_queue_notify_trampoline.o txm_module_manager_semaphore_notify_trampoline.o +arm-none-eabi-ar -r tx.a txm_module_manager_mm_register_setup.o txm_module_manager_start.o txm_module_manager_stop.o +arm-none-eabi-ar -r tx.a txm_module_manager_thread_create.o txm_module_manager_thread_notify_trampoline.o txm_module_manager_thread_reset.o +arm-none-eabi-ar -r tx.a txm_module_manager_timer_notify_trampoline.o txm_module_manager_unload.o txm_module_manager_thread_stack_build.o +arm-none-eabi-ar -r tx.a txm_module_manager_internal_load.o +arm-none-eabi-ar -r tx.a txm_module_manager_object_allocate.o +arm-none-eabi-ar -r tx.a txm_module_manager_object_deallocate.o +arm-none-eabi-ar -r tx.a txm_module_manager_object_pointer_get_extended.o +arm-none-eabi-ar -r tx.a txm_module_manager_properties_get.o +arm-none-eabi-ar -r tx.a txm_module_manager_util.o \ No newline at end of file diff --git a/ports_module/cortex-m4/gnu/example_build/build_threadx_module_library.bat b/ports_module/cortex-m4/gnu/example_build/build_threadx_module_library.bat new file mode 100644 index 00000000..bf4af9e6 --- /dev/null +++ b/ports_module/cortex-m4/gnu/example_build/build_threadx_module_library.bat @@ -0,0 +1,118 @@ +del txm.a + +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_set_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_application_request.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_callback_request_thread_entry.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_object_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_object_deallocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_object_pointer_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\module_lib\src\txm_module_thread_shell_entry.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_thread_system_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_flush.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_front_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_receive.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_send_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_ceiling_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_put_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_entry_exit_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_identify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_interrupt_control.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_preemption_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_relinquish.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_reset.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_sleep.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_stack_error_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_terminate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_time_slice_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_wait_abort.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_time_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_time_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_buffer_full_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_disable.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_enable.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_event_filter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_event_unfilter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_isr_enter_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_isr_exit_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_user_event_insert.c + +arm-none-eabi-ar -r txm.a txm_block_allocate.o txm_block_pool_create.o txm_block_pool_delete.o txm_block_pool_info_get.o txm_block_pool_performance_info_get.o txm_block_pool_performance_system_info_get.o +arm-none-eabi-ar -r txm.a txm_block_pool_prioritize.o txm_block_release.o +arm-none-eabi-ar -r txm.a txm_byte_allocate.o txm_byte_pool_create.o txm_byte_pool_delete.o txm_byte_pool_info_get.o txm_byte_pool_performance_info_get.o txm_byte_pool_performance_system_info_get.o +arm-none-eabi-ar -r txm.a txm_byte_pool_prioritize.o txm_byte_release.o +arm-none-eabi-ar -r txm.a txm_event_flags_create.o txm_event_flags_delete.o txm_event_flags_get.o txm_event_flags_info_get.o txm_event_flags_performance_info_get.o txm_event_flags_performance_system_info_get.o +arm-none-eabi-ar -r txm.a txm_event_flags_set.o txm_event_flags_set_notify.o +arm-none-eabi-ar -r txm.a txm_module_application_request.o txm_module_callback_request_thread_entry.o txm_module_object_allocate.o txm_module_object_deallocate.o txm_module_object_pointer_get.o txm_module_thread_shell_entry.o txm_module_thread_system_suspend.o +arm-none-eabi-ar -r txm.a txm_mutex_create.o txm_mutex_delete.o txm_mutex_get.o txm_mutex_info_get.o txm_mutex_performance_info_get.o txm_mutex_performance_system_info_get.o txm_mutex_prioritize.o txm_mutex_put.o +arm-none-eabi-ar -r txm.a txm_queue_create.o txm_queue_delete.o txm_queue_flush.o txm_queue_front_send.o txm_queue_info_get.o txm_queue_performance_info_get.o txm_queue_performance_system_info_get.o +arm-none-eabi-ar -r txm.a txm_queue_prioritize.o txm_queue_receive.o txm_queue_send.o txm_queue_send_notify.o +arm-none-eabi-ar -r txm.a txm_semaphore_ceiling_put.o txm_semaphore_create.o txm_semaphore_delete.o txm_semaphore_get.o txm_semaphore_info_get.o txm_semaphore_performance_info_get.o txm_semaphore_performance_system_info_get.o +arm-none-eabi-ar -r txm.a txm_semaphore_prioritize.o txm_semaphore_put.o txm_semaphore_put_notify.o +arm-none-eabi-ar -r txm.a txm_thread_create.o txm_thread_delete.o txm_thread_entry_exit_notify.o txm_thread_identify.o txm_thread_info_get.o txm_thread_interrupt_control.o txm_thread_performance_info_get.o +arm-none-eabi-ar -r txm.a txm_thread_performance_system_info_get.o txm_thread_preemption_change.o txm_thread_priority_change.o txm_thread_relinquish.o txm_thread_reset.o txm_thread_resume.o +arm-none-eabi-ar -r txm.a txm_thread_sleep.o txm_thread_stack_error_notify.o txm_thread_suspend.o txm_thread_terminate.o txm_thread_time_slice_change.o txm_thread_wait_abort.o +arm-none-eabi-ar -r txm.a txm_time_get.o txm_time_set.o +arm-none-eabi-ar -r txm.a txm_timer_activate.o txm_timer_change.o txm_timer_create.o txm_timer_deactivate.o txm_timer_delete.o txm_timer_info_get.o txm_timer_performance_info_get.o txm_timer_performance_system_info_get.o +arm-none-eabi-ar -r txm.a txm_trace_buffer_full_notify.o txm_trace_disable.o txm_trace_enable.o txm_trace_event_filter.o txm_trace_event_unfilter.o txm_trace_isr_enter_insert.o txm_trace_isr_exit_insert.o txm_trace_user_event_insert.o diff --git a/ports_module/cortex-m4/gnu/example_build/build_threadx_module_manager_sample.bat b/ports_module/cortex-m4/gnu/example_build/build_threadx_module_manager_sample.bat new file mode 100644 index 00000000..8d24580f --- /dev/null +++ b/ports_module/cortex-m4/gnu/example_build/build_threadx_module_manager_sample.bat @@ -0,0 +1,4 @@ +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc sample_threadx_module_manager.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb tx_simulator_startup.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb cortexm_crt0.S +arm-none-eabi-ld -A cortex-m4 -ereset_handler -T sample_threadx.ld tx_simulator_startup.o cortexm_crt0.o sample_threadx_module_manager.o tx.a libc.a -o sample_threadx_module_manager.axf -M > sample_threadx_module_manager.map diff --git a/ports_module/cortex-m4/gnu/example_build/build_threadx_module_sample.bat b/ports_module/cortex-m4/gnu/example_build/build_threadx_module_sample.bat new file mode 100644 index 00000000..37e68d0d --- /dev/null +++ b/ports_module/cortex-m4/gnu/example_build/build_threadx_module_sample.bat @@ -0,0 +1,5 @@ +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -fpie -fno-plt -mpic-data-is-text-relative -msingle-pic-base txm_module_preamble.s +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -fpie -fno-plt -mpic-data-is-text-relative -msingle-pic-base gcc_setup.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -fpie -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc sample_threadx_module.c +arm-none-eabi-ld -A cortex-m4 -T sample_threadx_module.ld txm_module_preamble.o gcc_setup.o sample_threadx_module.o -e _txm_module_thread_shell_entry txm.a -o sample_threadx_module.axf -M > sample_threadx_module.map + diff --git a/ports_module/cortex-m4/gnu/example_build/cortexm_crt0.s b/ports_module/cortex-m4/gnu/example_build/cortexm_crt0.s new file mode 100644 index 00000000..d4cb1636 --- /dev/null +++ b/ports_module/cortex-m4/gnu/example_build/cortexm_crt0.s @@ -0,0 +1,127 @@ + .global _start + .extern main + + + .section .init, "ax" + .code 16 + .align 2 + .thumb_func + + +_start: + CPSID i + ldr r1, =__stack_end__ + mov sp, r1 + + + /* Copy initialised sections into RAM if required. */ + ldr r0, =__data_load_start__ + ldr r1, =__data_start__ + ldr r2, =__data_end__ + bl crt0_memory_copy + ldr r0, =__text_load_start__ + ldr r1, =__text_start__ + ldr r2, =__text_end__ + bl crt0_memory_copy + ldr r0, =__fast_load_start__ + ldr r1, =__fast_start__ + ldr r2, =__fast_end__ + bl crt0_memory_copy + ldr r0, =__ctors_load_start__ + ldr r1, =__ctors_start__ + ldr r2, =__ctors_end__ + bl crt0_memory_copy + ldr r0, =__dtors_load_start__ + ldr r1, =__dtors_start__ + ldr r2, =__dtors_end__ + bl crt0_memory_copy + ldr r0, =__rodata_load_start__ + ldr r1, =__rodata_start__ + ldr r2, =__rodata_end__ + bl crt0_memory_copy + + + /* Zero bss. */ + ldr r0, =__bss_start__ + ldr r1, =__bss_end__ + mov r2, #0 + bl crt0_memory_set + + + /* Setup heap - not recommended for Threadx but here for compatibility reasons */ + ldr r0, = __heap_start__ + ldr r1, = __heap_end__ + sub r1, r1, r0 + mov r2, #0 + str r2, [r0] + add r0, r0, #4 + str r1, [r0] + + + /* constructors in case of using C++ */ + ldr r0, =__ctors_start__ + ldr r1, =__ctors_end__ +crt0_ctor_loop: + cmp r0, r1 + beq crt0_ctor_end + ldr r2, [r0] + add r0, #4 + push {r0-r1} + blx r2 + pop {r0-r1} + b crt0_ctor_loop +crt0_ctor_end: + + + /* Setup call frame for main() */ + mov r0, #0 + mov lr, r0 + mov r12, sp + + +start: + /* Jump to main() */ + mov r0, #0 + mov r1, #0 + ldr r2, =main + blx r2 + /* when main returns, loop forever. */ +crt0_exit_loop: + b crt0_exit_loop + + + + /* Startup helper functions. */ + + +crt0_memory_copy: + cmp r0, r1 + beq memory_copy_done + sub r2, r2, r1 + beq memory_copy_done +memory_copy_loop: + ldrb r3, [r0] + add r0, r0, #1 + strb r3, [r1] + add r1, r1, #1 + sub r2, r2, #1 + bne memory_copy_loop +memory_copy_done: + bx lr + + +crt0_memory_set: + cmp r0, r1 + beq memory_set_done + strb r2, [r0] + add r0, r0, #1 + b crt0_memory_set +memory_set_done: + bx lr + + + /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */ + .section .stack, "wa", %nobits + .section .stack_process, "wa", %nobits + .section .heap, "wa", %nobits + \ No newline at end of file diff --git a/ports_module/cortex-m4/gnu/example_build/gcc_setup.s b/ports_module/cortex-m4/gnu/example_build/gcc_setup.s new file mode 100644 index 00000000..d7c61892 --- /dev/null +++ b/ports_module/cortex-m4/gnu/example_build/gcc_setup.s @@ -0,0 +1,127 @@ + + .text + .align 4 + .syntax unified + + .global _gcc_setup + .thumb_func +_gcc_setup: + + STMDB sp!, {r3, r4, r5, r6, r7, lr} // Store other preserved registers + + ldr r3, =__FLASH_segment_start__ + ldr r4, =__RAM_segment_start__ + mov r5,r0 + + /* Copy GOT table. */ + + ldr r0, =__got_load_start__ + sub r0,r0,r3 + add r0,r0,r5 + ldr r1, =__new_got_start__ + sub r1,r1, r4 + add r1,r1,r9 + ldr r2, =__new_got_end__ + sub r2,r2,r4 + add r2,r2,r9 + +new_got_setup: + cmp r1, r2 // See if there are more GOT entries + beq got_setup_done // No, done with GOT setup + ldr r6, [r0] // Pickup current GOT entry + cmp r6, #0 // Is it 0? + beq address_built // Yes, just skip the adjustment + cmp r6, r4 // Is it in the code or data area? + blt flash_area // If less than, it is a code address + sub r6, r6, r4 // Compute offset of data area + add r6, r6, r9 // Build address based on the loaded data address + b address_built // Finished building address +flash_area: + sub r6, r6, r3 // Compute offset of code area + add r6, r6, r5 // Build address based on the loaded code address +address_built: + str r6, [r1] // Store in new GOT table + add r0, r0, #4 // Move to next entry + add r1, r1, #4 // + b new_got_setup // Continue at the top of the loop +got_setup_done: + + + /* Copy initialised sections into RAM if required. */ + + ldr r0, =__data_load_start__ + sub r0,r0,r3 + add r0,r0,r5 + ldr r1, =__data_start__ + sub r1,r1, r4 + add r1,r1,r9 + ldr r2, =__data_end__ + sub r2,r2,r4 + add r2,r2,r9 + bl crt0_memory_copy + + /* Zero bss. */ + + ldr r0, =__bss_start__ + sub r0,r0,r4 + add r0,r0,r9 + ldr r1, =__bss_end__ + sub r1,r1,r4 + add r1,r1,r9 + mov r2, #0 + bl crt0_memory_set + + + /* Setup heap - not recommended for Threadx but here for compatibility reasons */ + + ldr r0, =__heap_start__ + sub r0,r0,r4 + add r0,r0,r9 + ldr r1, =__heap_end__ + sub r1,r1,r4 + add r1,r1,r9 + sub r1,r1,r0 + mov r2, #0 + str r2, [r0] + add r0, r0, #4 + str r1, [r0] + + LDMIA sp!, {r3, r4, r5, r6, r7, lr} // Store other preserved registers + bx lr // Return to caller + + .align 4 + + /* Startup helper functions. */ + + .thumb_func +crt0_memory_copy: + + cmp r0, r1 + beq memory_copy_done + cmp r2, r1 + beq memory_copy_done + sub r2, r2, r1 +memory_copy_loop: + ldrb r3, [r0] + add r0, r0, #1 + strb r3, [r1] + add r1, r1, #1 + sub r2, r2, #1 + cmp r2, #0 + bne memory_copy_loop +memory_copy_done: + bx lr + + .thumb_func +crt0_memory_set: + cmp r0, r1 + beq memory_set_done + strb r2, [r0] + add r0, r0, #1 + b crt0_memory_set +memory_set_done: + bx lr + + /* Setup attibutes of heap section so it doesn't take up room in the elf file */ + .section .heap, "wa", %nobits + \ No newline at end of file diff --git a/ports_module/cortex-m4/gnu/example_build/sample_threadx.ld b/ports_module/cortex-m4/gnu/example_build/sample_threadx.ld new file mode 100644 index 00000000..4a7ce31d --- /dev/null +++ b/ports_module/cortex-m4/gnu/example_build/sample_threadx.ld @@ -0,0 +1,206 @@ +MEMORY +{ + UNPLACED_SECTIONS (wx) : ORIGIN = 0x100000000, LENGTH = 0 + CM3_System_Control_Space (wx) : ORIGIN = 0xe000e000, LENGTH = 0x00001000 + AHB_Peripherals (wx) : ORIGIN = 0x50000000, LENGTH = 0x00200000 + APB1_Peripherals (wx) : ORIGIN = 0x40080000, LENGTH = 0x00080000 + APB0_Peripherals (wx) : ORIGIN = 0x40000000, LENGTH = 0x00080000 + GPIO (wx) : ORIGIN = 0x2009c000, LENGTH = 0x00004000 + AHBSRAM1 (wx) : ORIGIN = 0x20080000, LENGTH = 0x00004000 + AHBSRAM0 (wx) : ORIGIN = 0x2007c000, LENGTH = 0x00004000 + RAM (wx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 +} + + +SECTIONS +{ + __CM3_System_Control_Space_segment_start__ = 0xe000e000; + __CM3_System_Control_Space_segment_end__ = 0xe000f000; + __AHB_Peripherals_segment_start__ = 0x50000000; + __AHB_Peripherals_segment_end__ = 0x50200000; + __APB1_Peripherals_segment_start__ = 0x40080000; + __APB1_Peripherals_segment_end__ = 0x40100000; + __APB0_Peripherals_segment_start__ = 0x40000000; + __APB0_Peripherals_segment_end__ = 0x40080000; + __GPIO_segment_start__ = 0x2009c000; + __GPIO_segment_end__ = 0x200a0000; + __AHBSRAM1_segment_start__ = 0x20080000; + __AHBSRAM1_segment_end__ = 0x20084000; + __AHBSRAM0_segment_start__ = 0x2007c000; + __AHBSRAM0_segment_end__ = 0x20080000; + __RAM_segment_start__ = 0x20000000; + __RAM_segment_end__ = 0x20008000; + __FLASH_segment_start__ = 0x00000000; + __FLASH_segment_end__ = 0x00030000; + + __STACKSIZE__ = 1024; + __STACKSIZE_PROCESS__ = 0; + __STACKSIZE_IRQ__ = 0; + __STACKSIZE_FIQ__ = 0; + __STACKSIZE_SVC__ = 0; + __STACKSIZE_ABT__ = 0; + __STACKSIZE_UND__ = 0; + __HEAPSIZE__ = 128; + + __vectors_load_start__ = __FLASH_segment_start__; + .vectors __FLASH_segment_start__ : AT(__FLASH_segment_start__) + { + __vectors_start__ = .; + *(.vectors .vectors.*) + } + __vectors_end__ = __vectors_start__ + SIZEOF(.vectors); + + . = ASSERT(__vectors_end__ >= __FLASH_segment_start__ && __vectors_end__ <= (__FLASH_segment_start__ + 0x00030000) , "error: .vectors is too large to fit in FLASH memory segment"); + + __init_load_start__ = ALIGN(__vectors_end__ , 4); + .init ALIGN(__vectors_end__ , 4) : AT(ALIGN(__vectors_end__ , 4)) + { + __init_start__ = .; + *(.init .init.*) + } + __init_end__ = __init_start__ + SIZEOF(.init); + + . = ASSERT(__init_end__ >= __FLASH_segment_start__ && __init_end__ <= (__FLASH_segment_start__ + 0x00030000) , "error: .init is too large to fit in FLASH memory segment"); + + __text_load_start__ = ALIGN(__init_end__ , 4); + .text ALIGN(__init_end__ , 4) : AT(ALIGN(__init_end__ , 4)) + { + __text_start__ = .; + *(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table) + } + __text_end__ = __text_start__ + SIZEOF(.text); + + . = ASSERT(__text_end__ >= __FLASH_segment_start__ && __text_end__ <= (__FLASH_segment_start__ + 0x00030000) , "error: .text is too large to fit in FLASH memory segment"); + + __dtors_load_start__ = ALIGN(__text_end__ , 4); + .dtors ALIGN(__text_end__ , 4) : AT(ALIGN(__text_end__ , 4)) + { + __dtors_start__ = .; + KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) + } + __dtors_end__ = __dtors_start__ + SIZEOF(.dtors); + + . = ASSERT(__dtors_end__ >= __FLASH_segment_start__ && __dtors_end__ <= (__FLASH_segment_start__ + 0x00030000) , "error: .dtors is too large to fit in FLASH memory segment"); + + __ctors_load_start__ = ALIGN(__dtors_end__ , 4); + .ctors ALIGN(__dtors_end__ , 4) : AT(ALIGN(__dtors_end__ , 4)) + { + __ctors_start__ = .; + KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) + } + __ctors_end__ = __ctors_start__ + SIZEOF(.ctors); + + . = ASSERT(__ctors_end__ >= __FLASH_segment_start__ && __ctors_end__ <= (__FLASH_segment_start__ + 0x00030000) , "error: .ctors is too large to fit in FLASH memory segment"); + + __rodata_load_start__ = ALIGN(__ctors_end__ , 4); + .rodata ALIGN(__ctors_end__ , 4) : AT(ALIGN(__ctors_end__ , 4)) + { + __rodata_start__ = .; + *(.rodata .rodata.* .gnu.linkonce.r.*) + } + __rodata_end__ = __rodata_start__ + SIZEOF(.rodata); + + . = ASSERT(__rodata_end__ >= __FLASH_segment_start__ && __rodata_end__ <= (__FLASH_segment_start__ + 0x00030000) , "error: .rodata is too large to fit in FLASH memory segment"); + + __fast_load_start__ = ALIGN(__rodata_end__ , 4); + .fast ALIGN(__RAM_segment_start__ , 4) : AT(ALIGN(__rodata_end__ , 4)) + { + __fast_start__ = .; + *(.fast .fast.*) + } + __fast_end__ = __fast_start__ + SIZEOF(.fast); + + __fast_load_end__ = __fast_load_start__ + SIZEOF(.fast); + + . = ASSERT((__fast_load_start__ + SIZEOF(.fast)) >= __FLASH_segment_start__ && (__fast_load_start__ + SIZEOF(.fast)) <= (__FLASH_segment_start__ + 0x00030000) , "error: .fast is too large to fit in FLASH memory segment"); + + .fast_run ALIGN(__RAM_segment_start__ , 4) (NOLOAD) : + { + __fast_run_start__ = .; + . = MAX(__fast_run_start__ + SIZEOF(.fast), .); + } + __fast_run_end__ = __fast_run_start__ + SIZEOF(.fast_run); + + . = ASSERT(__fast_run_end__ >= __RAM_segment_start__ && __fast_run_end__ <= (__RAM_segment_start__ + 0x00020000) , "error: .fast_run is too large to fit in RAM memory segment"); + + __data_load_start__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4); + .data ALIGN(__fast_run_end__ , 4) : AT(ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4)) + { + __data_start__ = .; + *(.data .data.* .gnu.linkonce.d.*) + } + __data_end__ = __data_start__ + SIZEOF(.data); + + __data_load_end__ = __data_load_start__ + SIZEOF(.data); + + __FLASH_segment_used_end__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4) + SIZEOF(.data); + + . = ASSERT((__data_load_start__ + SIZEOF(.data)) >= __FLASH_segment_start__ && (__data_load_start__ + SIZEOF(.data)) <= (__FLASH_segment_start__ + 0x00030000) , "error: .data is too large to fit in FLASH memory segment"); + + .data_run ALIGN(__fast_run_end__ , 4) (NOLOAD) : + { + __data_run_start__ = .; + . = MAX(__data_run_start__ + SIZEOF(.data), .); + } + __data_run_end__ = __data_run_start__ + SIZEOF(.data_run); + + . = ASSERT(__data_run_end__ >= __RAM_segment_start__ && __data_run_end__ <= (__RAM_segment_start__ + 0x00020000) , "error: .data_run is too large to fit in RAM memory segment"); + + __bss_load_start__ = ALIGN(__data_run_end__ , 4); + .bss ALIGN(__data_run_end__ , 4) (NOLOAD) : AT(ALIGN(__data_run_end__ , 4)) + { + __bss_start__ = .; + *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON) + } + __bss_end__ = __bss_start__ + SIZEOF(.bss); + + . = ASSERT(__bss_end__ >= __RAM_segment_start__ && __bss_end__ <= (__RAM_segment_start__ + 0x00020000) , "error: .bss is too large to fit in RAM memory segment"); + + __non_init_load_start__ = ALIGN(__bss_end__ , 4); + .non_init ALIGN(__bss_end__ , 4) (NOLOAD) : AT(ALIGN(__bss_end__ , 4)) + { + __non_init_start__ = .; + *(.non_init .non_init.*) + } + __non_init_end__ = __non_init_start__ + SIZEOF(.non_init); + + . = ASSERT(__non_init_end__ >= __RAM_segment_start__ && __non_init_end__ <= (__RAM_segment_start__ + 0x00020000) , "error: .non_init is too large to fit in RAM memory segment"); + + __heap_load_start__ = ALIGN(__non_init_end__ , 4); + .heap ALIGN(__non_init_end__ , 4) (NOLOAD) : AT(ALIGN(__non_init_end__ , 4)) + { + __heap_start__ = .; + *(.heap) + . = ALIGN(MAX(__heap_start__ + __HEAPSIZE__ , .), 4); + } + __heap_end__ = __heap_start__ + SIZEOF(.heap); + + . = ASSERT(__heap_end__ >= __RAM_segment_start__ && __heap_end__ <= (__RAM_segment_start__ + 0x00020000) , "error: .heap is too large to fit in RAM memory segment"); + + __stack_load_start__ = ALIGN(__heap_end__ , 4); + .stack ALIGN(__heap_end__ , 4) (NOLOAD) : AT(ALIGN(__heap_end__ , 4)) + { + __stack_start__ = .; + *(.stack) + . = ALIGN(MAX(__stack_start__ + __STACKSIZE__ , .), 4); + } + __stack_end__ = __stack_start__ + SIZEOF(.stack); + + . = ASSERT(__stack_end__ >= __RAM_segment_start__ && __stack_end__ <= (__RAM_segment_start__ + 0x00020000) , "error: .stack is too large to fit in RAM memory segment"); + + __stack_process_load_start__ = ALIGN(__stack_end__ , 4); + .stack_process ALIGN(__stack_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_end__ , 4)) + { + __stack_process_start__ = .; + *(.stack_process) + . = ALIGN(MAX(__stack_process_start__ + __STACKSIZE_PROCESS__ , .), 4); + } + __stack_process_end__ = __stack_process_start__ + SIZEOF(.stack_process); + + __RAM_segment_used_end__ = ALIGN(__stack_end__ , 4) + SIZEOF(.stack_process); + + . = ASSERT(__stack_process_end__ >= __RAM_segment_start__ && __stack_process_end__ <= (__RAM_segment_start__ + 0x00020000) , "error: .stack_process is too large to fit in RAM memory segment"); + +} + diff --git a/ports_module/cortex-m4/gnu/example_build/sample_threadx_module.c b/ports_module/cortex-m4/gnu/example_build/sample_threadx_module.c new file mode 100644 index 00000000..52557312 --- /dev/null +++ b/ports_module/cortex-m4/gnu/example_build/sample_threadx_module.c @@ -0,0 +1,428 @@ +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, + event flags group, byte pool, and block pool. */ + +/* Specify that this is a module! */ + +#define TXM_MODULE + + +/* Include the ThreadX module definitions. */ + +#include "txm_module.h" + + +/* Define constants. */ + +#define DEMO_STACK_SIZE 512 +#define DEMO_BYTE_POOL_SIZE 6000 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the pool space in the bss section of the module. ULONG is used to + get the word alignment. */ + +ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD *thread_0; +TX_THREAD *thread_1; +TX_THREAD *thread_2; +TX_THREAD *thread_3; +TX_THREAD *thread_4; +TX_THREAD *thread_5; +TX_THREAD *thread_6; +TX_THREAD *thread_7; +TX_QUEUE *queue_0; +TX_SEMAPHORE *semaphore_0; +TX_MUTEX *mutex_0; +TX_EVENT_FLAGS_GROUP *event_flags_0; +TX_BYTE_POOL *byte_pool_0; +TX_BLOCK_POOL *block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; +ULONG semaphore_0_puts; +ULONG event_0_sets; +ULONG queue_0_sends; + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + +void semaphore_0_notify(TX_SEMAPHORE *semaphore_ptr) +{ + + if (semaphore_ptr == semaphore_0) + semaphore_0_puts++; +} + + +void event_0_notify(TX_EVENT_FLAGS_GROUP *event_flag_group_ptr) +{ + + if (event_flag_group_ptr == event_flags_0) + event_0_sets++; +} + + +void queue_0_notify(TX_QUEUE *queue_ptr) +{ + + if (queue_ptr == queue_0) + queue_0_sends++; +} + + +/* Define the module start function. */ + +void demo_module_start(ULONG id) +{ + +CHAR *pointer; + + /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + the control block(s). */ + txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_2, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_3, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_4, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_5, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_6, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_7, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&queue_0, sizeof(TX_QUEUE)); + txm_module_object_allocate((void*)&semaphore_0, sizeof(TX_SEMAPHORE)); + txm_module_object_allocate((void*)&mutex_0, sizeof(TX_MUTEX)); + txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); + txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); + txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(byte_pool_0, "module byte pool 0", (UCHAR*)demo_module_pool_space, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(queue_0, "module queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + tx_queue_send_notify(queue_0, queue_0_notify); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(semaphore_0, "module semaphore 0", 1); + + tx_semaphore_put_notify(semaphore_0, semaphore_0_notify); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(event_flags_0, "module event flags 0"); + + tx_event_flags_set_notify(event_flags_0, event_0_notify); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(mutex_0, "module mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(block_pool_0, "module block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + /* Test memory handler. */ + *(ULONG *)0x20010000 = 0xCDCDCDCD; + + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + diff --git a/ports_module/cortex-m4/gnu/example_build/sample_threadx_module.ld b/ports_module/cortex-m4/gnu/example_build/sample_threadx_module.ld new file mode 100644 index 00000000..a33fbfeb --- /dev/null +++ b/ports_module/cortex-m4/gnu/example_build/sample_threadx_module.ld @@ -0,0 +1,210 @@ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00030000, LENGTH = 0x00010000 + RAM (wx) : ORIGIN = 0, LENGTH = 0x00100000 +} + + +SECTIONS +{ + __FLASH_segment_start__ = 0x00030000; + __FLASH_segment_end__ = 0x00040000; + __RAM_segment_start__ = 0; + __RAM_segment_end__ = 0x8000; + + __HEAPSIZE__ = 128; + + __preamble_load_start__ = __FLASH_segment_start__; + .preamble __FLASH_segment_start__ : AT(__FLASH_segment_start__) + { + __preamble_start__ = .; + *(.preamble .preamble.*) + } + __preamble_end__ = __preamble_start__ + SIZEOF(.preamble); + + __dynsym_load_start__ = ALIGN(__preamble_end__ , 4); + .dynsym ALIGN(__dynsym_load_start__ , 4) : AT(ALIGN(__dynsym_load_start__ , 4)) + { + . = ALIGN(4); + KEEP (*(.dynsym)) + KEEP (*(.dynsym*)) + . = ALIGN(4); + } + __dynsym_end__ = __dynsym_load_start__ + SIZEOF(.dynsym); + + __dynstr_load_start__ = ALIGN(__dynsym_end__ , 4); + .dynstr ALIGN(__dynstr_load_start__ , 4) : AT(ALIGN(__dynstr_load_start__, 4)) + { + . = ALIGN(4); + KEEP (*(.dynstr)) + KEEP (*(.dynstr*)) + . = ALIGN(4); + } + __dynstr_end__ = __dynstr_load_start__ + SIZEOF(.dynstr); + + __reldyn_load_start__ = ALIGN(__dynstr_end__ , 4); + .rel.dyn ALIGN(__reldyn_load_start__ , 4) : AT(ALIGN(__reldyn_load_start__ , 4)) + { + . = ALIGN(4); + KEEP (*(.rel.dyn)) + KEEP (*(.rel.dyn*)) + . = ALIGN(4); + } + __reldyn_end__ = __reldyn_load_start__ + SIZEOF(.rel.dyn); + + __relplt_load_start__ = ALIGN(__reldyn_end__ , 4); + .rel.plt ALIGN(__relplt_load_start__ , 4) : AT(ALIGN(__relplt_load_start__ , 4)) + { + . = ALIGN(4); + KEEP (*(.rel.plt)) + KEEP (*(.rel.plt*)) + . = ALIGN(4); + } + __relplt_end__ = __relplt_load_start__ + SIZEOF(.rel.plt); + + __plt_load_start__ = ALIGN(__relplt_end__ , 4); + .plt ALIGN(__plt_load_start__ , 4) : AT(ALIGN(__plt_load_start__ , 4)) + { + . = ALIGN(4); + KEEP (*(.plt)) + KEEP (*(.plt*)) + . = ALIGN(4); + } + __plt_end__ = __plt_load_start__ + SIZEOF(.plt); + + __interp_load_start__ = ALIGN(__plt_end__ , 4); + .interp ALIGN(__interp_load_start__ , 4) : AT(ALIGN(__interp_load_start__ , 4)) + { + . = ALIGN(4); + KEEP (*(.interp)) + KEEP (*(.interp*)) + . = ALIGN(4); + } + __interp_end__ = __interp_load_start__ + SIZEOF(.interp); + + __hash_load_start__ = ALIGN(__interp_end__ , 4); + .hash ALIGN(__hash_load_start__ , 4) : AT(ALIGN(__hash_load_start__, 4)) + { + . = ALIGN(4); + KEEP (*(.hash)) + KEEP (*(.hash*)) + . = ALIGN(4); + } + __hash_end__ = __hash_load_start__ + SIZEOF(.hash); + + __text_load_start__ = ALIGN(__hash_end__ , 4); + .text ALIGN(__text_load_start__ , 4) : AT(ALIGN(__text_load_start__, 4)) + { + __text_start__ = .; + *(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table ) + } + __text_end__ = __text_start__ + SIZEOF(.text); + + __dtors_load_start__ = ALIGN(__text_end__ , 4); + .dtors ALIGN(__text_end__ , 4) : AT(ALIGN(__text_end__ , 4)) + { + __dtors_start__ = .; + KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) + } + __dtors_end__ = __dtors_start__ + SIZEOF(.dtors); + + __ctors_load_start__ = ALIGN(__dtors_end__ , 4); + .ctors ALIGN(__dtors_end__ , 4) : AT(ALIGN(__dtors_end__ , 4)) + { + __ctors_start__ = .; + KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) + } + __ctors_end__ = __ctors_start__ + SIZEOF(.ctors); + + __got_load_start__ = ALIGN(__ctors_end__ , 4); + .got ALIGN(__ctors_end__ , 4) : AT(ALIGN(__ctors_end__ , 4)) + { + . = ALIGN(4); + _sgot = .; + KEEP (*(.got)) + KEEP (*(.got*)) + . = ALIGN(4); + _egot = .; + } + __got_end__ = __got_load_start__ + SIZEOF(.got); + + __rodata_load_start__ = ALIGN(__got_end__ , 4); + .rodata ALIGN(__got_end__ , 4) : AT(ALIGN(__got_end__ , 4)) + { + __rodata_start__ = .; + *(.rodata .rodata.* .gnu.linkonce.r.*) + } + __rodata_end__ = __rodata_start__ + SIZEOF(.rodata); + + __code_size__ = __rodata_end__ - __FLASH_segment_start__; + + __fast_load_start__ = ALIGN(__rodata_end__ , 4); + + __fast_load_end__ = __fast_load_start__ + SIZEOF(.fast); + + __new_got_start__ = ALIGN(__RAM_segment_start__ , 4); + + __new_got_end__ = __new_got_start__ + SIZEOF(.got); + + .fast ALIGN(__new_got_end__ , 4) : AT(ALIGN(__rodata_end__ , 4)) + { + __fast_start__ = .; + *(.fast .fast.*) + } + __fast_end__ = __fast_start__ + SIZEOF(.fast); + + .fast_run ALIGN(__fast_end__ , 4) (NOLOAD) : + { + __fast_run_start__ = .; + . = MAX(__fast_run_start__ + SIZEOF(.fast), .); + } + __fast_run_end__ = __fast_run_start__ + SIZEOF(.fast_run); + + __data_load_start__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4); + .data ALIGN(__fast_run_end__ , 4) : AT(ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4)) + { + __data_start__ = .; + *(.data .data.* .gnu.linkonce.d.*) + } + __data_end__ = __data_start__ + SIZEOF(.data); + + __data_load_end__ = __data_load_start__ + SIZEOF(.data); + + __FLASH_segment_used_end__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4) + SIZEOF(.data); + + .data_run ALIGN(__fast_run_end__ , 4) (NOLOAD) : + { + __data_run_start__ = .; + . = MAX(__data_run_start__ + SIZEOF(.data), .); + } + __data_run_end__ = __data_run_start__ + SIZEOF(.data_run); + + __bss_load_start__ = ALIGN(__data_run_end__ , 4); + .bss ALIGN(__data_run_end__ , 4) (NOLOAD) : AT(ALIGN(__data_run_end__ , 4)) + { + __bss_start__ = .; + *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON) + } + __bss_end__ = __bss_start__ + SIZEOF(.bss); + + __non_init_load_start__ = ALIGN(__bss_end__ , 4); + .non_init ALIGN(__bss_end__ , 4) (NOLOAD) : AT(ALIGN(__bss_end__ , 4)) + { + __non_init_start__ = .; + *(.non_init .non_init.*) + } + __non_init_end__ = __non_init_start__ + SIZEOF(.non_init); + + __heap_load_start__ = ALIGN(__non_init_end__ , 4); + .heap ALIGN(__non_init_end__ , 4) (NOLOAD) : AT(ALIGN(__non_init_end__ , 4)) + { + __heap_start__ = .; + *(.heap) + . = ALIGN(MAX(__heap_start__ + __HEAPSIZE__ , .), 4); + } + __heap_end__ = __heap_start__ + SIZEOF(.heap); + + __data_size__ = __heap_end__ - __RAM_segment_start__; + +} + diff --git a/ports_module/cortex-m4/gnu/example_build/sample_threadx_module_manager.c b/ports_module/cortex-m4/gnu/example_build/sample_threadx_module_manager.c new file mode 100644 index 00000000..203223be --- /dev/null +++ b/ports_module/cortex-m4/gnu/example_build/sample_threadx_module_manager.c @@ -0,0 +1,109 @@ +/* Small demonstration of the ThreadX module manager. */ + +#include "tx_api.h" +#include "txm_module.h" + + +#define DEMO_STACK_SIZE 1024 + +/* Define the ThreadX object control blocks... */ + +TX_THREAD module_manager; +TXM_MODULE_INSTANCE my_module; + + +/* Define the object pool area. */ + +UCHAR object_memory[16384]; +UCHAR module_ram[32768]; + +/* Define the count of memory faults. */ + +ULONG memory_faults; + + +/* Define thread prototypes. */ + +void module_manager_entry(ULONG thread_input); + + +/* Define fault handler. */ + +VOID module_fault_handler(TX_THREAD *thread, TXM_MODULE_INSTANCE *module) +{ + + /* Just increment the fault counter. */ + memory_faults++; +} + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = (CHAR*)first_unused_memory; + + + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + pointer = pointer + DEMO_STACK_SIZE; +} + + + + +/* Define the test threads. */ + +void module_manager_entry(ULONG thread_input) +{ + + /* Initialize the module manager. */ + txm_module_manager_initialize((VOID *) module_ram, 32768); + + txm_module_manager_object_pool_create(object_memory, sizeof(object_memory)); + + /* Register a fault handler. */ + txm_module_manager_memory_fault_notify(module_fault_handler); + + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ + txm_module_manager_memory_load(&my_module, "my module", (VOID *) 0x00030000); + + /* Enable 128 byte read/write shared memory region at 0x20010000. */ + txm_module_manager_external_memory_enable(&my_module, (void *) 0x20010000, 128, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); + + /* Start the module. */ + txm_module_manager_start(&my_module); + + /* Sleep for a while.... */ + tx_thread_sleep(1000); + + /* Stop the module. */ + txm_module_manager_stop(&my_module); + + /* Unload the module. */ + txm_module_manager_unload(&my_module); + + /* Load the module that is already there. */ + txm_module_manager_in_place_load(&my_module, "my module", (VOID *) 0x00030000); + + /* Start the module again. */ + txm_module_manager_start(&my_module); + + /* Now just spin... */ + while(1) + { + + tx_thread_sleep(100); + } +} diff --git a/ports_module/cortex-m4/gnu/example_build/tx_initialize_low_level.S b/ports_module/cortex-m4/gnu/example_build/tx_initialize_low_level.S new file mode 100644 index 00000000..e7bac6a1 --- /dev/null +++ b/ports_module/cortex-m4/gnu/example_build/tx_initialize_low_level.S @@ -0,0 +1,209 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global __RAM_segment_used_end__ + .global _tx_timer_interrupt + .global __main + .global _vectors + .global __tx_NMIHandler @ NMI + .global __tx_BadHandler @ HardFault + .global __tx_DBGHandler @ Monitor + .global __tx_PendSVHandler @ PendSV + .global __tx_SysTickHandler @ SysTick + .global __tx_IntHandler @ Int 0 + +SYSTEM_CLOCK = 6000000 +SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) + + .text 32 + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-M4/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +//VOID _tx_initialize_low_level(VOID) +//{ + .global _tx_initialize_low_level + .thumb_func +_tx_initialize_low_level: + + /* Disable interrupts during ThreadX initialization. */ + CPSID i + + /* Set base of available memory to end of non-initialised RAM area. */ + LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer + LDR r1, =__RAM_segment_used_end__ @ Build first free address + ADD r1, r1, #4 @ + STR r1, [r0] @ Setup first unused memory pointer + + /* Setup Vector Table Offset Register. */ + MOV r0, #0xE000E000 @ Build address of NVIC registers + LDR r1, =_vectors @ Pickup address of vector table + STR r1, [r0, #0xD08] @ Set vector table address + + /* Set system stack pointer from vector value. */ + LDR r0, =_tx_thread_system_stack_ptr @ Build address of system stack pointer + LDR r1, =_vectors @ Pickup address of vector table + LDR r1, [r1] @ Pickup reset stack pointer + STR r1, [r0] @ Save system stack pointer + + /* Enable the cycle count register. */ + LDR r0, =0xE0001000 @ Build address of DWT register + LDR r1, [r0] @ Pickup the current value + ORR r1, r1, #1 @ Set the CYCCNTENA bit + STR r1, [r0] @ Enable the cycle count register + + /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ + MOV r0, #0xE000E000 @ Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] @ Setup SysTick Reload Value + MOV r1, #0x7 @ Build SysTick Control Enable Value + STR r1, [r0, #0x10] @ Setup SysTick Control + + /* Configure handler priorities. */ + LDR r1, =0x00000000 @ Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] @ Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 @ SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] @ Setup System Handlers 8-11 Priority Registers + @ Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] @ Setup System Handlers 12-15 Priority Registers + @ Note: PnSV must be lowest priority, which is 0xFF + + + /* Return to caller. */ + BX lr +//} + + +/* Define shells for each of the unused vectors. */ + + .global __tx_BadHandler + .thumb_func +__tx_BadHandler: + B __tx_BadHandler + +/* added to catch the hardfault */ + + .global __tx_HardfaultHandler + .thumb_func +__tx_HardfaultHandler: + B __tx_HardfaultHandler + +/* Generic interrupt handler template */ + .global __tx_IntHandler + .thumb_func +__tx_IntHandler: +// VOID InterruptHandler (VOID) +// { + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter // Call the ISR enter function +#endif + + /* Do interrupt handler work here */ + /* BL .... */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit // Call the ISR exit function +#endif + POP {r0, lr} + BX LR +// } + +/* System Tick timer interrupt handler */ + .global __tx_SysTickHandler + .global SysTick_Handler + .thumb_func +__tx_SysTickHandler: + .thumb_func +SysTick_Handler: +// VOID TimerInterruptHandler (VOID) +// { + + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter // Call the ISR enter function +#endif + BL _tx_timer_interrupt +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit // Call the ISR exit function +#endif + POP {r0, lr} + BX LR +// } + + +/* NMI, DBG handlers */ + .global __tx_NMIHandler + .thumb_func +__tx_NMIHandler: + B __tx_NMIHandler + + .global __tx_DBGHandler + .thumb_func +__tx_DBGHandler: + B __tx_DBGHandler + diff --git a/ports_module/cortex-m4/gnu/example_build/tx_simulator_startup.s b/ports_module/cortex-m4/gnu/example_build/tx_simulator_startup.s new file mode 100644 index 00000000..73692924 --- /dev/null +++ b/ports_module/cortex-m4/gnu/example_build/tx_simulator_startup.s @@ -0,0 +1,73 @@ + + .syntax unified + .section .vectors, "ax" + .code 16 + .align 0 + .global _vectors + +_vectors: + .word __stack_end__ + .word reset_handler + .word __tx_NMIHandler + .word __tx_HardfaultHandler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word __tx_SVCallHandler //_SVC_Handler - used by Threadx scheduler // + .word __tx_DBGHandler + .word 0 // Reserved + .word __tx_PendSVHandler + .word __tx_SysTickHandler // Used by Threadx timer functionality + .word __tx_BadHandler // Populate with user Interrupt handler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + + + + .section .init, "ax" + .global reset_handler + .thumb_func +reset_handler: + +// low level hardware config, such as PLL setup goes here + + b _start + + + diff --git a/ports_module/cortex-m4/gnu/example_build/txm_module_preamble.S b/ports_module/cortex-m4/gnu/example_build/txm_module_preamble.S new file mode 100644 index 00000000..e2df9b29 --- /dev/null +++ b/ports_module/cortex-m4/gnu/example_build/txm_module_preamble.S @@ -0,0 +1,58 @@ + .text + .align 4 + .syntax unified + + /* Define public symbols. */ + .global __txm_module_preamble + + /* Define application-specific start/stop entry points for the module. */ + .global demo_module_start + + /* Define common external refrences. */ + .global _txm_module_thread_shell_entry + .global _txm_module_callback_request_thread_entry + +__txm_module_preamble: + .dc.l 0x4D4F4455 // Module ID + .dc.l 0x6 // Module Major Version + .dc.l 0x1 // Module Minor Version + .dc.l 32 // Module Preamble Size in 32-bit words + .dc.l 0x12345678 // Module ID (application defined) + .dc.l 0x02000007 // Module Properties where: + // Bits 31-24: Compiler ID + // 0 -> IAR + // 1 -> RVDS + // 2 -> GNU + // Bits 23-3: Reserved + // Bit 2: 0 -> Disable shared/external memory access + // 1 -> Enable shared/external memory access + // Bit 1: 0 -> No MPU protection + // 1 -> MPU protection (must have user mode selected - bit 0 set) + // Bit 0: 0 -> Privileged mode execution + // 1 -> User mode execution + .dc.l _txm_module_thread_shell_entry - . - 0 // Module Shell Entry Point + .dc.l demo_module_start - . - 0 // Module Start Thread Entry Point + .dc.l 0 // Module Stop Thread Entry Point + .dc.l 1 // Module Start/Stop Thread Priority + .dc.l 1024 // Module Start/Stop Thread Stack Size + .dc.l _txm_module_callback_request_thread_entry - . - 0 // Module Callback Thread Entry + .dc.l 1 // Module Callback Thread Priority + .dc.l 1024 // Module Callback Thread Stack Size + .dc.l __code_size__ // Module Code Size + .dc.l __data_size__ // Module Data Size + .dc.l 0 // Reserved 0 + .dc.l 0 // Reserved 1 + .dc.l 0 // Reserved 2 + .dc.l 0 // Reserved 3 + .dc.l 0 // Reserved 4 + .dc.l 0 // Reserved 5 + .dc.l 0 // Reserved 6 + .dc.l 0 // Reserved 7 + .dc.l 0 // Reserved 8 + .dc.l 0 // Reserved 9 + .dc.l 0 // Reserved 10 + .dc.l 0 // Reserved 11 + .dc.l 0 // Reserved 12 + .dc.l 0 // Reserved 13 + .dc.l 0 // Reserved 14 + .dc.l 0 // Reserved 15 diff --git a/ports_module/cortex-m4/gnu/inc/tx_port.h b/ports_module/cortex-m4/gnu/inc/tx_port.h new file mode 100644 index 00000000..1cf859e1 --- /dev/null +++ b/ports_module/cortex-m4/gnu/inc/tx_port.h @@ -0,0 +1,518 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-M4/GNU */ +/* 6.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX Cortex-M7 port. */ + +#define TX_INT_DISABLE 1 /* Disable interrupts */ +#define TX_INT_ENABLE 0 /* Enable interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0 + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); + +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) + + +#ifdef TX_ENABLE_FPU_SUPPORT + + +#ifdef TX_MISRA_ENABLE + +ULONG _tx_misra_control_get(void); +void _tx_misra_control_set(ULONG value); +ULONG _tx_misra_fpccr_get(void); +void _tx_misra_vfp_touch(void); + +#else + +__attribute__( ( always_inline ) ) static inline ULONG __get_control(void) +{ + +ULONG control_value; + + __asm__ volatile (" MRS %0,CONTROL ": "=r" (control_value) ); + return(control_value); +} + + +__attribute__( ( always_inline ) ) static inline void __set_control(ULONG control_value) +{ + + __asm__ volatile (" MSR CONTROL,%0": : "r" (control_value): "memory" ); +} + + +#endif + + +/* A completed thread falls into _thread_shell_entry and we can simply deactivate the FPU via CONTROL.FPCA + in order to ensure no lazy stacking will occur. */ + +#ifndef TX_MISRA_ENABLE + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_control(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_control(_tx_vfp_state); \ + } +#else + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } + +#endif + + +/* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. + If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + the lazy FPU save, then restore the CONTROL.FPCA state. */ + +#ifndef TX_MISRA_ENABLE + + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_control(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_control(_tx_vfp_state); \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = *((ULONG *) 0xE000EF34); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_control(); \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + __asm__ volatile ("vmov.f32 s0, s0"); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = __get_control(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_control(_tx_vfp_state); \ + } \ + } \ + } \ + } +#else + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = _tx_misra_fpccr_get(); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + _tx_misra_vfp_touch(); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + } \ + } \ + } +#endif + +#else + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + +#endif + + + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define the get system state macro. */ + +#ifndef TX_THREAD_GET_SYSTEM_STATE +#ifndef TX_MISRA_ENABLE + +__attribute__( ( always_inline ) ) static inline unsigned int __get_ipsr_value(void) +{ + +unsigned int ipsr_value; + + __asm__ volatile (" MRS %0,IPSR ": "=r" (ipsr_value) ); + return(ipsr_value); +} + + +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | __get_ipsr_value()) +#else +ULONG _tx_misra_ipsr_get(VOID); +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get()) +#endif +#endif + + +/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value + indicates that _tx_thread_system_return should not be called. */ + +#ifndef TX_THREAD_SYSTEM_RETURN_CHECK +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#endif + +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to + prevent early scheduling on Cortex-M parts. */ + +#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; + + +/* This ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + +#endif + + +#ifndef TX_DISABLE_INLINE + +/* Define GNU specific macros, with in-line assembly for performance. */ + +__attribute__( ( always_inline ) ) static inline unsigned int __disable_interrupts(void) +{ + +unsigned int primask_value; + + __asm__ volatile (" MRS %0,PRIMASK ": "=r" (primask_value) ); + __asm__ volatile (" CPSID i" : : : "memory" ); + return(primask_value); +} + +__attribute__( ( always_inline ) ) static inline void __restore_interrupts(unsigned int primask_value) +{ + + __asm__ volatile (" MSR PRIMASK,%0": : "r" (primask_value): "memory" ); +} + +__attribute__( ( always_inline ) ) static inline unsigned int __get_primask_value(void) +{ + +unsigned int primask_value; + + __asm__ volatile (" MRS %0,PRIMASK ": "=r" (primask_value) ); + return(primask_value); +} + +__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void) +{ + + __asm__ volatile (" CPSIE i": : : "memory" ); +} + + +__attribute__( ( always_inline ) ) static inline void _tx_thread_system_return_inline(void) +{ +unsigned int interrupt_save; + + *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + if (__get_ipsr_value() == 0) + { + interrupt_save = __get_primask_value(); + __enable_interrupts(); + __restore_interrupts(interrupt_save); + } +} + + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = __disable_interrupts(); +#define TX_RESTORE __restore_interrupts(interrupt_save); + + +/* Redefine _tx_thread_system_return for improved performance. */ + +#define _tx_thread_system_return _tx_thread_system_return_inline + + +#else + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); +#define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); +#endif + + +/* Define FPU extension for the Cortex-M4. Each is assumed to be called in the context of the executing + thread. This is for legacy only, and not needed anylonger. */ + +void tx_thread_fpu_enable(void); +void tx_thread_fpu_disable(void); + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/GNU Version 6.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + + + + + diff --git a/ports_module/cortex-m4/gnu/inc/txm_module_port.h b/ports_module/cortex-m4/gnu/inc/txm_module_port.h new file mode 100644 index 00000000..107b99f6 --- /dev/null +++ b/ports_module/cortex-m4/gnu/inc/txm_module_port.h @@ -0,0 +1,323 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* txm_module_port.h Cortex-M4/MPU/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the basic module constants, interface structures, */ +/* and function prototypes. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TXM_MODULE_PORT_H +#define TXM_MODULE_PORT_H + +/* Determine if the optional Modules user define file should be used. */ + +#ifdef TXM_MODULE_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in txm_module_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "txm_module_user.h" +#endif + +/* It is assumed that the base ThreadX tx_port.h file has been modified to add the + following extensions to the ThreadX thread control block (this code should replace + the corresponding macro define in tx_port.h): + +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; + +The following extensions must also be defined in tx_port.h: + +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); + +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); +*/ + +/* Define the kernel stack size for a module thread. */ +#ifndef TXM_MODULE_KERNEL_STACK_SIZE +#define TXM_MODULE_KERNEL_STACK_SIZE 768 +#endif + +/* Define constants specific to the tools the module can be built with for this particular modules port. */ + +#define TXM_MODULE_IAR_COMPILER 0x00000000 +#define TXM_MODULE_RVDS_COMPILER 0x01000000 +#define TXM_MODULE_GNU_COMPILER 0x02000000 +#define TXM_MODULE_COMPILER_MASK 0xFF000000 +#define TXM_MODULE_OPTIONS_MASK 0x000000FF + + +/* Define the properties for this particular module port. */ + +#define TXM_MODULE_MEMORY_PROTECTION_ENABLED + +#ifdef TXM_MODULE_MEMORY_PROTECTION_ENABLED +#define TXM_MODULE_REQUIRE_ALLOCATED_OBJECT_MEMORY +#else +#define TXM_MODULE_REQUIRE_LOCAL_OBJECT_MEMORY +#endif + +#define TXM_MODULE_USER_MODE 0x00000001 +#define TXM_MODULE_MEMORY_PROTECTION 0x00000002 +#define TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS 0x00000004 + + +/* Define the supported options for this module. */ + +#define TXM_MODULE_MANAGER_SUPPORTED_OPTIONS (TXM_MODULE_USER_MODE | TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS) +#define TXM_MODULE_MANAGER_REQUIRED_OPTIONS 0 + + +/* Define offset adjustments according to the compiler used to build the module. */ + +#define TXM_MODULE_IAR_SHELL_ADJUST 24 +#define TXM_MODULE_IAR_START_ADJUST 28 +#define TXM_MODULE_IAR_STOP_ADJUST 32 +#define TXM_MODULE_IAR_CALLBACK_ADJUST 44 + +#define TXM_MODULE_RVDS_SHELL_ADJUST 0 +#define TXM_MODULE_RVDS_START_ADJUST 0 +#define TXM_MODULE_RVDS_STOP_ADJUST 0 +#define TXM_MODULE_RVDS_CALLBACK_ADJUST 0 + +#define TXM_MODULE_GNU_SHELL_ADJUST 24 +#define TXM_MODULE_GNU_START_ADJUST 28 +#define TXM_MODULE_GNU_STOP_ADJUST 32 +#define TXM_MODULE_GNU_CALLBACK_ADJUST 44 + + +/* Define other module port-specific constants. */ + +/* Define INLINE_DECLARE to inline for GNU compiler. */ + +#define INLINE_DECLARE inline + +/* Define the number of MPU entries assigned to the code and data sections. On Cortex-M parts, there can only be 7 total + entries, since ThreadX uses one for access to the kernel dispatch function. */ + +#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 +#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 +#define TXM_MODULE_MANAGER_SHARED_MPU_INDEX 8 +#define TXM_MODULE_MANAGER_SHARED_MPU_REGION 4 + +/* Shared memory region attributes. */ +#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 +#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 + +/* Define the port-extensions to the module manager instance structure. */ + +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + ULONG txm_module_instance_mpu_registers[16]; \ + ULONG txm_module_instance_shared_memory_address; \ + ULONG txm_module_instance_shared_memory_length; + + +/* Define the memory fault information structure that is populated when a memory fault occurs. */ + + +typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT +{ + TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr; + VOID *txm_module_manager_memory_fault_info_code_location; + ULONG txm_module_manager_memory_fault_info_shcsr; + ULONG txm_module_manager_memory_fault_info_cfsr; + ULONG txm_module_manager_memory_fault_info_mmfar; + ULONG txm_module_manager_memory_fault_info_bfar; + ULONG txm_module_manager_memory_fault_info_control; + ULONG txm_module_manager_memory_fault_info_sp; + ULONG txm_module_manager_memory_fault_info_r0; + ULONG txm_module_manager_memory_fault_info_r1; + ULONG txm_module_manager_memory_fault_info_r2; + ULONG txm_module_manager_memory_fault_info_r3; + ULONG txm_module_manager_memory_fault_info_r4; + ULONG txm_module_manager_memory_fault_info_r5; + ULONG txm_module_manager_memory_fault_info_r6; + ULONG txm_module_manager_memory_fault_info_r7; + ULONG txm_module_manager_memory_fault_info_r8; + ULONG txm_module_manager_memory_fault_info_r9; + ULONG txm_module_manager_memory_fault_info_r10; + ULONG txm_module_manager_memory_fault_info_r11; + ULONG txm_module_manager_memory_fault_info_r12; + ULONG txm_module_manager_memory_fault_info_lr; + ULONG txm_module_manager_memory_fault_info_xpsr; +} TXM_MODULE_MANAGER_MEMORY_FAULT_INFO; + + +#define TXM_MODULE_MANAGER_FAULT_INFO \ + TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info; + +/* Define the macro to check the code alignment. */ + +#define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment) \ + { \ + ULONG temp; \ + temp = (ULONG) module_location; \ + temp = temp & (code_alignment - 1); \ + if (temp) \ + { \ + _tx_mutex_put(&_txm_module_manager_mutex); \ + return(TXM_MODULE_ALIGNMENT_ERROR); \ + } \ + } + + +/* Define the macro to adjust the alignment and size for code/data areas. */ + +#define TXM_MODULE_MANAGER_ALIGNMENT_ADJUST(module_preamble, code_size, code_alignment, data_size, data_alignment) _txm_module_manager_alignment_adjust(module_preamble, &code_size, &code_alignment, &data_size, &data_alignment); + + +/* Define the macro to adjust the symbols in the module preamble. */ + +#define TXM_MODULE_MANAGER_CALCULATE_ADJUSTMENTS(properties, shell_function_adjust, start_function_adjust, stop_function_adjust, callback_function_adjust) \ + if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_IAR_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_IAR_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_IAR_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_IAR_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_IAR_CALLBACK_ADJUST; \ + } \ + else if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_RVDS_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_RVDS_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_RVDS_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_RVDS_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_RVDS_CALLBACK_ADJUST; \ + } \ + else \ + { \ + shell_function_adjust = TXM_MODULE_GNU_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_GNU_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_GNU_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_GNU_CALLBACK_ADJUST; \ + } + + +/* Define the macro to populate the thread control block with module port-specific information. + Check if the module is in user mode and set up txm_module_thread_entry_info_kernel_call_dispatcher accordingly. +*/ + +#define TXM_MODULE_MANAGER_THREAD_SETUP(thread_ptr, module_instance) \ + thread_ptr -> tx_thread_module_current_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \ + thread_ptr -> tx_thread_module_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \ + if (thread_ptr -> tx_thread_module_user_mode) \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_user_mode_entry; \ + } \ + else \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_kernel_dispatch; \ + } + + +/* Define the macro to populate the module control block with module port-specific information. + If memory protection is enabled, set up the MPU registers. +*/ +#define TXM_MODULE_MANAGER_MODULE_SETUP(module_instance) \ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE) \ + { \ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) \ + { \ + _txm_module_manager_mm_register_setup(module_instance); \ + } \ + } \ + else \ + { \ + /* Do nothing. */ \ + } + +/* Define the macro to perform port-specific functions when unloading the module. */ +/* Nothing needs to be done for this port. */ +#define TXM_MODULE_MANAGER_MODULE_UNLOAD(module_instance) + + +/* Define the macros to perform port-specific checks when passing pointers to the kernel. */ + +/* Define macro to make sure object is inside the module's data. */ +#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ + /* Check if it's inside module data. */ \ + ((((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && \ + (((obj_ptr) + (obj_size)) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) || \ + /* Check if it's inside shared memory. */ \ + (((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address) && \ + (((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (module_instance -> txm_module_instance_shared_memory_address + module_instance -> txm_module_instance_shared_memory_length)))) + + +/* Define some internal prototypes to this module port. */ + +#ifndef TX_SOURCE_CODE +#define txm_module_manager_memory_fault_notify _txm_module_manager_memory_fault_notify +#endif + + +#define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES \ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment); \ +VOID _txm_module_manager_memory_fault_handler(VOID); \ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)); \ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \ +ULONG _txm_power_of_two_block_size(ULONG size); \ +ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); \ +ULONG _txm_module_manager_region_size_get(ULONG block_size); + +#define TXM_MODULE_MANAGER_VERSION_ID \ +CHAR _txm_module_manager_version_id[] = \ + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/MPU/GNU Version 6.1 *"; + +#endif diff --git a/ports_module/cortex-m4/gnu/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex-m4/gnu/module_lib/src/txm_module_thread_shell_entry.c new file mode 100644 index 00000000..212cc5fe --- /dev/null +++ b/ports_module/cortex-m4/gnu/module_lib/src/txm_module_thread_shell_entry.c @@ -0,0 +1,174 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#ifndef TXM_MODULE +#define TXM_MODULE +#endif + +#ifndef TX_SOURCE_CODE +#define TX_SOURCE_CODE +#endif + + +/* Include necessary system files. */ + +#include "txm_module.h" +#include "tx_thread.h" + +/* Define the global module entry pointer from the start thread of the module. */ + +TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; + + +/* Define the dispatch function pointer used in the module implementation. */ + +ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3); + + +/* Define the GCC startup code that clears the uninitialized global data and sets up the + preset global variables. */ + +extern VOID _gcc_setup(TXM_MODULE_INSTANCE *); + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_thread_shell_entry Cortex-M4/MPU/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calls the specified entry function of the thread. It */ +/* also provides a place for the thread's entry function to return. */ +/* If the thread returns, this function places the thread in a */ +/* "COMPLETED" state. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to current thread */ +/* thread_info Pointer to thread entry info */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _gcc_setup GNU global init function */ +/* thread_entry Thread's entry function */ +/* tx_thread_resume Resume the module callback thread */ +/* _txm_module_thread_system_suspend Module thread suspension routine */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) +{ + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + VOID (*entry_exit_notify)(TX_THREAD *, UINT); +#endif + + + /* Determine if this is the start thread. If so, we must prepare the module for + execution. If not, simply skip the C startup code. */ + if (thread_info -> txm_module_thread_entry_info_start_thread) + { + /* Initialize the GNU C environment. */ + _gcc_setup(thread_info -> txm_module_thread_entry_info_code_base_address); + + /* Save the entry info pointer, for later use. */ + _txm_module_entry_info = thread_info; + + /* Save the kernel function dispatch address. This is used to make all resident calls from + the module. */ + _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; + + /* Ensure that we have a valid pointer. */ + while (!_txm_module_kernel_call_dispatcher) + { + /* Loop here, if an error is present getting the dispatch function pointer! + An error here typically indicates the resident portion of _tx_thread_schedule + is not supporting the trap to obtain the function pointer. */ + } + + /* Resume the module's callback thread, already created in the manager. */ + _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); + } + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has been entered! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_ENTRY); + } +#endif + + /* Call current thread's entry function. */ + (thread_info -> txm_module_thread_entry_info_entry) (thread_info -> txm_module_thread_entry_info_parameter); + + /* Suspend thread with a "completed" state. */ + + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine again. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has exited! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_EXIT); + } +#endif + + /* Call actual thread suspension routine. */ + _txm_module_thread_system_suspend(thread_ptr); + +#ifdef TX_SAFETY_CRITICAL + + /* If we ever get here, raise safety critical exception. */ + TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0); +#endif +} + diff --git a/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_context_restore.S new file mode 100644 index 00000000..2101419a --- /dev/null +++ b/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_context_restore.S @@ -0,0 +1,87 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_system_stack_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable + .global _tx_execution_isr_exit +@ +@ + .text + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_restore Cortex-M4/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is only needed for legacy applications and it should */ +@/* not be called in any new development on a Cortex-M. */ +@/* This function restores the interrupt context if it is processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs Interrupt Service Routines */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_restore(VOID) +@{ + .global _tx_thread_context_restore + .thumb_func +_tx_thread_context_restore: +@ +@ /* Not needed for this port - just return! */ + BX lr +@} diff --git a/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_context_save.S b/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_context_save.S new file mode 100644 index 00000000..03fe07ce --- /dev/null +++ b/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_context_save.S @@ -0,0 +1,81 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_execution_isr_enter +@ +@ + .text + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_save Cortex-M4/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is only needed for legacy applications and it should */ +@/* not be called in any new development on a Cortex-M. */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_save(VOID) +@{ + .global _tx_thread_context_save + .thumb_func +_tx_thread_context_save: +@ +@ /* Not needed for this port - just return! */ + BX lr +@} diff --git a/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..411db298 --- /dev/null +++ b/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_interrupt_control.S @@ -0,0 +1,81 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ + + +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ + + + .text 32 + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_control Cortex-M4/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for changing the interrupt lockout */ +@/* posture of the system. */ +@/* */ +@/* INPUT */ +@/* */ +@/* new_posture New interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@/* UINT _tx_thread_interrupt_control(UINT new_posture) +{ */ + .global _tx_thread_interrupt_control + .thumb_func +_tx_thread_interrupt_control: + +@/* Pickup current interrupt lockout posture. */ + + MRS r1, PRIMASK @ Pickup current interrupt lockout + +@/* Apply the new interrupt posture. */ + + MSR PRIMASK, r0 @ Apply the new interrupt lockout + MOV r0, r1 @ Transfer old to return register + BX lr @ Return to caller + +@/* } */ diff --git a/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_schedule.S new file mode 100644 index 00000000..c7181bcf --- /dev/null +++ b/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_schedule.S @@ -0,0 +1,551 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .global _tx_thread_current_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_system_stack_ptr + .global _tx_execution_thread_enter + .global _tx_execution_thread_exit + .global _tx_thread_preempt_disable + .global _txm_module_manager_memory_fault_handler + .global _txm_module_manager_memory_fault_info + + .text + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule Cortex-M4/MPU/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* _tx_thread_context_restore Restore thread's context */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_schedule(VOID) +// { + .global _tx_thread_schedule + .thumb_func +_tx_thread_schedule: + + /* This function should only ever be called on Cortex-M + from the first schedule request. Subsequent scheduling occurs + from the PendSV handling routines below. */ + + /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ + + MOV r0, #0 // Build value for TX_FALSE + LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag + STR r0, [r2, #0] // Clear preempt disable flag + + /* Clear CONTROL.FPCA bit so FPU registers aren't unnecessarily stacked. */ + +#ifdef __ARMVFP__ + MRS r0, CONTROL // Pickup current CONTROL register + BIC r0, r0, #4 // Clear the FPCA bit + MSR CONTROL, r0 // Setup new CONTROL register +#endif + + /* Enable memory fault registers. */ + + LDR r0, =0xE000ED24 // Build SHCSR address + LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults + STR r1, [r0] // + + /* Enable interrupts */ + + CPSIE i + + /* Enter the scheduler for the first time. */ + + MOV r0, #0x10000000 // Load PENDSVSET bit + MOV r1, #0xE000E000 // Load NVIC base + STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + DSB // Complete all memory accesses + ISB // Flush pipeline + + /* Wait here for the PendSV to take place. */ + +__tx_wait_here: + B __tx_wait_here // Wait for the PendSV to happen +// } + + + /* Memory Exception Handler. */ + .global MemManage_Handler + .global BusFault_Handler + .global UsageFault_Handler + .thumb_func +MemManage_Handler: + .thumb_func +BusFault_Handler: + .thumb_func +UsageFault_Handler: + + CPSID i // Disable interrupts + + /* Now pickup and store all the fault related information. */ + + LDR r12,=_txm_module_manager_memory_fault_info // Pickup fault info struct + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r0] // Pickup the current thread pointer + STR r1, [r12, #0] // Save current thread pointer in fault info structure + LDR r0, =0xE000ED24 // Build SHCSR address + LDR r1, [r0] // Pickup SHCSR + STR r1, [r12, #8] // Save SHCSR + LDR r0, =0xE000ED28 // Build CFSR address + LDR r1, [r0] // Pickup CFSR + STR r1, [r12, #12] // Save CFSR + LDR r0, =0xE000ED34 // Build MMFAR address + LDR r1, [r0] // Pickup MMFAR + STR r1, [r12, #16] // Save MMFAR + LDR r0, =0xE000ED38 // Build BFAR address + LDR r1, [r0] // Pickup BFAR + STR r1, [r12, #20] // Save BFAR + MRS r0, CONTROL // Pickup current CONTROL register + STR r0, [r12, #24] // Save CONTROL + MRS r1, PSP // Pickup thread stack pointer + STR r1, [r12, #28] // Save thread stack pointer + LDR r0, [r1] // Pickup saved r0 + STR r0, [r12, #32] // Save r0 + LDR r0, [r1, #4] // Pickup saved r1 + STR r0, [r12, #36] // Save r1 + STR r2, [r12, #40] // Save r2 + STR r3, [r12, #44] // Save r3 + STR r4, [r12, #48] // Save r4 + STR r5, [r12, #52] // Save r5 + STR r6, [r12, #56] // Save r6 + STR r7, [r12, #60] // Save r7 + STR r8, [r12, #64] // Save r8 + STR r9, [r12, #68] // Save r9 + STR r10,[r12, #72] // Save r10 + STR r11,[r12, #76] // Save r11 + LDR r0, [r1, #16] // Pickup saved r12 + STR r0, [r12, #80] // Save r12 + LDR r0, [r1, #20] // Pickup saved lr + STR r0, [r12, #84] // Save lr + LDR r0, [r1, #24] // Pickup instruction address at point of fault + STR r0, [r12, #4] // Save point of fault + LDR r0, [r1, #28] // Pickup xPSR + STR r0, [r12, #88] // Save xPSR + + MRS r0, CONTROL // Pickup current CONTROL register + BIC r0, r0, #1 // Clear the UNPRIV bit + MSR CONTROL, r0 // Setup new CONTROL register + + LDR r0, =0xE000ED28 // Build the Memory Management Fault Status Register (MMFSR) + LDRB r1, [r0] // Pickup the MMFSR, with the following bit definitions: + // Bit 0 = 1 -> Instruction address violation + // Bit 1 = 1 -> Load/store address violation + // Bit 7 = 1 -> MMFAR is valid + STRB r1, [r0] // Clear the MMFSR + +#ifdef __ARMVFP__ + LDR r0, =0xE000EF34 // Cleanup FPU context: Load FPCCR address + LDR r1, [r0] // Load FPCCR + BIC r1, r1, #1 // Clear the lazy preservation active bit + STR r1, [r0] // Store the value +#endif + + BL _txm_module_manager_memory_fault_handler // Call memory manager fault handler + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread exit function to indicate the thread is no longer executing. */ + + CPSID i // Disable interrupts + BL _tx_execution_thread_exit // Call the thread exit function + CPSIE i // Enable interrupts +#endif + + MOV r1, #0 // Build NULL value + LDR r0, =_tx_thread_current_ptr // Pickup address of current thread pointer + STR r1, [r0] // Clear current thread pointer + + // Return from MemManage_Handler exception + LDR r0, =0xE000ED04 // Load ICSR + LDR r1, =0x10000000 // Set PENDSVSET bit + STR r1, [r0] // Store ICSR + DSB // Wait for memory access to complete + CPSIE i // Enable interrupts + MOV lr, #0xFFFFFFFD // Load exception return code + BX lr // Return from exception + + + /* Generic context PendSV handler. */ + + .global PendSV_Handler + .global __tx_PendSVHandler + .syntax unified + .thumb_func +PendSV_Handler: + .thumb_func +__tx_PendSVHandler: + + /* Get current thread value and new thread pointer. */ + +__tx_ts_handler: + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread exit function to indicate the thread is no longer executing. */ + + CPSID i // Disable interrupts + PUSH {r0, lr} // Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit // Call the thread exit function + POP {r0, lr} // Recover LR + CPSIE i // Enable interrupts +#endif + + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address + MOV r3, #0 // Build NULL value + LDR r1, [r0] // Pickup current thread pointer + + /* Determine if there is a current thread to finish preserving. */ + + CBZ r1, __tx_ts_new // If NULL, skip preservation + + /* Recover PSP and preserve current thread context. */ + + STR r3, [r0] // Set _tx_thread_current_ptr to NULL + MRS r12, PSP // Pickup PSP pointer (thread's stack pointer) + STMDB r12!, {r4-r11} // Save its remaining registers +#ifdef __ARMVFP__ + TST LR, #0x10 // Determine if the VFP extended frame is present + BNE _skip_vfp_save + VSTMDB r12!,{s16-s31} // Yes, save additional VFP registers +_skip_vfp_save: +#endif + LDR r4, =_tx_timer_time_slice // Build address of time-slice variable + STMDB r12!, {LR} // Save LR on the stack + + /* Determine if time-slice is active. If it isn't, skip time handling processing. */ + + LDR r5, [r4] // Pickup current time-slice + STR r12, [r1, #8] // Save the thread stack pointer + CBZ r5, __tx_ts_new // If not active, skip processing + + /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ + + STR r5, [r1, #24] // Save current time-slice + + /* Clear the global time-slice. */ + + STR r3, [r4] // Clear time-slice + + /* Executing thread is now completely preserved!!! */ + +__tx_ts_new: + + /* Now we are looking for a new thread to execute! */ + + CPSID i // Disable interrupts + LDR r1, [r2] // Is there another thread ready to execute? + CBZ r1, __tx_ts_wait // No, skip to the wait processing + + /* Yes, another thread is ready for else, make the current thread the new thread. */ + + STR r1, [r0] // Setup the current thread pointer to the new thread + CPSIE i // Enable interrupts + + /* Increment the thread run count. */ + +__tx_ts_restore: + LDR r7, [r1, #4] // Pickup the current thread run count + LDR r4, =_tx_timer_time_slice // Build address of time-slice variable + LDR r5, [r1, #24] // Pickup thread's current time-slice + ADD r7, r7, #1 // Increment the thread run count + STR r7, [r1, #4] // Store the new run count + + /* Setup global time-slice with thread's current time-slice. */ + + STR r5, [r4] // Setup global time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread entry function to indicate the thread is executing. */ + + PUSH {r0, r1} // Save r0 and r1 + BL _tx_execution_thread_enter // Call the thread execution enter function + POP {r0, r1} // Recover r0 and r1 +#endif + + /* Restore the thread context and PSP. */ + + LDR r12, [r1, #8] // Pickup thread's stack pointer + + MRS r5, CONTROL // Pickup current CONTROL register + LDR r4, [r1, #0x98] // Pickup current user mode flag + BIC r5, r5, #1 // Clear the UNPRIV bit + ORR r4, r4, r5 // Build new CONTROL register + MSR CONTROL, r4 // Setup new CONTROL register + + LDR r0, =0xE000ED94 // Build MPU control reg address + MOV r3, #0 // Build disable value + STR r3, [r0] // Disable MPU + LDR r0, [r1, #0x90] // Pickup the module instance pointer + CBZ r0, skip_mpu_setup // Is this thread owned by a module? No, skip MPU setup + LDR r1, [r0, #0x64] // Pickup MPU register[0] + CBZ r1, skip_mpu_setup // Is protection required for this module? No, skip MPU setup + LDR r1, =0xE000ED9C // Build address of MPU base register + + // Use alias registers to quickly load MPU + ADD r0, r0, #100 // Build address of MPU register start in thread control block + LDM r0!,{r2-r9} // Load first four MPU regions + STM r1,{r2-r9} // Store first four MPU regions + LDM r0,{r2-r9} // Load second four MPU regions + STM r1,{r2-r9} // Store second four MPU regions + LDR r0, =0xE000ED94 // Build MPU control reg address + MOV r1, #5 // Build enable value with background region enabled + STR r1, [r0] // Enable MPU +skip_mpu_setup: + LDMIA r12!, {LR} // Pickup LR +#ifdef __ARMVFP__ + TST LR, #0x10 // Determine if the VFP extended frame is present + BNE _skip_vfp_restore // If not, skip VFP restore + VLDMIA r12!, {s16-s31} // Yes, restore additional VFP registers +_skip_vfp_restore: +#endif + LDMIA r12!, {r4-r11} // Recover thread's registers + MSR PSP, r12 // Setup the thread's stack pointer + + /* Return to thread. */ + + BX lr // Return to thread! + + /* The following is the idle wait processing... in this case, no threads are ready for execution and the + system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts + are disabled to allow use of WFI for waiting for a thread to arrive. */ + +__tx_ts_wait: + CPSID i // Disable interrupts + LDR r1, [r2] // Pickup the next thread to execute pointer + STR r1, [r0] // Store it in the current pointer + CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! +#ifdef TX_ENABLE_WFI + DSB // Ensure no outstanding memory transactions + WFI // Wait for interrupt + ISB // Ensure pipeline is flushed +#endif + CPSIE i // Enable interrupts + B __tx_ts_wait // Loop to continue waiting + + /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are + already in the handler! */ + +__tx_ts_ready: + MOV r7, #0x08000000 // Build clear PendSV value + MOV r8, #0xE000E000 // Build base NVIC address + STR r7, [r8, #0xD04] // Clear any PendSV + + /* Re-enable interrupts and restore new thread. */ + + CPSIE i // Enable interrupts + B __tx_ts_restore // Restore the thread + + + /* SVC Handler. */ + + .global SVC_Handler + .global __tx_SVCallHandler + .syntax unified + .thumb_func +SVC_Handler: + .thumb_func +__tx_SVCallHandler: + + MRS r0, PSP // Pickup the PSP stack + LDR r1, [r0, #24] // Pickup the point of interrupt + LDRB r2, [r1, #-2] // Pickup the SVC parameter + + /* Determine which SVC trap we are processing */ + + CMP r2, #1 // Is it the entry into ThreadX? + BNE _tx_thread_user_return // No, return to user mode + + /* At this point we have an SVC 1, which means we are entering + the kernel from a module thread with user mode selected. */ + + LDR r2, =_txm_module_priv // Load address of where we should have come from + CMP r1, r2 // Did we come from user_mode_entry? + IT NE // If no (not equal), then... + BXNE lr // return from where we came. + + LDR r3, [r0, #20] // This is the saved LR + LDR r1, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, [r1] // Pickup current thread pointer + MOV r1, #0 // Build clear value + STR r1, [r2, #0x98] // Clear the current user mode selection for thread + STR r3, [r2, #0xA0] // Save the original LR in thread control block + + /* If there is memory protection, use kernel stack */ + LDR r0, [r2, #0x90] // Load the module instance ptr + LDR r0, [r0, #0x0C] // Load the module property flags + TST r0, #2 // Check if memory protected + BEQ _tx_skip_kernel_stack_enter + + /* Switch to the module thread's kernel stack */ + LDR r0, [r2, #0xA8] // Load the module kernel stack end +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + LDR r1, [r2, #0xA4] // Load the module kernel stack start + LDR r3, [r2, #0xAC] // Load the module kernel stack size + STR r1, [r2, #12] // Set stack start + STR r0, [r2, #16] // Set stack end + STR r3, [r2, #20] // Set stack size +#endif + + MRS r3, PSP // Pickup thread stack pointer + STR r3, [r2, #0xB0] // Save thread stack pointer + + /* Build kernel stack by copying thread stack two registers at a time */ + ADD r3, r3, #32 // Start at bottom of hardware stack + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + + MSR PSP, r0 // Set kernel stack pointer + +_tx_skip_kernel_stack_enter: + MRS r0, CONTROL // Pickup current CONTROL register + BIC r0, r0, #1 // Clear the UNPRIV bit + MSR CONTROL, r0 // Setup new CONTROL register + BX lr // Return to thread + +_tx_thread_user_return: + LDR r2, =_txm_module_user_mode_exit // Load address of where we should have come from + CMP r1, r2 // Did we come from user_mode_exit? + IT NE // If no (not equal), then... + BXNE lr // return from where we came + + LDR r1, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, [r1] // Pickup current thread pointer + LDR r1, [r2, #0x9C] // Pick up user mode + STR r1, [r2, #0x98] // Set the current user mode selection for thread + + /* If there is memory protection, use kernel stack */ + LDR r0, [r2, #0x90] // Load the module instance ptr + LDR r0, [r0, #0x0C] // Load the module property flags + TST r0, #2 // Check if memory protected + BEQ _tx_skip_kernel_stack_exit + +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + LDR r0, [r2, #0xB4] // Load the module thread stack start + LDR r1, [r2, #0xB8] // Load the module thread stack end + LDR r3, [r2, #0xBC] // Load the module thread stack size + STR r0, [r2, #12] // Set stack start + STR r1, [r2, #16] // Set stack end + STR r3, [r2, #20] // Set stack size +#endif + LDR r0, [r2, #0xB0] // Load the module thread stack pointer + MRS r3, PSP // Pickup kernel stack pointer + + /* Copy kernel hardware stack to module thread stack. */ + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + SUB r0, r0, #32 // Subtract 32 to get back to top of stack + MSR PSP, r0 // Set thread stack pointer + + LDR r1, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, [r1] // Pickup current thread pointer + LDR r1, [r2, #0x9C] // Pick up user mode + +_tx_skip_kernel_stack_exit: + MRS r0, CONTROL // Pickup current CONTROL register + ORR r0, r0, r1 // OR in the user mode bit + MSR CONTROL, r0 // Setup new CONTROL register + BX lr // Return to thread + + + /* Kernel entry function from user mode. */ + + .global _txm_module_manager_kernel_dispatch + .align 5 + .syntax unified +// VOID _txm_module_manager_user_mode_entry(VOID) +// { + .global _txm_module_manager_user_mode_entry + .thumb_func +_txm_module_manager_user_mode_entry: + SVC 1 // Enter kernel +_txm_module_priv: + /* At this point, we are out of user mode. The original LR has been saved in the + thread control block. Simply call the kernel dispatch function. */ + BL _txm_module_manager_kernel_dispatch + + /* Pickup the original LR value while still in privileged mode */ + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r3, [r2] // Pickup current thread pointer + LDR lr, [r3, #0xA0] // Pickup saved LR from original call + + SVC 2 // Exit kernel and return to user mode +_txm_module_user_mode_exit: + BX lr // Return to the caller + NOP + NOP + NOP + NOP +// } diff --git a/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_stack_build.S new file mode 100644 index 00000000..91e51381 --- /dev/null +++ b/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_stack_build.S @@ -0,0 +1,135 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ + .text + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_stack_build Cortex-M4/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function builds a stack frame on the supplied thread's stack. */ +@/* The stack frame results in a fake interrupt return to the supplied */ +@/* function pointer. */ +@/* */ +@/* INPUT */ +@/* */ +@/* thread_ptr Pointer to thread control blk */ +@/* function_ptr Pointer to return function */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_thread_create Create thread service */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +@{ + .global _tx_thread_stack_build + .thumb_func +_tx_thread_stack_build: +@ +@ +@ /* Build a fake interrupt frame. The form of the fake interrupt stack +@ on the Cortex-M4 should look like the following after it is built: +@ +@ Stack Top: +@ LR Interrupted LR (LR at time of PENDSV) +@ r4 Initial value for r4 +@ r5 Initial value for r5 +@ r6 Initial value for r6 +@ r7 Initial value for r7 +@ r8 Initial value for r8 +@ r9 Initial value for r9 +@ r10 Initial value for r10 +@ r11 Initial value for r11 +@ r0 Initial value for r0 (Hardware stack starts here!!) +@ r1 Initial value for r1 +@ r2 Initial value for r2 +@ r3 Initial value for r3 +@ r12 Initial value for r12 +@ lr Initial value for lr +@ pc Initial value for pc +@ xPSR Initial value for xPSR +@ +@ Stack Bottom: (higher memory address) */ +@ + LDR r2, [r0, #16] @ Pickup end of stack area + BIC r2, r2, #0x7 @ Align frame + SUB r2, r2, #68 @ Subtract frame size + LDR r3, =0xFFFFFFFD @ Build initial LR value + STR r3, [r2, #0] @ Save on the stack +@ +@ /* Actually build the stack frame. */ +@ + MOV r3, #0 @ Build initial register value + STR r3, [r2, #4] @ Store initial r4 + STR r3, [r2, #8] @ Store initial r5 + STR r3, [r2, #12] @ Store initial r6 + STR r3, [r2, #16] @ Store initial r7 + STR r3, [r2, #20] @ Store initial r8 + STR r3, [r2, #24] @ Store initial r9 + STR r3, [r2, #28] @ Store initial r10 + STR r3, [r2, #32] @ Store initial r11 +@ +@ /* Hardware stack follows. */ +@ + STR r3, [r2, #36] @ Store initial r0 + STR r3, [r2, #40] @ Store initial r1 + STR r3, [r2, #44] @ Store initial r2 + STR r3, [r2, #48] @ Store initial r3 + STR r3, [r2, #52] @ Store initial r12 + MOV r3, #0xFFFFFFFF @ Poison EXC_RETURN value + STR r3, [r2, #56] @ Store initial lr + STR r1, [r2, #60] @ Store initial pc + MOV r3, #0x01000000 @ Only T-bit need be set + STR r3, [r2, #64] @ Store initial xPSR +@ +@ /* Setup stack pointer. */ +@ thread_ptr -> tx_thread_stack_ptr = r2; +@ + STR r2, [r0, #8] @ Save stack pointer in thread's + @ control block + BX lr @ Return to caller +@} diff --git a/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_system_return.S b/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_system_return.S new file mode 100644 index 00000000..32601837 --- /dev/null +++ b/ports_module/cortex-m4/gnu/module_manager/src/tx_thread_system_return.S @@ -0,0 +1,88 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ + + + .text 32 + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_system_return Cortex-M4/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is target processor specific. It is used to transfer */ +@/* control from a thread back to the ThreadX system. Only a */ +@/* minimal context is saved since the compiler assumes temp registers */ +@/* are going to get slicked by a function call anyway. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling loop */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX components */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@/* VOID _tx_thread_system_return(VOID) +@{ */ + .thumb_func + .global _tx_thread_system_return +_tx_thread_system_return: +@ +@ /* Return to real scheduler via PendSV. Note that this routine is often +@ replaced with in-line assembly in tx_port.h to improved performance. */ +@ + MOV r0, #0x10000000 @ Load PENDSVSET bit + MOV r1, #0xE000E000 @ Load NVIC base + STR r0, [r1, #0xD04] @ Set PENDSVBIT in ICSR + MRS r0, IPSR @ Pickup IPSR + CMP r0, #0 @ Is it a thread returning? + BNE _isr_context @ If ISR, skip interrupt enable + MRS r1, PRIMASK @ Thread context returning, pickup PRIMASK + CPSIE i @ Enable interrupts + MSR PRIMASK, r1 @ Restore original interrupt posture +_isr_context: + BX lr @ Return to caller + +@/* } */ diff --git a/ports_module/cortex-m4/gnu/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex-m4/gnu/module_manager/src/tx_timer_interrupt.S new file mode 100644 index 00000000..0691e893 --- /dev/null +++ b/ports_module/cortex-m4/gnu/module_manager/src/tx_timer_interrupt.S @@ -0,0 +1,257 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Timer */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ + .global _tx_timer_time_slice + .global _tx_timer_system_clock + .global _tx_timer_current_ptr + .global _tx_timer_list_start + .global _tx_timer_list_end + .global _tx_timer_expired_time_slice + .global _tx_timer_expired + .global _tx_thread_time_slice + .global _tx_timer_expiration_process +@ +@ + .text + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_timer_interrupt Cortex-M4/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function processes the hardware timer interrupt. This */ +@/* processing includes incrementing the system clock and checking for */ +@/* time slice and/or timer expiration. If either is found, the */ +@/* interrupt context save/restore functions are called along with the */ +@/* expiration functions. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_timer_expiration_process Timer expiration processing */ +@/* _tx_thread_time_slice Time slice interrupted thread */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* interrupt vector */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_timer_interrupt(VOID) +@{ + .global _tx_timer_interrupt + .thumb_func +_tx_timer_interrupt: +@ +@ /* Upon entry to this routine, it is assumed that context save has already +@ been called, and therefore the compiler scratch registers are available +@ for use. */ +@ +@ /* Increment the system clock. */ +@ _tx_timer_system_clock++; +@ + LDR r1, =_tx_timer_system_clock @ Pickup address of system clock + LDR r0, [r1, #0] @ Pickup system clock + ADD r0, r0, #1 @ Increment system clock + STR r0, [r1, #0] @ Store new system clock +@ +@ /* Test for time-slice expiration. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice + LDR r2, [r3, #0] @ Pickup time-slice + CMP r2, #0 @ Is it non-active? + BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing +@ +@ /* Decrement the time_slice. */ +@ _tx_timer_time_slice--; +@ + SUB r2, r2, #1 @ Decrement the time-slice + STR r2, [r3, #0] @ Store new time-slice value +@ +@ /* Check for expiration. */ +@ if (__tx_timer_time_slice == 0) +@ + CMP r2, #0 @ Has it expired? + BNE __tx_timer_no_time_slice @ No, skip expiration processing +@ +@ /* Set the time-slice expired flag. */ +@ _tx_timer_expired_time_slice = TX_TRUE; +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of expired flag + MOV r0, #1 @ Build expired value + STR r0, [r3, #0] @ Set time-slice expiration flag +@ +@ } +@ +__tx_timer_no_time_slice: +@ +@ /* Test for timer expiration. */ +@ if (*_tx_timer_current_ptr) +@ { +@ + LDR r1, =_tx_timer_current_ptr @ Pickup current timer pointer address + LDR r0, [r1, #0] @ Pickup current timer + LDR r2, [r0, #0] @ Pickup timer list entry + CMP r2, #0 @ Is there anything in the list? + BEQ __tx_timer_no_timer @ No, just increment the timer +@ +@ /* Set expiration flag. */ +@ _tx_timer_expired = TX_TRUE; +@ + LDR r3, =_tx_timer_expired @ Pickup expiration flag address + MOV r2, #1 @ Build expired value + STR r2, [r3, #0] @ Set expired flag + B __tx_timer_done @ Finished timer processing +@ +@ } +@ else +@ { +__tx_timer_no_timer: +@ +@ /* No timer expired, increment the timer pointer. */ +@ _tx_timer_current_ptr++; +@ + ADD r0, r0, #4 @ Move to next timer +@ +@ /* Check for wrap-around. */ +@ if (_tx_timer_current_ptr == _tx_timer_list_end) +@ + LDR r3, =_tx_timer_list_end @ Pickup addr of timer list end + LDR r2, [r3, #0] @ Pickup list end + CMP r0, r2 @ Are we at list end? + BNE __tx_timer_skip_wrap @ No, skip wrap-around logic +@ +@ /* Wrap to beginning of list. */ +@ _tx_timer_current_ptr = _tx_timer_list_start; +@ + LDR r3, =_tx_timer_list_start @ Pickup addr of timer list start + LDR r0, [r3, #0] @ Set current pointer to list start +@ +__tx_timer_skip_wrap: +@ + STR r0, [r1, #0] @ Store new current timer pointer +@ } +@ +__tx_timer_done: +@ +@ +@ /* See if anything has expired. */ +@ if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +@ { +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of expired flag + LDR r2, [r3, #0] @ Pickup time-slice expired flag + CMP r2, #0 @ Did a time-slice expire? + BNE __tx_something_expired @ If non-zero, time-slice expired + LDR r1, =_tx_timer_expired @ Pickup addr of other expired flag + LDR r0, [r1, #0] @ Pickup timer expired flag + CMP r0, #0 @ Did a timer expire? + BEQ __tx_timer_nothing_expired @ No, nothing expired +@ +__tx_something_expired: +@ +@ + STMDB sp!, {r0, lr} @ Save the lr register on the stack + @ and save r0 just to keep 8-byte alignment +@ +@ /* Did a timer expire? */ +@ if (_tx_timer_expired) +@ { +@ + LDR r1, =_tx_timer_expired @ Pickup addr of expired flag + LDR r0, [r1, #0] @ Pickup timer expired flag + CMP r0, #0 @ Check for timer expiration + BEQ __tx_timer_dont_activate @ If not set, skip timer activation +@ +@ /* Process timer expiration. */ +@ _tx_timer_expiration_process(); +@ + BL _tx_timer_expiration_process @ Call the timer expiration handling routine +@ +@ } +__tx_timer_dont_activate: +@ +@ /* Did time slice expire? */ +@ if (_tx_timer_expired_time_slice) +@ { +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired + LDR r2, [r3, #0] @ Pickup the actual flag + CMP r2, #0 @ See if the flag is set + BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing +@ +@ /* Time slice interrupted thread. */ +@ _tx_thread_time_slice(); +@ + BL _tx_thread_time_slice @ Call time-slice processing + LDR r0, =_tx_thread_preempt_disable @ Build address of preempt disable flag + LDR r1, [r0] @ Is the preempt disable flag set? + CBNZ r1, __tx_timer_skip_time_slice @ Yes, skip the PendSV logic + LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address + LDR r1, [r0] @ Pickup the current thread pointer + LDR r2, =_tx_thread_execute_ptr @ Build execute thread pointer address + LDR r3, [r2] @ Pickup the execute thread pointer + LDR r0, =0xE000ED04 @ Build address of control register + LDR r2, =0x10000000 @ Build value for PendSV bit + CMP r1, r3 @ Are they the same? + BEQ __tx_timer_skip_time_slice @ If the same, there was no time-slice performed + STR r2, [r0] @ Not the same, issue the PendSV for preemption +__tx_timer_skip_time_slice: +@ +@ } +@ +__tx_timer_not_ts_expiration: +@ + LDMIA sp!, {r0, lr} @ Recover lr register (r0 is just there for + @ the 8-byte stack alignment +@ +@ } +@ +__tx_timer_nothing_expired: + + DSB @ Complete all memory access + BX lr @ Return to caller +@ +@} diff --git a/ports_module/cortex-m4/gnu/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex-m4/gnu/module_manager/src/txm_module_manager_alignment_adjust.c new file mode 100644 index 00000000..7842572e --- /dev/null +++ b/ports_module/cortex-m4/gnu/module_manager/src/txm_module_manager_alignment_adjust.c @@ -0,0 +1,399 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_power_of_two_block_size Cortex-M4/MPU/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calculates a power of two size at or immediately above*/ +/* the input size and returns it to the caller. */ +/* */ +/* INPUT */ +/* */ +/* size Block size */ +/* */ +/* OUTPUT */ +/* */ +/* calculated size Rounded up to power of two */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_power_of_two_block_size(ULONG size) +{ + /* Check for 0 size. */ + if(size == 0) + return 0; + + /* Minimum MPU block size is 32. */ + if(size <= 32) + return 32; + + /* Bit twiddling trick to round to next high power of 2 + (if original size is power of 2, it will return original size. Perfect!) */ + size--; + size |= size >> 1; + size |= size >> 2; + size |= size >> 4; + size |= size >> 8; + size |= size >> 16; + size++; + + /* Return a power of 2 size at or above the input size. */ + return(size); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_alignment_adjust Cortex-M4/MPU/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function adjusts the alignment and size of the code and data */ +/* section for a given module implementation. */ +/* */ +/* INPUT */ +/* */ +/* module_preamble Pointer to module preamble */ +/* code_size Size of the code area (updated) */ +/* code_alignment Code area alignment (updated) */ +/* data_size Size of data area (updated) */ +/* data_alignment Data area alignment (updated) */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_power_of_two_block_size Calculate power of two size */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, + ULONG *code_size, + ULONG *code_alignment, + ULONG *data_size, + ULONG *data_alignment) +{ + +ULONG local_code_size; +ULONG local_code_alignment; +ULONG local_data_size; +ULONG local_data_alignment; +ULONG code_block_size; +ULONG data_block_size; +ULONG code_size_accum; +ULONG data_size_accum; + + /* Copy the input parameters into local variables for ease of use. */ + local_code_size = *code_size; + local_code_alignment = *code_alignment; + local_data_size = *data_size; + local_data_alignment = *data_alignment; + + + /* Test for external memory enabled in preamble. */ + if(module_preamble -> txm_module_preamble_property_flags & TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS) + { + /* External/shared memory enabled. TXM_MODULE_MANAGER_CODE_MPU_ENTRIES-1 code entries will be used. */ + if (local_code_size <= (32*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 32 is best. */ + code_block_size = 32; + } + else if (local_code_size <= (64*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 64 is best. */ + code_block_size = 64; + } + else if (local_code_size <= (128*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 128 is best. */ + code_block_size = 128; + } + else if (local_code_size <= (256*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 256 is best. */ + code_block_size = 256; + } + else if (local_code_size <= (512*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 512 is best. */ + code_block_size = 512; + } + else if (local_code_size <= (1024*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 1024 is best. */ + code_block_size = 1024; + } + else if (local_code_size <= (2048*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 2048 is best. */ + code_block_size = 2048; + } + else if (local_code_size <= (4096*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 4096 is best. */ + code_block_size = 4096; + } + else if (local_code_size <= (8192*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 8192 is best. */ + code_block_size = 8192; + } + else if (local_code_size <= (16384*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 16384 is best. */ + code_block_size = 16384; + } + else if (local_code_size <= (32768*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 32768 is best. */ + code_block_size = 32768; + } + else if (local_code_size <= (65536*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 65536 is best. */ + code_block_size = 65536; + } + else if (local_code_size <= (131072*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 131072 is best. */ + code_block_size = 131072; + } + else if (local_code_size <= (262144*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 262144 is best. */ + code_block_size = 262144; + } + else if (local_code_size <= (524288*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 524288 is best. */ + code_block_size = 524288; + } + else if (local_code_size <= (1048576*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 1048576 is best. */ + code_block_size = 1048576; + } + else if (local_code_size <= (2097152*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 2097152 is best. */ + code_block_size = 2097152; + } + else if (local_code_size <= (4194304*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 4194304 is best. */ + code_block_size = 4194304; + } + else + { + /* Just set block size to 32MB just to create an allocation error! */ + code_block_size = 33554432; + } + + /* Calculate the new code size. */ + local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); + + /* Determine if the code block size is greater than the current alignment. If so, use block size + as the alignment. */ + if (code_block_size > local_code_alignment) + local_code_alignment = code_block_size; + + } + else + { + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + local_code_alignment = _txm_power_of_two_block_size(local_code_size) >> 2; + code_size_accum = local_code_alignment + local_code_alignment; + code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); + code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); + local_code_size = code_size_accum; + } + + /* Determine the best data block size, which in our case is the minimal alignment. */ + if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 32 is best. */ + data_block_size = 32; + } + else if (local_data_size <= (64*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 64 is best. */ + data_block_size = 64; + } + else if (local_data_size <= (128*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 128 is best. */ + data_block_size = 128; + } + else if (local_data_size <= (256*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 256 is best. */ + data_block_size = 256; + } + else if (local_data_size <= (512*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 512 is best. */ + data_block_size = 512; + } + else if (local_data_size <= (1024*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 1024 is best. */ + data_block_size = 1024; + } + else if (local_data_size <= (2048*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 2048 is best. */ + data_block_size = 2048; + } + else if (local_data_size <= (4096*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 4096 is best. */ + data_block_size = 4096; + } + else if (local_data_size <= (8192*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 8192 is best. */ + data_block_size = 8192; + } + else if (local_data_size <= (16384*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 16384 is best. */ + data_block_size = 16384; + } + else if (local_data_size <= (32768*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 32768 is best. */ + data_block_size = 32768; + } + else if (local_data_size <= (65536*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 65536 is best. */ + data_block_size = 65536; + } + else if (local_data_size <= (131072*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 131072 is best. */ + data_block_size = 131072; + } + else if (local_data_size <= (262144*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 262144 is best. */ + data_block_size = 262144; + } + else if (local_data_size <= (524288*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 524288 is best. */ + data_block_size = 524288; + } + else if (local_data_size <= (1048576*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 1048576 is best. */ + data_block_size = 1048576; + } + else if (local_data_size <= (2097152*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 2097152 is best. */ + data_block_size = 2097152; + } + else if (local_data_size <= (4194304*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 4194304 is best. */ + data_block_size = 4194304; + } + else + { + /* Just set data block size to 32MB just to create an allocation error! */ + data_block_size = 33554432; + } + + /* Calculate the new data size. */ + data_size_accum = data_block_size; + while(data_size_accum < local_data_size) + { + data_size_accum += data_block_size; + } + local_data_size = data_size_accum; + + /* Determine if the data block size is greater than the current alignment. If so, use block size + as the alignment. */ + if (data_block_size > local_data_alignment) + { + local_data_alignment = data_block_size; + } + + /* Return all the information to the caller. */ + *code_size = local_code_size; + *code_alignment = local_code_alignment; + *data_size = local_data_size; + *data_alignment = local_data_alignment; +} diff --git a/ports_module/cortex-m4/gnu/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex-m4/gnu/module_manager/src/txm_module_manager_external_memory_enable.c new file mode 100644 index 00000000..22bc194f --- /dev/null +++ b/ports_module/cortex-m4/gnu/module_manager/src/txm_module_manager_external_memory_enable.c @@ -0,0 +1,182 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_mutex.h" +#include "tx_queue.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_external_memory_enable Cortex-M4/MPU/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates an entry in the MPU table for a shared */ +/* memory space. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* start_address Start address of memory */ +/* length Length of external memory */ +/* attributes Memory attributes (r/w) */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_mutex_get Get protection mutex */ +/* _tx_mutex_put Release protection mutex */ +/* _txm_power_of_two_block_size Round length to power of two */ +/* _txm_module_manager_mm_register_setup Reconfigure MPU registers */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, + VOID *start_address, + ULONG length, + UINT attributes) +{ + +ULONG block_size; +ULONG region_size; +ULONG subregion_bits; +ULONG address; +UINT attributes_check = 0; +TXM_MODULE_PREAMBLE *module_preamble; + + /* Determine if the module manager has not been initialized yet. */ + if (_txm_module_manager_ready != TX_TRUE) + { + /* Module manager has not been initialized. */ + return(TX_NOT_AVAILABLE); + } + + /* Determine if the module is valid. */ + if (module_instance == TX_NULL) + { + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Get module manager protection mutex. */ + _tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER); + + /* Determine if the module instance is valid. */ + if (module_instance -> txm_module_instance_id != TXM_MODULE_ID) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Determine if the module instance is in the loaded state. */ + if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if the module is not ready. */ + return(TX_START_ERROR); + } + + /* Check if preamble shared mem and mem protection property bits are set. */ + module_preamble = module_instance -> txm_module_instance_preamble_ptr; + if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) + != (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if bit not set. */ + return(TXM_MODULE_INVALID_PROPERTIES); + } + + /* Start address and length must adhere to Cortex-M MPU. + The address must align with the block size. */ + + block_size = _txm_power_of_two_block_size(length); + address = (ULONG) start_address; + if(address != (address & ~(block_size - 1))) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return alignment error. */ + return(TXM_MODULE_ALIGNMENT_ERROR); + } + + /* At this point, we have a valid address and block size. + Set up MPU registers. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | 0x10; + + /* Calculate the region size. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + /* Calculate the subregion bits. */ + subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); + + /* Check for valid attributes. */ + if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) + { + attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; + } + + /* Build register with attributes. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX+1] = region_size | subregion_bits | attributes_check | 0x12070001; + + /* Keep track of shared memory address and length in module instance. */ + module_instance -> txm_module_instance_shared_memory_address = address; + module_instance -> txm_module_instance_shared_memory_length = length; + + /* Recalculate MPU settings. */ + _txm_module_manager_mm_register_setup(module_instance); + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/ports_module/cortex-m4/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex-m4/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c new file mode 100644 index 00000000..c349ccc2 --- /dev/null +++ b/ports_module/cortex-m4/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -0,0 +1,110 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + +/* Define a macro that can be used to allocate global variables useful to + store information about the last fault. This macro is defined in + txm_module_port.h and is usually populated in the assembly language + fault handling prior to the code calling _txm_module_manager_memory_fault_handler. */ + +TXM_MODULE_MANAGER_FAULT_INFO + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_handler Cortex-M4/MPU/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles a fault associated with a memory protected */ +/* module. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_terminate Terminate thread */ +/* */ +/* CALLED BY */ +/* */ +/* Fault handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_memory_fault_handler(VOID) +{ + +TXM_MODULE_INSTANCE *module_instance_ptr; +TX_THREAD *thread_ptr; + + /* Pickup the current thread. */ + thread_ptr = _tx_thread_current_ptr; + + /* Initialize the module instance pointer to NULL. */ + module_instance_ptr = TX_NULL; + + /* Is there a thread? */ + if (thread_ptr) + { + /* Pickup the module instance. */ + module_instance_ptr = thread_ptr -> tx_thread_module_instance_ptr; + + /* Terminate the current thread. */ + _tx_thread_terminate(_tx_thread_current_ptr); + } + + /* Determine if there is a user memory fault notification callback. */ + if (_txm_module_manager_fault_notify) + { + /* Yes, call the user's notification memory fault callback. */ + (_txm_module_manager_fault_notify)(thread_ptr, module_instance_ptr); + } +} diff --git a/ports_module/cortex-m4/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex-m4/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c new file mode 100644 index 00000000..44f6f74b --- /dev/null +++ b/ports_module/cortex-m4/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -0,0 +1,84 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the external user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_notify Cortex-M4/MPU/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application callback when/if a memory */ +/* fault occurs. The supplied thread is automatically terminated, but */ +/* any other threads in the same module may still execute. */ +/* */ +/* INPUT */ +/* */ +/* notify_function Memory fault notification */ +/* function, NULL disables. */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +{ + /* Setup notification function. */ + _txm_module_manager_fault_notify = notify_function; + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/ports_module/cortex-m4/gnu/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex-m4/gnu/module_manager/src/txm_module_manager_mm_register_setup.c new file mode 100644 index 00000000..9869aa62 --- /dev/null +++ b/ports_module/cortex-m4/gnu/module_manager/src/txm_module_manager_mm_register_setup.c @@ -0,0 +1,512 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_region_size_get Cortex-M4/MPU/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function converts the region size in bytes to the block size */ +/* for the Cortex-M4 MPU specification. */ +/* */ +/* INPUT */ +/* */ +/* block_size Size of the block in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* MPU size specification */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_module_manager_region_size_get(ULONG block_size) +{ + +ULONG return_value; + + /* Process relative to the input block size. */ + if (block_size == 32) + { + return_value = 0x04; + } + else if (block_size == 64) + { + return_value = 0x05; + } + else if (block_size == 128) + { + return_value = 0x06; + } + else if (block_size == 256) + { + return_value = 0x07; + } + else if (block_size == 512) + { + return_value = 0x08; + } + else if (block_size == 1024) + { + return_value = 0x09; + } + else if (block_size == 2048) + { + return_value = 0x0A; + } + else if (block_size == 4096) + { + return_value = 0x0B; + } + else if (block_size == 8192) + { + return_value = 0x0C; + } + else if (block_size == 16384) + { + return_value = 0x0D; + } + else if (block_size == 32768) + { + return_value = 0x0E; + } + else if (block_size == 65536) + { + return_value = 0x0F; + } + else if (block_size == 131072) + { + return_value = 0x10; + } + else if (block_size == 262144) + { + return_value = 0x11; + } + else if (block_size == 524288) + { + return_value = 0x12; + } + else if (block_size == 1048576) + { + return_value = 0x13; + } + else if (block_size == 2097152) + { + return_value = 0x14; + } + else + { + /* Max 4MB MPU pages for modules. */ + return_value = 0x15; + } + + return(return_value); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_calculate_srd_bits Cortex-M4/MPU/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calculates the SRD bits that need to be set to */ +/* protect "length" bytes in a block. */ +/* */ +/* INPUT */ +/* */ +/* block_size Size of the block in bytes */ +/* length Actual length in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* SRD bits to be OR'ed with region attribute register. */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) +{ + +ULONG srd_bits = 0; +UINT srd_bit_index; + + /* length is smaller than block_size, set SRD bits if block_size is 256 or more. */ + if((block_size >= 256) && (length < block_size)) + { + /* Divide block_size by 8 by shifting right 3. Result is size of subregion. */ + block_size = block_size >> 3; + + /* Set SRD index into attribute register. */ + srd_bit_index = 8; + + /* If subregion overlaps length, move to the next subregion. */ + while(length > block_size) + { + length = length - block_size; + srd_bit_index++; + } + /* Check for a portion of code remaining. */ + if(length) + { + srd_bit_index++; + } + + /* Set unused subregion bits. */ + while(srd_bit_index < 16) + { + srd_bits = srd_bits | (0x1 << srd_bit_index); + srd_bit_index++; + } + } + + return(srd_bits); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_mm_register_setup Cortex-M4/MPU/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets up the Cortex-M4 MPU register definitions based */ +/* on the module's memory characteristics. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* */ +/* OUTPUT */ +/* */ +/* MPU specifications for module in module_instance */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_manager_region_size_get */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_thread_create */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) +{ + +ULONG code_address; +ULONG code_size; +ULONG data_address; +ULONG data_size; +ULONG start_stop_stack_size; +ULONG callback_stack_size; +ULONG block_size; +ULONG base_address_register; +ULONG base_attribute_register; +ULONG region_size; +ULONG srd_bits = 0; +UINT mpu_register = 0; +UINT mpu_table_index; +UINT i; + + + /* Setup the first region for the ThreadX trampoline code. */ + /* Set base register to user mode entry, which is guaranteed to be at least 32-byte aligned. */ + base_address_register = (ULONG) _txm_module_manager_user_mode_entry; + + /* Mask address to proper range, region 0, set Valid bit. */ + base_address_register = (base_address_register & 0xFFFFFFE0) | mpu_register | 0x10; + module_instance -> txm_module_instance_mpu_registers[0] = base_address_register; + + /* Attributes: read only, write-back, shareable, size 32 bytes, region enabled. */ + module_instance -> txm_module_instance_mpu_registers[1] = 0x06070009; + + /* Initialize the MPU register. */ + mpu_register = 1; + + /* Initialize the MPU table index. */ + mpu_table_index = 2; + + /* Setup values for code area. */ + code_address = (ULONG) module_instance -> txm_module_instance_code_start; + code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; + + /* Check if shared memory was set up. If so, only 3 entries are available for + code protection. If not set up, 4 code entries are available. */ + if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] == 0) + { + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + + /* Now loop through to setup MPU protection for the code area. */ + for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES; i++) + { + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + if (i < 2) + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + } + + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ + else if (i == 2) + { + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size) >> 1; + } + + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + else + { + /* Calculate remaining space. */ + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + + /* Build the base address register. */ + base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Build the base attribute register. */ + base_attribute_register = region_size | srd_bits | 0x06070001; + + /* Setup the MPU Base Address Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; + + /* Setup the MPU Base Attribute Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; + + /* Adjust the code address. */ + code_address = code_address + block_size; + + /* Move MPU table index. */ + mpu_table_index = mpu_table_index + 2; + + /* Increment the MPU register index. */ + mpu_register++; + } + } + + /* Only 3 code entries available. */ + else + { + /* Calculate block size, one code entry taken up by shared memory. */ + block_size = _txm_power_of_two_block_size(code_size / (TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)); + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Now loop through to setup MPU protection for the code area. */ + for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) + { + /* Build the base address register. */ + base_address_register = code_address & ~(block_size - 1) | mpu_register | 0x10; + + /* Check if SRD bits need to be set. */ + if (code_size < block_size) + { + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + + /* Build the base attribute register. */ + base_attribute_register = region_size | srd_bits | 0x06070000; + + /* Is there still some code? If so set the region enable bit. */ + if (code_size) + { + /* Set the region enable bit. */ + base_attribute_register = base_attribute_register | 0x1; + } + /* Setup the MPU Base Address Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; + + /* Setup the MPU Base Attribute Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; + + /* Adjust the code address. */ + code_address = code_address + block_size; + + /* Decrement the code size. */ + if (code_size > block_size) + { + code_size = code_size - block_size; + } + else + { + code_size = 0; + } + + /* Move MPU table index. */ + mpu_table_index = mpu_table_index + 2; + + /* Increment the MPU register index. */ + mpu_register++; + } + + /* Adjust indeces to pass over the shared memory entry. */ + /* Move MPU table index. */ + mpu_table_index = mpu_table_index + 2; + + /* Increment the MPU register index. */ + mpu_register++; + } + + /* Setup values for data area. */ + data_address = (ULONG) module_instance -> txm_module_instance_data_start; + + /* Adjust the size of the module elements to be aligned to the default alignment. We do this + so that when we partition the allocated memory, we can simply place these regions right beside + each other without having to align their pointers. Note this only works when they all have + the same alignment. */ + + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; + start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; + callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; + + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + /* Update the data size to include thread stacks. */ + data_size = data_size + start_stop_stack_size + callback_stack_size; + + block_size = _txm_power_of_two_block_size(data_size / TXM_MODULE_MANAGER_DATA_MPU_ENTRIES); + + /* Reset SRD bitfield. */ + srd_bits = 0; + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Now loop through to setup MPU protection for the data area. */ + for (i = 0; i < TXM_MODULE_MANAGER_DATA_MPU_ENTRIES; i++) + { + /* Build the base address register. */ + base_address_register = (data_address & ~(block_size - 1)) | mpu_register | 0x10; + + /* Check if SRD bits need to be set. */ + if (data_size < block_size) + { + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + } + + /* Build the base attribute register. */ + base_attribute_register = region_size | srd_bits | 0x13070000; + + /* Is there still some data? If so set the region enable bit. */ + if (data_size) + { + /* Set the region enable bit. */ + base_attribute_register = base_attribute_register | 0x1; + } + + /* Setup the MPU Base Address Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; + + /* Setup the MPU Base Attribute Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; + + /* Adjust the data address. */ + data_address = data_address + block_size; + + /* Decrement the data size. */ + if (data_size > block_size) + { + data_size = data_size - block_size; + } + else + { + data_size = 0; + } + + /* Move MPU table index. */ + mpu_table_index = mpu_table_index + 2; + + /* Increment the MPU register index. */ + mpu_register++; + } +} diff --git a/ports_module/cortex-m4/gnu/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex-m4/gnu/module_manager/src/txm_module_manager_thread_stack_build.s new file mode 100644 index 00000000..62f8f7d3 --- /dev/null +++ b/ports_module/cortex-m4/gnu/module_manager/src/txm_module_manager_thread_stack_build.s @@ -0,0 +1,139 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .align 4 + .syntax unified + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_thread_stack_build Cortex-M4/MPU/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread */ +/* function_ptr Pointer to shell function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +// { + .global _txm_module_manager_thread_stack_build + .thumb_func +_txm_module_manager_thread_stack_build: + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-M should look like the following after it is built: + + Stack Top: + LR Interrupted LR (LR at time of PENDSV) + r4 Initial value for r4 + r5 Initial value for r5 + r6 Initial value for r6 + r7 Initial value for r7 + r8 Initial value for r8 + r9 Initial value for r9 + r10 Initial value for r10 + r11 Initial value for r11 + r0 Initial value for r0 (Hardware stack starts here!!) + r1 Initial value for r1 + r2 Initial value for r2 + r3 Initial value for r3 + r12 Initial value for r12 + lr Initial value for lr + pc Initial value for pc + xPSR Initial value for xPSR + + Stack Bottom: (higher memory address) */ + + LDR r2, [r0, #16] // Pickup end of stack area + BIC r2, r2, #0x7 // Align frame + SUB r2, r2, #68 // Subtract frame size + LDR r3, =0xFFFFFFFD // Build initial LR value + STR r3, [r2, #0] // Save on the stack + + /* Actually build the stack frame. */ + + MOV r3, #0 // Build initial register value + STR r3, [r2, #4] // Store initial r4 + STR r3, [r2, #8] // Store initial r5 + STR r3, [r2, #12] // Store initial r6 + STR r3, [r2, #16] // Store initial r7 + STR r3, [r2, #20] // Store initial r8 + STR r3, [r2, #28] // Store initial r10 + STR r3, [r2, #32] // Store initial r11 + + /* Hardware stack follows. */ + + STR r0, [r2, #36] // Store initial r0, which is the thread control block + + LDR r3, [r0, #8] // Pickup thread entry info pointer,which is in the stack pointer position of the thread control block. + // It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this + // function with the actual, initial stack pointer. + STR r3, [r2, #40] // Store initial r1, which is the module entry information. + LDR r3, [r3, #8] // Pickup data base register from the module information + STR r3, [r2, #24] // Store initial r9 (data base register) + MOV r3, #0 // Clear r3 again + + STR r3, [r2, #44] // Store initial r2 + STR r3, [r2, #48] // Store initial r3 + STR r3, [r2, #52] // Store initial r12 + MOV r3, #0xFFFFFFFF // Poison EXC_RETURN value + STR r3, [r2, #56] // Store initial lr + STR r1, [r2, #60] // Store initial pc + MOV r3, #0x01000000 // Only T-bit need be set + STR r3, [r2, #64] // Store initial xPSR + + /* Setup stack pointer. */ + // thread_ptr -> tx_thread_stack_ptr = r2; + + STR r2, [r0, #8] // Save stack pointer in thread's control block + BX lr // Return to caller diff --git a/ports_module/cortex-m4/iar/example_build/sample_threadx.ewp b/ports_module/cortex-m4/iar/example_build/sample_threadx.ewp index 55896717..472b07aa 100644 --- a/ports_module/cortex-m4/iar/example_build/sample_threadx.ewp +++ b/ports_module/cortex-m4/iar/example_build/sample_threadx.ewp @@ -66,7 +66,7 @@ @@ -1176,7 +1176,7 @@ diff --git a/ports_module/cortex-m4/iar/example_build/tx_initialize_low_level.s b/ports_module/cortex-m4/iar/example_build/tx_initialize_low_level.s index c252a33f..3c1bff45 100644 --- a/ports_module/cortex-m4/iar/example_build/tx_initialize_low_level.s +++ b/ports_module/cortex-m4/iar/example_build/tx_initialize_low_level.s @@ -55,7 +55,7 @@ __tx_free_memory_start ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level Cortex-M4/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -88,7 +88,7 @@ __tx_free_memory_start ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports_module/cortex-m4/iar/example_build/txm.ewp b/ports_module/cortex-m4/iar/example_build/txm.ewp index 86ee626f..4f31ba9f 100644 --- a/ports_module/cortex-m4/iar/example_build/txm.ewp +++ b/ports_module/cortex-m4/iar/example_build/txm.ewp @@ -66,7 +66,7 @@ @@ -2165,13 +2165,13 @@ $PROJ_DIR$\..\..\..\..\common\inc\tx_user_sample.h - $PROJ_DIR$\..\..\..\..\common_modules\module_common\inc\txm_module.h + $PROJ_DIR$\..\..\..\..\common_modules\inc\txm_module.h - $PROJ_DIR$\..\module_common\inc\txm_module_port.h + $PROJ_DIR$\..\inc\txm_module_port.h - $PROJ_DIR$\..\..\..\..\common_modules\module_common\inc\txm_module_user.h + $PROJ_DIR$\..\..\..\..\common_modules\inc\txm_module_user.h diff --git a/ports_module/cortex-m4/iar/example_build/txm_module_preamble.s b/ports_module/cortex-m4/iar/example_build/txm_module_preamble.s index 81f6b250..5488df2a 100644 --- a/ports_module/cortex-m4/iar/example_build/txm_module_preamble.s +++ b/ports_module/cortex-m4/iar/example_build/txm_module_preamble.s @@ -1,7 +1,7 @@ SECTION .text:CODE - AAPCS INTERWORK, ROPI, RWPI_COMPATIBLE, VFP_COMPATIBLE - PRESERVE8 + AAPCS INTERWORK, ROPI, RWPI_COMPATIBLE, VFP_COMPATIBLE + PRESERVE8 /* Define public symbols. */ @@ -15,56 +15,55 @@ /* Define common external refrences. */ - EXTERN _txm_module_thread_shell_entry - EXTERN _txm_module_callback_request_thread_entry - EXTERN ROPI$$Length - EXTERN RWPI$$Length + EXTERN _txm_module_thread_shell_entry + EXTERN _txm_module_callback_request_thread_entry + EXTERN ROPI$$Length + EXTERN RWPI$$Length - DATA + DATA __txm_module_preamble: - DC32 0x4D4F4455 ; Module ID - DC32 0x5 ; Module Major Version - DC32 0x6 ; Module Minor Version - DC32 32 ; Module Preamble Size in 32-bit words - DC32 0x12345678 ; Module ID (application defined) - DC32 0x00000007 ; Module Properties where: - ; Bits 31-24: Compiler ID - ; 0 -> IAR - ; 1 -> RVDS - ; 2 -> GNU - ; Bit 0: 0 -> Privileged mode execution - ; 1 -> User mode execution - ; Bit 1: 0 -> No MPU protection - ; 1 -> MPU protection (must have user mode selected) - ; Bit 2: 0 -> Disable shared/external memory access - ; 1 -> Enable shared/external memory access - DC32 _txm_module_thread_shell_entry - . - 0 ; Module Shell Entry Point - DC32 demo_module_start - . - 0 ; Module Start Thread Entry Point - DC32 0 ; Module Stop Thread Entry Point - DC32 1 ; Module Start/Stop Thread Priority - DC32 1022 ; Module Start/Stop Thread Stack Size - DC32 _txm_module_callback_request_thread_entry - . - 0 ; Module Callback Thread Entry - DC32 1 ; Module Callback Thread Priority - DC32 1022 ; Module Callback Thread Stack Size - DC32 ROPI$$Length ; Module Code Size - DC32 RWPI$$Length ; Module Data Size - DC32 0 ; Reserved 0 - DC32 0 ; Reserved 1 - DC32 0 ; Reserved 2 - DC32 0 ; Reserved 3 - DC32 0 ; Reserved 4 - DC32 0 ; Reserved 5 - DC32 0 ; Reserved 6 - DC32 0 ; Reserved 7 - DC32 0 ; Reserved 8 - DC32 0 ; Reserved 9 - DC32 0 ; Reserved 10 - DC32 0 ; Reserved 11 - DC32 0 ; Reserved 12 - DC32 0 ; Reserved 13 - DC32 0 ; Reserved 14 - DC32 0 ; Reserved 15 - - END - + DC32 0x4D4F4455 ; Module ID + DC32 0x6 ; Module Major Version + DC32 0x1 ; Module Minor Version + DC32 32 ; Module Preamble Size in 32-bit words + DC32 0x12345678 ; Module ID (application defined) + DC32 0x00000007 ; Module Properties where: + ; Bits 31-24: Compiler ID + ; 0 -> IAR + ; 1 -> RVDS + ; 2 -> GNU + ; Bits 23-3: Reserved + ; Bit 2: 0 -> Disable shared/external memory access + ; 1 -> Enable shared/external memory access + ; Bit 1: 0 -> No MPU protection + ; 1 -> MPU protection (must have user mode selected - bit 0 set) + ; Bit 0: 0 -> Privileged mode execution + ; 1 -> User mode execution + DC32 _txm_module_thread_shell_entry - . - 0 ; Module Shell Entry Point + DC32 demo_module_start - . - 0 ; Module Start Thread Entry Point + DC32 0 ; Module Stop Thread Entry Point + DC32 1 ; Module Start/Stop Thread Priority + DC32 1024 ; Module Start/Stop Thread Stack Size + DC32 _txm_module_callback_request_thread_entry - . - 0 ; Module Callback Thread Entry + DC32 1 ; Module Callback Thread Priority + DC32 1024 ; Module Callback Thread Stack Size + DC32 ROPI$$Length ; Module Code Size + DC32 RWPI$$Length ; Module Data Size + DC32 0 ; Reserved 0 + DC32 0 ; Reserved 1 + DC32 0 ; Reserved 2 + DC32 0 ; Reserved 3 + DC32 0 ; Reserved 4 + DC32 0 ; Reserved 5 + DC32 0 ; Reserved 6 + DC32 0 ; Reserved 7 + DC32 0 ; Reserved 8 + DC32 0 ; Reserved 9 + DC32 0 ; Reserved 10 + DC32 0 ; Reserved 11 + DC32 0 ; Reserved 12 + DC32 0 ; Reserved 13 + DC32 0 ; Reserved 14 + DC32 0 ; Reserved 15 + END diff --git a/ports_module/cortex-m4/iar/inc/tx_port.h b/ports_module/cortex-m4/iar/inc/tx_port.h index b5f4e221..6d65baa5 100644 --- a/ports_module/cortex-m4/iar/inc/tx_port.h +++ b/ports_module/cortex-m4/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M4/IAR */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -117,7 +117,7 @@ typedef unsigned short USHORT; #endif -/* Define various constants for the ThreadX Cortex-M3 port. */ +/* Define various constants for the ThreadX ARM Cortex-M port. */ #define TX_INT_DISABLE 1 /* Disable interrupts */ #define TX_INT_ENABLE 0 /* Enable interrupts */ @@ -376,7 +376,7 @@ void _tx_misra_vfp_touch(void); #else #define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) -#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) #endif @@ -506,7 +506,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/IAR Version 6.0.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/IAR Version 6.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex-m4/iar/inc/txm_module_port.h b/ports_module/cortex-m4/iar/inc/txm_module_port.h index 5220e5b9..1ef45a55 100644 --- a/ports_module/cortex-m4/iar/inc/txm_module_port.h +++ b/ports_module/cortex-m4/iar/inc/txm_module_port.h @@ -10,37 +10,37 @@ /**************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ -/**************************************************************************/ -/* */ -/* APPLICATION INTERFACE DEFINITION RELEASE */ -/* */ -/* txm_module_port.h Cortex-M4/MPU/IAR */ -/* 6.0.1 */ +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* txm_module_port.h Cortex-M4/MPU/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This file defines the basic module constants, interface structures, */ -/* and function prototypes. */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the basic module constants, interface structures, */ +/* and function prototypes. */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -52,13 +52,13 @@ #ifdef TXM_MODULE_INCLUDE_USER_DEFINE_FILE -/* Yes, include the user defines in txm_module_user.h. The defines in this file may +/* Yes, include the user defines in txm_module_user.h. The defines in this file may alternately be defined on the command line. */ #include "txm_module_user.h" #endif -/* It is assumed that the base ThreadX tx_port.h file has been modified to add the +/* It is assumed that the base ThreadX tx_port.h file has been modified to add the following extensions to the ThreadX thread control block (this code should replace the corresponding macro define in tx_port.h): @@ -151,7 +151,7 @@ The following extensions must also be defined in tx_port.h: #define INLINE_DECLARE inline -/* Define the number of MPU entries assigned to the code and data sections. On Cortex-M parts, there can only be 7 total +/* Define the number of MPU entries assigned to the code and data sections. On Cortex-M parts, there can only be 7 total entries, since ThreadX uses one for access to the kernel dispatch function. */ #define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 @@ -205,9 +205,6 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT #define TXM_MODULE_MANAGER_FAULT_INFO \ TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info; -/* Define the macro to check the stack available in dispatch. */ -#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE - /* Define the macro to check the code alignment. */ #define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment) \ @@ -292,16 +289,16 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT #define TXM_MODULE_MANAGER_MODULE_UNLOAD(module_instance) -/* Define the macro to perform port-specific functions when passing function pointer to kernel. */ -/* Determine if the pointer is within the module's code memory. */ -#define TXM_MODULE_MANAGER_CHECK_FUNCTION_POINTER(module_instance, pointer) \ - if (((pointer < sizeof(TXM_MODULE_PREAMBLE) + (ULONG) module_instance -> txm_module_instance_code_start) || \ - ((pointer+sizeof(pointer)) > (ULONG) module_instance -> txm_module_instance_code_end)) \ - && (pointer != (ULONG) TX_NULL)) \ - { \ - return(TX_PTR_ERROR); \ - } +/* Define the macros to perform port-specific checks when passing pointers to the kernel. */ +/* Define macro to make sure object is inside the module's data. */ +#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ + /* Check if it's inside module data. */ \ + ((((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && \ + (((obj_ptr) + (obj_size)) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) || \ + /* Check if it's inside shared memory. */ \ + (((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address) && \ + (((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (module_instance -> txm_module_instance_shared_memory_address + module_instance -> txm_module_instance_shared_memory_length)))) /* Define some internal prototypes to this module port. */ @@ -311,21 +308,17 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT #endif -#define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES \ +#define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES \ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment); \ -VOID _txm_module_manager_memory_fault_handler(VOID); \ -UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)); \ -VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \ -ULONG _txm_power_of_two_block_size(ULONG size); \ -ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); \ -ULONG _txm_module_manager_region_size_get(ULONG block_size); \ -UCHAR _txm_module_manager_shared_memory_check_outside(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size); \ -UCHAR _txm_module_manager_shared_memory_check_inside(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size); \ -UCHAR _txm_module_manager_shared_memory_check_inside_byte(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr); +VOID _txm_module_manager_memory_fault_handler(VOID); \ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)); \ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \ +ULONG _txm_power_of_two_block_size(ULONG size); \ +ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); \ +ULONG _txm_module_manager_region_size_get(ULONG block_size); #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/MPU/IAR Version 6.0.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/MPU/IAR Version 6.1 *"; #endif - diff --git a/ports_module/cortex-m4/iar/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex-m4/iar/module_lib/src/txm_module_thread_shell_entry.c index 91fd4706..3525846e 100644 --- a/ports_module/cortex-m4/iar/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex-m4/iar/module_lib/src/txm_module_thread_shell_entry.c @@ -10,15 +10,15 @@ /**************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #ifndef TXM_MODULE #define TXM_MODULE @@ -44,54 +44,54 @@ TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3); -/* Define the IAR startup code that clears the uninitialized global data and sets up the +/* Define the IAR startup code that clears the uninitialized global data and sets up the preset global variables. */ extern VOID __iar_data_init3(VOID); -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_thread_shell_entry Cortex-M4/MPU/IAR */ -/* 6.0.1 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_thread_shell_entry Cortex-M4/MPU/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function calls the specified entry function of the thread. It */ -/* also provides a place for the thread's entry function to return. */ -/* If the thread returns, this function places the thread in a */ -/* "COMPLETED" state. */ -/* */ -/* INPUT */ -/* */ -/* thread_ptr Pointer to current thread */ -/* thread_info Pointer to thread entry info */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* __iar_data_init3 IAR global initialization function*/ -/* thread_entry Thread's entry function */ -/* tx_thread_resume Resume the module callback thread */ -/* _txm_module_thread_system_suspend Module thread suspension routine */ -/* */ -/* CALLED BY */ -/* */ -/* Initial thread stack frame */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function calls the specified entry function of the thread. It */ +/* also provides a place for the thread's entry function to return. */ +/* If the thread returns, this function places the thread in a */ +/* "COMPLETED" state. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to current thread */ +/* thread_info Pointer to thread entry info */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __iar_data_init3 IAR global initialization function*/ +/* thread_entry Thread's entry function */ +/* tx_thread_resume Resume the module callback thread */ +/* _txm_module_thread_system_suspend Module thread suspension routine */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) @@ -102,25 +102,23 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN #endif - /* Determine if this is the start thread. If so, we must prepare the module for + /* Determine if this is the start thread. If so, we must prepare the module for execution. If not, simply skip the C startup code. */ if (thread_info -> txm_module_thread_entry_info_start_thread) { - /* Initialize the IAR C environment. */ __iar_data_init3(); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - - /* Save the kernel function dispatch address. This is used to make all resident calls from + + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { - /* Loop here, if an error is present getting the dispatch function pointer! An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ @@ -165,7 +163,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN #endif /* Call actual thread suspension routine. */ - _txm_module_thread_system_suspend(thread_ptr); + _txm_module_thread_system_suspend(thread_ptr); #ifdef TX_SAFETY_CRITICAL diff --git a/ports_module/cortex-m4/iar/module_manager/src/tx_misra.s b/ports_module/cortex-m4/iar/module_manager/src/tx_misra.s index 8a13551e..53c60fbc 100644 --- a/ports_module/cortex-m4/iar/module_manager/src/tx_misra.s +++ b/ports_module/cortex-m4/iar/module_manager/src/tx_misra.s @@ -107,7 +107,7 @@ SECTION `.data`:DATA:REORDER:NOROOT(2) DATA -// 51 CHAR _tx_version_id[100] = "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX 6.0.1 MISRA C Compliant *"; +// 51 CHAR _tx_version_id[100] = "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX 6.1 MISRA C Compliant *"; _tx_version_id: DC8 43H, 6FH, 70H, 79H, 72H, 69H, 67H, 68H DC8 74H, 20H, 28H, 63H, 29H, 20H, 31H, 39H diff --git a/ports_module/cortex-m4/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex-m4/iar/module_manager/src/tx_thread_context_restore.s index 1930c870..850fefa9 100644 --- a/ports_module/cortex-m4/iar/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex-m4/iar/module_manager/src/tx_thread_context_restore.s @@ -21,33 +21,25 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE + EXTERN _tx_execution_isr_exit ; ; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; - EXTERN _tx_execution_isr_exit -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore Cortex-M4/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ ;/* This function restores the interrupt context if it is processing a */ ;/* nested interrupt. If not, it returns to the interrupt thread if no */ ;/* preemption is necessary. Otherwise, if preemption is necessary or */ @@ -73,7 +65,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) @@ -94,5 +86,4 @@ _tx_thread_context_restore: BX lr ; ;} - END - + END diff --git a/ports_module/cortex-m4/iar/module_manager/src/tx_thread_context_save.s b/ports_module/cortex-m4/iar/module_manager/src/tx_thread_context_save.s index ab563506..46cc01d0 100644 --- a/ports_module/cortex-m4/iar/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex-m4/iar/module_manager/src/tx_thread_context_save.s @@ -21,33 +21,25 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE + EXTERN _tx_execution_isr_enter ; ; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; - EXTERN _tx_execution_isr_enter -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save Cortex-M4/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ ;/* This function saves the context of an executing thread in the */ ;/* beginning of interrupt processing. The function also ensures that */ ;/* the system stack is used upon return to the calling ISR. */ @@ -72,7 +64,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -82,7 +74,7 @@ _tx_thread_context_save: #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY ; ; /* Call the ISR enter function to indicate an ISR is starting. */ -; +; PUSH {r0, lr} ; Save return address BL _tx_execution_isr_enter ; Call the ISR enter function POP {r0, lr} ; Recover return address diff --git a/ports_module/cortex-m4/iar/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex-m4/iar/module_manager/src/tx_thread_interrupt_control.s index e04f8ceb..c903f17b 100644 --- a/ports_module/cortex-m4/iar/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex-m4/iar/module_manager/src/tx_thread_interrupt_control.s @@ -20,23 +20,15 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE ; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control Cortex-M4/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -66,21 +58,17 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) ;{ PUBLIC _tx_thread_interrupt_control _tx_thread_interrupt_control: -; -; /* Pickup current interrupt lockout posture. */ -; - MRS r1, PRIMASK - MSR PRIMASK, r0 - MOV r0, r1 - BX lr + MRS r1, PRIMASK ; Pickup current interrupt lockout + MSR PRIMASK, r0 ; Apply the new interrupt lockout + MOV r0, r1 ; Transfer old to return register + BX lr ; Return to caller ; ;} END - diff --git a/ports_module/cortex-m4/iar/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex-m4/iar/module_manager/src/tx_thread_interrupt_disable.s index 7807d5c8..5577555c 100644 --- a/ports_module/cortex-m4/iar/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex-m4/iar/module_manager/src/tx_thread_interrupt_disable.s @@ -20,23 +20,15 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE ; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-M4/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -66,7 +58,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(UINT new_posture) diff --git a/ports_module/cortex-m4/iar/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex-m4/iar/module_manager/src/tx_thread_interrupt_restore.s index 2159ae40..10baa764 100644 --- a/ports_module/cortex-m4/iar/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex-m4/iar/module_manager/src/tx_thread_interrupt_restore.s @@ -20,23 +20,15 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE ; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-M4/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -66,7 +58,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_interrupt_restore(UINT new_posture) diff --git a/ports_module/cortex-m4/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex-m4/iar/module_manager/src/tx_thread_schedule.s index dfbeed5e..c6f2d1da 100644 --- a/ports_module/cortex-m4/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex-m4/iar/module_manager/src/tx_thread_schedule.s @@ -12,8 +12,8 @@ ; ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ @@ -21,68 +21,58 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE -; -#define TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; - EXTERN _tx_thread_current_ptr - EXTERN _tx_thread_execute_ptr - EXTERN _tx_timer_time_slice - EXTERN _tx_thread_system_stack_ptr - EXTERN _tx_execution_thread_enter - EXTERN _tx_execution_thread_exit - EXTERN _tx_thread_preempt_disable - EXTERN _txm_module_manager_memory_fault_handler - EXTERN _txm_module_manager_memory_fault_info + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_execution_thread_enter + EXTERN _tx_execution_thread_exit + EXTERN _tx_thread_preempt_disable + EXTERN _txm_module_manager_memory_fault_handler + EXTERN _txm_module_manager_memory_fault_info ; ; - SECTION `.text`:CODE:NOROOT(2) - THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_schedule Cortex-M4/MPU/IAR */ -;/* 6.0.1 */ + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-M4/MPU/IAR */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ ;/* None */ -;/* */ -;/* CALLS */ -;/* */ +;/* */ +;/* OUTPUT */ +;/* */ ;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -95,7 +85,7 @@ _tx_thread_schedule: ; from the PendSV handling routines below. */ ; ; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ -; +; MOV r0, #0 ; Build value for TX_FALSE LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag STR r0, [r2, #0] ; Clear preempt disable flag @@ -104,7 +94,7 @@ _tx_thread_schedule: ; #ifdef __ARMVFP__ MRS r0, CONTROL ; Pickup current CONTROL register - BIC r0, r0, #4 ; Clear the FPCA bit + BIC r0, r0, #4 ; Clear the FPCA bit MSR CONTROL, r0 ; Setup new CONTROL register #endif ; @@ -112,26 +102,24 @@ _tx_thread_schedule: ; LDR r0, =0xE000ED24 ; Build SHCSR address LDR r1, =0x70000 ; Enable Usage, Bus, and MemManage faults - STR r1, [r0] ; + STR r1, [r0] ; ; ; /* Enable interrupts */ ; CPSIE i -; +; ; /* Enter the scheduler for the first time. */ ; MOV r0, #0x10000000 ; Load PENDSVSET bit MOV r1, #0xE000E000 ; Load NVIC base STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR - NOP ; - NOP ; - NOP ; - NOP ; -; -; /* We should never get here - ever! */ -; - BKPT 0xEF ; Setup error conditions - BX lr ; + DSB ; Complete all memory accesses + ISB ; Flush pipeline + +; /* Wait here for the PendSV to take place. */ + +__tx_wait_here: + B __tx_wait_here ; Wait for the PendSV to happen ;} ; @@ -193,7 +181,7 @@ UsageFault_Handler: STR r0, [r12, #88] ; Save xPSR MRS r0, CONTROL ; Pickup current CONTROL register - BIC r0, r0, #1 ; Clear the UNPRIV bit + BIC r0, r0, #1 ; Clear the UNPRIV bit MSR CONTROL, r0 ; Setup new CONTROL register LDR r0, =0xE000ED28 ; Build the Memory Management Fault Status Register (MMFSR) @@ -209,7 +197,7 @@ UsageFault_Handler: BIC r1, r1, #1 ; Clear the lazy preservation active bit STR r1, [r0] ; Store the value #endif - + BL _txm_module_manager_memory_fault_handler ; Call memory manager fault handler #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY @@ -237,15 +225,15 @@ UsageFault_Handler: ; ; /* Generic context PendSV handler. */ -; +; PUBLIC PendSV_Handler PUBLIC __tx_PendSVHandler PendSV_Handler: __tx_PendSVHandler: ; ; /* Get current thread value and new thread pointer. */ -; -__tx_ts_handler: +; +__tx_ts_handler: #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY ; @@ -263,7 +251,7 @@ __tx_ts_handler: LDR r1, [r0] ; Pickup current thread pointer ; ; /* Determine if there is a current thread to finish preserving. */ -; +; CBZ r1, __tx_ts_new ; If NULL, skip preservation ; ; /* Recover PSP and preserve current thread context. */ @@ -338,7 +326,7 @@ __tx_ts_restore: MRS r5, CONTROL ; Pickup current CONTROL register LDR r4, [r1, #0x98] ; Pickup current user mode flag - BIC r5, r5, #1 ; Clear the UNPRIV bit + BIC r5, r5, #1 ; Clear the UNPRIV bit ORR r4, r4, r5 ; Build new CONTROL register MSR CONTROL, r4 ; Setup new CONTROL register @@ -347,7 +335,7 @@ __tx_ts_restore: STR r3, [r0] ; Disable MPU LDR r0, [r1, #0x90] ; Pickup the module instance pointer CBZ r0, skip_mpu_setup ; Is this thread owned by a module? No, skip MPU setup - LDR r1, [r0, #0x64] ; Pickup MPU register[0] + LDR r1, [r0, #0x64] ; Pickup MPU register[0] CBZ r1, skip_mpu_setup ; Is protection required for this module? No, skip MPU setup LDR r1, =0xE000ED9C ; Build address of MPU base register @@ -358,13 +346,13 @@ __tx_ts_restore: LDM r0,{r2-r9} ; Load second four MPU regions STM r1,{r2-r9} ; Store second four MPU regions LDR r0, =0xE000ED94 ; Build MPU control reg address - MOV r1, #5 ; Build enable value + MOV r1, #5 ; Build enable value with background region enabled STR r1, [r0] ; Enable MPU skip_mpu_setup: LDMIA r12!, {LR} ; Pickup LR #ifdef __ARMVFP__ TST LR, #0x10 ; Determine if the VFP extended frame is present - BNE _skip_vfp_restore ; If not, skip VFP restore + BNE _skip_vfp_restore ; If not, skip VFP restore VLDMIA r12!, {s16-s31} ; Yes, restore additional VFP registers _skip_vfp_restore: #endif @@ -372,11 +360,11 @@ _skip_vfp_restore: MSR PSP, r12 ; Setup the thread's stack pointer ; ; /* Return to thread. */ -; +; BX lr ; Return to thread! ; ; /* The following is the idle wait processing... in this case, no threads are ready for execution and the -; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts ; are disabled to allow use of WFI for waiting for a thread to arrive. */ ; __tx_ts_wait: @@ -392,16 +380,16 @@ __tx_ts_wait: CPSIE i ; Enable interrupts B __tx_ts_wait ; Loop to continue waiting ; -; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are ; already in the handler! */ ; __tx_ts_ready: MOV r7, #0x08000000 ; Build clear PendSV value MOV r8, #0xE000E000 ; Build base NVIC address - STR r7, [r8, #0xD04] ; Clear any PendSV + STR r7, [r8, #0xD04] ; Clear any PendSV ; ; /* Re-enable interrupts and restore new thread. */ -; +; CPSIE i ; Enable interrupts B __tx_ts_restore ; Restore the thread ;} @@ -429,7 +417,7 @@ __tx_SVCallHandler: CMP r1, r2 ; Did we come from user_mode_entry? IT NE ; If no (not equal), then... BXNE lr ; return from where we came. - + LDR r3, [r0, #20] ; This is the saved LR LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address LDR r2, [r1] ; Pickup current thread pointer @@ -438,73 +426,72 @@ __tx_SVCallHandler: STR r3, [r2, #0xA0] ; Save the original LR in thread control block ; If there is memory protection, use kernel stack - LDR r0, [r2, #0x90] ; Load the module instance ptr - LDR r0, [r0, #0x0C] ; Load the module property flags - TST r0, #2 ; Check if memory protected + LDR r0, [r2, #0x90] ; Load the module instance ptr + LDR r0, [r0, #0x0C] ; Load the module property flags + TST r0, #2 ; Check if memory protected BEQ _tx_skip_kernel_stack_enter ; Switch to the module thread's kernel stack - LDR r0, [r2, #0xA8] ; Load the module kernel stack end + LDR r0, [r2, #0xA8] ; Load the module kernel stack end #ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE - LDR r1, [r2, #0xA4] ; Load the module kernel stack start - LDR r3, [r2, #0xAC] ; Load the module kernel stack size - STR r1, [r2, #12] ; Set stack start - STR r0, [r2, #16] ; Set stack end - STR r3, [r2, #20] ; Set stack size + LDR r1, [r2, #0xA4] ; Load the module kernel stack start + LDR r3, [r2, #0xAC] ; Load the module kernel stack size + STR r1, [r2, #12] ; Set stack start + STR r0, [r2, #16] ; Set stack end + STR r3, [r2, #20] ; Set stack size #endif - MRS r3, PSP ; Pickup thread stack pointer - STR r3, [r2, #0xB0] ; Save thread stack pointer + MRS r3, PSP ; Pickup thread stack pointer + STR r3, [r2, #0xB0] ; Save thread stack pointer ; Build kernel stack by copying thread stack two registers at a time - ADD r3, r3, #32 ; start at bottom of hardware stack - LDMDB r3!,{r1-r2} ; - STMDB r0!,{r1-r2} ; - LDMDB r3!,{r1-r2} ; - STMDB r0!,{r1-r2} ; - LDMDB r3!,{r1-r2} ; - STMDB r0!,{r1-r2} ; - LDMDB r3!,{r1-r2} ; - STMDB r0!,{r1-r2} ; + ADD r3, r3, #32 ; start at bottom of hardware stack + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} - MSR PSP, r0 ; Set kernel stack pointer - -_tx_skip_kernel_stack_enter: + MSR PSP, r0 ; Set kernel stack pointer + +_tx_skip_kernel_stack_enter: MRS r0, CONTROL ; Pickup current CONTROL register - BIC r0, r0, #1 ; Clear the UNPRIV bit + BIC r0, r0, #1 ; Clear the UNPRIV bit MSR CONTROL, r0 ; Setup new CONTROL register BX lr ; Return to thread _tx_thread_user_return: - LDR r2, =_txm_module_user_mode_exit-1 ; Subtract 1 because of THUMB mode. CMP r1, r2 ; Did we come from user_mode_exit? IT NE ; If no (not equal), then... BXNE lr ; return from where we came - + LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address LDR r2, [r1] ; Pickup current thread pointer LDR r1, [r2, #0x9C] ; Pick up user mode STR r1, [r2, #0x98] ; Set the current user mode selection for thread ; If there is memory protection, use kernel stack - LDR r0, [r2, #0x90] ; Load the module instance ptr - LDR r0, [r0, #0x0C] ; Load the module property flags - TST r0, #2 ; Check if memory protected + LDR r0, [r2, #0x90] ; Load the module instance ptr + LDR r0, [r0, #0x0C] ; Load the module property flags + TST r0, #2 ; Check if memory protected BEQ _tx_skip_kernel_stack_exit - -#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE - LDR r0, [r2, #0xB4] ; Load the module thread stack start - LDR r1, [r2, #0xB8] ; Load the module thread stack end - LDR r3, [r2, #0xBC] ; Load the module thread stack size - STR r0, [r2, #12] ; Set stack start - STR r1, [r2, #16] ; Set stack end - STR r3, [r2, #20] ; Set stack size -#endif - LDR r0, [r2, #0xB0] ; Load the module thread stack pointer - MRS r3, PSP ; Pickup kernel stack pointer - ; Copy kernel hardware stack to module thread stack. +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + LDR r0, [r2, #0xB4] ; Load the module thread stack start + LDR r1, [r2, #0xB8] ; Load the module thread stack end + LDR r3, [r2, #0xBC] ; Load the module thread stack size + STR r0, [r2, #12] ; Set stack start + STR r1, [r2, #16] ; Set stack end + STR r3, [r2, #20] ; Set stack size +#endif + LDR r0, [r2, #0xB0] ; Load the module thread stack pointer + MRS r3, PSP ; Pickup kernel stack pointer + + ; Copy kernel hardware stack to module thread stack. LDM r3!,{r1-r2} STM r0!,{r1-r2} LDM r3!,{r1-r2} @@ -513,13 +500,13 @@ _tx_thread_user_return: STM r0!,{r1-r2} LDM r3!,{r1-r2} STM r0!,{r1-r2} - SUB r0, r0, #32 ; Subtract 32 to get back to top of stack - MSR PSP, r0 ; Set thread stack pointer + SUB r0, r0, #32 ; Subtract 32 to get back to top of stack + MSR PSP, r0 ; Set thread stack pointer LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address LDR r2, [r1] ; Pickup current thread pointer LDR r1, [r2, #0x9C] ; Pick up user mode - + _tx_skip_kernel_stack_exit: MRS r0, CONTROL ; Pickup current CONTROL register ORR r0, r0, r1 ; OR in the user mode bit @@ -544,7 +531,7 @@ _txm_module_priv: ; At this point, we are out of user mode. The original LR has been saved in the ; thread control block. Simply call the kernel dispatch function. BL _txm_module_manager_kernel_dispatch - + ; Pickup the original LR value while still in privileged mode LDR r2, =_tx_thread_current_ptr ; Build current thread pointer address LDR r3, [r2] ; Pickup current thread pointer @@ -552,7 +539,7 @@ _txm_module_priv: SVC 2 ; Exit kernel and return to user mode _txm_module_user_mode_exit: - BX lr ; Return to the caller + BX lr ; Return to the caller NOP NOP NOP @@ -565,7 +552,7 @@ _txm_module_user_mode_exit: PUBLIC tx_thread_fpu_enable tx_thread_fpu_enable: ; -; /* Automatic VPF logic is supported, this function is present only for +; /* Automatic VPF logic is supported, this function is present only for ; backward compatibility purposes and therefore simply returns. */ ; BX LR ; Return to caller @@ -573,7 +560,7 @@ tx_thread_fpu_enable: PUBLIC tx_thread_fpu_disable tx_thread_fpu_disable: ; -; /* Automatic VPF logic is supported, this function is present only for +; /* Automatic VPF logic is supported, this function is present only for ; backward compatibility purposes and therefore simply returns. */ ; BX LR ; Return to caller diff --git a/ports_module/cortex-m4/iar/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex-m4/iar/module_manager/src/tx_thread_stack_build.s index 55a8bc5e..493ee69d 100644 --- a/ports_module/cortex-m4/iar/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex-m4/iar/module_manager/src/tx_thread_stack_build.s @@ -21,14 +21,14 @@ ;/**************************************************************************/ ; ; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build Cortex-M4/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -60,7 +60,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -68,11 +68,11 @@ PUBLIC _tx_thread_stack_build _tx_thread_stack_build: ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-M should look like the following after it is built: -; -; Stack Top: +; +; Stack Top: ; LR Interrupted LR (LR at time of PENDSV) ; r4 Initial value for r4 ; r5 Initial value for r5 @@ -132,4 +132,3 @@ _tx_thread_stack_build: BX lr ; Return to caller ;} END - diff --git a/ports_module/cortex-m4/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex-m4/iar/module_manager/src/tx_thread_system_return.s index 9820752e..4ea6aa72 100644 --- a/ports_module/cortex-m4/iar/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex-m4/iar/module_manager/src/tx_thread_system_return.s @@ -20,25 +20,15 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE ; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return Cortex-M4/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -70,7 +60,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -79,9 +69,9 @@ _tx_thread_system_return??rA: _tx_thread_system_return: ; -; /* Return to real scheduler via PendSV. Note that this routine is often +; /* Return to real scheduler via PendSV. Note that this routine is often ; replaced with in-line assembly in tx_port.h to improved performance. */ -; +; MOV r0, #0x10000000 ; Load PENDSVSET bit MOV r1, #0xE000E000 ; Load NVIC base STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR @@ -92,7 +82,6 @@ _tx_thread_system_return: CPSIE i ; Enable interrupts MSR PRIMASK, r1 ; Restore original interrupt posture _isr_context: - BX lr ; Return to caller + BX lr ; Return to caller ;} - END - + END diff --git a/ports_module/cortex-m4/iar/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex-m4/iar/module_manager/src/tx_timer_interrupt.s index 0a3c3e52..dabf7e1c 100644 --- a/ports_module/cortex-m4/iar/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex-m4/iar/module_manager/src/tx_timer_interrupt.s @@ -20,17 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_timer.h" -;#include "tx_thread.h" -; -; -;Define Assembly language external references... ; EXTERN _tx_timer_time_slice EXTERN _tx_timer_system_clock @@ -46,14 +35,14 @@ EXTERN _tx_thread_preempt_disable ; ; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt Cortex-M4/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -86,7 +75,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -109,7 +98,7 @@ _tx_timer_interrupt: ; if (_tx_timer_time_slice) ; { ; - MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice + MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CBZ r2, __tx_timer_no_time_slice ; Is it non-active? ; Yes, skip time-slice processing @@ -226,13 +215,13 @@ __tx_timer_dont_activate: ; if (_tx_timer_expired_time_slice) ; { ; - MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired + MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag @@ -265,4 +254,3 @@ __tx_timer_nothing_expired: ; ;} END - diff --git a/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_alignment_adjust.c index 7425245b..27c1759d 100644 --- a/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_alignment_adjust.c @@ -31,7 +31,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_power_of_two_block_size Cortex-M4/MPU/IAR */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -61,7 +61,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) @@ -69,11 +69,11 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* Check for 0 size. */ if(size == 0) return 0; - + /* Minimum MPU block size is 32. */ if(size <= 32) return 32; - + /* Bit twiddling trick to round to next high power of 2 (if original size is power of 2, it will return original size. Perfect!) */ size--; @@ -83,7 +83,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) size |= size >> 8; size |= size >> 16; size++; - + /* Return a power of 2 size at or above the input size. */ return(size); } @@ -94,15 +94,15 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_alignment_adjust Cortex-M4/MPU/IAR */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ -/* This function adjusts the alignment and size of the code and data */ -/* section for a given module implementation. */ +/* This function adjusts the alignment and size of the code and data */ +/* section for a given module implementation. */ /* */ /* INPUT */ /* */ @@ -128,7 +128,7 @@ ULONG _txm_power_of_two_block_size(ULONG size) /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, @@ -253,19 +253,18 @@ ULONG data_size_accum; /* Just set block size to 32MB just to create an allocation error! */ code_block_size = 33554432; } - + /* Calculate the new code size. */ local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); - + /* Determine if the code block size is greater than the current alignment. If so, use block size as the alignment. */ if (code_block_size > local_code_alignment) local_code_alignment = code_block_size; - + } else { - /* Determine code block sizes. Minimize the alignment requirement. There are 4 MPU code entries available. The following is how the code size will be distributed: @@ -279,11 +278,10 @@ ULONG data_size_accum; code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); local_code_size = code_size_accum; } - + /* Determine the best data block size, which in our case is the minimal alignment. */ if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) { - /* Block size of 32 is best. */ data_block_size = 32; } @@ -374,7 +372,6 @@ ULONG data_size_accum; } else { - /* Just set data block size to 32MB just to create an allocation error! */ data_block_size = 33554432; } @@ -386,11 +383,13 @@ ULONG data_size_accum; data_size_accum += data_block_size; } local_data_size = data_size_accum; - + /* Determine if the data block size is greater than the current alignment. If so, use block size as the alignment. */ if (data_block_size > local_data_alignment) + { local_data_alignment = data_block_size; + } /* Return all the information to the caller. */ *code_size = local_code_size; diff --git a/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_external_memory_enable.c index 4df714a7..635b617b 100644 --- a/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -10,15 +10,15 @@ /**************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #define TX_SOURCE_CODE @@ -29,52 +29,53 @@ #include "txm_module.h" -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_external_memory_enable Cortex-M4/MPU/IAR */ -/* 6.0.1 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_external_memory_enable Cortex-M4/MPU/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function creates an entry in the MPU table for a shared */ -/* memory space. */ -/* */ -/* INPUT */ -/* */ -/* module_instance Module instance pointer */ -/* start_address Start address of memory */ -/* length Length of external memory */ -/* attributes Memory attributes (r/w) */ -/* */ -/* OUTPUT */ -/* */ -/* status Completion status */ -/* */ -/* CALLS */ -/* */ -/* _tx_mutex_get Get protection mutex */ -/* _tx_mutex_put Release protection mutex */ -/* _txm_power_of_two_block_size Round length to power of two */ -/* */ -/* CALLED BY */ -/* */ -/* Application code */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function creates an entry in the MPU table for a shared */ +/* memory space. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* start_address Start address of memory */ +/* length Length of external memory */ +/* attributes Memory attributes (r/w) */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_mutex_get Get protection mutex */ +/* _tx_mutex_put Release protection mutex */ +/* _txm_power_of_two_block_size Round length to power of two */ +/* _txm_module_manager_mm_register_setup Reconfigure MPU registers */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, - VOID *start_address, - ULONG length, +UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, + VOID *start_address, + ULONG length, UINT attributes) { @@ -88,15 +89,13 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Determine if the module manager has not been initialized yet. */ if (_txm_module_manager_ready != TX_TRUE) { - /* Module manager has not been initialized. */ - return(TX_NOT_AVAILABLE); + return(TX_NOT_AVAILABLE); } /* Determine if the module is valid. */ if (module_instance == TX_NULL) { - /* Invalid module pointer. */ return(TX_PTR_ERROR); } @@ -107,7 +106,6 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Determine if the module instance is valid. */ if (module_instance -> txm_module_instance_id != TXM_MODULE_ID) { - /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); @@ -118,7 +116,6 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { - /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); @@ -138,7 +135,7 @@ TXM_MODULE_PREAMBLE *module_preamble; return(TXM_MODULE_INVALID_PROPERTIES); } - /* Start address and length must adhere to Cortex-M MPU. + /* Start address and length must adhere to Cortex-M MPU. The address must align with the block size. */ block_size = _txm_power_of_two_block_size(length); @@ -183,4 +180,3 @@ TXM_MODULE_PREAMBLE *module_preamble; /* Return success. */ return(TX_SUCCESS); } - diff --git a/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_memory_fault_handler.c index a6d64282..6b63fe46 100644 --- a/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -10,15 +10,15 @@ /**************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #define TX_SOURCE_CODE @@ -33,50 +33,50 @@ VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); -/* Define a macro that can be used to allocate global variables useful to - store information about the last fault. This macro is defined in +/* Define a macro that can be used to allocate global variables useful to + store information about the last fault. This macro is defined in txm_module_port.h and is usually populated in the assembly language fault handling prior to the code calling _txm_module_manager_memory_fault_handler. */ TXM_MODULE_MANAGER_FAULT_INFO -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_memory_fault_handler Cortex-M4/MPU/IAR */ -/* 6.0.1 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_handler Cortex-M4/MPU/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function handles a fault associated with a memory protected */ -/* module. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* _tx_thread_terminate Terminate thread */ -/* */ -/* CALLED BY */ -/* */ -/* Fault handler */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function handles a fault associated with a memory protected */ +/* module. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_terminate Terminate thread */ +/* */ +/* CALLED BY */ +/* */ +/* Fault handler */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) @@ -85,7 +85,6 @@ VOID _txm_module_manager_memory_fault_handler(VOID) TXM_MODULE_INSTANCE *module_instance_ptr; TX_THREAD *thread_ptr; - /* Pickup the current thread. */ thread_ptr = _tx_thread_current_ptr; @@ -95,7 +94,6 @@ TX_THREAD *thread_ptr; /* Is there a thread? */ if (thread_ptr) { - /* Pickup the module instance. */ module_instance_ptr = thread_ptr -> tx_thread_module_instance_ptr; @@ -106,9 +104,7 @@ TX_THREAD *thread_ptr; /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { - /* Yes, call the user's notification memory fault callback. */ (_txm_module_manager_fault_notify)(thread_ptr, module_instance_ptr); } } - diff --git a/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_memory_fault_notify.c index 833d98bf..0e5b94c8 100644 --- a/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -10,15 +10,15 @@ /**************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #define TX_SOURCE_CODE @@ -34,53 +34,51 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_memory_fault_notify Cortex-M4/MPU/IAR */ -/* 6.0.1 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_notify Cortex-M4/MPU/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function registers an application callback when/if a memory */ -/* fault occurs. The supplied thread is automatically terminated, but */ -/* any other threads in the same module may still execute. */ -/* */ -/* INPUT */ -/* */ -/* notify_function Memory fault notification */ -/* function, NULL disables. */ -/* */ -/* OUTPUT */ -/* */ -/* status Completion status */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application callback when/if a memory */ +/* fault occurs. The supplied thread is automatically terminated, but */ +/* any other threads in the same module may still execute. */ +/* */ +/* INPUT */ +/* */ +/* notify_function Memory fault notification */ +/* function, NULL disables. */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { - /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; /* Return success. */ return(TX_SUCCESS); } - diff --git a/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_mm_register_setup.c index e567b33d..d337bbaa 100644 --- a/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -10,59 +10,58 @@ /**************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #define TX_SOURCE_CODE #include "tx_api.h" #include "txm_module.h" -#include "txm_module_manager_util.h" -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_region_size_get Cortex-M4/MPU/IAR */ -/* 6.0.1 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_region_size_get Cortex-M4/MPU/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function converts the region size in bytes to the block size */ -/* for the Cortex-M4 MPU specification. */ -/* */ -/* INPUT */ -/* */ -/* block_size Size of the block in bytes */ -/* */ -/* OUTPUT */ -/* */ -/* MPU size specification */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _txm_module_manager_mm_register_setup */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function converts the region size in bytes to the block size */ +/* for the Cortex-M4 MPU specification. */ +/* */ +/* INPUT */ +/* */ +/* block_size Size of the block in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* MPU size specification */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) @@ -70,7 +69,6 @@ ULONG _txm_module_manager_region_size_get(ULONG block_size) ULONG return_value; - /* Process relative to the input block size. */ if (block_size == 32) { @@ -140,7 +138,7 @@ ULONG return_value; { return_value = 0x14; } - else + else { /* Max 4MB MPU pages for modules. */ return_value = 0x15; @@ -150,45 +148,43 @@ ULONG return_value; } - - -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_calculate_srd_bits Cortex-M4/MPU/IAR */ -/* 6.0.1 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_calculate_srd_bits Cortex-M4/MPU/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function calculates the SRD bits that need to be set to */ -/* protect "length" bytes in a block. */ -/* */ -/* INPUT */ -/* */ -/* block_size Size of the block in bytes */ -/* length Actual length in bytes */ -/* */ -/* OUTPUT */ -/* */ -/* SRD bits to be OR'ed with region attribute register. */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _txm_module_manager_mm_register_setup */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function calculates the SRD bits that need to be set to */ +/* protect "length" bytes in a block. */ +/* */ +/* INPUT */ +/* */ +/* block_size Size of the block in bytes */ +/* length Actual length in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* SRD bits to be OR'ed with region attribute register. */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) @@ -230,43 +226,42 @@ UINT srd_bit_index; } - -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_mm_register_setup Cortex-M4/MPU/IAR */ -/* 6.0.1 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_mm_register_setup Cortex-M4/MPU/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function sets up the Cortex-M4 MPU register definitions based */ -/* on the module's memory characteristics. */ -/* */ -/* INPUT */ -/* */ -/* module_instance Pointer to module instance */ -/* */ -/* OUTPUT */ -/* */ -/* MPU specifications for module in module_instance */ -/* */ -/* CALLS */ -/* */ -/* _txm_module_manager_region_size_get */ -/* */ -/* CALLED BY */ -/* */ -/* _txm_module_manager_thread_create */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function sets up the Cortex-M4 MPU register definitions based */ +/* on the module's memory characteristics. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* */ +/* OUTPUT */ +/* */ +/* MPU specifications for module in module_instance */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_manager_region_size_get */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_thread_create */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) @@ -291,9 +286,11 @@ UINT i; /* Setup the first region for the ThreadX trampoline code. */ /* Set base register to user mode entry, which is guaranteed to be at least 32-byte aligned. */ base_address_register = (ULONG) _txm_module_manager_user_mode_entry; + /* Mask address to proper range, region 0, set Valid bit. */ base_address_register = (base_address_register & 0xFFFFFFE0) | mpu_register | 0x10; module_instance -> txm_module_instance_mpu_registers[0] = base_address_register; + /* Attributes: read only, write-back, shareable, size 32 bytes, region enabled. */ module_instance -> txm_module_instance_mpu_registers[1] = 0x06070009; @@ -304,11 +301,10 @@ UINT i; mpu_table_index = 2; /* Setup values for code area. */ - code_address = (ULONG) module_instance -> txm_module_instance_code_start; + code_address = (ULONG) module_instance -> txm_module_instance_code_start; code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; - - /* Check if shared memory was set up. If so, only 3 entries are available for + /* Check if shared memory was set up. If so, only 3 entries are available for code protection. If not set up, 4 code entries are available. */ if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] == 0) { @@ -352,7 +348,7 @@ UINT i; /* Calculate the region size information. */ region_size = (_txm_module_manager_region_size_get(block_size) << 1); - + /* Build the base attribute register. */ base_attribute_register = region_size | srd_bits | 0x06070001; @@ -385,7 +381,6 @@ UINT i; /* Now loop through to setup MPU protection for the code area. */ for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) { - /* Build the base address register. */ base_address_register = code_address & ~(block_size - 1) | mpu_register | 0x10; @@ -405,7 +400,7 @@ UINT i; base_attribute_register = base_attribute_register | 0x1; } /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; + module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; /* Setup the MPU Base Attribute Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; @@ -415,9 +410,13 @@ UINT i; /* Decrement the code size. */ if (code_size > block_size) + { code_size = code_size - block_size; + } else + { code_size = 0; + } /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; @@ -435,7 +434,7 @@ UINT i; } /* Setup values for data area. */ - data_address = (ULONG) module_instance -> txm_module_instance_data_start; + data_address = (ULONG) module_instance -> txm_module_instance_data_start; /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside @@ -455,8 +454,7 @@ UINT i; /* Update the data size to include thread stacks. */ data_size = data_size + start_stop_stack_size + callback_stack_size; - - block_size = _txm_power_of_two_block_size(data_size / TXM_MODULE_MANAGER_DATA_MPU_ENTRIES); + block_size = _txm_power_of_two_block_size(data_size / TXM_MODULE_MANAGER_DATA_MPU_ENTRIES); /* Reset SRD bitfield. */ srd_bits = 0; @@ -467,7 +465,6 @@ UINT i; /* Now loop through to setup MPU protection for the data area. */ for (i = 0; i < TXM_MODULE_MANAGER_DATA_MPU_ENTRIES; i++) { - /* Build the base address register. */ base_address_register = (data_address & ~(block_size - 1)) | mpu_register | 0x10; @@ -475,11 +472,11 @@ UINT i; if (data_size < block_size) { srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); - } + } /* Build the base attribute register. */ base_attribute_register = region_size | srd_bits | 0x13070000; - + /* Is there still some data? If so set the region enable bit. */ if (data_size) { @@ -488,7 +485,7 @@ UINT i; } /* Setup the MPU Base Address Register. */ - module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; + module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; /* Setup the MPU Base Attribute Register. */ module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; @@ -498,9 +495,13 @@ UINT i; /* Decrement the data size. */ if (data_size > block_size) + { data_size = data_size - block_size; + } else + { data_size = 0; + } /* Move MPU table index. */ mpu_table_index = mpu_table_index + 2; @@ -508,176 +509,4 @@ UINT i; /* Increment the MPU register index. */ mpu_register++; } - -} - -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_shared_memory_check_outside */ -/* Cortex-M4/MPU/IAR */ -/* 6.0.1 */ -/* AUTHOR */ -/* */ -/* Scott Larson, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function checks if the specified object is outside shared */ -/* memory. */ -/* */ -/* INPUT */ -/* */ -/* module_instance Pointer to module instance */ -/* obj_ptr Pointer to the object */ -/* obj_size Size of the object */ -/* */ -/* OUTPUT */ -/* */ -/* Whether the object is outside the shared memory region. */ -/* */ -/* CALLS */ -/* */ -/* N/A */ -/* */ -/* CALLED BY */ -/* */ -/* Module dispatch check functions */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ -/* */ -/**************************************************************************/ -UCHAR _txm_module_manager_shared_memory_check_outside(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) -{ - -ALIGN_TYPE shared_memory_start; -ALIGN_TYPE shared_memory_end; - - shared_memory_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address; - shared_memory_end = shared_memory_start + module_instance -> txm_module_instance_shared_memory_length; - - if (TXM_MODULE_MANAGER_CHECK_OUTSIDE_RANGE_EXCLUSIVE(shared_memory_start, shared_memory_end, - obj_ptr, obj_size)) - { - return(TX_TRUE); - } - return(TX_FALSE); -} - -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_shared_memory_check_inside Cortex-M4/MPU/IAR */ -/* 6.0.1 */ -/* AUTHOR */ -/* */ -/* Scott Larson, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function checks if the specified object is inside shared */ -/* memory. */ -/* */ -/* INPUT */ -/* */ -/* module_instance Pointer to module instance */ -/* obj_ptr Pointer to the object */ -/* obj_size Size of the object */ -/* */ -/* OUTPUT */ -/* */ -/* Whether the object is inside the shared memory region. */ -/* */ -/* CALLS */ -/* */ -/* N/A */ -/* */ -/* CALLED BY */ -/* */ -/* Module dispatch check functions */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ -/* */ -/**************************************************************************/ -UCHAR _txm_module_manager_shared_memory_check_inside(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) -{ - -ALIGN_TYPE shared_memory_start; -ALIGN_TYPE shared_memory_end; - - shared_memory_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address; - shared_memory_end = shared_memory_start + module_instance -> txm_module_instance_shared_memory_length; - - if (TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_EXCLUSIVE(shared_memory_start, shared_memory_end, - obj_ptr, obj_size)) - { - return(TX_TRUE); - } - return(TX_FALSE); -} - -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_shared_memory_check_inside_byte */ -/* Cortex-M4/MPU/IAR */ -/* 6.0.1 */ -/* AUTHOR */ -/* */ -/* Scott Larson, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function checks if the specified byte is inside shared memory. */ -/* */ -/* INPUT */ -/* */ -/* module_instance Pointer to module instance */ -/* byte_ptr Pointer to the byte */ -/* */ -/* OUTPUT */ -/* */ -/* Whether the byte is inside the shared memory region. */ -/* */ -/* CALLS */ -/* */ -/* N/A */ -/* */ -/* CALLED BY */ -/* */ -/* Module dispatch check functions */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ -/* */ -/**************************************************************************/ -UCHAR _txm_module_manager_shared_memory_check_inside_byte(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE byte_ptr) -{ - -ALIGN_TYPE shared_memory_start; -ALIGN_TYPE shared_memory_end; - - shared_memory_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address; - shared_memory_end = shared_memory_start + module_instance -> txm_module_instance_shared_memory_length; - - if (TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_EXCLUSIVE_BYTE(shared_memory_start, shared_memory_end, - byte_ptr)) - { - return(TX_TRUE); - } - return(TX_FALSE); } diff --git a/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_thread_stack_build.s index f7dc7b68..ac318fcf 100644 --- a/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_thread_stack_build.s @@ -10,66 +10,57 @@ ;/**************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Module Manager */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Module Manager */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _txm_module_manager_thread_stack_build Cortex-M4/MPU/IAR */ -;/* 6.0.1 */ + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _txm_module_manager_thread_stack_build Cortex-M4/MPU/IAR */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function builds a stack frame on the supplied thread's stack. */ -;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ -;/* thread_ptr Pointer to thread */ -;/* function_ptr Pointer to shell function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread */ +;/* function_ptr Pointer to shell function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) @@ -77,11 +68,11 @@ PUBLIC _txm_module_manager_thread_stack_build _txm_module_manager_thread_stack_build: ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-M should look like the following after it is built: -; -; Stack Top: +; +; Stack Top: ; LR Interrupted LR (LR at time of PENDSV) ; r4 Initial value for r4 ; r5 Initial value for r5 @@ -89,7 +80,7 @@ _txm_module_manager_thread_stack_build: ; r7 Initial value for r7 ; r8 Initial value for r8 ; r9 Initial value for r9 -; r10 (sl) Initial value for r10 (sl) +; r10 Initial value for r10 ; r11 Initial value for r11 ; r0 Initial value for r0 (Hardware stack starts here!!) ; r1 Initial value for r1 @@ -116,17 +107,15 @@ _txm_module_manager_thread_stack_build: STR r3, [r2, #12] ; Store initial r6 STR r3, [r2, #16] ; Store initial r7 STR r3, [r2, #20] ; Store initial r8 - LDR r3, [r0, #12] ; Pickup stack starting address - STR r3, [r2, #28] ; Store initial r10 (sl) - MOV r3, #0 ; Build initial register value + STR r3, [r2, #28] ; Store initial r10 STR r3, [r2, #32] ; Store initial r11 ; -; /* Hardware stack follows. / +; /* Hardware stack follows. */ ; STR r0, [r2, #36] ; Store initial r0, which is the thread control block LDR r3, [r0, #8] ; Pickup thread entry info pointer,which is in the stack pointer position of the thread control block. - ; It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this + ; It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this ; function with the actual, initial stack pointer. STR r3, [r2, #40] ; Store initial r1, which is the module entry information. LDR r3, [r3, #8] ; Pickup data base register from the module information @@ -145,8 +134,7 @@ _txm_module_manager_thread_stack_build: ; /* Setup stack pointer. */ ; thread_ptr -> tx_thread_stack_ptr = r2; ; - STR r2, [r0, #8] ; Save stack pointer in thread's - ; control block + STR r2, [r0, #8] ; Save stack pointer in thread's control block BX lr ; Return to caller ;} END diff --git a/ports_module/cortex-m7/ac5/example_build/build.bat b/ports_module/cortex-m7/ac5/example_build/build.bat new file mode 100644 index 00000000..57eae574 --- /dev/null +++ b/ports_module/cortex-m7/ac5/example_build/build.bat @@ -0,0 +1,8 @@ +@ECHO OFF +ECHO Starting build... +CALL build_threadx.bat +CALL build_threadx_demo.bat +CALL build_threadx_module_library.bat +CALL build_threadx_module_demo.bat +CALL build_threadx_module_manager_demo.bat +ECHO Build finished. diff --git a/ports_module/cortex-m7/ac5/example_build/build_threadx.bat b/ports_module/cortex-m7/ac5/example_build/build_threadx.bat new file mode 100644 index 00000000..e227ec37 --- /dev/null +++ b/ports_module/cortex-m7/ac5/example_build/build_threadx.bat @@ -0,0 +1,240 @@ +del tx.a +armasm -g --cpu=cortex-m7 --fpu=softvfp --apcs=/interwork tx_initialize_low_level.S +armasm -g --cpu=cortex-m7 --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_stack_build.S +armasm -g --cpu=cortex-m7 --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_schedule.S +armasm -g --cpu=cortex-m7 --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_system_return.S +armasm -g --cpu=cortex-m7 --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_context_save.S +armasm -g --cpu=cortex-m7 --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_context_restore.S +armasm -g --cpu=cortex-m7 --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_interrupt_control.S +armasm -g --cpu=cortex-m7 --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_timer_interrupt.S +armasm -g --cpu=cortex-m7 --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_interrupt_disable.S +armasm -g --cpu=cortex-m7 --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_interrupt_restore.S +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_allocate.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_cleanup.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_create.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_delete.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_info_get.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_initialize.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_performance_info_get.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_performance_system_info_get.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_prioritize.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_release.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_allocate.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_cleanup.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_create.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_delete.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_info_get.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_initialize.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_performance_info_get.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_prioritize.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_search.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_release.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_cleanup.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_create.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_delete.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_get.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_info_get.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_initialize.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_performance_info_get.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_performance_system_info_get.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_set.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_set_notify.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_initialize_high_level.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_initialize_kernel_enter.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_initialize_kernel_setup.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_cleanup.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_create.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_delete.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_get.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_info_get.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_initialize.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_performance_info_get.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_performance_system_info_get.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_prioritize.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_priority_change.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_put.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_cleanup.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_create.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_delete.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_flush.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_front_send.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_info_get.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_initialize.c +armcc -g -O0 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../../../../common/src/txe_thread_terminate.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_time_slice_change.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_wait_abort.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_activate.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_change.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_create.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_deactivate.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_delete.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_info_get.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_application_request.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_callback_request.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_event_flags_notify_trampoline.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_file_load.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_in_place_load.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_internal_load.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_initialize.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_kernel_dispatch.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_maximum_module_priority_set.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_memory_load.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_allocate.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_deallocate.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_pointer_get.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_pointer_get_extended.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_pool_create.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_properties_get.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_queue_notify_trampoline.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_semaphore_notify_trampoline.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_start.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_stop.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_thread_create.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_thread_notify_trampoline.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_thread_reset.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_timer_notify_trampoline.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_unload.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_util.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_alignment_adjust.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_external_memory_enable.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_memory_fault_handler.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_memory_fault_notify.c +armcc -g -O0 --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_mm_register_setup.c +armasm -g --cpu=cortex-m7 --fpu=softvfp --apcs=/interwork ../module_manager/src/txm_module_manager_thread_stack_build.S +armasm -g --cpu=cortex-m7 --fpu=softvfp --apcs=/interwork ../module_manager/src/txm_module_manager_user_mode_entry.S + +armar --create tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o tx_initialize_low_level.o tx_thread_interrupt_disable.o tx_thread_interrupt_restore.o tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o + +armar -r tx.a tx_event_flags_performance_system_info_get.o tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o + +armar -r tx.a tx_semaphore_put_notify.o tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o + +armar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o + +armar -r tx.a txe_queue_prioritize.o txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o txm_module_manager_alignment_adjust.o txm_module_manager_application_request.o txm_module_manager_callback_request.o txm_module_manager_event_flags_notify_trampoline.o txm_module_manager_external_memory_enable.o txm_module_manager_file_load.o txm_module_manager_in_place_load.o + +armar -r tx.a txm_module_manager_initialize.o txm_module_manager_kernel_dispatch.o txm_module_manager_maximum_module_priority_set.o txm_module_manager_memory_fault_handler.o txm_module_manager_memory_fault_notify.o txm_module_manager_memory_load.o txm_module_manager_object_pointer_get.o txm_module_manager_object_pool_create.o txm_module_manager_queue_notify_trampoline.o txm_module_manager_semaphore_notify_trampoline.o txm_module_manager_mm_register_setup.o txm_module_manager_start.o txm_module_manager_stop.o txm_module_manager_thread_create.o txm_module_manager_thread_notify_trampoline.o txm_module_manager_thread_reset.o txm_module_manager_timer_notify_trampoline.o txm_module_manager_unload.o txm_module_manager_thread_stack_build.o txm_module_manager_internal_load.o txm_module_manager_object_allocate.o txm_module_manager_object_deallocate.o txm_module_manager_object_pointer_get_extended.o txm_module_manager_properties_get.o txm_module_manager_util.o txm_module_manager_user_mode_entry.o diff --git a/ports_module/cortex-m7/ac5/example_build/build_threadx_demo.bat b/ports_module/cortex-m7/ac5/example_build/build_threadx_demo.bat new file mode 100644 index 00000000..70d0bc23 --- /dev/null +++ b/ports_module/cortex-m7/ac5/example_build/build_threadx_demo.bat @@ -0,0 +1,4 @@ +armasm -g --cpu=cortex-m7 --apcs=interwork tx_initialize_low_level.S +armcc -c -g --cpu=cortex-m7 -O2 -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc sample_threadx.c +armlink -d -o sample_threadx.axf --elf --map --ro-base=0x00000000 --rw-base=0x20000000 --first __tx_vectors --datacompressor=off --inline --info=inline --callgraph --list sample_threadx.map tx_initialize_low_level.o sample_threadx.o tx.a + diff --git a/ports_module/cortex-m7/ac5/example_build/build_threadx_module_demo.bat b/ports_module/cortex-m7/ac5/example_build/build_threadx_module_demo.bat new file mode 100644 index 00000000..ed0f8e49 --- /dev/null +++ b/ports_module/cortex-m7/ac5/example_build/build_threadx_module_demo.bat @@ -0,0 +1,3 @@ +armasm -g --cpu=cortex-m7 --fpu=softvfp --apcs=/interwork/ropi/rwpi txm_module_preamble.S +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi --lower_ropi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc sample_threadx_module.c +armlink -d -o sample_threadx_module.axf --elf --ro=0x30000 --rw=0x40000 --first txm_module_preamble.o(Init) --entry=_txm_module_thread_shell_entry --ropi --rwpi --remove --map --symbols --list sample_threadx_module.map txm_module_preamble.o sample_threadx_module.o txm.a diff --git a/ports_module/cortex-m7/ac5/example_build/build_threadx_module_library.bat b/ports_module/cortex-m7/ac5/example_build/build_threadx_module_library.bat new file mode 100644 index 00000000..e08cb5ca --- /dev/null +++ b/ports_module/cortex-m7/ac5/example_build/build_threadx_module_library.bat @@ -0,0 +1,106 @@ +del txm.a + +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_allocate.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_pool_create.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_pool_delete.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_pool_info_get.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_pool_performance_info_get.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_pool_performance_system_info_get.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_pool_prioritize.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_release.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_allocate.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_pool_create.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_pool_delete.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_pool_info_get.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_pool_performance_info_get.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_pool_performance_system_info_get.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_pool_prioritize.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_release.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_create.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_delete.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_get.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_info_get.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_performance_info_get.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_performance_system_info_get.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_set.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_set_notify.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_module_application_request.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_module_callback_request_thread_entry.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_module_object_allocate.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_module_object_deallocate.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_module_object_pointer_get.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_module_thread_system_suspend.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_create.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_delete.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_get.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_info_get.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_performance_info_get.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_performance_system_info_get.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_prioritize.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_put.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_create.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_delete.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_flush.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_front_send.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_info_get.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_performance_info_get.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_performance_system_info_get.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_prioritize.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_receive.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_send.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_send_notify.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_ceiling_put.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_create.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_delete.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_get.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_info_get.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_performance_info_get.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_performance_system_info_get.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_prioritize.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_put.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_put_notify.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_create.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_delete.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_entry_exit_notify.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_identify.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_info_get.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_interrupt_control.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_performance_info_get.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_performance_system_info_get.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_preemption_change.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_priority_change.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_relinquish.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_reset.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_resume.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_sleep.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_stack_error_notify.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_suspend.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_terminate.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_time_slice_change.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_wait_abort.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_time_get.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_time_set.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_activate.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_change.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_create.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_deactivate.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_delete.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_info_get.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_performance_info_get.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_performance_system_info_get.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_buffer_full_notify.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_disable.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_enable.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_event_filter.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_event_unfilter.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_isr_enter_insert.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_isr_exit_insert.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_user_event_insert.c +armcc -g --cpu=cortex-m7 --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ..//module_lib/src/txm_module_thread_shell_entry.c +armasm -g --cpu=cortex-m7 --fpu=softvfp --apcs=/interwork/ropi/rwpi --cpreproc --cpreproc_opts=-D,TXM_ASSEMBLY --cpreproc_opts=-D,TXM_MODULE_HEAP_SIZE=512 -I../inc ../module_lib/src/txm_module_initialize.S + +armar --create txm.a txm_block_allocate.o txm_block_pool_create.o txm_block_pool_delete.o txm_block_pool_info_get.o txm_block_pool_performance_info_get.o txm_block_pool_performance_system_info_get.o txm_block_pool_prioritize.o txm_block_release.o txm_byte_allocate.o txm_byte_pool_create.o txm_byte_pool_delete.o txm_byte_pool_info_get.o txm_byte_pool_performance_info_get.o txm_byte_pool_performance_system_info_get.o txm_byte_pool_prioritize.o txm_byte_release.o txm_event_flags_create.o txm_event_flags_delete.o txm_event_flags_get.o txm_event_flags_info_get.o txm_event_flags_performance_info_get.o txm_event_flags_performance_system_info_get.o txm_event_flags_set.o txm_event_flags_set_notify.o txm_module_application_request.o txm_module_callback_request_thread_entry.o txm_module_initialize.o txm_module_object_allocate.o txm_module_object_deallocate.o txm_module_object_pointer_get.o txm_module_thread_shell_entry.o txm_module_thread_system_suspend.o txm_mutex_create.o txm_mutex_delete.o txm_mutex_get.o + +armar -r txm.a txm_mutex_info_get.o txm_mutex_performance_info_get.o txm_mutex_performance_system_info_get.o txm_mutex_prioritize.o txm_mutex_put.o txm_queue_create.o txm_queue_delete.o txm_queue_flush.o txm_queue_front_send.o txm_queue_info_get.o txm_queue_performance_info_get.o txm_queue_performance_system_info_get.o txm_queue_prioritize.o txm_queue_receive.o txm_queue_send.o txm_queue_send_notify.o txm_semaphore_ceiling_put.o txm_semaphore_create.o txm_semaphore_delete.o txm_semaphore_get.o txm_semaphore_info_get.o txm_semaphore_performance_info_get.o txm_semaphore_performance_system_info_get.o txm_semaphore_prioritize.o txm_semaphore_put.o txm_semaphore_put_notify.o txm_thread_create.o txm_thread_delete.o txm_thread_entry_exit_notify.o txm_thread_identify.o txm_thread_info_get.o txm_thread_interrupt_control.o txm_thread_performance_info_get.o txm_thread_performance_system_info_get.o txm_thread_preemption_change.o txm_thread_priority_change.o txm_thread_relinquish.o txm_thread_reset.o txm_thread_resume.o + +armar -r txm.a txm_thread_sleep.o txm_thread_stack_error_notify.o txm_thread_suspend.o txm_thread_terminate.o txm_thread_time_slice_change.o txm_thread_wait_abort.o txm_time_get.o txm_time_set.o txm_timer_activate.o txm_timer_change.o txm_timer_create.o txm_timer_deactivate.o txm_timer_delete.o txm_timer_info_get.o txm_timer_performance_info_get.o txm_timer_performance_system_info_get.o txm_trace_buffer_full_notify.o txm_trace_disable.o txm_trace_enable.o txm_trace_event_filter.o txm_trace_event_unfilter.o txm_trace_isr_enter_insert.o txm_trace_isr_exit_insert.o txm_trace_user_event_insert.o diff --git a/ports_module/cortex-m7/ac5/example_build/build_threadx_module_manager_demo.bat b/ports_module/cortex-m7/ac5/example_build/build_threadx_module_manager_demo.bat new file mode 100644 index 00000000..095ffe96 --- /dev/null +++ b/ports_module/cortex-m7/ac5/example_build/build_threadx_module_manager_demo.bat @@ -0,0 +1,3 @@ +armasm -g --cpu=cortex-m7 --fpu=softvfp --apcs=interwork tx_initialize_low_level.S +armcc -g --cpu=cortex-m7 --fpu=softvfp -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc sample_threadx_module_manager.c +armlink -d -o sample_threadx_module_manager.axf --elf --ro 0x00000000 --first tx_initialize_low_level.o(RESET) --remove --map --symbols --list sample_threadx_module_manager.map tx_initialize_low_level.o sample_threadx_module_manager.o tx.a diff --git a/ports_module/cortex-m7/ac5/example_build/clean.bat b/ports_module/cortex-m7/ac5/example_build/clean.bat new file mode 100644 index 00000000..3217f01b --- /dev/null +++ b/ports_module/cortex-m7/ac5/example_build/clean.bat @@ -0,0 +1,2 @@ +@ECHO OFF +DEL *.o *.a *.axf *.map diff --git a/ports_module/cortex-m7/ac5/example_build/sample_threadx.c b/ports_module/cortex-m7/ac5/example_build/sample_threadx.c new file mode 100644 index 00000000..418ec634 --- /dev/null +++ b/ports_module/cortex-m7/ac5/example_build/sample_threadx.c @@ -0,0 +1,369 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports_module/cortex-m7/ac5/example_build/sample_threadx_module.c b/ports_module/cortex-m7/ac5/example_build/sample_threadx_module.c new file mode 100644 index 00000000..f2647144 --- /dev/null +++ b/ports_module/cortex-m7/ac5/example_build/sample_threadx_module.c @@ -0,0 +1,432 @@ +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, + event flags group, byte pool, and block pool. */ + +/* Specify that this is a module! */ + +#define TXM_MODULE + + +/* Include the ThreadX module definitions. */ + +#include "txm_module.h" + + +/* Define constants. */ + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the external memory area. */ + +#define EXTERNAL_MEMORY_SIZE (64 * 1024) +#define EXTERNAL_MEMORY (0x80000) + + +/* Define the pool space in the bss section of the module. ULONG is used to + get the word alignment. */ + +ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD *thread_0; +TX_THREAD *thread_1; +TX_THREAD *thread_2; +TX_THREAD *thread_3; +TX_THREAD *thread_4; +TX_THREAD *thread_5; +TX_THREAD *thread_6; +TX_THREAD *thread_7; +TX_QUEUE *queue_0; +TX_SEMAPHORE *semaphore_0; +TX_MUTEX *mutex_0; +TX_EVENT_FLAGS_GROUP *event_flags_0; +TX_BYTE_POOL *byte_pool_0; +TX_BLOCK_POOL *block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; +ULONG semaphore_0_puts; +ULONG event_0_sets; +ULONG queue_0_sends; + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + +void semaphore_0_notify(TX_SEMAPHORE *semaphore_ptr) +{ + + if (semaphore_ptr == semaphore_0) + semaphore_0_puts++; +} + + +void event_0_notify(TX_EVENT_FLAGS_GROUP *event_flag_group_ptr) +{ + + if (event_flag_group_ptr == event_flags_0) + event_0_sets++; +} + + +void queue_0_notify(TX_QUEUE *queue_ptr) +{ + + if (queue_ptr == queue_0) + queue_0_sends++; +} + + +/* Define the module start function. */ + +void demo_module_start(ULONG id) +{ + +CHAR *pointer; + + /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + the control block(s). */ + txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_2, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_3, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_4, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_5, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_6, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_7, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&queue_0, sizeof(TX_QUEUE)); + txm_module_object_allocate((void*)&semaphore_0, sizeof(TX_SEMAPHORE)); + txm_module_object_allocate((void*)&mutex_0, sizeof(TX_MUTEX)); + txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); + txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); + txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(queue_0, "module queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + tx_queue_send_notify(queue_0, queue_0_notify); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(semaphore_0, "module semaphore 0", 1); + + tx_semaphore_put_notify(semaphore_0, semaphore_0_notify); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(event_flags_0, "module event flags 0"); + + tx_event_flags_set_notify(event_flags_0, event_0_notify); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(mutex_0, "module mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(block_pool_0, "module block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + /* Test external memory sharing. */ + *(ULONG *)EXTERNAL_MEMORY = 0xABABABAB; + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + diff --git a/ports_module/cortex-m7/ac5/example_build/sample_threadx_module_manager.c b/ports_module/cortex-m7/ac5/example_build/sample_threadx_module_manager.c new file mode 100644 index 00000000..210f0be0 --- /dev/null +++ b/ports_module/cortex-m7/ac5/example_build/sample_threadx_module_manager.c @@ -0,0 +1,126 @@ +/* Small demonstration of the ThreadX module manager. */ + +#include "tx_api.h" +#include "txm_module.h" + + +#define DEMO_STACK_SIZE 1024 + +/* Define the ThreadX object control blocks... */ + +TX_THREAD module_manager; +TXM_MODULE_INSTANCE my_module; + + +/* Define the object pool area. */ + +UCHAR object_memory[16384]; + + +/* Define the module data pool area. */ + +#define MODULE_DATA_SIZE (256 * 1024) +#define MODULE_DATA (0x40000) + + +/* The module code should be loaded here. */ + +#define MODULE_CODE (0x30000) + + +/* Define the external memory area. */ + +#define EXTERNAL_MEMORY_SIZE (64 * 1024) +#define EXTERNAL_MEMORY (0x80000) + + +/* Define the count of memory faults. */ + +ULONG memory_faults; + + +/* Define thread prototypes. */ + +void module_manager_entry(ULONG thread_input); + + +/* Define fault handler. */ + +VOID module_fault_handler(TX_THREAD *thread, TXM_MODULE_INSTANCE *module) +{ + + /* Just increment the fault counter. */ + memory_faults++; +} + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = (CHAR*)first_unused_memory; + + + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + pointer = pointer + DEMO_STACK_SIZE; +} + + + + +/* Define the test threads. */ + +void module_manager_entry(ULONG thread_input) +{ + + /* Initialize the module manager. */ + txm_module_manager_initialize((void *) MODULE_DATA, MODULE_DATA_SIZE); + + txm_module_manager_object_pool_create(object_memory, sizeof(object_memory)); + + /* Register a fault handler. */ + txm_module_manager_memory_fault_notify(module_fault_handler); + + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ + txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE); + + /* Enable a read/write shared memory region. */ + txm_module_manager_external_memory_enable(&my_module, (void *) EXTERNAL_MEMORY, EXTERNAL_MEMORY_SIZE, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); + + /* Start the module. */ + txm_module_manager_start(&my_module); + + /* Sleep for a while.... */ + tx_thread_sleep(1000); + + /* Stop the module. */ + txm_module_manager_stop(&my_module); + + /* Unload the module. */ + txm_module_manager_unload(&my_module); + + /* Load the module that is already there. */ + txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE); + + /* Start the module again. */ + txm_module_manager_start(&my_module); + + /* Now just spin... */ + while(1) + { + + tx_thread_sleep(100); + } +} diff --git a/ports_module/cortex-m7/ac5/example_build/setenv.bat b/ports_module/cortex-m7/ac5/example_build/setenv.bat new file mode 100644 index 00000000..965f12f3 --- /dev/null +++ b/ports_module/cortex-m7/ac5/example_build/setenv.bat @@ -0,0 +1,13 @@ +@echo off + +REM *** ARM DS 2020 +REM SET PATH=%ProgramFiles%\Arm\Development Studio 2020.0\sw\ARMCompiler5.06u6\bin;%PATH% +REM SET ARMLMD_LICENSE_FILE=%APPDATA%\arm\ds\licenses +REM SET ARM_CONFIG_PATH=%APPDATA%\arm\ds\2020.0 +REM SET ARM_PRODUCT_DEF=%ProgramFiles%\Arm\Development Studio 2020.0\sw\mappings\gold.elmap + +REM *** legacy ARM DS 5 +SET PATH=%ProgramFiles%\DS-5 v5.29.3\sw\ARMCompiler5.06u6\bin;%PATH% +SET ARMLMD_LICENSE_FILE=%APPDATA%\ARM\DS-5\licenses +SET ARM_CONFIG_PATH=%APPDATA%\ARM\DS-5_v5.29.3 +SET ARM_PRODUCT_PATH=%ProgramFiles%\DS-5 v5.29.3\sw\mappings diff --git a/ports_module/cortex-m7/ac5/example_build/tx_initialize_low_level.S b/ports_module/cortex-m7/ac5/example_build/tx_initialize_low_level.S new file mode 100644 index 00000000..bdc41ea8 --- /dev/null +++ b/ports_module/cortex-m7/ac5/example_build/tx_initialize_low_level.S @@ -0,0 +1,285 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_initialize.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IMPORT _tx_thread_system_stack_ptr + IMPORT _tx_initialize_unused_memory + IMPORT _tx_thread_context_save + IMPORT _tx_thread_context_restore + IMPORT _tx_timer_interrupt + IMPORT __main + IMPORT |Image$$RO$$Limit| + IMPORT |Image$$RW$$Base| + IMPORT |Image$$ZI$$Base| + IMPORT |Image$$ZI$$Limit| + IMPORT __tx_PendSVHandler + IMPORT __tx_SVCallHandler + IMPORT MemManage_Handler +; +; +SYSTEM_CLOCK EQU 6000000 +SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1) +; +; +;/* Setup the stack and heap areas. */ +; +STACK_SIZE EQU 0x00000400 +HEAP_SIZE EQU 0x00000000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +StackMem + SPACE STACK_SIZE +__initial_sp + + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +HeapMem + SPACE HEAP_SIZE +__heap_limit + + + AREA RESET, CODE, READONLY +; + EXPORT __tx_vectors + EXPORT __vector_table +__vector_table +__tx_vectors + DCD __initial_sp ; Reset and system stack ptr + DCD Reset_Handler ; Reset goes to startup function + DCD __tx_NMIHandler ; NMI + DCD __tx_BadHandler ; HardFault + DCD MemManage_Handler ; MemManage + DCD 0 ; BusFault + DCD 0 ; UsageFault + DCD 0 ; 7 + DCD 0 ; 8 + DCD 0 ; 9 + DCD 0 ; 10 + DCD __tx_SVCallHandler ; SVCall + DCD __tx_DBGHandler ; Monitor + DCD 0 ; 13 + DCD __tx_PendSVHandler ; PendSV + DCD __tx_SysTickHandler ; SysTick + DCD __tx_IntHandler ; Int 0 + DCD __tx_IntHandler ; Int 1 + DCD __tx_IntHandler ; Int 2 + DCD __tx_IntHandler ; Int 3 + +; +; + AREA ||.text||, CODE, READONLY + EXPORT Reset_Handler +Reset_Handler + CPSID i + IF {TARGET_FPU_VFP} = {TRUE} + LDR r0, =0xE000ED88 ; Pickup address of CPACR + LDR r1, [r0] ; Pickup CPACR + MOV32 r2, 0x00F00000 ; Build enable value + ORR r1, r1, r2 ; Or in enable value + STR r1, [r0] ; Setup CPACR + ENDIF + LDR r0, =__main + BX r0 + + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-M7/MPU/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + EXPORT _tx_initialize_low_level +_tx_initialize_low_level +; +; /* Disable interrupts during ThreadX initialization. */ +; + CPSID i +; +; /* Set base of available memory to end of non-initialised RAM area. */ +; + LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer + LDR r1, =|Image$$ZI$$Limit| ; Build first free address + ADD r1, r1, #4 ; + STR r1, [r0] ; Setup first unused memory pointer +; +; /* Setup Vector Table Offset Register. */ +; + MOV r0, #0xE000E000 ; Build address of NVIC registers + LDR r1, =__tx_vectors ; Pickup address of vector table + STR r1, [r0, #0xD08] ; Set vector table address +; +; /* Enable the cycle count register. */ +; +; LDR r0, =0xE0001000 ; Build address of DWT register +; LDR r1, [r0] ; Pickup the current value +; ORR r1, r1, #1 ; Set the CYCCNTENA bit +; STR r1, [r0] ; Enable the cycle count register +; +; /* Set system stack pointer from vector value. */ +; + LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer + LDR r1, =__tx_vectors ; Pickup address of vector table + LDR r1, [r1] ; Pickup reset stack pointer + STR r1, [r0] ; Save system stack pointer +; +; /* Configure SysTick. */ +; + MOV r0, #0xE000E000 ; Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] ; Setup SysTick Reload Value + MOV r1, #0x7 ; Build SysTick Control Enable Value + STR r1, [r0, #0x10] ; Setup SysTick Control +; +; /* Configure handler priorities. */ +; + LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] ; Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] ; Setup System Handlers 8-11 Priority Registers + ; Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] ; Setup System Handlers 12-15 Priority Registers + ; Note: PnSV must be lowest priority, which is 0xFF +; +; /* Return to caller. */ +; + BX lr +;} +; +; +;/* Define initial heap/stack routine for the ARM RVCT startup code. +; This routine will set the initial stack and heap locations */ +; + EXPORT __user_initial_stackheap +__user_initial_stackheap + LDR r0, =HeapMem + LDR r1, =(StackMem + STACK_SIZE) + LDR r2, =(HeapMem + HEAP_SIZE) + LDR r3, =StackMem + BX lr +; +; +;/* Define shells for each of the unused vectors. */ +; + EXPORT __tx_BadHandler +__tx_BadHandler + B __tx_BadHandler + +; EXPORT __tx_SVCallHandler +;__tx_SVCallHandler +; B __tx_SVCallHandler + + EXPORT __tx_IntHandler +__tx_IntHandler +; VOID InterruptHandler (VOID) +; { + PUSH {lr} + +; /* Do interrupt handler work here */ +; /* .... */ + + POP {lr} + BX LR +; } + + EXPORT __tx_SysTickHandler +__tx_SysTickHandler +; VOID TimerInterruptHandler (VOID) +; { +; + PUSH {lr} + BL _tx_timer_interrupt + POP {lr} + BX LR +; } + + EXPORT __tx_NMIHandler +__tx_NMIHandler + B __tx_NMIHandler + + EXPORT __tx_DBGHandler +__tx_DBGHandler + B __tx_DBGHandler + + EXPORT _tx_execution_thread_enter +_tx_execution_thread_enter + BX LR + + EXPORT _tx_execution_thread_exit +_tx_execution_thread_exit + BX LR + + ALIGN + LTORG + END + + diff --git a/ports_module/cortex-m7/ac5/example_build/txm_module_preamble.S b/ports_module/cortex-m7/ac5/example_build/txm_module_preamble.S new file mode 100644 index 00000000..1e7a1800 --- /dev/null +++ b/ports_module/cortex-m7/ac5/example_build/txm_module_preamble.S @@ -0,0 +1,69 @@ + AREA Init, CODE, READONLY + + PRESERVE8 + + ; Define public symbols + + EXPORT __txm_module_preamble + + + ; Define application-specific start/stop entry points for the module + + EXTERN demo_module_start + + + ; Define common external references + + IMPORT _txm_module_thread_shell_entry + IMPORT _txm_module_callback_request_thread_entry + IMPORT |Image$$ER_RO$$Length| + IMPORT |Image$$ER_RW$$Length| + IMPORT |Image$$ER_RW$$RW$$Length| + IMPORT |Image$$ER_RW$$ZI$$Length| + IMPORT |Image$$ER_ZI$$ZI$$Length| + +__txm_module_preamble + DCD 0x4D4F4455 ; Module ID + DCD 0x6 ; Module Major Version + DCD 0x1 ; Module Minor Version + DCD 32 ; Module Preamble Size in 32-bit words + DCD 0x12345678 ; Module ID (application defined) + DCD 0x01000007 ; Module Properties where: + ; Bits 31-24: Compiler ID + ; 0 -> IAR + ; 1 -> ARM + ; 2 -> GNU + ; Bit 0: 0 -> Privileged mode execution + ; 1 -> User mode execution + ; Bit 1: 0 -> No MPU protection + ; 1 -> MPU protection (must have user mode selected) + ; Bit 2: 0 -> Disable shared/external memory access + ; 1 -> Enable shared/external memory access + DCD _txm_module_thread_shell_entry - __txm_module_preamble ; Module Shell Entry Point + DCD demo_module_start - __txm_module_preamble ; Module Start Thread Entry Point + DCD 0 ; Module Stop Thread Entry Point + DCD 1 ; Module Start/Stop Thread Priority + DCD 1024 ; Module Start/Stop Thread Stack Size + DCD _txm_module_callback_request_thread_entry - __txm_module_preamble ; Module Callback Thread Entry + DCD 1 ; Module Callback Thread Priority + DCD 1024 ; Module Callback Thread Stack Size + DCD |Image$$ER_RO$$Length| + |Image$$ER_RW$$Length| ; Module Code Size + DCD |Image$$ER_RW$$Length| + |Image$$ER_ZI$$ZI$$Length| ; Module Data Size + DCD 0 ; Reserved 0 + DCD 0 ; Reserved 1 + DCD 0 ; Reserved 2 + DCD 0 ; Reserved 3 + DCD 0 ; Reserved 4 + DCD 0 ; Reserved 5 + DCD 0 ; Reserved 6 + DCD 0 ; Reserved 7 + DCD 0 ; Reserved 8 + DCD 0 ; Reserved 9 + DCD 0 ; Reserved 10 + DCD 0 ; Reserved 11 + DCD 0 ; Reserved 12 + DCD 0 ; Reserved 13 + DCD 0 ; Reserved 14 + DCD 0 ; Reserved 15 + + END diff --git a/ports_module/cortex-m7/ac5/inc/tx_port.h b/ports_module/cortex-m7/ac5/inc/tx_port.h index c4153b1d..0962e1d9 100644 --- a/ports_module/cortex-m7/ac5/inc/tx_port.h +++ b/ports_module/cortex-m7/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M7/AC5 */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -113,7 +113,7 @@ typedef unsigned short USHORT; #endif -/* Define various constants for the ThreadX Cortex-M3 port. */ +/* Define various constants for the ThreadX Cortex-M7 port. */ #define TX_INT_DISABLE 1 /* Disable interrupts */ #define TX_INT_ENABLE 0 /* Enable interrupts */ @@ -128,15 +128,9 @@ typedef unsigned short USHORT; */ -#ifndef TX_MISRA_ENABLE #ifndef TX_TRACE_TIME_SOURCE #define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) #endif -#else -ULONG _tx_misra_time_stamp_get(VOID); -#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() -#endif - #ifndef TX_TRACE_TIME_MASK #define TX_TRACE_TIME_MASK 0xFFFFFFFFUL #endif @@ -145,18 +139,14 @@ ULONG _tx_misra_time_stamp_get(VOID); /* Define the port specific options for the _tx_build_options variable. This variable indicates how the ThreadX library was built. */ -#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0) +#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0 /* Define the in-line initialization constant so that modules with in-line initialization capabilities can prevent their initialization from being a function call. */ -#ifdef TX_MISRA_ENABLE -#define TX_DISABLE_INLINE -#else #define TX_INLINE_INITIALIZATION -#endif /* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is @@ -165,19 +155,17 @@ ULONG _tx_misra_time_stamp_get(VOID); define is negated, thereby forcing the stack fill which is necessary for the stack checking logic. */ -#ifndef TX_MISRA_ENABLE #ifdef TX_ENABLE_STACK_CHECKING #undef TX_DISABLE_STACK_FILLING #endif -#endif /* Define the TX_THREAD control block extensions for this port. The main reason for the multiple macros is so that backward compatibility can be maintained with existing ThreadX kernel awareness modules. */ -#define TX_THREAD_EXTENSION_0 -#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 #define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ VOID *tx_thread_module_entry_info_ptr; \ ULONG tx_thread_module_current_user_mode; \ @@ -191,20 +179,23 @@ ULONG _tx_misra_time_stamp_get(VOID); VOID *tx_thread_module_stack_end; \ ULONG tx_thread_module_stack_size; \ VOID *tx_thread_module_reserved; -#define TX_THREAD_EXTENSION_3 +#define TX_THREAD_EXTENSION_3 /* Define the port extensions of the remaining ThreadX objects. */ #define TX_BLOCK_POOL_EXTENSION #define TX_BYTE_POOL_EXTENSION +#define TX_MUTEX_EXTENSION #define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); -#define TX_MUTEX_EXTENSION + #define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + #define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + #define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ VOID (*tx_timer_module_expiration_function)(ULONG id); @@ -224,14 +215,10 @@ ULONG _tx_misra_time_stamp_get(VOID); #define TX_THREAD_CREATE_EXTENSION(thread_ptr) #define TX_THREAD_DELETE_EXTENSION(thread_ptr) - #ifndef TX_MISRA_ENABLE - register unsigned int _ipsr __asm("ipsr"); - #endif - #ifdef __TARGET_FPU_VFP #ifdef TX_MISRA_ENABLE @@ -272,6 +259,7 @@ register ULONG _control __asm("control"); #endif + /* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush @@ -353,6 +341,8 @@ void _tx_vfp_access(void); #endif + + /* Define the ThreadX object creation extensions for the remaining objects. */ #define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) @@ -403,7 +393,7 @@ ULONG _tx_misra_ipsr_get(VOID); #define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; -/* Determine if the ARM architecture has the CLZ instruction. This is available on +/* This ARM architecture has the CLZ instruction. This is available on architectures v5 and above. If available, redefine the macro for calculating the lowest bit set. */ @@ -470,7 +460,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/AC5 Version 6.0.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/AC5 Version 6.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex-m7/ac5/inc/txm_module_port.h b/ports_module/cortex-m7/ac5/inc/txm_module_port.h index caf00eae..8f6be388 100644 --- a/ports_module/cortex-m7/ac5/inc/txm_module_port.h +++ b/ports_module/cortex-m7/ac5/inc/txm_module_port.h @@ -10,44 +10,55 @@ /**************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ -/**************************************************************************/ -/* */ -/* APPLICATION INTERFACE DEFINITION RELEASE */ -/* */ -/* txm_module_port.h Cortex-M7/MPU/AC5 */ -/* 6.0.1 */ +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* txm_module_port.h Cortex-M7/MPU/AC5 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This file defines the basic module constants, interface structures, */ -/* and function prototypes. */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the basic module constants, interface structures, */ +/* and function prototypes. */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H #define TXM_MODULE_PORT_H -/* It is assumed that the base ThreadX tx_port.h file has been modified to add the +/* Determine if the optional Modules user define file should be used. */ + +#ifdef TXM_MODULE_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in txm_module_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "txm_module_user.h" +#endif + +/* It is assumed that the base ThreadX tx_port.h file has been modified to add the following extensions to the ThreadX thread control block (this code should replace the corresponding macro define in tx_port.h): @@ -80,21 +91,14 @@ The following extensions must also be defined in tx_port.h: VOID (*tx_timer_module_expiration_function)(ULONG id); */ -#define TXM_MODULE_THREAD_ENTRY_INFO_USER_EXTENSION - -/**************************************************************************/ -/* User-adjustable constants */ -/**************************************************************************/ /* Size of module heap. */ #define TXM_MODULE_HEAP_SIZE 512 -#ifndef TXM_ASSEMBLY - /* Define the kernel stack size for a module thread. */ #ifndef TXM_MODULE_KERNEL_STACK_SIZE -#define TXM_MODULE_KERNEL_STACK_SIZE 512 +#define TXM_MODULE_KERNEL_STACK_SIZE 768 #endif /* For the following 3 access control settings, change TEX and C, B, S (bits 21 through 16 of MPU_RASR) @@ -106,11 +110,6 @@ The following extensions must also be defined in tx_port.h: /* Shared region access control: execute never, read-only, outer & inner write-back, normal memory, shareable. */ #define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 -/**************************************************************************/ -/* End of user-adjustable constants */ -/**************************************************************************/ - - /* Define constants specific to the tools the module can be built with for this particular modules port. */ @@ -162,12 +161,12 @@ The following extensions must also be defined in tx_port.h: /* Define other module port-specific constants. */ -/* Define INLINE_DECLARE to whitespace for ARM compiler. */ +/* Define INLINE_DECLARE to inline for ARM compiler. */ -#define INLINE_DECLARE +#define INLINE_DECLARE inline /* Define the number of MPU entries assigned to the code and data sections. - On Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access + On Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access to the kernel entry function, thus 15 remain for code and data protection. */ #define TXM_MODULE_MPU_TOTAL_ENTRIES 16 #define TXM_MODULE_MPU_CODE_ENTRIES 4 @@ -206,8 +205,9 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr; VOID *txm_module_manager_memory_fault_info_code_location; ULONG txm_module_manager_memory_fault_info_shcsr; - ULONG txm_module_manager_memory_fault_info_mmfsr; + ULONG txm_module_manager_memory_fault_info_cfsr; ULONG txm_module_manager_memory_fault_info_mmfar; + ULONG txm_module_manager_memory_fault_info_bfar; ULONG txm_module_manager_memory_fault_info_control; ULONG txm_module_manager_memory_fault_info_sp; ULONG txm_module_manager_memory_fault_info_r0; @@ -231,18 +231,6 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT #define TXM_MODULE_MANAGER_FAULT_INFO \ TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info; -/* Define the macro to check the stack available in dispatch. */ -#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE \ - ULONG stack_available; \ - __asm("MOV %0, SP" : "=r"(stack_available)); \ - stack_available -= (ULONG)_tx_thread_current_ptr->tx_thread_stack_start; \ - if((stack_available < TXM_MODULE_MINIMUM_STACK_AVAILABLE) || \ - (stack_available > _tx_thread_current_ptr->tx_thread_stack_size)) \ - { \ - return(TX_SIZE_ERROR); \ - } - - /* Define the macro to check the code alignment. */ #define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment) \ @@ -327,20 +315,11 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT #define TXM_MODULE_MANAGER_MODULE_UNLOAD(module_instance) -/* Define the macro to perform port-specific functions when passing pointer to kernel. */ -#define TXM_MODULE_MANAGER_CHECK_DATA_POINTER(module_instance, pointer) \ - if(_txm_module_manager_data_pointer_check(module_instance, pointer)) \ - { return(TXM_MODULE_INVALID_MEMORY); } +/* Define the macros to perform port-specific checks when passing pointers to the kernel. */ -/* Define the macro to perform port-specific functions when passing function pointer to kernel. */ -/* Determine if the pointer is within the module's code memory. */ -#define TXM_MODULE_MANAGER_CHECK_FUNCTION_POINTER(module_instance, pointer) \ - if (((pointer < sizeof(TXM_MODULE_PREAMBLE) + (ULONG) module_instance -> txm_module_instance_code_start) || \ - ((pointer+sizeof(pointer)) > (ULONG) module_instance -> txm_module_instance_code_end)) \ - && (pointer != (ULONG) TX_NULL)) \ - { \ - return(TX_PTR_ERROR); \ - } +/* Define macro to make sure object is inside the module's data. */ +#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ + _txm_module_manager_inside_data_check(module_instance, obj_ptr, obj_size) /* Define some internal prototypes to this module port. */ @@ -351,21 +330,16 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT #define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES \ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment); \ -ULONG _txm_module_manager_data_pointer_check(TXM_MODULE_INSTANCE *module_instance, ULONG pointer); \ VOID _txm_module_manager_memory_fault_handler(VOID); \ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)); \ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \ ULONG _txm_power_of_two_block_size(ULONG size); \ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); \ ULONG _txm_module_manager_region_size_get(ULONG block_size); \ -ULONG _txm_module_manager_pointer_check(TXM_MODULE_INSTANCE *module_instance, ULONG pointer); \ -UCHAR _txm_module_manager_shared_memory_check_outside(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size); \ -UCHAR _txm_module_manager_shared_memory_check_inside(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size); \ -UCHAR _txm_module_manager_shared_memory_check_inside_byte(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr); +UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size); #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M7/MPU/AC5 Version 6.0.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M7/MPU/AC5 Version 6.1 *"; -#endif /* ifndef TXM_ASSEMBLY */ #endif diff --git a/ports_module/cortex-m7/ac5/module_lib/src/txm_module_initialize.s b/ports_module/cortex-m7/ac5/module_lib/src/txm_module_initialize.s index 8563b535..a7f8aa0b 100644 --- a/ports_module/cortex-m7/ac5/module_lib/src/txm_module_initialize.s +++ b/ports_module/cortex-m7/ac5/module_lib/src/txm_module_initialize.s @@ -10,70 +10,57 @@ ;/**************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Module */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ -; -; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" - -#include "txm_module_port.h" - +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Module */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; IMPORT __use_two_region_memory IMPORT __scatterload IMPORT txm_heap - - + AREA ||.text||, CODE, READONLY -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _txm_module_initialize Cortex-M7/MPU/AC5 */ -;/* 6.0.1 */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _txm_module_initialize Cortex-M7/MPU/AC5 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function initializes the module c runtime. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* __scatterload Initialize C runtime */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _txm_module_thread_shell_entry Start module thread */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function initializes the module c runtime. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* __scatterload Initialize C runtime */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _txm_module_thread_shell_entry Start module thread */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _txm_module_initialize(VOID) @@ -81,7 +68,7 @@ EXPORT _txm_module_initialize _txm_module_initialize PUSH {r4-r12,lr} ; Save dregs and LR - + B __scatterload ; Call ARM func to initialize variables ; @@ -89,7 +76,7 @@ _txm_module_initialize ; EXPORT __rt_exit __rt_exit - + POP {r4-r12,lr} ; Restore dregs and LR BX lr ; Return to caller ; @@ -106,12 +93,12 @@ __user_setup_stackheap MOV r2, #TXM_MODULE_HEAP_SIZE ; load heap size ADD r2, r2, r0 ; calculate heap end address BX lr - + ALIGN 4 _tx_heap_offset DCDO txm_heap AREA ||.arm_vfe_header||, DATA, READONLY, NOALLOC, ALIGN=2 - + IMPORT txm_heap [DATA] ; @@ -121,6 +108,5 @@ _tx_heap_offset EXPORT main main BX lr - - END + END diff --git a/ports_module/cortex-m7/ac5/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex-m7/ac5/module_lib/src/txm_module_thread_shell_entry.c index b6567baf..cb74cdd3 100644 --- a/ports_module/cortex-m7/ac5/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex-m7/ac5/module_lib/src/txm_module_thread_shell_entry.c @@ -10,15 +10,15 @@ /**************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #ifndef TXM_MODULE #define TXM_MODULE @@ -49,48 +49,48 @@ extern VOID _txm_module_initialize(VOID); __align(8) UCHAR txm_heap[TXM_MODULE_HEAP_SIZE]; -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_thread_shell_entry Cortex-M7/MPU/AC5 */ -/* 6.0.1 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_thread_shell_entry Cortex-M7/MPU/AC5 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function calls the specified entry function of the thread. It */ -/* also provides a place for the thread's entry function to return. */ -/* If the thread returns, this function places the thread in a */ -/* "COMPLETED" state. */ -/* */ -/* INPUT */ -/* */ -/* thread_ptr Pointer to current thread */ -/* thread_info Pointer to thread entry info */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* _txm_module_initialize cstartup initialization */ -/* thread_entry Thread's entry function */ -/* tx_thread_resume Resume the module callback thread */ -/* _txm_module_thread_system_suspend Module thread suspension routine */ -/* */ -/* CALLED BY */ -/* */ -/* Initial thread stack frame */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function calls the specified entry function of the thread. It */ +/* also provides a place for the thread's entry function to return. */ +/* If the thread returns, this function places the thread in a */ +/* "COMPLETED" state. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to current thread */ +/* thread_info Pointer to thread entry info */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_initialize cstartup initialization */ +/* thread_entry Thread's entry function */ +/* tx_thread_resume Resume the module callback thread */ +/* _txm_module_thread_system_suspend Module thread suspension routine */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) @@ -101,25 +101,23 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN #endif - /* Determine if this is the start thread. If so, we must prepare the module for + /* Determine if this is the start thread. If so, we must prepare the module for execution. If not, simply skip the C startup code. */ if (thread_info -> txm_module_thread_entry_info_start_thread) { - /* Initialize the ARM C environment. */ _txm_module_initialize(); /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - /* Save the kernel function dispatch address. This is used to make all resident calls from + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { - /* Loop here, if an error is present getting the dispatch function pointer! An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ @@ -164,7 +162,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN #endif /* Call actual thread suspension routine. */ - _txm_module_thread_system_suspend(thread_ptr); + _txm_module_thread_system_suspend(thread_ptr); #ifdef TX_SAFETY_CRITICAL diff --git a/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_context_restore.s index 6d310a17..d63c29c8 100644 --- a/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_context_restore.s @@ -2,6 +2,11 @@ ;/* */ ;/* Copyright (c) Microsoft Corporation. All rights reserved. */ ;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ ;/**************************************************************************/ ; ; @@ -15,16 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; ; IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY IMPORT _tx_execution_isr_exit @@ -37,14 +32,16 @@ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ -;/* _tx_thread_context_restore Cortex-M4/AC5 */ -;/* 6.0.1 */ +;/* _tx_thread_context_restore Cortex-M7/AC5 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ ;/* This function restores the interrupt context if it is processing a */ ;/* nested interrupt. If not, it returns to the interrupt thread if no */ ;/* preemption is necessary. Otherwise, if preemption is necessary or */ @@ -70,7 +67,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_context_save.s b/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_context_save.s index 052c3e5a..55747b13 100644 --- a/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_context_save.s @@ -2,6 +2,11 @@ ;/* */ ;/* Copyright (c) Microsoft Corporation. All rights reserved. */ ;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ ;/**************************************************************************/ ; ; @@ -15,16 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; ; IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY IMPORT _tx_execution_isr_enter @@ -37,14 +32,16 @@ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ -;/* _tx_thread_context_save Cortex-M4/AC5 */ -;/* 6.0.1 */ +;/* _tx_thread_context_save Cortex-M7/AC5 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ ;/* This function saves the context of an executing thread in the */ ;/* beginning of interrupt processing. The function also ensures that */ ;/* the system stack is used upon return to the calling ISR. */ @@ -69,7 +66,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -82,11 +79,11 @@ _tx_thread_context_save ; PUSH {r0, lr} ; Save ISR lr BL _tx_execution_isr_enter ; Call the ISR enter function - POP {lr0, r} ; Recover ISR lr + POP {r0, lr} ; Recover ISR lr ENDIF ; ; /* Return to interrupt processing. */ -; +; BX lr ; Return to interrupt processing caller ;} ALIGN diff --git a/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_interrupt_control.s index e97c7a47..059053b5 100644 --- a/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_interrupt_control.s @@ -2,6 +2,11 @@ ;/* */ ;/* Copyright (c) Microsoft Corporation. All rights reserved. */ ;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ ;/**************************************************************************/ ; ; @@ -15,22 +20,14 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; ; AREA ||.text||, CODE, READONLY ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ -;/* _tx_thread_interrupt_control Cortex-M4/AC5 */ -;/* 6.0.1 */ +;/* _tx_thread_interrupt_control Cortex-M7/AC5 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -60,7 +57,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) @@ -77,4 +74,3 @@ _tx_thread_interrupt_control ; ;} END - diff --git a/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_interrupt_disable.s index e366e44b..0030e9a4 100644 --- a/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_interrupt_disable.s @@ -2,6 +2,11 @@ ;/* */ ;/* Copyright (c) Microsoft Corporation. All rights reserved. */ ;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ ;/**************************************************************************/ ; ; @@ -15,25 +20,17 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; ; AREA ||.text||, CODE, READONLY ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ -;/* _tx_thread_interrupt_disable Cortex-M4/AC5 */ -;/* 6.0.1 */ +;/* _tx_thread_interrupt_disable Cortex-M7/AC5 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ -;/* William E. Lamie, Microsoft Corporation. */ +;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ @@ -60,7 +57,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(UINT new_posture) diff --git a/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_interrupt_restore.s index 1d0bffb6..8bb8fea2 100644 --- a/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_interrupt_restore.s @@ -2,6 +2,11 @@ ;/* */ ;/* Copyright (c) Microsoft Corporation. All rights reserved. */ ;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ ;/**************************************************************************/ ; ; @@ -15,25 +20,17 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; ; AREA ||.text||, CODE, READONLY ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ -;/* _tx_thread_interrupt_restore Cortex-M4/AC5 */ -;/* 6.0.1 */ +;/* _tx_thread_interrupt_restore Cortex-M7/AC5 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ -;/* William E. Lamie, Microsoft Corporation. */ +;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ @@ -60,7 +57,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_interrupt_restore(UINT new_posture) diff --git a/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_schedule.s b/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_schedule.s index f096baa2..14329dfd 100644 --- a/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_schedule.s @@ -10,80 +10,73 @@ ;/**************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; - IMPORT _tx_thread_current_ptr - IMPORT _tx_thread_execute_ptr - IMPORT _tx_timer_time_slice - IMPORT _tx_thread_system_stack_ptr - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY - IMPORT _tx_execution_thread_enter - IMPORT _tx_execution_thread_exit + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_execute_ptr + IMPORT _tx_timer_time_slice + IMPORT _tx_thread_system_stack_ptr + IF :DEF: TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_thread_enter + IMPORT _tx_execution_thread_exit ENDIF - IMPORT _tx_thread_preempt_disable - IMPORT _txm_module_manager_memory_fault_handler - IMPORT _txm_module_manager_memory_fault_info + IMPORT _tx_thread_preempt_disable + IMPORT _txm_module_manager_memory_fault_handler + IMPORT _txm_module_manager_memory_fault_info + IMPORT _txm_module_priv + IMPORT _txm_module_user_mode_exit ; ; - AREA ||.text||, CODE, READONLY - THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_schedule Cortex-M7/MPU/AC5 */ -;/* 6.0.1 */ + AREA ||.text||, CODE, READONLY + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-M7/MPU/AC5 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ ;/* None */ -;/* */ -;/* CALLS */ -;/* */ +;/* */ +;/* OUTPUT */ +;/* */ ;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -96,16 +89,16 @@ _tx_thread_schedule ; from the PendSV handling routines below. */ ; ; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ -; +; MOV r0, #0 ; Build value for TX_FALSE LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag STR r0, [r2, #0] ; Clear preempt disable flag ; ; /* Clear CONTROL.FPCA bit so FPU registers aren't unnecessarily stacked. */ ; - IF :DEF:__ARMVFP__ + IF :DEF: __ARMVFP__ MRS r0, CONTROL ; Pickup current CONTROL register - BIC r0, r0, #4 ; Clear the FPCA bit + BIC r0, r0, #4 ; Clear the FPCA bit MSR CONTROL, r0 ; Setup new CONTROL register ENDIF ; @@ -113,28 +106,24 @@ _tx_thread_schedule ; LDR r0, =0xE000ED24 ; Build SHCSR address LDR r1, =0x70000 ; Enable Usage, Bus, and MemManage faults - STR r1, [r0] ; + STR r1, [r0] ; ; ; /* Enable interrupts */ ; CPSIE i -; +; ; /* Enter the scheduler for the first time. */ ; MOV r0, #0x10000000 ; Load PENDSVSET bit MOV r1, #0xE000E000 ; Load NVIC base STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR - NOP ; - NOP ; - NOP ; - NOP ; -__wait_loop - B __wait_loop -; -; /* We should never get here - ever! */ -; - BKPT 0xEF ; Setup error conditions - BX lr ; + DSB ; Complete all memory accesses + ISB ; Flush pipeline + +; /* Wait here for the PendSV to take place. */ + +__tx_wait_here + B __tx_wait_here ; Wait for the PendSV to happen ;} ; @@ -155,41 +144,44 @@ MemManage_Handler LDR r0, =0xE000ED24 ; Build SHCSR address LDR r1, [r0] ; Pickup SHCSR STR r1, [r12, #8] ; Save SHCSR - LDR r0, =0xE000ED28 ; Build MMFSR address - LDR r1, [r0] ; Pickup MMFSR (and other fault status too!) - STR r1, [r12, #12] ; Save MMFSR + LDR r0, =0xE000ED28 ; Build CFSR address + LDR r1, [r0] ; Pickup CFSR + STR r1, [r12, #12] ; Save CFSR LDR r0, =0xE000ED34 ; Build MMFAR address LDR r1, [r0] ; Pickup MMFAR STR r1, [r12, #16] ; Save MMFAR + LDR r0, =0xE000ED38 ; Build BFAR address + LDR r1, [r0] ; Pickup BFAR + STR r1, [r12, #20] ; Save BFAR MRS r0, CONTROL ; Pickup current CONTROL register - STR r0, [r12, #20] ; Save CONTROL + STR r0, [r12, #24] ; Save CONTROL MRS r1, PSP ; Pickup thread stack pointer - STR r1, [r12, #24] ; Save thread stack pointer + STR r1, [r12, #28] ; Save thread stack pointer LDR r0, [r1] ; Pickup saved r0 - STR r0, [r12, #28] ; Save r0 + STR r0, [r12, #32] ; Save r0 LDR r0, [r1, #4] ; Pickup saved r1 - STR r0, [r12, #32] ; Save r1 - STR r2, [r12, #36] ; Save r2 - STR r3, [r12, #40] ; Save r3 - STR r4, [r12, #44] ; Save r4 - STR r5, [r12, #48] ; Save r5 - STR r6, [r12, #52] ; Save r6 - STR r7, [r12, #56] ; Save r7 - STR r8, [r12, #60] ; Save r8 - STR r9, [r12, #64] ; Save r9 - STR r10,[r12, #68] ; Save r10 - STR r11,[r12, #72] ; Save r11 + STR r0, [r12, #36] ; Save r1 + STR r2, [r12, #40] ; Save r2 + STR r3, [r12, #44] ; Save r3 + STR r4, [r12, #48] ; Save r4 + STR r5, [r12, #52] ; Save r5 + STR r6, [r12, #56] ; Save r6 + STR r7, [r12, #60] ; Save r7 + STR r8, [r12, #64] ; Save r8 + STR r9, [r12, #68] ; Save r9 + STR r10,[r12, #72] ; Save r10 + STR r11,[r12, #76] ; Save r11 LDR r0, [r1, #16] ; Pickup saved r12 - STR r0, [r12, #76] ; Save r12 + STR r0, [r12, #80] ; Save r12 LDR r0, [r1, #20] ; Pickup saved lr - STR r0, [r12, #80] ; Save lr + STR r0, [r12, #84] ; Save lr LDR r0, [r1, #24] ; Pickup instruction address at point of fault STR r0, [r12, #4] ; Save point of fault LDR r0, [r1, #28] ; Pickup xPSR - STR r0, [r12, #84] ; Save xPSR + STR r0, [r12, #88] ; Save xPSR MRS r0, CONTROL ; Pickup current CONTROL register - BIC r0, r0, #1 ; Clear the UNPRIV bit + BIC r0, r0, #1 ; Clear the UNPRIV bit MSR CONTROL, r0 ; Setup new CONTROL register LDR r0, =0xE000ED28 ; Build the Memory Management Fault Status Register (MMFSR) @@ -199,7 +191,7 @@ MemManage_Handler ; Bit 7 = 1 -> MMFAR is valid STRB r1, [r0] ; Clear the MMFSR - IF :DEF:__ARMVFP__ + IF :DEF: __ARMVFP__ LDR r0, =0xE000EF34 ; Cleanup FPU context: Load FPCCR address LDR r1, [r0] ; Load FPCCR BIC r1, r1, #1 ; Clear the lazy preservation active bit @@ -208,7 +200,7 @@ MemManage_Handler BL _txm_module_manager_memory_fault_handler ; Call memory manager fault handler - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IF :DEF: TX_ENABLE_EXECUTION_CHANGE_NOTIFY ; ; /* Call the thread exit function to indicate the thread is no longer executing. */ ; @@ -233,17 +225,17 @@ MemManage_Handler ; ; /* Generic context PendSV handler. */ -; +; EXPORT PendSV_Handler EXPORT __tx_PendSVHandler PendSV_Handler __tx_PendSVHandler ; ; /* Get current thread value and new thread pointer. */ -; +; __tx_ts_handler - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IF :DEF: TX_ENABLE_EXECUTION_CHANGE_NOTIFY ; ; /* Call the thread exit function to indicate the thread is no longer executing. */ ; @@ -259,7 +251,7 @@ __tx_ts_handler LDR r1, [r0] ; Pickup current thread pointer ; ; /* Determine if there is a current thread to finish preserving. */ -; +; CBZ r1, __tx_ts_new ; If NULL, skip preservation ; ; /* Recover PSP and preserve current thread context. */ @@ -267,7 +259,7 @@ __tx_ts_handler STR r3, [r0] ; Set _tx_thread_current_ptr to NULL MRS r12, PSP ; Pickup PSP pointer (thread's stack pointer) STMDB r12!, {r4-r11} ; Save its remaining registers - IF :DEF:__ARMVFP__ + IF :DEF: __ARMVFP__ TST LR, #0x10 ; Determine if the VFP extended frame is present BNE _skip_vfp_save VSTMDB r12!,{s16-s31} ; Yes, save additional VFP registers @@ -290,7 +282,6 @@ _skip_vfp_save ; STR r3, [r4] ; Clear time-slice ; -; ; /* Executing thread is now completely preserved!!! */ ; __tx_ts_new @@ -319,7 +310,7 @@ __tx_ts_restore ; STR r5, [r4] ; Setup global time-slice - IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IF :DEF: TX_ENABLE_EXECUTION_CHANGE_NOTIFY ; ; /* Call the thread entry function to indicate the thread is executing. */ ; @@ -334,7 +325,7 @@ __tx_ts_restore MRS r5, CONTROL ; Pickup current CONTROL register LDR r4, [r1, #0x98] ; Pickup current user mode flag - BIC r5, r5, #1 ; Clear the UNPRIV bit + BIC r5, r5, #1 ; Clear the UNPRIV bit ORR r4, r4, r5 ; Build new CONTROL register MSR CONTROL, r4 ; Setup new CONTROL register @@ -343,7 +334,7 @@ __tx_ts_restore STR r3, [r0] ; Disable MPU LDR r0, [r1, #0x90] ; Pickup the module instance pointer CBZ r0, skip_mpu_setup ; Is this thread owned by a module? No, skip MPU setup - LDR r1, [r0, #0x64] ; Pickup MPU register[0] + LDR r1, [r0, #0x64] ; Pickup MPU register[0] CBZ r1, skip_mpu_setup ; Is protection required for this module? No, skip MPU setup LDR r1, =0xE000ED9C ; Build address of MPU base register @@ -362,9 +353,9 @@ __tx_ts_restore STR r1, [r0] ; Enable MPU skip_mpu_setup LDMIA r12!, {LR} ; Pickup LR - IF :DEF:__ARMVFP__ + IF :DEF: __ARMVFP__ TST LR, #0x10 ; Determine if the VFP extended frame is present - BNE _skip_vfp_restore ; If not, skip VFP restore + BNE _skip_vfp_restore ; If not, skip VFP restore VLDMIA r12!, {s16-s31} ; Yes, restore additional VFP registers _skip_vfp_restore ENDIF @@ -372,11 +363,11 @@ _skip_vfp_restore MSR PSP, r12 ; Setup the thread's stack pointer ; ; /* Return to thread. */ -; +; BX lr ; Return to thread! ; ; /* The following is the idle wait processing... in this case, no threads are ready for execution and the -; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts ; are disabled to allow use of WFI for waiting for a thread to arrive. */ ; __tx_ts_wait @@ -392,16 +383,16 @@ __tx_ts_wait CPSIE i ; Enable interrupts B __tx_ts_wait ; Loop to continue waiting ; -; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are ; already in the handler! */ ; __tx_ts_ready MOV r7, #0x08000000 ; Build clear PendSV value MOV r8, #0xE000E000 ; Build base NVIC address - STR r7, [r8, #0xD04] ; Clear any PendSV + STR r7, [r8, #0xD04] ; Clear any PendSV ; ; /* Re-enable interrupts and restore new thread. */ -; +; CPSIE i ; Enable interrupts B __tx_ts_restore ; Restore the thread ;} @@ -426,11 +417,11 @@ __tx_SVCallHandler ; At this point we have an SVC 1, which means we are entering the kernel from a module thread with user mode selected ; LDR r2, =_txm_module_priv ; Subtract 1 because of THUMB mode. - SUB r2, r2, #1 ; Temporary fix until ARM describes how to load label above correctly. + SUB r2, r2, #1 ; Temporary fix until ARM describes how to load label above correctly. CMP r1, r2 ; Did we come from user_mode_entry? IT NE ; If no (not equal), then... BXNE lr ; return from where we came. - + LDR r3, [r0, #20] ; This is the saved LR LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address LDR r2, [r1] ; Pickup current thread pointer @@ -439,74 +430,73 @@ __tx_SVCallHandler STR r3, [r2, #0xA0] ; Save the original LR in thread control block ; If there is memory protection, use kernel stack - LDR r0, [r2, #0x90] ; Load the module instance ptr - LDR r0, [r0, #0x0C] ; Load the module property flags - TST r0, #2 ; Check if memory protected + LDR r0, [r2, #0x90] ; Load the module instance ptr + LDR r0, [r0, #0x0C] ; Load the module property flags + TST r0, #2 ; Check if memory protected BEQ _tx_skip_kernel_stack_enter ; Switch to the module thread's kernel stack - LDR r0, [r2, #0xA8] ; Load the module kernel stack end - IF :LNOT: :DEF:TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE - LDR r1, [r2, #0xA4] ; Load the module kernel stack start - LDR r3, [r2, #0xAC] ; Load the module kernel stack size - STR r1, [r2, #12] ; Set stack start - STR r0, [r2, #16] ; Set stack end - STR r3, [r2, #20] ; Set stack size + LDR r0, [r2, #0xA8] ; Load the module kernel stack end + IF :LNOT: :DEF: TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + LDR r1, [r2, #0xA4] ; Load the module kernel stack start + LDR r3, [r2, #0xAC] ; Load the module kernel stack size + STR r1, [r2, #12] ; Set stack start + STR r0, [r2, #16] ; Set stack end + STR r3, [r2, #20] ; Set stack size ENDIF - MRS r3, PSP ; Pickup thread stack pointer - STR r3, [r2, #0xB0] ; Save thread stack pointer + MRS r3, PSP ; Pickup thread stack pointer + STR r3, [r2, #0xB0] ; Save thread stack pointer ; Build kernel stack by copying thread stack two registers at a time - ADD r3, r3, #32 ; start at bottom of hardware stack - LDMDB r3!,{r1-r2} ; - STMDB r0!,{r1-r2} ; - LDMDB r3!,{r1-r2} ; - STMDB r0!,{r1-r2} ; - LDMDB r3!,{r1-r2} ; - STMDB r0!,{r1-r2} ; - LDMDB r3!,{r1-r2} ; - STMDB r0!,{r1-r2} ; + ADD r3, r3, #32 ; start at bottom of hardware stack + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + + MSR PSP, r0 ; Set kernel stack pointer - MSR PSP, r0 ; Set kernel stack pointer - _tx_skip_kernel_stack_enter MRS r0, CONTROL ; Pickup current CONTROL register - BIC r0, r0, #1 ; Clear the UNPRIV bit + BIC r0, r0, #1 ; Clear the UNPRIV bit MSR CONTROL, r0 ; Setup new CONTROL register BX lr ; Return to thread _tx_thread_user_return - LDR r2, =_txm_module_user_mode_exit ; Subtract 1 because of THUMB mode. - SUB r2, r2, #1 ; Temporary fix until ARM describes how to load label above correctly. + SUB r2, r2, #1 ; Temporary fix until ARM describes how to load label above correctly. CMP r1, r2 ; Did we come from user_mode_exit? IT NE ; If no (not equal), then... BXNE lr ; return from where we came - + LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address LDR r2, [r1] ; Pickup current thread pointer LDR r1, [r2, #0x9C] ; Pick up user mode STR r1, [r2, #0x98] ; Set the current user mode selection for thread ; If there is memory protection, use kernel stack - LDR r0, [r2, #0x90] ; Load the module instance ptr - LDR r0, [r0, #0x0C] ; Load the module property flags - TST r0, #2 ; Check if memory protected + LDR r0, [r2, #0x90] ; Load the module instance ptr + LDR r0, [r0, #0x0C] ; Load the module property flags + TST r0, #2 ; Check if memory protected BEQ _tx_skip_kernel_stack_exit - - IF :LNOT: :DEF:TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE - LDR r0, [r2, #0xB4] ; Load the module thread stack start - LDR r1, [r2, #0xB8] ; Load the module thread stack end - LDR r3, [r2, #0xBC] ; Load the module thread stack size - STR r0, [r2, #12] ; Set stack start - STR r1, [r2, #16] ; Set stack end - STR r3, [r2, #20] ; Set stack size - ENDIF - LDR r0, [r2, #0xB0] ; Load the module thread stack pointer - MRS r3, PSP ; Pickup kernel stack pointer - ; Copy kernel hardware stack to module thread stack. + IF :LNOT: :DEF: TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + LDR r0, [r2, #0xB4] ; Load the module thread stack start + LDR r1, [r2, #0xB8] ; Load the module thread stack end + LDR r3, [r2, #0xBC] ; Load the module thread stack size + STR r0, [r2, #12] ; Set stack start + STR r1, [r2, #16] ; Set stack end + STR r3, [r2, #20] ; Set stack size + ENDIF + LDR r0, [r2, #0xB0] ; Load the module thread stack pointer + MRS r3, PSP ; Pickup kernel stack pointer + + ; Copy kernel hardware stack to module thread stack. LDM r3!,{r1-r2} STM r0!,{r1-r2} LDM r3!,{r1-r2} @@ -515,13 +505,13 @@ _tx_thread_user_return STM r0!,{r1-r2} LDM r3!,{r1-r2} STM r0!,{r1-r2} - SUB r0, r0, #32 ; Subtract 32 to get back to top of stack - MSR PSP, r0 ; Set thread stack pointer + SUB r0, r0, #32 ; Subtract 32 to get back to top of stack + MSR PSP, r0 ; Set thread stack pointer LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address LDR r2, [r1] ; Pickup current thread pointer LDR r1, [r2, #0x9C] ; Pick up user mode - + _tx_skip_kernel_stack_exit MRS r0, CONTROL ; Pickup current CONTROL register ORR r0, r0, r1 ; OR in the user mode bit @@ -529,55 +519,25 @@ _tx_skip_kernel_stack_exit BX lr ; Return to thread ;} - IF :DEF:__ARMVFP__ - AREA ||.text||, CODE, READONLY + IF :DEF: __ARMVFP__ EXPORT tx_thread_fpu_enable tx_thread_fpu_enable ; -; /* Automatic VPF logic is supported, this function is present only for -; backward compatibility purposes and therefore simply returns. */ -; - BX LR ; Return to caller - - EXPORT tx_thread_fpu_disable -tx_thread_fpu_disable -; -; /* Automatic VPF logic is supported, this function is present only for +; /* Automatic VPF logic is supported, this function is present only for ; backward compatibility purposes and therefore simply returns. */ ; BX LR ; Return to caller ENDIF - + IF :DEF: __ARMVFP__ + EXPORT tx_thread_fpu_disable +tx_thread_fpu_disable ; -; /* Kernel entry function from user mode. */ +; /* Automatic VPF logic is supported, this function is present only for +; backward compatibility purposes and therefore simply returns. */ ; - IMPORT _txm_module_manager_kernel_dispatch -; - AREA ||.text||, CODE, READONLY, ALIGN=5 - THUMB -;VOID _txm_module_manager_user_mode_entry(VOID) -;{ - EXPORT _txm_module_manager_user_mode_entry -_txm_module_manager_user_mode_entry - SVC 1 ; Enter kernel -_txm_module_priv - ; At this point, we are out of user mode. The original LR has been saved in the - ; thread control block. Simply call the kernel dispatch function. - BL _txm_module_manager_kernel_dispatch - - ; Pickup the original LR value while still in privileged mode - LDR r2, =_tx_thread_current_ptr ; Build current thread pointer address - LDR r3, [r2] ; Pickup current thread pointer - LDR lr, [r3, #0xA0] ; Pickup saved LR from original call - - SVC 2 ; Exit kernel and return to user mode -_txm_module_user_mode_exit - BX lr ; Return to the caller - NOP - NOP - NOP - NOP -;} + BX LR ; Return to caller + ENDIF + ALIGN 4 END diff --git a/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_stack_build.s index d24adb08..73fcccf2 100644 --- a/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_stack_build.s @@ -2,6 +2,11 @@ ;/* */ ;/* Copyright (c) Microsoft Corporation. All rights reserved. */ ;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ ;/**************************************************************************/ ; ; @@ -21,8 +26,8 @@ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ -;/* _tx_thread_stack_build Cortex-M4/AC5 */ -;/* 6.0.1 */ +;/* _tx_thread_stack_build Cortex-M7/AC5 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -54,7 +59,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -62,11 +67,11 @@ EXPORT _tx_thread_stack_build _tx_thread_stack_build ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack -; on the Cortex-M4 should look like the following after it is built: -; -; Stack Top: +; on the Cortex-M7 should look like the following after it is built: +; +; Stack Top: ; LR Interrupted LR (LR at time of PENDSV) ; r4 Initial value for r4 ; r5 Initial value for r5 @@ -126,4 +131,3 @@ _tx_thread_stack_build BX lr ; Return to caller ;} END - diff --git a/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_system_return.s b/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_system_return.s index c61d0e53..917abbc8 100644 --- a/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_system_return.s @@ -2,6 +2,11 @@ ;/* */ ;/* Copyright (c) Microsoft Corporation. All rights reserved. */ ;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ ;/**************************************************************************/ ; ; @@ -15,24 +20,14 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; ; AREA ||.text||, CODE, READONLY ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ -;/* _tx_thread_system_return Cortex-M4/AC5 */ -;/* 6.0.1 */ +;/* _tx_thread_system_return Cortex-M7/AC5 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -64,7 +59,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -72,9 +67,9 @@ EXPORT _tx_thread_system_return _tx_thread_system_return ; -; /* Return to real scheduler via PendSV. Note that this routine is often +; /* Return to real scheduler via PendSV. Note that this routine is often ; replaced with in-line assembly in tx_port.h to improved performance. */ -; +; MOV r0, #0x10000000 ; Load PENDSVSET bit MOV r1, #0xE000E000 ; Load NVIC base STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR @@ -85,7 +80,6 @@ _tx_thread_system_return CPSIE i ; Enable interrupts MSR PRIMASK, r1 ; Restore original interrupt posture _isr_context - BX lr ; Return to caller + BX lr ; Return to caller ;} - END - + END diff --git a/ports_module/cortex-m7/ac5/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex-m7/ac5/module_manager/src/tx_timer_interrupt.s index af94c70c..d18bbd08 100644 --- a/ports_module/cortex-m7/ac5/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex-m7/ac5/module_manager/src/tx_timer_interrupt.s @@ -2,6 +2,11 @@ ;/* */ ;/* Copyright (c) Microsoft Corporation. All rights reserved. */ ;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ ;/**************************************************************************/ ; ; @@ -15,17 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_timer.h" -;#include "tx_thread.h" -; -; -;Define Assembly language external references... ; IMPORT _tx_timer_time_slice IMPORT _tx_timer_system_clock @@ -47,8 +41,8 @@ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ -;/* _tx_timer_interrupt Cortex-M4/AC5 */ -;/* 6.0.1 */ +;/* _tx_timer_interrupt Cortex-M7/AC5 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +76,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -106,7 +100,7 @@ _tx_timer_interrupt ; if (_tx_timer_time_slice) ; { ; - MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice + MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CBZ r2, __tx_timer_no_time_slice ; Is it non-active? ; Yes, skip time-slice processing @@ -223,13 +217,13 @@ __tx_timer_dont_activate ; if (_tx_timer_expired_time_slice) ; { ; - MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired + MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag @@ -263,4 +257,3 @@ __tx_timer_nothing_expired ALIGN LTORG END - diff --git a/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_alignment_adjust.c index 9d1b0a17..a4ebdf5d 100644 --- a/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_alignment_adjust.c @@ -10,15 +10,15 @@ /**************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #define TX_SOURCE_CODE @@ -26,42 +26,42 @@ #include "txm_module.h" -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_power_of_two_block_size Cortex-M7/MPU/AC5 */ -/* 6.0.1 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_power_of_two_block_size Cortex-M7/MPU/AC5 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function calculates a power of two size at or immediately above*/ -/* the input size and returns it to the caller. */ -/* */ -/* INPUT */ -/* */ -/* size Block size */ -/* */ -/* OUTPUT */ -/* */ -/* calculated size Rounded up to power of two */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function calculates a power of two size at or immediately above*/ +/* the input size and returns it to the caller. */ +/* */ +/* INPUT */ +/* */ +/* size Block size */ +/* */ +/* OUTPUT */ +/* */ +/* calculated size Rounded up to power of two */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) @@ -89,52 +89,52 @@ ULONG _txm_power_of_two_block_size(ULONG size) } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_alignment_adjust Cortex-M7/MPU/AC5 */ -/* 6.0.1 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_alignment_adjust Cortex-M7/MPU/AC5 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function adjusts the alignment and size of the code and data */ -/* section for a given module implementation. */ -/* */ -/* INPUT */ -/* */ -/* module_preamble Pointer to module preamble */ -/* code_size Size of the code area (updated) */ -/* code_alignment Code area alignment (updated) */ -/* data_size Size of data area (updated) */ -/* data_alignment Data area alignment (updated) */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* _txm_power_of_two_block_size Calculate power of two size */ -/* */ -/* CALLED BY */ -/* */ -/* Initial thread stack frame */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function adjusts the alignment and size of the code and data */ +/* section for a given module implementation. */ +/* */ +/* INPUT */ +/* */ +/* module_preamble Pointer to module preamble */ +/* code_size Size of the code area (updated) */ +/* code_alignment Code area alignment (updated) */ +/* data_size Size of data area (updated) */ +/* data_alignment Data area alignment (updated) */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_power_of_two_block_size Calculate power of two size */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, - ULONG *code_size, - ULONG *code_alignment, - ULONG *data_size, +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, + ULONG *code_size, + ULONG *code_alignment, + ULONG *data_size, ULONG *data_alignment) { @@ -178,11 +178,8 @@ ULONG data_size_accum; local_data_size = data_size_accum; /* Return all the information to the caller. */ - *code_size = local_code_size; + *code_size = local_code_size; *code_alignment = local_code_alignment; *data_size = local_data_size; *data_alignment = local_data_alignment; } - - - diff --git a/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_external_memory_enable.c index 27e2cc34..f9a317a9 100644 --- a/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_external_memory_enable.c @@ -10,15 +10,15 @@ /**************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #define TX_SOURCE_CODE @@ -29,52 +29,52 @@ #include "txm_module.h" -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_external_memory_enable Cortex-M7/MPU/AC5 */ -/* 6.0.1 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_external_memory_enable Cortex-M7/MPU/AC5 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function creates an entry in the MPU table for a shared */ -/* memory space. */ -/* */ -/* INPUT */ -/* */ -/* module_instance Module instance pointer */ -/* start_address Start address of memory */ -/* length Length of external memory */ -/* attributes Memory attributes (r/w) */ -/* */ -/* OUTPUT */ -/* */ -/* status Completion status */ -/* */ -/* CALLS */ -/* */ -/* _tx_mutex_get Get protection mutex */ -/* _tx_mutex_put Release protection mutex */ -/* _txm_power_of_two_block_size Round length to power of two */ -/* */ -/* CALLED BY */ -/* */ -/* Application code */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function creates an entry in the MPU table for a shared */ +/* memory space. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* start_address Start address of memory */ +/* length Length of external memory */ +/* attributes Memory attributes (r/w) */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_mutex_get Get protection mutex */ +/* _tx_mutex_put Release protection mutex */ +/* _txm_power_of_two_block_size Round length to power of two */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, - VOID *start_address, - ULONG length, +UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, + VOID *start_address, + ULONG length, UINT attributes) { @@ -86,18 +86,16 @@ ULONG address; ULONG shared_index; ULONG attributes_check = 0; - /* Determine if the module manager has been initialized. */ + /* Determine if the module manager has not been initialized yet. */ if (_txm_module_manager_ready != TX_TRUE) { - /* Module manager has not been initialized. */ - return(TX_NOT_AVAILABLE); + return(TX_NOT_AVAILABLE); } /* Determine if the module is valid. */ if (module_instance == TX_NULL) { - /* Invalid module pointer. */ return(TX_PTR_ERROR); } @@ -108,7 +106,6 @@ ULONG attributes_check = 0; /* Determine if the module instance is valid. */ if (module_instance -> txm_module_instance_id != TXM_MODULE_ID) { - /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); @@ -119,7 +116,6 @@ ULONG attributes_check = 0; /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { - /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); @@ -130,7 +126,6 @@ ULONG attributes_check = 0; /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) { - /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); @@ -138,7 +133,7 @@ ULONG attributes_check = 0; return(TX_NO_MEMORY); } - /* Start address and length must adhere to Cortex-M7 MPU. + /* Start address and length must adhere to Cortex-M7 MPU. The address must align with the block size. */ block_size = _txm_power_of_two_block_size(length); @@ -192,4 +187,3 @@ ULONG attributes_check = 0; /* Return success. */ return(TX_SUCCESS); } - diff --git a/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c index 35f06b2a..b41f07b7 100644 --- a/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -10,15 +10,15 @@ /**************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #define TX_SOURCE_CODE @@ -33,50 +33,50 @@ VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); -/* Define a macro that can be used to allocate global variables useful to - store information about the last fault. This macro is defined in +/* Define a macro that can be used to allocate global variables useful to + store information about the last fault. This macro is defined in txm_module_port.h and is usually populated in the assembly language fault handling prior to the code calling _txm_module_manager_memory_fault_handler. */ TXM_MODULE_MANAGER_FAULT_INFO -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_memory_fault_handler Cortex-M7/MPU/AC5 */ -/* 6.0.1 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_handler Cortex-M7/MPU/AC5 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function handles a fault associated with a memory protected */ -/* module. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* _tx_thread_terminate Terminate thread */ -/* */ -/* CALLED BY */ -/* */ -/* Fault handler */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function handles a fault associated with a memory protected */ +/* module. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_terminate Terminate thread */ +/* */ +/* CALLED BY */ +/* */ +/* Fault handler */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) @@ -85,7 +85,6 @@ VOID _txm_module_manager_memory_fault_handler(VOID) TXM_MODULE_INSTANCE *module_instance_ptr; TX_THREAD *thread_ptr; - /* Pickup the current thread. */ thread_ptr = _tx_thread_current_ptr; @@ -95,7 +94,6 @@ TX_THREAD *thread_ptr; /* Is there a thread? */ if (thread_ptr) { - /* Pickup the module instance. */ module_instance_ptr = thread_ptr -> tx_thread_module_instance_ptr; @@ -106,9 +104,7 @@ TX_THREAD *thread_ptr; /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { - /* Yes, call the user's notification memory fault callback. */ (_txm_module_manager_fault_notify)(thread_ptr, module_instance_ptr); } } - diff --git a/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c index b9558f19..46cb2bcb 100644 --- a/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -10,15 +10,15 @@ /**************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #define TX_SOURCE_CODE @@ -34,53 +34,51 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_memory_fault_notify Cortex-M7/MPU/AC5 */ -/* 6.0.1 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_notify Cortex-M7/MPU/AC5 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function registers an application callback when/if a memory */ -/* fault occurs. The supplied thread is automatically terminated, but */ -/* any other threads in the same module may still execute. */ -/* */ -/* INPUT */ -/* */ -/* notify_function Memory fault notification */ -/* function, NULL disables. */ -/* */ -/* OUTPUT */ -/* */ -/* status Completion status */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application callback when/if a memory */ +/* fault occurs. The supplied thread is automatically terminated, but */ +/* any other threads in the same module may still execute. */ +/* */ +/* INPUT */ +/* */ +/* notify_function Memory fault notification */ +/* function, NULL disables. */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { - /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; /* Return success. */ return(TX_SUCCESS); } - diff --git a/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c index a3847297..8afa4571 100644 --- a/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c @@ -10,59 +10,58 @@ /**************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #define TX_SOURCE_CODE #include "tx_api.h" #include "txm_module.h" -#include "txm_module_manager_util.h" -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_region_size_get Cortex-M7/MPU/AC5 */ -/* 6.0.1 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_region_size_get Cortex-M7/MPU/AC5 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function converts the region size in bytes to the block size */ -/* for the Cortex-M7 MPU specification. */ -/* */ -/* INPUT */ -/* */ -/* block_size Size of the block in bytes */ -/* */ -/* OUTPUT */ -/* */ -/* MPU size specification */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _txm_module_manager_mm_register_setup */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function converts the region size in bytes to the block size */ +/* for the Cortex-M7 MPU specification. */ +/* */ +/* INPUT */ +/* */ +/* block_size Size of the block in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* MPU size specification */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) @@ -70,7 +69,6 @@ ULONG _txm_module_manager_region_size_get(ULONG block_size) ULONG return_value; - /* Process relative to the input block size. */ if (block_size == 32) { @@ -140,7 +138,7 @@ ULONG return_value; { return_value = 0x14; } - else + else { /* Max 4MB MPU pages for modules. */ return_value = 0x15; @@ -150,45 +148,43 @@ ULONG return_value; } - - -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_calculate_srd_bits Cortex-M7/MPU/AC5 */ -/* 6.0.1 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_calculate_srd_bits Cortex-M7/MPU/AC5 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function calculates the SRD bits that need to be set to */ -/* protect "length" bytes in a block. */ -/* */ -/* INPUT */ -/* */ -/* block_size Size of the block in bytes */ -/* length Actual length in bytes */ -/* */ -/* OUTPUT */ -/* */ -/* SRD bits to be OR'ed with region attribute register. */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _txm_module_manager_mm_register_setup */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function calculates the SRD bits that need to be set to */ +/* protect "length" bytes in a block. */ +/* */ +/* INPUT */ +/* */ +/* block_size Size of the block in bytes */ +/* length Actual length in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* SRD bits to be OR'ed with region attribute register. */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) @@ -230,62 +226,61 @@ UINT srd_bit_index; } - -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_mm_register_setup Cortex-M7/MPU/AC5 */ -/* 6.0.1 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_mm_register_setup Cortex-M7/MPU/AC5 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function sets up the MPU register definitions based on the */ -/* module's memory characteristics. */ -/* MPU layout for the Cortex-M7: */ -/* Entry Description */ -/* 0 Kernel mode entry */ -/* 1 Module code region */ -/* 2 Module code region */ -/* 3 Module code region */ -/* 4 Module code region */ -/* 5 Module data region */ -/* 6 Module data region */ -/* 7 Module data region */ -/* 8 Module data region */ -/* 9 Module shared memory region */ -/* 10 Module shared memory region */ -/* 11 Module shared memory region */ -/* 12 Unused region */ -/* 13 Unused region */ -/* 14 Unused region */ -/* 15 Unused region */ -/* */ -/* */ -/* INPUT */ -/* */ -/* module_instance Pointer to module instance */ -/* */ -/* OUTPUT */ -/* */ -/* MPU specifications for module in module_instance */ -/* */ -/* CALLS */ -/* */ -/* _txm_module_manager_region_size_get */ -/* */ -/* CALLED BY */ -/* */ -/* _txm_module_manager_thread_create */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function sets up the MPU register definitions based on the */ +/* module's memory characteristics. */ +/* MPU layout for the Cortex-M7: */ +/* Entry Description */ +/* 0 Kernel mode entry */ +/* 1 Module code region */ +/* 2 Module code region */ +/* 3 Module code region */ +/* 4 Module code region */ +/* 5 Module data region */ +/* 6 Module data region */ +/* 7 Module data region */ +/* 8 Module data region */ +/* 9 Module shared memory region */ +/* 10 Module shared memory region */ +/* 11 Module shared memory region */ +/* 12 Unused region */ +/* 13 Unused region */ +/* 14 Unused region */ +/* 15 Unused region */ +/* */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* */ +/* OUTPUT */ +/* */ +/* MPU specifications for module in module_instance */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_manager_region_size_get */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_thread_create */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) @@ -305,7 +300,7 @@ UINT i; /* Setup the first MPU region for kernel mode entry. */ - /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. + /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. Mask address to proper range, region 0, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | 0x10; /* Set the attributes, size (32 bytes) and enable bit. */ @@ -378,7 +373,7 @@ UINT i; srd_bits = 0; /* Pickup data starting address and actual size. */ - data_address = (ULONG) module_instance -> txm_module_instance_data_start; + data_address = (ULONG) module_instance -> txm_module_instance_data_start; /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside @@ -460,48 +455,48 @@ UINT i; } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_shared_memory_check_outside */ -/* Cortex-M7/MPU/AC5 */ -/* 6.0.1 */ + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_inside_data_check Cortex-M7/MPU/AC5 */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function checks if the specified object is outside shared */ -/* memory. */ -/* */ -/* INPUT */ -/* */ -/* module_instance Pointer to module instance */ -/* obj_ptr Pointer to the object */ -/* obj_size Size of the object */ -/* */ -/* OUTPUT */ -/* */ -/* Whether the object is outside the shared memory region. */ -/* */ -/* CALLS */ -/* */ -/* N/A */ -/* */ -/* CALLED BY */ -/* */ -/* Module dispatch check functions */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function checks if the specified object is inside shared */ +/* memory. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* obj_ptr Pointer to the object */ +/* obj_size Size of the object */ +/* */ +/* OUTPUT */ +/* */ +/* Whether the object is inside the shared memory region. */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Module dispatch check functions */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -UCHAR _txm_module_manager_shared_memory_check_outside(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) +UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) { UINT shared_memory_index; @@ -509,71 +504,14 @@ UINT num_shared_memory_mpu_entries; ALIGN_TYPE shared_memory_address_start; ALIGN_TYPE shared_memory_address_end; - num_shared_memory_mpu_entries = module_instance -> txm_module_instance_shared_memory_count; - for (shared_memory_index = 0; shared_memory_index < num_shared_memory_mpu_entries; shared_memory_index++) + /* Check if the object is inside the module data. */ + if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && + ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) { - - shared_memory_address_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address[shared_memory_index]; - shared_memory_address_end = shared_memory_address_start + module_instance -> txm_module_instance_shared_memory_length[shared_memory_index]; - - if (TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_EXCLUSIVE(shared_memory_address_start, shared_memory_address_end, - obj_ptr, obj_size)) - { - return(TX_FALSE); - } + return(TX_TRUE); } - return(TX_TRUE); -} - -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_shared_memory_check_inside Cortex-M7/MPU/AC5 */ -/* 6.0.1 */ -/* AUTHOR */ -/* */ -/* Scott Larson, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function checks if the specified object is inside shared */ -/* memory. */ -/* */ -/* INPUT */ -/* */ -/* module_instance Pointer to module instance */ -/* obj_ptr Pointer to the object */ -/* obj_size Size of the object */ -/* */ -/* OUTPUT */ -/* */ -/* Whether the object is inside the shared memory region. */ -/* */ -/* CALLS */ -/* */ -/* N/A */ -/* */ -/* CALLED BY */ -/* */ -/* Module dispatch check functions */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ -/* */ -/**************************************************************************/ -UCHAR _txm_module_manager_shared_memory_check_inside(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) -{ - -UINT shared_memory_index; -UINT num_shared_memory_mpu_entries; -ALIGN_TYPE shared_memory_address_start; -ALIGN_TYPE shared_memory_address_end; - + /* Check if the object is inside the shared memory. */ num_shared_memory_mpu_entries = module_instance -> txm_module_instance_shared_memory_count; for (shared_memory_index = 0; shared_memory_index < num_shared_memory_mpu_entries; shared_memory_index++) { @@ -581,72 +519,8 @@ ALIGN_TYPE shared_memory_address_end; shared_memory_address_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address[shared_memory_index]; shared_memory_address_end = shared_memory_address_start + module_instance -> txm_module_instance_shared_memory_length[shared_memory_index]; - if (TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_EXCLUSIVE(shared_memory_address_start, shared_memory_address_end, - obj_ptr, obj_size)) - { - return(TX_TRUE); - } - } - - return(TX_FALSE); -} - -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_shared_memory_check_inside_byte */ -/* Cortex-M7/MPU/AC5 */ -/* 6.0.1 */ -/* AUTHOR */ -/* */ -/* Scott Larson, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function checks if the specified byte is inside shared memory. */ -/* */ -/* INPUT */ -/* */ -/* module_instance Pointer to module instance */ -/* byte_ptr Pointer to the byte */ -/* */ -/* OUTPUT */ -/* */ -/* Whether the byte is inside the shared memory region. */ -/* */ -/* CALLS */ -/* */ -/* N/A */ -/* */ -/* CALLED BY */ -/* */ -/* Module dispatch check functions */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ -/* */ -/**************************************************************************/ -UCHAR _txm_module_manager_shared_memory_check_inside_byte(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE byte_ptr) -{ - -UINT shared_memory_index; -UINT num_shared_memory_mpu_entries; -ALIGN_TYPE shared_memory_address_start; -ALIGN_TYPE shared_memory_address_end; - - num_shared_memory_mpu_entries = module_instance -> txm_module_instance_shared_memory_count; - for (shared_memory_index = 0; shared_memory_index < num_shared_memory_mpu_entries; shared_memory_index++) - { - - shared_memory_address_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address[shared_memory_index]; - shared_memory_address_end = shared_memory_address_start + module_instance -> txm_module_instance_shared_memory_length[shared_memory_index]; - - if (TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_EXCLUSIVE_BYTE(shared_memory_address_start, shared_memory_address_end, - byte_ptr)) + if ((obj_ptr >= (ALIGN_TYPE) shared_memory_address_start) && + ((obj_ptr + obj_size) <= (ALIGN_TYPE) shared_memory_address_end)) { return(TX_TRUE); } diff --git a/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_thread_stack_build.s index 995eeb56..7acb64eb 100644 --- a/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_thread_stack_build.s @@ -10,66 +10,57 @@ ;/**************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Module Manager */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Module Manager */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; -; - AREA ||.text||, CODE, READONLY - THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _txm_module_manager_thread_stack_build Cortex-M7/MPU/AC5 */ -;/* 6.0.1 */ + AREA ||.text||, CODE, READONLY + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _txm_module_manager_thread_stack_build Cortex-M7/MPU/AC5 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function builds a stack frame on the supplied thread's stack. */ -;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ -;/* thread_ptr Pointer to thread */ -;/* function_ptr Pointer to shell function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread */ +;/* function_ptr Pointer to shell function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) @@ -77,11 +68,11 @@ EXPORT _txm_module_manager_thread_stack_build _txm_module_manager_thread_stack_build ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-M should look like the following after it is built: -; -; Stack Top: +; +; Stack Top: ; LR Interrupted LR (LR at time of PENDSV) ; r4 Initial value for r4 ; r5 Initial value for r5 @@ -89,7 +80,7 @@ _txm_module_manager_thread_stack_build ; r7 Initial value for r7 ; r8 Initial value for r8 ; r9 Initial value for r9 -; r10 (sl) Initial value for r10 (sl) +; r10 Initial value for r10 ; r11 Initial value for r11 ; r0 Initial value for r0 (Hardware stack starts here!!) ; r1 Initial value for r1 @@ -116,17 +107,15 @@ _txm_module_manager_thread_stack_build STR r3, [r2, #12] ; Store initial r6 STR r3, [r2, #16] ; Store initial r7 STR r3, [r2, #20] ; Store initial r8 - LDR r3, [r0, #12] ; Pickup stack starting address - STR r3, [r2, #28] ; Store initial r10 (sl) - MOV r3, #0 ; Build initial register value + STR r3, [r2, #28] ; Store initial r10 STR r3, [r2, #32] ; Store initial r11 ; -; /* Hardware stack follows. / +; /* Hardware stack follows. */ ; STR r0, [r2, #36] ; Store initial r0, which is the thread control block LDR r3, [r0, #8] ; Pickup thread entry info pointer,which is in the stack pointer position of the thread control block. - ; It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this + ; It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this ; function with the actual, initial stack pointer. STR r3, [r2, #40] ; Store initial r1, which is the module entry information. LDR r3, [r3, #8] ; Pickup data base register from the module information @@ -145,8 +134,7 @@ _txm_module_manager_thread_stack_build ; /* Setup stack pointer. */ ; thread_ptr -> tx_thread_stack_ptr = r2; ; - STR r2, [r0, #8] ; Save stack pointer in thread's - ; control block + STR r2, [r0, #8] ; Save stack pointer in thread's control block BX lr ; Return to caller ;} END diff --git a/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_user_mode_entry.S b/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_user_mode_entry.S new file mode 100644 index 00000000..b91f2f97 --- /dev/null +++ b/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_user_mode_entry.S @@ -0,0 +1,88 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Module Manager */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; + IMPORT _txm_module_manager_kernel_dispatch + IMPORT _tx_thread_current_ptr +; + AREA ||.text||, CODE, READONLY, ALIGN=5 + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _txm_module_manager_user_mode_entry Cortex-M7/MPU/AC5 */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function allows modules to enter kernel mode. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* SVC 1 Enter kernel mode */ +;/* SVC 2 Exit kernel mode */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Modules in user mode */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/; +;VOID _txm_module_manager_user_mode_entry(VOID) +;{ + EXPORT _txm_module_manager_user_mode_entry +_txm_module_manager_user_mode_entry + SVC 1 ; Enter kernel + EXPORT _txm_module_priv +_txm_module_priv + ; At this point, we are out of user mode. The original LR has been saved in the + ; thread control block. Simply call the kernel dispatch function. + BL _txm_module_manager_kernel_dispatch + + ; Pickup the original LR value while still in privileged mode + LDR r2, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r3, [r2] ; Pickup current thread pointer + LDR lr, [r3, #0xA0] ; Pickup saved LR from original call + + SVC 2 ; Exit kernel and return to user mode + EXPORT _txm_module_user_mode_exit +_txm_module_user_mode_exit + BX lr ; Return to the caller +;} + ALIGN 32 + END diff --git a/ports_module/cortex-m7/ac6/example_build/all.bat b/ports_module/cortex-m7/ac6/example_build/all.bat new file mode 100644 index 00000000..748e5743 --- /dev/null +++ b/ports_module/cortex-m7/ac6/example_build/all.bat @@ -0,0 +1,5 @@ +@ECHO OFF +CALL clean.bat +CALL setenv.bat +CALL initws.bat +CALL build.bat diff --git a/ports_module/cortex-m7/ac6/example_build/build.bat b/ports_module/cortex-m7/ac6/example_build/build.bat new file mode 100644 index 00000000..6ebdf460 --- /dev/null +++ b/ports_module/cortex-m7/ac6/example_build/build.bat @@ -0,0 +1,24 @@ +@ECHO OFF + +ECHO Build starting... + +SETLOCAL ENABLEEXTENSIONS + +IF DEFINED ARMDSIDEC GOTO IARBUILD_DEFINED +ECHO ERROR: please set ARMDSIDEC to the path of the ARM Developer Studio eclipsec.exe program +EXIT /B 2 +:IARBUILD_DEFINED + +IF EXIST %ARMDSIDEC% GOTO ARMDSIDEC_FOUND +ECHO ERROR: the command ARMDSIDEC doesn't exist: %ARMDSIDEC% +EXIT /B 2 +:ARMDSIDEC_FOUND + +%ARMDSIDEC% -nosplash -application org.eclipse.cdt.managedbuilder.core.headlessbuild -data .\workspace -build all +IF %ERRORLEVEL% EQU 0 GOTO BUILD_OK +ECHO ERROR: build failed. +EXIT /B 1 +:BUILD_OK + +ECHO Build completed without errors. +EXIT /B 0 diff --git a/ports_module/cortex-m7/ac6/example_build/clean.bat b/ports_module/cortex-m7/ac6/example_build/clean.bat new file mode 100644 index 00000000..8a48e5c9 --- /dev/null +++ b/ports_module/cortex-m7/ac6/example_build/clean.bat @@ -0,0 +1,4 @@ +@ECHO OFF +ECHO Cleaning... +RMDIR /Q /S workspace +ECHO Done. diff --git a/ports_module/cortex-m7/ac6/example_build/initws.bat b/ports_module/cortex-m7/ac6/example_build/initws.bat new file mode 100644 index 00000000..62806594 --- /dev/null +++ b/ports_module/cortex-m7/ac6/example_build/initws.bat @@ -0,0 +1,14 @@ +@ECHO OFF + +ECHO Initializing the workspace... + +SETLOCAL ENABLEEXTENSIONS + +%ARMDSIDEC% -nosplash -application org.eclipse.cdt.managedbuilder.core.headlessbuild -data .\workspace -import .\tx -import .\txm -import .\sample_threadx -import .\sample_threadx_module -import .\sample_threadx_module_manager +IF %ERRORLEVEL% EQU 0 GOTO WS_INITIALIZED +ECHO ERROR: failed to initialize the workspace +EXIT /B 2 + +:WS_INITIALIZED +echo Workspace initialized. +EXIT /B 0 diff --git a/ports_module/cortex-m7/ac6/example_build/sample_threadx/.cproject b/ports_module/cortex-m7/ac6/example_build/sample_threadx/.cproject new file mode 100644 index 00000000..9d81f0c7 --- /dev/null +++ b/ports_module/cortex-m7/ac6/example_build/sample_threadx/.cproject @@ -0,0 +1,192 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_module/cortex-m7/ac6/example_build/sample_threadx/.project b/ports_module/cortex-m7/ac6/example_build/sample_threadx/.project new file mode 100644 index 00000000..2a6b3cb1 --- /dev/null +++ b/ports_module/cortex-m7/ac6/example_build/sample_threadx/.project @@ -0,0 +1,28 @@ + + + sample_threadx + + + tx + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.arm.debug.ds.nature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/ports_module/cortex-m7/ac6/example_build/sample_threadx/exceptions.c b/ports_module/cortex-m7/ac6/example_build/sample_threadx/exceptions.c new file mode 100644 index 00000000..01dd0b27 --- /dev/null +++ b/ports_module/cortex-m7/ac6/example_build/sample_threadx/exceptions.c @@ -0,0 +1,96 @@ +/* +** Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. +** Use, modification and redistribution of this file is subject to your possession of a +** valid End User License Agreement for the Arm Product of which these examples are part of +** and your compliance with all applicable terms and conditions of such licence agreement. +*/ + +/* This file contains the default exception handlers and vector table. +All exceptions are handled in Handler mode. Processor state is automatically +pushed onto the stack when an exception occurs, and popped from the stack at +the end of the handler */ + + +/* Exception Handlers */ +/* Marking as __attribute__((interrupt)) avoids them being accidentally called from elsewhere */ + +__attribute__((interrupt)) void NMIException(void) +{ while(1); } + +__attribute__((interrupt)) void HardFaultException(void) +{ while(1); } + +__attribute__((interrupt)) void MemManageException(void) +{ while(1); } + +__attribute__((interrupt)) void BusFaultException(void) +{ while(1); } + +__attribute__((interrupt)) void UsageFaultException(void) +{ while(1); } + +void __tx_SVCallHandler(void); + +__attribute__((interrupt)) void DebugMonitor(void) +{ while(1); } + +void __tx_PendSVHandler(void); + +void __tx_SysTickHandler(void); + +__attribute__((interrupt)) void InterruptHandler(void) +{ while(1); } + + +/* typedef for the function pointers in the vector table */ +typedef void(* const ExecFuncPtr)(void) __attribute__((interrupt)); + +/* Linker-generated Stack Base address */ +#ifdef TWO_REGION +extern unsigned int Image$$ARM_LIB_STACK$$ZI$$Limit; /* for Two Region model */ +#else +extern unsigned int Image$$ARM_LIB_STACKHEAP$$ZI$$Limit; /* for (default) One Region model */ +#endif + +/* Entry point for C run-time initialization */ +extern int __main(void); + + +/* Vector table +Create a named ELF section for the vector table that can be placed in a scatter file. +The first two entries are: + Initial SP = |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit| for (default) One Region model + or |Image$$ARM_LIB_STACK$$ZI$$Limit| for Two Region model + Initial PC= &__main (with LSB set to indicate Thumb) +*/ + +ExecFuncPtr vector_table[] __attribute__((section("vectors"))) = { + /* Configure Initial Stack Pointer using linker-generated symbol */ +#ifdef TWO_REGION + #pragma import(__use_two_region_memory) + (ExecFuncPtr)&Image$$ARM_LIB_STACK$$ZI$$Limit, +#else /* (default) One Region model */ + (ExecFuncPtr)&Image$$ARM_LIB_STACKHEAP$$ZI$$Limit, +#endif + (ExecFuncPtr)__main, /* Initial PC, set to entry point */ + NMIException, + HardFaultException, + MemManageException, + BusFaultException, + UsageFaultException, + 0, 0, 0, 0, /* Reserved */ + __tx_SVCallHandler, + DebugMonitor, + 0, /* Reserved */ + __tx_PendSVHandler, + __tx_SysTickHandler, + + /* Add up to 240 interrupt handlers, starting here... */ + InterruptHandler, + InterruptHandler, /* Some dummy interrupt handlers */ + InterruptHandler + /* + : + */ +}; + diff --git a/ports_module/cortex-m7/ac6/example_build/sample_threadx/sample_threadx.c b/ports_module/cortex-m7/ac6/example_build/sample_threadx/sample_threadx.c new file mode 100644 index 00000000..597f373c --- /dev/null +++ b/ports_module/cortex-m7/ac6/example_build/sample_threadx/sample_threadx.c @@ -0,0 +1,370 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; +UCHAR memory_area[DEMO_BYTE_POOL_SIZE]; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports_module/cortex-m7/ac6/example_build/sample_threadx/sample_threadx.launch b/ports_module/cortex-m7/ac6/example_build/sample_threadx/sample_threadx.launch new file mode 100644 index 00000000..de47ed52 --- /dev/null +++ b/ports_module/cortex-m7/ac6/example_build/sample_threadx/sample_threadx.launch @@ -0,0 +1,194 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_module/cortex-m7/ac6/example_build/sample_threadx/sample_threadx.scat b/ports_module/cortex-m7/ac6/example_build/sample_threadx/sample_threadx.scat new file mode 100644 index 00000000..8b4bb5bd --- /dev/null +++ b/ports_module/cortex-m7/ac6/example_build/sample_threadx/sample_threadx.scat @@ -0,0 +1,44 @@ +;******************************************************* +; Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. +; Use, modification and redistribution of this file is subject to your possession of a +; valid End User License Agreement for the Arm Product of which these examples are part of +; and your compliance with all applicable terms and conditions of such licence agreement. +;******************************************************* + +; Scatter-file for Cortex-M7 bare-metal example + +; This scatter-file places the vector table, application code, data, stacks and heap at suitable addresses in the memory map. + +; The vector table is placed first at the start of the image. +; Code starts after the last entry in the vector table. +; Data is placed at an address that must correspond to RAM. +; Stack and Heap are placed using ARM_LIB_STACKHEAP, to eliminate the need to set stack-base or heap-base in the debugger. +; System Control Space registers appear at their architecturally-defined addresses, based at 0xE000E000. + + +LOAD_REGION 0x00000000 +{ + VECTORS +0 0xC0 ; 16 exceptions + up to 32 interrupts, 4 bytes each entry == 0xC0 + { + exceptions.o (vectors, +FIRST) ; from exceptions.c + } + + ; Code is placed immediately (+0) after the previous root region + ; (so code region will also be a root region) + CODE +0 + { + * (+RO) ; All program code, including library code + } + + DATA +0 + { + * (+RW, +ZI) ; All RW and ZI data + } + + ; Heap grows upwards from start of this region and + ; Stack grows downwards from end of this region + ; The Main Stack Pointer is initialized on reset to the top addresses of this region + ARM_LIB_STACKHEAP +0 EMPTY 0x1000 + { + } +} diff --git a/ports_module/cortex-m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports_module/cortex-m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S new file mode 100644 index 00000000..0cf03005 --- /dev/null +++ b/ports_module/cortex-m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -0,0 +1,231 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global _tx_timer_interrupt + .global __main + .global __tx_NMIHandler // NMI + .global __tx_BadHandler // HardFault + .global __tx_SVCallHandler // SVCall + .global __tx_DBGHandler // Monitor + .global __tx_PendSVHandler // PendSV + .global __tx_SysTickHandler // SysTick + .global __tx_IntHandler // Int 0 + + +SYSTEM_CLOCK = 6000000 +SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) + + + .text 32 + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-M7/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_initialize_low_level(VOID) +// { + .global _tx_initialize_low_level + .thumb_func +_tx_initialize_low_level: + + /* Disable interrupts during ThreadX initialization. */ + + CPSID i + + /* Set base of available memory to end of non-initialised RAM area. */ + + LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer + LDR r1, =Image$$ARM_LIB_STACKHEAP$$ZI$$Limit // Build first free address + ADD r1, r1, #4 // + STR r1, [r0] // Setup first unused memory pointer + + /* Setup Vector Table Offset Register. */ + + MOV r0, #0xE000E000 // Build address of NVIC registers + LDR r1, =vector_table // Pickup address of vector table + STR r1, [r0, #0xD08] // Set vector table address + + /* Set system stack pointer from vector value. */ + + LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer + LDR r1, =vector_table // Pickup address of vector table + LDR r1, [r1] // Pickup reset stack pointer + STR r1, [r0] // Save system stack pointer + + /* Enable the cycle count register. */ + + LDR r0, =0xE0001000 // Build address of DWT register + LDR r1, [r0] // Pickup the current value + ORR r1, r1, #1 // Set the CYCCNTENA bit + STR r1, [r0] // Enable the cycle count register + + /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ + + MOV r0, #0xE000E000 // Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] // Setup SysTick Reload Value + MOV r1, #0x7 // Build SysTick Control Enable Value + STR r1, [r0, #0x10] // Setup SysTick Control + + /* Configure handler priorities. */ + + LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] // Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] // Setup System Handlers 8-11 Priority Registers + // Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] // Setup System Handlers 12-15 Priority Registers + // Note: PnSV must be lowest priority, which is 0xFF + + /* Return to caller. */ + + BX lr +// } + + +/* Define shells for each of the unused vectors. */ + + .global __tx_BadHandler + .thumb_func +__tx_BadHandler: + B __tx_BadHandler + +/* added to catch the hardfault */ + + .global __tx_HardfaultHandler + .thumb_func +__tx_HardfaultHandler: + B __tx_HardfaultHandler + +/* Generic interrupt handler template */ + .global __tx_IntHandler + .thumb_func +__tx_IntHandler: +// VOID InterruptHandler (VOID) +// { + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter // Call the ISR enter function +#endif + + /* Do interrupt handler work here */ + /* BL .... */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit // Call the ISR exit function +#endif + POP {r0, lr} + BX LR +// } + +/* System Tick timer interrupt handler */ + .global __tx_SysTickHandler + .global SysTick_Handler + .thumb_func +__tx_SysTickHandler: + .thumb_func +SysTick_Handler: +// VOID TimerInterruptHandler (VOID) +// { + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter // Call the ISR enter function +#endif + BL _tx_timer_interrupt +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit // Call the ISR exit function +#endif + POP {r0, lr} + BX LR +// } + + +/* NMI, DBG handlers */ + .global __tx_NMIHandler + .thumb_func +__tx_NMIHandler: + B __tx_NMIHandler + + .global __tx_DBGHandler + .thumb_func +__tx_DBGHandler: + B __tx_DBGHandler + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +/* Execution change notify functions */ + .global _tx_execution_isr_enter + .thumb_func +_tx_execution_isr_enter: + BX LR +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +/* Execution change notify functions */ + .global _tx_execution_isr_exit + .thumb_func +_tx_execution_isr_exit: + BX LR +#endif diff --git a/ports_module/cortex-m7/ac6/example_build/sample_threadx_module/.cproject b/ports_module/cortex-m7/ac6/example_build/sample_threadx_module/.cproject new file mode 100644 index 00000000..ccfc3584 --- /dev/null +++ b/ports_module/cortex-m7/ac6/example_build/sample_threadx_module/.cproject @@ -0,0 +1,250 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_module/cortex-m7/ac6/example_build/sample_threadx_module/.project b/ports_module/cortex-m7/ac6/example_build/sample_threadx_module/.project new file mode 100644 index 00000000..5f1f1fa6 --- /dev/null +++ b/ports_module/cortex-m7/ac6/example_build/sample_threadx_module/.project @@ -0,0 +1,28 @@ + + + sample_threadx_module + + + txm + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.arm.debug.ds.nature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/ports_module/cortex-m7/ac6/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex-m7/ac6/example_build/sample_threadx_module/sample_threadx_module.c new file mode 100644 index 00000000..f2647144 --- /dev/null +++ b/ports_module/cortex-m7/ac6/example_build/sample_threadx_module/sample_threadx_module.c @@ -0,0 +1,432 @@ +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, + event flags group, byte pool, and block pool. */ + +/* Specify that this is a module! */ + +#define TXM_MODULE + + +/* Include the ThreadX module definitions. */ + +#include "txm_module.h" + + +/* Define constants. */ + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the external memory area. */ + +#define EXTERNAL_MEMORY_SIZE (64 * 1024) +#define EXTERNAL_MEMORY (0x80000) + + +/* Define the pool space in the bss section of the module. ULONG is used to + get the word alignment. */ + +ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD *thread_0; +TX_THREAD *thread_1; +TX_THREAD *thread_2; +TX_THREAD *thread_3; +TX_THREAD *thread_4; +TX_THREAD *thread_5; +TX_THREAD *thread_6; +TX_THREAD *thread_7; +TX_QUEUE *queue_0; +TX_SEMAPHORE *semaphore_0; +TX_MUTEX *mutex_0; +TX_EVENT_FLAGS_GROUP *event_flags_0; +TX_BYTE_POOL *byte_pool_0; +TX_BLOCK_POOL *block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; +ULONG semaphore_0_puts; +ULONG event_0_sets; +ULONG queue_0_sends; + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + +void semaphore_0_notify(TX_SEMAPHORE *semaphore_ptr) +{ + + if (semaphore_ptr == semaphore_0) + semaphore_0_puts++; +} + + +void event_0_notify(TX_EVENT_FLAGS_GROUP *event_flag_group_ptr) +{ + + if (event_flag_group_ptr == event_flags_0) + event_0_sets++; +} + + +void queue_0_notify(TX_QUEUE *queue_ptr) +{ + + if (queue_ptr == queue_0) + queue_0_sends++; +} + + +/* Define the module start function. */ + +void demo_module_start(ULONG id) +{ + +CHAR *pointer; + + /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + the control block(s). */ + txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_2, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_3, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_4, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_5, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_6, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_7, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&queue_0, sizeof(TX_QUEUE)); + txm_module_object_allocate((void*)&semaphore_0, sizeof(TX_SEMAPHORE)); + txm_module_object_allocate((void*)&mutex_0, sizeof(TX_MUTEX)); + txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); + txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); + txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(queue_0, "module queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + tx_queue_send_notify(queue_0, queue_0_notify); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(semaphore_0, "module semaphore 0", 1); + + tx_semaphore_put_notify(semaphore_0, semaphore_0_notify); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(event_flags_0, "module event flags 0"); + + tx_event_flags_set_notify(event_flags_0, event_0_notify); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(mutex_0, "module mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(block_pool_0, "module block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + /* Test external memory sharing. */ + *(ULONG *)EXTERNAL_MEMORY = 0xABABABAB; + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + diff --git a/ports_module/cortex-m7/ac6/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex-m7/ac6/example_build/sample_threadx_module/txm_module_preamble.S new file mode 100644 index 00000000..1fcc5d15 --- /dev/null +++ b/ports_module/cortex-m7/ac6/example_build/sample_threadx_module/txm_module_preamble.S @@ -0,0 +1,62 @@ + .text + .align 4 + .syntax unified + .section Init + + // Define public symbols + .global __txm_module_preamble + + // Define application-specific start/stop entry points for the module + .global demo_module_start + + // Define common external references + .global _txm_module_thread_shell_entry + .global _txm_module_callback_request_thread_entry + + .eabi_attribute Tag_ABI_PCS_RO_data, 1 + .eabi_attribute Tag_ABI_PCS_R9_use, 1 + .eabi_attribute Tag_ABI_PCS_RW_data, 2 + +__txm_module_preamble: + .dc.l 0x4D4F4455 // Module ID + .dc.l 0x6 // Module Major Version + .dc.l 0x1 // Module Minor Version + .dc.l 32 // Module Preamble Size in 32-bit words + .dc.l 0x12345678 // Module ID (application defined) + .dc.l 0x01000007 // Module Properties where: + // Bits 31-24: Compiler ID + // 0 -> IAR + // 1 -> ARM + // 2 -> GNU + // Bit 0: 0 -> Privileged mode execution + // 1 -> User mode execution + // Bit 1: 0 -> No MPU protection + // 1 -> MPU protection (must have user mode selected) + // Bit 2: 0 -> Disable shared/external memory access + // 1 -> Enable shared/external memory access + .dc.l _txm_module_thread_shell_entry - __txm_module_preamble // Module Shell Entry Point + .dc.l demo_module_start - __txm_module_preamble // Module Start Thread Entry Point + .dc.l 0 // Module Stop Thread Entry Point + .dc.l 1 // Module Start/Stop Thread Priority + .dc.l 1024 // Module Start/Stop Thread Stack Size + .dc.l _txm_module_callback_request_thread_entry - __txm_module_preamble // Module Callback Thread Entry + .dc.l 1 // Module Callback Thread Priority + .dc.l 1024 // Module Callback Thread Stack Size + .dc.l 0x10000 // Module Code Size + .dc.l 0x10000 // Module Data Size + .dc.l 0 // Reserved 0 + .dc.l 0 // Reserved 1 + .dc.l 0 // Reserved 2 + .dc.l 0 // Reserved 3 + .dc.l 0 // Reserved 4 + .dc.l 0 // Reserved 5 + .dc.l 0 // Reserved 6 + .dc.l 0 // Reserved 7 + .dc.l 0 // Reserved 8 + .dc.l 0 // Reserved 9 + .dc.l 0 // Reserved 10 + .dc.l 0 // Reserved 11 + .dc.l 0 // Reserved 12 + .dc.l 0 // Reserved 13 + .dc.l 0 // Reserved 14 + .dc.l 0 // Reserved 15 diff --git a/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/.cproject b/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/.cproject new file mode 100644 index 00000000..0cf83cff --- /dev/null +++ b/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/.cproject @@ -0,0 +1,198 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/.project b/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/.project new file mode 100644 index 00000000..bddfb9ee --- /dev/null +++ b/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/.project @@ -0,0 +1,29 @@ + + + sample_threadx_module_manager + + + sample_threadx_module + tx + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.arm.debug.ds.nature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/exceptions.c b/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/exceptions.c new file mode 100644 index 00000000..0cef25ce --- /dev/null +++ b/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/exceptions.c @@ -0,0 +1,93 @@ +/* +** Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. +** Use, modification and redistribution of this file is subject to your possession of a +** valid End User License Agreement for the Arm Product of which these examples are part of +** and your compliance with all applicable terms and conditions of such licence agreement. +*/ + +/* This file contains the default exception handlers and vector table. +All exceptions are handled in Handler mode. Processor state is automatically +pushed onto the stack when an exception occurs, and popped from the stack at +the end of the handler */ + + +/* Exception Handlers */ +/* Marking as __attribute__((interrupt)) avoids them being accidentally called from elsewhere */ + +__attribute__((interrupt)) void NMIException(void) +{ while(1); } + +__attribute__((interrupt)) void HardFaultException(void) +{ while(1); } + +void MemManage_Handler(void); + +void BusFault_Handler(void); + +void UsageFault_Handler(void); + +void __tx_SVCallHandler(void); + +__attribute__((interrupt)) void DebugMonitor(void) +{ while(1); } + +void __tx_PendSVHandler(void); + +void __tx_SysTickHandler(void); + +__attribute__((interrupt)) void InterruptHandler(void) +{ while(1); } + + +/* typedef for the function pointers in the vector table */ +typedef void(* const ExecFuncPtr)(void) __attribute__((interrupt)); + +/* Linker-generated Stack Base address */ +#ifdef TWO_REGION +extern unsigned int Image$$ARM_LIB_STACK$$ZI$$Limit; /* for Two Region model */ +#else +extern unsigned int Image$$ARM_LIB_STACKHEAP$$ZI$$Limit; /* for (default) One Region model */ +#endif + +/* Entry point for C run-time initialization */ +extern int __main(void); + + +/* Vector table +Create a named ELF section for the vector table that can be placed in a scatter file. +The first two entries are: + Initial SP = |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit| for (default) One Region model + or |Image$$ARM_LIB_STACK$$ZI$$Limit| for Two Region model + Initial PC= &__main (with LSB set to indicate Thumb) +*/ + +ExecFuncPtr vector_table[] __attribute__((section("vectors"))) = { + /* Configure Initial Stack Pointer using linker-generated symbol */ +#ifdef TWO_REGION + #pragma import(__use_two_region_memory) + (ExecFuncPtr)&Image$$ARM_LIB_STACK$$ZI$$Limit, +#else /* (default) One Region model */ + (ExecFuncPtr)&Image$$ARM_LIB_STACKHEAP$$ZI$$Limit, +#endif + (ExecFuncPtr)__main, /* Initial PC, set to entry point */ + NMIException, + HardFaultException, + MemManage_Handler, + BusFault_Handler, + UsageFault_Handler, + 0, 0, 0, 0, /* Reserved */ + __tx_SVCallHandler, + DebugMonitor, + 0, /* Reserved */ + __tx_PendSVHandler, + __tx_SysTickHandler, + + /* Add up to 240 interrupt handlers, starting here... */ + InterruptHandler, + InterruptHandler, /* Some dummy interrupt handlers */ + InterruptHandler + /* + : + */ +}; + diff --git a/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat b/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat new file mode 100644 index 00000000..8b4bb5bd --- /dev/null +++ b/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat @@ -0,0 +1,44 @@ +;******************************************************* +; Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. +; Use, modification and redistribution of this file is subject to your possession of a +; valid End User License Agreement for the Arm Product of which these examples are part of +; and your compliance with all applicable terms and conditions of such licence agreement. +;******************************************************* + +; Scatter-file for Cortex-M7 bare-metal example + +; This scatter-file places the vector table, application code, data, stacks and heap at suitable addresses in the memory map. + +; The vector table is placed first at the start of the image. +; Code starts after the last entry in the vector table. +; Data is placed at an address that must correspond to RAM. +; Stack and Heap are placed using ARM_LIB_STACKHEAP, to eliminate the need to set stack-base or heap-base in the debugger. +; System Control Space registers appear at their architecturally-defined addresses, based at 0xE000E000. + + +LOAD_REGION 0x00000000 +{ + VECTORS +0 0xC0 ; 16 exceptions + up to 32 interrupts, 4 bytes each entry == 0xC0 + { + exceptions.o (vectors, +FIRST) ; from exceptions.c + } + + ; Code is placed immediately (+0) after the previous root region + ; (so code region will also be a root region) + CODE +0 + { + * (+RO) ; All program code, including library code + } + + DATA +0 + { + * (+RW, +ZI) ; All RW and ZI data + } + + ; Heap grows upwards from start of this region and + ; Stack grows downwards from end of this region + ; The Main Stack Pointer is initialized on reset to the top addresses of this region + ARM_LIB_STACKHEAP +0 EMPTY 0x1000 + { + } +} diff --git a/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c b/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c new file mode 100644 index 00000000..210f0be0 --- /dev/null +++ b/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c @@ -0,0 +1,126 @@ +/* Small demonstration of the ThreadX module manager. */ + +#include "tx_api.h" +#include "txm_module.h" + + +#define DEMO_STACK_SIZE 1024 + +/* Define the ThreadX object control blocks... */ + +TX_THREAD module_manager; +TXM_MODULE_INSTANCE my_module; + + +/* Define the object pool area. */ + +UCHAR object_memory[16384]; + + +/* Define the module data pool area. */ + +#define MODULE_DATA_SIZE (256 * 1024) +#define MODULE_DATA (0x40000) + + +/* The module code should be loaded here. */ + +#define MODULE_CODE (0x30000) + + +/* Define the external memory area. */ + +#define EXTERNAL_MEMORY_SIZE (64 * 1024) +#define EXTERNAL_MEMORY (0x80000) + + +/* Define the count of memory faults. */ + +ULONG memory_faults; + + +/* Define thread prototypes. */ + +void module_manager_entry(ULONG thread_input); + + +/* Define fault handler. */ + +VOID module_fault_handler(TX_THREAD *thread, TXM_MODULE_INSTANCE *module) +{ + + /* Just increment the fault counter. */ + memory_faults++; +} + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = (CHAR*)first_unused_memory; + + + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + pointer = pointer + DEMO_STACK_SIZE; +} + + + + +/* Define the test threads. */ + +void module_manager_entry(ULONG thread_input) +{ + + /* Initialize the module manager. */ + txm_module_manager_initialize((void *) MODULE_DATA, MODULE_DATA_SIZE); + + txm_module_manager_object_pool_create(object_memory, sizeof(object_memory)); + + /* Register a fault handler. */ + txm_module_manager_memory_fault_notify(module_fault_handler); + + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ + txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE); + + /* Enable a read/write shared memory region. */ + txm_module_manager_external_memory_enable(&my_module, (void *) EXTERNAL_MEMORY, EXTERNAL_MEMORY_SIZE, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); + + /* Start the module. */ + txm_module_manager_start(&my_module); + + /* Sleep for a while.... */ + tx_thread_sleep(1000); + + /* Stop the module. */ + txm_module_manager_stop(&my_module); + + /* Unload the module. */ + txm_module_manager_unload(&my_module); + + /* Load the module that is already there. */ + txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE); + + /* Start the module again. */ + txm_module_manager_start(&my_module); + + /* Now just spin... */ + while(1) + { + + tx_thread_sleep(100); + } +} diff --git a/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.ds b/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.ds new file mode 100644 index 00000000..b1993316 --- /dev/null +++ b/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.ds @@ -0,0 +1,3 @@ +wait +load ..\sample_threadx_module\Debug\sample_threadx_module.axf +wait diff --git a/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.launch b/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.launch new file mode 100644 index 00000000..d088487d --- /dev/null +++ b/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.launch @@ -0,0 +1,228 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager_debug.ds b/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager_debug.ds new file mode 100644 index 00000000..fc83a4f2 --- /dev/null +++ b/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager_debug.ds @@ -0,0 +1,3 @@ +wait +add-symbol-file ..\sample_threadx_module\Debug\sample_threadx_module.axf +wait diff --git a/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S b/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S new file mode 100644 index 00000000..aaab2108 --- /dev/null +++ b/ports_module/cortex-m7/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S @@ -0,0 +1,231 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global _tx_timer_interrupt + .global __main + .global __tx_NMIHandler // NMI + .global __tx_BadHandler // HardFault + .global __tx_SVCallHandler // SVCall + .global __tx_DBGHandler // Monitor + .global __tx_PendSVHandler // PendSV + .global __tx_SysTickHandler // SysTick + .global __tx_IntHandler // Int 0 + + +SYSTEM_CLOCK = 6000000 +SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) + + + .text 32 + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-M7/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_initialize_low_level(VOID) +// { + .global _tx_initialize_low_level + .thumb_func +_tx_initialize_low_level: + + /* Disable interrupts during ThreadX initialization. */ + + CPSID i + + /* Set base of available memory to end of non-initialised RAM area. */ + + LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer + LDR r1, =Image$$ARM_LIB_STACKHEAP$$ZI$$Limit // Build first free address + ADD r1, r1, #4 // + STR r1, [r0] // Setup first unused memory pointer + + /* Setup Vector Table Offset Register. */ + + MOV r0, #0xE000E000 // Build address of NVIC registers + LDR r1, =vector_table // Pickup address of vector table + STR r1, [r0, #0xD08] // Set vector table address + + /* Set system stack pointer from vector value. */ + + LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer + LDR r1, =vector_table // Pickup address of vector table + LDR r1, [r1] // Pickup reset stack pointer + STR r1, [r0] // Save system stack pointer + + /* Enable the cycle count register. */ + + LDR r0, =0xE0001000 // Build address of DWT register + LDR r1, [r0] // Pickup the current value + ORR r1, r1, #1 // Set the CYCCNTENA bit + STR r1, [r0] // Enable the cycle count register + + /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ + + MOV r0, #0xE000E000 // Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] // Setup SysTick Reload Value + MOV r1, #0x7 // Build SysTick Control Enable Value + STR r1, [r0, #0x10] // Setup SysTick Control + + /* Configure handler priorities. */ + + LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] // Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] // Setup System Handlers 8-11 Priority Registers + // Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] // Setup System Handlers 12-15 Priority Registers + // Note: PnSV must be lowest priority, which is 0xFF + + /* Return to caller. */ + + BX lr +// } + + +/* Define shells for each of the unused vectors. */ + + .global __tx_BadHandler + .thumb_func +__tx_BadHandler: + B __tx_BadHandler + +/* added to catch the hardfault */ + + .global __tx_HardfaultHandler + .thumb_func +__tx_HardfaultHandler: + B __tx_HardfaultHandler + +/* Generic interrupt handler template */ + .global __tx_IntHandler + .thumb_func +__tx_IntHandler: +// VOID InterruptHandler (VOID) +// { + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter // Call the ISR enter function +#endif + + /* Do interrupt handler work here */ + /* BL .... */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit // Call the ISR exit function +#endif + POP {r0, lr} + BX LR +// } + +/* System Tick timer interrupt handler */ + .global __tx_SysTickHandler + .global SysTick_Handler + .thumb_func +__tx_SysTickHandler: + .thumb_func +SysTick_Handler: +// VOID TimerInterruptHandler (VOID) +// { + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter // Call the ISR enter function +#endif + BL _tx_timer_interrupt +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit // Call the ISR exit function +#endif + POP {r0, lr} + BX LR +// } + + +/* NMI, DBG handlers */ + .global __tx_NMIHandler + .thumb_func +__tx_NMIHandler: + B __tx_NMIHandler + + .global __tx_DBGHandler + .thumb_func +__tx_DBGHandler: + B __tx_DBGHandler + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +/* Execution change notify functions */ + .global _tx_execution_isr_enter + .thumb_func +_tx_execution_isr_enter: + BX LR +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +/* Execution change notify functions */ + .global _tx_execution_isr_exit + .thumb_func +_tx_execution_isr_exit: + BX LR +#endif diff --git a/ports_module/cortex-m7/ac6/example_build/setenv.bat b/ports_module/cortex-m7/ac6/example_build/setenv.bat new file mode 100644 index 00000000..27fecdfc --- /dev/null +++ b/ports_module/cortex-m7/ac6/example_build/setenv.bat @@ -0,0 +1,16 @@ +@ECHO OFF + +SET ARMDSDIR="C:\Program Files\Arm\Development Studio 2020.0" +IF EXIST %ARMDSDIR% GOTO FOUND_ARMDS +ECHO ARM Development Studio not found. +EXIT /B 1 + +:FOUND_ARMDS +SET ARMDSIDEC=%ARMDSDIR%\bin\armds_idec.exe +IF EXIST %ARMDSIDEC% GOTO FOUND_ARMDS_IDEC +ECHO armds_idec.exe not found. +EXIT /B 1 + +:FOUND_ARMDS_IDEC +ECHO armds_idec.exe found at %ARMDSIDEC% +EXIT /B 0 diff --git a/ports_module/cortex-m7/ac6/example_build/tx/.cproject b/ports_module/cortex-m7/ac6/example_build/tx/.cproject new file mode 100644 index 00000000..5115080e --- /dev/null +++ b/ports_module/cortex-m7/ac6/example_build/tx/.cproject @@ -0,0 +1,162 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_module/cortex-m7/ac6/example_build/tx/.project b/ports_module/cortex-m7/ac6/example_build/tx/.project new file mode 100644 index 00000000..207f353b --- /dev/null +++ b/ports_module/cortex-m7/ac6/example_build/tx/.project @@ -0,0 +1,63 @@ + + + tx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + inc_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/inc + + + inc_generic_module_manager + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common_modules/module_manager/inc + + + inc_generic_modules + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common_modules/inc + + + inc_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/inc + + + src_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/src + + + src_generic_module_manager + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common_modules/module_manager/src + + + src_port_module_manager + 2 + $%7BPARENT-2-PROJECT_LOC%7D/module_manager/src + + + diff --git a/ports_module/cortex-m7/ac6/example_build/txm/.cproject b/ports_module/cortex-m7/ac6/example_build/txm/.cproject new file mode 100644 index 00000000..02c85d5a --- /dev/null +++ b/ports_module/cortex-m7/ac6/example_build/txm/.cproject @@ -0,0 +1,184 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_module/cortex-m7/ac6/example_build/txm/.project b/ports_module/cortex-m7/ac6/example_build/txm/.project new file mode 100644 index 00000000..8b510516 --- /dev/null +++ b/ports_module/cortex-m7/ac6/example_build/txm/.project @@ -0,0 +1,58 @@ + + + txm + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + inc_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/inc + + + inc_generic_module_manager + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common_modules/module_manager/inc + + + inc_generic_modules + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common_modules/inc + + + inc_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/inc + + + src_generic_module_lib + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common_modules/module_lib/src + + + src_port_module_lib + 2 + $%7BPARENT-2-PROJECT_LOC%7D/module_lib/src + + + diff --git a/ports_module/cortex-m7/ac6/inc/tx_port.h b/ports_module/cortex-m7/ac6/inc/tx_port.h new file mode 100644 index 00000000..8c761ecf --- /dev/null +++ b/ports_module/cortex-m7/ac6/inc/tx_port.h @@ -0,0 +1,516 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-M7/AC6 */ +/* 6.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX Cortex-M7 port. */ + +#define TX_INT_DISABLE 1 /* Disable interrupts */ +#define TX_INT_ENABLE 0 /* Enable interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0 + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); + +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) + +#ifdef TX_ENABLE_FPU_SUPPORT + + +#ifdef TX_MISRA_ENABLE + +ULONG _tx_misra_control_get(void); +void _tx_misra_control_set(ULONG value); +ULONG _tx_misra_fpccr_get(void); +void _tx_misra_vfp_touch(void); + +#else + +__attribute__( ( always_inline ) ) static inline ULONG __get_control(void) +{ + +ULONG control_value; + + __asm__ volatile (" MRS %0,CONTROL ": "=r" (control_value) ); + return(control_value); +} + + +__attribute__( ( always_inline ) ) static inline void __set_control(ULONG control_value) +{ + + __asm__ volatile (" MSR CONTROL,%0": : "r" (control_value): "memory" ); +} + + +#endif + + +/* A completed thread falls into _thread_shell_entry and we can simply deactivate the FPU via CONTROL.FPCA + in order to ensure no lazy stacking will occur. */ + +#ifndef TX_MISRA_ENABLE + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_control(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_control(_tx_vfp_state); \ + } +#else + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } + +#endif + + +/* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. + If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + the lazy FPU save, then restore the CONTROL.FPCA state. */ + +#ifndef TX_MISRA_ENABLE + + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_control(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_control(_tx_vfp_state); \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = *((ULONG *) 0xE000EF34); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_control(); \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + __asm__ volatile ("vmov.f32 s0, s0"); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = __get_control(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_control(_tx_vfp_state); \ + } \ + } \ + } \ + } +#else + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = _tx_misra_fpccr_get(); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + _tx_misra_vfp_touch(); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + } \ + } \ + } +#endif + +#else + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + +#endif + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define the get system state macro. */ + +#ifndef TX_THREAD_GET_SYSTEM_STATE +#ifndef TX_MISRA_ENABLE + +__attribute__( ( always_inline ) ) static inline unsigned int __get_ipsr_value(void) +{ + +unsigned int ipsr_value; + + __asm__ volatile (" MRS %0,IPSR ": "=r" (ipsr_value) ); + return(ipsr_value); +} + + +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | __get_ipsr_value()) +#else +ULONG _tx_misra_ipsr_get(VOID); +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get()) +#endif +#endif + + +/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value + indicates that _tx_thread_system_return should not be called. */ + +#ifndef TX_THREAD_SYSTEM_RETURN_CHECK +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#endif + +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to + prevent early scheduling on Cortex-M parts. */ + +#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; + + +/* This ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + +#endif + + +#ifndef TX_DISABLE_INLINE + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + + +__attribute__( ( always_inline ) ) static inline unsigned int __disable_interrupts(void) +{ + +unsigned int primask_value; + + __asm__ volatile (" MRS %0,PRIMASK ": "=r" (primask_value) ); + __asm__ volatile (" CPSID i" : : : "memory" ); + return(primask_value); +} + +__attribute__( ( always_inline ) ) static inline void __restore_interrupts(unsigned int primask_value) +{ + + __asm__ volatile (" MSR PRIMASK,%0": : "r" (primask_value): "memory" ); +} + +__attribute__( ( always_inline ) ) static inline unsigned int __get_primask_value(void) +{ + +unsigned int primask_value; + + __asm__ volatile (" MRS %0,PRIMASK ": "=r" (primask_value) ); + return(primask_value); +} + +__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void) +{ + + __asm__ volatile (" CPSIE i": : : "memory" ); +} + + +__attribute__( ( always_inline ) ) static inline void _tx_thread_system_return_inline(void) +{ +unsigned int interrupt_save; + + *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + if (__get_ipsr_value() == 0) + { + interrupt_save = __get_primask_value(); + __enable_interrupts(); + __restore_interrupts(interrupt_save); + } +} + + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = __disable_interrupts(); +#define TX_RESTORE __restore_interrupts(interrupt_save); + + +/* Redefine _tx_thread_system_return for improved performance. */ + +#define _tx_thread_system_return _tx_thread_system_return_inline + + +#else + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); +#define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); +#endif + + +/* Define FPU extension for the Cortex-M7. Each is assumed to be called in the context of the executing + thread. These are no longer needed, but are preserved for backward compatibility only. */ + +void tx_thread_fpu_enable(void); +void tx_thread_fpu_disable(void); + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/AC6 Version 6.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif diff --git a/ports_module/cortex-m7/ac6/inc/txm_module_port.h b/ports_module/cortex-m7/ac6/inc/txm_module_port.h new file mode 100644 index 00000000..9b653720 --- /dev/null +++ b/ports_module/cortex-m7/ac6/inc/txm_module_port.h @@ -0,0 +1,340 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* txm_module_port.h Cortex-M7/MPU/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the basic module constants, interface structures, */ +/* and function prototypes. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TXM_MODULE_PORT_H +#define TXM_MODULE_PORT_H + +/* Determine if the optional Modules user define file should be used. */ + +#ifdef TXM_MODULE_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in txm_module_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "txm_module_user.h" +#endif + +/* It is assumed that the base ThreadX tx_port.h file has been modified to add the + following extensions to the ThreadX thread control block (this code should replace + the corresponding macro define in tx_port.h): + +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; + +The following extensions must also be defined in tx_port.h: + +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); + +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); +*/ + +/* Define the kernel stack size for a module thread. */ +#ifndef TXM_MODULE_KERNEL_STACK_SIZE +#define TXM_MODULE_KERNEL_STACK_SIZE 768 +#endif + +/* For the following 3 access control settings, change TEX and C, B, S (bits 21 through 16 of MPU_RASR) + * to reflect your system memory attributes (cache, shareable, memory type). */ +/* Code region access control: privileged read-only, outer & inner write-back, normal memory, shareable. */ +#define TXM_MODULE_MPU_CODE_ACCESS_CONTROL 0x06070000 +/* Data region access control: execute never, read/write, outer & inner write-back, normal memory, shareable. */ +#define TXM_MODULE_MPU_DATA_ACCESS_CONTROL 0x13070000 +/* Shared region access control: execute never, read-only, outer & inner write-back, normal memory, shareable. */ +#define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 + + +/* Define constants specific to the tools the module can be built with for this particular modules port. */ + +#define TXM_MODULE_IAR_COMPILER 0x00000000 +#define TXM_MODULE_RVDS_COMPILER 0x01000000 +#define TXM_MODULE_GNU_COMPILER 0x02000000 +#define TXM_MODULE_COMPILER_MASK 0xFF000000 +#define TXM_MODULE_OPTIONS_MASK 0x000000FF + + +/* Define the properties for this particular module port. */ + +#define TXM_MODULE_MEMORY_PROTECTION_ENABLED + +#ifdef TXM_MODULE_MEMORY_PROTECTION_ENABLED +#define TXM_MODULE_REQUIRE_ALLOCATED_OBJECT_MEMORY +#else +#define TXM_MODULE_REQUIRE_LOCAL_OBJECT_MEMORY +#endif + +#define TXM_MODULE_USER_MODE 0x00000001 +#define TXM_MODULE_MEMORY_PROTECTION 0x00000002 +#define TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS 0x00000004 + + +/* Define the supported options for this module. */ + +#define TXM_MODULE_MANAGER_SUPPORTED_OPTIONS (TXM_MODULE_USER_MODE | TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS) +#define TXM_MODULE_MANAGER_REQUIRED_OPTIONS 0 + + +/* Define offset adjustments according to the compiler used to build the module. */ + +#define TXM_MODULE_IAR_SHELL_ADJUST 24 +#define TXM_MODULE_IAR_START_ADJUST 28 +#define TXM_MODULE_IAR_STOP_ADJUST 32 +#define TXM_MODULE_IAR_CALLBACK_ADJUST 44 + +#define TXM_MODULE_RVDS_SHELL_ADJUST 0 +#define TXM_MODULE_RVDS_START_ADJUST 0 +#define TXM_MODULE_RVDS_STOP_ADJUST 0 +#define TXM_MODULE_RVDS_CALLBACK_ADJUST 0 + +#define TXM_MODULE_GNU_SHELL_ADJUST 24 +#define TXM_MODULE_GNU_START_ADJUST 28 +#define TXM_MODULE_GNU_STOP_ADJUST 32 +#define TXM_MODULE_GNU_CALLBACK_ADJUST 44 + + +/* Define other module port-specific constants. */ + +/* Define INLINE_DECLARE to inline for ARM compiler. */ + +#define INLINE_DECLARE inline + +/* Define the number of MPU entries assigned to the code and data sections. + On Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access + to the kernel entry function, thus 15 remain for code and data protection. */ +#define TXM_MODULE_MPU_TOTAL_ENTRIES 16 +#define TXM_MODULE_MPU_CODE_ENTRIES 4 +#define TXM_MODULE_MPU_DATA_ENTRIES 4 +#define TXM_MODULE_MPU_SHARED_ENTRIES 3 + +#define TXM_MODULE_MPU_KERNEL_ENTRY_INDEX 0 +#define TXM_MODULE_MPU_SHARED_INDEX 9 + +#define TXM_ENABLE_REGION 0x01 + +/* There are 2 registers to set up each MPU region: MPU_RBAR, MPU_RASR. */ +typedef struct TXM_MODULE_MPU_INFO_STRUCT +{ + ULONG txm_module_mpu_region_address; + ULONG txm_module_mpu_region_attribute_size; +} TXM_MODULE_MPU_INFO; +/* Shared memory region attributes. */ +#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 +#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 + +/* Define the port-extensions to the module manager instance structure. */ + +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_count; \ + ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES]; + + +/* Define the memory fault information structure that is populated when a memory fault occurs. */ + + +typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT +{ + TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr; + VOID *txm_module_manager_memory_fault_info_code_location; + ULONG txm_module_manager_memory_fault_info_shcsr; + ULONG txm_module_manager_memory_fault_info_cfsr; + ULONG txm_module_manager_memory_fault_info_mmfar; + ULONG txm_module_manager_memory_fault_info_bfar; + ULONG txm_module_manager_memory_fault_info_control; + ULONG txm_module_manager_memory_fault_info_sp; + ULONG txm_module_manager_memory_fault_info_r0; + ULONG txm_module_manager_memory_fault_info_r1; + ULONG txm_module_manager_memory_fault_info_r2; + ULONG txm_module_manager_memory_fault_info_r3; + ULONG txm_module_manager_memory_fault_info_r4; + ULONG txm_module_manager_memory_fault_info_r5; + ULONG txm_module_manager_memory_fault_info_r6; + ULONG txm_module_manager_memory_fault_info_r7; + ULONG txm_module_manager_memory_fault_info_r8; + ULONG txm_module_manager_memory_fault_info_r9; + ULONG txm_module_manager_memory_fault_info_r10; + ULONG txm_module_manager_memory_fault_info_r11; + ULONG txm_module_manager_memory_fault_info_r12; + ULONG txm_module_manager_memory_fault_info_lr; + ULONG txm_module_manager_memory_fault_info_xpsr; +} TXM_MODULE_MANAGER_MEMORY_FAULT_INFO; + + +#define TXM_MODULE_MANAGER_FAULT_INFO \ + TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info; + +/* Define the macro to check the code alignment. */ + +#define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment) \ + { \ + ULONG temp; \ + temp = (ULONG) module_location; \ + temp = temp & (code_alignment - 1); \ + if (temp) \ + { \ + _tx_mutex_put(&_txm_module_manager_mutex); \ + return(TXM_MODULE_ALIGNMENT_ERROR); \ + } \ + } + + +/* Define the macro to adjust the alignment and size for code/data areas. */ + +#define TXM_MODULE_MANAGER_ALIGNMENT_ADJUST(module_preamble, code_size, code_alignment, data_size, data_alignment) _txm_module_manager_alignment_adjust(module_preamble, &code_size, &code_alignment, &data_size, &data_alignment); + + +/* Define the macro to adjust the symbols in the module preamble. */ + +#define TXM_MODULE_MANAGER_CALCULATE_ADJUSTMENTS(properties, shell_function_adjust, start_function_adjust, stop_function_adjust, callback_function_adjust) \ + if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_IAR_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_IAR_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_IAR_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_IAR_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_IAR_CALLBACK_ADJUST; \ + } \ + else if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_RVDS_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_RVDS_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_RVDS_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_RVDS_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_RVDS_CALLBACK_ADJUST; \ + } \ + else \ + { \ + shell_function_adjust = TXM_MODULE_GNU_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_GNU_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_GNU_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_GNU_CALLBACK_ADJUST; \ + } + + +/* Define the macro to populate the thread control block with module port-specific information. + Check if the module is in user mode and set up txm_module_thread_entry_info_kernel_call_dispatcher accordingly. +*/ + +#define TXM_MODULE_MANAGER_THREAD_SETUP(thread_ptr, module_instance) \ + thread_ptr -> tx_thread_module_current_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \ + thread_ptr -> tx_thread_module_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \ + if (thread_ptr -> tx_thread_module_user_mode) \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_user_mode_entry; \ + } \ + else \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_kernel_dispatch; \ + } + + +/* Define the macro to populate the module control block with module port-specific information. + If memory protection is enabled, set up the MPU registers. +*/ +#define TXM_MODULE_MANAGER_MODULE_SETUP(module_instance) \ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE) \ + { \ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) \ + { \ + _txm_module_manager_mm_register_setup(module_instance); \ + } \ + } \ + else \ + { \ + /* Do nothing. */ \ + } + +/* Define the macro to perform port-specific functions when unloading the module. */ +/* Nothing needs to be done for this port. */ +#define TXM_MODULE_MANAGER_MODULE_UNLOAD(module_instance) + + +/* Define the macros to perform port-specific checks when passing pointers to the kernel. */ + +/* Define macro to make sure object is inside the module's data. */ +#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ + _txm_module_manager_inside_data_check(module_instance, obj_ptr, obj_size) + +/* Define some internal prototypes to this module port. */ + +#ifndef TX_SOURCE_CODE +#define txm_module_manager_memory_fault_notify _txm_module_manager_memory_fault_notify +#endif + + +#define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES \ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment); \ +VOID _txm_module_manager_memory_fault_handler(VOID); \ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)); \ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \ +ULONG _txm_power_of_two_block_size(ULONG size); \ +ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); \ +ULONG _txm_module_manager_region_size_get(ULONG block_size); \ +UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size); + +#define TXM_MODULE_MANAGER_VERSION_ID \ +CHAR _txm_module_manager_version_id[] = \ + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M7/MPU/AC6 Version 6.1 *"; + +#endif diff --git a/ports_module/cortex-m7/ac6/module_lib/src/txm_module_initialize.S b/ports_module/cortex-m7/ac6/module_lib/src/txm_module_initialize.S new file mode 100644 index 00000000..d0ff2577 --- /dev/null +++ b/ports_module/cortex-m7/ac6/module_lib/src/txm_module_initialize.S @@ -0,0 +1,104 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .global __use_two_region_memory + .global __scatterload + + + .eabi_attribute Tag_ABI_PCS_RO_data, 1 + .eabi_attribute Tag_ABI_PCS_R9_use, 1 + .eabi_attribute Tag_ABI_PCS_RW_data, 2 + + .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_initialize Cortex-M7/MPU/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes the module c runtime. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __scatterload Initialize C runtime */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_thread_shell_entry Start module thread */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Andres Mlinar Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _txm_module_initialize(VOID) + .global _txm_module_initialize + .thumb_func +_txm_module_initialize: + PUSH {r4-r12,lr} // Save dregs and LR + //B __scatterload // Call ARM func to initialize variables + +// Override the __rt_exit function. + .global __rt_exit + .thumb_func +__rt_exit: + POP {r4-r12,lr} // Restore dregs and LR + BX lr // Return to caller + +#define TXM_MODULE_HEAP_SIZE 512 + +// returns heap start address in R0 +// returns heap end address in R2 +// does not touch SP, it is already set up before the module runs + .global __user_setup_stackheap + .thumb_func +__user_setup_stackheap: + LDR r1, _txm_heap // load heap offset + MOV r2, TXM_MODULE_HEAP_SIZE // load heap size + ADD r2, r2, r0 // calculate heap end address + BX lr + +// dummy main function + .global main + .thumb_func +main: + BX lr + + .align 8 +_txm_heap: + .zero TXM_MODULE_HEAP_SIZE diff --git a/ports_module/cortex-m7/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex-m7/ac6/module_lib/src/txm_module_thread_shell_entry.c new file mode 100644 index 00000000..649973db --- /dev/null +++ b/ports_module/cortex-m7/ac6/module_lib/src/txm_module_thread_shell_entry.c @@ -0,0 +1,172 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#ifndef TXM_MODULE +#define TXM_MODULE +#endif + +#ifndef TX_SOURCE_CODE +#define TX_SOURCE_CODE +#endif + + +/* Include necessary system files. */ + +#include "txm_module.h" +#include "tx_thread.h" + +/* Define the global module entry pointer from the start thread of the module. */ + +TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; + + +/* Define the dispatch function pointer used in the module implementation. */ + +ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3); + + +/* Define the ARM cstartup code. */ +extern VOID _txm_module_initialize(VOID); + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_thread_shell_entry Cortex-M7/MPU/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calls the specified entry function of the thread. It */ +/* also provides a place for the thread's entry function to return. */ +/* If the thread returns, this function places the thread in a */ +/* "COMPLETED" state. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to current thread */ +/* thread_info Pointer to thread entry info */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_initialize cstartup initialization */ +/* thread_entry Thread's entry function */ +/* tx_thread_resume Resume the module callback thread */ +/* _txm_module_thread_system_suspend Module thread suspension routine */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) +{ + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + VOID (*entry_exit_notify)(TX_THREAD *, UINT); +#endif + + + /* Determine if this is the start thread. If so, we must prepare the module for + execution. If not, simply skip the C startup code. */ + if (thread_info -> txm_module_thread_entry_info_start_thread) + { + /* Initialize the ARM C environment. */ + _txm_module_initialize(); + + /* Save the entry info pointer, for later use. */ + _txm_module_entry_info = thread_info; + + /* Save the kernel function dispatch address. This is used to make all resident calls from + the module. */ + _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; + + /* Ensure that we have a valid pointer. */ + while (!_txm_module_kernel_call_dispatcher) + { + /* Loop here, if an error is present getting the dispatch function pointer! + An error here typically indicates the resident portion of _tx_thread_schedule + is not supporting the trap to obtain the function pointer. */ + } + + /* Resume the module's callback thread, already created in the manager. */ + _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); + } + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has been entered! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_ENTRY); + } +#endif + + /* Call current thread's entry function. */ + (thread_info -> txm_module_thread_entry_info_entry) (thread_info -> txm_module_thread_entry_info_parameter); + + /* Suspend thread with a "completed" state. */ + + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine again. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has exited! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_EXIT); + } +#endif + + /* Call actual thread suspension routine. */ + _txm_module_thread_system_suspend(thread_ptr); + +#ifdef TX_SAFETY_CRITICAL + + /* If we ever get here, raise safety critical exception. */ + TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0); +#endif +} + diff --git a/ports_module/cortex-m7/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex-m7/ac6/module_manager/src/tx_thread_context_restore.S new file mode 100644 index 00000000..92b11d0d --- /dev/null +++ b/ports_module/cortex-m7/ac6/module_manager/src/tx_thread_context_restore.S @@ -0,0 +1,76 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .text + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore Cortex-M7/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is only needed for legacy applications and it should */ +/* not be called in any new development on a Cortex-M. */ +/* This function restores the interrupt context if it is processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_context_restore(VOID) +// { + .global _tx_thread_context_restore + .thumb_func +_tx_thread_context_restore: + /* Not needed for this port - just return! */ + BX lr +// } diff --git a/ports_module/cortex-m7/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex-m7/ac6/module_manager/src/tx_thread_context_save.S new file mode 100644 index 00000000..a91908ba --- /dev/null +++ b/ports_module/cortex-m7/ac6/module_manager/src/tx_thread_context_save.S @@ -0,0 +1,75 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .text + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save Cortex-M7/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is only needed for legacy applications and it should */ +/* not be called in any new development on a Cortex-M. */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_context_save(VOID) +// { + .global _tx_thread_context_save + .thumb_func +_tx_thread_context_save: + /* Not needed for this port - just return! */ + BX lr +// } diff --git a/ports_module/cortex-m7/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex-m7/ac6/module_manager/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..1b62c490 --- /dev/null +++ b/ports_module/cortex-m7/ac6/module_manager/src/tx_thread_interrupt_control.S @@ -0,0 +1,80 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text 32 + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control Cortex-M7/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_interrupt_control(UINT new_posture) +// { + .global _tx_thread_interrupt_control + .thumb_func +_tx_thread_interrupt_control: + + // Pickup current interrupt lockout posture. + + MRS r1, PRIMASK // Pickup current interrupt lockout + + // Apply the new interrupt posture. + + MSR PRIMASK, r0 // Apply the new interrupt lockout + MOV r0, r1 // Transfer old to return register + BX lr // Return to caller + +// } diff --git a/ports_module/cortex-m7/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex-m7/ac6/module_manager/src/tx_thread_schedule.S new file mode 100644 index 00000000..326bb601 --- /dev/null +++ b/ports_module/cortex-m7/ac6/module_manager/src/tx_thread_schedule.S @@ -0,0 +1,574 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .global _tx_thread_current_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_system_stack_ptr + .global _tx_thread_preempt_disable + .global _txm_module_manager_memory_fault_handler + .global _txm_module_manager_memory_fault_info +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + .global _tx_execution_thread_enter + .global _tx_execution_thread_exit +#endif + + .text + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule Cortex-M7/MPU/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* _tx_thread_context_restore Restore thread's context */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_schedule(VOID) +// { + .global _tx_thread_schedule + .thumb_func +_tx_thread_schedule: + + /* This function should only ever be called on Cortex-M + from the first schedule request. Subsequent scheduling occurs + from the PendSV handling routines below. */ + + /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ + + MOV r0, #0 // Build value for TX_FALSE + LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag + STR r0, [r2, #0] // Clear preempt disable flag + + /* Clear CONTROL.FPCA bit so FPU registers aren't unnecessarily stacked. */ + +#ifdef __ARMVFP__ + MRS r0, CONTROL // Pickup current CONTROL register + BIC r0, r0, #4 // Clear the FPCA bit + MSR CONTROL, r0 // Setup new CONTROL register +#endif + + /* Enable memory fault registers. */ + + LDR r0, =0xE000ED24 // Build SHCSR address + LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults + STR r1, [r0] // + + /* Enable interrupts */ + + CPSIE i + + /* Enter the scheduler for the first time. */ + + MOV r0, #0x10000000 // Load PENDSVSET bit + MOV r1, #0xE000E000 // Load NVIC base + STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + DSB // Complete all memory accesses + ISB // Flush pipeline + + /* Wait here for the PendSV to take place. */ + +__tx_wait_here: + B __tx_wait_here // Wait for the PendSV to happen +// } + + + /* Memory Exception Handler. */ + .global MemManage_Handler + .global BusFault_Handler + .global UsageFault_Handler + .thumb_func +MemManage_Handler: + .thumb_func +BusFault_Handler: + .thumb_func +UsageFault_Handler: + + CPSID i // Disable interrupts + + /* Now pickup and store all the fault related information. */ + + LDR r12,=_txm_module_manager_memory_fault_info // Pickup fault info struct + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r0] // Pickup the current thread pointer + STR r1, [r12, #0] // Save current thread pointer in fault info structure + LDR r0, =0xE000ED24 // Build SHCSR address + LDR r1, [r0] // Pickup SHCSR + STR r1, [r12, #8] // Save SHCSR + LDR r0, =0xE000ED28 // Build CFSR address + LDR r1, [r0] // Pickup CFSR + STR r1, [r12, #12] // Save CFSR + LDR r0, =0xE000ED34 // Build MMFAR address + LDR r1, [r0] // Pickup MMFAR + STR r1, [r12, #16] // Save MMFAR + LDR r0, =0xE000ED38 // Build BFAR address + LDR r1, [r0] // Pickup BFAR + STR r1, [r12, #20] // Save BFAR + MRS r0, CONTROL // Pickup current CONTROL register + STR r0, [r12, #24] // Save CONTROL + MRS r1, PSP // Pickup thread stack pointer + STR r1, [r12, #28] // Save thread stack pointer + LDR r0, [r1] // Pickup saved r0 + STR r0, [r12, #32] // Save r0 + LDR r0, [r1, #4] // Pickup saved r1 + STR r0, [r12, #36] // Save r1 + STR r2, [r12, #40] // Save r2 + STR r3, [r12, #44] // Save r3 + STR r4, [r12, #48] // Save r4 + STR r5, [r12, #52] // Save r5 + STR r6, [r12, #56] // Save r6 + STR r7, [r12, #60] // Save r7 + STR r8, [r12, #64] // Save r8 + STR r9, [r12, #68] // Save r9 + STR r10,[r12, #72] // Save r10 + STR r11,[r12, #76] // Save r11 + LDR r0, [r1, #16] // Pickup saved r12 + STR r0, [r12, #80] // Save r12 + LDR r0, [r1, #20] // Pickup saved lr + STR r0, [r12, #84] // Save lr + LDR r0, [r1, #24] // Pickup instruction address at point of fault + STR r0, [r12, #4] // Save point of fault + LDR r0, [r1, #28] // Pickup xPSR + STR r0, [r12, #88] // Save xPSR + + MRS r0, CONTROL // Pickup current CONTROL register + BIC r0, r0, #1 // Clear the UNPRIV bit + MSR CONTROL, r0 // Setup new CONTROL register + + LDR r0, =0xE000ED28 // Build the Memory Management Fault Status Register (MMFSR) + LDRB r1, [r0] // Pickup the MMFSR, with the following bit definitions: + // Bit 0 = 1 -> Instruction address violation + // Bit 1 = 1 -> Load/store address violation + // Bit 7 = 1 -> MMFAR is valid + STRB r1, [r0] // Clear the MMFSR + +#ifdef __ARMVFP__ + LDR r0, =0xE000EF34 // Cleanup FPU context: Load FPCCR address + LDR r1, [r0] // Load FPCCR + BIC r1, r1, #1 // Clear the lazy preservation active bit + STR r1, [r0] // Store the value +#endif + + BL _txm_module_manager_memory_fault_handler // Call memory manager fault handler + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread exit function to indicate the thread is no longer executing. */ + + CPSID i // Disable interrupts + BL _tx_execution_thread_exit // Call the thread exit function + CPSIE i // Enable interrupts +#endif + + MOV r1, #0 // Build NULL value + LDR r0, =_tx_thread_current_ptr // Pickup address of current thread pointer + STR r1, [r0] // Clear current thread pointer + + // Return from MemManage_Handler exception + LDR r0, =0xE000ED04 // Load ICSR + LDR r1, =0x10000000 // Set PENDSVSET bit + STR r1, [r0] // Store ICSR + DSB // Wait for memory access to complete + CPSIE i // Enable interrupts + MOV lr, #0xFFFFFFFD // Load exception return code + BX lr // Return from exception + + + /* Generic context PendSV handler. */ + + .global PendSV_Handler + .thumb_func +PendSV_Handler: + .global __tx_PendSVHandler + .thumb_func +__tx_PendSVHandler: + + /* Get current thread value and new thread pointer. */ + +__tx_ts_handler: + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread exit function to indicate the thread is no longer executing. */ + + CPSID i // Disable interrupts + PUSH {r0, lr} // Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit // Call the thread exit function + POP {r0, lr} // Recover LR + CPSIE i // Enable interrupts +#endif + + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address + MOV r3, #0 // Build NULL value + LDR r1, [r0] // Pickup current thread pointer + + /* Determine if there is a current thread to finish preserving. */ + + CBZ r1, __tx_ts_new // If NULL, skip preservation + + /* Recover PSP and preserve current thread context. */ + + STR r3, [r0] // Set _tx_thread_current_ptr to NULL + MRS r12, PSP // Pickup PSP pointer (thread's stack pointer) + STMDB r12!, {r4-r11} // Save its remaining registers +#ifdef __ARMVFP__ + TST LR, #0x10 // Determine if the VFP extended frame is present + BNE _skip_vfp_save + VSTMDB r12!,{s16-s31} // Yes, save additional VFP registers +_skip_vfp_save: +#endif + LDR r4, =_tx_timer_time_slice // Build address of time-slice variable + STMDB r12!, {LR} // Save LR on the stack + + /* Determine if time-slice is active. If it isn't, skip time handling processing. */ + + LDR r5, [r4] // Pickup current time-slice + STR r12, [r1, #8] // Save the thread stack pointer + CBZ r5, __tx_ts_new // If not active, skip processing + + /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ + + STR r5, [r1, #24] // Save current time-slice + + /* Clear the global time-slice. */ + + STR r3, [r4] // Clear time-slice + + /* Executing thread is now completely preserved!!! */ + +__tx_ts_new: + + /* Now we are looking for a new thread to execute! */ + + CPSID i // Disable interrupts + LDR r1, [r2] // Is there another thread ready to execute? + CBZ r1, __tx_ts_wait // No, skip to the wait processing + + /* Yes, another thread is ready for else, make the current thread the new thread. */ + + STR r1, [r0] // Setup the current thread pointer to the new thread + CPSIE i // Enable interrupts + + /* Increment the thread run count. */ + +__tx_ts_restore: + LDR r7, [r1, #4] // Pickup the current thread run count + LDR r4, =_tx_timer_time_slice // Build address of time-slice variable + LDR r5, [r1, #24] // Pickup thread's current time-slice + ADD r7, r7, #1 // Increment the thread run count + STR r7, [r1, #4] // Store the new run count + + /* Setup global time-slice with thread's current time-slice. */ + + STR r5, [r4] // Setup global time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread entry function to indicate the thread is executing. */ + + PUSH {r0, r1} // Save r0 and r1 + BL _tx_execution_thread_enter // Call the thread execution enter function + POP {r0, r1} // Recover r0 and r1 +#endif + + /* Restore the thread context and PSP. */ + + LDR r12, [r1, #8] // Pickup thread's stack pointer + + MRS r5, CONTROL // Pickup current CONTROL register + LDR r4, [r1, #0x98] // Pickup current user mode flag + BIC r5, r5, #1 // Clear the UNPRIV bit + ORR r4, r4, r5 // Build new CONTROL register + MSR CONTROL, r4 // Setup new CONTROL register + + LDR r0, =0xE000ED94 // Build MPU control reg address + MOV r3, #0 // Build disable value + STR r3, [r0] // Disable MPU + LDR r0, [r1, #0x90] // Pickup the module instance pointer + CBZ r0, skip_mpu_setup // Is this thread owned by a module? No, skip MPU setup + LDR r1, [r0, #0x64] // Pickup MPU register[0] + CBZ r1, skip_mpu_setup // Is protection required for this module? No, skip MPU setup + LDR r1, =0xE000ED9C // Build address of MPU base register + + // Use alias registers to quickly load MPU + ADD r0, r0, #100 // Build address of MPU register start in thread control block + LDM r0!,{r2-r9} // Load MPU regions 0-3 + STM r1,{r2-r9} // Store MPU regions 0-3 + LDM r0!,{r2-r9} // Load MPU regions 4-7 + STM r1,{r2-r9} // Store MPU regions 4-7 + LDM r0!,{r2-r9} // Load MPU regions 8-11 + STM r1,{r2-r9} // Store MPU regions 8-11 + LDM r0!,{r2-r9} // Load MPU regions 12-15 + STM r1,{r2-r9} // Store MPU regions 12-15 + LDR r0, =0xE000ED94 // Build MPU control reg address + MOV r1, #5 // Build enable value with background region enabled + STR r1, [r0] // Enable MPU +skip_mpu_setup: + LDMIA r12!, {LR} // Pickup LR +#ifdef __ARMVFP__ + TST LR, #0x10 // Determine if the VFP extended frame is present + BNE _skip_vfp_restore // If not, skip VFP restore + VLDMIA r12!, {s16-s31} // Yes, restore additional VFP registers +_skip_vfp_restore: +#endif + LDMIA r12!, {r4-r11} // Recover thread's registers + MSR PSP, r12 // Setup the thread's stack pointer + + /* Return to thread. */ + + BX lr // Return to thread! + + /* The following is the idle wait processing... in this case, no threads are ready for execution and the + system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts + are disabled to allow use of WFI for waiting for a thread to arrive. */ + +__tx_ts_wait: + CPSID i // Disable interrupts + LDR r1, [r2] // Pickup the next thread to execute pointer + STR r1, [r0] // Store it in the current pointer + CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! +#ifdef TX_ENABLE_WFI + DSB // Ensure no outstanding memory transactions + WFI // Wait for interrupt + ISB // Ensure pipeline is flushed +#endif + CPSIE i // Enable interrupts + B __tx_ts_wait // Loop to continue waiting + + /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are + already in the handler! */ + +__tx_ts_ready: + MOV r7, #0x08000000 // Build clear PendSV value + MOV r8, #0xE000E000 // Build base NVIC address + STR r7, [r8, #0xD04] // Clear any PendSV + + /* Re-enable interrupts and restore new thread. */ + + CPSIE i // Enable interrupts + B __tx_ts_restore // Restore the thread + + + /* SVC Handler. */ + + .global SVC_Handler + .thumb_func +SVC_Handler: + .global __tx_SVCallHandler + .thumb_func +__tx_SVCallHandler: + + MRS r0, PSP // Pickup the PSP stack + LDR r1, [r0, #24] // Pickup the point of interrupt + LDRB r2, [r1, #-2] // Pickup the SVC parameter + + /* Determine which SVC trap we are processing */ + + CMP r2, #1 // Is it the entry into ThreadX? + BNE _tx_thread_user_return // No, return to user mode + + /* At this point we have an SVC 1, which means we are entering + the kernel from a module thread with user mode selected. */ + + LDR r2, =_txm_module_priv // Load address of where we should have come from + CMP r1, r2 // Did we come from user_mode_entry? + IT NE // If no (not equal), then... + BXNE lr // return from where we came. + + LDR r3, [r0, #20] // This is the saved LR + LDR r1, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, [r1] // Pickup current thread pointer + MOV r1, #0 // Build clear value + STR r1, [r2, #0x98] // Clear the current user mode selection for thread + STR r3, [r2, #0xA0] // Save the original LR in thread control block + + /* If there is memory protection, use kernel stack */ + LDR r0, [r2, #0x90] // Load the module instance ptr + LDR r0, [r0, #0x0C] // Load the module property flags + TST r0, #2 // Check if memory protected + BEQ _tx_skip_kernel_stack_enter + + /* Switch to the module thread's kernel stack */ + LDR r0, [r2, #0xA8] // Load the module kernel stack end +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + LDR r1, [r2, #0xA4] // Load the module kernel stack start + LDR r3, [r2, #0xAC] // Load the module kernel stack size + STR r1, [r2, #12] // Set stack start + STR r0, [r2, #16] // Set stack end + STR r3, [r2, #20] // Set stack size +#endif + + MRS r3, PSP // Pickup thread stack pointer + STR r3, [r2, #0xB0] // Save thread stack pointer + + /* Build kernel stack by copying thread stack two registers at a time */ + ADD r3, r3, #32 // Start at bottom of hardware stack + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + + MSR PSP, r0 // Set kernel stack pointer + +_tx_skip_kernel_stack_enter: + MRS r0, CONTROL // Pickup current CONTROL register + BIC r0, r0, #1 // Clear the UNPRIV bit + MSR CONTROL, r0 // Setup new CONTROL register + BX lr // Return to thread + +_tx_thread_user_return: + LDR r2, =_txm_module_user_mode_exit // Load address of where we should have come from + CMP r1, r2 // Did we come from user_mode_exit? + IT NE // If no (not equal), then... + BXNE lr // return from where we came + + LDR r1, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, [r1] // Pickup current thread pointer + LDR r1, [r2, #0x9C] // Pick up user mode + STR r1, [r2, #0x98] // Set the current user mode selection for thread + + /* If there is memory protection, use kernel stack */ + LDR r0, [r2, #0x90] // Load the module instance ptr + LDR r0, [r0, #0x0C] // Load the module property flags + TST r0, #2 // Check if memory protected + BEQ _tx_skip_kernel_stack_exit + +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + LDR r0, [r2, #0xB4] // Load the module thread stack start + LDR r1, [r2, #0xB8] // Load the module thread stack end + LDR r3, [r2, #0xBC] // Load the module thread stack size + STR r0, [r2, #12] // Set stack start + STR r1, [r2, #16] // Set stack end + STR r3, [r2, #20] // Set stack size +#endif + LDR r0, [r2, #0xB0] // Load the module thread stack pointer + MRS r3, PSP // Pickup kernel stack pointer + + /* Copy kernel hardware stack to module thread stack. */ + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + SUB r0, r0, #32 // Subtract 32 to get back to top of stack + MSR PSP, r0 // Set thread stack pointer + + LDR r1, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, [r1] // Pickup current thread pointer + LDR r1, [r2, #0x9C] // Pick up user mode + +_tx_skip_kernel_stack_exit: + MRS r0, CONTROL // Pickup current CONTROL register + ORR r0, r0, r1 // OR in the user mode bit + MSR CONTROL, r0 // Setup new CONTROL register + BX lr // Return to thread + + + /* Kernel entry function from user mode. */ + + .global _txm_module_manager_kernel_dispatch + .align 5 + .syntax unified +// VOID _txm_module_manager_user_mode_entry(VOID) +// { + .global _txm_module_manager_user_mode_entry + .thumb_func +_txm_module_manager_user_mode_entry: + SVC 1 // Enter kernel +_txm_module_priv: + /* At this point, we are out of user mode. The original LR has been saved in the + thread control block. Simply call the kernel dispatch function. */ + BL _txm_module_manager_kernel_dispatch + + /* Pickup the original LR value while still in privileged mode */ + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r3, [r2] // Pickup current thread pointer + LDR lr, [r3, #0xA0] // Pickup saved LR from original call + + SVC 2 // Exit kernel and return to user mode +_txm_module_user_mode_exit: + BX lr // Return to the caller + NOP + NOP + NOP + NOP +// } + +#ifdef TX_ENABLE_FPU_SUPPORT + + .global tx_thread_fpu_enable + .thumb_func +tx_thread_fpu_enable: + /* Automatic VPF logic is supported, this function is present only for + backward compatibility purposes and therefore simply returns. */ + BX LR // Return to caller + + .global tx_thread_fpu_disable + .thumb_func +tx_thread_fpu_disable: + /* Automatic VPF logic is supported, this function is present only for + backward compatibility purposes and therefore simply returns. */ + BX LR // Return to caller + +#endif + diff --git a/ports_module/cortex-m7/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex-m7/ac6/module_manager/src/tx_thread_stack_build.S new file mode 100644 index 00000000..31510bd1 --- /dev/null +++ b/ports_module/cortex-m7/ac6/module_manager/src/tx_thread_stack_build.S @@ -0,0 +1,135 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .text + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build Cortex-M7/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +// { + .global _tx_thread_stack_build + .thumb_func +_tx_thread_stack_build: + + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-M should look like the following after it is built: + + Stack Top: + LR Interrupted LR (LR at time of PENDSV) + r4 Initial value for r4 + r5 Initial value for r5 + r6 Initial value for r6 + r7 Initial value for r7 + r8 Initial value for r8 + r9 Initial value for r9 + r10 Initial value for r10 + r11 Initial value for r11 + r0 Initial value for r0 (Hardware stack starts here!!) + r1 Initial value for r1 + r2 Initial value for r2 + r3 Initial value for r3 + r12 Initial value for r12 + lr Initial value for lr + pc Initial value for pc + xPSR Initial value for xPSR + + Stack Bottom: (higher memory address) */ + + LDR r2, [r0, #16] // Pickup end of stack area + BIC r2, r2, #0x7 // Align frame + SUB r2, r2, #68 // Subtract frame size + LDR r3, =0xFFFFFFFD // Build initial LR value + STR r3, [r2, #0] // Save on the stack + + /* Actually build the stack frame. */ + + MOV r3, #0 // Build initial register value + STR r3, [r2, #4] // Store initial r4 + STR r3, [r2, #8] // Store initial r5 + STR r3, [r2, #12] // Store initial r6 + STR r3, [r2, #16] // Store initial r7 + STR r3, [r2, #20] // Store initial r8 + STR r3, [r2, #24] // Store initial r9 + STR r3, [r2, #28] // Store initial r10 + STR r3, [r2, #32] // Store initial r11 + + /* Hardware stack follows. */ + + STR r3, [r2, #36] // Store initial r0 + STR r3, [r2, #40] // Store initial r1 + STR r3, [r2, #44] // Store initial r2 + STR r3, [r2, #48] // Store initial r3 + STR r3, [r2, #52] // Store initial r12 + MOV r3, #0xFFFFFFFF // Poison EXC_RETURN value + STR r3, [r2, #56] // Store initial lr + STR r1, [r2, #60] // Store initial pc + MOV r3, #0x01000000 // Only T-bit need be set + STR r3, [r2, #64] // Store initial xPSR + + /* Setup stack pointer. */ + // thread_ptr -> tx_thread_stack_ptr = r2; + + STR r2, [r0, #8] // Save stack pointer in thread's + // control block + BX lr // Return to caller +// } diff --git a/ports_module/cortex-m7/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex-m7/ac6/module_manager/src/tx_thread_system_return.S new file mode 100644 index 00000000..0e4fcafc --- /dev/null +++ b/ports_module/cortex-m7/ac6/module_manager/src/tx_thread_system_return.S @@ -0,0 +1,88 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .text 32 + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return Cortex-M7/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the ThreadX system. Only a */ +/* minimal context is saved since the compiler assumes temp registers */ +/* are going to get slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_system_return(VOID) +// { + .thumb_func + .global _tx_thread_system_return +_tx_thread_system_return: + + /* Return to real scheduler via PendSV. Note that this routine is often + replaced with in-line assembly in tx_port.h to improved performance. */ + + MOV r0, #0x10000000 // Load PENDSVSET bit + MOV r1, #0xE000E000 // Load NVIC base + STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + MRS r0, IPSR // Pickup IPSR + CMP r0, #0 // Is it a thread returning? + BNE _isr_context // If ISR, skip interrupt enable + MRS r1, PRIMASK // Thread context returning, pickup PRIMASK + CPSIE i // Enable interrupts + MSR PRIMASK, r1 // Restore original interrupt posture +_isr_context: + BX lr // Return to caller + +// } diff --git a/ports_module/cortex-m7/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex-m7/ac6/module_manager/src/tx_timer_interrupt.S new file mode 100644 index 00000000..00ae04c8 --- /dev/null +++ b/ports_module/cortex-m7/ac6/module_manager/src/tx_timer_interrupt.S @@ -0,0 +1,257 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .global _tx_timer_time_slice + .global _tx_timer_system_clock + .global _tx_timer_current_ptr + .global _tx_timer_list_start + .global _tx_timer_list_end + .global _tx_timer_expired_time_slice + .global _tx_timer_expired + .global _tx_thread_time_slice + .global _tx_timer_expiration_process + + + .text + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt Cortex-M7/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_timer_interrupt(VOID) +// { + .global _tx_timer_interrupt + .thumb_func +_tx_timer_interrupt: + + /* Upon entry to this routine, it is assumed that context save has already + been called, and therefore the compiler scratch registers are available + for use. */ + + /* Increment the system clock. */ + // _tx_timer_system_clock++; + + LDR r1, =_tx_timer_system_clock // Pickup address of system clock + LDR r0, [r1, #0] // Pickup system clock + ADD r0, r0, #1 // Increment system clock + STR r0, [r1, #0] // Store new system clock + + /* Test for time-slice expiration. */ + // if (_tx_timer_time_slice) + // { + + LDR r3, =_tx_timer_time_slice // Pickup address of time-slice + LDR r2, [r3, #0] // Pickup time-slice + CBZ r2, __tx_timer_no_time_slice // Is it non-active? + // Yes, skip time-slice processing + + /* Decrement the time_slice. */ + // _tx_timer_time_slice--; + + SUB r2, r2, #1 // Decrement the time-slice + STR r2, [r3, #0] // Store new time-slice value + + /* Check for expiration. */ + // if (__tx_timer_time_slice == 0) + + CBNZ r2, __tx_timer_no_time_slice // Has it expired? + // No, skip expiration processing + + /* Set the time-slice expired flag. */ + // _tx_timer_expired_time_slice = TX_TRUE; + + LDR r3, =_tx_timer_expired_time_slice // Pickup address of expired flag + MOV r0, #1 // Build expired value + STR r0, [r3, #0] // Set time-slice expiration flag + + // } + +__tx_timer_no_time_slice: + + /* Test for timer expiration. */ + // if (*_tx_timer_current_ptr) + // { + + LDR r1, =_tx_timer_current_ptr // Pickup current timer pointer address + LDR r0, [r1, #0] // Pickup current timer + LDR r2, [r0, #0] // Pickup timer list entry + CBZ r2, __tx_timer_no_timer // Is there anything in the list? + // No, just increment the timer + + /* Set expiration flag. */ + // _tx_timer_expired = TX_TRUE; + + LDR r3, =_tx_timer_expired // Pickup expiration flag address + MOV r2, #1 // Build expired value + STR r2, [r3, #0] // Set expired flag + B __tx_timer_done // Finished timer processing + + // } + // else + // { +__tx_timer_no_timer: + + /* No timer expired, increment the timer pointer. */ + // _tx_timer_current_ptr++; + + ADD r0, r0, #4 // Move to next timer + + /* Check for wrap-around. */ + // if (_tx_timer_current_ptr == _tx_timer_list_end) + + LDR r3, =_tx_timer_list_end // Pickup addr of timer list end + LDR r2, [r3, #0] // Pickup list end + CMP r0, r2 // Are we at list end? + BNE __tx_timer_skip_wrap // No, skip wrap-around logic + + /* Wrap to beginning of list. */ + // _tx_timer_current_ptr = _tx_timer_list_start; + + LDR r3, =_tx_timer_list_start // Pickup addr of timer list start + LDR r0, [r3, #0] // Set current pointer to list start + +__tx_timer_skip_wrap: + + STR r0, [r1, #0] // Store new current timer pointer + // } + +__tx_timer_done: + + + /* See if anything has expired. */ + // if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) + // { + + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of expired flag + LDR r2, [r3, #0] // Pickup time-slice expired flag + CBNZ r2, __tx_something_expired // Did a time-slice expire? + // If non-zero, time-slice expired + LDR r1, =_tx_timer_expired // Pickup addr of other expired flag + LDR r0, [r1, #0] // Pickup timer expired flag + CBZ r0, __tx_timer_nothing_expired // Did a timer expire? + // No, nothing expired + +__tx_something_expired: + + + STMDB sp!, {r0, lr} // Save the lr register on the stack + // and save r0 just to keep 8-byte alignment + + /* Did a timer expire? */ + // if (_tx_timer_expired) + // { + + LDR r1, =_tx_timer_expired // Pickup addr of expired flag + LDR r0, [r1, #0] // Pickup timer expired flag + CBZ r0, __tx_timer_dont_activate // Check for timer expiration + // If not set, skip timer activation + + /* Process timer expiration. */ + // _tx_timer_expiration_process(); + + BL _tx_timer_expiration_process // Call the timer expiration handling routine + + // } +__tx_timer_dont_activate: + + /* Did time slice expire? */ + // if (_tx_timer_expired_time_slice) + // { + + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of time-slice expired + LDR r2, [r3, #0] // Pickup the actual flag + CBZ r2, __tx_timer_not_ts_expiration // See if the flag is set + // No, skip time-slice processing + + /* Time slice interrupted thread. */ + // _tx_thread_time_slice(); + + BL _tx_thread_time_slice // Call time-slice processing + LDR r0, =_tx_thread_preempt_disable // Build address of preempt disable flag + LDR r1, [r0] // Is the preempt disable flag set? + CBNZ r1, __tx_timer_skip_time_slice // Yes, skip the PendSV logic + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r0] // Pickup the current thread pointer + LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address + LDR r3, [r2] // Pickup the execute thread pointer + LDR r0, =0xE000ED04 // Build address of control register + LDR r2, =0x10000000 // Build value for PendSV bit + CMP r1, r3 // Are they the same? + BEQ __tx_timer_skip_time_slice // If the same, there was no time-slice performed + STR r2, [r0] // Not the same, issue the PendSV for preemption +__tx_timer_skip_time_slice: + + // } + +__tx_timer_not_ts_expiration: + + LDMIA sp!, {r0, lr} // Recover lr register (r0 is just there for + // the 8-byte stack alignment + + // } + +__tx_timer_nothing_expired: + + DSB // Complete all memory access + BX lr // Return to caller + +// } diff --git a/ports_module/cortex-m7/ac6/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex-m7/ac6/module_manager/src/txm_module_manager_alignment_adjust.c new file mode 100644 index 00000000..7c39daaf --- /dev/null +++ b/ports_module/cortex-m7/ac6/module_manager/src/txm_module_manager_alignment_adjust.c @@ -0,0 +1,185 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_power_of_two_block_size Cortex-M7/MPU/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calculates a power of two size at or immediately above*/ +/* the input size and returns it to the caller. */ +/* */ +/* INPUT */ +/* */ +/* size Block size */ +/* */ +/* OUTPUT */ +/* */ +/* calculated size Rounded up to power of two */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_power_of_two_block_size(ULONG size) +{ + /* Check for 0 size. */ + if(size == 0) + return 0; + + /* Minimum MPU block size is 32. */ + if(size <= 32) + return 32; + + /* Bit twiddling trick to round to next high power of 2 + (if original size is power of 2, it will return original size. Perfect!) */ + size--; + size |= size >> 1; + size |= size >> 2; + size |= size >> 4; + size |= size >> 8; + size |= size >> 16; + size++; + + /* Return a power of 2 size at or above the input size. */ + return(size); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_alignment_adjust Cortex-M7/MPU/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function adjusts the alignment and size of the code and data */ +/* section for a given module implementation. */ +/* */ +/* INPUT */ +/* */ +/* module_preamble Pointer to module preamble */ +/* code_size Size of the code area (updated) */ +/* code_alignment Code area alignment (updated) */ +/* data_size Size of data area (updated) */ +/* data_alignment Data area alignment (updated) */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_power_of_two_block_size Calculate power of two size */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, + ULONG *code_size, + ULONG *code_alignment, + ULONG *data_size, + ULONG *data_alignment) +{ + +ULONG local_code_size; +ULONG local_code_alignment; +ULONG local_data_size; +ULONG local_data_alignment; +ULONG code_size_accum; +ULONG data_size_accum; + + /* Copy the input parameters into local variables for ease of use. */ + local_code_size = *code_size; + local_code_alignment = *code_alignment; + local_data_size = *data_size; + local_data_alignment = *data_alignment; + + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + local_code_alignment = _txm_power_of_two_block_size(local_code_size) >> 2; + code_size_accum = local_code_alignment + local_code_alignment; + code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); + code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); + local_code_size = code_size_accum; + + /* Determine data block sizes. Minimize the alignment requirement. + There are 4 MPU data entries available. The following is how the data size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to data size. + 2. 1/4 of the largest power of two that is greater than or equal to data size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + local_data_alignment = _txm_power_of_two_block_size(local_data_size) >> 2; + data_size_accum = local_data_alignment + local_data_alignment; + data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); + data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); + local_data_size = data_size_accum; + + /* Return all the information to the caller. */ + *code_size = local_code_size; + *code_alignment = local_code_alignment; + *data_size = local_data_size; + *data_alignment = local_data_alignment; +} diff --git a/ports_module/cortex-m7/ac6/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex-m7/ac6/module_manager/src/txm_module_manager_external_memory_enable.c new file mode 100644 index 00000000..8eaf2833 --- /dev/null +++ b/ports_module/cortex-m7/ac6/module_manager/src/txm_module_manager_external_memory_enable.c @@ -0,0 +1,189 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_mutex.h" +#include "tx_queue.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_external_memory_enable Cortex-M7/MPU/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates an entry in the MPU table for a shared */ +/* memory space. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* start_address Start address of memory */ +/* length Length of external memory */ +/* attributes Memory attributes (r/w) */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_mutex_get Get protection mutex */ +/* _tx_mutex_put Release protection mutex */ +/* _txm_power_of_two_block_size Round length to power of two */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, + VOID *start_address, + ULONG length, + UINT attributes) +{ + +ULONG block_size; +ULONG region_size; +ULONG srd_bits; +ULONG size_register; +ULONG address; +ULONG shared_index; +ULONG attributes_check = 0; + + /* Determine if the module manager has not been initialized yet. */ + if (_txm_module_manager_ready != TX_TRUE) + { + /* Module manager has not been initialized. */ + return(TX_NOT_AVAILABLE); + } + + /* Determine if the module is valid. */ + if (module_instance == TX_NULL) + { + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Get module manager protection mutex. */ + _tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER); + + /* Determine if the module instance is valid. */ + if (module_instance -> txm_module_instance_id != TXM_MODULE_ID) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Determine if the module instance is in the loaded state. */ + if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if the module is not ready. */ + return(TX_START_ERROR); + } + + /* Determine if there are shared memory entries available. */ + if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* No more entries available. */ + return(TX_NO_MEMORY); + } + + /* Start address and length must adhere to Cortex-M7 MPU. + The address must align with the block size. */ + + block_size = _txm_power_of_two_block_size(length); + address = (ULONG) start_address; + if(address != (address & ~(block_size - 1))) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return alignment error. */ + return(TXM_MODULE_ALIGNMENT_ERROR); + } + + /* At this point, we have a valid address and block size. + Set up MPU registers. */ + + /* Pick up index into shared memory entries. */ + shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; + + /* Save address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | 0x10; + + /* Calculate the region size. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Calculate the subregion bits. */ + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); + + /* Generate SRD, size, and enable attributes. */ + size_register = srd_bits | region_size | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; + + /* Check for optional write attribute. */ + if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) + { + attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; + } + + /* Save attribute-size register. */ + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; + + /* Keep track of shared memory address and length in module instance. */ + module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; + module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; + + /* Increment counter. */ + module_instance -> txm_module_instance_shared_memory_count++; + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/ports_module/cortex-m7/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex-m7/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c new file mode 100644 index 00000000..16c9b84b --- /dev/null +++ b/ports_module/cortex-m7/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -0,0 +1,110 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + +/* Define a macro that can be used to allocate global variables useful to + store information about the last fault. This macro is defined in + txm_module_port.h and is usually populated in the assembly language + fault handling prior to the code calling _txm_module_manager_memory_fault_handler. */ + +TXM_MODULE_MANAGER_FAULT_INFO + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_handler Cortex-M7/MPU/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles a fault associated with a memory protected */ +/* module. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_terminate Terminate thread */ +/* */ +/* CALLED BY */ +/* */ +/* Fault handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_memory_fault_handler(VOID) +{ + +TXM_MODULE_INSTANCE *module_instance_ptr; +TX_THREAD *thread_ptr; + + /* Pickup the current thread. */ + thread_ptr = _tx_thread_current_ptr; + + /* Initialize the module instance pointer to NULL. */ + module_instance_ptr = TX_NULL; + + /* Is there a thread? */ + if (thread_ptr) + { + /* Pickup the module instance. */ + module_instance_ptr = thread_ptr -> tx_thread_module_instance_ptr; + + /* Terminate the current thread. */ + _tx_thread_terminate(_tx_thread_current_ptr); + } + + /* Determine if there is a user memory fault notification callback. */ + if (_txm_module_manager_fault_notify) + { + /* Yes, call the user's notification memory fault callback. */ + (_txm_module_manager_fault_notify)(thread_ptr, module_instance_ptr); + } +} diff --git a/ports_module/cortex-m7/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex-m7/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c new file mode 100644 index 00000000..aa0f502c --- /dev/null +++ b/ports_module/cortex-m7/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -0,0 +1,84 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the external user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_notify Cortex-M7/MPU/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application callback when/if a memory */ +/* fault occurs. The supplied thread is automatically terminated, but */ +/* any other threads in the same module may still execute. */ +/* */ +/* INPUT */ +/* */ +/* notify_function Memory fault notification */ +/* function, NULL disables. */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +{ + /* Setup notification function. */ + _txm_module_manager_fault_notify = notify_function; + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/ports_module/cortex-m7/ac6/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex-m7/ac6/module_manager/src/txm_module_manager_mm_register_setup.c new file mode 100644 index 00000000..7a4e63d3 --- /dev/null +++ b/ports_module/cortex-m7/ac6/module_manager/src/txm_module_manager_mm_register_setup.c @@ -0,0 +1,530 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_region_size_get Cortex-M7/MPU/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function converts the region size in bytes to the block size */ +/* for the Cortex-M7 MPU specification. */ +/* */ +/* INPUT */ +/* */ +/* block_size Size of the block in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* MPU size specification */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_module_manager_region_size_get(ULONG block_size) +{ + +ULONG return_value; + + /* Process relative to the input block size. */ + if (block_size == 32) + { + return_value = 0x04; + } + else if (block_size == 64) + { + return_value = 0x05; + } + else if (block_size == 128) + { + return_value = 0x06; + } + else if (block_size == 256) + { + return_value = 0x07; + } + else if (block_size == 512) + { + return_value = 0x08; + } + else if (block_size == 1024) + { + return_value = 0x09; + } + else if (block_size == 2048) + { + return_value = 0x0A; + } + else if (block_size == 4096) + { + return_value = 0x0B; + } + else if (block_size == 8192) + { + return_value = 0x0C; + } + else if (block_size == 16384) + { + return_value = 0x0D; + } + else if (block_size == 32768) + { + return_value = 0x0E; + } + else if (block_size == 65536) + { + return_value = 0x0F; + } + else if (block_size == 131072) + { + return_value = 0x10; + } + else if (block_size == 262144) + { + return_value = 0x11; + } + else if (block_size == 524288) + { + return_value = 0x12; + } + else if (block_size == 1048576) + { + return_value = 0x13; + } + else if (block_size == 2097152) + { + return_value = 0x14; + } + else + { + /* Max 4MB MPU pages for modules. */ + return_value = 0x15; + } + + return(return_value); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_calculate_srd_bits Cortex-M7/MPU/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calculates the SRD bits that need to be set to */ +/* protect "length" bytes in a block. */ +/* */ +/* INPUT */ +/* */ +/* block_size Size of the block in bytes */ +/* length Actual length in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* SRD bits to be OR'ed with region attribute register. */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) +{ + +ULONG srd_bits = 0; +UINT srd_bit_index; + + /* length is smaller than block_size, set SRD bits if block_size is 256 or more. */ + if((block_size >= 256) && (length < block_size)) + { + /* Divide block_size by 8 by shifting right 3. Result is size of subregion. */ + block_size = block_size >> 3; + + /* Set SRD index into attribute register. */ + srd_bit_index = 8; + + /* If subregion overlaps length, move to the next subregion. */ + while(length > block_size) + { + length = length - block_size; + srd_bit_index++; + } + /* Check for a portion of code remaining. */ + if(length) + { + srd_bit_index++; + } + + /* Set unused subregion bits. */ + while(srd_bit_index < 16) + { + srd_bits = srd_bits | (0x1 << srd_bit_index); + srd_bit_index++; + } + } + + return(srd_bits); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_mm_register_setup Cortex-M7/MPU/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets up the MPU register definitions based on the */ +/* module's memory characteristics. */ +/* MPU layout for the Cortex-M7: */ +/* Entry Description */ +/* 0 Kernel mode entry */ +/* 1 Module code region */ +/* 2 Module code region */ +/* 3 Module code region */ +/* 4 Module code region */ +/* 5 Module data region */ +/* 6 Module data region */ +/* 7 Module data region */ +/* 8 Module data region */ +/* 9 Module shared memory region */ +/* 10 Module shared memory region */ +/* 11 Module shared memory region */ +/* 12 Unused region */ +/* 13 Unused region */ +/* 14 Unused region */ +/* 15 Unused region */ +/* */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* */ +/* OUTPUT */ +/* */ +/* MPU specifications for module in module_instance */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_manager_region_size_get */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_thread_create */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) +{ + +ULONG code_address; +ULONG code_size; +ULONG data_address; +ULONG data_size; +ULONG start_stop_stack_size; +ULONG callback_stack_size; +ULONG block_size; +ULONG region_size; +ULONG srd_bits = 0; +UINT mpu_table_index; +UINT i; + + + /* Setup the first MPU region for kernel mode entry. */ + /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. + Mask address to proper range, region 0, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | 0x10; + /* Set the attributes, size (32 bytes) and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | (_txm_module_manager_region_size_get(32) << 1) | TXM_ENABLE_REGION; + /* End of kernel mode entry setup. */ + + /* Setup code protection. */ + + /* Initialize the MPU table index. */ + mpu_table_index = 1; + + /* Pickup code starting address and actual size. */ + code_address = (ULONG) module_instance -> txm_module_instance_code_start; + code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; + + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + + /* Now loop through to setup MPU protection for the code area. */ + for (i = 0; i < TXM_MODULE_MPU_CODE_ENTRIES; i++) + { + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + if (i < 2) + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + } + + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ + else if (i == 2) + { + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size) >> 1; + } + + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + else + { + /* Calculate remaining space. */ + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | 0x10; + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; + + /* Adjust the code address. */ + code_address = code_address + block_size; + + /* Increment MPU table index. */ + mpu_table_index++; + } + /* End of code protection. */ + + /* Setup data protection. */ + + /* Reset SRD bitfield. */ + srd_bits = 0; + + /* Pickup data starting address and actual size. */ + data_address = (ULONG) module_instance -> txm_module_instance_data_start; + + /* Adjust the size of the module elements to be aligned to the default alignment. We do this + so that when we partition the allocated memory, we can simply place these regions right beside + each other without having to align their pointers. Note this only works when they all have + the same alignment. */ + + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; + start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; + callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; + + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + /* Update the data size to include thread stacks. */ + data_size = data_size + start_stop_stack_size + callback_stack_size; + + /* Determine data block sizes. Minimize the alignment requirement. + There are 4 MPU data entries available. The following is how the data size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to data size. + 2. 1/4 of the largest power of two that is greater than or equal to data size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + + /* Now loop through to setup MPU protection for the data area. */ + for (i = 0; i < TXM_MODULE_MPU_DATA_ENTRIES; i++) + { + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to data size. */ + if (i < 2) + { + block_size = _txm_power_of_two_block_size(data_size) >> 2; + } + + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ + else if (i == 2) + { + /* Subtract (block_size*2) from data_size to calculate remaining space. */ + data_size = data_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(data_size) >> 1; + } + + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + else + { + /* Calculate remaining space. */ + data_size = data_size - block_size; + block_size = _txm_power_of_two_block_size(data_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + } + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | 0x10; + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; + + /* Adjust the data address. */ + data_address = data_address + block_size; + + /* Increment MPU table index. */ + mpu_table_index++; + } + + /* Setup MPU for the remaining regions. */ + while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES) + { + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10; + + /* Increment MPU table index. */ + mpu_table_index++; + } + +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_inside_data_check Cortex-M7/MPU/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks if the specified object is inside shared */ +/* memory. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* obj_ptr Pointer to the object */ +/* obj_size Size of the object */ +/* */ +/* OUTPUT */ +/* */ +/* Whether the object is inside the shared memory region. */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Module dispatch check functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) +{ + +UINT shared_memory_index; +UINT num_shared_memory_mpu_entries; +ALIGN_TYPE shared_memory_address_start; +ALIGN_TYPE shared_memory_address_end; + + /* Check if the object is inside the module data. */ + if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && + ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) + { + return(TX_TRUE); + } + + /* Check if the object is inside the shared memory. */ + num_shared_memory_mpu_entries = module_instance -> txm_module_instance_shared_memory_count; + for (shared_memory_index = 0; shared_memory_index < num_shared_memory_mpu_entries; shared_memory_index++) + { + + shared_memory_address_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address[shared_memory_index]; + shared_memory_address_end = shared_memory_address_start + module_instance -> txm_module_instance_shared_memory_length[shared_memory_index]; + + if ((obj_ptr >= (ALIGN_TYPE) shared_memory_address_start) && + ((obj_ptr + obj_size) <= (ALIGN_TYPE) shared_memory_address_end)) + { + return(TX_TRUE); + } + } + + return(TX_FALSE); +} diff --git a/ports_module/cortex-m7/ac6/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex-m7/ac6/module_manager/src/txm_module_manager_thread_stack_build.S new file mode 100644 index 00000000..0ea5e872 --- /dev/null +++ b/ports_module/cortex-m7/ac6/module_manager/src/txm_module_manager_thread_stack_build.S @@ -0,0 +1,141 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .align 4 + .syntax unified + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_thread_stack_build Cortex-M7/MPU/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread */ +/* function_ptr Pointer to shell function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +// { + .global _txm_module_manager_thread_stack_build + .thumb_func +_txm_module_manager_thread_stack_build: + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-M should look like the following after it is built: + + Stack Top: + LR Interrupted LR (LR at time of PENDSV) + r4 Initial value for r4 + r5 Initial value for r5 + r6 Initial value for r6 + r7 Initial value for r7 + r8 Initial value for r8 + r9 Initial value for r9 + r10 Initial value for r10 + r11 Initial value for r11 + r0 Initial value for r0 (Hardware stack starts here!!) + r1 Initial value for r1 + r2 Initial value for r2 + r3 Initial value for r3 + r12 Initial value for r12 + lr Initial value for lr + pc Initial value for pc + xPSR Initial value for xPSR + + Stack Bottom: (higher memory address) */ + + LDR r2, [r0, #16] // Pickup end of stack area + BIC r2, r2, #0x7 // Align frame + SUB r2, r2, #68 // Subtract frame size + LDR r3, =0xFFFFFFFD // Build initial LR value + STR r3, [r2, #0] // Save on the stack + + /* Actually build the stack frame. */ + + MOV r3, #0 // Build initial register value + STR r3, [r2, #4] // Store initial r4 + STR r3, [r2, #8] // Store initial r5 + STR r3, [r2, #12] // Store initial r6 + STR r3, [r2, #16] // Store initial r7 + STR r3, [r2, #20] // Store initial r8 + STR r3, [r2, #28] // Store initial r10 + STR r3, [r2, #32] // Store initial r11 + + /* Hardware stack follows. */ + + STR r0, [r2, #36] // Store initial r0, which is the thread control block + + LDR r3, [r0, #8] // Pickup thread entry info pointer,which is in the stack pointer position of the thread control block. + // It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this + // function with the actual, initial stack pointer. + STR r3, [r2, #40] // Store initial r1, which is the module entry information. + LDR r3, [r3, #8] // Pickup data base register from the module information + STR r3, [r2, #24] // Store initial r9 (data base register) + MOV r3, #0 // Clear r3 again + + STR r3, [r2, #44] // Store initial r2 + STR r3, [r2, #48] // Store initial r3 + STR r3, [r2, #52] // Store initial r12 + MOV r3, #0xFFFFFFFF // Poison EXC_RETURN value + STR r3, [r2, #56] // Store initial lr + STR r1, [r2, #60] // Store initial pc + MOV r3, #0x01000000 // Only T-bit need be set + STR r3, [r2, #64] // Store initial xPSR + + /* Setup stack pointer. */ + // thread_ptr -> tx_thread_stack_ptr = r2; + + STR r2, [r0, #8] // Save stack pointer in thread's control block + BX lr // Return to caller +// } + diff --git a/ports_module/cortex-m7/gnu/example_build/build_all.bat b/ports_module/cortex-m7/gnu/example_build/build_all.bat new file mode 100644 index 00000000..70c43ec3 --- /dev/null +++ b/ports_module/cortex-m7/gnu/example_build/build_all.bat @@ -0,0 +1,5 @@ + +call build_threadx.bat +call build_threadx_module_library.bat +call build_threadx_module_sample.bat +call build_threadx_module_manager_sample.bat \ No newline at end of file diff --git a/ports_module/cortex-m7/gnu/example_build/build_threadx.bat b/ports_module/cortex-m7/gnu/example_build/build_threadx.bat new file mode 100644 index 00000000..85fc9713 --- /dev/null +++ b/ports_module/cortex-m7/gnu/example_build/build_threadx.bat @@ -0,0 +1,280 @@ +del tx.a +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb tx_initialize_low_level.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb ..\module_manager\src\tx_thread_stack_build.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb ..\module_manager\src\tx_thread_schedule.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb ..\module_manager\src\tx_thread_system_return.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb ..\module_manager\src\tx_thread_context_save.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb ..\module_manager\src\tx_thread_context_restore.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb ..\module_manager\src\tx_thread_interrupt_control.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb ..\module_manager\src\tx_timer_interrupt.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb ..\module_manager\src\txm_module_manager_thread_stack_build.S + +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_pool_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_pool_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_block_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_pool_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_pool_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_pool_search.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_byte_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_event_flags_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_event_flags_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_event_flags_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_event_flags_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_event_flags_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_event_flags_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_event_flags_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_event_flags_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_event_flags_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_event_flags_set_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_initialize_high_level.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_initialize_kernel_enter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_initialize_kernel_setup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_mutex_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_mutex_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_mutex_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_mutex_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_mutex_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_mutex_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_mutex_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_mutex_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_mutex_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_mutex_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_mutex_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_queue_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_queue_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_queue_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_queue_flush.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_queue_front_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_queue_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_queue_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_queue_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_queue_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_queue_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_queue_receive.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_queue_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_queue_send_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_semaphore_ceiling_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_semaphore_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_semaphore_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_semaphore_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_semaphore_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_semaphore_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_semaphore_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_semaphore_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_semaphore_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_semaphore_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_semaphore_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_semaphore_put_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_entry_exit_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_identify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_preemption_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_relinquish.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_reset.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_shell_entry.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_sleep.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_stack_analyze.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_stack_error_handler.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_stack_error_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_system_preempt_check.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_system_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_system_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_terminate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc ..\..\..\..\common\src\tx_thread_time_slice.c +arm-none-eabi-gcc -c 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-I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_unload.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc -I..\..\..\..\common_modules\module_manager\inc ..\..\..\..\common_modules\module_manager\src\txm_module_manager_util.c + + +arm-none-eabi-ar -r tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o +arm-none-eabi-ar -r tx.a tx_thread_interrupt_control.o tx_initialize_low_level.o +arm-none-eabi-ar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o +arm-none-eabi-ar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o +arm-none-eabi-ar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o +arm-none-eabi-ar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o +arm-none-eabi-ar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o +arm-none-eabi-ar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o +arm-none-eabi-ar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o +arm-none-eabi-ar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o +arm-none-eabi-ar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o +arm-none-eabi-ar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o +arm-none-eabi-ar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o +arm-none-eabi-ar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o +arm-none-eabi-ar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o +arm-none-eabi-ar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o +arm-none-eabi-ar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o +arm-none-eabi-ar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o +arm-none-eabi-ar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o +arm-none-eabi-ar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o +arm-none-eabi-ar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o +arm-none-eabi-ar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o +arm-none-eabi-ar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o +arm-none-eabi-ar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o +arm-none-eabi-ar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o +arm-none-eabi-ar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o +arm-none-eabi-ar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o +arm-none-eabi-ar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o +arm-none-eabi-ar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o +arm-none-eabi-ar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o +arm-none-eabi-ar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o +arm-none-eabi-ar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o +arm-none-eabi-ar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o +arm-none-eabi-ar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o +arm-none-eabi-ar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o + +arm-none-eabi-ar -r tx.a txm_module_manager_alignment_adjust.o txm_module_manager_application_request.o txm_module_manager_callback_request.o +arm-none-eabi-ar -r tx.a txm_module_manager_event_flags_notify_trampoline.o txm_module_manager_external_memory_enable.o txm_module_manager_file_load.o +arm-none-eabi-ar -r tx.a txm_module_manager_in_place_load.o txm_module_manager_initialize.o +arm-none-eabi-ar -r tx.a txm_module_manager_kernel_dispatch.o txm_module_manager_maximum_module_priority_set.o txm_module_manager_memory_fault_handler.o +arm-none-eabi-ar -r tx.a txm_module_manager_memory_fault_notify.o txm_module_manager_memory_load.o txm_module_manager_object_pointer_get.o +arm-none-eabi-ar -r tx.a txm_module_manager_object_pool_create.o txm_module_manager_queue_notify_trampoline.o txm_module_manager_semaphore_notify_trampoline.o +arm-none-eabi-ar -r tx.a txm_module_manager_mm_register_setup.o txm_module_manager_start.o txm_module_manager_stop.o +arm-none-eabi-ar -r tx.a txm_module_manager_thread_create.o txm_module_manager_thread_notify_trampoline.o txm_module_manager_thread_reset.o +arm-none-eabi-ar -r tx.a txm_module_manager_timer_notify_trampoline.o txm_module_manager_unload.o txm_module_manager_thread_stack_build.o +arm-none-eabi-ar -r tx.a txm_module_manager_internal_load.o +arm-none-eabi-ar -r tx.a txm_module_manager_object_allocate.o +arm-none-eabi-ar -r tx.a txm_module_manager_object_deallocate.o +arm-none-eabi-ar -r tx.a txm_module_manager_object_pointer_get_extended.o +arm-none-eabi-ar -r tx.a txm_module_manager_properties_get.o +arm-none-eabi-ar -r tx.a txm_module_manager_util.o \ No newline at end of file diff --git a/ports_module/cortex-m7/gnu/example_build/build_threadx_module_library.bat b/ports_module/cortex-m7/gnu/example_build/build_threadx_module_library.bat new file mode 100644 index 00000000..865d611f --- /dev/null +++ b/ports_module/cortex-m7/gnu/example_build/build_threadx_module_library.bat @@ -0,0 +1,118 @@ +del txm.a + +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_set_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_application_request.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_callback_request_thread_entry.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_object_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_object_deallocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_object_pointer_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\module_lib\src\txm_module_thread_shell_entry.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_thread_system_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_flush.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_front_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_receive.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_send_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_ceiling_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_put_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_entry_exit_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_identify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_interrupt_control.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_preemption_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_relinquish.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_reset.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_sleep.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_stack_error_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_terminate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_time_slice_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_wait_abort.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_time_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_time_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_buffer_full_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_disable.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_enable.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_event_filter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_event_unfilter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_isr_enter_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_isr_exit_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_user_event_insert.c + +arm-none-eabi-ar -r txm.a txm_block_allocate.o txm_block_pool_create.o txm_block_pool_delete.o txm_block_pool_info_get.o txm_block_pool_performance_info_get.o txm_block_pool_performance_system_info_get.o +arm-none-eabi-ar -r txm.a txm_block_pool_prioritize.o txm_block_release.o +arm-none-eabi-ar -r txm.a txm_byte_allocate.o txm_byte_pool_create.o txm_byte_pool_delete.o txm_byte_pool_info_get.o txm_byte_pool_performance_info_get.o txm_byte_pool_performance_system_info_get.o +arm-none-eabi-ar -r txm.a txm_byte_pool_prioritize.o txm_byte_release.o +arm-none-eabi-ar -r txm.a txm_event_flags_create.o txm_event_flags_delete.o txm_event_flags_get.o txm_event_flags_info_get.o txm_event_flags_performance_info_get.o txm_event_flags_performance_system_info_get.o +arm-none-eabi-ar -r txm.a txm_event_flags_set.o txm_event_flags_set_notify.o +arm-none-eabi-ar -r txm.a txm_module_application_request.o txm_module_callback_request_thread_entry.o txm_module_object_allocate.o txm_module_object_deallocate.o txm_module_object_pointer_get.o txm_module_thread_shell_entry.o txm_module_thread_system_suspend.o +arm-none-eabi-ar -r txm.a txm_mutex_create.o txm_mutex_delete.o txm_mutex_get.o txm_mutex_info_get.o txm_mutex_performance_info_get.o txm_mutex_performance_system_info_get.o txm_mutex_prioritize.o txm_mutex_put.o +arm-none-eabi-ar -r txm.a txm_queue_create.o txm_queue_delete.o txm_queue_flush.o txm_queue_front_send.o txm_queue_info_get.o txm_queue_performance_info_get.o txm_queue_performance_system_info_get.o +arm-none-eabi-ar -r txm.a txm_queue_prioritize.o txm_queue_receive.o txm_queue_send.o txm_queue_send_notify.o +arm-none-eabi-ar -r txm.a txm_semaphore_ceiling_put.o txm_semaphore_create.o txm_semaphore_delete.o txm_semaphore_get.o txm_semaphore_info_get.o txm_semaphore_performance_info_get.o txm_semaphore_performance_system_info_get.o +arm-none-eabi-ar -r txm.a txm_semaphore_prioritize.o txm_semaphore_put.o txm_semaphore_put_notify.o +arm-none-eabi-ar -r txm.a txm_thread_create.o txm_thread_delete.o txm_thread_entry_exit_notify.o txm_thread_identify.o txm_thread_info_get.o txm_thread_interrupt_control.o txm_thread_performance_info_get.o +arm-none-eabi-ar -r txm.a txm_thread_performance_system_info_get.o txm_thread_preemption_change.o txm_thread_priority_change.o txm_thread_relinquish.o txm_thread_reset.o txm_thread_resume.o +arm-none-eabi-ar -r txm.a txm_thread_sleep.o txm_thread_stack_error_notify.o txm_thread_suspend.o txm_thread_terminate.o txm_thread_time_slice_change.o txm_thread_wait_abort.o +arm-none-eabi-ar -r txm.a txm_time_get.o txm_time_set.o +arm-none-eabi-ar -r txm.a txm_timer_activate.o txm_timer_change.o txm_timer_create.o txm_timer_deactivate.o txm_timer_delete.o txm_timer_info_get.o txm_timer_performance_info_get.o txm_timer_performance_system_info_get.o +arm-none-eabi-ar -r txm.a txm_trace_buffer_full_notify.o txm_trace_disable.o txm_trace_enable.o txm_trace_event_filter.o txm_trace_event_unfilter.o txm_trace_isr_enter_insert.o txm_trace_isr_exit_insert.o txm_trace_user_event_insert.o diff --git a/ports_module/cortex-m7/gnu/example_build/build_threadx_module_manager_sample.bat b/ports_module/cortex-m7/gnu/example_build/build_threadx_module_manager_sample.bat new file mode 100644 index 00000000..9130af01 --- /dev/null +++ b/ports_module/cortex-m7/gnu/example_build/build_threadx_module_manager_sample.bat @@ -0,0 +1,4 @@ +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc sample_threadx_module_manager.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb tx_simulator_startup.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb cortexm_crt0.S +arm-none-eabi-ld -A cortex-m7 -ereset_handler -T sample_threadx.ld tx_simulator_startup.o cortexm_crt0.o sample_threadx_module_manager.o tx.a libc.a -o sample_threadx_module_manager.axf -M > sample_threadx_module_manager.map diff --git a/ports_module/cortex-m7/gnu/example_build/build_threadx_module_sample.bat b/ports_module/cortex-m7/gnu/example_build/build_threadx_module_sample.bat new file mode 100644 index 00000000..de4e6a1f --- /dev/null +++ b/ports_module/cortex-m7/gnu/example_build/build_threadx_module_sample.bat @@ -0,0 +1,5 @@ +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -fpie -fno-plt -mpic-data-is-text-relative -msingle-pic-base txm_module_preamble.s +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -fpie -fno-plt -mpic-data-is-text-relative -msingle-pic-base gcc_setup.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -fpie -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc sample_threadx_module.c +arm-none-eabi-ld -A cortex-m7 -T sample_threadx_module.ld txm_module_preamble.o gcc_setup.o sample_threadx_module.o -e _txm_module_thread_shell_entry txm.a -o sample_threadx_module.axf -M > sample_threadx_module.map + diff --git a/ports_module/cortex-m7/gnu/example_build/cortexm_crt0.s b/ports_module/cortex-m7/gnu/example_build/cortexm_crt0.s new file mode 100644 index 00000000..d4cb1636 --- /dev/null +++ b/ports_module/cortex-m7/gnu/example_build/cortexm_crt0.s @@ -0,0 +1,127 @@ + .global _start + .extern main + + + .section .init, "ax" + .code 16 + .align 2 + .thumb_func + + +_start: + CPSID i + ldr r1, =__stack_end__ + mov sp, r1 + + + /* Copy initialised sections into RAM if required. */ + ldr r0, =__data_load_start__ + ldr r1, =__data_start__ + ldr r2, =__data_end__ + bl crt0_memory_copy + ldr r0, =__text_load_start__ + ldr r1, =__text_start__ + ldr r2, =__text_end__ + bl crt0_memory_copy + ldr r0, =__fast_load_start__ + ldr r1, =__fast_start__ + ldr r2, =__fast_end__ + bl crt0_memory_copy + ldr r0, =__ctors_load_start__ + ldr r1, =__ctors_start__ + ldr r2, =__ctors_end__ + bl crt0_memory_copy + ldr r0, =__dtors_load_start__ + ldr r1, =__dtors_start__ + ldr r2, =__dtors_end__ + bl crt0_memory_copy + ldr r0, =__rodata_load_start__ + ldr r1, =__rodata_start__ + ldr r2, =__rodata_end__ + bl crt0_memory_copy + + + /* Zero bss. */ + ldr r0, =__bss_start__ + ldr r1, =__bss_end__ + mov r2, #0 + bl crt0_memory_set + + + /* Setup heap - not recommended for Threadx but here for compatibility reasons */ + ldr r0, = __heap_start__ + ldr r1, = __heap_end__ + sub r1, r1, r0 + mov r2, #0 + str r2, [r0] + add r0, r0, #4 + str r1, [r0] + + + /* constructors in case of using C++ */ + ldr r0, =__ctors_start__ + ldr r1, =__ctors_end__ +crt0_ctor_loop: + cmp r0, r1 + beq crt0_ctor_end + ldr r2, [r0] + add r0, #4 + push {r0-r1} + blx r2 + pop {r0-r1} + b crt0_ctor_loop +crt0_ctor_end: + + + /* Setup call frame for main() */ + mov r0, #0 + mov lr, r0 + mov r12, sp + + +start: + /* Jump to main() */ + mov r0, #0 + mov r1, #0 + ldr r2, =main + blx r2 + /* when main returns, loop forever. */ +crt0_exit_loop: + b crt0_exit_loop + + + + /* Startup helper functions. */ + + +crt0_memory_copy: + cmp r0, r1 + beq memory_copy_done + sub r2, r2, r1 + beq memory_copy_done +memory_copy_loop: + ldrb r3, [r0] + add r0, r0, #1 + strb r3, [r1] + add r1, r1, #1 + sub r2, r2, #1 + bne memory_copy_loop +memory_copy_done: + bx lr + + +crt0_memory_set: + cmp r0, r1 + beq memory_set_done + strb r2, [r0] + add r0, r0, #1 + b crt0_memory_set +memory_set_done: + bx lr + + + /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */ + .section .stack, "wa", %nobits + .section .stack_process, "wa", %nobits + .section .heap, "wa", %nobits + \ No newline at end of file diff --git a/ports_module/cortex-m7/gnu/example_build/gcc_setup.s b/ports_module/cortex-m7/gnu/example_build/gcc_setup.s new file mode 100644 index 00000000..d7c61892 --- /dev/null +++ b/ports_module/cortex-m7/gnu/example_build/gcc_setup.s @@ -0,0 +1,127 @@ + + .text + .align 4 + .syntax unified + + .global _gcc_setup + .thumb_func +_gcc_setup: + + STMDB sp!, {r3, r4, r5, r6, r7, lr} // Store other preserved registers + + ldr r3, =__FLASH_segment_start__ + ldr r4, =__RAM_segment_start__ + mov r5,r0 + + /* Copy GOT table. */ + + ldr r0, =__got_load_start__ + sub r0,r0,r3 + add r0,r0,r5 + ldr r1, =__new_got_start__ + sub r1,r1, r4 + add r1,r1,r9 + ldr r2, =__new_got_end__ + sub r2,r2,r4 + add r2,r2,r9 + +new_got_setup: + cmp r1, r2 // See if there are more GOT entries + beq got_setup_done // No, done with GOT setup + ldr r6, [r0] // Pickup current GOT entry + cmp r6, #0 // Is it 0? + beq address_built // Yes, just skip the adjustment + cmp r6, r4 // Is it in the code or data area? + blt flash_area // If less than, it is a code address + sub r6, r6, r4 // Compute offset of data area + add r6, r6, r9 // Build address based on the loaded data address + b address_built // Finished building address +flash_area: + sub r6, r6, r3 // Compute offset of code area + add r6, r6, r5 // Build address based on the loaded code address +address_built: + str r6, [r1] // Store in new GOT table + add r0, r0, #4 // Move to next entry + add r1, r1, #4 // + b new_got_setup // Continue at the top of the loop +got_setup_done: + + + /* Copy initialised sections into RAM if required. */ + + ldr r0, =__data_load_start__ + sub r0,r0,r3 + add r0,r0,r5 + ldr r1, =__data_start__ + sub r1,r1, r4 + add r1,r1,r9 + ldr r2, =__data_end__ + sub r2,r2,r4 + add r2,r2,r9 + bl crt0_memory_copy + + /* Zero bss. */ + + ldr r0, =__bss_start__ + sub r0,r0,r4 + add r0,r0,r9 + ldr r1, =__bss_end__ + sub r1,r1,r4 + add r1,r1,r9 + mov r2, #0 + bl crt0_memory_set + + + /* Setup heap - not recommended for Threadx but here for compatibility reasons */ + + ldr r0, =__heap_start__ + sub r0,r0,r4 + add r0,r0,r9 + ldr r1, =__heap_end__ + sub r1,r1,r4 + add r1,r1,r9 + sub r1,r1,r0 + mov r2, #0 + str r2, [r0] + add r0, r0, #4 + str r1, [r0] + + LDMIA sp!, {r3, r4, r5, r6, r7, lr} // Store other preserved registers + bx lr // Return to caller + + .align 4 + + /* Startup helper functions. */ + + .thumb_func +crt0_memory_copy: + + cmp r0, r1 + beq memory_copy_done + cmp r2, r1 + beq memory_copy_done + sub r2, r2, r1 +memory_copy_loop: + ldrb r3, [r0] + add r0, r0, #1 + strb r3, [r1] + add r1, r1, #1 + sub r2, r2, #1 + cmp r2, #0 + bne memory_copy_loop +memory_copy_done: + bx lr + + .thumb_func +crt0_memory_set: + cmp r0, r1 + beq memory_set_done + strb r2, [r0] + add r0, r0, #1 + b crt0_memory_set +memory_set_done: + bx lr + + /* Setup attibutes of heap section so it doesn't take up room in the elf file */ + .section .heap, "wa", %nobits + \ No newline at end of file diff --git a/ports_module/cortex-m7/gnu/example_build/sample_threadx.ld b/ports_module/cortex-m7/gnu/example_build/sample_threadx.ld new file mode 100644 index 00000000..4a7ce31d --- /dev/null +++ b/ports_module/cortex-m7/gnu/example_build/sample_threadx.ld @@ -0,0 +1,206 @@ +MEMORY +{ + UNPLACED_SECTIONS (wx) : ORIGIN = 0x100000000, LENGTH = 0 + CM3_System_Control_Space (wx) : ORIGIN = 0xe000e000, LENGTH = 0x00001000 + AHB_Peripherals (wx) : ORIGIN = 0x50000000, LENGTH = 0x00200000 + APB1_Peripherals (wx) : ORIGIN = 0x40080000, LENGTH = 0x00080000 + APB0_Peripherals (wx) : ORIGIN = 0x40000000, LENGTH = 0x00080000 + GPIO (wx) : ORIGIN = 0x2009c000, LENGTH = 0x00004000 + AHBSRAM1 (wx) : ORIGIN = 0x20080000, LENGTH = 0x00004000 + AHBSRAM0 (wx) : ORIGIN = 0x2007c000, LENGTH = 0x00004000 + RAM (wx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 +} + + +SECTIONS +{ + __CM3_System_Control_Space_segment_start__ = 0xe000e000; + __CM3_System_Control_Space_segment_end__ = 0xe000f000; + __AHB_Peripherals_segment_start__ = 0x50000000; + __AHB_Peripherals_segment_end__ = 0x50200000; + __APB1_Peripherals_segment_start__ = 0x40080000; + __APB1_Peripherals_segment_end__ = 0x40100000; + __APB0_Peripherals_segment_start__ = 0x40000000; + __APB0_Peripherals_segment_end__ = 0x40080000; + __GPIO_segment_start__ = 0x2009c000; + __GPIO_segment_end__ = 0x200a0000; + __AHBSRAM1_segment_start__ = 0x20080000; + __AHBSRAM1_segment_end__ = 0x20084000; + __AHBSRAM0_segment_start__ = 0x2007c000; + __AHBSRAM0_segment_end__ = 0x20080000; + __RAM_segment_start__ = 0x20000000; + __RAM_segment_end__ = 0x20008000; + __FLASH_segment_start__ = 0x00000000; + __FLASH_segment_end__ = 0x00030000; + + __STACKSIZE__ = 1024; + __STACKSIZE_PROCESS__ = 0; + __STACKSIZE_IRQ__ = 0; + __STACKSIZE_FIQ__ = 0; + __STACKSIZE_SVC__ = 0; + __STACKSIZE_ABT__ = 0; + __STACKSIZE_UND__ = 0; + __HEAPSIZE__ = 128; + + __vectors_load_start__ = __FLASH_segment_start__; + .vectors __FLASH_segment_start__ : AT(__FLASH_segment_start__) + { + __vectors_start__ = .; + *(.vectors .vectors.*) + } + __vectors_end__ = __vectors_start__ + SIZEOF(.vectors); + + . = ASSERT(__vectors_end__ >= __FLASH_segment_start__ && __vectors_end__ <= (__FLASH_segment_start__ + 0x00030000) , "error: .vectors is too large to fit in FLASH memory segment"); + + __init_load_start__ = ALIGN(__vectors_end__ , 4); + .init ALIGN(__vectors_end__ , 4) : AT(ALIGN(__vectors_end__ , 4)) + { + __init_start__ = .; + *(.init .init.*) + } + __init_end__ = __init_start__ + SIZEOF(.init); + + . = ASSERT(__init_end__ >= __FLASH_segment_start__ && __init_end__ <= (__FLASH_segment_start__ + 0x00030000) , "error: .init is too large to fit in FLASH memory segment"); + + __text_load_start__ = ALIGN(__init_end__ , 4); + .text ALIGN(__init_end__ , 4) : AT(ALIGN(__init_end__ , 4)) + { + __text_start__ = .; + *(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table) + } + __text_end__ = __text_start__ + SIZEOF(.text); + + . = ASSERT(__text_end__ >= __FLASH_segment_start__ && __text_end__ <= (__FLASH_segment_start__ + 0x00030000) , "error: .text is too large to fit in FLASH memory segment"); + + __dtors_load_start__ = ALIGN(__text_end__ , 4); + .dtors ALIGN(__text_end__ , 4) : AT(ALIGN(__text_end__ , 4)) + { + __dtors_start__ = .; + KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) + } + __dtors_end__ = __dtors_start__ + SIZEOF(.dtors); + + . = ASSERT(__dtors_end__ >= __FLASH_segment_start__ && __dtors_end__ <= (__FLASH_segment_start__ + 0x00030000) , "error: .dtors is too large to fit in FLASH memory segment"); + + __ctors_load_start__ = ALIGN(__dtors_end__ , 4); + .ctors ALIGN(__dtors_end__ , 4) : AT(ALIGN(__dtors_end__ , 4)) + { + __ctors_start__ = .; + KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) + } + __ctors_end__ = __ctors_start__ + SIZEOF(.ctors); + + . = ASSERT(__ctors_end__ >= __FLASH_segment_start__ && __ctors_end__ <= (__FLASH_segment_start__ + 0x00030000) , "error: .ctors is too large to fit in FLASH memory segment"); + + __rodata_load_start__ = ALIGN(__ctors_end__ , 4); + .rodata ALIGN(__ctors_end__ , 4) : AT(ALIGN(__ctors_end__ , 4)) + { + __rodata_start__ = .; + *(.rodata .rodata.* .gnu.linkonce.r.*) + } + __rodata_end__ = __rodata_start__ + SIZEOF(.rodata); + + . = ASSERT(__rodata_end__ >= __FLASH_segment_start__ && __rodata_end__ <= (__FLASH_segment_start__ + 0x00030000) , "error: .rodata is too large to fit in FLASH memory segment"); + + __fast_load_start__ = ALIGN(__rodata_end__ , 4); + .fast ALIGN(__RAM_segment_start__ , 4) : AT(ALIGN(__rodata_end__ , 4)) + { + __fast_start__ = .; + *(.fast .fast.*) + } + __fast_end__ = __fast_start__ + SIZEOF(.fast); + + __fast_load_end__ = __fast_load_start__ + SIZEOF(.fast); + + . = ASSERT((__fast_load_start__ + SIZEOF(.fast)) >= __FLASH_segment_start__ && (__fast_load_start__ + SIZEOF(.fast)) <= (__FLASH_segment_start__ + 0x00030000) , "error: .fast is too large to fit in FLASH memory segment"); + + .fast_run ALIGN(__RAM_segment_start__ , 4) (NOLOAD) : + { + __fast_run_start__ = .; + . = MAX(__fast_run_start__ + SIZEOF(.fast), .); + } + __fast_run_end__ = __fast_run_start__ + SIZEOF(.fast_run); + + . = ASSERT(__fast_run_end__ >= __RAM_segment_start__ && __fast_run_end__ <= (__RAM_segment_start__ + 0x00020000) , "error: .fast_run is too large to fit in RAM memory segment"); + + __data_load_start__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4); + .data ALIGN(__fast_run_end__ , 4) : AT(ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4)) + { + __data_start__ = .; + *(.data .data.* .gnu.linkonce.d.*) + } + __data_end__ = __data_start__ + SIZEOF(.data); + + __data_load_end__ = __data_load_start__ + SIZEOF(.data); + + __FLASH_segment_used_end__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4) + SIZEOF(.data); + + . = ASSERT((__data_load_start__ + SIZEOF(.data)) >= __FLASH_segment_start__ && (__data_load_start__ + SIZEOF(.data)) <= (__FLASH_segment_start__ + 0x00030000) , "error: .data is too large to fit in FLASH memory segment"); + + .data_run ALIGN(__fast_run_end__ , 4) (NOLOAD) : + { + __data_run_start__ = .; + . = MAX(__data_run_start__ + SIZEOF(.data), .); + } + __data_run_end__ = __data_run_start__ + SIZEOF(.data_run); + + . = ASSERT(__data_run_end__ >= __RAM_segment_start__ && __data_run_end__ <= (__RAM_segment_start__ + 0x00020000) , "error: .data_run is too large to fit in RAM memory segment"); + + __bss_load_start__ = ALIGN(__data_run_end__ , 4); + .bss ALIGN(__data_run_end__ , 4) (NOLOAD) : AT(ALIGN(__data_run_end__ , 4)) + { + __bss_start__ = .; + *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON) + } + __bss_end__ = __bss_start__ + SIZEOF(.bss); + + . = ASSERT(__bss_end__ >= __RAM_segment_start__ && __bss_end__ <= (__RAM_segment_start__ + 0x00020000) , "error: .bss is too large to fit in RAM memory segment"); + + __non_init_load_start__ = ALIGN(__bss_end__ , 4); + .non_init ALIGN(__bss_end__ , 4) (NOLOAD) : AT(ALIGN(__bss_end__ , 4)) + { + __non_init_start__ = .; + *(.non_init .non_init.*) + } + __non_init_end__ = __non_init_start__ + SIZEOF(.non_init); + + . = ASSERT(__non_init_end__ >= __RAM_segment_start__ && __non_init_end__ <= (__RAM_segment_start__ + 0x00020000) , "error: .non_init is too large to fit in RAM memory segment"); + + __heap_load_start__ = ALIGN(__non_init_end__ , 4); + .heap ALIGN(__non_init_end__ , 4) (NOLOAD) : AT(ALIGN(__non_init_end__ , 4)) + { + __heap_start__ = .; + *(.heap) + . = ALIGN(MAX(__heap_start__ + __HEAPSIZE__ , .), 4); + } + __heap_end__ = __heap_start__ + SIZEOF(.heap); + + . = ASSERT(__heap_end__ >= __RAM_segment_start__ && __heap_end__ <= (__RAM_segment_start__ + 0x00020000) , "error: .heap is too large to fit in RAM memory segment"); + + __stack_load_start__ = ALIGN(__heap_end__ , 4); + .stack ALIGN(__heap_end__ , 4) (NOLOAD) : AT(ALIGN(__heap_end__ , 4)) + { + __stack_start__ = .; + *(.stack) + . = ALIGN(MAX(__stack_start__ + __STACKSIZE__ , .), 4); + } + __stack_end__ = __stack_start__ + SIZEOF(.stack); + + . = ASSERT(__stack_end__ >= __RAM_segment_start__ && __stack_end__ <= (__RAM_segment_start__ + 0x00020000) , "error: .stack is too large to fit in RAM memory segment"); + + __stack_process_load_start__ = ALIGN(__stack_end__ , 4); + .stack_process ALIGN(__stack_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_end__ , 4)) + { + __stack_process_start__ = .; + *(.stack_process) + . = ALIGN(MAX(__stack_process_start__ + __STACKSIZE_PROCESS__ , .), 4); + } + __stack_process_end__ = __stack_process_start__ + SIZEOF(.stack_process); + + __RAM_segment_used_end__ = ALIGN(__stack_end__ , 4) + SIZEOF(.stack_process); + + . = ASSERT(__stack_process_end__ >= __RAM_segment_start__ && __stack_process_end__ <= (__RAM_segment_start__ + 0x00020000) , "error: .stack_process is too large to fit in RAM memory segment"); + +} + diff --git a/ports_module/cortex-m7/gnu/example_build/sample_threadx_module.c b/ports_module/cortex-m7/gnu/example_build/sample_threadx_module.c new file mode 100644 index 00000000..52557312 --- /dev/null +++ b/ports_module/cortex-m7/gnu/example_build/sample_threadx_module.c @@ -0,0 +1,428 @@ +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, + event flags group, byte pool, and block pool. */ + +/* Specify that this is a module! */ + +#define TXM_MODULE + + +/* Include the ThreadX module definitions. */ + +#include "txm_module.h" + + +/* Define constants. */ + +#define DEMO_STACK_SIZE 512 +#define DEMO_BYTE_POOL_SIZE 6000 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the pool space in the bss section of the module. ULONG is used to + get the word alignment. */ + +ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD *thread_0; +TX_THREAD *thread_1; +TX_THREAD *thread_2; +TX_THREAD *thread_3; +TX_THREAD *thread_4; +TX_THREAD *thread_5; +TX_THREAD *thread_6; +TX_THREAD *thread_7; +TX_QUEUE *queue_0; +TX_SEMAPHORE *semaphore_0; +TX_MUTEX *mutex_0; +TX_EVENT_FLAGS_GROUP *event_flags_0; +TX_BYTE_POOL *byte_pool_0; +TX_BLOCK_POOL *block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; +ULONG semaphore_0_puts; +ULONG event_0_sets; +ULONG queue_0_sends; + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + +void semaphore_0_notify(TX_SEMAPHORE *semaphore_ptr) +{ + + if (semaphore_ptr == semaphore_0) + semaphore_0_puts++; +} + + +void event_0_notify(TX_EVENT_FLAGS_GROUP *event_flag_group_ptr) +{ + + if (event_flag_group_ptr == event_flags_0) + event_0_sets++; +} + + +void queue_0_notify(TX_QUEUE *queue_ptr) +{ + + if (queue_ptr == queue_0) + queue_0_sends++; +} + + +/* Define the module start function. */ + +void demo_module_start(ULONG id) +{ + +CHAR *pointer; + + /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + the control block(s). */ + txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_2, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_3, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_4, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_5, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_6, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_7, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&queue_0, sizeof(TX_QUEUE)); + txm_module_object_allocate((void*)&semaphore_0, sizeof(TX_SEMAPHORE)); + txm_module_object_allocate((void*)&mutex_0, sizeof(TX_MUTEX)); + txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); + txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); + txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(byte_pool_0, "module byte pool 0", (UCHAR*)demo_module_pool_space, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(queue_0, "module queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + tx_queue_send_notify(queue_0, queue_0_notify); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(semaphore_0, "module semaphore 0", 1); + + tx_semaphore_put_notify(semaphore_0, semaphore_0_notify); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(event_flags_0, "module event flags 0"); + + tx_event_flags_set_notify(event_flags_0, event_0_notify); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(mutex_0, "module mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(block_pool_0, "module block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + /* Test memory handler. */ + *(ULONG *)0x20010000 = 0xCDCDCDCD; + + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + diff --git a/ports_module/cortex-m7/gnu/example_build/sample_threadx_module.ld b/ports_module/cortex-m7/gnu/example_build/sample_threadx_module.ld new file mode 100644 index 00000000..a33fbfeb --- /dev/null +++ b/ports_module/cortex-m7/gnu/example_build/sample_threadx_module.ld @@ -0,0 +1,210 @@ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00030000, LENGTH = 0x00010000 + RAM (wx) : ORIGIN = 0, LENGTH = 0x00100000 +} + + +SECTIONS +{ + __FLASH_segment_start__ = 0x00030000; + __FLASH_segment_end__ = 0x00040000; + __RAM_segment_start__ = 0; + __RAM_segment_end__ = 0x8000; + + __HEAPSIZE__ = 128; + + __preamble_load_start__ = __FLASH_segment_start__; + .preamble __FLASH_segment_start__ : AT(__FLASH_segment_start__) + { + __preamble_start__ = .; + *(.preamble .preamble.*) + } + __preamble_end__ = __preamble_start__ + SIZEOF(.preamble); + + __dynsym_load_start__ = ALIGN(__preamble_end__ , 4); + .dynsym ALIGN(__dynsym_load_start__ , 4) : AT(ALIGN(__dynsym_load_start__ , 4)) + { + . = ALIGN(4); + KEEP (*(.dynsym)) + KEEP (*(.dynsym*)) + . = ALIGN(4); + } + __dynsym_end__ = __dynsym_load_start__ + SIZEOF(.dynsym); + + __dynstr_load_start__ = ALIGN(__dynsym_end__ , 4); + .dynstr ALIGN(__dynstr_load_start__ , 4) : AT(ALIGN(__dynstr_load_start__, 4)) + { + . = ALIGN(4); + KEEP (*(.dynstr)) + KEEP (*(.dynstr*)) + . = ALIGN(4); + } + __dynstr_end__ = __dynstr_load_start__ + SIZEOF(.dynstr); + + __reldyn_load_start__ = ALIGN(__dynstr_end__ , 4); + .rel.dyn ALIGN(__reldyn_load_start__ , 4) : AT(ALIGN(__reldyn_load_start__ , 4)) + { + . = ALIGN(4); + KEEP (*(.rel.dyn)) + KEEP (*(.rel.dyn*)) + . = ALIGN(4); + } + __reldyn_end__ = __reldyn_load_start__ + SIZEOF(.rel.dyn); + + __relplt_load_start__ = ALIGN(__reldyn_end__ , 4); + .rel.plt ALIGN(__relplt_load_start__ , 4) : AT(ALIGN(__relplt_load_start__ , 4)) + { + . = ALIGN(4); + KEEP (*(.rel.plt)) + KEEP (*(.rel.plt*)) + . = ALIGN(4); + } + __relplt_end__ = __relplt_load_start__ + SIZEOF(.rel.plt); + + __plt_load_start__ = ALIGN(__relplt_end__ , 4); + .plt ALIGN(__plt_load_start__ , 4) : AT(ALIGN(__plt_load_start__ , 4)) + { + . = ALIGN(4); + KEEP (*(.plt)) + KEEP (*(.plt*)) + . = ALIGN(4); + } + __plt_end__ = __plt_load_start__ + SIZEOF(.plt); + + __interp_load_start__ = ALIGN(__plt_end__ , 4); + .interp ALIGN(__interp_load_start__ , 4) : AT(ALIGN(__interp_load_start__ , 4)) + { + . = ALIGN(4); + KEEP (*(.interp)) + KEEP (*(.interp*)) + . = ALIGN(4); + } + __interp_end__ = __interp_load_start__ + SIZEOF(.interp); + + __hash_load_start__ = ALIGN(__interp_end__ , 4); + .hash ALIGN(__hash_load_start__ , 4) : AT(ALIGN(__hash_load_start__, 4)) + { + . = ALIGN(4); + KEEP (*(.hash)) + KEEP (*(.hash*)) + . = ALIGN(4); + } + __hash_end__ = __hash_load_start__ + SIZEOF(.hash); + + __text_load_start__ = ALIGN(__hash_end__ , 4); + .text ALIGN(__text_load_start__ , 4) : AT(ALIGN(__text_load_start__, 4)) + { + __text_start__ = .; + *(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table ) + } + __text_end__ = __text_start__ + SIZEOF(.text); + + __dtors_load_start__ = ALIGN(__text_end__ , 4); + .dtors ALIGN(__text_end__ , 4) : AT(ALIGN(__text_end__ , 4)) + { + __dtors_start__ = .; + KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) + } + __dtors_end__ = __dtors_start__ + SIZEOF(.dtors); + + __ctors_load_start__ = ALIGN(__dtors_end__ , 4); + .ctors ALIGN(__dtors_end__ , 4) : AT(ALIGN(__dtors_end__ , 4)) + { + __ctors_start__ = .; + KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) + } + __ctors_end__ = __ctors_start__ + SIZEOF(.ctors); + + __got_load_start__ = ALIGN(__ctors_end__ , 4); + .got ALIGN(__ctors_end__ , 4) : AT(ALIGN(__ctors_end__ , 4)) + { + . = ALIGN(4); + _sgot = .; + KEEP (*(.got)) + KEEP (*(.got*)) + . = ALIGN(4); + _egot = .; + } + __got_end__ = __got_load_start__ + SIZEOF(.got); + + __rodata_load_start__ = ALIGN(__got_end__ , 4); + .rodata ALIGN(__got_end__ , 4) : AT(ALIGN(__got_end__ , 4)) + { + __rodata_start__ = .; + *(.rodata .rodata.* .gnu.linkonce.r.*) + } + __rodata_end__ = __rodata_start__ + SIZEOF(.rodata); + + __code_size__ = __rodata_end__ - __FLASH_segment_start__; + + __fast_load_start__ = ALIGN(__rodata_end__ , 4); + + __fast_load_end__ = __fast_load_start__ + SIZEOF(.fast); + + __new_got_start__ = ALIGN(__RAM_segment_start__ , 4); + + __new_got_end__ = __new_got_start__ + SIZEOF(.got); + + .fast ALIGN(__new_got_end__ , 4) : AT(ALIGN(__rodata_end__ , 4)) + { + __fast_start__ = .; + *(.fast .fast.*) + } + __fast_end__ = __fast_start__ + SIZEOF(.fast); + + .fast_run ALIGN(__fast_end__ , 4) (NOLOAD) : + { + __fast_run_start__ = .; + . = MAX(__fast_run_start__ + SIZEOF(.fast), .); + } + __fast_run_end__ = __fast_run_start__ + SIZEOF(.fast_run); + + __data_load_start__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4); + .data ALIGN(__fast_run_end__ , 4) : AT(ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4)) + { + __data_start__ = .; + *(.data .data.* .gnu.linkonce.d.*) + } + __data_end__ = __data_start__ + SIZEOF(.data); + + __data_load_end__ = __data_load_start__ + SIZEOF(.data); + + __FLASH_segment_used_end__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4) + SIZEOF(.data); + + .data_run ALIGN(__fast_run_end__ , 4) (NOLOAD) : + { + __data_run_start__ = .; + . = MAX(__data_run_start__ + SIZEOF(.data), .); + } + __data_run_end__ = __data_run_start__ + SIZEOF(.data_run); + + __bss_load_start__ = ALIGN(__data_run_end__ , 4); + .bss ALIGN(__data_run_end__ , 4) (NOLOAD) : AT(ALIGN(__data_run_end__ , 4)) + { + __bss_start__ = .; + *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON) + } + __bss_end__ = __bss_start__ + SIZEOF(.bss); + + __non_init_load_start__ = ALIGN(__bss_end__ , 4); + .non_init ALIGN(__bss_end__ , 4) (NOLOAD) : AT(ALIGN(__bss_end__ , 4)) + { + __non_init_start__ = .; + *(.non_init .non_init.*) + } + __non_init_end__ = __non_init_start__ + SIZEOF(.non_init); + + __heap_load_start__ = ALIGN(__non_init_end__ , 4); + .heap ALIGN(__non_init_end__ , 4) (NOLOAD) : AT(ALIGN(__non_init_end__ , 4)) + { + __heap_start__ = .; + *(.heap) + . = ALIGN(MAX(__heap_start__ + __HEAPSIZE__ , .), 4); + } + __heap_end__ = __heap_start__ + SIZEOF(.heap); + + __data_size__ = __heap_end__ - __RAM_segment_start__; + +} + diff --git a/ports_module/cortex-m7/gnu/example_build/sample_threadx_module_manager.c b/ports_module/cortex-m7/gnu/example_build/sample_threadx_module_manager.c new file mode 100644 index 00000000..203223be --- /dev/null +++ b/ports_module/cortex-m7/gnu/example_build/sample_threadx_module_manager.c @@ -0,0 +1,109 @@ +/* Small demonstration of the ThreadX module manager. */ + +#include "tx_api.h" +#include "txm_module.h" + + +#define DEMO_STACK_SIZE 1024 + +/* Define the ThreadX object control blocks... */ + +TX_THREAD module_manager; +TXM_MODULE_INSTANCE my_module; + + +/* Define the object pool area. */ + +UCHAR object_memory[16384]; +UCHAR module_ram[32768]; + +/* Define the count of memory faults. */ + +ULONG memory_faults; + + +/* Define thread prototypes. */ + +void module_manager_entry(ULONG thread_input); + + +/* Define fault handler. */ + +VOID module_fault_handler(TX_THREAD *thread, TXM_MODULE_INSTANCE *module) +{ + + /* Just increment the fault counter. */ + memory_faults++; +} + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = (CHAR*)first_unused_memory; + + + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + pointer = pointer + DEMO_STACK_SIZE; +} + + + + +/* Define the test threads. */ + +void module_manager_entry(ULONG thread_input) +{ + + /* Initialize the module manager. */ + txm_module_manager_initialize((VOID *) module_ram, 32768); + + txm_module_manager_object_pool_create(object_memory, sizeof(object_memory)); + + /* Register a fault handler. */ + txm_module_manager_memory_fault_notify(module_fault_handler); + + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ + txm_module_manager_memory_load(&my_module, "my module", (VOID *) 0x00030000); + + /* Enable 128 byte read/write shared memory region at 0x20010000. */ + txm_module_manager_external_memory_enable(&my_module, (void *) 0x20010000, 128, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); + + /* Start the module. */ + txm_module_manager_start(&my_module); + + /* Sleep for a while.... */ + tx_thread_sleep(1000); + + /* Stop the module. */ + txm_module_manager_stop(&my_module); + + /* Unload the module. */ + txm_module_manager_unload(&my_module); + + /* Load the module that is already there. */ + txm_module_manager_in_place_load(&my_module, "my module", (VOID *) 0x00030000); + + /* Start the module again. */ + txm_module_manager_start(&my_module); + + /* Now just spin... */ + while(1) + { + + tx_thread_sleep(100); + } +} diff --git a/ports_module/cortex-m7/gnu/example_build/tx_initialize_low_level.S b/ports_module/cortex-m7/gnu/example_build/tx_initialize_low_level.S new file mode 100644 index 00000000..d4b5f65d --- /dev/null +++ b/ports_module/cortex-m7/gnu/example_build/tx_initialize_low_level.S @@ -0,0 +1,209 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global __RAM_segment_used_end__ + .global _tx_timer_interrupt + .global __main + .global _vectors + .global __tx_NMIHandler @ NMI + .global __tx_BadHandler @ HardFault + .global __tx_DBGHandler @ Monitor + .global __tx_PendSVHandler @ PendSV + .global __tx_SysTickHandler @ SysTick + .global __tx_IntHandler @ Int 0 + +SYSTEM_CLOCK = 6000000 +SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) + + .text 32 + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-M7/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +//VOID _tx_initialize_low_level(VOID) +//{ + .global _tx_initialize_low_level + .thumb_func +_tx_initialize_low_level: + + /* Disable interrupts during ThreadX initialization. */ + CPSID i + + /* Set base of available memory to end of non-initialised RAM area. */ + LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer + LDR r1, =__RAM_segment_used_end__ @ Build first free address + ADD r1, r1, #4 @ + STR r1, [r0] @ Setup first unused memory pointer + + /* Setup Vector Table Offset Register. */ + MOV r0, #0xE000E000 @ Build address of NVIC registers + LDR r1, =_vectors @ Pickup address of vector table + STR r1, [r0, #0xD08] @ Set vector table address + + /* Set system stack pointer from vector value. */ + LDR r0, =_tx_thread_system_stack_ptr @ Build address of system stack pointer + LDR r1, =_vectors @ Pickup address of vector table + LDR r1, [r1] @ Pickup reset stack pointer + STR r1, [r0] @ Save system stack pointer + + /* Enable the cycle count register. */ + LDR r0, =0xE0001000 @ Build address of DWT register + LDR r1, [r0] @ Pickup the current value + ORR r1, r1, #1 @ Set the CYCCNTENA bit + STR r1, [r0] @ Enable the cycle count register + + /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ + MOV r0, #0xE000E000 @ Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] @ Setup SysTick Reload Value + MOV r1, #0x7 @ Build SysTick Control Enable Value + STR r1, [r0, #0x10] @ Setup SysTick Control + + /* Configure handler priorities. */ + LDR r1, =0x00000000 @ Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] @ Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 @ SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] @ Setup System Handlers 8-11 Priority Registers + @ Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] @ Setup System Handlers 12-15 Priority Registers + @ Note: PnSV must be lowest priority, which is 0xFF + + + /* Return to caller. */ + BX lr +//} + + +/* Define shells for each of the unused vectors. */ + + .global __tx_BadHandler + .thumb_func +__tx_BadHandler: + B __tx_BadHandler + +/* added to catch the hardfault */ + + .global __tx_HardfaultHandler + .thumb_func +__tx_HardfaultHandler: + B __tx_HardfaultHandler + +/* Generic interrupt handler template */ + .global __tx_IntHandler + .thumb_func +__tx_IntHandler: +// VOID InterruptHandler (VOID) +// { + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter // Call the ISR enter function +#endif + + /* Do interrupt handler work here */ + /* BL .... */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit // Call the ISR exit function +#endif + POP {r0, lr} + BX LR +// } + +/* System Tick timer interrupt handler */ + .global __tx_SysTickHandler + .global SysTick_Handler + .thumb_func +__tx_SysTickHandler: + .thumb_func +SysTick_Handler: +// VOID TimerInterruptHandler (VOID) +// { + + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter // Call the ISR enter function +#endif + BL _tx_timer_interrupt +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit // Call the ISR exit function +#endif + POP {r0, lr} + BX LR +// } + + +/* NMI, DBG handlers */ + .global __tx_NMIHandler + .thumb_func +__tx_NMIHandler: + B __tx_NMIHandler + + .global __tx_DBGHandler + .thumb_func +__tx_DBGHandler: + B __tx_DBGHandler + diff --git a/ports_module/cortex-m7/gnu/example_build/tx_simulator_startup.s b/ports_module/cortex-m7/gnu/example_build/tx_simulator_startup.s new file mode 100644 index 00000000..73692924 --- /dev/null +++ b/ports_module/cortex-m7/gnu/example_build/tx_simulator_startup.s @@ -0,0 +1,73 @@ + + .syntax unified + .section .vectors, "ax" + .code 16 + .align 0 + .global _vectors + +_vectors: + .word __stack_end__ + .word reset_handler + .word __tx_NMIHandler + .word __tx_HardfaultHandler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word __tx_SVCallHandler //_SVC_Handler - used by Threadx scheduler // + .word __tx_DBGHandler + .word 0 // Reserved + .word __tx_PendSVHandler + .word __tx_SysTickHandler // Used by Threadx timer functionality + .word __tx_BadHandler // Populate with user Interrupt handler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + .word __tx_BadHandler + + + + .section .init, "ax" + .global reset_handler + .thumb_func +reset_handler: + +// low level hardware config, such as PLL setup goes here + + b _start + + + diff --git a/ports_module/cortex-m7/gnu/example_build/txm_module_preamble.S b/ports_module/cortex-m7/gnu/example_build/txm_module_preamble.S new file mode 100644 index 00000000..e2df9b29 --- /dev/null +++ b/ports_module/cortex-m7/gnu/example_build/txm_module_preamble.S @@ -0,0 +1,58 @@ + .text + .align 4 + .syntax unified + + /* Define public symbols. */ + .global __txm_module_preamble + + /* Define application-specific start/stop entry points for the module. */ + .global demo_module_start + + /* Define common external refrences. */ + .global _txm_module_thread_shell_entry + .global _txm_module_callback_request_thread_entry + +__txm_module_preamble: + .dc.l 0x4D4F4455 // Module ID + .dc.l 0x6 // Module Major Version + .dc.l 0x1 // Module Minor Version + .dc.l 32 // Module Preamble Size in 32-bit words + .dc.l 0x12345678 // Module ID (application defined) + .dc.l 0x02000007 // Module Properties where: + // Bits 31-24: Compiler ID + // 0 -> IAR + // 1 -> RVDS + // 2 -> GNU + // Bits 23-3: Reserved + // Bit 2: 0 -> Disable shared/external memory access + // 1 -> Enable shared/external memory access + // Bit 1: 0 -> No MPU protection + // 1 -> MPU protection (must have user mode selected - bit 0 set) + // Bit 0: 0 -> Privileged mode execution + // 1 -> User mode execution + .dc.l _txm_module_thread_shell_entry - . - 0 // Module Shell Entry Point + .dc.l demo_module_start - . - 0 // Module Start Thread Entry Point + .dc.l 0 // Module Stop Thread Entry Point + .dc.l 1 // Module Start/Stop Thread Priority + .dc.l 1024 // Module Start/Stop Thread Stack Size + .dc.l _txm_module_callback_request_thread_entry - . - 0 // Module Callback Thread Entry + .dc.l 1 // Module Callback Thread Priority + .dc.l 1024 // Module Callback Thread Stack Size + .dc.l __code_size__ // Module Code Size + .dc.l __data_size__ // Module Data Size + .dc.l 0 // Reserved 0 + .dc.l 0 // Reserved 1 + .dc.l 0 // Reserved 2 + .dc.l 0 // Reserved 3 + .dc.l 0 // Reserved 4 + .dc.l 0 // Reserved 5 + .dc.l 0 // Reserved 6 + .dc.l 0 // Reserved 7 + .dc.l 0 // Reserved 8 + .dc.l 0 // Reserved 9 + .dc.l 0 // Reserved 10 + .dc.l 0 // Reserved 11 + .dc.l 0 // Reserved 12 + .dc.l 0 // Reserved 13 + .dc.l 0 // Reserved 14 + .dc.l 0 // Reserved 15 diff --git a/ports_module/cortex-m7/gnu/inc/tx_port.h b/ports_module/cortex-m7/gnu/inc/tx_port.h new file mode 100644 index 00000000..78c15c58 --- /dev/null +++ b/ports_module/cortex-m7/gnu/inc/tx_port.h @@ -0,0 +1,515 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-M7/GNU */ +/* 6.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX Cortex-M7 port. */ + +#define TX_INT_DISABLE 1 /* Disable interrupts */ +#define TX_INT_ENABLE 0 /* Enable interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0 + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); + +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) + +#ifdef TX_ENABLE_FPU_SUPPORT + + +#ifdef TX_MISRA_ENABLE + +ULONG _tx_misra_control_get(void); +void _tx_misra_control_set(ULONG value); +ULONG _tx_misra_fpccr_get(void); +void _tx_misra_vfp_touch(void); + +#else + +__attribute__( ( always_inline ) ) static inline ULONG __get_control(void) +{ + +ULONG control_value; + + __asm__ volatile (" MRS %0,CONTROL ": "=r" (control_value) ); + return(control_value); +} + + +__attribute__( ( always_inline ) ) static inline void __set_control(ULONG control_value) +{ + + __asm__ volatile (" MSR CONTROL,%0": : "r" (control_value): "memory" ); +} + + +#endif + + +/* A completed thread falls into _thread_shell_entry and we can simply deactivate the FPU via CONTROL.FPCA + in order to ensure no lazy stacking will occur. */ + +#ifndef TX_MISRA_ENABLE + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_control(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_control(_tx_vfp_state); \ + } +#else + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } + +#endif + + +/* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. + If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + the lazy FPU save, then restore the CONTROL.FPCA state. */ + +#ifndef TX_MISRA_ENABLE + + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_control(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_control(_tx_vfp_state); \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = *((ULONG *) 0xE000EF34); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_control(); \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + __asm__ volatile ("vmov.f32 s0, s0"); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = __get_control(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_control(_tx_vfp_state); \ + } \ + } \ + } \ + } +#else + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = _tx_misra_fpccr_get(); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + _tx_misra_vfp_touch(); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + } \ + } \ + } +#endif + +#else + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + +#endif + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define the get system state macro. */ + +#ifndef TX_THREAD_GET_SYSTEM_STATE +#ifndef TX_MISRA_ENABLE + +__attribute__( ( always_inline ) ) static inline unsigned int __get_ipsr_value(void) +{ + +unsigned int ipsr_value; + + __asm__ volatile (" MRS %0,IPSR ": "=r" (ipsr_value) ); + return(ipsr_value); +} + + +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | __get_ipsr_value()) +#else +ULONG _tx_misra_ipsr_get(VOID); +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get()) +#endif +#endif + + +/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value + indicates that _tx_thread_system_return should not be called. */ + +#ifndef TX_THREAD_SYSTEM_RETURN_CHECK +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#endif + +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to + prevent early scheduling on Cortex-M parts. */ + +#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; + + +/* This ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + +#endif + + +#ifndef TX_DISABLE_INLINE + +/* Define GNU specific macros, with in-line assembly for performance. */ + +__attribute__( ( always_inline ) ) static inline unsigned int __disable_interrupts(void) +{ + +unsigned int primask_value; + + __asm__ volatile (" MRS %0,PRIMASK ": "=r" (primask_value) ); + __asm__ volatile (" CPSID i" : : : "memory" ); + return(primask_value); +} + +__attribute__( ( always_inline ) ) static inline void __restore_interrupts(unsigned int primask_value) +{ + + __asm__ volatile (" MSR PRIMASK,%0": : "r" (primask_value): "memory" ); +} + +__attribute__( ( always_inline ) ) static inline unsigned int __get_primask_value(void) +{ + +unsigned int primask_value; + + __asm__ volatile (" MRS %0,PRIMASK ": "=r" (primask_value) ); + return(primask_value); +} + +__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void) +{ + + __asm__ volatile (" CPSIE i": : : "memory" ); +} + + +__attribute__( ( always_inline ) ) static inline void _tx_thread_system_return_inline(void) +{ +unsigned int interrupt_save; + + *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + if (__get_ipsr_value() == 0) + { + interrupt_save = __get_primask_value(); + __enable_interrupts(); + __restore_interrupts(interrupt_save); + } +} + + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = __disable_interrupts(); +#define TX_RESTORE __restore_interrupts(interrupt_save); + + +/* Redefine _tx_thread_system_return for improved performance. */ + +#define _tx_thread_system_return _tx_thread_system_return_inline + + +#else + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); +#define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); +#endif + + +/* Define FPU extension for the Cortex-M7. Each is assumed to be called in the context of the executing + thread. This is for legacy only, and not needed any longer. */ + +void tx_thread_fpu_enable(void); +void tx_thread_fpu_disable(void); + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/GNU Version 6.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + + + + + diff --git a/ports_module/cortex-m7/gnu/inc/txm_module_port.h b/ports_module/cortex-m7/gnu/inc/txm_module_port.h new file mode 100644 index 00000000..0c70ef8b --- /dev/null +++ b/ports_module/cortex-m7/gnu/inc/txm_module_port.h @@ -0,0 +1,340 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* txm_module_port.h Cortex-M7/MPU/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the basic module constants, interface structures, */ +/* and function prototypes. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TXM_MODULE_PORT_H +#define TXM_MODULE_PORT_H + +/* Determine if the optional Modules user define file should be used. */ + +#ifdef TXM_MODULE_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in txm_module_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "txm_module_user.h" +#endif + +/* It is assumed that the base ThreadX tx_port.h file has been modified to add the + following extensions to the ThreadX thread control block (this code should replace + the corresponding macro define in tx_port.h): + +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; + +The following extensions must also be defined in tx_port.h: + +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); + +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); +*/ + +/* Define the kernel stack size for a module thread. */ +#ifndef TXM_MODULE_KERNEL_STACK_SIZE +#define TXM_MODULE_KERNEL_STACK_SIZE 768 +#endif + +/* For the following 3 access control settings, change TEX and C, B, S (bits 21 through 16 of MPU_RASR) + * to reflect your system memory attributes (cache, shareable, memory type). */ +/* Code region access control: privileged read-only, outer & inner write-back, normal memory, shareable. */ +#define TXM_MODULE_MPU_CODE_ACCESS_CONTROL 0x06070000 +/* Data region access control: execute never, read/write, outer & inner write-back, normal memory, shareable. */ +#define TXM_MODULE_MPU_DATA_ACCESS_CONTROL 0x13070000 +/* Shared region access control: execute never, read-only, outer & inner write-back, normal memory, shareable. */ +#define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 + + +/* Define constants specific to the tools the module can be built with for this particular modules port. */ + +#define TXM_MODULE_IAR_COMPILER 0x00000000 +#define TXM_MODULE_RVDS_COMPILER 0x01000000 +#define TXM_MODULE_GNU_COMPILER 0x02000000 +#define TXM_MODULE_COMPILER_MASK 0xFF000000 +#define TXM_MODULE_OPTIONS_MASK 0x000000FF + + +/* Define the properties for this particular module port. */ + +#define TXM_MODULE_MEMORY_PROTECTION_ENABLED + +#ifdef TXM_MODULE_MEMORY_PROTECTION_ENABLED +#define TXM_MODULE_REQUIRE_ALLOCATED_OBJECT_MEMORY +#else +#define TXM_MODULE_REQUIRE_LOCAL_OBJECT_MEMORY +#endif + +#define TXM_MODULE_USER_MODE 0x00000001 +#define TXM_MODULE_MEMORY_PROTECTION 0x00000002 +#define TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS 0x00000004 + + +/* Define the supported options for this module. */ + +#define TXM_MODULE_MANAGER_SUPPORTED_OPTIONS (TXM_MODULE_USER_MODE | TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS) +#define TXM_MODULE_MANAGER_REQUIRED_OPTIONS 0 + + +/* Define offset adjustments according to the compiler used to build the module. */ + +#define TXM_MODULE_IAR_SHELL_ADJUST 24 +#define TXM_MODULE_IAR_START_ADJUST 28 +#define TXM_MODULE_IAR_STOP_ADJUST 32 +#define TXM_MODULE_IAR_CALLBACK_ADJUST 44 + +#define TXM_MODULE_RVDS_SHELL_ADJUST 0 +#define TXM_MODULE_RVDS_START_ADJUST 0 +#define TXM_MODULE_RVDS_STOP_ADJUST 0 +#define TXM_MODULE_RVDS_CALLBACK_ADJUST 0 + +#define TXM_MODULE_GNU_SHELL_ADJUST 24 +#define TXM_MODULE_GNU_START_ADJUST 28 +#define TXM_MODULE_GNU_STOP_ADJUST 32 +#define TXM_MODULE_GNU_CALLBACK_ADJUST 44 + + +/* Define other module port-specific constants. */ + +/* Define INLINE_DECLARE to inline for GNU compiler. */ + +#define INLINE_DECLARE inline + +/* Define the number of MPU entries assigned to the code and data sections. + On Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access + to the kernel entry function, thus 15 remain for code and data protection. */ +#define TXM_MODULE_MPU_TOTAL_ENTRIES 16 +#define TXM_MODULE_MPU_CODE_ENTRIES 4 +#define TXM_MODULE_MPU_DATA_ENTRIES 4 +#define TXM_MODULE_MPU_SHARED_ENTRIES 3 + +#define TXM_MODULE_MPU_KERNEL_ENTRY_INDEX 0 +#define TXM_MODULE_MPU_SHARED_INDEX 9 + +#define TXM_ENABLE_REGION 0x01 + +/* There are 2 registers to set up each MPU region: MPU_RBAR, MPU_RASR. */ +typedef struct TXM_MODULE_MPU_INFO_STRUCT +{ + ULONG txm_module_mpu_region_address; + ULONG txm_module_mpu_region_attribute_size; +} TXM_MODULE_MPU_INFO; +/* Shared memory region attributes. */ +#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 +#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 + +/* Define the port-extensions to the module manager instance structure. */ + +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_count; \ + ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES]; + + +/* Define the memory fault information structure that is populated when a memory fault occurs. */ + + +typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT +{ + TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr; + VOID *txm_module_manager_memory_fault_info_code_location; + ULONG txm_module_manager_memory_fault_info_shcsr; + ULONG txm_module_manager_memory_fault_info_cfsr; + ULONG txm_module_manager_memory_fault_info_mmfar; + ULONG txm_module_manager_memory_fault_info_bfar; + ULONG txm_module_manager_memory_fault_info_control; + ULONG txm_module_manager_memory_fault_info_sp; + ULONG txm_module_manager_memory_fault_info_r0; + ULONG txm_module_manager_memory_fault_info_r1; + ULONG txm_module_manager_memory_fault_info_r2; + ULONG txm_module_manager_memory_fault_info_r3; + ULONG txm_module_manager_memory_fault_info_r4; + ULONG txm_module_manager_memory_fault_info_r5; + ULONG txm_module_manager_memory_fault_info_r6; + ULONG txm_module_manager_memory_fault_info_r7; + ULONG txm_module_manager_memory_fault_info_r8; + ULONG txm_module_manager_memory_fault_info_r9; + ULONG txm_module_manager_memory_fault_info_r10; + ULONG txm_module_manager_memory_fault_info_r11; + ULONG txm_module_manager_memory_fault_info_r12; + ULONG txm_module_manager_memory_fault_info_lr; + ULONG txm_module_manager_memory_fault_info_xpsr; +} TXM_MODULE_MANAGER_MEMORY_FAULT_INFO; + + +#define TXM_MODULE_MANAGER_FAULT_INFO \ + TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info; + +/* Define the macro to check the code alignment. */ + +#define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment) \ + { \ + ULONG temp; \ + temp = (ULONG) module_location; \ + temp = temp & (code_alignment - 1); \ + if (temp) \ + { \ + _tx_mutex_put(&_txm_module_manager_mutex); \ + return(TXM_MODULE_ALIGNMENT_ERROR); \ + } \ + } + + +/* Define the macro to adjust the alignment and size for code/data areas. */ + +#define TXM_MODULE_MANAGER_ALIGNMENT_ADJUST(module_preamble, code_size, code_alignment, data_size, data_alignment) _txm_module_manager_alignment_adjust(module_preamble, &code_size, &code_alignment, &data_size, &data_alignment); + + +/* Define the macro to adjust the symbols in the module preamble. */ + +#define TXM_MODULE_MANAGER_CALCULATE_ADJUSTMENTS(properties, shell_function_adjust, start_function_adjust, stop_function_adjust, callback_function_adjust) \ + if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_IAR_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_IAR_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_IAR_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_IAR_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_IAR_CALLBACK_ADJUST; \ + } \ + else if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_RVDS_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_RVDS_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_RVDS_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_RVDS_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_RVDS_CALLBACK_ADJUST; \ + } \ + else \ + { \ + shell_function_adjust = TXM_MODULE_GNU_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_GNU_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_GNU_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_GNU_CALLBACK_ADJUST; \ + } + + +/* Define the macro to populate the thread control block with module port-specific information. + Check if the module is in user mode and set up txm_module_thread_entry_info_kernel_call_dispatcher accordingly. +*/ + +#define TXM_MODULE_MANAGER_THREAD_SETUP(thread_ptr, module_instance) \ + thread_ptr -> tx_thread_module_current_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \ + thread_ptr -> tx_thread_module_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \ + if (thread_ptr -> tx_thread_module_user_mode) \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_user_mode_entry; \ + } \ + else \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_kernel_dispatch; \ + } + + +/* Define the macro to populate the module control block with module port-specific information. + If memory protection is enabled, set up the MPU registers. +*/ +#define TXM_MODULE_MANAGER_MODULE_SETUP(module_instance) \ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE) \ + { \ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) \ + { \ + _txm_module_manager_mm_register_setup(module_instance); \ + } \ + } \ + else \ + { \ + /* Do nothing. */ \ + } + +/* Define the macro to perform port-specific functions when unloading the module. */ +/* Nothing needs to be done for this port. */ +#define TXM_MODULE_MANAGER_MODULE_UNLOAD(module_instance) + + +/* Define the macros to perform port-specific checks when passing pointers to the kernel. */ + +/* Define macro to make sure object is inside the module's data. */ +#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ + _txm_module_manager_inside_data_check(module_instance, obj_ptr, obj_size) + +/* Define some internal prototypes to this module port. */ + +#ifndef TX_SOURCE_CODE +#define txm_module_manager_memory_fault_notify _txm_module_manager_memory_fault_notify +#endif + + +#define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES \ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment); \ +VOID _txm_module_manager_memory_fault_handler(VOID); \ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)); \ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \ +ULONG _txm_power_of_two_block_size(ULONG size); \ +ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); \ +ULONG _txm_module_manager_region_size_get(ULONG block_size); \ +UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size); + +#define TXM_MODULE_MANAGER_VERSION_ID \ +CHAR _txm_module_manager_version_id[] = \ + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M7/MPU/GNU Version 6.1 *"; + +#endif diff --git a/ports_module/cortex-m7/gnu/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex-m7/gnu/module_lib/src/txm_module_thread_shell_entry.c new file mode 100644 index 00000000..c665ebc7 --- /dev/null +++ b/ports_module/cortex-m7/gnu/module_lib/src/txm_module_thread_shell_entry.c @@ -0,0 +1,174 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#ifndef TXM_MODULE +#define TXM_MODULE +#endif + +#ifndef TX_SOURCE_CODE +#define TX_SOURCE_CODE +#endif + + +/* Include necessary system files. */ + +#include "txm_module.h" +#include "tx_thread.h" + +/* Define the global module entry pointer from the start thread of the module. */ + +TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; + + +/* Define the dispatch function pointer used in the module implementation. */ + +ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3); + + +/* Define the GCC startup code that clears the uninitialized global data and sets up the + preset global variables. */ + +extern VOID _gcc_setup(TXM_MODULE_INSTANCE *); + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_thread_shell_entry Cortex-M7/MPU/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calls the specified entry function of the thread. It */ +/* also provides a place for the thread's entry function to return. */ +/* If the thread returns, this function places the thread in a */ +/* "COMPLETED" state. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to current thread */ +/* thread_info Pointer to thread entry info */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _gcc_setup GNU global init function */ +/* thread_entry Thread's entry function */ +/* tx_thread_resume Resume the module callback thread */ +/* _txm_module_thread_system_suspend Module thread suspension routine */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) +{ + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + VOID (*entry_exit_notify)(TX_THREAD *, UINT); +#endif + + + /* Determine if this is the start thread. If so, we must prepare the module for + execution. If not, simply skip the C startup code. */ + if (thread_info -> txm_module_thread_entry_info_start_thread) + { + /* Initialize the GNU C environment. */ + _gcc_setup(thread_info -> txm_module_thread_entry_info_code_base_address); + + /* Save the entry info pointer, for later use. */ + _txm_module_entry_info = thread_info; + + /* Save the kernel function dispatch address. This is used to make all resident calls from + the module. */ + _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; + + /* Ensure that we have a valid pointer. */ + while (!_txm_module_kernel_call_dispatcher) + { + /* Loop here, if an error is present getting the dispatch function pointer! + An error here typically indicates the resident portion of _tx_thread_schedule + is not supporting the trap to obtain the function pointer. */ + } + + /* Resume the module's callback thread, already created in the manager. */ + _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); + } + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has been entered! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_ENTRY); + } +#endif + + /* Call current thread's entry function. */ + (thread_info -> txm_module_thread_entry_info_entry) (thread_info -> txm_module_thread_entry_info_parameter); + + /* Suspend thread with a "completed" state. */ + + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine again. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has exited! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_EXIT); + } +#endif + + /* Call actual thread suspension routine. */ + _txm_module_thread_system_suspend(thread_ptr); + +#ifdef TX_SAFETY_CRITICAL + + /* If we ever get here, raise safety critical exception. */ + TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0); +#endif +} + diff --git a/ports_module/cortex-m7/gnu/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex-m7/gnu/module_manager/src/tx_thread_context_restore.S new file mode 100644 index 00000000..642af3d6 --- /dev/null +++ b/ports_module/cortex-m7/gnu/module_manager/src/tx_thread_context_restore.S @@ -0,0 +1,77 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ + .text + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_restore Cortex-M7/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is only needed for legacy applications and it should */ +@/* not be called in any new development on a Cortex-M. */ +@/* This function restores the interrupt context if it is processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs Interrupt Service Routines */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_restore(VOID) +@{ + .global _tx_thread_context_restore + .thumb_func +_tx_thread_context_restore: +@ +@ /* Not needed for this port - just return! */ + BX lr +@} diff --git a/ports_module/cortex-m7/gnu/module_manager/src/tx_thread_context_save.S b/ports_module/cortex-m7/gnu/module_manager/src/tx_thread_context_save.S new file mode 100644 index 00000000..3b798d47 --- /dev/null +++ b/ports_module/cortex-m7/gnu/module_manager/src/tx_thread_context_save.S @@ -0,0 +1,76 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ + .text + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_save Cortex-M7/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is only needed for legacy applications and it should */ +@/* not be called in any new development on a Cortex-M. */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_save(VOID) +@{ + .global _tx_thread_context_save + .thumb_func +_tx_thread_context_save: +@ +@ /* Not needed for this port - just return! */ + BX lr +@} diff --git a/ports_module/cortex-m7/gnu/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex-m7/gnu/module_manager/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..c4e4e7d9 --- /dev/null +++ b/ports_module/cortex-m7/gnu/module_manager/src/tx_thread_interrupt_control.S @@ -0,0 +1,80 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ + + +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ + + .text 32 + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_control Cortex-M7/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for changing the interrupt lockout */ +@/* posture of the system. */ +@/* */ +@/* INPUT */ +@/* */ +@/* new_posture New interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@/* UINT _tx_thread_interrupt_control(UINT new_posture) +{ */ + .global _tx_thread_interrupt_control + .thumb_func +_tx_thread_interrupt_control: + +@/* Pickup current interrupt lockout posture. */ + + MRS r1, PRIMASK @ Pickup current interrupt lockout + +@/* Apply the new interrupt posture. */ + + MSR PRIMASK, r0 @ Apply the new interrupt lockout + MOV r0, r1 @ Transfer old to return register + BX lr @ Return to caller + +@/* } */ diff --git a/ports_module/cortex-m7/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex-m7/gnu/module_manager/src/tx_thread_schedule.S new file mode 100644 index 00000000..be1bd05c --- /dev/null +++ b/ports_module/cortex-m7/gnu/module_manager/src/tx_thread_schedule.S @@ -0,0 +1,555 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .global _tx_thread_current_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_system_stack_ptr + .global _tx_execution_thread_enter + .global _tx_execution_thread_exit + .global _tx_thread_preempt_disable + .global _txm_module_manager_memory_fault_handler + .global _txm_module_manager_memory_fault_info + + .text + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule Cortex-M7/MPU/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* _tx_thread_context_restore Restore thread's context */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_schedule(VOID) +// { + .global _tx_thread_schedule + .thumb_func +_tx_thread_schedule: + + /* This function should only ever be called on Cortex-M + from the first schedule request. Subsequent scheduling occurs + from the PendSV handling routines below. */ + + /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ + + MOV r0, #0 // Build value for TX_FALSE + LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag + STR r0, [r2, #0] // Clear preempt disable flag + + /* Clear CONTROL.FPCA bit so FPU registers aren't unnecessarily stacked. */ + +#ifdef __ARMVFP__ + MRS r0, CONTROL // Pickup current CONTROL register + BIC r0, r0, #4 // Clear the FPCA bit + MSR CONTROL, r0 // Setup new CONTROL register +#endif + + /* Enable memory fault registers. */ + + LDR r0, =0xE000ED24 // Build SHCSR address + LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults + STR r1, [r0] // + + /* Enable interrupts */ + + CPSIE i + + /* Enter the scheduler for the first time. */ + + MOV r0, #0x10000000 // Load PENDSVSET bit + MOV r1, #0xE000E000 // Load NVIC base + STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + DSB // Complete all memory accesses + ISB // Flush pipeline + + /* Wait here for the PendSV to take place. */ + +__tx_wait_here: + B __tx_wait_here // Wait for the PendSV to happen +// } + + + /* Memory Exception Handler. */ + .global MemManage_Handler + .global BusFault_Handler + .global UsageFault_Handler + .thumb_func +MemManage_Handler: + .thumb_func +BusFault_Handler: + .thumb_func +UsageFault_Handler: + + CPSID i // Disable interrupts + + /* Now pickup and store all the fault related information. */ + + LDR r12,=_txm_module_manager_memory_fault_info // Pickup fault info struct + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r0] // Pickup the current thread pointer + STR r1, [r12, #0] // Save current thread pointer in fault info structure + LDR r0, =0xE000ED24 // Build SHCSR address + LDR r1, [r0] // Pickup SHCSR + STR r1, [r12, #8] // Save SHCSR + LDR r0, =0xE000ED28 // Build CFSR address + LDR r1, [r0] // Pickup CFSR + STR r1, [r12, #12] // Save CFSR + LDR r0, =0xE000ED34 // Build MMFAR address + LDR r1, [r0] // Pickup MMFAR + STR r1, [r12, #16] // Save MMFAR + LDR r0, =0xE000ED38 // Build BFAR address + LDR r1, [r0] // Pickup BFAR + STR r1, [r12, #20] // Save BFAR + MRS r0, CONTROL // Pickup current CONTROL register + STR r0, [r12, #24] // Save CONTROL + MRS r1, PSP // Pickup thread stack pointer + STR r1, [r12, #28] // Save thread stack pointer + LDR r0, [r1] // Pickup saved r0 + STR r0, [r12, #32] // Save r0 + LDR r0, [r1, #4] // Pickup saved r1 + STR r0, [r12, #36] // Save r1 + STR r2, [r12, #40] // Save r2 + STR r3, [r12, #44] // Save r3 + STR r4, [r12, #48] // Save r4 + STR r5, [r12, #52] // Save r5 + STR r6, [r12, #56] // Save r6 + STR r7, [r12, #60] // Save r7 + STR r8, [r12, #64] // Save r8 + STR r9, [r12, #68] // Save r9 + STR r10,[r12, #72] // Save r10 + STR r11,[r12, #76] // Save r11 + LDR r0, [r1, #16] // Pickup saved r12 + STR r0, [r12, #80] // Save r12 + LDR r0, [r1, #20] // Pickup saved lr + STR r0, [r12, #84] // Save lr + LDR r0, [r1, #24] // Pickup instruction address at point of fault + STR r0, [r12, #4] // Save point of fault + LDR r0, [r1, #28] // Pickup xPSR + STR r0, [r12, #88] // Save xPSR + + MRS r0, CONTROL // Pickup current CONTROL register + BIC r0, r0, #1 // Clear the UNPRIV bit + MSR CONTROL, r0 // Setup new CONTROL register + + LDR r0, =0xE000ED28 // Build the Memory Management Fault Status Register (MMFSR) + LDRB r1, [r0] // Pickup the MMFSR, with the following bit definitions: + // Bit 0 = 1 -> Instruction address violation + // Bit 1 = 1 -> Load/store address violation + // Bit 7 = 1 -> MMFAR is valid + STRB r1, [r0] // Clear the MMFSR + +#ifdef __ARMVFP__ + LDR r0, =0xE000EF34 // Cleanup FPU context: Load FPCCR address + LDR r1, [r0] // Load FPCCR + BIC r1, r1, #1 // Clear the lazy preservation active bit + STR r1, [r0] // Store the value +#endif + + BL _txm_module_manager_memory_fault_handler // Call memory manager fault handler + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread exit function to indicate the thread is no longer executing. */ + + CPSID i // Disable interrupts + BL _tx_execution_thread_exit // Call the thread exit function + CPSIE i // Enable interrupts +#endif + + MOV r1, #0 // Build NULL value + LDR r0, =_tx_thread_current_ptr // Pickup address of current thread pointer + STR r1, [r0] // Clear current thread pointer + + // Return from MemManage_Handler exception + LDR r0, =0xE000ED04 // Load ICSR + LDR r1, =0x10000000 // Set PENDSVSET bit + STR r1, [r0] // Store ICSR + DSB // Wait for memory access to complete + CPSIE i // Enable interrupts + MOV lr, #0xFFFFFFFD // Load exception return code + BX lr // Return from exception + + + /* Generic context PendSV handler. */ + + .global PendSV_Handler + .global __tx_PendSVHandler + .syntax unified + .thumb_func +PendSV_Handler: + .thumb_func +__tx_PendSVHandler: + + /* Get current thread value and new thread pointer. */ + +__tx_ts_handler: + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread exit function to indicate the thread is no longer executing. */ + + CPSID i // Disable interrupts + PUSH {r0, lr} // Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit // Call the thread exit function + POP {r0, lr} // Recover LR + CPSIE i // Enable interrupts +#endif + + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address + MOV r3, #0 // Build NULL value + LDR r1, [r0] // Pickup current thread pointer + + /* Determine if there is a current thread to finish preserving. */ + + CBZ r1, __tx_ts_new // If NULL, skip preservation + + /* Recover PSP and preserve current thread context. */ + + STR r3, [r0] // Set _tx_thread_current_ptr to NULL + MRS r12, PSP // Pickup PSP pointer (thread's stack pointer) + STMDB r12!, {r4-r11} // Save its remaining registers +#ifdef __ARMVFP__ + TST LR, #0x10 // Determine if the VFP extended frame is present + BNE _skip_vfp_save + VSTMDB r12!,{s16-s31} // Yes, save additional VFP registers +_skip_vfp_save: +#endif + LDR r4, =_tx_timer_time_slice // Build address of time-slice variable + STMDB r12!, {LR} // Save LR on the stack + + /* Determine if time-slice is active. If it isn't, skip time handling processing. */ + + LDR r5, [r4] // Pickup current time-slice + STR r12, [r1, #8] // Save the thread stack pointer + CBZ r5, __tx_ts_new // If not active, skip processing + + /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ + + STR r5, [r1, #24] // Save current time-slice + + /* Clear the global time-slice. */ + + STR r3, [r4] // Clear time-slice + + /* Executing thread is now completely preserved!!! */ + +__tx_ts_new: + + /* Now we are looking for a new thread to execute! */ + + CPSID i // Disable interrupts + LDR r1, [r2] // Is there another thread ready to execute? + CBZ r1, __tx_ts_wait // No, skip to the wait processing + + /* Yes, another thread is ready for else, make the current thread the new thread. */ + + STR r1, [r0] // Setup the current thread pointer to the new thread + CPSIE i // Enable interrupts + + /* Increment the thread run count. */ + +__tx_ts_restore: + LDR r7, [r1, #4] // Pickup the current thread run count + LDR r4, =_tx_timer_time_slice // Build address of time-slice variable + LDR r5, [r1, #24] // Pickup thread's current time-slice + ADD r7, r7, #1 // Increment the thread run count + STR r7, [r1, #4] // Store the new run count + + /* Setup global time-slice with thread's current time-slice. */ + + STR r5, [r4] // Setup global time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread entry function to indicate the thread is executing. */ + + PUSH {r0, r1} // Save r0 and r1 + BL _tx_execution_thread_enter // Call the thread execution enter function + POP {r0, r1} // Recover r0 and r1 +#endif + + /* Restore the thread context and PSP. */ + + LDR r12, [r1, #8] // Pickup thread's stack pointer + + MRS r5, CONTROL // Pickup current CONTROL register + LDR r4, [r1, #0x98] // Pickup current user mode flag + BIC r5, r5, #1 // Clear the UNPRIV bit + ORR r4, r4, r5 // Build new CONTROL register + MSR CONTROL, r4 // Setup new CONTROL register + + LDR r0, =0xE000ED94 // Build MPU control reg address + MOV r3, #0 // Build disable value + STR r3, [r0] // Disable MPU + LDR r0, [r1, #0x90] // Pickup the module instance pointer + CBZ r0, skip_mpu_setup // Is this thread owned by a module? No, skip MPU setup + LDR r1, [r0, #0x64] // Pickup MPU register[0] + CBZ r1, skip_mpu_setup // Is protection required for this module? No, skip MPU setup + LDR r1, =0xE000ED9C // Build address of MPU base register + + // Use alias registers to quickly load MPU + ADD r0, r0, #100 // Build address of MPU register start in thread control block + LDM r0!,{r2-r9} // Load MPU regions 0-3 + STM r1,{r2-r9} // Store MPU regions 0-3 + LDM r0!,{r2-r9} // Load MPU regions 4-7 + STM r1,{r2-r9} // Store MPU regions 4-7 + LDM r0!,{r2-r9} // Load MPU regions 8-11 + STM r1,{r2-r9} // Store MPU regions 8-11 + LDM r0!,{r2-r9} // Load MPU regions 12-15 + STM r1,{r2-r9} // Store MPU regions 12-15 + LDR r0, =0xE000ED94 // Build MPU control reg address + MOV r1, #5 // Build enable value with background region enabled + STR r1, [r0] // Enable MPU +skip_mpu_setup: + LDMIA r12!, {LR} // Pickup LR +#ifdef __ARMVFP__ + TST LR, #0x10 // Determine if the VFP extended frame is present + BNE _skip_vfp_restore // If not, skip VFP restore + VLDMIA r12!, {s16-s31} // Yes, restore additional VFP registers +_skip_vfp_restore: +#endif + LDMIA r12!, {r4-r11} // Recover thread's registers + MSR PSP, r12 // Setup the thread's stack pointer + + /* Return to thread. */ + + BX lr // Return to thread! + + /* The following is the idle wait processing... in this case, no threads are ready for execution and the + system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts + are disabled to allow use of WFI for waiting for a thread to arrive. */ + +__tx_ts_wait: + CPSID i // Disable interrupts + LDR r1, [r2] // Pickup the next thread to execute pointer + STR r1, [r0] // Store it in the current pointer + CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! +#ifdef TX_ENABLE_WFI + DSB // Ensure no outstanding memory transactions + WFI // Wait for interrupt + ISB // Ensure pipeline is flushed +#endif + CPSIE i // Enable interrupts + B __tx_ts_wait // Loop to continue waiting + + /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are + already in the handler! */ + +__tx_ts_ready: + MOV r7, #0x08000000 // Build clear PendSV value + MOV r8, #0xE000E000 // Build base NVIC address + STR r7, [r8, #0xD04] // Clear any PendSV + + /* Re-enable interrupts and restore new thread. */ + + CPSIE i // Enable interrupts + B __tx_ts_restore // Restore the thread + + + /* SVC Handler. */ + + .global SVC_Handler + .global __tx_SVCallHandler + .syntax unified + .thumb_func +SVC_Handler: + .thumb_func +__tx_SVCallHandler: + + MRS r0, PSP // Pickup the PSP stack + LDR r1, [r0, #24] // Pickup the point of interrupt + LDRB r2, [r1, #-2] // Pickup the SVC parameter + + /* Determine which SVC trap we are processing */ + + CMP r2, #1 // Is it the entry into ThreadX? + BNE _tx_thread_user_return // No, return to user mode + + /* At this point we have an SVC 1, which means we are entering + the kernel from a module thread with user mode selected. */ + + LDR r2, =_txm_module_priv // Load address of where we should have come from + CMP r1, r2 // Did we come from user_mode_entry? + IT NE // If no (not equal), then... + BXNE lr // return from where we came. + + LDR r3, [r0, #20] // This is the saved LR + LDR r1, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, [r1] // Pickup current thread pointer + MOV r1, #0 // Build clear value + STR r1, [r2, #0x98] // Clear the current user mode selection for thread + STR r3, [r2, #0xA0] // Save the original LR in thread control block + + /* If there is memory protection, use kernel stack */ + LDR r0, [r2, #0x90] // Load the module instance ptr + LDR r0, [r0, #0x0C] // Load the module property flags + TST r0, #2 // Check if memory protected + BEQ _tx_skip_kernel_stack_enter + + /* Switch to the module thread's kernel stack */ + LDR r0, [r2, #0xA8] // Load the module kernel stack end +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + LDR r1, [r2, #0xA4] // Load the module kernel stack start + LDR r3, [r2, #0xAC] // Load the module kernel stack size + STR r1, [r2, #12] // Set stack start + STR r0, [r2, #16] // Set stack end + STR r3, [r2, #20] // Set stack size +#endif + + MRS r3, PSP // Pickup thread stack pointer + STR r3, [r2, #0xB0] // Save thread stack pointer + + /* Build kernel stack by copying thread stack two registers at a time */ + ADD r3, r3, #32 // Start at bottom of hardware stack + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + + MSR PSP, r0 // Set kernel stack pointer + +_tx_skip_kernel_stack_enter: + MRS r0, CONTROL // Pickup current CONTROL register + BIC r0, r0, #1 // Clear the UNPRIV bit + MSR CONTROL, r0 // Setup new CONTROL register + BX lr // Return to thread + +_tx_thread_user_return: + LDR r2, =_txm_module_user_mode_exit // Load address of where we should have come from + CMP r1, r2 // Did we come from user_mode_exit? + IT NE // If no (not equal), then... + BXNE lr // return from where we came + + LDR r1, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, [r1] // Pickup current thread pointer + LDR r1, [r2, #0x9C] // Pick up user mode + STR r1, [r2, #0x98] // Set the current user mode selection for thread + + /* If there is memory protection, use kernel stack */ + LDR r0, [r2, #0x90] // Load the module instance ptr + LDR r0, [r0, #0x0C] // Load the module property flags + TST r0, #2 // Check if memory protected + BEQ _tx_skip_kernel_stack_exit + +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + LDR r0, [r2, #0xB4] // Load the module thread stack start + LDR r1, [r2, #0xB8] // Load the module thread stack end + LDR r3, [r2, #0xBC] // Load the module thread stack size + STR r0, [r2, #12] // Set stack start + STR r1, [r2, #16] // Set stack end + STR r3, [r2, #20] // Set stack size +#endif + LDR r0, [r2, #0xB0] // Load the module thread stack pointer + MRS r3, PSP // Pickup kernel stack pointer + + /* Copy kernel hardware stack to module thread stack. */ + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + SUB r0, r0, #32 // Subtract 32 to get back to top of stack + MSR PSP, r0 // Set thread stack pointer + + LDR r1, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, [r1] // Pickup current thread pointer + LDR r1, [r2, #0x9C] // Pick up user mode + +_tx_skip_kernel_stack_exit: + MRS r0, CONTROL // Pickup current CONTROL register + ORR r0, r0, r1 // OR in the user mode bit + MSR CONTROL, r0 // Setup new CONTROL register + BX lr // Return to thread + + + /* Kernel entry function from user mode. */ + + .global _txm_module_manager_kernel_dispatch + .align 5 + .syntax unified +// VOID _txm_module_manager_user_mode_entry(VOID) +// { + .global _txm_module_manager_user_mode_entry + .thumb_func +_txm_module_manager_user_mode_entry: + SVC 1 // Enter kernel +_txm_module_priv: + /* At this point, we are out of user mode. The original LR has been saved in the + thread control block. Simply call the kernel dispatch function. */ + BL _txm_module_manager_kernel_dispatch + + /* Pickup the original LR value while still in privileged mode */ + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r3, [r2] // Pickup current thread pointer + LDR lr, [r3, #0xA0] // Pickup saved LR from original call + + SVC 2 // Exit kernel and return to user mode +_txm_module_user_mode_exit: + BX lr // Return to the caller + NOP + NOP + NOP + NOP +// } diff --git a/ports_module/cortex-m7/gnu/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex-m7/gnu/module_manager/src/tx_thread_stack_build.S new file mode 100644 index 00000000..11f622c1 --- /dev/null +++ b/ports_module/cortex-m7/gnu/module_manager/src/tx_thread_stack_build.S @@ -0,0 +1,135 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ + .text + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_stack_build Cortex-M7/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function builds a stack frame on the supplied thread's stack. */ +@/* The stack frame results in a fake interrupt return to the supplied */ +@/* function pointer. */ +@/* */ +@/* INPUT */ +@/* */ +@/* thread_ptr Pointer to thread control blk */ +@/* function_ptr Pointer to return function */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_thread_create Create thread service */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +@{ + .global _tx_thread_stack_build + .thumb_func +_tx_thread_stack_build: +@ +@ +@ /* Build a fake interrupt frame. The form of the fake interrupt stack +@ on the Cortex-M7 should look like the following after it is built: +@ +@ Stack Top: +@ LR Interrupted LR (LR at time of PENDSV) +@ r4 Initial value for r4 +@ r5 Initial value for r5 +@ r6 Initial value for r6 +@ r7 Initial value for r7 +@ r8 Initial value for r8 +@ r9 Initial value for r9 +@ r10 Initial value for r10 +@ r11 Initial value for r11 +@ r0 Initial value for r0 (Hardware stack starts here!!) +@ r1 Initial value for r1 +@ r2 Initial value for r2 +@ r3 Initial value for r3 +@ r12 Initial value for r12 +@ lr Initial value for lr +@ pc Initial value for pc +@ xPSR Initial value for xPSR +@ +@ Stack Bottom: (higher memory address) */ +@ + LDR r2, [r0, #16] @ Pickup end of stack area + BIC r2, r2, #0x7 @ Align frame + SUB r2, r2, #68 @ Subtract frame size + LDR r3, =0xFFFFFFFD @ Build initial LR value + STR r3, [r2, #0] @ Save on the stack +@ +@ /* Actually build the stack frame. */ +@ + MOV r3, #0 @ Build initial register value + STR r3, [r2, #4] @ Store initial r4 + STR r3, [r2, #8] @ Store initial r5 + STR r3, [r2, #12] @ Store initial r6 + STR r3, [r2, #16] @ Store initial r7 + STR r3, [r2, #20] @ Store initial r8 + STR r3, [r2, #24] @ Store initial r9 + STR r3, [r2, #28] @ Store initial r10 + STR r3, [r2, #32] @ Store initial r11 +@ +@ /* Hardware stack follows. */ +@ + STR r3, [r2, #36] @ Store initial r0 + STR r3, [r2, #40] @ Store initial r1 + STR r3, [r2, #44] @ Store initial r2 + STR r3, [r2, #48] @ Store initial r3 + STR r3, [r2, #52] @ Store initial r12 + MOV r3, #0xFFFFFFFF @ Poison EXC_RETURN value + STR r3, [r2, #56] @ Store initial lr + STR r1, [r2, #60] @ Store initial pc + MOV r3, #0x01000000 @ Only T-bit need be set + STR r3, [r2, #64] @ Store initial xPSR +@ +@ /* Setup stack pointer. */ +@ thread_ptr -> tx_thread_stack_ptr = r2; +@ + STR r2, [r0, #8] @ Save stack pointer in thread's + @ control block + BX lr @ Return to caller +@} diff --git a/ports_module/cortex-m7/gnu/module_manager/src/tx_thread_system_return.S b/ports_module/cortex-m7/gnu/module_manager/src/tx_thread_system_return.S new file mode 100644 index 00000000..94f1f407 --- /dev/null +++ b/ports_module/cortex-m7/gnu/module_manager/src/tx_thread_system_return.S @@ -0,0 +1,88 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ + + + .text 32 + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_system_return Cortex-M7/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is target processor specific. It is used to transfer */ +@/* control from a thread back to the ThreadX system. Only a */ +@/* minimal context is saved since the compiler assumes temp registers */ +@/* are going to get slicked by a function call anyway. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling loop */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX components */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@/* VOID _tx_thread_system_return(VOID) +@{ */ + .thumb_func + .global _tx_thread_system_return +_tx_thread_system_return: +@ +@ /* Return to real scheduler via PendSV. Note that this routine is often +@ replaced with in-line assembly in tx_port.h to improved performance. */ +@ + MOV r0, #0x10000000 @ Load PENDSVSET bit + MOV r1, #0xE000E000 @ Load NVIC base + STR r0, [r1, #0xD04] @ Set PENDSVBIT in ICSR + MRS r0, IPSR @ Pickup IPSR + CMP r0, #0 @ Is it a thread returning? + BNE _isr_context @ If ISR, skip interrupt enable + MRS r1, PRIMASK @ Thread context returning, pickup PRIMASK + CPSIE i @ Enable interrupts + MSR PRIMASK, r1 @ Restore original interrupt posture +_isr_context: + BX lr @ Return to caller + +@/* } */ diff --git a/ports_module/cortex-m7/gnu/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex-m7/gnu/module_manager/src/tx_timer_interrupt.S new file mode 100644 index 00000000..095714a4 --- /dev/null +++ b/ports_module/cortex-m7/gnu/module_manager/src/tx_timer_interrupt.S @@ -0,0 +1,257 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Timer */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ + .global _tx_timer_time_slice + .global _tx_timer_system_clock + .global _tx_timer_current_ptr + .global _tx_timer_list_start + .global _tx_timer_list_end + .global _tx_timer_expired_time_slice + .global _tx_timer_expired + .global _tx_thread_time_slice + .global _tx_timer_expiration_process +@ +@ + .text + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_timer_interrupt Cortex-M7/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function processes the hardware timer interrupt. This */ +@/* processing includes incrementing the system clock and checking for */ +@/* time slice and/or timer expiration. If either is found, the */ +@/* interrupt context save/restore functions are called along with the */ +@/* expiration functions. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_timer_expiration_process Timer expiration processing */ +@/* _tx_thread_time_slice Time slice interrupted thread */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* interrupt vector */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_timer_interrupt(VOID) +@{ + .global _tx_timer_interrupt + .thumb_func +_tx_timer_interrupt: +@ +@ /* Upon entry to this routine, it is assumed that context save has already +@ been called, and therefore the compiler scratch registers are available +@ for use. */ +@ +@ /* Increment the system clock. */ +@ _tx_timer_system_clock++; +@ + LDR r1, =_tx_timer_system_clock @ Pickup address of system clock + LDR r0, [r1, #0] @ Pickup system clock + ADD r0, r0, #1 @ Increment system clock + STR r0, [r1, #0] @ Store new system clock +@ +@ /* Test for time-slice expiration. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice + LDR r2, [r3, #0] @ Pickup time-slice + CMP r2, #0 @ Is it non-active? + BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing +@ +@ /* Decrement the time_slice. */ +@ _tx_timer_time_slice--; +@ + SUB r2, r2, #1 @ Decrement the time-slice + STR r2, [r3, #0] @ Store new time-slice value +@ +@ /* Check for expiration. */ +@ if (__tx_timer_time_slice == 0) +@ + CMP r2, #0 @ Has it expired? + BNE __tx_timer_no_time_slice @ No, skip expiration processing +@ +@ /* Set the time-slice expired flag. */ +@ _tx_timer_expired_time_slice = TX_TRUE; +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of expired flag + MOV r0, #1 @ Build expired value + STR r0, [r3, #0] @ Set time-slice expiration flag +@ +@ } +@ +__tx_timer_no_time_slice: +@ +@ /* Test for timer expiration. */ +@ if (*_tx_timer_current_ptr) +@ { +@ + LDR r1, =_tx_timer_current_ptr @ Pickup current timer pointer address + LDR r0, [r1, #0] @ Pickup current timer + LDR r2, [r0, #0] @ Pickup timer list entry + CMP r2, #0 @ Is there anything in the list? + BEQ __tx_timer_no_timer @ No, just increment the timer +@ +@ /* Set expiration flag. */ +@ _tx_timer_expired = TX_TRUE; +@ + LDR r3, =_tx_timer_expired @ Pickup expiration flag address + MOV r2, #1 @ Build expired value + STR r2, [r3, #0] @ Set expired flag + B __tx_timer_done @ Finished timer processing +@ +@ } +@ else +@ { +__tx_timer_no_timer: +@ +@ /* No timer expired, increment the timer pointer. */ +@ _tx_timer_current_ptr++; +@ + ADD r0, r0, #4 @ Move to next timer +@ +@ /* Check for wrap-around. */ +@ if (_tx_timer_current_ptr == _tx_timer_list_end) +@ + LDR r3, =_tx_timer_list_end @ Pickup addr of timer list end + LDR r2, [r3, #0] @ Pickup list end + CMP r0, r2 @ Are we at list end? + BNE __tx_timer_skip_wrap @ No, skip wrap-around logic +@ +@ /* Wrap to beginning of list. */ +@ _tx_timer_current_ptr = _tx_timer_list_start; +@ + LDR r3, =_tx_timer_list_start @ Pickup addr of timer list start + LDR r0, [r3, #0] @ Set current pointer to list start +@ +__tx_timer_skip_wrap: +@ + STR r0, [r1, #0] @ Store new current timer pointer +@ } +@ +__tx_timer_done: +@ +@ +@ /* See if anything has expired. */ +@ if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +@ { +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of expired flag + LDR r2, [r3, #0] @ Pickup time-slice expired flag + CMP r2, #0 @ Did a time-slice expire? + BNE __tx_something_expired @ If non-zero, time-slice expired + LDR r1, =_tx_timer_expired @ Pickup addr of other expired flag + LDR r0, [r1, #0] @ Pickup timer expired flag + CMP r0, #0 @ Did a timer expire? + BEQ __tx_timer_nothing_expired @ No, nothing expired +@ +__tx_something_expired: +@ +@ + STMDB sp!, {r0, lr} @ Save the lr register on the stack + @ and save r0 just to keep 8-byte alignment +@ +@ /* Did a timer expire? */ +@ if (_tx_timer_expired) +@ { +@ + LDR r1, =_tx_timer_expired @ Pickup addr of expired flag + LDR r0, [r1, #0] @ Pickup timer expired flag + CMP r0, #0 @ Check for timer expiration + BEQ __tx_timer_dont_activate @ If not set, skip timer activation +@ +@ /* Process timer expiration. */ +@ _tx_timer_expiration_process(); +@ + BL _tx_timer_expiration_process @ Call the timer expiration handling routine +@ +@ } +__tx_timer_dont_activate: +@ +@ /* Did time slice expire? */ +@ if (_tx_timer_expired_time_slice) +@ { +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired + LDR r2, [r3, #0] @ Pickup the actual flag + CMP r2, #0 @ See if the flag is set + BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing +@ +@ /* Time slice interrupted thread. */ +@ _tx_thread_time_slice(); +@ + BL _tx_thread_time_slice @ Call time-slice processing + LDR r0, =_tx_thread_preempt_disable @ Build address of preempt disable flag + LDR r1, [r0] @ Is the preempt disable flag set? + CBNZ r1, __tx_timer_skip_time_slice @ Yes, skip the PendSV logic + LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address + LDR r1, [r0] @ Pickup the current thread pointer + LDR r2, =_tx_thread_execute_ptr @ Build execute thread pointer address + LDR r3, [r2] @ Pickup the execute thread pointer + LDR r0, =0xE000ED04 @ Build address of control register + LDR r2, =0x10000000 @ Build value for PendSV bit + CMP r1, r3 @ Are they the same? + BEQ __tx_timer_skip_time_slice @ If the same, there was no time-slice performed + STR r2, [r0] @ Not the same, issue the PendSV for preemption +__tx_timer_skip_time_slice: +@ +@ } +@ +__tx_timer_not_ts_expiration: +@ + LDMIA sp!, {r0, lr} @ Recover lr register (r0 is just there for + @ the 8-byte stack alignment +@ +@ } +@ +__tx_timer_nothing_expired: + + DSB @ Complete all memory access + BX lr @ Return to caller +@ +@} diff --git a/ports_module/cortex-m7/gnu/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex-m7/gnu/module_manager/src/txm_module_manager_alignment_adjust.c new file mode 100644 index 00000000..611ad89e --- /dev/null +++ b/ports_module/cortex-m7/gnu/module_manager/src/txm_module_manager_alignment_adjust.c @@ -0,0 +1,185 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_power_of_two_block_size Cortex-M7/MPU/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calculates a power of two size at or immediately above*/ +/* the input size and returns it to the caller. */ +/* */ +/* INPUT */ +/* */ +/* size Block size */ +/* */ +/* OUTPUT */ +/* */ +/* calculated size Rounded up to power of two */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_power_of_two_block_size(ULONG size) +{ + /* Check for 0 size. */ + if(size == 0) + return 0; + + /* Minimum MPU block size is 32. */ + if(size <= 32) + return 32; + + /* Bit twiddling trick to round to next high power of 2 + (if original size is power of 2, it will return original size. Perfect!) */ + size--; + size |= size >> 1; + size |= size >> 2; + size |= size >> 4; + size |= size >> 8; + size |= size >> 16; + size++; + + /* Return a power of 2 size at or above the input size. */ + return(size); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_alignment_adjust Cortex-M7/MPU/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function adjusts the alignment and size of the code and data */ +/* section for a given module implementation. */ +/* */ +/* INPUT */ +/* */ +/* module_preamble Pointer to module preamble */ +/* code_size Size of the code area (updated) */ +/* code_alignment Code area alignment (updated) */ +/* data_size Size of data area (updated) */ +/* data_alignment Data area alignment (updated) */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_power_of_two_block_size Calculate power of two size */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, + ULONG *code_size, + ULONG *code_alignment, + ULONG *data_size, + ULONG *data_alignment) +{ + +ULONG local_code_size; +ULONG local_code_alignment; +ULONG local_data_size; +ULONG local_data_alignment; +ULONG code_size_accum; +ULONG data_size_accum; + + /* Copy the input parameters into local variables for ease of use. */ + local_code_size = *code_size; + local_code_alignment = *code_alignment; + local_data_size = *data_size; + local_data_alignment = *data_alignment; + + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + local_code_alignment = _txm_power_of_two_block_size(local_code_size) >> 2; + code_size_accum = local_code_alignment + local_code_alignment; + code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); + code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); + local_code_size = code_size_accum; + + /* Determine data block sizes. Minimize the alignment requirement. + There are 4 MPU data entries available. The following is how the data size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to data size. + 2. 1/4 of the largest power of two that is greater than or equal to data size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + local_data_alignment = _txm_power_of_two_block_size(local_data_size) >> 2; + data_size_accum = local_data_alignment + local_data_alignment; + data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); + data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); + local_data_size = data_size_accum; + + /* Return all the information to the caller. */ + *code_size = local_code_size; + *code_alignment = local_code_alignment; + *data_size = local_data_size; + *data_alignment = local_data_alignment; +} diff --git a/ports_module/cortex-m7/gnu/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex-m7/gnu/module_manager/src/txm_module_manager_external_memory_enable.c new file mode 100644 index 00000000..e2e7698d --- /dev/null +++ b/ports_module/cortex-m7/gnu/module_manager/src/txm_module_manager_external_memory_enable.c @@ -0,0 +1,189 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_mutex.h" +#include "tx_queue.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_external_memory_enable Cortex-M7/MPU/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates an entry in the MPU table for a shared */ +/* memory space. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* start_address Start address of memory */ +/* length Length of external memory */ +/* attributes Memory attributes (r/w) */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_mutex_get Get protection mutex */ +/* _tx_mutex_put Release protection mutex */ +/* _txm_power_of_two_block_size Round length to power of two */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, + VOID *start_address, + ULONG length, + UINT attributes) +{ + +ULONG block_size; +ULONG region_size; +ULONG srd_bits; +ULONG size_register; +ULONG address; +ULONG shared_index; +ULONG attributes_check = 0; + + /* Determine if the module manager has not been initialized yet. */ + if (_txm_module_manager_ready != TX_TRUE) + { + /* Module manager has not been initialized. */ + return(TX_NOT_AVAILABLE); + } + + /* Determine if the module is valid. */ + if (module_instance == TX_NULL) + { + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Get module manager protection mutex. */ + _tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER); + + /* Determine if the module instance is valid. */ + if (module_instance -> txm_module_instance_id != TXM_MODULE_ID) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Determine if the module instance is in the loaded state. */ + if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if the module is not ready. */ + return(TX_START_ERROR); + } + + /* Determine if there are shared memory entries available. */ + if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* No more entries available. */ + return(TX_NO_MEMORY); + } + + /* Start address and length must adhere to Cortex-M7 MPU. + The address must align with the block size. */ + + block_size = _txm_power_of_two_block_size(length); + address = (ULONG) start_address; + if(address != (address & ~(block_size - 1))) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return alignment error. */ + return(TXM_MODULE_ALIGNMENT_ERROR); + } + + /* At this point, we have a valid address and block size. + Set up MPU registers. */ + + /* Pick up index into shared memory entries. */ + shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; + + /* Save address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | 0x10; + + /* Calculate the region size. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Calculate the subregion bits. */ + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); + + /* Generate SRD, size, and enable attributes. */ + size_register = srd_bits | region_size | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; + + /* Check for optional write attribute. */ + if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) + { + attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; + } + + /* Save attribute-size register. */ + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; + + /* Keep track of shared memory address and length in module instance. */ + module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; + module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; + + /* Increment counter. */ + module_instance -> txm_module_instance_shared_memory_count++; + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/ports_module/cortex-m7/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex-m7/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c new file mode 100644 index 00000000..8d09a9e5 --- /dev/null +++ b/ports_module/cortex-m7/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -0,0 +1,110 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + +/* Define a macro that can be used to allocate global variables useful to + store information about the last fault. This macro is defined in + txm_module_port.h and is usually populated in the assembly language + fault handling prior to the code calling _txm_module_manager_memory_fault_handler. */ + +TXM_MODULE_MANAGER_FAULT_INFO + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_handler Cortex-M7/MPU/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles a fault associated with a memory protected */ +/* module. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_terminate Terminate thread */ +/* */ +/* CALLED BY */ +/* */ +/* Fault handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_memory_fault_handler(VOID) +{ + +TXM_MODULE_INSTANCE *module_instance_ptr; +TX_THREAD *thread_ptr; + + /* Pickup the current thread. */ + thread_ptr = _tx_thread_current_ptr; + + /* Initialize the module instance pointer to NULL. */ + module_instance_ptr = TX_NULL; + + /* Is there a thread? */ + if (thread_ptr) + { + /* Pickup the module instance. */ + module_instance_ptr = thread_ptr -> tx_thread_module_instance_ptr; + + /* Terminate the current thread. */ + _tx_thread_terminate(_tx_thread_current_ptr); + } + + /* Determine if there is a user memory fault notification callback. */ + if (_txm_module_manager_fault_notify) + { + /* Yes, call the user's notification memory fault callback. */ + (_txm_module_manager_fault_notify)(thread_ptr, module_instance_ptr); + } +} diff --git a/ports_module/cortex-m7/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex-m7/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c new file mode 100644 index 00000000..e4fd949b --- /dev/null +++ b/ports_module/cortex-m7/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -0,0 +1,84 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the external user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_notify Cortex-M7/MPU/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application callback when/if a memory */ +/* fault occurs. The supplied thread is automatically terminated, but */ +/* any other threads in the same module may still execute. */ +/* */ +/* INPUT */ +/* */ +/* notify_function Memory fault notification */ +/* function, NULL disables. */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +{ + /* Setup notification function. */ + _txm_module_manager_fault_notify = notify_function; + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/ports_module/cortex-m7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex-m7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c new file mode 100644 index 00000000..ec85828e --- /dev/null +++ b/ports_module/cortex-m7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c @@ -0,0 +1,530 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_region_size_get Cortex-M7/MPU/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function converts the region size in bytes to the block size */ +/* for the Cortex-M7 MPU specification. */ +/* */ +/* INPUT */ +/* */ +/* block_size Size of the block in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* MPU size specification */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_module_manager_region_size_get(ULONG block_size) +{ + +ULONG return_value; + + /* Process relative to the input block size. */ + if (block_size == 32) + { + return_value = 0x04; + } + else if (block_size == 64) + { + return_value = 0x05; + } + else if (block_size == 128) + { + return_value = 0x06; + } + else if (block_size == 256) + { + return_value = 0x07; + } + else if (block_size == 512) + { + return_value = 0x08; + } + else if (block_size == 1024) + { + return_value = 0x09; + } + else if (block_size == 2048) + { + return_value = 0x0A; + } + else if (block_size == 4096) + { + return_value = 0x0B; + } + else if (block_size == 8192) + { + return_value = 0x0C; + } + else if (block_size == 16384) + { + return_value = 0x0D; + } + else if (block_size == 32768) + { + return_value = 0x0E; + } + else if (block_size == 65536) + { + return_value = 0x0F; + } + else if (block_size == 131072) + { + return_value = 0x10; + } + else if (block_size == 262144) + { + return_value = 0x11; + } + else if (block_size == 524288) + { + return_value = 0x12; + } + else if (block_size == 1048576) + { + return_value = 0x13; + } + else if (block_size == 2097152) + { + return_value = 0x14; + } + else + { + /* Max 4MB MPU pages for modules. */ + return_value = 0x15; + } + + return(return_value); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_calculate_srd_bits Cortex-M7/MPU/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calculates the SRD bits that need to be set to */ +/* protect "length" bytes in a block. */ +/* */ +/* INPUT */ +/* */ +/* block_size Size of the block in bytes */ +/* length Actual length in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* SRD bits to be OR'ed with region attribute register. */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) +{ + +ULONG srd_bits = 0; +UINT srd_bit_index; + + /* length is smaller than block_size, set SRD bits if block_size is 256 or more. */ + if((block_size >= 256) && (length < block_size)) + { + /* Divide block_size by 8 by shifting right 3. Result is size of subregion. */ + block_size = block_size >> 3; + + /* Set SRD index into attribute register. */ + srd_bit_index = 8; + + /* If subregion overlaps length, move to the next subregion. */ + while(length > block_size) + { + length = length - block_size; + srd_bit_index++; + } + /* Check for a portion of code remaining. */ + if(length) + { + srd_bit_index++; + } + + /* Set unused subregion bits. */ + while(srd_bit_index < 16) + { + srd_bits = srd_bits | (0x1 << srd_bit_index); + srd_bit_index++; + } + } + + return(srd_bits); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_mm_register_setup Cortex-M7/MPU/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets up the MPU register definitions based on the */ +/* module's memory characteristics. */ +/* MPU layout for the Cortex-M7: */ +/* Entry Description */ +/* 0 Kernel mode entry */ +/* 1 Module code region */ +/* 2 Module code region */ +/* 3 Module code region */ +/* 4 Module code region */ +/* 5 Module data region */ +/* 6 Module data region */ +/* 7 Module data region */ +/* 8 Module data region */ +/* 9 Module shared memory region */ +/* 10 Module shared memory region */ +/* 11 Module shared memory region */ +/* 12 Unused region */ +/* 13 Unused region */ +/* 14 Unused region */ +/* 15 Unused region */ +/* */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* */ +/* OUTPUT */ +/* */ +/* MPU specifications for module in module_instance */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_manager_region_size_get */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_thread_create */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) +{ + +ULONG code_address; +ULONG code_size; +ULONG data_address; +ULONG data_size; +ULONG start_stop_stack_size; +ULONG callback_stack_size; +ULONG block_size; +ULONG region_size; +ULONG srd_bits = 0; +UINT mpu_table_index; +UINT i; + + + /* Setup the first MPU region for kernel mode entry. */ + /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. + Mask address to proper range, region 0, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | 0x10; + /* Set the attributes, size (32 bytes) and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | (_txm_module_manager_region_size_get(32) << 1) | TXM_ENABLE_REGION; + /* End of kernel mode entry setup. */ + + /* Setup code protection. */ + + /* Initialize the MPU table index. */ + mpu_table_index = 1; + + /* Pickup code starting address and actual size. */ + code_address = (ULONG) module_instance -> txm_module_instance_code_start; + code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; + + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + + /* Now loop through to setup MPU protection for the code area. */ + for (i = 0; i < TXM_MODULE_MPU_CODE_ENTRIES; i++) + { + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + if (i < 2) + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + } + + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ + else if (i == 2) + { + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size) >> 1; + } + + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + else + { + /* Calculate remaining space. */ + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | 0x10; + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; + + /* Adjust the code address. */ + code_address = code_address + block_size; + + /* Increment MPU table index. */ + mpu_table_index++; + } + /* End of code protection. */ + + /* Setup data protection. */ + + /* Reset SRD bitfield. */ + srd_bits = 0; + + /* Pickup data starting address and actual size. */ + data_address = (ULONG) module_instance -> txm_module_instance_data_start; + + /* Adjust the size of the module elements to be aligned to the default alignment. We do this + so that when we partition the allocated memory, we can simply place these regions right beside + each other without having to align their pointers. Note this only works when they all have + the same alignment. */ + + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; + start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; + callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; + + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + /* Update the data size to include thread stacks. */ + data_size = data_size + start_stop_stack_size + callback_stack_size; + + /* Determine data block sizes. Minimize the alignment requirement. + There are 4 MPU data entries available. The following is how the data size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to data size. + 2. 1/4 of the largest power of two that is greater than or equal to data size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + + /* Now loop through to setup MPU protection for the data area. */ + for (i = 0; i < TXM_MODULE_MPU_DATA_ENTRIES; i++) + { + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to data size. */ + if (i < 2) + { + block_size = _txm_power_of_two_block_size(data_size) >> 2; + } + + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ + else if (i == 2) + { + /* Subtract (block_size*2) from data_size to calculate remaining space. */ + data_size = data_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(data_size) >> 1; + } + + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + else + { + /* Calculate remaining space. */ + data_size = data_size - block_size; + block_size = _txm_power_of_two_block_size(data_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + } + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | 0x10; + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; + + /* Adjust the data address. */ + data_address = data_address + block_size; + + /* Increment MPU table index. */ + mpu_table_index++; + } + + /* Setup MPU for the remaining regions. */ + while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES) + { + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10; + + /* Increment MPU table index. */ + mpu_table_index++; + } + +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_inside_data_check Cortex-M7/MPU/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks if the specified object is inside shared */ +/* memory. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* obj_ptr Pointer to the object */ +/* obj_size Size of the object */ +/* */ +/* OUTPUT */ +/* */ +/* Whether the object is inside the shared memory region. */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Module dispatch check functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) +{ + +UINT shared_memory_index; +UINT num_shared_memory_mpu_entries; +ALIGN_TYPE shared_memory_address_start; +ALIGN_TYPE shared_memory_address_end; + + /* Check if the object is inside the module data. */ + if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && + ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) + { + return(TX_TRUE); + } + + /* Check if the object is inside the shared memory. */ + num_shared_memory_mpu_entries = module_instance -> txm_module_instance_shared_memory_count; + for (shared_memory_index = 0; shared_memory_index < num_shared_memory_mpu_entries; shared_memory_index++) + { + + shared_memory_address_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address[shared_memory_index]; + shared_memory_address_end = shared_memory_address_start + module_instance -> txm_module_instance_shared_memory_length[shared_memory_index]; + + if ((obj_ptr >= (ALIGN_TYPE) shared_memory_address_start) && + ((obj_ptr + obj_size) <= (ALIGN_TYPE) shared_memory_address_end)) + { + return(TX_TRUE); + } + } + + return(TX_FALSE); +} diff --git a/ports_module/cortex-m7/gnu/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex-m7/gnu/module_manager/src/txm_module_manager_thread_stack_build.s new file mode 100644 index 00000000..a0bcf40b --- /dev/null +++ b/ports_module/cortex-m7/gnu/module_manager/src/txm_module_manager_thread_stack_build.s @@ -0,0 +1,139 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .align 4 + .syntax unified + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_thread_stack_build Cortex-M7/MPU/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread */ +/* function_ptr Pointer to shell function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +// { + .global _txm_module_manager_thread_stack_build + .thumb_func +_txm_module_manager_thread_stack_build: + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-M should look like the following after it is built: + + Stack Top: + LR Interrupted LR (LR at time of PENDSV) + r4 Initial value for r4 + r5 Initial value for r5 + r6 Initial value for r6 + r7 Initial value for r7 + r8 Initial value for r8 + r9 Initial value for r9 + r10 Initial value for r10 + r11 Initial value for r11 + r0 Initial value for r0 (Hardware stack starts here!!) + r1 Initial value for r1 + r2 Initial value for r2 + r3 Initial value for r3 + r12 Initial value for r12 + lr Initial value for lr + pc Initial value for pc + xPSR Initial value for xPSR + + Stack Bottom: (higher memory address) */ + + LDR r2, [r0, #16] // Pickup end of stack area + BIC r2, r2, #0x7 // Align frame + SUB r2, r2, #68 // Subtract frame size + LDR r3, =0xFFFFFFFD // Build initial LR value + STR r3, [r2, #0] // Save on the stack + + /* Actually build the stack frame. */ + + MOV r3, #0 // Build initial register value + STR r3, [r2, #4] // Store initial r4 + STR r3, [r2, #8] // Store initial r5 + STR r3, [r2, #12] // Store initial r6 + STR r3, [r2, #16] // Store initial r7 + STR r3, [r2, #20] // Store initial r8 + STR r3, [r2, #28] // Store initial r10 + STR r3, [r2, #32] // Store initial r11 + + /* Hardware stack follows. */ + + STR r0, [r2, #36] // Store initial r0, which is the thread control block + + LDR r3, [r0, #8] // Pickup thread entry info pointer,which is in the stack pointer position of the thread control block. + // It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this + // function with the actual, initial stack pointer. + STR r3, [r2, #40] // Store initial r1, which is the module entry information. + LDR r3, [r3, #8] // Pickup data base register from the module information + STR r3, [r2, #24] // Store initial r9 (data base register) + MOV r3, #0 // Clear r3 again + + STR r3, [r2, #44] // Store initial r2 + STR r3, [r2, #48] // Store initial r3 + STR r3, [r2, #52] // Store initial r12 + MOV r3, #0xFFFFFFFF // Poison EXC_RETURN value + STR r3, [r2, #56] // Store initial lr + STR r1, [r2, #60] // Store initial pc + MOV r3, #0x01000000 // Only T-bit need be set + STR r3, [r2, #64] // Store initial xPSR + + /* Setup stack pointer. */ + // thread_ptr -> tx_thread_stack_ptr = r2; + + STR r2, [r0, #8] // Save stack pointer in thread's control block + BX lr // Return to caller diff --git a/ports_module/cortex-m7/iar/example_build/sample_threadx.ewp b/ports_module/cortex-m7/iar/example_build/sample_threadx.ewp index 7cadda54..66516133 100644 --- a/ports_module/cortex-m7/iar/example_build/sample_threadx.ewp +++ b/ports_module/cortex-m7/iar/example_build/sample_threadx.ewp @@ -349,11 +349,8 @@ @@ -1176,7 +1176,7 @@ @@ -2165,13 +2165,13 @@ $PROJ_DIR$\..\..\..\..\common\inc\tx_user_sample.h - $PROJ_DIR$\..\..\..\..\common_modules\txm_module.h + $PROJ_DIR$\..\..\..\..\common_modules\inc\txm_module.h - $PROJ_DIR$\..\module_common\inc\txm_module_port.h + $PROJ_DIR$\..\inc\txm_module_port.h - $PROJ_DIR$\..\..\..\..\common_modules\module_common\inc\txm_module_user.h + $PROJ_DIR$\..\..\..\..\common_modules\inc\txm_module_user.h diff --git a/ports_module/cortex-m7/iar/example_build/txm_module_preamble.s b/ports_module/cortex-m7/iar/example_build/txm_module_preamble.s index 44819d7f..5488df2a 100644 --- a/ports_module/cortex-m7/iar/example_build/txm_module_preamble.s +++ b/ports_module/cortex-m7/iar/example_build/txm_module_preamble.s @@ -1,7 +1,7 @@ SECTION .text:CODE - AAPCS INTERWORK, ROPI, RWPI_COMPATIBLE, VFP_COMPATIBLE - PRESERVE8 + AAPCS INTERWORK, ROPI, RWPI_COMPATIBLE, VFP_COMPATIBLE + PRESERVE8 /* Define public symbols. */ @@ -15,56 +15,55 @@ /* Define common external refrences. */ - EXTERN _txm_module_thread_shell_entry - EXTERN _txm_module_callback_request_thread_entry - EXTERN ROPI$$Length - EXTERN RWPI$$Length + EXTERN _txm_module_thread_shell_entry + EXTERN _txm_module_callback_request_thread_entry + EXTERN ROPI$$Length + EXTERN RWPI$$Length - DATA + DATA __txm_module_preamble: - DC32 0x4D4F4455 ; Module ID - DC32 0x5 ; Module Major Version - DC32 0x6 ; Module Minor Version - DC32 32 ; Module Preamble Size in 32-bit words - DC32 0x12345678 ; Module ID (application defined) - DC32 0x00000007 ; Module Properties where: - ; Bits 31-24: Compiler ID - ; 0 -> IAR - ; 1 -> RVDS - ; 2 -> GNU - ; Bit 0: 0 -> Privileged mode execution - ; 1 -> User mode execution - ; Bit 1: 0 -> No MPU protection - ; 1 -> MPU protection (must have user mode selected) - ; Bit 2: 0 -> Disable shared/external memory access - ; 1 -> Enable shared/external memory access - DC32 _txm_module_thread_shell_entry - . - 0 ; Module Shell Entry Point - DC32 demo_module_start - . - 0 ; Module Start Thread Entry Point - DC32 0 ; Module Stop Thread Entry Point - DC32 1 ; Module Start/Stop Thread Priority - DC32 1024 ; Module Start/Stop Thread Stack Size - DC32 _txm_module_callback_request_thread_entry - . - 0 ; Module Callback Thread Entry - DC32 1 ; Module Callback Thread Priority - DC32 1024 ; Module Callback Thread Stack Size - DC32 ROPI$$Length ; Module Code Size - DC32 RWPI$$Length ; Module Data Size - DC32 0 ; Reserved 0 - DC32 0 ; Reserved 1 - DC32 0 ; Reserved 2 - DC32 0 ; Reserved 3 - DC32 0 ; Reserved 4 - DC32 0 ; Reserved 5 - DC32 0 ; Reserved 6 - DC32 0 ; Reserved 7 - DC32 0 ; Reserved 8 - DC32 0 ; Reserved 9 - DC32 0 ; Reserved 10 - DC32 0 ; Reserved 11 - DC32 0 ; Reserved 12 - DC32 0 ; Reserved 13 - DC32 0 ; Reserved 14 - DC32 0 ; Reserved 15 - - END - + DC32 0x4D4F4455 ; Module ID + DC32 0x6 ; Module Major Version + DC32 0x1 ; Module Minor Version + DC32 32 ; Module Preamble Size in 32-bit words + DC32 0x12345678 ; Module ID (application defined) + DC32 0x00000007 ; Module Properties where: + ; Bits 31-24: Compiler ID + ; 0 -> IAR + ; 1 -> RVDS + ; 2 -> GNU + ; Bits 23-3: Reserved + ; Bit 2: 0 -> Disable shared/external memory access + ; 1 -> Enable shared/external memory access + ; Bit 1: 0 -> No MPU protection + ; 1 -> MPU protection (must have user mode selected - bit 0 set) + ; Bit 0: 0 -> Privileged mode execution + ; 1 -> User mode execution + DC32 _txm_module_thread_shell_entry - . - 0 ; Module Shell Entry Point + DC32 demo_module_start - . - 0 ; Module Start Thread Entry Point + DC32 0 ; Module Stop Thread Entry Point + DC32 1 ; Module Start/Stop Thread Priority + DC32 1024 ; Module Start/Stop Thread Stack Size + DC32 _txm_module_callback_request_thread_entry - . - 0 ; Module Callback Thread Entry + DC32 1 ; Module Callback Thread Priority + DC32 1024 ; Module Callback Thread Stack Size + DC32 ROPI$$Length ; Module Code Size + DC32 RWPI$$Length ; Module Data Size + DC32 0 ; Reserved 0 + DC32 0 ; Reserved 1 + DC32 0 ; Reserved 2 + DC32 0 ; Reserved 3 + DC32 0 ; Reserved 4 + DC32 0 ; Reserved 5 + DC32 0 ; Reserved 6 + DC32 0 ; Reserved 7 + DC32 0 ; Reserved 8 + DC32 0 ; Reserved 9 + DC32 0 ; Reserved 10 + DC32 0 ; Reserved 11 + DC32 0 ; Reserved 12 + DC32 0 ; Reserved 13 + DC32 0 ; Reserved 14 + DC32 0 ; Reserved 15 + END diff --git a/ports_module/cortex-m7/iar/inc/tx_port.h b/ports_module/cortex-m7/iar/inc/tx_port.h index 745fb5fe..c0f84f96 100644 --- a/ports_module/cortex-m7/iar/inc/tx_port.h +++ b/ports_module/cortex-m7/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M7/IAR */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -512,7 +512,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/IAR Version 6.0.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/IAR Version 6.1 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex-m7/iar/inc/txm_module_port.h b/ports_module/cortex-m7/iar/inc/txm_module_port.h index 2e101a44..3ec363e1 100644 --- a/ports_module/cortex-m7/iar/inc/txm_module_port.h +++ b/ports_module/cortex-m7/iar/inc/txm_module_port.h @@ -10,44 +10,55 @@ /**************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ -/**************************************************************************/ -/* */ -/* APPLICATION INTERFACE DEFINITION RELEASE */ -/* */ -/* txm_module_port.h Cortex-M7/MPU/IAR */ -/* 6.0.1 */ +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* txm_module_port.h Cortex-M7/MPU/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This file defines the basic module constants, interface structures, */ -/* and function prototypes. */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the basic module constants, interface structures, */ +/* and function prototypes. */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ #ifndef TXM_MODULE_PORT_H #define TXM_MODULE_PORT_H -/* It is assumed that the base ThreadX tx_port.h file has been modified to add the +/* Determine if the optional Modules user define file should be used. */ + +#ifdef TXM_MODULE_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in txm_module_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "txm_module_user.h" +#endif + +/* It is assumed that the base ThreadX tx_port.h file has been modified to add the following extensions to the ThreadX thread control block (this code should replace the corresponding macro define in tx_port.h): @@ -81,12 +92,6 @@ The following extensions must also be defined in tx_port.h: VOID (*tx_timer_module_expiration_function)(ULONG id); */ -#define TXM_MODULE_THREAD_ENTRY_INFO_USER_EXTENSION - -/**************************************************************************/ -/* User-adjustable constants */ -/**************************************************************************/ - /* Define the kernel stack size for a module thread. */ #ifndef TXM_MODULE_KERNEL_STACK_SIZE #define TXM_MODULE_KERNEL_STACK_SIZE 512 @@ -101,11 +106,6 @@ The following extensions must also be defined in tx_port.h: /* Shared region access control: execute never, read-only, outer & inner write-back, normal memory, shareable. */ #define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 -/**************************************************************************/ -/* End of user-adjustable constants */ -/**************************************************************************/ - - /* Define constants specific to the tools the module can be built with for this particular modules port. */ @@ -162,7 +162,7 @@ The following extensions must also be defined in tx_port.h: #define INLINE_DECLARE inline /* Define the number of MPU entries assigned to the code and data sections. - On Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access + On Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access to the kernel entry function, thus 15 remain for code and data protection. */ #define TXM_MODULE_MPU_TOTAL_ENTRIES 16 #define TXM_MODULE_MPU_CODE_ENTRIES 4 @@ -201,8 +201,9 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr; VOID *txm_module_manager_memory_fault_info_code_location; ULONG txm_module_manager_memory_fault_info_shcsr; - ULONG txm_module_manager_memory_fault_info_mmfsr; + ULONG txm_module_manager_memory_fault_info_cfsr; ULONG txm_module_manager_memory_fault_info_mmfar; + ULONG txm_module_manager_memory_fault_info_bfar; ULONG txm_module_manager_memory_fault_info_control; ULONG txm_module_manager_memory_fault_info_sp; ULONG txm_module_manager_memory_fault_info_r0; @@ -226,18 +227,6 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT #define TXM_MODULE_MANAGER_FAULT_INFO \ TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info; -/* Define the macro to check the stack available in dispatch. */ -#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE \ - ULONG stack_available; \ - __asm("MOV %0, SP" : "=r"(stack_available)); \ - stack_available -= (ULONG)_tx_thread_current_ptr->tx_thread_stack_start; \ - if((stack_available < TXM_MODULE_MINIMUM_STACK_AVAILABLE) || \ - (stack_available > _tx_thread_current_ptr->tx_thread_stack_size)) \ - { \ - return(TX_SIZE_ERROR); \ - } - - /* Define the macro to check the code alignment. */ #define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment) \ @@ -321,15 +310,12 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT /* Nothing needs to be done for this port. */ #define TXM_MODULE_MANAGER_MODULE_UNLOAD(module_instance) -/* Define the macro to perform port-specific functions when passing function pointer to kernel. */ -/* Determine if the pointer is within the module's code memory. */ -#define TXM_MODULE_MANAGER_CHECK_FUNCTION_POINTER(module_instance, pointer) \ - if (((pointer < sizeof(TXM_MODULE_PREAMBLE) + (ULONG) module_instance -> txm_module_instance_code_start) || \ - ((pointer+sizeof(pointer)) > (ULONG) module_instance -> txm_module_instance_code_end)) \ - && (pointer != (ULONG) TX_NULL)) \ - { \ - return(TX_PTR_ERROR); \ - } + +/* Define the macros to perform port-specific checks when passing pointers to the kernel. */ + +/* Define macro to make sure object is inside the module's data. */ +#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ + _txm_module_manager_inside_data_check(module_instance, obj_ptr, obj_size) /* Define some internal prototypes to this module port. */ @@ -340,20 +326,16 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT #define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES \ VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment); \ -ULONG _txm_module_manager_data_pointer_check(TXM_MODULE_INSTANCE *module_instance, ULONG pointer); \ VOID _txm_module_manager_memory_fault_handler(VOID); \ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)); \ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \ ULONG _txm_power_of_two_block_size(ULONG size); \ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); \ ULONG _txm_module_manager_region_size_get(ULONG block_size); \ -UCHAR _txm_module_manager_shared_memory_check_outside(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size); \ -UCHAR _txm_module_manager_shared_memory_check_inside(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size); \ -UCHAR _txm_module_manager_shared_memory_check_inside_byte(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr); +UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size); #define TXM_MODULE_MANAGER_VERSION_ID \ CHAR _txm_module_manager_version_id[] = \ - "Copyright (c) 1996-2018 Express Logic Inc. * ThreadX Module Cortex-M7/MPU/IAR Version G5.8.2 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M7/MPU/IAR Version 6.1 *"; #endif - diff --git a/ports_module/cortex-m7/iar/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex-m7/iar/module_lib/src/txm_module_thread_shell_entry.c index 0e10bf64..25fe42c2 100644 --- a/ports_module/cortex-m7/iar/module_lib/src/txm_module_thread_shell_entry.c +++ b/ports_module/cortex-m7/iar/module_lib/src/txm_module_thread_shell_entry.c @@ -10,15 +10,15 @@ /**************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #ifndef TXM_MODULE #define TXM_MODULE @@ -44,54 +44,54 @@ TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3); -/* Define the IAR startup code that clears the uninitialized global data and sets up the +/* Define the IAR startup code that clears the uninitialized global data and sets up the preset global variables. */ extern VOID __iar_data_init3(VOID); -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_thread_shell_entry Cortex-M7/MPU/IAR */ -/* 6.0.1 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_thread_shell_entry Cortex-M7/MPU/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function calls the specified entry function of the thread. It */ -/* also provides a place for the thread's entry function to return. */ -/* If the thread returns, this function places the thread in a */ -/* "COMPLETED" state. */ -/* */ -/* INPUT */ -/* */ -/* thread_ptr Pointer to current thread */ -/* thread_info Pointer to thread entry info */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* __iar_data_init3 IAR global initialization function*/ -/* thread_entry Thread's entry function */ -/* tx_thread_resume Resume the module callback thread */ -/* _txm_module_thread_system_suspend Module thread suspension routine */ -/* */ -/* CALLED BY */ -/* */ -/* Initial thread stack frame */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function calls the specified entry function of the thread. It */ +/* also provides a place for the thread's entry function to return. */ +/* If the thread returns, this function places the thread in a */ +/* "COMPLETED" state. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to current thread */ +/* thread_info Pointer to thread entry info */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __iar_data_init3 IAR global initialization function*/ +/* thread_entry Thread's entry function */ +/* tx_thread_resume Resume the module callback thread */ +/* _txm_module_thread_system_suspend Module thread suspension routine */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) @@ -102,25 +102,23 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN #endif - /* Determine if this is the start thread. If so, we must prepare the module for + /* Determine if this is the start thread. If so, we must prepare the module for execution. If not, simply skip the C startup code. */ if (thread_info -> txm_module_thread_entry_info_start_thread) { - /* Initialize the IAR C environment. */ __iar_data_init3(); - + /* Save the entry info pointer, for later use. */ _txm_module_entry_info = thread_info; - - /* Save the kernel function dispatch address. This is used to make all resident calls from + + /* Save the kernel function dispatch address. This is used to make all resident calls from the module. */ _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; - + /* Ensure that we have a valid pointer. */ while (!_txm_module_kernel_call_dispatcher) { - /* Loop here, if an error is present getting the dispatch function pointer! An error here typically indicates the resident portion of _tx_thread_schedule is not supporting the trap to obtain the function pointer. */ @@ -165,7 +163,7 @@ VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_EN #endif /* Call actual thread suspension routine. */ - _txm_module_thread_system_suspend(thread_ptr); + _txm_module_thread_system_suspend(thread_ptr); #ifdef TX_SAFETY_CRITICAL diff --git a/ports_module/cortex-m7/iar/module_manager/src/tx_misra.s b/ports_module/cortex-m7/iar/module_manager/src/tx_misra.s index 8a13551e..53c60fbc 100644 --- a/ports_module/cortex-m7/iar/module_manager/src/tx_misra.s +++ b/ports_module/cortex-m7/iar/module_manager/src/tx_misra.s @@ -107,7 +107,7 @@ SECTION `.data`:DATA:REORDER:NOROOT(2) DATA -// 51 CHAR _tx_version_id[100] = "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX 6.0.1 MISRA C Compliant *"; +// 51 CHAR _tx_version_id[100] = "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX 6.1 MISRA C Compliant *"; _tx_version_id: DC8 43H, 6FH, 70H, 79H, 72H, 69H, 67H, 68H DC8 74H, 20H, 28H, 63H, 29H, 20H, 31H, 39H diff --git a/ports_module/cortex-m7/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex-m7/iar/module_manager/src/tx_thread_context_restore.s index f671f2d4..e269a807 100644 --- a/ports_module/cortex-m7/iar/module_manager/src/tx_thread_context_restore.s +++ b/ports_module/cortex-m7/iar/module_manager/src/tx_thread_context_restore.s @@ -21,40 +21,32 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_schedule + EXTERN _tx_thread_preempt_disable + EXTERN _tx_execution_isr_exit ; ; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; - EXTERN _tx_thread_system_state - EXTERN _tx_thread_current_ptr - EXTERN _tx_thread_system_stack_ptr - EXTERN _tx_thread_execute_ptr - EXTERN _tx_timer_time_slice - EXTERN _tx_thread_schedule - EXTERN _tx_thread_preempt_disable - EXTERN _tx_execution_isr_exit -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore Cortex-M7/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ ;/* This function restores the interrupt context if it is processing a */ ;/* nested interrupt. If not, it returns to the interrupt thread if no */ ;/* preemption is necessary. Otherwise, if preemption is necessary or */ @@ -80,7 +72,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) @@ -101,5 +93,4 @@ _tx_thread_context_restore: BX lr ; ;} - END - + END diff --git a/ports_module/cortex-m7/iar/module_manager/src/tx_thread_context_save.s b/ports_module/cortex-m7/iar/module_manager/src/tx_thread_context_save.s index 1febcc18..75a20061 100644 --- a/ports_module/cortex-m7/iar/module_manager/src/tx_thread_context_save.s +++ b/ports_module/cortex-m7/iar/module_manager/src/tx_thread_context_save.s @@ -21,35 +21,27 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN _tx_execution_isr_enter ; ; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; - EXTERN _tx_thread_system_state - EXTERN _tx_thread_current_ptr - EXTERN _tx_execution_isr_enter -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save Cortex-M7/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ ;/* */ +;/* This function is only needed for legacy applications and it should */ +;/* not be called in any new development on a Cortex-M. */ ;/* This function saves the context of an executing thread in the */ ;/* beginning of interrupt processing. The function also ensures that */ ;/* the system stack is used upon return to the calling ISR. */ @@ -74,7 +66,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) @@ -84,7 +76,7 @@ _tx_thread_context_save: #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY ; ; /* Call the ISR enter function to indicate an ISR is starting. */ -; +; PUSH {r0, lr} ; Save return address BL _tx_execution_isr_enter ; Call the ISR enter function POP {r0, lr} ; Recover return address diff --git a/ports_module/cortex-m7/iar/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex-m7/iar/module_manager/src/tx_thread_interrupt_control.s index 2e95e0f7..b8f727e3 100644 --- a/ports_module/cortex-m7/iar/module_manager/src/tx_thread_interrupt_control.s +++ b/ports_module/cortex-m7/iar/module_manager/src/tx_thread_interrupt_control.s @@ -20,23 +20,15 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE ; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control Cortex-M7/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -66,7 +58,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) @@ -82,5 +74,4 @@ _tx_thread_interrupt_control: BX lr ; ;} - END - + END diff --git a/ports_module/cortex-m7/iar/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex-m7/iar/module_manager/src/tx_thread_interrupt_disable.s index e435b0b8..bea68745 100644 --- a/ports_module/cortex-m7/iar/module_manager/src/tx_thread_interrupt_disable.s +++ b/ports_module/cortex-m7/iar/module_manager/src/tx_thread_interrupt_disable.s @@ -20,23 +20,15 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE ; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-M7/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -66,7 +58,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(UINT new_posture) diff --git a/ports_module/cortex-m7/iar/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex-m7/iar/module_manager/src/tx_thread_interrupt_restore.s index cfdb140d..64ffcce0 100644 --- a/ports_module/cortex-m7/iar/module_manager/src/tx_thread_interrupt_restore.s +++ b/ports_module/cortex-m7/iar/module_manager/src/tx_thread_interrupt_restore.s @@ -20,23 +20,15 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE ; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore Cortex-M7/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -66,7 +58,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_interrupt_restore(UINT new_posture) diff --git a/ports_module/cortex-m7/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex-m7/iar/module_manager/src/tx_thread_schedule.s index 9f06add8..5e11d863 100644 --- a/ports_module/cortex-m7/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex-m7/iar/module_manager/src/tx_thread_schedule.s @@ -10,78 +10,69 @@ ;/**************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Thread */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_execution_thread_enter + EXTERN _tx_execution_thread_exit + EXTERN _tx_thread_preempt_disable + EXTERN _txm_module_manager_memory_fault_handler + EXTERN _txm_module_manager_memory_fault_info ; ; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; - EXTERN _tx_thread_current_ptr - EXTERN _tx_thread_execute_ptr - EXTERN _tx_timer_time_slice - EXTERN _tx_thread_system_stack_ptr - EXTERN _tx_execution_thread_enter - EXTERN _tx_execution_thread_exit - EXTERN _tx_thread_preempt_disable - EXTERN _txm_module_manager_memory_fault_handler - EXTERN _txm_module_manager_memory_fault_info -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _tx_thread_schedule Cortex-M7/MPU/IAR */ -;/* 6.0.1 */ + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-M7/MPU/IAR */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ ;/* None */ -;/* */ -;/* CALLS */ -;/* */ +;/* */ +;/* OUTPUT */ +;/* */ ;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -94,7 +85,7 @@ _tx_thread_schedule: ; from the PendSV handling routines below. */ ; ; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ -; +; MOV r0, #0 ; Build value for TX_FALSE LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag STR r0, [r2, #0] ; Clear preempt disable flag @@ -103,7 +94,7 @@ _tx_thread_schedule: ; #ifdef __ARMVFP__ MRS r0, CONTROL ; Pickup current CONTROL register - BIC r0, r0, #4 ; Clear the FPCA bit + BIC r0, r0, #4 ; Clear the FPCA bit MSR CONTROL, r0 ; Setup new CONTROL register #endif ; @@ -111,28 +102,24 @@ _tx_thread_schedule: ; LDR r0, =0xE000ED24 ; Build SHCSR address LDR r1, =0x70000 ; Enable Usage, Bus, and MemManage faults - STR r1, [r0] ; + STR r1, [r0] ; ; ; /* Enable interrupts */ ; CPSIE i -; +; ; /* Enter the scheduler for the first time. */ ; MOV r0, #0x10000000 ; Load PENDSVSET bit MOV r1, #0xE000E000 ; Load NVIC base STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR - NOP ; - NOP ; - NOP ; - NOP ; -__wait_loop: - B __wait_loop -; -; /* We should never get here - ever! */ -; - BKPT 0xEF ; Setup error conditions - BX lr ; + DSB ; Complete all memory accesses + ISB ; Flush pipeline + +; /* Wait here for the PendSV to take place. */ + +__tx_wait_here: + B __tx_wait_here ; Wait for the PendSV to happen ;} ; @@ -140,7 +127,11 @@ __wait_loop: ; /* Memory Exception Handler. */ ; PUBLIC MemManage_Handler + PUBLIC BusFault_Handler + PUBLIC UsageFault_Handler MemManage_Handler: +BusFault_Handler: +UsageFault_Handler: ;{ CPSID i ; Disable interrupts ; @@ -153,41 +144,44 @@ MemManage_Handler: LDR r0, =0xE000ED24 ; Build SHCSR address LDR r1, [r0] ; Pickup SHCSR STR r1, [r12, #8] ; Save SHCSR - LDR r0, =0xE000ED28 ; Build MMFSR address - LDR r1, [r0] ; Pickup MMFSR (and other fault status too!) - STR r1, [r12, #12] ; Save MMFSR + LDR r0, =0xE000ED28 ; Build CFSR address + LDR r1, [r0] ; Pickup CFSR + STR r1, [r12, #12] ; Save CFSR LDR r0, =0xE000ED34 ; Build MMFAR address LDR r1, [r0] ; Pickup MMFAR STR r1, [r12, #16] ; Save MMFAR + LDR r0, =0xE000ED38 ; Build BFAR address + LDR r1, [r0] ; Pickup BFAR + STR r1, [r12, #20] ; Save BFAR MRS r0, CONTROL ; Pickup current CONTROL register - STR r0, [r12, #20] ; Save CONTROL + STR r0, [r12, #24] ; Save CONTROL MRS r1, PSP ; Pickup thread stack pointer - STR r1, [r12, #24] ; Save thread stack pointer + STR r1, [r12, #28] ; Save thread stack pointer LDR r0, [r1] ; Pickup saved r0 - STR r0, [r12, #28] ; Save r0 + STR r0, [r12, #32] ; Save r0 LDR r0, [r1, #4] ; Pickup saved r1 - STR r0, [r12, #32] ; Save r1 - STR r2, [r12, #36] ; Save r2 - STR r3, [r12, #40] ; Save r3 - STR r4, [r12, #44] ; Save r4 - STR r5, [r12, #48] ; Save r5 - STR r6, [r12, #52] ; Save r6 - STR r7, [r12, #56] ; Save r7 - STR r8, [r12, #60] ; Save r8 - STR r9, [r12, #64] ; Save r9 - STR r10,[r12, #68] ; Save r10 - STR r11,[r12, #72] ; Save r11 + STR r0, [r12, #36] ; Save r1 + STR r2, [r12, #40] ; Save r2 + STR r3, [r12, #44] ; Save r3 + STR r4, [r12, #48] ; Save r4 + STR r5, [r12, #52] ; Save r5 + STR r6, [r12, #56] ; Save r6 + STR r7, [r12, #60] ; Save r7 + STR r8, [r12, #64] ; Save r8 + STR r9, [r12, #68] ; Save r9 + STR r10,[r12, #72] ; Save r10 + STR r11,[r12, #76] ; Save r11 LDR r0, [r1, #16] ; Pickup saved r12 - STR r0, [r12, #76] ; Save r12 + STR r0, [r12, #80] ; Save r12 LDR r0, [r1, #20] ; Pickup saved lr - STR r0, [r12, #80] ; Save lr + STR r0, [r12, #84] ; Save lr LDR r0, [r1, #24] ; Pickup instruction address at point of fault STR r0, [r12, #4] ; Save point of fault LDR r0, [r1, #28] ; Pickup xPSR - STR r0, [r12, #84] ; Save xPSR + STR r0, [r12, #88] ; Save xPSR MRS r0, CONTROL ; Pickup current CONTROL register - BIC r0, r0, #1 ; Clear the UNPRIV bit + BIC r0, r0, #1 ; Clear the UNPRIV bit MSR CONTROL, r0 ; Setup new CONTROL register LDR r0, =0xE000ED28 ; Build the Memory Management Fault Status Register (MMFSR) @@ -231,15 +225,15 @@ MemManage_Handler: ; ; /* Generic context PendSV handler. */ -; +; PUBLIC PendSV_Handler PUBLIC __tx_PendSVHandler PendSV_Handler: __tx_PendSVHandler: ; ; /* Get current thread value and new thread pointer. */ -; -__tx_ts_handler: +; +__tx_ts_handler: #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY ; @@ -257,7 +251,7 @@ __tx_ts_handler: LDR r1, [r0] ; Pickup current thread pointer ; ; /* Determine if there is a current thread to finish preserving. */ -; +; CBZ r1, __tx_ts_new ; If NULL, skip preservation ; ; /* Recover PSP and preserve current thread context. */ @@ -332,7 +326,7 @@ __tx_ts_restore: MRS r5, CONTROL ; Pickup current CONTROL register LDR r4, [r1, #0x98] ; Pickup current user mode flag - BIC r5, r5, #1 ; Clear the UNPRIV bit + BIC r5, r5, #1 ; Clear the UNPRIV bit ORR r4, r4, r5 ; Build new CONTROL register MSR CONTROL, r4 ; Setup new CONTROL register @@ -341,7 +335,7 @@ __tx_ts_restore: STR r3, [r0] ; Disable MPU LDR r0, [r1, #0x90] ; Pickup the module instance pointer CBZ r0, skip_mpu_setup ; Is this thread owned by a module? No, skip MPU setup - LDR r1, [r0, #0x64] ; Pickup MPU register[0] + LDR r1, [r0, #0x64] ; Pickup MPU register[0] CBZ r1, skip_mpu_setup ; Is protection required for this module? No, skip MPU setup LDR r1, =0xE000ED9C ; Build address of MPU base register @@ -362,7 +356,7 @@ skip_mpu_setup: LDMIA r12!, {LR} ; Pickup LR #ifdef __ARMVFP__ TST LR, #0x10 ; Determine if the VFP extended frame is present - BNE _skip_vfp_restore ; If not, skip VFP restore + BNE _skip_vfp_restore ; If not, skip VFP restore VLDMIA r12!, {s16-s31} ; Yes, restore additional VFP registers _skip_vfp_restore: #endif @@ -370,11 +364,11 @@ _skip_vfp_restore: MSR PSP, r12 ; Setup the thread's stack pointer ; ; /* Return to thread. */ -; +; BX lr ; Return to thread! ; ; /* The following is the idle wait processing... in this case, no threads are ready for execution and the -; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts ; are disabled to allow use of WFI for waiting for a thread to arrive. */ ; __tx_ts_wait: @@ -390,16 +384,16 @@ __tx_ts_wait: CPSIE i ; Enable interrupts B __tx_ts_wait ; Loop to continue waiting ; -; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are ; already in the handler! */ ; __tx_ts_ready: MOV r7, #0x08000000 ; Build clear PendSV value MOV r8, #0xE000E000 ; Build base NVIC address - STR r7, [r8, #0xD04] ; Clear any PendSV + STR r7, [r8, #0xD04] ; Clear any PendSV ; ; /* Re-enable interrupts and restore new thread. */ -; +; CPSIE i ; Enable interrupts B __tx_ts_restore ; Restore the thread ;} @@ -427,7 +421,7 @@ __tx_SVCallHandler: CMP r1, r2 ; Did we come from user_mode_entry? IT NE ; If no (not equal), then... BXNE lr ; return from where we came. - + LDR r3, [r0, #20] ; This is the saved LR LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address LDR r2, [r1] ; Pickup current thread pointer @@ -436,73 +430,72 @@ __tx_SVCallHandler: STR r3, [r2, #0xA0] ; Save the original LR in thread control block ; If there is memory protection, use kernel stack - LDR r0, [r2, #0x90] ; Load the module instance ptr - LDR r0, [r0, #0x0C] ; Load the module property flags - TST r0, #2 ; Check if memory protected + LDR r0, [r2, #0x90] ; Load the module instance ptr + LDR r0, [r0, #0x0C] ; Load the module property flags + TST r0, #2 ; Check if memory protected BEQ _tx_skip_kernel_stack_enter ; Switch to the module thread's kernel stack - LDR r0, [r2, #0xA8] ; Load the module kernel stack end + LDR r0, [r2, #0xA8] ; Load the module kernel stack end #ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE - LDR r1, [r2, #0xA4] ; Load the module kernel stack start - LDR r3, [r2, #0xAC] ; Load the module kernel stack size - STR r1, [r2, #12] ; Set stack start - STR r0, [r2, #16] ; Set stack end - STR r3, [r2, #20] ; Set stack size + LDR r1, [r2, #0xA4] ; Load the module kernel stack start + LDR r3, [r2, #0xAC] ; Load the module kernel stack size + STR r1, [r2, #12] ; Set stack start + STR r0, [r2, #16] ; Set stack end + STR r3, [r2, #20] ; Set stack size #endif - MRS r3, PSP ; Pickup thread stack pointer - STR r3, [r2, #0xB0] ; Save thread stack pointer + MRS r3, PSP ; Pickup thread stack pointer + STR r3, [r2, #0xB0] ; Save thread stack pointer ; Build kernel stack by copying thread stack two registers at a time - ADD r3, r3, #32 ; start at bottom of hardware stack - LDMDB r3!,{r1-r2} ; - STMDB r0!,{r1-r2} ; - LDMDB r3!,{r1-r2} ; - STMDB r0!,{r1-r2} ; - LDMDB r3!,{r1-r2} ; - STMDB r0!,{r1-r2} ; - LDMDB r3!,{r1-r2} ; - STMDB r0!,{r1-r2} ; + ADD r3, r3, #32 ; start at bottom of hardware stack + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + LDMDB r3!,{r1-r2} + STMDB r0!,{r1-r2} + + MSR PSP, r0 ; Set kernel stack pointer - MSR PSP, r0 ; Set kernel stack pointer - _tx_skip_kernel_stack_enter: MRS r0, CONTROL ; Pickup current CONTROL register - BIC r0, r0, #1 ; Clear the UNPRIV bit + BIC r0, r0, #1 ; Clear the UNPRIV bit MSR CONTROL, r0 ; Setup new CONTROL register BX lr ; Return to thread _tx_thread_user_return: - LDR r2, =_txm_module_user_mode_exit-1 ; Subtract 1 because of THUMB mode. CMP r1, r2 ; Did we come from user_mode_exit? IT NE ; If no (not equal), then... BXNE lr ; return from where we came - + LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address LDR r2, [r1] ; Pickup current thread pointer LDR r1, [r2, #0x9C] ; Pick up user mode STR r1, [r2, #0x98] ; Set the current user mode selection for thread ; If there is memory protection, use kernel stack - LDR r0, [r2, #0x90] ; Load the module instance ptr - LDR r0, [r0, #0x0C] ; Load the module property flags - TST r0, #2 ; Check if memory protected + LDR r0, [r2, #0x90] ; Load the module instance ptr + LDR r0, [r0, #0x0C] ; Load the module property flags + TST r0, #2 ; Check if memory protected BEQ _tx_skip_kernel_stack_exit - -#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE - LDR r0, [r2, #0xB4] ; Load the module thread stack start - LDR r1, [r2, #0xB8] ; Load the module thread stack end - LDR r3, [r2, #0xBC] ; Load the module thread stack size - STR r0, [r2, #12] ; Set stack start - STR r1, [r2, #16] ; Set stack end - STR r3, [r2, #20] ; Set stack size -#endif - LDR r0, [r2, #0xB0] ; Load the module thread stack pointer - MRS r3, PSP ; Pickup kernel stack pointer - ; Copy kernel hardware stack to module thread stack. +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + LDR r0, [r2, #0xB4] ; Load the module thread stack start + LDR r1, [r2, #0xB8] ; Load the module thread stack end + LDR r3, [r2, #0xBC] ; Load the module thread stack size + STR r0, [r2, #12] ; Set stack start + STR r1, [r2, #16] ; Set stack end + STR r3, [r2, #20] ; Set stack size +#endif + LDR r0, [r2, #0xB0] ; Load the module thread stack pointer + MRS r3, PSP ; Pickup kernel stack pointer + + ; Copy kernel hardware stack to module thread stack. LDM r3!,{r1-r2} STM r0!,{r1-r2} LDM r3!,{r1-r2} @@ -511,13 +504,13 @@ _tx_thread_user_return: STM r0!,{r1-r2} LDM r3!,{r1-r2} STM r0!,{r1-r2} - SUB r0, r0, #32 ; Subtract 32 to get back to top of stack - MSR PSP, r0 ; Set thread stack pointer + SUB r0, r0, #32 ; Subtract 32 to get back to top of stack + MSR PSP, r0 ; Set thread stack pointer LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address LDR r2, [r1] ; Pickup current thread pointer LDR r1, [r2, #0x9C] ; Pick up user mode - + _tx_skip_kernel_stack_exit: MRS r0, CONTROL ; Pickup current CONTROL register ORR r0, r0, r1 ; OR in the user mode bit @@ -542,7 +535,7 @@ _txm_module_priv: ; At this point, we are out of user mode. The original LR has been saved in the ; thread control block. Simply call the kernel dispatch function. BL _txm_module_manager_kernel_dispatch - + ; Pickup the original LR value while still in privileged mode LDR r2, =_tx_thread_current_ptr ; Build current thread pointer address LDR r3, [r2] ; Pickup current thread pointer @@ -550,7 +543,7 @@ _txm_module_priv: SVC 2 ; Exit kernel and return to user mode _txm_module_user_mode_exit: - BX lr ; Return to the caller + BX lr ; Return to the caller NOP NOP NOP @@ -563,7 +556,7 @@ _txm_module_user_mode_exit: PUBLIC tx_thread_fpu_enable tx_thread_fpu_enable: ; -; /* Automatic VPF logic is supported, this function is present only for +; /* Automatic VPF logic is supported, this function is present only for ; backward compatibility purposes and therefore simply returns. */ ; BX LR ; Return to caller @@ -571,7 +564,7 @@ tx_thread_fpu_enable: PUBLIC tx_thread_fpu_disable tx_thread_fpu_disable: ; -; /* Automatic VPF logic is supported, this function is present only for +; /* Automatic VPF logic is supported, this function is present only for ; backward compatibility purposes and therefore simply returns. */ ; BX LR ; Return to caller diff --git a/ports_module/cortex-m7/iar/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex-m7/iar/module_manager/src/tx_thread_stack_build.s index 36518e5e..919b0da7 100644 --- a/ports_module/cortex-m7/iar/module_manager/src/tx_thread_stack_build.s +++ b/ports_module/cortex-m7/iar/module_manager/src/tx_thread_stack_build.s @@ -21,23 +21,14 @@ ;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build Cortex-M7/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -69,7 +60,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -77,11 +68,11 @@ PUBLIC _tx_thread_stack_build _tx_thread_stack_build: ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-M7 should look like the following after it is built: -; -; Stack Top: +; +; Stack Top: ; LR Interrupted LR (LR at time of PENDSV) ; r4 Initial value for r4 ; r5 Initial value for r5 @@ -120,7 +111,7 @@ _tx_thread_stack_build: STR r3, [r2, #28] ; Store initial r10 STR r3, [r2, #32] ; Store initial r11 ; -; /* Hardware stack follows. / +; /* Hardware stack follows. */ ; STR r3, [r2, #36] ; Store initial r0 STR r3, [r2, #40] ; Store initial r1 @@ -141,4 +132,3 @@ _tx_thread_stack_build: BX lr ; Return to caller ;} END - diff --git a/ports_module/cortex-m7/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex-m7/iar/module_manager/src/tx_thread_system_return.s index 126a9c78..81be6e32 100644 --- a/ports_module/cortex-m7/iar/module_manager/src/tx_thread_system_return.s +++ b/ports_module/cortex-m7/iar/module_manager/src/tx_thread_system_return.s @@ -20,25 +20,15 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE ; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return Cortex-M7/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -70,7 +60,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -79,9 +69,9 @@ _tx_thread_system_return??rA: _tx_thread_system_return: ; -; /* Return to real scheduler via PendSV. Note that this routine is often +; /* Return to real scheduler via PendSV. Note that this routine is often ; replaced with in-line assembly in tx_port.h to improved performance. */ -; +; MOV r0, #0x10000000 ; Load PENDSVSET bit MOV r1, #0xE000E000 ; Load NVIC base STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR @@ -92,6 +82,6 @@ _tx_thread_system_return: CPSIE i ; Enable interrupts MSR PRIMASK, r1 ; Restore original interrupt posture _isr_context: - BX lr ; Return to caller + BX lr ; Return to caller ;} - END + END diff --git a/ports_module/cortex-m7/iar/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex-m7/iar/module_manager/src/tx_timer_interrupt.s index c900f267..2f5594d5 100644 --- a/ports_module/cortex-m7/iar/module_manager/src/tx_timer_interrupt.s +++ b/ports_module/cortex-m7/iar/module_manager/src/tx_timer_interrupt.s @@ -20,17 +20,6 @@ ;/**************************************************************************/ ;/**************************************************************************/ ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_timer.h" -;#include "tx_thread.h" -; -; -;Define Assembly language external references... ; EXTERN _tx_timer_time_slice EXTERN _tx_timer_system_clock @@ -46,14 +35,14 @@ EXTERN _tx_thread_preempt_disable ; ; - SECTION `.text`:CODE:NOROOT(2) - THUMB + SECTION `.text`:CODE:NOROOT(2) + THUMB ;/**************************************************************************/ ;/* */ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt Cortex-M7/IAR */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -86,7 +75,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) @@ -109,7 +98,7 @@ _tx_timer_interrupt: ; if (_tx_timer_time_slice) ; { ; - MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice + MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice LDR r2, [r3, #0] ; Pickup time-slice CBZ r2, __tx_timer_no_time_slice ; Is it non-active? ; Yes, skip time-slice processing @@ -226,13 +215,13 @@ __tx_timer_dont_activate: ; if (_tx_timer_expired_time_slice) ; { ; - MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired + MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired LDR r2, [r3, #0] ; Pickup the actual flag CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set ; No, skip time-slice processing ; ; /* Time slice interrupted thread. */ -; _tx_thread_time_slice(); +; _tx_thread_time_slice(); BL _tx_thread_time_slice ; Call time-slice processing MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag @@ -265,4 +254,3 @@ __tx_timer_nothing_expired: ; ;} END - diff --git a/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_alignment_adjust.c index e962906f..278c3f8a 100644 --- a/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_alignment_adjust.c +++ b/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_alignment_adjust.c @@ -10,15 +10,15 @@ /**************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #define TX_SOURCE_CODE @@ -26,42 +26,42 @@ #include "txm_module.h" -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_power_of_two_block_size Cortex-M7/MPU/IAR */ -/* 6.0.1 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_power_of_two_block_size Cortex-M7/MPU/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function calculates a power of two size at or immediately above*/ -/* the input size and returns it to the caller. */ -/* */ -/* INPUT */ -/* */ -/* size Block size */ -/* */ -/* OUTPUT */ -/* */ -/* calculated size Rounded up to power of two */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function calculates a power of two size at or immediately above*/ +/* the input size and returns it to the caller. */ +/* */ +/* INPUT */ +/* */ +/* size Block size */ +/* */ +/* OUTPUT */ +/* */ +/* calculated size Rounded up to power of two */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_power_of_two_block_size(ULONG size) @@ -89,52 +89,52 @@ ULONG _txm_power_of_two_block_size(ULONG size) } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_alignment_adjust Cortex-M7/MPU/IAR */ -/* 6.0.1 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_alignment_adjust Cortex-M7/MPU/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function adjusts the alignment and size of the code and data */ -/* section for a given module implementation. */ -/* */ -/* INPUT */ -/* */ -/* module_preamble Pointer to module preamble */ -/* code_size Size of the code area (updated) */ -/* code_alignment Code area alignment (updated) */ -/* data_size Size of data area (updated) */ -/* data_alignment Data area alignment (updated) */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* _txm_power_of_two_block_size Calculate power of two size */ -/* */ -/* CALLED BY */ -/* */ -/* Initial thread stack frame */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function adjusts the alignment and size of the code and data */ +/* section for a given module implementation. */ +/* */ +/* INPUT */ +/* */ +/* module_preamble Pointer to module preamble */ +/* code_size Size of the code area (updated) */ +/* code_alignment Code area alignment (updated) */ +/* data_size Size of data area (updated) */ +/* data_alignment Data area alignment (updated) */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_power_of_two_block_size Calculate power of two size */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, - ULONG *code_size, - ULONG *code_alignment, - ULONG *data_size, +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, + ULONG *code_size, + ULONG *code_alignment, + ULONG *data_size, ULONG *data_alignment) { @@ -178,11 +178,8 @@ ULONG data_size_accum; local_data_size = data_size_accum; /* Return all the information to the caller. */ - *code_size = local_code_size; + *code_size = local_code_size; *code_alignment = local_code_alignment; *data_size = local_data_size; *data_alignment = local_data_alignment; } - - - diff --git a/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_external_memory_enable.c index f17e7388..3ac6b6fe 100644 --- a/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_external_memory_enable.c +++ b/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -10,15 +10,15 @@ /**************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #define TX_SOURCE_CODE @@ -29,52 +29,52 @@ #include "txm_module.h" -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_external_memory_enable Cortex-M7/MPU/IAR */ -/* 6.0.1 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_external_memory_enable Cortex-M7/MPU/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function creates an entry in the MPU table for a shared */ -/* memory space. */ -/* */ -/* INPUT */ -/* */ -/* module_instance Module instance pointer */ -/* start_address Start address of memory */ -/* length Length of external memory */ -/* attributes Memory attributes (r/w) */ -/* */ -/* OUTPUT */ -/* */ -/* status Completion status */ -/* */ -/* CALLS */ -/* */ -/* _tx_mutex_get Get protection mutex */ -/* _tx_mutex_put Release protection mutex */ -/* _txm_power_of_two_block_size Round length to power of two */ -/* */ -/* CALLED BY */ -/* */ -/* Application code */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function creates an entry in the MPU table for a shared */ +/* memory space. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* start_address Start address of memory */ +/* length Length of external memory */ +/* attributes Memory attributes (r/w) */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_mutex_get Get protection mutex */ +/* _tx_mutex_put Release protection mutex */ +/* _txm_power_of_two_block_size Round length to power of two */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, - VOID *start_address, - ULONG length, +UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, + VOID *start_address, + ULONG length, UINT attributes) { @@ -86,18 +86,16 @@ ULONG address; ULONG shared_index; ULONG attributes_check = 0; - /* Determine if the module manager has been initialized. */ + /* Determine if the module manager has not been initialized yet. */ if (_txm_module_manager_ready != TX_TRUE) { - /* Module manager has not been initialized. */ - return(TX_NOT_AVAILABLE); + return(TX_NOT_AVAILABLE); } /* Determine if the module is valid. */ if (module_instance == TX_NULL) { - /* Invalid module pointer. */ return(TX_PTR_ERROR); } @@ -108,7 +106,6 @@ ULONG attributes_check = 0; /* Determine if the module instance is valid. */ if (module_instance -> txm_module_instance_id != TXM_MODULE_ID) { - /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); @@ -119,7 +116,6 @@ ULONG attributes_check = 0; /* Determine if the module instance is in the loaded state. */ if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) { - /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); @@ -130,7 +126,6 @@ ULONG attributes_check = 0; /* Determine if there are shared memory entries available. */ if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) { - /* Release the protection mutex. */ _tx_mutex_put(&_txm_module_manager_mutex); @@ -138,7 +133,7 @@ ULONG attributes_check = 0; return(TX_NO_MEMORY); } - /* Start address and length must adhere to Cortex-M7 MPU. + /* Start address and length must adhere to Cortex-M7 MPU. The address must align with the block size. */ block_size = _txm_power_of_two_block_size(length); @@ -192,4 +187,3 @@ ULONG attributes_check = 0; /* Return success. */ return(TX_SUCCESS); } - diff --git a/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_memory_fault_handler.c index 5aac2bac..c61dd2fd 100644 --- a/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_memory_fault_handler.c +++ b/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -10,15 +10,15 @@ /**************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #define TX_SOURCE_CODE @@ -33,50 +33,50 @@ VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); -/* Define a macro that can be used to allocate global variables useful to - store information about the last fault. This macro is defined in +/* Define a macro that can be used to allocate global variables useful to + store information about the last fault. This macro is defined in txm_module_port.h and is usually populated in the assembly language fault handling prior to the code calling _txm_module_manager_memory_fault_handler. */ TXM_MODULE_MANAGER_FAULT_INFO -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_memory_fault_handler Cortex-M7/MPU/IAR */ -/* 6.0.1 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_handler Cortex-M7/MPU/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function handles a fault associated with a memory protected */ -/* module. */ -/* */ -/* INPUT */ -/* */ -/* None */ -/* */ -/* OUTPUT */ -/* */ -/* None */ -/* */ -/* CALLS */ -/* */ -/* _tx_thread_terminate Terminate thread */ -/* */ -/* CALLED BY */ -/* */ -/* Fault handler */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function handles a fault associated with a memory protected */ +/* module. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_terminate Terminate thread */ +/* */ +/* CALLED BY */ +/* */ +/* Fault handler */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_memory_fault_handler(VOID) @@ -85,7 +85,6 @@ VOID _txm_module_manager_memory_fault_handler(VOID) TXM_MODULE_INSTANCE *module_instance_ptr; TX_THREAD *thread_ptr; - /* Pickup the current thread. */ thread_ptr = _tx_thread_current_ptr; @@ -95,7 +94,6 @@ TX_THREAD *thread_ptr; /* Is there a thread? */ if (thread_ptr) { - /* Pickup the module instance. */ module_instance_ptr = thread_ptr -> tx_thread_module_instance_ptr; @@ -106,9 +104,7 @@ TX_THREAD *thread_ptr; /* Determine if there is a user memory fault notification callback. */ if (_txm_module_manager_fault_notify) { - /* Yes, call the user's notification memory fault callback. */ (_txm_module_manager_fault_notify)(thread_ptr, module_instance_ptr); } } - diff --git a/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_memory_fault_notify.c index cd8c1e29..e7fe25de 100644 --- a/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_memory_fault_notify.c +++ b/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -10,15 +10,15 @@ /**************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #define TX_SOURCE_CODE @@ -34,53 +34,51 @@ extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTA -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_memory_fault_notify Cortex-M7/MPU/IAR */ -/* 6.0.1 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_notify Cortex-M7/MPU/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function registers an application callback when/if a memory */ -/* fault occurs. The supplied thread is automatically terminated, but */ -/* any other threads in the same module may still execute. */ -/* */ -/* INPUT */ -/* */ -/* notify_function Memory fault notification */ -/* function, NULL disables. */ -/* */ -/* OUTPUT */ -/* */ -/* status Completion status */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* Application Code */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application callback when/if a memory */ +/* fault occurs. The supplied thread is automatically terminated, but */ +/* any other threads in the same module may still execute. */ +/* */ +/* INPUT */ +/* */ +/* notify_function Memory fault notification */ +/* function, NULL disables. */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) { - /* Setup notification function. */ _txm_module_manager_fault_notify = notify_function; /* Return success. */ return(TX_SUCCESS); } - diff --git a/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_mm_register_setup.c index c797080c..db5d8de9 100644 --- a/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -10,59 +10,58 @@ /**************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ #define TX_SOURCE_CODE #include "tx_api.h" #include "txm_module.h" -#include "txm_module_manager_util.h" -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_region_size_get Cortex-M7/MPU/IAR */ -/* 6.0.1 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_region_size_get Cortex-M7/MPU/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function converts the region size in bytes to the block size */ -/* for the Cortex-M7 MPU specification. */ -/* */ -/* INPUT */ -/* */ -/* block_size Size of the block in bytes */ -/* */ -/* OUTPUT */ -/* */ -/* MPU size specification */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _txm_module_manager_mm_register_setup */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function converts the region size in bytes to the block size */ +/* for the Cortex-M7 MPU specification. */ +/* */ +/* INPUT */ +/* */ +/* block_size Size of the block in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* MPU size specification */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_region_size_get(ULONG block_size) @@ -70,7 +69,6 @@ ULONG _txm_module_manager_region_size_get(ULONG block_size) ULONG return_value; - /* Process relative to the input block size. */ if (block_size == 32) { @@ -140,7 +138,7 @@ ULONG return_value; { return_value = 0x14; } - else + else { /* Max 4MB MPU pages for modules. */ return_value = 0x15; @@ -150,45 +148,43 @@ ULONG return_value; } - - -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_calculate_srd_bits Cortex-M7/MPU/IAR */ -/* 6.0.1 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_calculate_srd_bits Cortex-M7/MPU/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function calculates the SRD bits that need to be set to */ -/* protect "length" bytes in a block. */ -/* */ -/* INPUT */ -/* */ -/* block_size Size of the block in bytes */ -/* length Actual length in bytes */ -/* */ -/* OUTPUT */ -/* */ -/* SRD bits to be OR'ed with region attribute register. */ -/* */ -/* CALLS */ -/* */ -/* None */ -/* */ -/* CALLED BY */ -/* */ -/* _txm_module_manager_mm_register_setup */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function calculates the SRD bits that need to be set to */ +/* protect "length" bytes in a block. */ +/* */ +/* INPUT */ +/* */ +/* block_size Size of the block in bytes */ +/* length Actual length in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* SRD bits to be OR'ed with region attribute register. */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) @@ -230,62 +226,61 @@ UINT srd_bit_index; } - -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_mm_register_setup Cortex-M7/MPU/IAR */ -/* 6.0.1 */ +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_mm_register_setup Cortex-M7/MPU/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function sets up the MPU register definitions based on the */ -/* module's memory characteristics. */ -/* MPU layout for the Cortex-M7: */ -/* Entry Description */ -/* 0 Kernel mode entry */ -/* 1 Module code region */ -/* 2 Module code region */ -/* 3 Module code region */ -/* 4 Module code region */ -/* 5 Module data region */ -/* 6 Module data region */ -/* 7 Module data region */ -/* 8 Module data region */ -/* 9 Module shared memory region */ -/* 10 Module shared memory region */ -/* 11 Module shared memory region */ -/* 12 Unused region */ -/* 13 Unused region */ -/* 14 Unused region */ -/* 15 Unused region */ -/* */ -/* */ -/* INPUT */ -/* */ -/* module_instance Pointer to module instance */ -/* */ -/* OUTPUT */ -/* */ -/* MPU specifications for module in module_instance */ -/* */ -/* CALLS */ -/* */ -/* _txm_module_manager_region_size_get */ -/* */ -/* CALLED BY */ -/* */ -/* _txm_module_manager_thread_create */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function sets up the MPU register definitions based on the */ +/* module's memory characteristics. */ +/* MPU layout for the Cortex-M7: */ +/* Entry Description */ +/* 0 Kernel mode entry */ +/* 1 Module code region */ +/* 2 Module code region */ +/* 3 Module code region */ +/* 4 Module code region */ +/* 5 Module data region */ +/* 6 Module data region */ +/* 7 Module data region */ +/* 8 Module data region */ +/* 9 Module shared memory region */ +/* 10 Module shared memory region */ +/* 11 Module shared memory region */ +/* 12 Unused region */ +/* 13 Unused region */ +/* 14 Unused region */ +/* 15 Unused region */ +/* */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* */ +/* OUTPUT */ +/* */ +/* MPU specifications for module in module_instance */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_manager_region_size_get */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_thread_create */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) @@ -305,7 +300,7 @@ UINT i; /* Setup the first MPU region for kernel mode entry. */ - /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. + /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. Mask address to proper range, region 0, set Valid bit. */ module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | 0x10; /* Set the attributes, size (32 bytes) and enable bit. */ @@ -378,7 +373,7 @@ UINT i; srd_bits = 0; /* Pickup data starting address and actual size. */ - data_address = (ULONG) module_instance -> txm_module_instance_data_start; + data_address = (ULONG) module_instance -> txm_module_instance_data_start; /* Adjust the size of the module elements to be aligned to the default alignment. We do this so that when we partition the allocated memory, we can simply place these regions right beside @@ -460,48 +455,48 @@ UINT i; } -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_shared_memory_check_outside */ -/* Cortex-M7/MPU/IAR */ -/* 6.0.1 */ + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_inside_data_check Cortex-M7/MPU/IAR */ +/* 6.1 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This function checks if the specified object is outside shared */ -/* memory. */ -/* */ -/* INPUT */ -/* */ -/* module_instance Pointer to module instance */ -/* obj_ptr Pointer to the object */ -/* obj_size Size of the object */ -/* */ -/* OUTPUT */ -/* */ -/* Whether the object is outside the shared memory region. */ -/* */ -/* CALLS */ -/* */ -/* N/A */ -/* */ -/* CALLED BY */ -/* */ -/* Module dispatch check functions */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This function checks if the specified object is inside shared */ +/* memory. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* obj_ptr Pointer to the object */ +/* obj_size Size of the object */ +/* */ +/* OUTPUT */ +/* */ +/* Whether the object is inside the shared memory region. */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Module dispatch check functions */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ /* */ /**************************************************************************/ -UCHAR _txm_module_manager_shared_memory_check_outside(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) +UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) { UINT shared_memory_index; @@ -509,71 +504,14 @@ UINT num_shared_memory_mpu_entries; ALIGN_TYPE shared_memory_address_start; ALIGN_TYPE shared_memory_address_end; - num_shared_memory_mpu_entries = module_instance -> txm_module_instance_shared_memory_count; - for (shared_memory_index = 0; shared_memory_index < num_shared_memory_mpu_entries; shared_memory_index++) + /* Check if the object is inside the module data. */ + if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && + ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) { - - shared_memory_address_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address[shared_memory_index]; - shared_memory_address_end = shared_memory_address_start + module_instance -> txm_module_instance_shared_memory_length[shared_memory_index]; - - if (TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_EXCLUSIVE(shared_memory_address_start, shared_memory_address_end, - obj_ptr, obj_size)) - { - return(TX_FALSE); - } + return(TX_TRUE); } - return(TX_TRUE); -} - -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_shared_memory_check_inside Cortex-M7/MPU/IAR */ -/* 6.0.1 */ -/* AUTHOR */ -/* */ -/* Scott Larson, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function checks if the specified object is inside shared */ -/* memory. */ -/* */ -/* INPUT */ -/* */ -/* module_instance Pointer to module instance */ -/* obj_ptr Pointer to the object */ -/* obj_size Size of the object */ -/* */ -/* OUTPUT */ -/* */ -/* Whether the object is inside the shared memory region. */ -/* */ -/* CALLS */ -/* */ -/* N/A */ -/* */ -/* CALLED BY */ -/* */ -/* Module dispatch check functions */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ -/* */ -/**************************************************************************/ -UCHAR _txm_module_manager_shared_memory_check_inside(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) -{ - -UINT shared_memory_index; -UINT num_shared_memory_mpu_entries; -ALIGN_TYPE shared_memory_address_start; -ALIGN_TYPE shared_memory_address_end; - + /* Check if the object is inside the shared memory. */ num_shared_memory_mpu_entries = module_instance -> txm_module_instance_shared_memory_count; for (shared_memory_index = 0; shared_memory_index < num_shared_memory_mpu_entries; shared_memory_index++) { @@ -581,72 +519,8 @@ ALIGN_TYPE shared_memory_address_end; shared_memory_address_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address[shared_memory_index]; shared_memory_address_end = shared_memory_address_start + module_instance -> txm_module_instance_shared_memory_length[shared_memory_index]; - if (TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_EXCLUSIVE(shared_memory_address_start, shared_memory_address_end, - obj_ptr, obj_size)) - { - return(TX_TRUE); - } - } - - return(TX_FALSE); -} - -/**************************************************************************/ -/* */ -/* FUNCTION RELEASE */ -/* */ -/* _txm_module_manager_shared_memory_check_inside_byte */ -/* Cortex-M7/MPU/IAR */ -/* 6.0.1 */ -/* AUTHOR */ -/* */ -/* Scott Larson, Microsoft Corporation */ -/* */ -/* DESCRIPTION */ -/* */ -/* This function checks if the specified byte is inside shared memory. */ -/* */ -/* INPUT */ -/* */ -/* module_instance Pointer to module instance */ -/* byte_ptr Pointer to the byte */ -/* */ -/* OUTPUT */ -/* */ -/* Whether the byte is inside the shared memory region. */ -/* */ -/* CALLS */ -/* */ -/* N/A */ -/* */ -/* CALLED BY */ -/* */ -/* Module dispatch check functions */ -/* */ -/* RELEASE HISTORY */ -/* */ -/* DATE NAME DESCRIPTION */ -/* */ -/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ -/* */ -/**************************************************************************/ -UCHAR _txm_module_manager_shared_memory_check_inside_byte(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE byte_ptr) -{ - -UINT shared_memory_index; -UINT num_shared_memory_mpu_entries; -ALIGN_TYPE shared_memory_address_start; -ALIGN_TYPE shared_memory_address_end; - - num_shared_memory_mpu_entries = module_instance -> txm_module_instance_shared_memory_count; - for (shared_memory_index = 0; shared_memory_index < num_shared_memory_mpu_entries; shared_memory_index++) - { - - shared_memory_address_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address[shared_memory_index]; - shared_memory_address_end = shared_memory_address_start + module_instance -> txm_module_instance_shared_memory_length[shared_memory_index]; - - if (TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_EXCLUSIVE_BYTE(shared_memory_address_start, shared_memory_address_end, - byte_ptr)) + if ((obj_ptr >= (ALIGN_TYPE) shared_memory_address_start) && + ((obj_ptr + obj_size) <= (ALIGN_TYPE) shared_memory_address_end)) { return(TX_TRUE); } diff --git a/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_thread_stack_build.s index 50f5b003..8491d221 100644 --- a/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_thread_stack_build.s +++ b/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_thread_stack_build.s @@ -10,66 +10,57 @@ ;/**************************************************************************/ ; ; -;/**************************************************************************/ -;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ -;/** */ -;/** Module Manager */ -;/** */ -;/**************************************************************************/ -;/**************************************************************************/ +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Module Manager */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ ; ; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; -; - SECTION `.text`:CODE:NOROOT(2) - THUMB -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ -;/* _txm_module_manager_thread_stack_build Cortex-M7/MPU/IAR */ -;/* 6.0.1 */ + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _txm_module_manager_thread_stack_build Cortex-M7/MPU/IAR */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ ;/* */ -;/* DESCRIPTION */ -;/* */ -;/* This function builds a stack frame on the supplied thread's stack. */ -;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ -;/* thread_ptr Pointer to thread */ -;/* function_ptr Pointer to shell function */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread */ +;/* function_ptr Pointer to shell function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) @@ -77,11 +68,11 @@ PUBLIC _txm_module_manager_thread_stack_build _txm_module_manager_thread_stack_build: ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the Cortex-M should look like the following after it is built: -; -; Stack Top: +; +; Stack Top: ; LR Interrupted LR (LR at time of PENDSV) ; r4 Initial value for r4 ; r5 Initial value for r5 @@ -89,7 +80,7 @@ _txm_module_manager_thread_stack_build: ; r7 Initial value for r7 ; r8 Initial value for r8 ; r9 Initial value for r9 -; r10 (sl) Initial value for r10 (sl) +; r10 Initial value for r10 ; r11 Initial value for r11 ; r0 Initial value for r0 (Hardware stack starts here!!) ; r1 Initial value for r1 @@ -116,17 +107,15 @@ _txm_module_manager_thread_stack_build: STR r3, [r2, #12] ; Store initial r6 STR r3, [r2, #16] ; Store initial r7 STR r3, [r2, #20] ; Store initial r8 - LDR r3, [r0, #12] ; Pickup stack starting address - STR r3, [r2, #28] ; Store initial r10 (sl) - MOV r3, #0 ; Build initial register value + STR r3, [r2, #28] ; Store initial r10 STR r3, [r2, #32] ; Store initial r11 ; -; /* Hardware stack follows. / +; /* Hardware stack follows. */ ; STR r0, [r2, #36] ; Store initial r0, which is the thread control block LDR r3, [r0, #8] ; Pickup thread entry info pointer,which is in the stack pointer position of the thread control block. - ; It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this + ; It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this ; function with the actual, initial stack pointer. STR r3, [r2, #40] ; Store initial r1, which is the module entry information. LDR r3, [r3, #8] ; Pickup data base register from the module information @@ -145,8 +134,7 @@ _txm_module_manager_thread_stack_build: ; /* Setup stack pointer. */ ; thread_ptr -> tx_thread_stack_ptr = r2; ; - STR r2, [r0, #8] ; Save stack pointer in thread's - ; control block + STR r2, [r0, #8] ; Save stack pointer in thread's control block BX lr ; Return to caller ;} END diff --git a/ports_module/cortex-r4/ac6/example_build/sample_threadx_module/.cproject b/ports_module/cortex-r4/ac6/example_build/sample_threadx_module/.cproject new file mode 100644 index 00000000..7f9fcfd7 --- /dev/null +++ b/ports_module/cortex-r4/ac6/example_build/sample_threadx_module/.cproject @@ -0,0 +1,153 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_module/cortex-r4/ac6/example_build/sample_threadx_module/.project b/ports_module/cortex-r4/ac6/example_build/sample_threadx_module/.project new file mode 100644 index 00000000..1db05610 --- /dev/null +++ b/ports_module/cortex-r4/ac6/example_build/sample_threadx_module/.project @@ -0,0 +1,28 @@ + + + sample_threadx_module + + + tx + txm + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/ports_module/cortex-r4/ac6/example_build/sample_threadx_module/.settings/language.settings.xml b/ports_module/cortex-r4/ac6/example_build/sample_threadx_module/.settings/language.settings.xml new file mode 100644 index 00000000..be74d0a1 --- /dev/null +++ b/ports_module/cortex-r4/ac6/example_build/sample_threadx_module/.settings/language.settings.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_module/cortex-r4/ac6/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex-r4/ac6/example_build/sample_threadx_module/sample_threadx_module.c new file mode 100644 index 00000000..feb9fb84 --- /dev/null +++ b/ports_module/cortex-r4/ac6/example_build/sample_threadx_module/sample_threadx_module.c @@ -0,0 +1,425 @@ +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, + event flags group, byte pool, and block pool. */ + +/* Specify that this is a module! */ + +#define TXM_MODULE + + +/* Include the ThreadX module definitions. */ + +#include "txm_module.h" + + +/* Define constants. */ + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the pool space in the bss section of the module. ULONG is used to + get the word alignment. */ + +ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD *thread_0; +TX_THREAD *thread_1; +TX_THREAD *thread_2; +TX_THREAD *thread_3; +TX_THREAD *thread_4; +TX_THREAD *thread_5; +TX_THREAD *thread_6; +TX_THREAD *thread_7; +TX_QUEUE *queue_0; +TX_SEMAPHORE *semaphore_0; +TX_MUTEX *mutex_0; +TX_EVENT_FLAGS_GROUP *event_flags_0; +TX_BYTE_POOL *byte_pool_0; +TX_BLOCK_POOL *block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter = 0x12; +ULONG thread_1_counter = 0x34; +ULONG thread_2_counter = 0x56; +ULONG thread_3_counter = 0x78; +ULONG thread_4_counter = 0x9A; +ULONG thread_5_counter = 0xBC; +ULONG thread_6_counter = 0xDE; +ULONG thread_7_counter = 0xEF; +ULONG semaphore_0_puts; +ULONG event_0_sets; +ULONG queue_0_sends; + +ULONG thread_1_messages_sent; +ULONG thread_2_messages_received; + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + +void semaphore_0_notify(TX_SEMAPHORE *semaphore_ptr) +{ + + if (semaphore_ptr == semaphore_0) + semaphore_0_puts++; +} + + +void event_0_notify(TX_EVENT_FLAGS_GROUP *event_flag_group_ptr) +{ + + if (event_flag_group_ptr == event_flags_0) + event_0_sets++; +} + + +void queue_0_notify(TX_QUEUE *queue_ptr) +{ + + if (queue_ptr == queue_0) + queue_0_sends++; +} + + +/* Define the module start function. */ + +void demo_module_start(ULONG id) +{ + +CHAR *pointer; + + /* Allocate all the objects. In MMU mode, modules cannot allocate control blocks within + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + the control block(s). */ + txm_module_object_allocate((void *) &thread_0, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &thread_1, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &thread_2, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &thread_3, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &thread_4, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &thread_5, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &thread_6, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &thread_7, sizeof(TX_THREAD)); + txm_module_object_allocate((void *) &queue_0, sizeof(TX_QUEUE)); + txm_module_object_allocate((void *) &semaphore_0, sizeof(TX_SEMAPHORE)); + txm_module_object_allocate((void *) &mutex_0, sizeof(TX_MUTEX)); + txm_module_object_allocate((void *) &event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); + txm_module_object_allocate((void *) &byte_pool_0, sizeof(TX_BYTE_POOL)); + txm_module_object_allocate((void *) &block_pool_0, sizeof(TX_BLOCK_POOL)); + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(queue_0, "module queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + tx_queue_send_notify(queue_0, queue_0_notify); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(semaphore_0, "module semaphore 0", 1); + + tx_semaphore_put_notify(semaphore_0, semaphore_0_notify); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(event_flags_0, "module event flags 0"); + + tx_event_flags_set_notify(event_flags_0, event_0_notify); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(mutex_0, "module mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(block_pool_0, "module block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + /* Test external/shared memory. */ + *(ULONG *) 0x08025000 = 0xdeadbeef; + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports_module/cortex-r4/ac6/example_build/sample_threadx_module/semihosting.c b/ports_module/cortex-r4/ac6/example_build/sample_threadx_module/semihosting.c new file mode 100644 index 00000000..29268630 --- /dev/null +++ b/ports_module/cortex-r4/ac6/example_build/sample_threadx_module/semihosting.c @@ -0,0 +1,27 @@ +/* Disable semihosting */ +#include + +#if (__ARMCC_VERSION < 6000000) +#pragma import(__use_no_semihosting) +#else +void use_no_semihosting(void) +{ + __asm(".global __use_no_semihosting\n\t"); +} +#endif + +char *$Sub$$_sys_command_string(char *cmd, int len) +{ + return 0; +} + +__attribute__((noreturn)) void $Sub$$_sys_exit(int return_code) +{ + while(1); +} + +__attribute__((noreturn)) int $Sub$$__raise(int signal, int type) +{ + while(1); +} + diff --git a/ports_module/cortex-r4/ac6/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex-r4/ac6/example_build/sample_threadx_module/txm_module_preamble.S new file mode 100644 index 00000000..b39ba709 --- /dev/null +++ b/ports_module/cortex-r4/ac6/example_build/sample_threadx_module/txm_module_preamble.S @@ -0,0 +1,58 @@ + + .text + +/* Define common external references. */ + +.global _txm_module_thread_shell_entry +.global demo_module_start +.global _txm_module_callback_request_thread_entry +.global Image$$ER_RO$$Length +.global Image$$ER_RW$$Length +.global Image$$ER_ZI$$ZI$$Length + +/* Stack aligned, ROPI and RWPI, R9 used as data offset register. */ +.eabi_attribute Tag_ABI_align_preserved, 1 +.eabi_attribute Tag_ABI_PCS_RO_data, 1 +.eabi_attribute Tag_ABI_PCS_R9_use, 1 +.eabi_attribute Tag_ABI_PCS_RW_data, 2 + +__txm_module_preamble: +.word 0x4D4F4455 /* Module ID */ +.word 0x6 /* Module Major Version */ +.word 0x1 /* Module Minor Version */ +.word 32 /* Module Preamble Size in 32-bit words */ +.word 0x12345678 /* Module ID (application defined) */ +.word 0x01000001 /* Module Properties where: + Bits 31-24: Compiler ID + 0 -> IAR + 1 -> RVDS/ARM + 2 -> GNU + Bits 23-1: Reserved + Bit 0: 0 -> Privileged mode execution (no MMU protection) + 1 -> User mode execution (MMU protection) */ +.word _txm_module_thread_shell_entry - __txm_module_preamble /* Module Shell Entry Point */ +.word demo_module_start - __txm_module_preamble /* Module Start Thread Entry Point */ +.word 0 /* Module Stop Thread Entry Point */ +.word 1 /* Module Start/Stop Thread Priority */ +.word 1024 /* Module Start/Stop Thread Stack Size */ +.word _txm_module_callback_request_thread_entry - __txm_module_preamble /* Module Callback Thread Entry */ +.word 1 /* Module Callback Thread Priority */ +.word 1024 /* Module Callback Thread Stack Size */ +.word 9000 /* Module Code Size */ +.word 11000 /* Module Data Size */ +.word 0 /* Reserved 0 */ +.word 0 /* Reserved 1 */ +.word 0 /* Reserved 2 */ +.word 0 /* Reserved 3 */ +.word 0 /* Reserved 4 */ +.word 0 /* Reserved 5 */ +.word 0 /* Reserved 6 */ +.word 0 /* Reserved 7 */ +.word 0 /* Reserved 8 */ +.word 0 /* Reserved 9 */ +.word 0 /* Reserved 10 */ +.word 0 /* Reserved 11 */ +.word 0 /* Reserved 12 */ +.word 0 /* Reserved 13 */ +.word 0 /* Reserved 14 */ +.word 0 /* Reserved 15 */ diff --git a/ports_module/cortex-r4/ac6/example_build/sample_threadx_module_manager/.cproject b/ports_module/cortex-r4/ac6/example_build/sample_threadx_module_manager/.cproject new file mode 100644 index 00000000..a8065ae9 --- /dev/null +++ b/ports_module/cortex-r4/ac6/example_build/sample_threadx_module_manager/.cproject @@ -0,0 +1,136 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_module/cortex-r4/ac6/example_build/sample_threadx_module_manager/.project b/ports_module/cortex-r4/ac6/example_build/sample_threadx_module_manager/.project new file mode 100644 index 00000000..58913117 --- /dev/null +++ b/ports_module/cortex-r4/ac6/example_build/sample_threadx_module_manager/.project @@ -0,0 +1,26 @@ + + + sample_threadx_module_manager + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/ports_module/cortex-r4/ac6/example_build/sample_threadx_module_manager/.settings/language.settings.xml b/ports_module/cortex-r4/ac6/example_build/sample_threadx_module_manager/.settings/language.settings.xml new file mode 100644 index 00000000..d7138707 --- /dev/null +++ b/ports_module/cortex-r4/ac6/example_build/sample_threadx_module_manager/.settings/language.settings.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_module/cortex-r4/ac6/example_build/sample_threadx_module_manager/gic.c b/ports_module/cortex-r4/ac6/example_build/sample_threadx_module_manager/gic.c new file mode 100644 index 00000000..32f21bbe --- /dev/null +++ b/ports_module/cortex-r4/ac6/example_build/sample_threadx_module_manager/gic.c @@ -0,0 +1,239 @@ +/** GIC start **/ +/* ------------------------- Interrupt Number Definition ------------------------ */ + +#include "gic.h" + +#define VE_R4_GIC_DISTRIBUTOR_BASE (0xAE001000UL) /*!< (PL390 GIC Distributor ) Base Address */ +#define VE_R4_GIC_INTERFACE_BASE (0xAE000000UL) /*!< (PL390 GIC CPU Interface) Base Address */ + +#define GICDistributor ((GICDistributor_Type *) VE_R4_GIC_DISTRIBUTOR_BASE ) /*!< GIC Distributor configuration struct */ +#define GICInterface ((GICInterface_Type *) VE_R4_GIC_INTERFACE_BASE ) /*!< GIC Interface configuration struct */ + +/* Globals for use of post-scatterloading code that must access GIC */ +const uint32_t GICDistributor_BASE = VE_R4_GIC_DISTRIBUTOR_BASE; +const uint32_t GICInterface_BASE = VE_R4_GIC_INTERFACE_BASE; + +#if 0 + +void GIC_SetICDICFR (const uint32_t *ICDICFRn) +{ + uint32_t i, num_irq; + + //Get the maximum number of interrupts that the GIC supports + num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1); + + for (i = 0; i < (num_irq/16); i++) + { + GICDistributor->ICDISPR[i] = *ICDICFRn++; + } +} + +uint32_t GIC_DistributorImplementer(void) +{ + return (uint32_t)(GICDistributor->ICDIIDR); +} + +uint32_t GIC_GetTarget(IRQn_Type IRQn) +{ + char* field = (char*)&(GICDistributor->ICDIPTR[IRQn / 4]); + field += IRQn % 4; + return ((uint32_t)*field & 0xf); +} + +IRQn_Type GIC_AcknowledgePending(void) +{ + return (IRQn_Type)(GICInterface->ICCIAR); +} + +uint32_t GIC_GetBinaryPoint(uint32_t binary_point) +{ + return (uint32_t)GICInterface->ICCBPR; +} + +uint32_t GIC_GetIRQStatus(IRQn_Type IRQn) +{ + uint32_t pending, active; + + active = ((GICDistributor->ICDABR[IRQn / 32]) >> (IRQn % 32)) & 0x1; + pending =((GICDistributor->ICDISPR[IRQn / 32]) >> (IRQn % 32)) & 0x1; + + return ((active<<1) | pending); +} + +void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list) +{ + GICDistributor->ICDSGIR = ((filter_list & 0x3) << 24) | ((target_list & 0xff) << 16) | (IRQn & 0xf); +} + +void GIC_EndInterrupt(IRQn_Type IRQn) +{ + GICInterface->ICCEOIR = IRQn; +} + +void GIC_SetPendingIRQ(IRQn_Type IRQn) +{ + GICDistributor->ICDISPR[IRQn / 32] = 1 << (IRQn % 32); +} + +void GIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + GICDistributor->ICDICPR[IRQn / 32] = 1 << (IRQn % 32); +} +#endif + +void GIC_EnableDistributor(void) +{ + GICDistributor->ICDDCR |= 1; //enable distributor +} + +void GIC_DisableDistributor(void) +{ + GICDistributor->ICDDCR &=~1; //disable distributor +} + +void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target) +{ + char* field = (char*)&(GICDistributor->ICDIPTR[IRQn / 4]); + field += IRQn % 4; + *field = (char)cpu_target & 0xf; +} + +void GIC_EnableInterface(void) +{ + GICInterface->ICCICR |= 1; //enable interface +} + +void GIC_DisableInterface(void) +{ + GICInterface->ICCICR &=~1; //disable distributor +} + +void GIC_EnableIRQ(IRQn_Type IRQn) +{ + GICDistributor->ICDISER[IRQn / 32] = 1 << (IRQn % 32); +} + +void GIC_DisableIRQ(IRQn_Type IRQn) +{ + GICDistributor->ICDICER[IRQn / 32] = 1 << (IRQn % 32); +} + +uint32_t GIC_DistributorInfo(void) +{ + return (uint32_t)(GICDistributor->ICDICTR); +} + + +void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model) +{ // Word-size read/writes must be used to access this register + volatile uint32_t * field = &(GICDistributor->ICDICFR[IRQn / 16]); + unsigned bit_shift = (IRQn % 16)<<1; + unsigned int save_word; + + save_word = *field; + save_word &= (~(3 << bit_shift)); + + *field = (save_word | (((edge_level<<1) | model) << bit_shift)); +} + +void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + char* field = (char*)&(GICDistributor->ICDIPR[IRQn / 4]); + field += IRQn % 4; + *field = (char)priority; +} + +uint32_t GIC_GetPriority(IRQn_Type IRQn) +{ + char* field = (char*)&(GICDistributor->ICDIPR[IRQn / 4]); + field += IRQn % 4; + return (uint32_t)*field; +} + +void GIC_InterfacePriorityMask(uint32_t priority) +{ + GICInterface->ICCPMR = priority & 0xff; //set priority mask +} + +void GIC_SetBinaryPoint(uint32_t binary_point) +{ + GICInterface->ICCBPR = binary_point & 0x07; //set binary point +} + +void GIC_DistInit(void) +{ + IRQn_Type i; + uint32_t num_irq = 0; + uint32_t priority_field; + + //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0, + //configuring all of the interrupts as Secure. + + //Disable interrupt forwarding + GIC_DisableDistributor(); + //Get the maximum number of interrupts that the GIC supports + num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1); + + /* Priority level is implementation defined. + To determine the number of priority bits implemented write 0xFF to an ICDIPR + priority field and read back the value stored.*/ + GIC_SetPriority((IRQn_Type)0, 0xff); + priority_field = GIC_GetPriority((IRQn_Type)0); + + for (i = (IRQn_Type)32; i < num_irq; i++) + { + //Disable the SPI interrupt + GIC_DisableIRQ(i); + //Set level-sensitive and 1-N model + GIC_SetLevelModel(i, 0, 1); + //Set priority + GIC_SetPriority(i, priority_field/2); + //Set target list to CPU0 + GIC_SetTarget(i, 1); + } + //Enable distributor + GIC_EnableDistributor(); +} + +void GIC_CPUInterfaceInit(void) +{ + IRQn_Type i; + uint32_t priority_field; + + //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0, + //configuring all of the interrupts as Secure. + + //Disable interrupt forwarding + GIC_DisableInterface(); + + /* Priority level is implementation defined. + To determine the number of priority bits implemented write 0xFF to an ICDIPR + priority field and read back the value stored.*/ + GIC_SetPriority((IRQn_Type)0, 0xff); + priority_field = GIC_GetPriority((IRQn_Type)0); + + //SGI and PPI + for (i = (IRQn_Type)0; i < 32; i++) + { + //Set level-sensitive and 1-N model for PPI + if(i > 15) + GIC_SetLevelModel(i, 0, 1); + //Disable SGI and PPI interrupts + GIC_DisableIRQ(i); + //Set priority + GIC_SetPriority(i, priority_field/2); + } + //Enable interface + GIC_EnableInterface(); + //Set binary point to 0 + GIC_SetBinaryPoint(0); + //Set priority mask + GIC_InterfacePriorityMask(0xff); +} + +void GIC_Enable(void) +{ + GIC_DistInit(); + GIC_CPUInterfaceInit(); //per CPU +} +/** GIC end **/ diff --git a/ports_module/cortex-r4/ac6/example_build/sample_threadx_module_manager/gic.h b/ports_module/cortex-r4/ac6/example_build/sample_threadx_module_manager/gic.h new file mode 100644 index 00000000..7891f74f --- /dev/null +++ b/ports_module/cortex-r4/ac6/example_build/sample_threadx_module_manager/gic.h @@ -0,0 +1,360 @@ +/**************************************************************************//** + * @file gic.h + * @brief Generic Interrupt Controller (GIC) functions + * @version + * @date 29 August 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2011 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#ifndef GIC_H_ +#define GIC_H_ + +#include "stdint.h" + +typedef enum IRQn +{ +/****** SGI Interrupts Numbers ****************************************/ + SGI0_IRQn = 0, + SGI1_IRQn = 1, + SGI2_IRQn = 2, + SGI3_IRQn = 3, + SGI4_IRQn = 4, + SGI5_IRQn = 5, + SGI6_IRQn = 6, + SGI7_IRQn = 7, + SGI8_IRQn = 8, + SGI9_IRQn = 9, + SGI10_IRQn = 10, + SGI11_IRQn = 11, + SGI12_IRQn = 12, + SGI13_IRQn = 13, + SGI14_IRQn = 14, + SGI15_IRQn = 15, + +/****** Cortex-R4 Processor Exceptions Numbers ****************************************/ + PrivTimer_IRQn = 34, /*!< Private Timer Interrupt */ + +/****** Platform Exceptions Numbers ***************************************************/ + Watchdog_IRQn = 32, /*!< SP805 Interrupt */ + Timer0_IRQn = 34, /*!< SP804 Interrupt */ + Timer1_IRQn = 35, /*!< SP804 Interrupt */ + RTClock_IRQn = 36, /*!< PL031 Interrupt */ + UART0_IRQn = 37, /*!< PL011 Interrupt */ + UART1_IRQn = 38, /*!< PL011 Interrupt */ + UART2_IRQn = 39, /*!< PL011 Interrupt */ + UART3_IRQn = 40, /*!< PL011 Interrupt */ + MCI0_IRQn = 41, /*!< PL180 Interrupt (1st) */ + MCI1_IRQn = 42, /*!< PL180 Interrupt (2nd) */ + AACI_IRQn = 43, /*!< PL041 Interrupt */ + Keyboard_IRQn = 44, /*!< PL050 Interrupt */ + Mouse_IRQn = 45, /*!< PL050 Interrupt */ + CLCD_IRQn = 46, /*!< PL111 Interrupt */ + Ethernet_IRQn = 47, /*!< SMSC_91C111 Interrupt */ + VFS2_IRQn = 73, /*!< VFS2 Interrupt */ +} IRQn_Type; + +/* IO definitions (access restrictions to peripheral registers) */ +/** +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD) + */ +typedef struct +{ + __IO uint32_t ICDDCR; + __I uint32_t ICDICTR; + __I uint32_t ICDIIDR; + uint32_t RESERVED0[29]; + __IO uint32_t ICDISR[32]; + __IO uint32_t ICDISER[32]; + __IO uint32_t ICDICER[32]; + __IO uint32_t ICDISPR[32]; + __IO uint32_t ICDICPR[32]; + __I uint32_t ICDABR[32]; + uint32_t RESERVED1[32]; + __IO uint32_t ICDIPR[256]; + __IO uint32_t ICDIPTR[256]; + __IO uint32_t ICDICFR[64]; + uint32_t RESERVED2[128]; + __IO uint32_t ICDSGIR; +} GICDistributor_Type; + +/** \brief Structure type to access the Controller Interface (GICC) + */ +typedef struct +{ + __IO uint32_t ICCICR; // +0x000 - RW - CPU Interface Control Register + __IO uint32_t ICCPMR; // +0x004 - RW - Interrupt Priority Mask Register + __IO uint32_t ICCBPR; // +0x008 - RW - Binary Point Register + __I uint32_t ICCIAR; // +0x00C - RO - Interrupt Acknowledge Register + __IO uint32_t ICCEOIR; // +0x010 - WO - End of Interrupt Register + __I uint32_t ICCRPR; // +0x014 - RO - Running Priority Register + __I uint32_t ICCHPIR; // +0x018 - RO - Highest Pending Interrupt Register + __IO uint32_t ICCABPR; // +0x01C - RW - Aliased Binary Point Register + + uint32_t RESERVED[55]; + + __I uint32_t ICCIIDR; // +0x0FC - RO - CPU Interface Identification Register +} GICInterface_Type; + +/*@} end of GICD */ + +/* ########################## GIC functions #################################### */ +/** \brief Functions that manage interrupts via the GIC. + @{ + */ + +/** \brief Enable DistributorGICInterface->ICCICR |= 1; //enable interface + + Enables the forwarding of pending interrupts to the CPU interfaces. + + */ +void GIC_EnableDistributor(void); + +/** \brief Disable Distributor + + Disables the forwarding of pending interrupts to the CPU interfaces. + + */ +void GIC_DisableDistributor(void); + +/** \brief Provides information about the configuration of the GIC. + Provides information about the configuration of the GIC. + - whether the GIC implements the Security Extensions + - the maximum number of interrupt IDs that the GIC supports + - the number of CPU interfaces implemented + - if the GIC implements the Security Extensions, the maximum number of implemented Lockable Shared Peripheral Interrupts (LSPIs). + + \return Distributor Information. + */ +uint32_t GIC_DistributorInfo(void); + +/** \brief Distributor Implementer Identification Register. + + Distributor Implementer Identification Register + + \return Implementer Information. + */ +uint32_t GIC_DistributorImplementer(void); + +/** \brief Set list of processors that the interrupt is sent to if it is asserted. + + The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC. + This field stores the list of processors that the interrupt is sent to if it is asserted. + + \param [in] IRQn Interrupt number. + \param [in] target CPU target + */ +void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target); + +/** \brief Get list of processors that the interrupt is sent to if it is asserted. + + The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC. + This field stores the list of processors that the interrupt is sent to if it is asserted. + + \param [in] IRQn Interrupt number. + \param [in] target CPU target +*/ +uint32_t GIC_GetTarget(IRQn_Type IRQn); + +/** \brief Enable Interface + + Enables the signalling of interrupts to the target processors. + + */ +void GIC_EnableInterface(void); + +/** \brief Disable Interface + + Disables the signalling of interrupts to the target processors. + + */ +void GIC_DisableInterface(void); + +/** \brief Acknowledge Interrupt + + The function acknowledges the highest priority pending interrupt and returns its IRQ number. + + \return Interrupt number + */ +IRQn_Type GIC_AcknowledgePending(void); + +/** \brief End Interrupt + + The function writes the end of interrupt register, indicating that handling of the interrupt is complete. + + \param [in] IRQn Interrupt number. + */ +void GIC_EndInterrupt(IRQn_Type IRQn); + + +/** \brief Enable Interrupt + + Set-enable bit for each interrupt supported by the GIC. + + \param [in] IRQn External interrupt number. + */ +void GIC_EnableIRQ(IRQn_Type IRQn); + +/** \brief Disable Interrupt + + Clear-enable bit for each interrupt supported by the GIC. + + \param [in] IRQn Number of the external interrupt to disable + */ +void GIC_DisableIRQ(IRQn_Type IRQn); + +/** \brief Set Pending Interrupt + + Set-pending bit for each interrupt supported by the GIC. + + \param [in] IRQn Interrupt number. + */ +void GIC_SetPendingIRQ(IRQn_Type IRQn); + +/** \brief Clear Pending Interrupt + + Clear-pending bit for each interrupt supported by the GIC + + \param [in] IRQn Number of the interrupt for clear pending + */ +void GIC_ClearPendingIRQ(IRQn_Type IRQn); + +/** \brief Int_config field for each interrupt supported by the GIC. + + This field identifies whether the corresponding interrupt is: + (1) edge-triggered or (0) level-sensitive + (1) 1-N model or (0) N-N model + + \param [in] IRQn Interrupt number. + \param [in] edge_level (1) edge-triggered or (0) level-sensitive + \param [in] model (1) 1-N model or (0) N-N model + */ +void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model); + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority); + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + */ +uint32_t GIC_GetPriority(IRQn_Type IRQn); + +/** \brief CPU Interface Priority Mask Register + + The priority mask level for the CPU interface. If the priority of an interrupt is higher than the + value indicated by this field, the interface signals the interrupt to the processor. + + \param [in] Mask. + */ +void GIC_InterfacePriorityMask(uint32_t priority); + +/** \brief Set the binary point. + + Set the point at which the priority value fields split into two parts, the group priority field and the subpriority field. + + \param [in] Mask. + */ +void GIC_SetBinaryPoint(uint32_t binary_point); + +/** \brief Get the binary point. + + Get the point at which the priority value fields split into two parts, the group priority field and the subpriority field. + + \return Binary point. + */ +uint32_t GIC_GetBinaryPoint(uint32_t binary_point); + +/** \brief Get Interrupt state. + + Get the interrupt state, whether pending and/or active + + \return 0 - inactive, 1 - pending, 2 - active, 3 - pending and active + */ +uint32_t GIC_GetIRQStatus(IRQn_Type IRQn); + +/** \brief Send Software Generated interrupt + + Provides an interrupt priority filter. Only interrupts with higher priority than the value in this register can be signalled to the processor. +GIC_InterfacePriorityMask + \param [in] IRQn The Interrupt ID of the SGI. + \param [in] target_list CPUTargetList + \param [in] filter_list TargetListFilter + */ +void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list); + +/** \brief API call to initialise the interrupt distributor + + API call to initialise the interrupt distributor + + */ +void GIC_DistInit(void); + +/** \brief API call to initialise the CPU interface + + API call to initialise the CPU interface + + */ +void GIC_CPUInterfaceInit(void); + +/** \brief API call to set the Interrupt Configuration Registers + + API call to initialise the Interrupt Configuration Registers + + */ +void GIC_SetICDICFR (const uint32_t *ICDICFRn); + +/** \brief API call to Enable the GIC + + API call to Enable the GIC + + */ +void GIC_Enable(void); + +#endif /* GIC_H_ */ diff --git a/ports_module/cortex-r4/ac6/example_build/sample_threadx_module_manager/module_code.c b/ports_module/cortex-r4/ac6/example_build/sample_threadx_module_manager/module_code.c new file mode 100644 index 00000000..6a92a2ac --- /dev/null +++ b/ports_module/cortex-r4/ac6/example_build/sample_threadx_module_manager/module_code.c @@ -0,0 +1,66089 @@ +/* + Input ELF file: sample_threadx_module.axf + Output C Array file: module_code.c +*/ + +unsigned char module_code[] = { + +/* Address Contents */ + +/* 0x00000000 */ 0x00, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00, 0x56, 0x00, 0x00, 0x00, /* SECTION: ER_RW */ +/* 0x00000010 */ 0x78, 0x00, 0x00, 0x00, 0x9A, 0x00, 0x00, 0x00, 0xBC, 0x00, 0x00, 0x00, 0xDE, 0x00, 0x00, 0x00, +/* 0x00000020 */ 0xEF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* 0x00000030 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* 0x00000040 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* 0x00000050 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* 0x00000060 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* 0x00000070 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* 0x00000080 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* 0x00000090 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* 0x000000A0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* 0x000000B0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* 0x000000C0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* 0x000000D0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* 0x000000E0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* 0x000000F0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* 0x00000100 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* 0x00000110 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* 0x00000120 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* 0x00000130 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* 0x00000140 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* 0x00000150 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* 0x00000160 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* 0x00000170 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* 0x00000180 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* 0x00000190 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* 0x000001A0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* 0x000001B0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* 0x000001C0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* 0x000001D0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* 0x000001E0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 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0xF0, +/* 0x00100170 */ 0x03, 0x01, 0xD2, 0xE9, 0x00, 0x03, 0x1B, 0x1A, 0x8B, 0x42, 0x01, 0xD2, 0x00, 0x20, 0x70, 0x47, +/* 0x00100180 */ 0x01, 0x44, 0xC9, 0x1D, 0x21, 0xF0, 0x07, 0x01, 0x11, 0x60, 0x70, 0x47, 0x2D, 0xE9, 0xF3, 0x4D, +/* 0x00100190 */ 0x84, 0xB0, 0x00, 0x27, 0x4F, 0xF4, 0x80, 0x74, 0xBB, 0x46, 0x04, 0xA8, 0x21, 0x46, 0x8D, 0xF8, +/* 0x001001A0 */ 0x00, 0x70, 0xFF, 0xF7, 0xE2, 0xFF, 0x5F, 0xEA, 0x00, 0x08, 0x01, 0xD1, 0x00, 0xF0, 0x77, 0xF8, +/* 0x001001B0 */ 0x21, 0x46, 0x40, 0x46, 0x00, 0xF0, 0x94, 0xE8, 0x06, 0x00, 0x09, 0xD0, 0x45, 0x46, 0xC2, 0x46, +/* 0x001001C0 */ 0x01, 0x20, 0x03, 0x90, 0x16, 0xF8, 0x01, 0x4B, 0x8F, 0xB1, 0x5C, 0x2C, 0x16, 0xD0, 0x1C, 0xE0, +/* 0x001001D0 */ 0x08, 0xF1, 0x08, 0x00, 0x41, 0x46, 0xC8, 0xF8, 0x00, 0x00, 0x00, 0x20, 0xC8, 0xF8, 0x04, 0x00, +/* 0x001001E0 */ 0xD8, 0xF8, 0x00, 0x40, 0x20, 0x70, 0x01, 0x20, 0x06, 0xB0, 0xBD, 0xE8, 0xF0, 0x8D, 0x22, 0x2C, +/* 0x001001F0 */ 0x01, 0xD0, 0x27, 0x2C, 0x0F, 0xD1, 0x27, 0x46, 0xBB, 0x46, 0x2D, 0xE0, 0x30, 0x78, 0x22, 0x28, +/* 0x00100200 */ 0x07, 0xD0, 0x5C, 0x28, 0x05, 0xD0, 0x27, 0x28, 0x03, 0xD0, 0xBC, 0x42, 0x03, 0xD1, 0x00, 0x27, +/* 0x00100210 */ 0x22, 0xE0, 0x76, 0x1C, 0x04, 0x46, 0x4C, 0xB1, 0x2F, 0xB9, 0x20, 0x2C, 0x06, 0xD0, 0xA4, 0xF1, +/* 0x00100220 */ 0x09, 0x00, 0x04, 0x28, 0x02, 0xD9, 0x05, 0xF8, 0x01, 0x4B, 0xCB, 0xE7, 0x55, 0x45, 0x02, 0xD1, +/* 0x00100230 */ 0xBB, 0xF1, 0x00, 0x0F, 0x10, 0xD0, 0x5A, 0x46, 0x51, 0x46, 0x00, 0x20, 0x05, 0xF8, 0x01, 0x0B, +/* 0x00100240 */ 0x68, 0x46, 0xAF, 0xF3, 0x00, 0x80, 0x9D, 0xF8, 0x00, 0x00, 0x78, 0xB1, 0x55, 0x46, 0x03, 0x98, +/* 0x00100250 */ 0x4F, 0xF0, 0x00, 0x0B, 0x40, 0x1C, 0x03, 0x90, 0x00, 0x2C, 0xB3, 0xD1, 0x03, 0x98, 0x81, 0x00, +/* 0x00100260 */ 0x04, 0xA8, 0xFF, 0xF7, 0x82, 0xFF, 0x04, 0x00, 0x02, 0xD0, 0x04, 0xE0, 0xAA, 0x46, 0xEE, 0xE7, +/* 0x00100270 */ 0x00, 0x20, 0x00, 0xF0, 0x14, 0xF8, 0x00, 0x20, 0x42, 0x46, 0xC4, 0xF8, 0x00, 0x80, 0x05, 0xE0, +/* 0x00100280 */ 0x12, 0xF8, 0x01, 0x1B, 0x11, 0xB9, 0x40, 0x1C, 0x44, 0xF8, 0x20, 0x20, 0xAA, 0x42, 0xF7, 0xD3, +/* 0x00100290 */ 0x00, 0x21, 0x44, 0xF8, 0x20, 0x10, 0x21, 0x46, 0xA6, 0xE7, 0x70, 0x47, 0x70, 0x47, 0x01, 0x46, +/* 0x001002A0 */ 0x09, 0x20, 0xAF, 0xF3, 0x00, 0x80, 0x10, 0xB5, 0x00, 0xF0, 0x08, 0xE8, 0x00, 0x28, 0x00, 0xD1, +/* 0x001002B0 */ 0x10, 0xBD, 0xBD, 0xE8, 0x10, 0x40, 0x00, 0xF0, 0x27, 0xB8, 0x00, 0x00, 0x14, 0xD0, 0x4D, 0xE2, +/* 0x001002C0 */ 0x01, 0x20, 0xA0, 0xE1, 0x00, 0x30, 0xA0, 0xE1, 0x0C, 0x00, 0x8D, 0xE5, 0x08, 0x10, 0x8D, 0xE5, +/* 0x001002D0 */ 0x04, 0x20, 0x8D, 0xE5, 0x00, 0x30, 0x8D, 0xE5, 0xFF, 0xFF, 0xFF, 0xEA, 0xFE, 0xFF, 0xFF, 0xEA, +/* 0x001002E0 */ 0x10, 0xD0, 0x4D, 0xE2, 0x01, 0x20, 0xA0, 0xE1, 0x00, 0x30, 0xA0, 0xE1, 0x0C, 0x00, 0x8D, 0xE5, +/* 0x001002F0 */ 0x08, 0x10, 0x8D, 0xE5, 0x00, 0x00, 0xA0, 0xE3, 0x04, 0x20, 0x8D, 0xE5, 0x00, 0x30, 0x8D, 0xE5, +/* 0x00100300 */ 0x10, 0xD0, 0x8D, 0xE2, 0x1E, 0xFF, 0x2F, 0xE1, 0x78, 0x47, 0xC0, 0x46, 0x08, 0xD0, 0x4D, 0xE2, +/* 0x00100310 */ 0x00, 0x10, 0xA0, 0xE1, 0x04, 0x00, 0x8D, 0xE5, 0x00, 0x10, 0x8D, 0xE5, 0xFF, 0xFF, 0xFF, 0xEA, +/* 0x00100320 */ 0xFE, 0xFF, 0xFF, 0xEA, 0x00, 0x48, 0x2D, 0xE9, 0x10, 0xD0, 0x4D, 0xE2, 0x00, 0x10, 0xA0, 0xE1, +/* 0x00100330 */ 0x0C, 0x00, 0x8D, 0xE5, 0x2C, 0x00, 0x00, 0xE3, 0x00, 0x00, 0x40, 0xE3, 0x09, 0x20, 0xA0, 0xE1, +/* 0x00100340 */ 0x00, 0x00, 0x92, 0xE7, 0x0C, 0x20, 0x9D, 0xE5, 0x43, 0x30, 0xA0, 0xE3, 0x00, 0xC0, 0xA0, 0xE3, +/* 0x00100350 */ 0x04, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, 0x00, 0x10, 0x8D, 0xE5, 0x02, 0x10, 0xA0, 0xE1, +/* 0x00100360 */ 0x0C, 0x20, 0xA0, 0xE1, 0x0C, 0x30, 0xA0, 0xE1, 0x04, 0xC0, 0x9D, 0xE5, 0x3C, 0xFF, 0x2F, 0xE1, +/* 0x00100370 */ 0x08, 0x00, 0x8D, 0xE5, 0x08, 0x00, 0x9D, 0xE5, 0x10, 0xD0, 0x8D, 0xE2, 0x00, 0x88, 0xBD, 0xE8, +/* 0x00100380 */ 0x30, 0x48, 0x2D, 0xE9, 0x20, 0xD0, 0x4D, 0xE2, 0x02, 0x30, 0xA0, 0xE1, 0x01, 0xC0, 0xA0, 0xE1, +/* 0x00100390 */ 0x00, 0xE0, 0xA0, 0xE1, 0x1C, 0x00, 0x8D, 0xE5, 0x18, 0x10, 0x8D, 0xE5, 0x14, 0x20, 0x8D, 0xE5, +/* 0x001003A0 */ 0x2C, 0x00, 0x00, 0xE3, 0x00, 0x00, 0x40, 0xE3, 0x09, 0x10, 0xA0, 0xE1, 0x00, 0x00, 0x91, 0xE7, +/* 0x001003B0 */ 0x1C, 0x10, 0x9D, 0xE5, 0x18, 0x20, 0x9D, 0xE5, 0x14, 0x40, 0x9D, 0xE5, 0x01, 0x50, 0xA0, 0xE3, +/* 0x001003C0 */ 0x0C, 0x00, 0x8D, 0xE5, 0x05, 0x00, 0xA0, 0xE1, 0x08, 0x30, 0x8D, 0xE5, 0x04, 0x30, 0xA0, 0xE1, +/* 0x001003D0 */ 0x0C, 0x40, 0x9D, 0xE5, 0x04, 0xE0, 0x8D, 0xE5, 0x00, 0xC0, 0x8D, 0xE5, 0x34, 0xFF, 0x2F, 0xE1, +/* 0x001003E0 */ 0x10, 0x00, 0x8D, 0xE5, 0x10, 0x00, 0x9D, 0xE5, 0x20, 0xD0, 0x8D, 0xE2, 0x30, 0x88, 0xBD, 0xE8, +/* 0x001003F0 */ 0xF0, 0x41, 0x2D, 0xE9, 0x40, 0xD0, 0x4D, 0xE2, 0x5C, 0xC0, 0x9D, 0xE5, 0x58, 0xE0, 0x9D, 0xE5, +/* 0x00100400 */ 0x03, 0x40, 0xA0, 0xE1, 0x02, 0x50, 0xA0, 0xE1, 0x01, 0x60, 0xA0, 0xE1, 0x00, 0x70, 0xA0, 0xE1, +/* 0x00100410 */ 0x3C, 0x00, 0x8D, 0xE5, 0x38, 0x10, 0x8D, 0xE5, 0x34, 0x20, 0x8D, 0xE5, 0x30, 0x30, 0x8D, 0xE5, +/* 0x00100420 */ 0x34, 0x00, 0x9D, 0xE5, 0x1C, 0x00, 0x8D, 0xE5, 0x30, 0x00, 0x9D, 0xE5, 0x20, 0x00, 0x8D, 0xE5, +/* 0x00100430 */ 0x58, 0x00, 0x9D, 0xE5, 0x24, 0x00, 0x8D, 0xE5, 0x5C, 0x00, 0x9D, 0xE5, 0x28, 0x00, 0x8D, 0xE5, +/* 0x00100440 */ 0x2C, 0x00, 0x00, 0xE3, 0x00, 0x00, 0x40, 0xE3, 0x09, 0x10, 0xA0, 0xE1, 0x00, 0x00, 0x91, 0xE7, +/* 0x00100450 */ 0x3C, 0x10, 0x9D, 0xE5, 0x38, 0x20, 0x9D, 0xE5, 0x02, 0x30, 0xA0, 0xE3, 0x1C, 0x80, 0x8D, 0xE2, +/* 0x00100460 */ 0x18, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, 0x08, 0x30, 0xA0, 0xE1, 0x18, 0x80, 0x9D, 0xE5, +/* 0x00100470 */ 0x14, 0x40, 0x8D, 0xE5, 0x10, 0x50, 0x8D, 0xE5, 0x0C, 0x60, 0x8D, 0xE5, 0x08, 0x70, 0x8D, 0xE5, +/* 0x00100480 */ 0x04, 0xC0, 0x8D, 0xE5, 0x00, 0xE0, 0x8D, 0xE5, 0x38, 0xFF, 0x2F, 0xE1, 0x2C, 0x00, 0x8D, 0xE5, +/* 0x00100490 */ 0x2C, 0x00, 0x9D, 0xE5, 0x40, 0xD0, 0x8D, 0xE2, 0xF0, 0x81, 0xBD, 0xE8, 0x00, 0x48, 0x2D, 0xE9, +/* 0x001004A0 */ 0x10, 0xD0, 0x4D, 0xE2, 0x00, 0x10, 0xA0, 0xE1, 0x0C, 0x00, 0x8D, 0xE5, 0x2C, 0x00, 0x00, 0xE3, +/* 0x001004B0 */ 0x00, 0x00, 0x40, 0xE3, 0x09, 0x20, 0xA0, 0xE1, 0x00, 0x00, 0x92, 0xE7, 0x0C, 0x20, 0x9D, 0xE5, +/* 0x001004C0 */ 0x08, 0x30, 0xA0, 0xE3, 0x00, 0xC0, 0xA0, 0xE3, 0x04, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, +/* 0x001004D0 */ 0x00, 0x10, 0x8D, 0xE5, 0x02, 0x10, 0xA0, 0xE1, 0x0C, 0x20, 0xA0, 0xE1, 0x0C, 0x30, 0xA0, 0xE1, +/* 0x001004E0 */ 0x04, 0xC0, 0x9D, 0xE5, 0x3C, 0xFF, 0x2F, 0xE1, 0x08, 0x00, 0x8D, 0xE5, 0x08, 0x00, 0x9D, 0xE5, +/* 0x001004F0 */ 0x10, 0xD0, 0x8D, 0xE2, 0x00, 0x88, 0xBD, 0xE8, 0x70, 0x40, 0x2D, 0xE9, 0x30, 0xD0, 0x4D, 0xE2, +/* 0x00100500 */ 0x03, 0xC0, 0xA0, 0xE1, 0x02, 0xE0, 0xA0, 0xE1, 0x01, 0x40, 0xA0, 0xE1, 0x00, 0x50, 0xA0, 0xE1, +/* 0x00100510 */ 0x2C, 0x00, 0x8D, 0xE5, 0x28, 0x10, 0x8D, 0xE5, 0x24, 0x20, 0x8D, 0xE5, 0x20, 0x30, 0x8D, 0xE5, +/* 0x00100520 */ 0x24, 0x00, 0x9D, 0xE5, 0x14, 0x00, 0x8D, 0xE5, 0x20, 0x00, 0x9D, 0xE5, 0x18, 0x00, 0x8D, 0xE5, +/* 0x00100530 */ 0x2C, 0x00, 0x00, 0xE3, 0x00, 0x00, 0x40, 0xE3, 0x09, 0x10, 0xA0, 0xE1, 0x00, 0x00, 0x91, 0xE7, +/* 0x00100540 */ 0x2C, 0x10, 0x9D, 0xE5, 0x28, 0x20, 0x9D, 0xE5, 0x09, 0x30, 0xA0, 0xE3, 0x14, 0x60, 0x8D, 0xE2, +/* 0x00100550 */ 0x10, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, 0x06, 0x30, 0xA0, 0xE1, 0x10, 0x60, 0x9D, 0xE5, +/* 0x00100560 */ 0x0C, 0xC0, 0x8D, 0xE5, 0x08, 0xE0, 0x8D, 0xE5, 0x04, 0x40, 0x8D, 0xE5, 0x00, 0x50, 0x8D, 0xE5, +/* 0x00100570 */ 0x36, 0xFF, 0x2F, 0xE1, 0x1C, 0x00, 0x8D, 0xE5, 0x1C, 0x00, 0x9D, 0xE5, 0x30, 0xD0, 0x8D, 0xE2, +/* 0x00100580 */ 0x70, 0x80, 0xBD, 0xE8, 0xF0, 0x48, 0x2D, 0xE9, 0x38, 0xD0, 0x4D, 0xE2, 0x50, 0xC0, 0x9D, 0xE5, +/* 0x00100590 */ 0x03, 0xE0, 0xA0, 0xE1, 0x02, 0x40, 0xA0, 0xE1, 0x01, 0x50, 0xA0, 0xE1, 0x00, 0x60, 0xA0, 0xE1, +/* 0x001005A0 */ 0x34, 0x00, 0x8D, 0xE5, 0x30, 0x10, 0x8D, 0xE5, 0x2C, 0x20, 0x8D, 0xE5, 0x28, 0x30, 0x8D, 0xE5, +/* 0x001005B0 */ 0x2C, 0x00, 0x9D, 0xE5, 0x18, 0x00, 0x8D, 0xE5, 0x28, 0x00, 0x9D, 0xE5, 0x1C, 0x00, 0x8D, 0xE5, +/* 0x001005C0 */ 0x50, 0x00, 0x9D, 0xE5, 0x20, 0x00, 0x8D, 0xE5, 0x2C, 0x00, 0x00, 0xE3, 0x00, 0x00, 0x40, 0xE3, +/* 0x001005D0 */ 0x09, 0x10, 0xA0, 0xE1, 0x00, 0x00, 0x91, 0xE7, 0x34, 0x10, 0x9D, 0xE5, 0x30, 0x20, 0x9D, 0xE5, +/* 0x001005E0 */ 0x0A, 0x30, 0xA0, 0xE3, 0x18, 0x70, 0x8D, 0xE2, 0x14, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, +/* 0x001005F0 */ 0x07, 0x30, 0xA0, 0xE1, 0x14, 0x70, 0x9D, 0xE5, 0x10, 0xE0, 0x8D, 0xE5, 0x0C, 0x40, 0x8D, 0xE5, +/* 0x00100600 */ 0x08, 0x50, 0x8D, 0xE5, 0x04, 0x60, 0x8D, 0xE5, 0x00, 0xC0, 0x8D, 0xE5, 0x37, 0xFF, 0x2F, 0xE1, +/* 0x00100610 */ 0x24, 0x00, 0x8D, 0xE5, 0x24, 0x00, 0x9D, 0xE5, 0x38, 0xD0, 0x8D, 0xE2, 0xF0, 0x88, 0xBD, 0xE8, +/* 0x00100620 */ 0x30, 0x48, 0x2D, 0xE9, 0x20, 0xD0, 0x4D, 0xE2, 0x02, 0x30, 0xA0, 0xE1, 0x01, 0xC0, 0xA0, 0xE1, +/* 0x00100630 */ 0x00, 0xE0, 0xA0, 0xE1, 0x1C, 0x00, 0x8D, 0xE5, 0x18, 0x10, 0x8D, 0xE5, 0x14, 0x20, 0x8D, 0xE5, +/* 0x00100640 */ 0x2C, 0x00, 0x00, 0xE3, 0x00, 0x00, 0x40, 0xE3, 0x09, 0x10, 0xA0, 0xE1, 0x00, 0x00, 0x91, 0xE7, +/* 0x00100650 */ 0x1C, 0x10, 0x9D, 0xE5, 0x18, 0x20, 0x9D, 0xE5, 0x14, 0x40, 0x9D, 0xE5, 0x11, 0x50, 0xA0, 0xE3, +/* 0x00100660 */ 0x0C, 0x00, 0x8D, 0xE5, 0x05, 0x00, 0xA0, 0xE1, 0x08, 0x30, 0x8D, 0xE5, 0x04, 0x30, 0xA0, 0xE1, +/* 0x00100670 */ 0x0C, 0x40, 0x9D, 0xE5, 0x04, 0xE0, 0x8D, 0xE5, 0x00, 0xC0, 0x8D, 0xE5, 0x34, 0xFF, 0x2F, 0xE1, +/* 0x00100680 */ 0x10, 0x00, 0x8D, 0xE5, 0x10, 0x00, 0x9D, 0xE5, 0x20, 0xD0, 0x8D, 0xE2, 0x30, 0x88, 0xBD, 0xE8, +/* 0x00100690 */ 0xF0, 0x48, 0x2D, 0xE9, 0x38, 0xD0, 0x4D, 0xE2, 0x50, 0xC0, 0x9D, 0xE5, 0x03, 0xE0, 0xA0, 0xE1, +/* 0x001006A0 */ 0x02, 0x40, 0xA0, 0xE1, 0x01, 0x50, 0xA0, 0xE1, 0x00, 0x60, 0xA0, 0xE1, 0x34, 0x00, 0x8D, 0xE5, +/* 0x001006B0 */ 0x30, 0x10, 0x8D, 0xE5, 0x2C, 0x20, 0x8D, 0xE5, 0x28, 0x30, 0x8D, 0xE5, 0x2C, 0x00, 0x9D, 0xE5, +/* 0x001006C0 */ 0x18, 0x00, 0x8D, 0xE5, 0x28, 0x00, 0x9D, 0xE5, 0x1C, 0x00, 0x8D, 0xE5, 0x50, 0x00, 0x9D, 0xE5, +/* 0x001006D0 */ 0x20, 0x00, 0x8D, 0xE5, 0x2C, 0x00, 0x00, 0xE3, 0x00, 0x00, 0x40, 0xE3, 0x09, 0x10, 0xA0, 0xE1, +/* 0x001006E0 */ 0x00, 0x00, 0x91, 0xE7, 0x34, 0x10, 0x9D, 0xE5, 0x30, 0x20, 0x9D, 0xE5, 0x13, 0x30, 0xA0, 0xE3, +/* 0x001006F0 */ 0x18, 0x70, 0x8D, 0xE2, 0x14, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, 0x07, 0x30, 0xA0, 0xE1, +/* 0x00100700 */ 0x14, 0x70, 0x9D, 0xE5, 0x10, 0xE0, 0x8D, 0xE5, 0x0C, 0x40, 0x8D, 0xE5, 0x08, 0x50, 0x8D, 0xE5, +/* 0x00100710 */ 0x04, 0x60, 0x8D, 0xE5, 0x00, 0xC0, 0x8D, 0xE5, 0x37, 0xFF, 0x2F, 0xE1, 0x24, 0x00, 0x8D, 0xE5, +/* 0x00100720 */ 0x24, 0x00, 0x9D, 0xE5, 0x38, 0xD0, 0x8D, 0xE2, 0xF0, 0x88, 0xBD, 0xE8, 0x30, 0x48, 0x2D, 0xE9, +/* 0x00100730 */ 0x20, 0xD0, 0x4D, 0xE2, 0x02, 0x30, 0xA0, 0xE1, 0x01, 0xC0, 0xA0, 0xE1, 0x00, 0xE0, 0xA0, 0xE1, +/* 0x00100740 */ 0x1C, 0x00, 0x8D, 0xE5, 0x18, 0x10, 0x8D, 0xE5, 0x14, 0x20, 0x8D, 0xE5, 0x2C, 0x00, 0x00, 0xE3, +/* 0x00100750 */ 0x00, 0x00, 0x40, 0xE3, 0x09, 0x10, 0xA0, 0xE1, 0x00, 0x00, 0x91, 0xE7, 0x1C, 0x10, 0x9D, 0xE5, +/* 0x00100760 */ 0x18, 0x20, 0x9D, 0xE5, 0x14, 0x40, 0x9D, 0xE5, 0x17, 0x50, 0xA0, 0xE3, 0x0C, 0x00, 0x8D, 0xE5, +/* 0x00100770 */ 0x05, 0x00, 0xA0, 0xE1, 0x08, 0x30, 0x8D, 0xE5, 0x04, 0x30, 0xA0, 0xE1, 0x0C, 0x40, 0x9D, 0xE5, +/* 0x00100780 */ 0x04, 0xE0, 0x8D, 0xE5, 0x00, 0xC0, 0x8D, 0xE5, 0x34, 0xFF, 0x2F, 0xE1, 0x10, 0x00, 0x8D, 0xE5, +/* 0x00100790 */ 0x10, 0x00, 0x9D, 0xE5, 0x20, 0xD0, 0x8D, 0xE2, 0x30, 0x88, 0xBD, 0xE8, 0x10, 0x40, 0x2D, 0xE9, +/* 0x001007A0 */ 0x18, 0xD0, 0x4D, 0xE2, 0x01, 0x20, 0xA0, 0xE1, 0x00, 0x30, 0xA0, 0xE1, 0x14, 0x00, 0x8D, 0xE5, +/* 0x001007B0 */ 0x10, 0x10, 0x8D, 0xE5, 0x2C, 0x00, 0x00, 0xE3, 0x00, 0x00, 0x40, 0xE3, 0x09, 0x10, 0xA0, 0xE1, +/* 0x001007C0 */ 0x00, 0x00, 0x91, 0xE7, 0x14, 0x10, 0x9D, 0xE5, 0x10, 0xC0, 0x9D, 0xE5, 0x18, 0xE0, 0xA0, 0xE3, +/* 0x001007D0 */ 0x00, 0x40, 0xA0, 0xE3, 0x08, 0x00, 0x8D, 0xE5, 0x0E, 0x00, 0xA0, 0xE1, 0x04, 0x20, 0x8D, 0xE5, +/* 0x001007E0 */ 0x0C, 0x20, 0xA0, 0xE1, 0x00, 0x30, 0x8D, 0xE5, 0x04, 0x30, 0xA0, 0xE1, 0x08, 0xC0, 0x9D, 0xE5, +/* 0x001007F0 */ 0x3C, 0xFF, 0x2F, 0xE1, 0x0C, 0x00, 0x8D, 0xE5, 0x0C, 0x00, 0x9D, 0xE5, 0x18, 0xD0, 0x8D, 0xE2, +/* 0x00100800 */ 0x10, 0x80, 0xBD, 0xE8, 0x70, 0x40, 0x2D, 0xE9, 0x30, 0xD0, 0x4D, 0xE2, 0x03, 0xC0, 0xA0, 0xE1, +/* 0x00100810 */ 0x02, 0xE0, 0xA0, 0xE1, 0x01, 0x40, 0xA0, 0xE1, 0x00, 0x50, 0xA0, 0xE1, 0x2C, 0x00, 0x8D, 0xE5, +/* 0x00100820 */ 0x28, 0x10, 0x8D, 0xE5, 0x24, 0x20, 0x8D, 0xE5, 0x20, 0x30, 0x8D, 0xE5, 0x24, 0x00, 0x9D, 0xE5, +/* 0x00100830 */ 0x14, 0x00, 0x8D, 0xE5, 0x20, 0x00, 0x9D, 0xE5, 0x18, 0x00, 0x8D, 0xE5, 0x2C, 0x00, 0x00, 0xE3, +/* 0x00100840 */ 0x00, 0x00, 0x40, 0xE3, 0x09, 0x10, 0xA0, 0xE1, 0x00, 0x00, 0x91, 0xE7, 0x2C, 0x10, 0x9D, 0xE5, +/* 0x00100850 */ 0x28, 0x20, 0x9D, 0xE5, 0x1A, 0x30, 0xA0, 0xE3, 0x14, 0x60, 0x8D, 0xE2, 0x10, 0x00, 0x8D, 0xE5, +/* 0x00100860 */ 0x03, 0x00, 0xA0, 0xE1, 0x06, 0x30, 0xA0, 0xE1, 0x10, 0x60, 0x9D, 0xE5, 0x0C, 0xC0, 0x8D, 0xE5, +/* 0x00100870 */ 0x08, 0xE0, 0x8D, 0xE5, 0x04, 0x40, 0x8D, 0xE5, 0x00, 0x50, 0x8D, 0xE5, 0x36, 0xFF, 0x2F, 0xE1, +/* 0x00100880 */ 0x1C, 0x00, 0x8D, 0xE5, 0x1C, 0x00, 0x9D, 0xE5, 0x30, 0xD0, 0x8D, 0xE2, 0x70, 0x80, 0xBD, 0xE8, +/* 0x00100890 */ 0x10, 0x40, 0x2D, 0xE9, 0x18, 0xD0, 0x4D, 0xE2, 0x01, 0x20, 0xA0, 0xE1, 0x00, 0x30, 0xA0, 0xE1, +/* 0x001008A0 */ 0x14, 0x00, 0x8D, 0xE5, 0x10, 0x10, 0x8D, 0xE5, 0x2C, 0x00, 0x00, 0xE3, 0x00, 0x00, 0x40, 0xE3, +/* 0x001008B0 */ 0x09, 0x10, 0xA0, 0xE1, 0x00, 0x00, 0x91, 0xE7, 0x14, 0x10, 0x9D, 0xE5, 0x10, 0xC0, 0x9D, 0xE5, +/* 0x001008C0 */ 0x1C, 0xE0, 0xA0, 0xE3, 0x00, 0x40, 0xA0, 0xE3, 0x08, 0x00, 0x8D, 0xE5, 0x0E, 0x00, 0xA0, 0xE1, +/* 0x001008D0 */ 0x04, 0x20, 0x8D, 0xE5, 0x0C, 0x20, 0xA0, 0xE1, 0x00, 0x30, 0x8D, 0xE5, 0x04, 0x30, 0xA0, 0xE1, +/* 0x001008E0 */ 0x08, 0xC0, 0x9D, 0xE5, 0x3C, 0xFF, 0x2F, 0xE1, 0x0C, 0x00, 0x8D, 0xE5, 0x0C, 0x00, 0x9D, 0xE5, +/* 0x001008F0 */ 0x18, 0xD0, 0x8D, 0xE2, 0x10, 0x80, 0xBD, 0xE8, 0x00, 0x48, 0x2D, 0xE9, 0x10, 0xD0, 0x4D, 0xE2, +/* 0x00100900 */ 0x00, 0x10, 0xA0, 0xE1, 0x0C, 0x00, 0x8D, 0xE5, 0x2C, 0x00, 0x00, 0xE3, 0x00, 0x00, 0x40, 0xE3, +/* 0x00100910 */ 0x09, 0x20, 0xA0, 0xE1, 0x00, 0x00, 0x92, 0xE7, 0x0C, 0x20, 0x9D, 0xE5, 0x21, 0x30, 0xA0, 0xE3, +/* 0x00100920 */ 0x00, 0xC0, 0xA0, 0xE3, 0x04, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, 0x00, 0x10, 0x8D, 0xE5, +/* 0x00100930 */ 0x02, 0x10, 0xA0, 0xE1, 0x0C, 0x20, 0xA0, 0xE1, 0x0C, 0x30, 0xA0, 0xE1, 0x04, 0xC0, 0x9D, 0xE5, +/* 0x00100940 */ 0x3C, 0xFF, 0x2F, 0xE1, 0x08, 0x00, 0x8D, 0xE5, 0x08, 0x00, 0x9D, 0xE5, 0x10, 0xD0, 0x8D, 0xE2, +/* 0x00100950 */ 0x00, 0x88, 0xBD, 0xE8, 0xF0, 0x41, 0x2D, 0xE9, 0x40, 0xD0, 0x4D, 0xE2, 0x5C, 0xC0, 0x9D, 0xE5, +/* 0x00100960 */ 0x58, 0xE0, 0x9D, 0xE5, 0x03, 0x40, 0xA0, 0xE1, 0x02, 0x50, 0xA0, 0xE1, 0x01, 0x60, 0xA0, 0xE1, +/* 0x00100970 */ 0x00, 0x70, 0xA0, 0xE1, 0x3C, 0x00, 0x8D, 0xE5, 0x38, 0x10, 0x8D, 0xE5, 0x34, 0x20, 0x8D, 0xE5, +/* 0x00100980 */ 0x30, 0x30, 0x8D, 0xE5, 0x34, 0x00, 0x9D, 0xE5, 0x1C, 0x00, 0x8D, 0xE5, 0x30, 0x00, 0x9D, 0xE5, +/* 0x00100990 */ 0x20, 0x00, 0x8D, 0xE5, 0x58, 0x00, 0x9D, 0xE5, 0x24, 0x00, 0x8D, 0xE5, 0x5C, 0x00, 0x9D, 0xE5, +/* 0x001009A0 */ 0x28, 0x00, 0x8D, 0xE5, 0x2C, 0x00, 0x00, 0xE3, 0x00, 0x00, 0x40, 0xE3, 0x09, 0x10, 0xA0, 0xE1, +/* 0x001009B0 */ 0x00, 0x00, 0x91, 0xE7, 0x3C, 0x10, 0x9D, 0xE5, 0x38, 0x20, 0x9D, 0xE5, 0x22, 0x30, 0xA0, 0xE3, +/* 0x001009C0 */ 0x1C, 0x80, 0x8D, 0xE2, 0x18, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, 0x08, 0x30, 0xA0, 0xE1, +/* 0x001009D0 */ 0x18, 0x80, 0x9D, 0xE5, 0x14, 0x40, 0x8D, 0xE5, 0x10, 0x50, 0x8D, 0xE5, 0x0C, 0x60, 0x8D, 0xE5, +/* 0x001009E0 */ 0x08, 0x70, 0x8D, 0xE5, 0x04, 0xC0, 0x8D, 0xE5, 0x00, 0xE0, 0x8D, 0xE5, 0x38, 0xFF, 0x2F, 0xE1, +/* 0x001009F0 */ 0x2C, 0x00, 0x8D, 0xE5, 0x2C, 0x00, 0x9D, 0xE5, 0x40, 0xD0, 0x8D, 0xE2, 0xF0, 0x81, 0xBD, 0xE8, +/* 0x00100A00 */ 0x30, 0x48, 0x2D, 0xE9, 0x20, 0xD0, 0x4D, 0xE2, 0x02, 0x30, 0xA0, 0xE1, 0x01, 0xC0, 0xA0, 0xE1, +/* 0x00100A10 */ 0x00, 0xE0, 0xA0, 0xE1, 0x1C, 0x00, 0x8D, 0xE5, 0x18, 0x10, 0x8D, 0xE5, 0x14, 0x20, 0x8D, 0xE5, +/* 0x00100A20 */ 0x2C, 0x00, 0x00, 0xE3, 0x00, 0x00, 0x40, 0xE3, 0x09, 0x10, 0xA0, 0xE1, 0x00, 0x00, 0x91, 0xE7, +/* 0x00100A30 */ 0x1C, 0x10, 0x9D, 0xE5, 0x18, 0x20, 0x9D, 0xE5, 0x14, 0x40, 0x9D, 0xE5, 0x2A, 0x50, 0xA0, 0xE3, +/* 0x00100A40 */ 0x0C, 0x00, 0x8D, 0xE5, 0x05, 0x00, 0xA0, 0xE1, 0x08, 0x30, 0x8D, 0xE5, 0x04, 0x30, 0xA0, 0xE1, +/* 0x00100A50 */ 0x0C, 0x40, 0x9D, 0xE5, 0x04, 0xE0, 0x8D, 0xE5, 0x00, 0xC0, 0x8D, 0xE5, 0x34, 0xFF, 0x2F, 0xE1, +/* 0x00100A60 */ 0x10, 0x00, 0x8D, 0xE5, 0x10, 0x00, 0x9D, 0xE5, 0x20, 0xD0, 0x8D, 0xE2, 0x30, 0x88, 0xBD, 0xE8, +/* 0x00100A70 */ 0x30, 0x48, 0x2D, 0xE9, 0x20, 0xD0, 0x4D, 0xE2, 0x02, 0x30, 0xA0, 0xE1, 0x01, 0xC0, 0xA0, 0xE1, +/* 0x00100A80 */ 0x00, 0xE0, 0xA0, 0xE1, 0x1C, 0x00, 0x8D, 0xE5, 0x18, 0x10, 0x8D, 0xE5, 0x14, 0x20, 0x8D, 0xE5, +/* 0x00100A90 */ 0x2C, 0x00, 0x00, 0xE3, 0x00, 0x00, 0x40, 0xE3, 0x09, 0x10, 0xA0, 0xE1, 0x00, 0x00, 0x91, 0xE7, +/* 0x00100AA0 */ 0x1C, 0x10, 0x9D, 0xE5, 0x18, 0x20, 0x9D, 0xE5, 0x14, 0x40, 0x9D, 0xE5, 0x2B, 0x50, 0xA0, 0xE3, +/* 0x00100AB0 */ 0x0C, 0x00, 0x8D, 0xE5, 0x05, 0x00, 0xA0, 0xE1, 0x08, 0x30, 0x8D, 0xE5, 0x04, 0x30, 0xA0, 0xE1, +/* 0x00100AC0 */ 0x0C, 0x40, 0x9D, 0xE5, 0x04, 0xE0, 0x8D, 0xE5, 0x00, 0xC0, 0x8D, 0xE5, 0x34, 0xFF, 0x2F, 0xE1, +/* 0x00100AD0 */ 0x10, 0x00, 0x8D, 0xE5, 0x10, 0x00, 0x9D, 0xE5, 0x20, 0xD0, 0x8D, 0xE2, 0x30, 0x88, 0xBD, 0xE8, +/* 0x00100AE0 */ 0x10, 0x40, 0x2D, 0xE9, 0x18, 0xD0, 0x4D, 0xE2, 0x01, 0x20, 0xA0, 0xE1, 0x00, 0x30, 0xA0, 0xE1, +/* 0x00100AF0 */ 0x14, 0x00, 0x8D, 0xE5, 0x10, 0x10, 0x8D, 0xE5, 0x2C, 0x00, 0x00, 0xE3, 0x00, 0x00, 0x40, 0xE3, +/* 0x00100B00 */ 0x09, 0x10, 0xA0, 0xE1, 0x00, 0x00, 0x91, 0xE7, 0x14, 0x10, 0x9D, 0xE5, 0x10, 0xC0, 0x9D, 0xE5, +/* 0x00100B10 */ 0x2C, 0xE0, 0xA0, 0xE3, 0x00, 0x40, 0xA0, 0xE3, 0x08, 0x00, 0x8D, 0xE5, 0x0E, 0x00, 0xA0, 0xE1, +/* 0x00100B20 */ 0x04, 0x20, 0x8D, 0xE5, 0x0C, 0x20, 0xA0, 0xE1, 0x00, 0x30, 0x8D, 0xE5, 0x04, 0x30, 0xA0, 0xE1, +/* 0x00100B30 */ 0x08, 0xC0, 0x9D, 0xE5, 0x3C, 0xFF, 0x2F, 0xE1, 0x0C, 0x00, 0x8D, 0xE5, 0x0C, 0x00, 0x9D, 0xE5, +/* 0x00100B40 */ 0x18, 0xD0, 0x8D, 0xE2, 0x10, 0x80, 0xBD, 0xE8, 0x70, 0x40, 0x2D, 0xE9, 0x30, 0xD0, 0x4D, 0xE2, +/* 0x00100B50 */ 0x03, 0xC0, 0xA0, 0xE1, 0x02, 0xE0, 0xA0, 0xE1, 0x01, 0x40, 0xA0, 0xE1, 0x00, 0x50, 0xA0, 0xE1, +/* 0x00100B60 */ 0x2C, 0x00, 0x8D, 0xE5, 0x28, 0x10, 0x8D, 0xE5, 0x24, 0x20, 0x8D, 0xE5, 0x20, 0x30, 0x8D, 0xE5, +/* 0x00100B70 */ 0x24, 0x00, 0x9D, 0xE5, 0x14, 0x00, 0x8D, 0xE5, 0x20, 0x00, 0x9D, 0xE5, 0x18, 0x00, 0x8D, 0xE5, +/* 0x00100B80 */ 0x2C, 0x00, 0x00, 0xE3, 0x00, 0x00, 0x40, 0xE3, 0x09, 0x10, 0xA0, 0xE1, 0x00, 0x00, 0x91, 0xE7, +/* 0x00100B90 */ 0x2C, 0x10, 0x9D, 0xE5, 0x28, 0x20, 0x9D, 0xE5, 0x2E, 0x30, 0xA0, 0xE3, 0x14, 0x60, 0x8D, 0xE2, +/* 0x00100BA0 */ 0x10, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, 0x06, 0x30, 0xA0, 0xE1, 0x10, 0x60, 0x9D, 0xE5, +/* 0x00100BB0 */ 0x0C, 0xC0, 0x8D, 0xE5, 0x08, 0xE0, 0x8D, 0xE5, 0x04, 0x40, 0x8D, 0xE5, 0x00, 0x50, 0x8D, 0xE5, +/* 0x00100BC0 */ 0x36, 0xFF, 0x2F, 0xE1, 0x1C, 0x00, 0x8D, 0xE5, 0x1C, 0x00, 0x9D, 0xE5, 0x30, 0xD0, 0x8D, 0xE2, +/* 0x00100BD0 */ 0x70, 0x80, 0xBD, 0xE8, 0x10, 0x40, 0x2D, 0xE9, 0x18, 0xD0, 0x4D, 0xE2, 0x01, 0x20, 0xA0, 0xE1, +/* 0x00100BE0 */ 0x00, 0x30, 0xA0, 0xE1, 0x14, 0x00, 0x8D, 0xE5, 0x10, 0x10, 0x8D, 0xE5, 0x2C, 0x00, 0x00, 0xE3, +/* 0x00100BF0 */ 0x00, 0x00, 0x40, 0xE3, 0x09, 0x10, 0xA0, 0xE1, 0x00, 0x00, 0x91, 0xE7, 0x14, 0x10, 0x9D, 0xE5, +/* 0x00100C00 */ 0x10, 0xC0, 0x9D, 0xE5, 0x30, 0xE0, 0xA0, 0xE3, 0x00, 0x40, 0xA0, 0xE3, 0x08, 0x00, 0x8D, 0xE5, +/* 0x00100C10 */ 0x0E, 0x00, 0xA0, 0xE1, 0x04, 0x20, 0x8D, 0xE5, 0x0C, 0x20, 0xA0, 0xE1, 0x00, 0x30, 0x8D, 0xE5, +/* 0x00100C20 */ 0x04, 0x30, 0xA0, 0xE1, 0x08, 0xC0, 0x9D, 0xE5, 0x3C, 0xFF, 0x2F, 0xE1, 0x0C, 0x00, 0x8D, 0xE5, +/* 0x00100C30 */ 0x0C, 0x00, 0x9D, 0xE5, 0x18, 0xD0, 0x8D, 0xE2, 0x10, 0x80, 0xBD, 0xE8, 0x00, 0x48, 0x2D, 0xE9, +/* 0x00100C40 */ 0x10, 0xD0, 0x4D, 0xE2, 0x00, 0x10, 0xA0, 0xE1, 0x0C, 0x00, 0x8D, 0xE5, 0x2C, 0x00, 0x00, 0xE3, +/* 0x00100C50 */ 0x00, 0x00, 0x40, 0xE3, 0x09, 0x20, 0xA0, 0xE1, 0x00, 0x00, 0x92, 0xE7, 0x0C, 0x20, 0x9D, 0xE5, +/* 0x00100C60 */ 0x35, 0x30, 0xA0, 0xE3, 0x00, 0xC0, 0xA0, 0xE3, 0x04, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, +/* 0x00100C70 */ 0x00, 0x10, 0x8D, 0xE5, 0x02, 0x10, 0xA0, 0xE1, 0x0C, 0x20, 0xA0, 0xE1, 0x0C, 0x30, 0xA0, 0xE1, +/* 0x00100C80 */ 0x04, 0xC0, 0x9D, 0xE5, 0x3C, 0xFF, 0x2F, 0xE1, 0x08, 0x00, 0x8D, 0xE5, 0x08, 0x00, 0x9D, 0xE5, +/* 0x00100C90 */ 0x10, 0xD0, 0x8D, 0xE2, 0x00, 0x88, 0xBD, 0xE8, 0x10, 0x40, 0x2D, 0xE9, 0x18, 0xD0, 0x4D, 0xE2, +/* 0x00100CA0 */ 0x01, 0x20, 0xA0, 0xE1, 0x00, 0x30, 0xA0, 0xE1, 0x14, 0x00, 0x8D, 0xE5, 0x10, 0x10, 0x8D, 0xE5, +/* 0x00100CB0 */ 0x2C, 0x00, 0x00, 0xE3, 0x00, 0x00, 0x40, 0xE3, 0x09, 0x10, 0xA0, 0xE1, 0x00, 0x00, 0x91, 0xE7, +/* 0x00100CC0 */ 0x14, 0x10, 0x9D, 0xE5, 0x10, 0xC0, 0x9D, 0xE5, 0x36, 0xE0, 0xA0, 0xE3, 0x00, 0x40, 0xA0, 0xE3, +/* 0x00100CD0 */ 0x08, 0x00, 0x8D, 0xE5, 0x0E, 0x00, 0xA0, 0xE1, 0x04, 0x20, 0x8D, 0xE5, 0x0C, 0x20, 0xA0, 0xE1, +/* 0x00100CE0 */ 0x00, 0x30, 0x8D, 0xE5, 0x04, 0x30, 0xA0, 0xE1, 0x08, 0xC0, 0x9D, 0xE5, 0x3C, 0xFF, 0x2F, 0xE1, +/* 0x00100CF0 */ 0x0C, 0x00, 0x8D, 0xE5, 0x0C, 0x00, 0x9D, 0xE5, 0x18, 0xD0, 0x8D, 0xE2, 0x10, 0x80, 0xBD, 0xE8, +/* 0x00100D00 */ 0xF0, 0x4D, 0x2D, 0xE9, 0x78, 0xD0, 0x4D, 0xE2, 0xB0, 0xC0, 0x9D, 0xE5, 0xAC, 0xE0, 0x9D, 0xE5, +/* 0x00100D10 */ 0xA8, 0x40, 0x9D, 0xE5, 0xA4, 0x50, 0x9D, 0xE5, 0xA0, 0x60, 0x9D, 0xE5, 0x9C, 0x70, 0x9D, 0xE5, +/* 0x00100D20 */ 0x98, 0x80, 0x9D, 0xE5, 0x03, 0xA0, 0xA0, 0xE1, 0x02, 0xB0, 0xA0, 0xE1, 0x3C, 0x00, 0x8D, 0xE5, +/* 0x00100D30 */ 0x01, 0x00, 0xA0, 0xE1, 0x38, 0x00, 0x8D, 0xE5, 0x3C, 0x00, 0x9D, 0xE5, 0x34, 0x00, 0x8D, 0xE5, +/* 0x00100D40 */ 0x3C, 0x00, 0x9D, 0xE5, 0x74, 0x00, 0x8D, 0xE5, 0x70, 0x10, 0x8D, 0xE5, 0x6C, 0x20, 0x8D, 0xE5, +/* 0x00100D50 */ 0x68, 0x30, 0x8D, 0xE5, 0x6C, 0x10, 0x9D, 0xE5, 0x40, 0x10, 0x8D, 0xE5, 0x68, 0x10, 0x9D, 0xE5, +/* 0x00100D60 */ 0x44, 0x10, 0x8D, 0xE5, 0x98, 0x10, 0x9D, 0xE5, 0x48, 0x10, 0x8D, 0xE5, 0x9C, 0x10, 0x9D, 0xE5, +/* 0x00100D70 */ 0x4C, 0x10, 0x8D, 0xE5, 0xA0, 0x10, 0x9D, 0xE5, 0x50, 0x10, 0x8D, 0xE5, 0xA4, 0x10, 0x9D, 0xE5, +/* 0x00100D80 */ 0x54, 0x10, 0x8D, 0xE5, 0xA8, 0x10, 0x9D, 0xE5, 0x58, 0x10, 0x8D, 0xE5, 0xAC, 0x10, 0x9D, 0xE5, +/* 0x00100D90 */ 0x5C, 0x10, 0x8D, 0xE5, 0xB0, 0x10, 0x9D, 0xE5, 0x60, 0x10, 0x8D, 0xE5, 0x2C, 0x10, 0x00, 0xE3, +/* 0x00100DA0 */ 0x00, 0x10, 0x40, 0xE3, 0x09, 0x20, 0xA0, 0xE1, 0x01, 0x10, 0x92, 0xE7, 0x74, 0x20, 0x9D, 0xE5, +/* 0x00100DB0 */ 0x70, 0x30, 0x9D, 0xE5, 0x37, 0x00, 0xA0, 0xE3, 0x30, 0x00, 0x8D, 0xE5, 0x40, 0x00, 0x8D, 0xE2, +/* 0x00100DC0 */ 0x2C, 0x00, 0x8D, 0xE5, 0x30, 0x00, 0x9D, 0xE5, 0x28, 0x10, 0x8D, 0xE5, 0x02, 0x10, 0xA0, 0xE1, +/* 0x00100DD0 */ 0x03, 0x20, 0xA0, 0xE1, 0x2C, 0x30, 0x9D, 0xE5, 0x24, 0xC0, 0x8D, 0xE5, 0x28, 0xC0, 0x9D, 0xE5, +/* 0x00100DE0 */ 0x20, 0x80, 0x8D, 0xE5, 0x1C, 0xA0, 0x8D, 0xE5, 0x18, 0xB0, 0x8D, 0xE5, 0x14, 0x70, 0x8D, 0xE5, +/* 0x00100DF0 */ 0x10, 0x60, 0x8D, 0xE5, 0x0C, 0xE0, 0x8D, 0xE5, 0x08, 0x40, 0x8D, 0xE5, 0x04, 0x50, 0x8D, 0xE5, +/* 0x00100E00 */ 0x3C, 0xFF, 0x2F, 0xE1, 0x64, 0x00, 0x8D, 0xE5, 0x64, 0x00, 0x9D, 0xE5, 0x78, 0xD0, 0x8D, 0xE2, +/* 0x00100E10 */ 0xF0, 0x8D, 0xBD, 0xE8, 0x00, 0x48, 0x2D, 0xE9, 0x10, 0xD0, 0x4D, 0xE2, 0x00, 0x10, 0xA0, 0xE1, +/* 0x00100E20 */ 0x0C, 0x00, 0x8D, 0xE5, 0x2C, 0x00, 0x00, 0xE3, 0x00, 0x00, 0x40, 0xE3, 0x09, 0x20, 0xA0, 0xE1, +/* 0x00100E30 */ 0x00, 0x00, 0x92, 0xE7, 0x0C, 0x20, 0x9D, 0xE5, 0x42, 0x30, 0xA0, 0xE3, 0x00, 0xC0, 0xA0, 0xE3, +/* 0x00100E40 */ 0x04, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, 0x00, 0x10, 0x8D, 0xE5, 0x02, 0x10, 0xA0, 0xE1, +/* 0x00100E50 */ 0x0C, 0x20, 0xA0, 0xE1, 0x0C, 0x30, 0xA0, 0xE1, 0x04, 0xC0, 0x9D, 0xE5, 0x3C, 0xFF, 0x2F, 0xE1, +/* 0x00100E60 */ 0x08, 0x00, 0x8D, 0xE5, 0x08, 0x00, 0x9D, 0xE5, 0x10, 0xD0, 0x8D, 0xE2, 0x00, 0x88, 0xBD, 0xE8, +/* 0x00100E70 */ 0x00, 0x48, 0x2D, 0xE9, 0x78, 0xD0, 0x4D, 0xE2, 0x00, 0x10, 0xA0, 0xE1, 0x74, 0x00, 0x8D, 0xE5, +/* 0x00100E80 */ 0x28, 0x00, 0x00, 0xE3, 0x00, 0x00, 0x40, 0xE3, 0x09, 0x20, 0xA0, 0xE1, 0x00, 0x00, 0x92, 0xE7, +/* 0x00100E90 */ 0x24, 0x00, 0x90, 0xE5, 0x70, 0x00, 0x8D, 0xE5, 0x1C, 0x10, 0x8D, 0xE5, 0xFF, 0xFF, 0xFF, 0xEA, +/* 0x00100EA0 */ 0x70, 0x00, 0x9D, 0xE5, 0x3C, 0x10, 0x8D, 0xE2, 0x00, 0x20, 0xE0, 0xE3, 0xD3, 0xFE, 0xFF, 0xEB, +/* 0x00100EB0 */ 0x20, 0x00, 0x8D, 0xE5, 0x20, 0x00, 0x9D, 0xE5, 0x00, 0x00, 0x50, 0xE3, 0x01, 0x00, 0x00, 0x0A, +/* 0x00100EC0 */ 0xFF, 0xFF, 0xFF, 0xEA, 0x48, 0x00, 0x00, 0xEA, 0x40, 0x00, 0x9D, 0xE5, 0x38, 0x00, 0x8D, 0xE5, +/* 0x00100ED0 */ 0xFF, 0xFF, 0xFF, 0xEA, 0x38, 0x00, 0x9D, 0xE5, 0x00, 0x00, 0x50, 0xE3, 0x41, 0x00, 0x00, 0x0A, +/* 0x00100EE0 */ 0xFF, 0xFF, 0xFF, 0xEA, 0x38, 0x00, 0x9D, 0xE5, 0x01, 0x00, 0x40, 0xE2, 0x38, 0x00, 0x8D, 0xE5, +/* 0x00100EF0 */ 0x3C, 0x00, 0x9D, 0xE5, 0x04, 0x00, 0x50, 0xE3, 0x18, 0x00, 0x8D, 0xE5, 0x37, 0x00, 0x00, 0x8A, +/* 0x00100F00 */ 0x08, 0x00, 0x8F, 0xE2, 0x18, 0x10, 0x9D, 0xE5, 0x01, 0x21, 0x90, 0xE7, 0x02, 0xF0, 0x80, 0xE0, +/* 0x00100F10 */ 0x14, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x5C, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, +/* 0x00100F20 */ 0xA4, 0x00, 0x00, 0x00, 0x44, 0x00, 0x9D, 0xE5, 0x34, 0x00, 0x8D, 0xE5, 0x34, 0x00, 0x9D, 0xE5, +/* 0x00100F30 */ 0x48, 0x10, 0x9D, 0xE5, 0x14, 0x00, 0x8D, 0xE5, 0x01, 0x00, 0xA0, 0xE1, 0x14, 0x10, 0x9D, 0xE5, +/* 0x00100F40 */ 0x31, 0xFF, 0x2F, 0xE1, 0x26, 0x00, 0x00, 0xEA, 0x44, 0x00, 0x9D, 0xE5, 0x30, 0x00, 0x8D, 0xE5, +/* 0x00100F50 */ 0x30, 0x00, 0x9D, 0xE5, 0x48, 0x10, 0x9D, 0xE5, 0x10, 0x00, 0x8D, 0xE5, 0x01, 0x00, 0xA0, 0xE1, +/* 0x00100F60 */ 0x10, 0x10, 0x9D, 0xE5, 0x31, 0xFF, 0x2F, 0xE1, 0x1D, 0x00, 0x00, 0xEA, 0x44, 0x00, 0x9D, 0xE5, +/* 0x00100F70 */ 0x28, 0x00, 0x8D, 0xE5, 0x28, 0x00, 0x9D, 0xE5, 0x48, 0x10, 0x9D, 0xE5, 0x0C, 0x00, 0x8D, 0xE5, +/* 0x00100F80 */ 0x01, 0x00, 0xA0, 0xE1, 0x0C, 0x10, 0x9D, 0xE5, 0x31, 0xFF, 0x2F, 0xE1, 0x14, 0x00, 0x00, 0xEA, +/* 0x00100F90 */ 0x44, 0x00, 0x9D, 0xE5, 0x2C, 0x00, 0x8D, 0xE5, 0x2C, 0x00, 0x9D, 0xE5, 0x48, 0x10, 0x9D, 0xE5, +/* 0x00100FA0 */ 0x08, 0x00, 0x8D, 0xE5, 0x01, 0x00, 0xA0, 0xE1, 0x08, 0x10, 0x9D, 0xE5, 0x31, 0xFF, 0x2F, 0xE1, +/* 0x00100FB0 */ 0x0B, 0x00, 0x00, 0xEA, 0x44, 0x00, 0x9D, 0xE5, 0x24, 0x00, 0x8D, 0xE5, 0x24, 0x00, 0x9D, 0xE5, +/* 0x00100FC0 */ 0x48, 0x10, 0x9D, 0xE5, 0x4C, 0x20, 0x9D, 0xE5, 0x04, 0x00, 0x8D, 0xE5, 0x01, 0x00, 0xA0, 0xE1, +/* 0x00100FD0 */ 0x02, 0x10, 0xA0, 0xE1, 0x04, 0x20, 0x9D, 0xE5, 0x32, 0xFF, 0x2F, 0xE1, 0x00, 0x00, 0x00, 0xEA, +/* 0x00100FE0 */ 0xFF, 0xFF, 0xFF, 0xEA, 0xBA, 0xFF, 0xFF, 0xEA, 0xAC, 0xFF, 0xFF, 0xEA, 0x78, 0xD0, 0x8D, 0xE2, +/* 0x00100FF0 */ 0x00, 0x88, 0xBD, 0xE8, 0x10, 0x40, 0x2D, 0xE9, 0x18, 0xD0, 0x4D, 0xE2, 0x01, 0x20, 0xA0, 0xE1, +/* 0x00101000 */ 0x00, 0x30, 0xA0, 0xE1, 0x14, 0x00, 0x8D, 0xE5, 0x10, 0x10, 0x8D, 0xE5, 0x2C, 0x00, 0x00, 0xE3, +/* 0x00101010 */ 0x00, 0x00, 0x40, 0xE3, 0x09, 0x10, 0xA0, 0xE1, 0x00, 0x00, 0x91, 0xE7, 0x14, 0x10, 0x9D, 0xE5, +/* 0x00101020 */ 0x10, 0xC0, 0x9D, 0xE5, 0x5F, 0xE0, 0xA0, 0xE3, 0x00, 0x40, 0xA0, 0xE3, 0x08, 0x00, 0x8D, 0xE5, +/* 0x00101030 */ 0x0E, 0x00, 0xA0, 0xE1, 0x04, 0x20, 0x8D, 0xE5, 0x0C, 0x20, 0xA0, 0xE1, 0x00, 0x30, 0x8D, 0xE5, +/* 0x00101040 */ 0x04, 0x30, 0xA0, 0xE1, 0x08, 0xC0, 0x9D, 0xE5, 0x3C, 0xFF, 0x2F, 0xE1, 0x0C, 0x00, 0x8D, 0xE5, +/* 0x00101050 */ 0x0C, 0x00, 0x9D, 0xE5, 0x18, 0xD0, 0x8D, 0xE2, 0x10, 0x80, 0xBD, 0xE8, 0x00, 0x48, 0x2D, 0xE9, +/* 0x00101060 */ 0x28, 0xD0, 0x4D, 0xE2, 0x01, 0x20, 0xA0, 0xE1, 0x00, 0x30, 0xA0, 0xE1, 0x24, 0x00, 0x8D, 0xE5, +/* 0x00101070 */ 0x20, 0x10, 0x8D, 0xE5, 0x20, 0x00, 0x9D, 0xE5, 0x1C, 0x00, 0x90, 0xE5, 0x00, 0x00, 0x50, 0xE3, +/* 0x00101080 */ 0x18, 0x20, 0x8D, 0xE5, 0x14, 0x30, 0x8D, 0xE5, 0x21, 0x00, 0x00, 0x0A, 0xFF, 0xFF, 0xFF, 0xEA, +/* 0x00101090 */ 0x20, 0x04, 0x02, 0xE3, 0x00, 0x00, 0x40, 0xE3, 0x09, 0x10, 0xA0, 0xE1, 0x00, 0x00, 0x81, 0xE0, +/* 0x001010A0 */ 0xFF, 0x23, 0x00, 0xE3, 0x02, 0x20, 0x80, 0xE0, 0x10, 0x10, 0x8D, 0xE5, 0x02, 0x10, 0xA0, 0xE1, +/* 0x001010B0 */ 0x24, 0xFC, 0xFF, 0xEB, 0x20, 0x00, 0x9D, 0xE5, 0x28, 0x10, 0x00, 0xE3, 0x00, 0x10, 0x40, 0xE3, +/* 0x001010C0 */ 0x10, 0x20, 0x9D, 0xE5, 0x01, 0x00, 0x82, 0xE7, 0x20, 0x00, 0x9D, 0xE5, 0x2C, 0x00, 0x90, 0xE5, +/* 0x001010D0 */ 0x2C, 0x10, 0x00, 0xE3, 0x00, 0x10, 0x40, 0xE3, 0x01, 0x00, 0x82, 0xE7, 0xFF, 0xFF, 0xFF, 0xEA, +/* 0x001010E0 */ 0x2C, 0x00, 0x00, 0xE3, 0x00, 0x00, 0x40, 0xE3, 0x09, 0x10, 0xA0, 0xE1, 0x00, 0x00, 0x91, 0xE7, +/* 0x001010F0 */ 0x00, 0x00, 0x50, 0xE3, 0x01, 0x00, 0x00, 0x1A, 0xFF, 0xFF, 0xFF, 0xEA, 0xF7, 0xFF, 0xFF, 0xEA, +/* 0x00101100 */ 0x20, 0x00, 0x9D, 0xE5, 0x20, 0x00, 0x90, 0xE5, 0x41, 0xFF, 0xFF, 0xEB, 0x0C, 0x00, 0x8D, 0xE5, +/* 0x00101110 */ 0xFF, 0xFF, 0xFF, 0xEA, 0x20, 0x00, 0x9D, 0xE5, 0x18, 0x00, 0x90, 0xE5, 0x1C, 0x00, 0x8D, 0xE5, +/* 0x00101120 */ 0x1C, 0x00, 0x9D, 0xE5, 0x00, 0x00, 0x50, 0xE3, 0x09, 0x00, 0x00, 0x0A, 0xFF, 0xFF, 0xFF, 0xEA, +/* 0x00101130 */ 0x1C, 0x00, 0x9D, 0xE5, 0x24, 0x10, 0x9D, 0xE5, 0x00, 0x20, 0xA0, 0xE3, 0x08, 0x00, 0x8D, 0xE5, +/* 0x00101140 */ 0x01, 0x00, 0xA0, 0xE1, 0x02, 0x10, 0xA0, 0xE1, 0x08, 0x20, 0x9D, 0xE5, 0x32, 0xFF, 0x2F, 0xE1, +/* 0x00101150 */ 0xFF, 0xFF, 0xFF, 0xEA, 0x20, 0x00, 0x9D, 0xE5, 0x10, 0x10, 0x90, 0xE5, 0x14, 0x00, 0x90, 0xE5, +/* 0x00101160 */ 0x31, 0xFF, 0x2F, 0xE1, 0x20, 0x00, 0x9D, 0xE5, 0x18, 0x00, 0x90, 0xE5, 0x1C, 0x00, 0x8D, 0xE5, +/* 0x00101170 */ 0x1C, 0x00, 0x9D, 0xE5, 0x00, 0x00, 0x50, 0xE3, 0x09, 0x00, 0x00, 0x0A, 0xFF, 0xFF, 0xFF, 0xEA, +/* 0x00101180 */ 0x1C, 0x00, 0x9D, 0xE5, 0x24, 0x10, 0x9D, 0xE5, 0x01, 0x20, 0xA0, 0xE3, 0x04, 0x00, 0x8D, 0xE5, +/* 0x00101190 */ 0x01, 0x00, 0xA0, 0xE1, 0x02, 0x10, 0xA0, 0xE1, 0x04, 0x20, 0x9D, 0xE5, 0x32, 0xFF, 0x2F, 0xE1, +/* 0x001011A0 */ 0xFF, 0xFF, 0xFF, 0xEA, 0x24, 0x00, 0x9D, 0xE5, 0x02, 0x00, 0x00, 0xEB, 0x00, 0x00, 0x8D, 0xE5, +/* 0x001011B0 */ 0x28, 0xD0, 0x8D, 0xE2, 0x00, 0x88, 0xBD, 0xE8, 0x00, 0x48, 0x2D, 0xE9, 0x10, 0xD0, 0x4D, 0xE2, +/* 0x001011C0 */ 0x00, 0x10, 0xA0, 0xE1, 0x0C, 0x00, 0x8D, 0xE5, 0x2C, 0x00, 0x00, 0xE3, 0x00, 0x00, 0x40, 0xE3, +/* 0x001011D0 */ 0x09, 0x20, 0xA0, 0xE1, 0x00, 0x00, 0x92, 0xE7, 0x0C, 0x20, 0x9D, 0xE5, 0x5C, 0x30, 0xA0, 0xE3, +/* 0x001011E0 */ 0x00, 0xC0, 0xA0, 0xE3, 0x04, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, 0x00, 0x10, 0x8D, 0xE5, +/* 0x001011F0 */ 0x02, 0x10, 0xA0, 0xE1, 0x0C, 0x20, 0xA0, 0xE1, 0x0C, 0x30, 0xA0, 0xE1, 0x04, 0xC0, 0x9D, 0xE5, +/* 0x00101200 */ 0x3C, 0xFF, 0x2F, 0xE1, 0x08, 0x00, 0x8D, 0xE5, 0x08, 0x00, 0x9D, 0xE5, 0x10, 0xD0, 0x8D, 0xE2, +/* 0x00101210 */ 0x00, 0x88, 0xBD, 0xE8, 0xF0, 0x4D, 0x2D, 0xE9, 0x15, 0xDE, 0x4D, 0xE2, 0x00, 0x10, 0xA0, 0xE1, +/* 0x00101220 */ 0x4C, 0x01, 0x8D, 0xE5, 0xF4, 0x03, 0x02, 0xE3, 0x00, 0x00, 0x40, 0xE3, 0x09, 0x20, 0xA0, 0xE1, +/* 0x00101230 */ 0x00, 0x30, 0x82, 0xE0, 0xE8, 0xC0, 0xA0, 0xE3, 0x44, 0x01, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, +/* 0x00101240 */ 0x40, 0x11, 0x8D, 0xE5, 0x0C, 0x10, 0xA0, 0xE1, 0x3C, 0x21, 0x8D, 0xE5, 0x38, 0xC1, 0x8D, 0xE5, +/* 0x00101250 */ 0x67, 0xFF, 0xFF, 0xEB, 0xF8, 0x13, 0x02, 0xE3, 0x00, 0x10, 0x40, 0xE3, 0x3C, 0x21, 0x9D, 0xE5, +/* 0x00101260 */ 0x01, 0x30, 0x82, 0xE0, 0x34, 0x01, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, 0x38, 0x31, 0x9D, 0xE5, +/* 0x00101270 */ 0x30, 0x11, 0x8D, 0xE5, 0x03, 0x10, 0xA0, 0xE1, 0x5D, 0xFF, 0xFF, 0xEB, 0x00, 0x14, 0x02, 0xE3, +/* 0x00101280 */ 0x00, 0x10, 0x40, 0xE3, 0x3C, 0x21, 0x9D, 0xE5, 0x01, 0x30, 0x82, 0xE0, 0x2C, 0x01, 0x8D, 0xE5, +/* 0x00101290 */ 0x03, 0x00, 0xA0, 0xE1, 0x38, 0x31, 0x9D, 0xE5, 0x28, 0x11, 0x8D, 0xE5, 0x03, 0x10, 0xA0, 0xE1, +/* 0x001012A0 */ 0x53, 0xFF, 0xFF, 0xEB, 0x08, 0x14, 0x02, 0xE3, 0x00, 0x10, 0x40, 0xE3, 0x3C, 0x21, 0x9D, 0xE5, +/* 0x001012B0 */ 0x01, 0x30, 0x82, 0xE0, 0x24, 0x01, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, 0x38, 0x31, 0x9D, 0xE5, +/* 0x001012C0 */ 0x20, 0x11, 0x8D, 0xE5, 0x03, 0x10, 0xA0, 0xE1, 0x49, 0xFF, 0xFF, 0xEB, 0x0C, 0x14, 0x02, 0xE3, +/* 0x001012D0 */ 0x00, 0x10, 0x40, 0xE3, 0x3C, 0x21, 0x9D, 0xE5, 0x01, 0x30, 0x82, 0xE0, 0x1C, 0x01, 0x8D, 0xE5, +/* 0x001012E0 */ 0x03, 0x00, 0xA0, 0xE1, 0x38, 0x31, 0x9D, 0xE5, 0x18, 0x11, 0x8D, 0xE5, 0x03, 0x10, 0xA0, 0xE1, +/* 0x001012F0 */ 0x3F, 0xFF, 0xFF, 0xEB, 0x10, 0x14, 0x02, 0xE3, 0x00, 0x10, 0x40, 0xE3, 0x3C, 0x21, 0x9D, 0xE5, +/* 0x00101300 */ 0x01, 0x30, 0x82, 0xE0, 0x14, 0x01, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, 0x38, 0x31, 0x9D, 0xE5, +/* 0x00101310 */ 0x10, 0x11, 0x8D, 0xE5, 0x03, 0x10, 0xA0, 0xE1, 0x35, 0xFF, 0xFF, 0xEB, 0x14, 0x14, 0x02, 0xE3, +/* 0x00101320 */ 0x00, 0x10, 0x40, 0xE3, 0x3C, 0x21, 0x9D, 0xE5, 0x01, 0x30, 0x82, 0xE0, 0x0C, 0x01, 0x8D, 0xE5, +/* 0x00101330 */ 0x03, 0x00, 0xA0, 0xE1, 0x38, 0x31, 0x9D, 0xE5, 0x08, 0x11, 0x8D, 0xE5, 0x03, 0x10, 0xA0, 0xE1, +/* 0x00101340 */ 0x2B, 0xFF, 0xFF, 0xEB, 0x18, 0x14, 0x02, 0xE3, 0x00, 0x10, 0x40, 0xE3, 0x3C, 0x21, 0x9D, 0xE5, +/* 0x00101350 */ 0x01, 0x30, 0x82, 0xE0, 0x04, 0x01, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, 0x38, 0x31, 0x9D, 0xE5, +/* 0x00101360 */ 0x00, 0x11, 0x8D, 0xE5, 0x03, 0x10, 0xA0, 0xE1, 0x21, 0xFF, 0xFF, 0xEB, 0xE4, 0x13, 0x02, 0xE3, +/* 0x00101370 */ 0x00, 0x10, 0x40, 0xE3, 0x3C, 0x21, 0x9D, 0xE5, 0x01, 0x30, 0x82, 0xE0, 0x44, 0xC0, 0xA0, 0xE3, +/* 0x00101380 */ 0xFC, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, 0xF8, 0x10, 0x8D, 0xE5, 0x0C, 0x10, 0xA0, 0xE1, +/* 0x00101390 */ 0xF4, 0xC0, 0x8D, 0xE5, 0x16, 0xFF, 0xFF, 0xEB, 0xEC, 0x13, 0x02, 0xE3, 0x00, 0x10, 0x40, 0xE3, +/* 0x001013A0 */ 0x3C, 0x21, 0x9D, 0xE5, 0x01, 0x30, 0x82, 0xE0, 0x28, 0xC0, 0xA0, 0xE3, 0xF0, 0x00, 0x8D, 0xE5, +/* 0x001013B0 */ 0x03, 0x00, 0xA0, 0xE1, 0xEC, 0x10, 0x8D, 0xE5, 0x0C, 0x10, 0xA0, 0xE1, 0xE8, 0xC0, 0x8D, 0xE5, +/* 0x001013C0 */ 0x0B, 0xFF, 0xFF, 0xEB, 0xE0, 0x13, 0x02, 0xE3, 0x00, 0x10, 0x40, 0xE3, 0x3C, 0x21, 0x9D, 0xE5, +/* 0x001013D0 */ 0x01, 0x30, 0x82, 0xE0, 0x34, 0xC0, 0xA0, 0xE3, 0xE4, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, +/* 0x001013E0 */ 0xE0, 0x10, 0x8D, 0xE5, 0x0C, 0x10, 0xA0, 0xE1, 0xDC, 0xC0, 0x8D, 0xE5, 0x00, 0xFF, 0xFF, 0xEB, +/* 0x001013F0 */ 0xDC, 0x13, 0x02, 0xE3, 0x00, 0x10, 0x40, 0xE3, 0x3C, 0x21, 0x9D, 0xE5, 0x01, 0x30, 0x82, 0xE0, +/* 0x00101400 */ 0x30, 0xC0, 0xA0, 0xE3, 0xD8, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, 0xD4, 0x10, 0x8D, 0xE5, +/* 0x00101410 */ 0x0C, 0x10, 0xA0, 0xE1, 0xD0, 0xC0, 0x8D, 0xE5, 0xF5, 0xFE, 0xFF, 0xEB, 0x34, 0x10, 0x00, 0xE3, +/* 0x00101420 */ 0x00, 0x10, 0x40, 0xE3, 0x3C, 0x21, 0x9D, 0xE5, 0x01, 0x30, 0x82, 0xE0, 0xCC, 0x00, 0x8D, 0xE5, +/* 0x00101430 */ 0x03, 0x00, 0xA0, 0xE1, 0xDC, 0x30, 0x9D, 0xE5, 0xC8, 0x10, 0x8D, 0xE5, 0x03, 0x10, 0xA0, 0xE1, +/* 0x00101440 */ 0xEB, 0xFE, 0xFF, 0xEB, 0x30, 0x10, 0x00, 0xE3, 0x00, 0x10, 0x40, 0xE3, 0x3C, 0x21, 0x9D, 0xE5, +/* 0x00101450 */ 0x01, 0x30, 0x82, 0xE0, 0xC4, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, 0xD0, 0x30, 0x9D, 0xE5, +/* 0x00101460 */ 0xC0, 0x10, 0x8D, 0xE5, 0x03, 0x10, 0xA0, 0xE1, 0xE1, 0xFE, 0xFF, 0xEB, 0x3C, 0x11, 0x9D, 0xE5, +/* 0x00101470 */ 0xC8, 0x20, 0x9D, 0xE5, 0x02, 0x30, 0x91, 0xE7, 0x0D, 0xC0, 0xA0, 0xE1, 0xDC, 0xE0, 0x9D, 0xE5, +/* 0x00101480 */ 0x00, 0xE0, 0x8C, 0xE5, 0x38, 0xC0, 0x00, 0xE3, 0x00, 0xC0, 0x40, 0xE3, 0x0C, 0x20, 0x81, 0xE0, +/* 0x00101490 */ 0x34, 0x1C, 0x00, 0xE3, 0x00, 0x10, 0x40, 0xE3, 0x01, 0x10, 0x8F, 0xE0, 0xA0, 0xC3, 0x02, 0xE3, +/* 0x001014A0 */ 0xBC, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, 0x0C, 0x30, 0xA0, 0xE1, 0x34, 0xFC, 0xFF, 0xEB, +/* 0x001014B0 */ 0x3C, 0x11, 0x9D, 0xE5, 0xC8, 0x20, 0x9D, 0xE5, 0x02, 0x30, 0x91, 0xE7, 0x52, 0xCF, 0x8D, 0xE2, +/* 0x001014C0 */ 0x01, 0xEB, 0xA0, 0xE3, 0x00, 0x40, 0xA0, 0xE3, 0xB8, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, +/* 0x001014D0 */ 0x0C, 0x10, 0xA0, 0xE1, 0x0E, 0x20, 0xA0, 0xE1, 0x04, 0x30, 0xA0, 0xE1, 0xB4, 0xE0, 0x8D, 0xE5, +/* 0x001014E0 */ 0xB0, 0xC0, 0x8D, 0xE5, 0xAC, 0x40, 0x8D, 0xE5, 0x02, 0xFC, 0xFF, 0xEB, 0x3C, 0x11, 0x9D, 0xE5, +/* 0x001014F0 */ 0x44, 0x21, 0x9D, 0xE5, 0x02, 0x30, 0x91, 0xE7, 0x48, 0xC1, 0x9D, 0xE5, 0x0D, 0xE0, 0xA0, 0xE1, +/* 0x00101500 */ 0x38, 0x41, 0x9D, 0xE5, 0x18, 0x40, 0x8E, 0xE5, 0x01, 0x50, 0xA0, 0xE3, 0x14, 0x50, 0x8E, 0xE5, +/* 0x00101510 */ 0xAC, 0x60, 0x9D, 0xE5, 0x10, 0x60, 0x8E, 0xE5, 0x0C, 0x50, 0x8E, 0xE5, 0x08, 0x50, 0x8E, 0xE5, +/* 0x00101520 */ 0xB4, 0x70, 0x9D, 0xE5, 0x04, 0x70, 0x8E, 0xE5, 0x00, 0xC0, 0x8E, 0xE5, 0xAB, 0x1B, 0x00, 0xE3, +/* 0x00101530 */ 0x00, 0x10, 0x40, 0xE3, 0x01, 0x10, 0x8F, 0xE0, 0x24, 0x27, 0x00, 0xE3, 0x00, 0x20, 0x40, 0xE3, +/* 0x00101540 */ 0x02, 0x20, 0x8F, 0xE0, 0xA8, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, 0x06, 0x30, 0xA0, 0xE1, +/* 0x00101550 */ 0xA4, 0x50, 0x8D, 0xE5, 0xE9, 0xFD, 0xFF, 0xEB, 0x3C, 0x11, 0x9D, 0xE5, 0xC8, 0x20, 0x9D, 0xE5, +/* 0x00101560 */ 0x02, 0x30, 0x91, 0xE7, 0xA0, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, 0xB0, 0x10, 0x9D, 0xE5, +/* 0x00101570 */ 0xB4, 0x20, 0x9D, 0xE5, 0xAC, 0x30, 0x9D, 0xE5, 0xDE, 0xFB, 0xFF, 0xEB, 0x3C, 0x11, 0x9D, 0xE5, +/* 0x00101580 */ 0x30, 0x21, 0x9D, 0xE5, 0x02, 0x30, 0x91, 0xE7, 0x48, 0xC1, 0x9D, 0xE5, 0x0D, 0xE0, 0xA0, 0xE1, +/* 0x00101590 */ 0x38, 0x41, 0x9D, 0xE5, 0x18, 0x40, 0x8E, 0xE5, 0xA4, 0x50, 0x9D, 0xE5, 0x14, 0x50, 0x8E, 0xE5, +/* 0x001015A0 */ 0x04, 0x60, 0xA0, 0xE3, 0x10, 0x60, 0x8E, 0xE5, 0x10, 0x70, 0xA0, 0xE3, 0x0C, 0x70, 0x8E, 0xE5, +/* 0x001015B0 */ 0x08, 0x70, 0x8E, 0xE5, 0xB4, 0x80, 0x9D, 0xE5, 0x04, 0x80, 0x8E, 0xE5, 0x00, 0xC0, 0x8E, 0xE5, +/* 0x001015C0 */ 0x27, 0x1B, 0x00, 0xE3, 0x00, 0x10, 0x40, 0xE3, 0x01, 0x10, 0x8F, 0xE0, 0x2C, 0x27, 0x00, 0xE3, +/* 0x001015D0 */ 0x00, 0x20, 0x40, 0xE3, 0x02, 0x20, 0x8F, 0xE0, 0x9C, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, +/* 0x001015E0 */ 0x05, 0x30, 0xA0, 0xE1, 0x98, 0x70, 0x8D, 0xE5, 0x94, 0x60, 0x8D, 0xE5, 0xC3, 0xFD, 0xFF, 0xEB, +/* 0x001015F0 */ 0x3C, 0x11, 0x9D, 0xE5, 0xC8, 0x20, 0x9D, 0xE5, 0x02, 0x30, 0x91, 0xE7, 0x90, 0x00, 0x8D, 0xE5, +/* 0x00101600 */ 0x03, 0x00, 0xA0, 0xE1, 0xB0, 0x10, 0x9D, 0xE5, 0xB4, 0x20, 0x9D, 0xE5, 0xAC, 0x30, 0x9D, 0xE5, +/* 0x00101610 */ 0xB8, 0xFB, 0xFF, 0xEB, 0x3C, 0x11, 0x9D, 0xE5, 0x28, 0x21, 0x9D, 0xE5, 0x02, 0x30, 0x91, 0xE7, +/* 0x00101620 */ 0x48, 0xC1, 0x9D, 0xE5, 0x0D, 0xE0, 0xA0, 0xE1, 0x38, 0x41, 0x9D, 0xE5, 0x18, 0x40, 0x8E, 0xE5, +/* 0x00101630 */ 0xA4, 0x50, 0x9D, 0xE5, 0x14, 0x50, 0x8E, 0xE5, 0x94, 0x60, 0x9D, 0xE5, 0x10, 0x60, 0x8E, 0xE5, +/* 0x00101640 */ 0x98, 0x70, 0x9D, 0xE5, 0x0C, 0x70, 0x8E, 0xE5, 0x08, 0x70, 0x8E, 0xE5, 0xB4, 0x80, 0x9D, 0xE5, +/* 0x00101650 */ 0x04, 0x80, 0x8E, 0xE5, 0x00, 0xC0, 0x8E, 0xE5, 0x9F, 0x1A, 0x00, 0xE3, 0x00, 0x10, 0x40, 0xE3, +/* 0x00101660 */ 0x01, 0x10, 0x8F, 0xE0, 0x20, 0x27, 0x00, 0xE3, 0x00, 0x20, 0x40, 0xE3, 0x02, 0x20, 0x8F, 0xE0, +/* 0x00101670 */ 0x02, 0xC0, 0xA0, 0xE3, 0x8C, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, 0x0C, 0x30, 0xA0, 0xE1, +/* 0x00101680 */ 0x9E, 0xFD, 0xFF, 0xEB, 0x3C, 0x11, 0x9D, 0xE5, 0xC8, 0x20, 0x9D, 0xE5, 0x02, 0x30, 0x91, 0xE7, +/* 0x00101690 */ 0x88, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, 0xB0, 0x10, 0x9D, 0xE5, 0xB4, 0x20, 0x9D, 0xE5, +/* 0x001016A0 */ 0xAC, 0x30, 0x9D, 0xE5, 0x93, 0xFB, 0xFF, 0xEB, 0x3C, 0x11, 0x9D, 0xE5, 0x20, 0x21, 0x9D, 0xE5, +/* 0x001016B0 */ 0x02, 0x30, 0x91, 0xE7, 0x48, 0xC1, 0x9D, 0xE5, 0x0D, 0xE0, 0xA0, 0xE1, 0x38, 0x41, 0x9D, 0xE5, +/* 0x001016C0 */ 0x18, 0x40, 0x8E, 0xE5, 0xA4, 0x50, 0x9D, 0xE5, 0x14, 0x50, 0x8E, 0xE5, 0xAC, 0x60, 0x9D, 0xE5, +/* 0x001016D0 */ 0x10, 0x60, 0x8E, 0xE5, 0x08, 0x70, 0xA0, 0xE3, 0x0C, 0x70, 0x8E, 0xE5, 0x08, 0x70, 0x8E, 0xE5, +/* 0x001016E0 */ 0xB4, 0x80, 0x9D, 0xE5, 0x04, 0x80, 0x8E, 0xE5, 0x00, 0xC0, 0x8E, 0xE5, 0x1B, 0x1A, 0x00, 0xE3, +/* 0x001016F0 */ 0x00, 0x10, 0x40, 0xE3, 0x01, 0x10, 0x8F, 0xE0, 0x30, 0xC7, 0x00, 0xE3, 0x00, 0xC0, 0x40, 0xE3, +/* 0x00101700 */ 0x0C, 0xC0, 0x8F, 0xE0, 0x03, 0xE0, 0xA0, 0xE3, 0x84, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, +/* 0x00101710 */ 0x0C, 0x20, 0xA0, 0xE1, 0x0E, 0x30, 0xA0, 0xE1, 0x80, 0xC0, 0x8D, 0xE5, 0x7C, 0x70, 0x8D, 0xE5, +/* 0x00101720 */ 0x76, 0xFD, 0xFF, 0xEB, 0x3C, 0x11, 0x9D, 0xE5, 0xC8, 0x20, 0x9D, 0xE5, 0x02, 0x30, 0x91, 0xE7, +/* 0x00101730 */ 0x78, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, 0xB0, 0x10, 0x9D, 0xE5, 0xB4, 0x20, 0x9D, 0xE5, +/* 0x00101740 */ 0xAC, 0x30, 0x9D, 0xE5, 0x6B, 0xFB, 0xFF, 0xEB, 0x3C, 0x11, 0x9D, 0xE5, 0x18, 0x21, 0x9D, 0xE5, +/* 0x00101750 */ 0x02, 0x30, 0x91, 0xE7, 0x48, 0xC1, 0x9D, 0xE5, 0x0D, 0xE0, 0xA0, 0xE1, 0x38, 0x41, 0x9D, 0xE5, +/* 0x00101760 */ 0x18, 0x40, 0x8E, 0xE5, 0xA4, 0x50, 0x9D, 0xE5, 0x14, 0x50, 0x8E, 0xE5, 0xAC, 0x60, 0x9D, 0xE5, +/* 0x00101770 */ 0x10, 0x60, 0x8E, 0xE5, 0x7C, 0x70, 0x9D, 0xE5, 0x0C, 0x70, 0x8E, 0xE5, 0x08, 0x70, 0x8E, 0xE5, +/* 0x00101780 */ 0xB4, 0x80, 0x9D, 0xE5, 0x04, 0x80, 0x8E, 0xE5, 0x00, 0xC0, 0x8E, 0xE5, 0x8B, 0x19, 0x00, 0xE3, +/* 0x00101790 */ 0x00, 0x10, 0x40, 0xE3, 0x01, 0x10, 0x8F, 0xE0, 0x74, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, +/* 0x001017A0 */ 0x80, 0x20, 0x9D, 0xE5, 0x94, 0x30, 0x9D, 0xE5, 0x54, 0xFD, 0xFF, 0xEB, 0x3C, 0x11, 0x9D, 0xE5, +/* 0x001017B0 */ 0xC8, 0x20, 0x9D, 0xE5, 0x02, 0x30, 0x91, 0xE7, 0x70, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, +/* 0x001017C0 */ 0xB0, 0x10, 0x9D, 0xE5, 0xB4, 0x20, 0x9D, 0xE5, 0xAC, 0x30, 0x9D, 0xE5, 0x49, 0xFB, 0xFF, 0xEB, +/* 0x001017D0 */ 0x3C, 0x11, 0x9D, 0xE5, 0x10, 0x21, 0x9D, 0xE5, 0x02, 0x30, 0x91, 0xE7, 0x48, 0xC1, 0x9D, 0xE5, +/* 0x001017E0 */ 0x0D, 0xE0, 0xA0, 0xE1, 0x38, 0x41, 0x9D, 0xE5, 0x18, 0x40, 0x8E, 0xE5, 0xA4, 0x50, 0x9D, 0xE5, +/* 0x001017F0 */ 0x14, 0x50, 0x8E, 0xE5, 0xAC, 0x60, 0x9D, 0xE5, 0x10, 0x60, 0x8E, 0xE5, 0x94, 0x70, 0x9D, 0xE5, +/* 0x00101800 */ 0x0C, 0x70, 0x8E, 0xE5, 0x08, 0x70, 0x8E, 0xE5, 0xB4, 0x80, 0x9D, 0xE5, 0x04, 0x80, 0x8E, 0xE5, +/* 0x00101810 */ 0x00, 0xC0, 0x8E, 0xE5, 0x13, 0x19, 0x00, 0xE3, 0x00, 0x10, 0x40, 0xE3, 0x01, 0x10, 0x8F, 0xE0, +/* 0x00101820 */ 0xE0, 0x26, 0x00, 0xE3, 0x00, 0x20, 0x40, 0xE3, 0x02, 0x20, 0x8F, 0xE0, 0x05, 0xC0, 0xA0, 0xE3, +/* 0x00101830 */ 0x6C, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, 0x0C, 0x30, 0xA0, 0xE1, 0x2F, 0xFD, 0xFF, 0xEB, +/* 0x00101840 */ 0x3C, 0x11, 0x9D, 0xE5, 0xC8, 0x20, 0x9D, 0xE5, 0x02, 0x30, 0x91, 0xE7, 0x68, 0x00, 0x8D, 0xE5, +/* 0x00101850 */ 0x03, 0x00, 0xA0, 0xE1, 0xB0, 0x10, 0x9D, 0xE5, 0xB4, 0x20, 0x9D, 0xE5, 0xAC, 0x30, 0x9D, 0xE5, +/* 0x00101860 */ 0x24, 0xFB, 0xFF, 0xEB, 0x3C, 0x11, 0x9D, 0xE5, 0x08, 0x21, 0x9D, 0xE5, 0x02, 0x30, 0x91, 0xE7, +/* 0x00101870 */ 0x48, 0xC1, 0x9D, 0xE5, 0x0D, 0xE0, 0xA0, 0xE1, 0x38, 0x41, 0x9D, 0xE5, 0x18, 0x40, 0x8E, 0xE5, +/* 0x00101880 */ 0xA4, 0x50, 0x9D, 0xE5, 0x14, 0x50, 0x8E, 0xE5, 0xAC, 0x60, 0x9D, 0xE5, 0x10, 0x60, 0x8E, 0xE5, +/* 0x00101890 */ 0x7C, 0x70, 0x9D, 0xE5, 0x0C, 0x70, 0x8E, 0xE5, 0x08, 0x70, 0x8E, 0xE5, 0xB4, 0x80, 0x9D, 0xE5, +/* 0x001018A0 */ 0x04, 0x80, 0x8E, 0xE5, 0x00, 0xC0, 0x8E, 0xE5, 0x8F, 0x18, 0x00, 0xE3, 0x00, 0x10, 0x40, 0xE3, +/* 0x001018B0 */ 0x01, 0x10, 0x8F, 0xE0, 0xDC, 0xC6, 0x00, 0xE3, 0x00, 0xC0, 0x40, 0xE3, 0x0C, 0xC0, 0x8F, 0xE0, +/* 0x001018C0 */ 0x06, 0xE0, 0xA0, 0xE3, 0x64, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, 0x0C, 0x20, 0xA0, 0xE1, +/* 0x001018D0 */ 0x0E, 0x30, 0xA0, 0xE1, 0x60, 0xC0, 0x8D, 0xE5, 0x08, 0xFD, 0xFF, 0xEB, 0x3C, 0x11, 0x9D, 0xE5, +/* 0x001018E0 */ 0xC8, 0x20, 0x9D, 0xE5, 0x02, 0x30, 0x91, 0xE7, 0x5C, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, +/* 0x001018F0 */ 0xB0, 0x10, 0x9D, 0xE5, 0xB4, 0x20, 0x9D, 0xE5, 0xAC, 0x30, 0x9D, 0xE5, 0xFD, 0xFA, 0xFF, 0xEB, +/* 0x00101900 */ 0x3C, 0x11, 0x9D, 0xE5, 0x00, 0x21, 0x9D, 0xE5, 0x02, 0x30, 0x91, 0xE7, 0x48, 0xC1, 0x9D, 0xE5, +/* 0x00101910 */ 0x0D, 0xE0, 0xA0, 0xE1, 0x38, 0x41, 0x9D, 0xE5, 0x18, 0x40, 0x8E, 0xE5, 0xA4, 0x50, 0x9D, 0xE5, +/* 0x00101920 */ 0x14, 0x50, 0x8E, 0xE5, 0xAC, 0x60, 0x9D, 0xE5, 0x10, 0x60, 0x8E, 0xE5, 0x7C, 0x70, 0x9D, 0xE5, +/* 0x00101930 */ 0x0C, 0x70, 0x8E, 0xE5, 0x08, 0x70, 0x8E, 0xE5, 0xB4, 0x80, 0x9D, 0xE5, 0x04, 0x80, 0x8E, 0xE5, +/* 0x00101940 */ 0x00, 0xC0, 0x8E, 0xE5, 0x03, 0x18, 0x00, 0xE3, 0x00, 0x10, 0x40, 0xE3, 0x01, 0x10, 0x8F, 0xE0, +/* 0x00101950 */ 0x07, 0xC0, 0xA0, 0xE3, 0x58, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, 0x60, 0x20, 0x9D, 0xE5, +/* 0x00101960 */ 0x0C, 0x30, 0xA0, 0xE1, 0xE5, 0xFC, 0xFF, 0xEB, 0x3C, 0x11, 0x9D, 0xE5, 0xC8, 0x20, 0x9D, 0xE5, +/* 0x00101970 */ 0x02, 0x30, 0x91, 0xE7, 0x19, 0xCE, 0xA0, 0xE3, 0x54, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, +/* 0x00101980 */ 0xB0, 0x10, 0x9D, 0xE5, 0x0C, 0x20, 0xA0, 0xE1, 0xAC, 0x30, 0x9D, 0xE5, 0x50, 0xC0, 0x8D, 0xE5, +/* 0x00101990 */ 0xD8, 0xFA, 0xFF, 0xEB, 0x3C, 0x11, 0x9D, 0xE5, 0xF8, 0x20, 0x9D, 0xE5, 0x02, 0x30, 0x91, 0xE7, +/* 0x001019A0 */ 0x48, 0xC1, 0x9D, 0xE5, 0x0D, 0xE0, 0xA0, 0xE1, 0xF4, 0x40, 0x9D, 0xE5, 0x04, 0x40, 0x8E, 0xE5, +/* 0x001019B0 */ 0x50, 0x50, 0x9D, 0xE5, 0x00, 0x50, 0x8E, 0xE5, 0x9F, 0x17, 0x00, 0xE3, 0x00, 0x10, 0x40, 0xE3, +/* 0x001019C0 */ 0x01, 0x10, 0x8F, 0xE0, 0x4C, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, 0xA4, 0x20, 0x9D, 0xE5, +/* 0x001019D0 */ 0x0C, 0x30, 0xA0, 0xE1, 0xDE, 0xFB, 0xFF, 0xEB, 0x3C, 0x11, 0x9D, 0xE5, 0xF8, 0x20, 0x9D, 0xE5, +/* 0x001019E0 */ 0x02, 0x30, 0x91, 0xE7, 0xD0, 0x11, 0x00, 0xE3, 0x00, 0x10, 0x40, 0xE3, 0x01, 0x10, 0x8F, 0xE0, +/* 0x001019F0 */ 0x48, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, 0x38, 0xFC, 0xFF, 0xEB, 0x3C, 0x11, 0x9D, 0xE5, +/* 0x00101A00 */ 0xEC, 0x20, 0x9D, 0xE5, 0x02, 0x30, 0x91, 0xE7, 0x5E, 0x17, 0x00, 0xE3, 0x00, 0x10, 0x40, 0xE3, +/* 0x00101A10 */ 0x01, 0x10, 0x8F, 0xE0, 0x44, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, 0xA4, 0x20, 0x9D, 0xE5, +/* 0x00101A20 */ 0xE8, 0x30, 0x9D, 0xE5, 0x47, 0xFC, 0xFF, 0xEB, 0x3C, 0x11, 0x9D, 0xE5, 0xEC, 0x20, 0x9D, 0xE5, +/* 0x00101A30 */ 0x02, 0x30, 0x91, 0xE7, 0xD4, 0x11, 0x00, 0xE3, 0x00, 0x10, 0x40, 0xE3, 0x01, 0x10, 0x8F, 0xE0, +/* 0x00101A40 */ 0x40, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, 0x92, 0xFC, 0xFF, 0xEB, 0x3C, 0x11, 0x9D, 0xE5, +/* 0x00101A50 */ 0xD4, 0x20, 0x9D, 0xE5, 0x02, 0x30, 0x91, 0xE7, 0x21, 0x17, 0x00, 0xE3, 0x00, 0x10, 0x40, 0xE3, +/* 0x00101A60 */ 0x01, 0x10, 0x8F, 0xE0, 0x3C, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, 0xD0, 0x20, 0x9D, 0xE5, +/* 0x00101A70 */ 0xEA, 0xFA, 0xFF, 0xEB, 0x3C, 0x11, 0x9D, 0xE5, 0xD4, 0x20, 0x9D, 0xE5, 0x02, 0x30, 0x91, 0xE7, +/* 0x00101A80 */ 0xE0, 0x10, 0x00, 0xE3, 0x00, 0x10, 0x40, 0xE3, 0x01, 0x10, 0x8F, 0xE0, 0x38, 0x00, 0x8D, 0xE5, +/* 0x00101A90 */ 0x03, 0x00, 0xA0, 0xE1, 0x40, 0xFB, 0xFF, 0xEB, 0x3C, 0x11, 0x9D, 0xE5, 0xE0, 0x20, 0x9D, 0xE5, +/* 0x00101AA0 */ 0x02, 0x30, 0x91, 0xE7, 0xEA, 0x16, 0x00, 0xE3, 0x00, 0x10, 0x40, 0xE3, 0x01, 0x10, 0x8F, 0xE0, +/* 0x00101AB0 */ 0x34, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, 0xAC, 0x20, 0x9D, 0xE5, 0xDC, 0x30, 0x9D, 0xE5, +/* 0x00101AC0 */ 0x4F, 0xFB, 0xFF, 0xEB, 0x3C, 0x11, 0x9D, 0xE5, 0xC8, 0x20, 0x9D, 0xE5, 0x02, 0x30, 0x91, 0xE7, +/* 0x00101AD0 */ 0x64, 0xC0, 0xA0, 0xE3, 0x30, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, 0xB0, 0x10, 0x9D, 0xE5, +/* 0x00101AE0 */ 0x0C, 0x20, 0xA0, 0xE1, 0xAC, 0x30, 0x9D, 0xE5, 0x2C, 0xC0, 0x8D, 0xE5, 0x81, 0xFA, 0xFF, 0xEB, +/* 0x00101AF0 */ 0x3C, 0x11, 0x9D, 0xE5, 0xC0, 0x20, 0x9D, 0xE5, 0x02, 0x30, 0x91, 0xE7, 0x48, 0xC1, 0x9D, 0xE5, +/* 0x00101B00 */ 0x0D, 0xE0, 0xA0, 0xE1, 0xD0, 0x40, 0x9D, 0xE5, 0x04, 0x40, 0x8E, 0xE5, 0x2C, 0x50, 0x9D, 0xE5, +/* 0x00101B10 */ 0x00, 0x50, 0x8E, 0xE5, 0x89, 0x16, 0x00, 0xE3, 0x00, 0x10, 0x40, 0xE3, 0x01, 0x10, 0x8F, 0xE0, +/* 0x00101B20 */ 0x28, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, 0x94, 0x20, 0x9D, 0xE5, 0x0C, 0x30, 0xA0, 0xE1, +/* 0x00101B30 */ 0x2E, 0xFA, 0xFF, 0xEB, 0x3C, 0x11, 0x9D, 0xE5, 0xC0, 0x20, 0x9D, 0xE5, 0x02, 0x30, 0x91, 0xE7, +/* 0x00101B40 */ 0x24, 0x00, 0x8D, 0xE5, 0x03, 0x00, 0xA0, 0xE1, 0xB0, 0x10, 0x9D, 0xE5, 0xAC, 0x20, 0x9D, 0xE5, +/* 0x00101B50 */ 0x0A, 0xFA, 0xFF, 0xEB, 0x48, 0x11, 0x9D, 0xE5, 0x20, 0x00, 0x8D, 0xE5, 0x01, 0x00, 0xA0, 0xE1, +/* 0x00101B60 */ 0x4D, 0xFA, 0xFF, 0xEB, 0x1C, 0x00, 0x8D, 0xE5, 0x15, 0xDE, 0x8D, 0xE2, 0xF0, 0x8D, 0xBD, 0xE8, +/* 0x00101B70 */ 0x08, 0xD0, 0x4D, 0xE2, 0x00, 0x10, 0xA0, 0xE1, 0x04, 0x00, 0x8D, 0xE5, 0x04, 0x00, 0x9D, 0xE5, +/* 0x00101B80 */ 0xDC, 0x23, 0x02, 0xE3, 0x00, 0x20, 0x40, 0xE3, 0x09, 0x30, 0xA0, 0xE1, 0x02, 0x20, 0x93, 0xE7, +/* 0x00101B90 */ 0x02, 0x00, 0x50, 0xE1, 0x00, 0x10, 0x8D, 0xE5, 0x07, 0x00, 0x00, 0x1A, 0xFF, 0xFF, 0xFF, 0xEA, +/* 0x00101BA0 */ 0xD8, 0x03, 0x02, 0xE3, 0x00, 0x00, 0x40, 0xE3, 0x09, 0x10, 0xA0, 0xE1, 0x00, 0x20, 0x91, 0xE7, +/* 0x00101BB0 */ 0x01, 0x20, 0x82, 0xE2, 0x00, 0x20, 0x81, 0xE7, 0xFF, 0xFF, 0xFF, 0xEA, 0x08, 0xD0, 0x8D, 0xE2, +/* 0x00101BC0 */ 0x1E, 0xFF, 0x2F, 0xE1, 0x08, 0xD0, 0x4D, 0xE2, 0x00, 0x10, 0xA0, 0xE1, 0x04, 0x00, 0x8D, 0xE5, +/* 0x00101BD0 */ 0x04, 0x00, 0x9D, 0xE5, 0xE4, 0x23, 0x02, 0xE3, 0x00, 0x20, 0x40, 0xE3, 0x09, 0x30, 0xA0, 0xE1, +/* 0x00101BE0 */ 0x02, 0x20, 0x93, 0xE7, 0x02, 0x00, 0x50, 0xE1, 0x00, 0x10, 0x8D, 0xE5, 0x07, 0x00, 0x00, 0x1A, +/* 0x00101BF0 */ 0xFF, 0xFF, 0xFF, 0xEA, 0xE8, 0x03, 0x02, 0xE3, 0x00, 0x00, 0x40, 0xE3, 0x09, 0x10, 0xA0, 0xE1, +/* 0x00101C00 */ 0x00, 0x20, 0x91, 0xE7, 0x01, 0x20, 0x82, 0xE2, 0x00, 0x20, 0x81, 0xE7, 0xFF, 0xFF, 0xFF, 0xEA, +/* 0x00101C10 */ 0x08, 0xD0, 0x8D, 0xE2, 0x1E, 0xFF, 0x2F, 0xE1, 0x08, 0xD0, 0x4D, 0xE2, 0x00, 0x10, 0xA0, 0xE1, +/* 0x00101C20 */ 0x04, 0x00, 0x8D, 0xE5, 0x04, 0x00, 0x9D, 0xE5, 0xEC, 0x23, 0x02, 0xE3, 0x00, 0x20, 0x40, 0xE3, +/* 0x00101C30 */ 0x09, 0x30, 0xA0, 0xE1, 0x02, 0x20, 0x93, 0xE7, 0x02, 0x00, 0x50, 0xE1, 0x00, 0x10, 0x8D, 0xE5, +/* 0x00101C40 */ 0x07, 0x00, 0x00, 0x1A, 0xFF, 0xFF, 0xFF, 0xEA, 0xF0, 0x03, 0x02, 0xE3, 0x00, 0x00, 0x40, 0xE3, +/* 0x00101C50 */ 0x09, 0x10, 0xA0, 0xE1, 0x00, 0x20, 0x91, 0xE7, 0x01, 0x20, 0x82, 0xE2, 0x00, 0x20, 0x81, 0xE7, +/* 0x00101C60 */ 0xFF, 0xFF, 0xFF, 0xEA, 0x08, 0xD0, 0x8D, 0xE2, 0x1E, 0xFF, 0x2F, 0xE1, 0x00, 0x48, 0x2D, 0xE9, +/* 0x00101C70 */ 0x18, 0xD0, 0x4D, 0xE2, 0x00, 0x10, 0xA0, 0xE1, 0x14, 0x00, 0x8D, 0xE5, 0x00, 0x00, 0x05, 0xE3, +/* 0x00101C80 */ 0x02, 0x08, 0x40, 0xE3, 0xEF, 0x2E, 0x0B, 0xE3, 0xAD, 0x2E, 0x4D, 0xE3, 0x00, 0x20, 0x80, 0xE5, +/* 0x00101C90 */ 0x0C, 0x10, 0x8D, 0xE5, 0xFF, 0xFF, 0xFF, 0xEA, 0x04, 0x00, 0x00, 0xE3, 0x00, 0x00, 0x40, 0xE3, +/* 0x00101CA0 */ 0x09, 0x10, 0xA0, 0xE1, 0x00, 0x20, 0x91, 0xE7, 0x01, 0x20, 0x82, 0xE2, 0x00, 0x20, 0x81, 0xE7, +/* 0x00101CB0 */ 0x0A, 0x00, 0xA0, 0xE3, 0x08, 0x10, 0x8D, 0xE5, 0x99, 0xF9, 0xFF, 0xEB, 0xDC, 0x13, 0x02, 0xE3, +/* 0x00101CC0 */ 0x00, 0x10, 0x40, 0xE3, 0x08, 0x20, 0x9D, 0xE5, 0x01, 0x10, 0x92, 0xE7, 0x01, 0xE0, 0xA0, 0xE3, +/* 0x00101CD0 */ 0x00, 0x20, 0xA0, 0xE3, 0x04, 0x00, 0x8D, 0xE5, 0x01, 0x00, 0xA0, 0xE1, 0x0E, 0x10, 0xA0, 0xE1, +/* 0x00101CE0 */ 0x91, 0xFA, 0xFF, 0xEB, 0x10, 0x00, 0x8D, 0xE5, 0x10, 0x00, 0x9D, 0xE5, 0x00, 0x00, 0x50, 0xE3, +/* 0x00101CF0 */ 0x01, 0x00, 0x00, 0x0A, 0xFF, 0xFF, 0xFF, 0xEA, 0x00, 0x00, 0x00, 0xEA, 0xE5, 0xFF, 0xFF, 0xEA, +/* 0x00101D00 */ 0x18, 0xD0, 0x8D, 0xE2, 0x00, 0x88, 0xBD, 0xE8, 0x00, 0x48, 0x2D, 0xE9, 0x10, 0xD0, 0x4D, 0xE2, +/* 0x00101D10 */ 0x00, 0x10, 0xA0, 0xE1, 0x0C, 0x00, 0x8D, 0xE5, 0x04, 0x10, 0x8D, 0xE5, 0xFF, 0xFF, 0xFF, 0xEA, +/* 0x00101D20 */ 0x08, 0x00, 0x00, 0xE3, 0x00, 0x00, 0x40, 0xE3, 0x09, 0x10, 0xA0, 0xE1, 0x00, 0x20, 0x91, 0xE7, +/* 0x00101D30 */ 0x01, 0x20, 0x82, 0xE2, 0x00, 0x20, 0x81, 0xE7, 0xE4, 0x03, 0x02, 0xE3, 0x00, 0x00, 0x40, 0xE3, +/* 0x00101D40 */ 0x00, 0x00, 0x91, 0xE7, 0xFC, 0x23, 0x02, 0xE3, 0x00, 0x20, 0x40, 0xE3, 0x02, 0x10, 0x81, 0xE0, +/* 0x00101D50 */ 0x00, 0x20, 0xE0, 0xE3, 0x45, 0xFB, 0xFF, 0xEB, 0x08, 0x00, 0x8D, 0xE5, 0x08, 0x00, 0x9D, 0xE5, +/* 0x00101D60 */ 0x00, 0x00, 0x50, 0xE3, 0x01, 0x00, 0x00, 0x0A, 0xFF, 0xFF, 0xFF, 0xEA, 0x06, 0x00, 0x00, 0xEA, +/* 0x00101D70 */ 0xFC, 0x03, 0x02, 0xE3, 0x00, 0x00, 0x40, 0xE3, 0x09, 0x10, 0xA0, 0xE1, 0x00, 0x20, 0x91, 0xE7, +/* 0x00101D80 */ 0x01, 0x20, 0x82, 0xE2, 0x00, 0x20, 0x81, 0xE7, 0xE4, 0xFF, 0xFF, 0xEA, 0x10, 0xD0, 0x8D, 0xE2, +/* 0x00101D90 */ 0x00, 0x88, 0xBD, 0xE8, 0x00, 0x48, 0x2D, 0xE9, 0x10, 0xD0, 0x4D, 0xE2, 0x00, 0x10, 0xA0, 0xE1, +/* 0x00101DA0 */ 0x0C, 0x00, 0x8D, 0xE5, 0x00, 0x10, 0x8D, 0xE5, 0xFF, 0xFF, 0xFF, 0xEA, 0x0C, 0x00, 0x00, 0xE3, +/* 0x00101DB0 */ 0x00, 0x00, 0x40, 0xE3, 0x09, 0x10, 0xA0, 0xE1, 0x00, 0x20, 0x91, 0xE7, 0x01, 0x20, 0x82, 0xE2, +/* 0x00101DC0 */ 0x00, 0x20, 0x81, 0xE7, 0xE4, 0x03, 0x02, 0xE3, 0x00, 0x00, 0x40, 0xE3, 0x00, 0x00, 0x91, 0xE7, +/* 0x00101DD0 */ 0x08, 0x10, 0x8D, 0xE2, 0x00, 0x20, 0xE0, 0xE3, 0x08, 0xFB, 0xFF, 0xEB, 0x04, 0x00, 0x8D, 0xE5, +/* 0x00101DE0 */ 0x04, 0x00, 0x9D, 0xE5, 0x00, 0x00, 0x50, 0xE3, 0x08, 0x00, 0x00, 0x1A, 0xFF, 0xFF, 0xFF, 0xEA, +/* 0x00101DF0 */ 0x08, 0x00, 0x9D, 0xE5, 0x04, 0x14, 0x02, 0xE3, 0x00, 0x10, 0x40, 0xE3, 0x09, 0x20, 0xA0, 0xE1, +/* 0x00101E00 */ 0x01, 0x10, 0x92, 0xE7, 0x01, 0x00, 0x50, 0xE1, 0x01, 0x00, 0x00, 0x0A, 0xFF, 0xFF, 0xFF, 0xEA, +/* 0x00101E10 */ 0x06, 0x00, 0x00, 0xEA, 0x04, 0x04, 0x02, 0xE3, 0x00, 0x00, 0x40, 0xE3, 0x09, 0x10, 0xA0, 0xE1, +/* 0x00101E20 */ 0x00, 0x20, 0x91, 0xE7, 0x01, 0x20, 0x82, 0xE2, 0x00, 0x20, 0x81, 0xE7, 0xDE, 0xFF, 0xFF, 0xEA, +/* 0x00101E30 */ 0x10, 0xD0, 0x8D, 0xE2, 0x00, 0x88, 0xBD, 0xE8, 0x00, 0x48, 0x2D, 0xE9, 0x10, 0xD0, 0x4D, 0xE2, +/* 0x00101E40 */ 0x00, 0x10, 0xA0, 0xE1, 0x0C, 0x00, 0x8D, 0xE5, 0x04, 0x10, 0x8D, 0xE5, 0xFF, 0xFF, 0xFF, 0xEA, +/* 0x00101E50 */ 0x0C, 0x00, 0x9D, 0xE5, 0x03, 0x00, 0x50, 0xE3, 0x07, 0x00, 0x00, 0x1A, 0xFF, 0xFF, 0xFF, 0xEA, +/* 0x00101E60 */ 0x10, 0x00, 0x00, 0xE3, 0x00, 0x00, 0x40, 0xE3, 0x09, 0x10, 0xA0, 0xE1, 0x00, 0x20, 0x91, 0xE7, +/* 0x00101E70 */ 0x01, 0x20, 0x82, 0xE2, 0x00, 0x20, 0x81, 0xE7, 0x06, 0x00, 0x00, 0xEA, 0x14, 0x00, 0x00, 0xE3, +/* 0x00101E80 */ 0x00, 0x00, 0x40, 0xE3, 0x09, 0x10, 0xA0, 0xE1, 0x00, 0x20, 0x91, 0xE7, 0x01, 0x20, 0x82, 0xE2, +/* 0x00101E90 */ 0x00, 0x20, 0x81, 0xE7, 0xFF, 0xFF, 0xFF, 0xEA, 0xEC, 0x03, 0x02, 0xE3, 0x00, 0x00, 0x40, 0xE3, +/* 0x00101EA0 */ 0x09, 0x10, 0xA0, 0xE1, 0x00, 0x00, 0x91, 0xE7, 0x00, 0x10, 0xE0, 0xE3, 0x48, 0xFB, 0xFF, 0xEB, +/* 0x00101EB0 */ 0x08, 0x00, 0x8D, 0xE5, 0x08, 0x00, 0x9D, 0xE5, 0x00, 0x00, 0x50, 0xE3, 0x01, 0x00, 0x00, 0x0A, +/* 0x00101EC0 */ 0xFF, 0xFF, 0xFF, 0xEA, 0x0F, 0x00, 0x00, 0xEA, 0x02, 0x00, 0xA0, 0xE3, 0x14, 0xF9, 0xFF, 0xEB, +/* 0x00101ED0 */ 0xEC, 0xE3, 0x02, 0xE3, 0x00, 0xE0, 0x40, 0xE3, 0x09, 0x10, 0xA0, 0xE1, 0x0E, 0x10, 0x91, 0xE7, +/* 0x00101EE0 */ 0x00, 0x00, 0x8D, 0xE5, 0x01, 0x00, 0xA0, 0xE1, 0x53, 0xFB, 0xFF, 0xEB, 0x08, 0x00, 0x8D, 0xE5, +/* 0x00101EF0 */ 0x08, 0x00, 0x9D, 0xE5, 0x00, 0x00, 0x50, 0xE3, 0x01, 0x00, 0x00, 0x0A, 0xFF, 0xFF, 0xFF, 0xEA, +/* 0x00101F00 */ 0x00, 0x00, 0x00, 0xEA, 0xD1, 0xFF, 0xFF, 0xEA, 0x10, 0xD0, 0x8D, 0xE2, 0x00, 0x88, 0xBD, 0xE8, +/* 0x00101F10 */ 0x00, 0x48, 0x2D, 0xE9, 0x18, 0xD0, 0x4D, 0xE2, 0x00, 0x10, 0xA0, 0xE1, 0x14, 0x00, 0x8D, 0xE5, +/* 0x00101F20 */ 0x08, 0x10, 0x8D, 0xE5, 0xFF, 0xFF, 0xFF, 0xEA, 0x18, 0x00, 0x00, 0xE3, 0x00, 0x00, 0x40, 0xE3, +/* 0x00101F30 */ 0x09, 0x10, 0xA0, 0xE1, 0x00, 0x20, 0x91, 0xE7, 0x01, 0x20, 0x82, 0xE2, 0x00, 0x20, 0x81, 0xE7, +/* 0x00101F40 */ 0xDC, 0x03, 0x02, 0xE3, 0x00, 0x00, 0x40, 0xE3, 0x00, 0x00, 0x91, 0xE7, 0x0D, 0x10, 0xA0, 0xE1, +/* 0x00101F50 */ 0x00, 0x20, 0xE0, 0xE3, 0x00, 0x20, 0x81, 0xE5, 0x01, 0x10, 0xA0, 0xE3, 0x0C, 0x30, 0x8D, 0xE2, +/* 0x00101F60 */ 0x04, 0x10, 0x8D, 0xE5, 0x04, 0x20, 0x9D, 0xE5, 0xC8, 0xF9, 0xFF, 0xEB, 0x10, 0x00, 0x8D, 0xE5, +/* 0x00101F70 */ 0x10, 0x00, 0x9D, 0xE5, 0x00, 0x00, 0x50, 0xE3, 0x04, 0x00, 0x00, 0x1A, 0xFF, 0xFF, 0xFF, 0xEA, +/* 0x00101F80 */ 0x0C, 0x00, 0x9D, 0xE5, 0x01, 0x00, 0x50, 0xE3, 0x01, 0x00, 0x00, 0x0A, 0xFF, 0xFF, 0xFF, 0xEA, +/* 0x00101F90 */ 0x00, 0x00, 0x00, 0xEA, 0xE3, 0xFF, 0xFF, 0xEA, 0x18, 0xD0, 0x8D, 0xE2, 0x00, 0x88, 0xBD, 0xE8, +/* 0x00101FA0 */ 0x00, 0x48, 0x2D, 0xE9, 0x10, 0xD0, 0x4D, 0xE2, 0x00, 0x10, 0xA0, 0xE1, 0x0C, 0x00, 0x8D, 0xE5, +/* 0x00101FB0 */ 0x04, 0x10, 0x8D, 0xE5, 0xFF, 0xFF, 0xFF, 0xEA, 0x0C, 0x00, 0x9D, 0xE5, 0x06, 0x00, 0x50, 0xE3, +/* 0x00101FC0 */ 0x07, 0x00, 0x00, 0x1A, 0xFF, 0xFF, 0xFF, 0xEA, 0x1C, 0x00, 0x00, 0xE3, 0x00, 0x00, 0x40, 0xE3, +/* 0x00101FD0 */ 0x09, 0x10, 0xA0, 0xE1, 0x00, 0x20, 0x91, 0xE7, 0x01, 0x20, 0x82, 0xE2, 0x00, 0x20, 0x81, 0xE7, +/* 0x00101FE0 */ 0x06, 0x00, 0x00, 0xEA, 0x20, 0x00, 0x00, 0xE3, 0x00, 0x00, 0x40, 0xE3, 0x09, 0x10, 0xA0, 0xE1, +/* 0x00101FF0 */ 0x00, 0x20, 0x91, 0xE7, 0x01, 0x20, 0x82, 0xE2, 0x00, 0x20, 0x81, 0xE7, 0xFF, 0xFF, 0xFF, 0xEA, +/* 0x00102000 */ 0xE0, 0x03, 0x02, 0xE3, 0x00, 0x00, 0x40, 0xE3, 0x09, 0x10, 0xA0, 0xE1, 0x00, 0x00, 0x91, 0xE7, +/* 0x00102010 */ 0x00, 0x10, 0xE0, 0xE3, 0x1D, 0xFA, 0xFF, 0xEB, 0x08, 0x00, 0x8D, 0xE5, 0x08, 0x00, 0x9D, 0xE5, +/* 0x00102020 */ 0x00, 0x00, 0x50, 0xE3, 0x01, 0x00, 0x00, 0x0A, 0xFF, 0xFF, 0xFF, 0xEA, 0x26, 0x00, 0x00, 0xEA, +/* 0x00102030 */ 0xE0, 0x03, 0x02, 0xE3, 0x00, 0x00, 0x40, 0xE3, 0x09, 0x10, 0xA0, 0xE1, 0x00, 0x00, 0x91, 0xE7, +/* 0x00102040 */ 0x00, 0x10, 0xE0, 0xE3, 0x11, 0xFA, 0xFF, 0xEB, 0x08, 0x00, 0x8D, 0xE5, 0x08, 0x00, 0x9D, 0xE5, +/* 0x00102050 */ 0x00, 0x00, 0x50, 0xE3, 0x01, 0x00, 0x00, 0x0A, 0xFF, 0xFF, 0xFF, 0xEA, 0x1A, 0x00, 0x00, 0xEA, +/* 0x00102060 */ 0x02, 0x00, 0xA0, 0xE3, 0xAE, 0xF8, 0xFF, 0xEB, 0xE0, 0xE3, 0x02, 0xE3, 0x00, 0xE0, 0x40, 0xE3, +/* 0x00102070 */ 0x09, 0x10, 0xA0, 0xE1, 0x0E, 0x10, 0x91, 0xE7, 0x00, 0x00, 0x8D, 0xE5, 0x01, 0x00, 0xA0, 0xE1, +/* 0x00102080 */ 0x1C, 0xFA, 0xFF, 0xEB, 0x08, 0x00, 0x8D, 0xE5, 0x08, 0x00, 0x9D, 0xE5, 0x00, 0x00, 0x50, 0xE3, +/* 0x00102090 */ 0x01, 0x00, 0x00, 0x0A, 0xFF, 0xFF, 0xFF, 0xEA, 0x0B, 0x00, 0x00, 0xEA, 0xE0, 0x03, 0x02, 0xE3, +/* 0x001020A0 */ 0x00, 0x00, 0x40, 0xE3, 0x09, 0x10, 0xA0, 0xE1, 0x00, 0x00, 0x91, 0xE7, 0x11, 0xFA, 0xFF, 0xEB, +/* 0x001020B0 */ 0x08, 0x00, 0x8D, 0xE5, 0x08, 0x00, 0x9D, 0xE5, 0x00, 0x00, 0x50, 0xE3, 0x01, 0x00, 0x00, 0x0A, +/* 0x001020C0 */ 0xFF, 0xFF, 0xFF, 0xEA, 0x00, 0x00, 0x00, 0xEA, 0xBA, 0xFF, 0xFF, 0xEA, 0x10, 0xD0, 0x8D, 0xE2, +/* 0x001020D0 */ 0x00, 0x88, 0xBD, 0xE8, 0x6D, 0x6F, 0x64, 0x75, 0x6C, 0x65, 0x20, 0x62, 0x79, 0x74, 0x65, 0x20, +/* 0x001020E0 */ 0x70, 0x6F, 0x6F, 0x6C, 0x20, 0x30, 0x00, 0x6D, 0x6F, 0x64, 0x75, 0x6C, 0x65, 0x20, 0x74, 0x68, +/* 0x001020F0 */ 0x72, 0x65, 0x61, 0x64, 0x20, 0x30, 0x00, 0x6D, 0x6F, 0x64, 0x75, 0x6C, 0x65, 0x20, 0x74, 0x68, +/* 0x00102100 */ 0x72, 0x65, 0x61, 0x64, 0x20, 0x31, 0x00, 0x6D, 0x6F, 0x64, 0x75, 0x6C, 0x65, 0x20, 0x74, 0x68, +/* 0x00102110 */ 0x72, 0x65, 0x61, 0x64, 0x20, 0x32, 0x00, 0x6D, 0x6F, 0x64, 0x75, 0x6C, 0x65, 0x20, 0x74, 0x68, +/* 0x00102120 */ 0x72, 0x65, 0x61, 0x64, 0x20, 0x33, 0x00, 0x6D, 0x6F, 0x64, 0x75, 0x6C, 0x65, 0x20, 0x74, 0x68, +/* 0x00102130 */ 0x72, 0x65, 0x61, 0x64, 0x20, 0x34, 0x00, 0x6D, 0x6F, 0x64, 0x75, 0x6C, 0x65, 0x20, 0x74, 0x68, +/* 0x00102140 */ 0x72, 0x65, 0x61, 0x64, 0x20, 0x35, 0x00, 0x6D, 0x6F, 0x64, 0x75, 0x6C, 0x65, 0x20, 0x74, 0x68, +/* 0x00102150 */ 0x72, 0x65, 0x61, 0x64, 0x20, 0x36, 0x00, 0x6D, 0x6F, 0x64, 0x75, 0x6C, 0x65, 0x20, 0x74, 0x68, +/* 0x00102160 */ 0x72, 0x65, 0x61, 0x64, 0x20, 0x37, 0x00, 0x6D, 0x6F, 0x64, 0x75, 0x6C, 0x65, 0x20, 0x71, 0x75, +/* 0x00102170 */ 0x65, 0x75, 0x65, 0x20, 0x30, 0x00, 0x6D, 0x6F, 0x64, 0x75, 0x6C, 0x65, 0x20, 0x73, 0x65, 0x6D, +/* 0x00102180 */ 0x61, 0x70, 0x68, 0x6F, 0x72, 0x65, 0x20, 0x30, 0x00, 0x6D, 0x6F, 0x64, 0x75, 0x6C, 0x65, 0x20, +/* 0x00102190 */ 0x65, 0x76, 0x65, 0x6E, 0x74, 0x20, 0x66, 0x6C, 0x61, 0x67, 0x73, 0x20, 0x30, 0x00, 0x6D, 0x6F, +/* 0x001021A0 */ 0x64, 0x75, 0x6C, 0x65, 0x20, 0x6D, 0x75, 0x74, 0x65, 0x78, 0x20, 0x30, 0x00, 0x6D, 0x6F, 0x64, +/* 0x001021B0 */ 0x75, 0x6C, 0x65, 0x20, 0x62, 0x6C, 0x6F, 0x63, 0x6B, 0x20, 0x70, 0x6F, 0x6F, 0x6C, 0x20, 0x30, +/* 0x001021C0 */ 0x00, 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, +/* 0x001021D0 */ 0x07, 0x21, 0x00, 0x00, 0x45, 0x00, 0x00, 0x00, 0x2A, 0x00, 0x00, 0x00, 0xF8, 0x27, 0x00, 0x00, +/* 0x001021E0 */ 0xCF, 0x20, 0x00, 0x00}; + diff --git a/ports_module/cortex-r4/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat b/ports_module/cortex-r4/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat new file mode 100644 index 00000000..926647b2 --- /dev/null +++ b/ports_module/cortex-r4/ac6/example_build/sample_threadx_module_manager/sample_threadx.scat @@ -0,0 +1,39 @@ +;************************************************** +; Copyright (c) 2017 ARM Ltd. All rights reserved. +;************************************************** + +; Scatter-file for RTX Example on Versatile Express R4 + +; This scatter-file places application code, data and peripherals at suitable addresses in the memory map. + +; This platform has 2GB SDRAM starting at 0x0. + + +SDRAM 0x0 0x40000000 +{ + CODE +0 0x200000 + { + startup.o (Vectors, +FIRST) ; Vector table and other (assembler) startup code + * (InRoot$$Sections) ; All (library) code that must be in a root region + * (+RO-CODE) ; Application RO code (.text) + * (+RO-DATA) ; Application RO data (.constdata) + } + + IRQ_STACK +0 ALIGN 8 EMPTY 1024 {} + + FIQ_STACK +0 ALIGN 8 EMPTY 512 {} + + SVC_STACK +0 ALIGN 8 EMPTY 2048 {} + + SYS_STACK +0 ALIGN 8 EMPTY 2048 {} + + ABORT_STACK +0 ALIGN 8 EMPTY 2048 {} + + ; Application RW & ZI data (.data & .bss) + DATA +0 0x100000 + { + * (+RW,+ZI) + } + + PERIPHERALS 0xA0000000 EMPTY 0x20000000 { }; Peripherals +} diff --git a/ports_module/cortex-r4/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c b/ports_module/cortex-r4/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c new file mode 100644 index 00000000..99e8fa3e --- /dev/null +++ b/ports_module/cortex-r4/ac6/example_build/sample_threadx_module_manager/sample_threadx_module_manager.c @@ -0,0 +1,119 @@ +/* Small demonstration of the ThreadX module manager. */ + +#include "tx_api.h" +#include "txm_module.h" +#include "timer.h" + +#define DEMO_STACK_SIZE 1024 + +/* Define the ThreadX object control blocks... */ + +TX_THREAD module_manager; +TXM_MODULE_INSTANCE my_module; + +UCHAR manager_stack[1024]; + +/* Define the object pool area. */ + +UCHAR object_memory[16384]; + +/* Define the module data pool area. */ +#define MODULE_DATA_SIZE 65536 +unsigned char module_data_area[MODULE_DATA_SIZE]; + +/* Module code is in an array created by module_to_c_array utility. */ +extern const unsigned char module_code[]; + +/* Define the count of memory faults. */ + +ULONG memory_faults; + + +/* Define thread prototypes. */ + +void module_manager_entry(ULONG thread_input); + + +/* Define fault handler. */ + +VOID module_fault_handler(TX_THREAD *thread, TXM_MODULE_INSTANCE *module) +{ + + /* Just increment the fault counter. */ + memory_faults++; +} + +/* Define main entry point. */ + +int main() +{ + + /* Setup the timer. */ + timer_init(); + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + manager_stack, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); +} + + + + +/* Define the test threads. */ + +void module_manager_entry(ULONG thread_input) +{ + + /* Initialize the module manager. */ + txm_module_manager_initialize((VOID *) module_data_area, MODULE_DATA_SIZE); + + txm_module_manager_object_pool_create(object_memory, sizeof(object_memory)); + + /* Register a fault handler. */ + txm_module_manager_memory_fault_notify(module_fault_handler); + + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ + txm_module_manager_in_place_load(&my_module, "my module", (VOID *) 0x00100000 /*module_code*/); + + /* Enable 128 byte read/write shared memory region at 0x08025000. */ + txm_module_manager_external_memory_enable(&my_module, (void *) 0x08025000, 128, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); + + /* Start the module. */ + txm_module_manager_start(&my_module); + + /* Sleep for a while.... */ + tx_thread_sleep(300); + + /* Stop the module. */ + txm_module_manager_stop(&my_module); + + /* Unload the module. */ + txm_module_manager_unload(&my_module); + + /* Load the module that is already there. */ + txm_module_manager_in_place_load(&my_module, "my module", (VOID *) 0x00100000); + + /* Set maximum module priority to 5. */ + txm_module_manager_maximum_module_priority_set(&my_module, 5); + /* In this demo, module threads 0 and 5 will not start because their priorities + * are higher than 5. */ + + /* Start the module again. */ + txm_module_manager_start(&my_module); + + /* Now just spin... */ + while(1) + { + + tx_thread_sleep(100); + } +} diff --git a/ports_module/cortex-r4/ac6/example_build/sample_threadx_module_manager/startup.S b/ports_module/cortex-r4/ac6/example_build/sample_threadx_module_manager/startup.S new file mode 100644 index 00000000..cd6479d3 --- /dev/null +++ b/ports_module/cortex-r4/ac6/example_build/sample_threadx_module_manager/startup.S @@ -0,0 +1,249 @@ +//---------------------------------------------------------------- +// Cortex-R4(F) Embedded example - Startup Code +// +// Copyright (c) 2006-2018 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +//---------------------------------------------------------------- + + +#define FIQ_MODE 0x11 +#define IRQ_MODE 0x12 +#define SVC_MODE 0x13 +#define ABT_MODE 0x17 +#define SYS_MODE 0x1F + +//---------------------------------------------------------------- + + .eabi_attribute Tag_ABI_align8_preserved,1 + + .section VECTORS,"ax" + .align 3 + .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + +//---------------------------------------------------------------- +// Exception Vector Table +//---------------------------------------------------------------- +// Note: LDR PC instructions are used here, though branch (B) instructions +// could also be used, unless the exception handlers are >32MB away. + + .global Vectors + +Vectors: + LDR PC, Reset_Addr + LDR pc,=__tx_undefined // Undefined handler + LDR pc,=__tx_svc_interrupt // Software interrupt handler + LDR pc,=__tx_prefetch_handler // Prefetch exception handler + LDR pc,=__tx_abort_handler // Abort exception handler + LDR pc,=__tx_reserved_handler // Reserved exception handler + LDR pc,=__tx_irq_handler // IRQ interrupt handler + LDR pc,=__tx_fiq_handler // FIQ interrupt handler + + + .balign 4 +Reset_Addr: .word Reset_Handler +Undefined_Addr: .word __tx_undefined +SVC_Addr: .word __tx_svc_interrupt +Prefetch_Addr: .word __tx_prefetch_handler +Abort_Addr: .word __tx_abort_handler +IRQ_Addr: .word __tx_irq_handler +FIQ_Addr: .word __tx_fiq_handler + + +//---------------------------------------------------------------- +// Reset Handler +//---------------------------------------------------------------- + + .global Reset_Handler + .type Reset_Handler, "function" +Reset_Handler: + +//---------------------------------------------------------------- +// Disable MPU and caches +//---------------------------------------------------------------- + +// Disable MPU and cache in case it was left enabled from an earlier run +// This does not need to be done from a cold reset + + MRC p15, 0, r0, c1, c0, 0 // Read System Control Register + BIC r0, r0, #(0x1 << 12) // Clear I bit 12 to disable I Cache + BIC r0, r0, #(0x1 << 2) // Clear C bit 2 to disable D Cache + BIC r0, r0, #0x1 // Clear M bit 0 to disable MPU + DSB // Ensure all previous loads/stores have completed + MCR p15, 0, r0, c1, c0, 0 // Write System Control Register + ISB // Ensure subsequent insts execute wrt new MPU settings + +//---------------------------------------------------------------- +// Disable Branch prediction +//---------------------------------------------------------------- + +// In the Cortex-R4, the Z-bit of the SCTLR does not control the program flow prediction. +// Some control bits in the ACTLR control the program flow and prefetch features instead. +// These are enabled by default, but are shown here for completeness. + + MRC p15, 0, r0, c1, c0, 1 // Read ACTLR + ORR r0, r0, #(0x1 << 17) // Enable RSDIS bit 17 to disable the return stack + ORR r0, r0, #(0x1 << 16) // Clear BP bit 15 and set BP bit 16: + BIC r0, r0, #(0x1 << 15) // Branch always not taken and history table updates disabled + MCR p15, 0, r0, c1, c0, 1 // Write ACTLR + ISB + +//---------------------------------------------------------------- +// Cache invalidation +//---------------------------------------------------------------- + + DSB // Complete all outstanding explicit memory operations + + MOV r0, #0 + + MCR p15, 0, r0, c7, c5, 0 // Invalidate entire instruction cache + MCR p15, 0, r0, c15, c5, 0 // Invalidate entire data cache + + +//---------------------------------------------------------------- +// Initialize Supervisor Mode Stack using Linker symbol from scatter file. +// Stacks must be 8 byte aligned. +//---------------------------------------------------------------- + + /****** NOTE ****** We must be in SVC MODE at this point. Some monitors + enter this routine in USER mode and require a software interrupt to + change into SVC mode. */ + +#ifdef TX_ENABLE_IRQ_NESTING + /* Setup the system mode stack for nested interrupt support */ + MOV r3, #SYS_MODE // Build SYS mode CPSR + MSR CPSR_c, r3 // Enter SYS mode + LDR sp, =Image$$SYS_STACK$$ZI$$Limit // Setup SYS stack pointer +#endif + + CPS #ABT_MODE // Build Abort mode CPSR + LDR sp, =Image$$ABORT_STACK$$ZI$$Limit // Setup abort stack pointer + + CPS #FIQ_MODE // Build FIQ mode CPSR + LDR sp, =Image$$FIQ_STACK$$ZI$$Limit // Setup FIQ stack pointer + MOV sl, #0 // Clear sl + MOV fp, #0 // Clear fp + + CPS #IRQ_MODE // Build IRQ mode CPSR + LDR sp, =Image$$IRQ_STACK$$ZI$$Limit // Setup IRQ stack pointer + + CPS #SVC_MODE // Build SVC mode CPSR + LDR sp, =Image$$SVC_STACK$$ZI$$Limit // Setup SVC stack pointer + + +//---------------------------------------------------------------- +// TCM Configuration +//---------------------------------------------------------------- + +// Cortex-R4 optionally provides two Tightly-Coupled Memory (TCM) blocks (ATCM and BTCM) for fast access to code or data. +// ATCM typically holds interrupt or exception code that must be accessed at high speed, +// without any potential delay resulting from a cache miss. +// BTCM typically holds a block of data for intensive processing, such as audio or video data. +// In the Cortex-R4 processor, both ATCM and BTCM support both instruction and data accesses. + +// The following illustrates basic TCM configuration, as the basis for exploration by the user + +#ifdef TCM + .global Image$$ATCM$$Base + .global Image$$BTCM0$$Base + .global Image$$BTCM1$$Base + + MRC p15, 0, r0, c0, c0, 2 // Read TCM Type Register + // r0 now contains ATCM & BTCM availability + + MRC p15, 0, r0, c9, c1, 1 // Read ATCM Region Register + // r0 now contains ATCM size in bits [6:2] + + MRC p15, 0, r0, c9, c1, 0 // Read BTCM Region Register + // r0 now contains BTCM size in bits [6:2] + +// The Cortex-R4F Core Tile has +// 64K ATCM from 0xE0FD0000 to 0xE0FDFFFF +// 64K BTCM0 from 0xE0FE0000 to 0xE0FEFFFF +// 64K BTCM1 from 0xE0FF0000 to 0xE0FFFFFF + + LDR r0, =Image$$ATCM$$Base // Set ATCM base address + ORR r0, r0, #1 // Enable it + MCR p15, 0, r0, c9, c1, 1 // Write ATCM Region Register + + LDR r0, =Image$$BTCM0$$Base // Set BTCM base address + ORR r0, r0, #1 // Enable it + MCR p15, 0, r0, c9, c1, 0 // Write BTCM Region Register + +#endif + +#ifdef __ARM_FP +//---------------------------------------------------------------- +// Enable access to VFP by enabling access to Coprocessors 10 and 11. +// Enables Full Access i.e. in both privileged and non privileged modes +//---------------------------------------------------------------- + + MRC p15, 0, r0, c1, c0, 2 // Read Coprocessor Access Control Register (CPACR) + ORR r0, r0, #(0xF << 20) // Enable access to CP 10 & 11 + MCR p15, 0, r0, c1, c0, 2 // Write Coprocessor Access Control Register (CPACR) + ISB + +//---------------------------------------------------------------- +// Switch on the VFP hardware +//---------------------------------------------------------------- + + MOV r0, #0x40000000 + VMSR FPEXC, r0 // Write FPEXC register, EN bit set +#endif + +//---------------------------------------------------------------- +// Enable Branch prediction +//---------------------------------------------------------------- + +// In the Cortex-R4, the Z-bit of the SCTLR does not control the program flow prediction. +// Some control bits in the ACTLR control the program flow and prefetch features instead. +// These are enabled by default, but are shown here for completeness. + + MRC p15, 0, r0, c1, c0, 1 // Read ACTLR + BIC r0, r0, #(0x1 << 17) // Clear RSDIS bit 17 to enable return stack + BIC r0, r0, #(0x1 << 16) // Clear BP bit 15 and BP bit 16: + BIC r0, r0, #(0x1 << 15) // Normal operation, BP is taken from the global history table. + MCR p15, 0, r0, c1, c0, 1 // Write ACTLR + ISB + + + /* Enable the GIC. */ + BL GIC_Enable + + .global __main + B __main + + .size Reset_Handler, . - Reset_Handler + +//---------------------------------------------------------------- +// Global Enable for Instruction and Data Caching +//---------------------------------------------------------------- + + .global enable_caches + + .type enable_caches, "function" + .cfi_startproc +enable_caches: + + MRC p15, 0, r0, c1, c0, 0 // Read System Control Register + ORR r0, r0, #(0x1 << 12) // enable I Cache + ORR r0, r0, #(0x1 << 2) // enable D Cache + MCR p15, 0, r0, c1, c0, 0 // Write System Control Register + ISB + + BX lr + .cfi_endproc + + .size enable_caches, . - enable_caches + +/* Define initial heap/stack routine for the ARM RealView (and ADS) startup code. This + routine will set the initial stack to use the ThreadX IRQ & FIQ & + (optionally SYS) stack areas. */ + + .global __user_initial_stackheap + .type __user_initial_stackheap, %function +__user_initial_stackheap: + + LDR r1, =Image$$SVC_STACK$$ZI$$Limit + BX lr // Return to caller diff --git a/ports_module/cortex-r4/ac6/example_build/sample_threadx_module_manager/timer.c b/ports_module/cortex-r4/ac6/example_build/sample_threadx_module_manager/timer.c new file mode 100644 index 00000000..e964d0f6 --- /dev/null +++ b/ports_module/cortex-r4/ac6/example_build/sample_threadx_module_manager/timer.c @@ -0,0 +1,28 @@ +#include "gic.h" + +/* Systick registers */ +#define PRIVTIM_IRQ 34 +#define PRIVATE_TIMER_BASE (0xB0110000) +#define PRIVTIM_RELOAD (*((volatile uint32_t *)(PRIVATE_TIMER_BASE + 0x0))) +#define PRIVTIM_CURRENT (*((volatile uint32_t *)(PRIVATE_TIMER_BASE + 0x4))) +#define PRIVTIM_CTRL (*((volatile uint32_t *)(PRIVATE_TIMER_BASE + 0x8))) +#define PRIVTIM_STATUS (*((volatile uint32_t *)(PRIVATE_TIMER_BASE + 0xc))) + +#define OS_CLOCK 12000000 +#define OS_TICK 1000 +#define OS_TRV ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1) + +#define U32 uint32_t +#define GICD_ICDICER0 (*((volatile U32 *)(GICDistributor_BASE + 0x180))) /* - RW - Interrupt Clear-Enable Registers */ +#define GICD_ICDISER0 (*((volatile U32 *)(GICDistributor_BASE + 0x100))) /* - RW - Interrupt Set-Enable Registers */ +#define GICD_ICDIPR0 (*((volatile U32 *)(GICDistributor_BASE + 0x400))) /* - RW - Interrupt Priority Registers */ +#define GICD_ICDSGIR (*((volatile U32 *)(GICDistributor_BASE + 0xf00))) /* - RW - Interrupt Software Interrupt Register */ +#define GICD_ICDICERx(irq) *(volatile U32 *)(&GICD_ICDICER0 + irq/32) +#define GICD_ICDISERx(irq) *(volatile U32 *)(&GICD_ICDISER0 + irq/32) + +void timer_init() +{ + GIC_EnableIRQ(34); + PRIVTIM_RELOAD = 0x200; + PRIVTIM_CTRL |= 0xC0; /* Enable timer, periodic mode */ +} diff --git a/ports_module/cortex-r4/ac6/example_build/sample_threadx_module_manager/timer.h b/ports_module/cortex-r4/ac6/example_build/sample_threadx_module_manager/timer.h new file mode 100644 index 00000000..efab1fe1 --- /dev/null +++ b/ports_module/cortex-r4/ac6/example_build/sample_threadx_module_manager/timer.h @@ -0,0 +1,4 @@ +#ifndef TIMER_H +#define TIMER_H +void timer_init(); +#endif diff --git a/ports_module/cortex-r4/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S b/ports_module/cortex-r4/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S new file mode 100644 index 00000000..4b2f6cb7 --- /dev/null +++ b/ports_module/cortex-r4/ac6/example_build/sample_threadx_module_manager/tx_initialize_low_level.S @@ -0,0 +1,477 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + +#define THUMB_MASK 0x20 // Thumb bit (5) of CPSR/SPSR +#define ABT_MODE 0x17 // ABT mode +#define SYS_MODE 0x1F // SYS mode + +#define GICI_BASE 0xAE000000 +#define ICCIAR_OFFSET 0x0000000C +#define ICCEOIR_OFFSET 0x00000010 + + + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global _tx_thread_context_save + .global _tx_thread_context_restore +#ifdef TX_ENABLE_FIQ_SUPPORT + .global _tx_thread_fiq_context_save + .global _tx_thread_fiq_context_restore +#endif +#ifdef TX_ENABLE_IRQ_NESTING + .global _tx_thread_irq_nesting_start + .global _tx_thread_irq_nesting_end +#endif +#ifdef TX_ENABLE_FIQ_NESTING + .global _tx_thread_fiq_nesting_start + .global _tx_thread_fiq_nesting_end +#endif + .global _tx_timer_interrupt + .global __main + .global _tx_version_id + .global _tx_build_options + +#ifdef TX_THUMB_MODE + .thumb +#else + .arm +#endif + .text + .eabi_attribute Tag_ABI_align_preserved, 1 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-R4/ARM */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_initialize_low_level(VOID) +{ */ + .global _tx_initialize_low_level + .type _tx_initialize_low_level, "function" +_tx_initialize_low_level: + + /* Save the system stack pointer. */ + /* _tx_thread_system_stack_ptr = (VOID_PTR) (sp); */ + + LDR r0, =Image$$SVC_STACK$$ZI$$Limit + LDR r1, =_tx_thread_system_stack_ptr // Pickup address of system stack ptr + STR r0, [r1] // Pickup system stack + + /* Save the first available memory address. */ + /* _tx_initialize_unused_memory = (VOID_PTR) Image$$ZI$$Limit + HEAP + [SYS_STACK] + FIQ_STACK + IRQ_STACK; */ + + LDR r0, =Image$$DATA$$ZI$$Limit + LDR r2, =_tx_initialize_unused_memory // Pickup unused memory ptr address + STR r0, [r2, #0] // Save first free memory address + + /* Return to caller. */ + BX lr // Return to caller +/* } */ + + /* Define shells for each of the interrupt vectors. */ + + .global __tx_undefined + .type __tx_undefined, "function" +__tx_undefined: + B __tx_undefined // Undefined handler + +/*** Prefetch and abort handlers are used below for MPU fault handling + .global __tx_prefetch_handler + .type __tx_prefetch_handler, "function" +__tx_prefetch_handler: + B __tx_prefetch_handler // Prefetch exception handler + + .global __tx_abort_handler + .type __tx_abort_handler, "function" +__tx_abort_handler: + B __tx_abort_handler // Abort exception handler +*/ + + .global __tx_reserved_handler + .type __tx_reserved_handler, "function" +__tx_reserved_handler: + B __tx_reserved_handler // Reserved exception handler + + + .global __tx_irq_handler + .type __tx_irq_handler, "function" + .global __tx_irq_processing_return + .type __tx_irq_processing_return, "function" +__tx_irq_handler: + + /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return: + + /* Acknowledge the interrupt. */ + LDR r1, =GICI_BASE // Load the base of the GIC + LDR r0, [r1, #ICCIAR_OFFSET] // Read ICCIAR (GIC CPU Interface register) + DSB // Ensure that interrupt acknowledge completes before re-enabling interrupts + PUSH {r0, r1} // Save the IRQ ID and the GIC base address on the stack + + /* Clear the timer interrupt. */ + LDR r0, =0xB0110000 // Load the base address of the timer + MOV r1, #1 // Setup value to write to the interrupt clear register - can be anything. + STR r1, [r0, #0x0C] // Clear the interrupt. 0x0C is the offset to the interrupt clear register. + + /* At this point execution is still in the IRQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. In + addition, IRQ interrupts may be re-enabled - with certain restrictions - + if nested IRQ interrupts are desired. Interrupts may be re-enabled over + small code sequences where lr is saved before enabling interrupts and + restored after interrupts are again disabled. */ + + + BL _tx_timer_interrupt // Timer interrupt handler +_tx_not_timer_interrupt: + + /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start + from IRQ mode with interrupts disabled. This routine switches to the + system mode and returns with IRQ interrupts enabled. */ + + /* NOTE: It is very important to ensure all IRQ interrupts are cleared + prior to enabling nested IRQ interrupts. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_start +#endif + + + /* Application IRQ handlers can be called here! */ + + /* If interrupt nesting was started earlier, the end of interrupt nesting + service must be called before returning to _tx_thread_context_restore. + This routine returns in processing in IRQ mode with interrupts disabled. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_end +#endif + + POP {r0, r1} // Restore the IRQ ID and GIC base address + STR r0, [r1, #ICCEOIR_OFFSET] // Write the IRQ ID to the End Of Interrupt register to clear the active bit + + /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + + /* This is an example of a vectored IRQ handler. */ + + .global __tx_example_vectored_irq_handler + .type __tx_example_vectored_irq_handler, "function" +__tx_example_vectored_irq_handler: + + + /* Save initial context and call context save to prepare for + vectored ISR execution. */ + +/* + STMDB sp!, {r0-r3} // Save some scratch registers + MRS r0, SPSR // Pickup saved SPSR + SUB lr, lr, #4 // Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} // Store other scratch registers + BL _tx_thread_vectored_context_save // Vectored context save +*/ + + /* At this point execution is still in the IRQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. In + addition, IRQ interrupts may be re-enabled - with certain restrictions - + if nested IRQ interrupts are desired. Interrupts may be re-enabled over + small code sequences where lr is saved before enabling interrupts and + restored after interrupts are again disabled. */ + + + /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start + from IRQ mode with interrupts disabled. This routine switches to the + system mode and returns with IRQ interrupts enabled. */ + + /* NOTE: It is very important to ensure all IRQ interrupts are cleared + prior to enabling nested IRQ interrupts. */ +/* +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_start +#endif +*/ + + /* Application IRQ handlers can be called here! */ + + /* If interrupt nesting was started earlier, the end of interrupt nesting + service must be called before returning to _tx_thread_context_restore. + This routine returns in processing in IRQ mode with interrupts disabled. */ +/* +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_end +#endif +*/ + + /* Jump to context restore to restore system context. */ +/* + B _tx_thread_context_restore +*/ + + +#ifdef TX_ENABLE_FIQ_SUPPORT + .global __tx_fiq_handler + .type __tx_fiq_handler, "function" +__tx_fiq_handler: + + /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save + + .global __tx_fiq_processing_return + .type __tx_fiq_processing_return, "function" +__tx_fiq_processing_return: + + /* At this point execution is still in the FIQ mode. The CPSR, point of + interrupt, and all C scratch registers are available for use. */ + + /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start + from FIQ mode with interrupts disabled. This routine switches to the + system mode and returns with FIQ interrupts enabled. */ + + /* NOTE: It is very important to ensure all FIQ interrupts are cleared + prior to enabling nested FIQ interrupts. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_start +#endif + + /* Application FIQ handlers can be called here! */ + + /* If interrupt nesting was started earlier, the end of interrupt nesting + service must be called before returning to _tx_thread_fiq_context_restore. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_end +#endif + + /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +#else + .global __tx_fiq_handler + .type __tx_fiq_handler, "function" +__tx_fiq_handler: + B __tx_fiq_handler // FIQ interrupt handler +#endif + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* __tx_prefetch_handler & __tx_abort_handler Cortex-R4/MPU/ARM */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles MPU exceptions and fills the */ +/* _txm_module_manager_memory_fault_info struct. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_manager_memory_fault_handler */ +/* _tx_execution_thread_exit */ +/* _tx_thread_schedule */ +/* */ +/* CALLED BY */ +/* */ +/* MMU exceptions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +/******************************************************************** + MMU Exception Handling +********************************************************************/ + .global _tx_thread_system_state + .global _txm_module_manager_memory_fault_info + .global _tx_thread_current_ptr + .global _txm_module_manager_memory_fault_handler + .global _tx_thread_schedule + + #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + .global _tx_execution_thread_exit + #endif + + + .arm /* Exception handler in ARM mode. */ + .align 3 + .global __tx_prefetch_handler + .global __tx_abort_handler + .type __tx_prefetch_handler, "function" + .type __tx_abort_handler, "function" + +__tx_prefetch_handler: +__tx_abort_handler: + STMDB sp!, {r0-r3} // Save some working registers + LDR r3, =_tx_thread_system_state // Pickup address of system state var + LDR r2, [r3, #0] // Pickup system state + ADD r2, r2, #1 // Increment the interrupt counter + STR r2, [r3, #0] // Store it back in the variable + + // Now pickup and store all the fault related information + + // Pickup the memory fault info struct + LDR r3, =_txm_module_manager_memory_fault_info + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r0] // Pickup the current thread pointer + STR r1, [r3, #0] // Save current thread pointer + + MRC p15, 0, r0, c6, c0, 0 // Read DFAR + STR r0, [r3, #8] // Save DFAR + + CMP r0, #0 // Was it a data or instruction fault? + SUBEQ lr, lr, #4 // Adjust point of exception for instruction + SUBNE lr, lr, #8 // Adjust point of exception for data + STR lr, [r3, #4] // Save point of fault + + MRC p15, 0, r0, c5, c0, 0 // Read DFSR + STR r0, [r3, #12] // Save DFSR + MRC p15, 0, r0, c6, c0, 2 // Read IFAR + STR r0, [r3, #16] // Save IFAR + MRC p15, 0, r0, c5, c0, 1 // Read IFSR + STR r0, [r3, #20] // Save IFSR + MOV r0, #0 // Build zero register + MCR p15, 0, r0, c6, c0, 0 // Clear DFAR + MCR p15, 0, r0, c5, c0, 0 // Clear DFSR + MCR p15, 0, r0, c6, c0, 2 // Clear IFAR + MCR p15, 0, r0, c5, c0, 1 // Clear IFSR + + // Save registers r0-r12 + POP {r0-r2} + STR r0, [r3, #28] // Save r0 + STR r1, [r3, #32] // Save r1 + STR r2, [r3, #36] // Save r2 + POP {r0} + STR r0, [r3, #40] // Save r3 + STR r4, [r3, #44] // Save r4 + STR r5, [r3, #48] // Save r5 + STR r6, [r3, #52] // Save r6 + STR r7, [r3, #56] // Save r7 + STR r8, [r3, #60] // Save r8 + STR r9, [r3, #64] // Save r9 + STR r10,[r3, #68] // Save r10 + STR r11,[r3, #72] // Save r11 + STR r12,[r3, #76] // Save r12 + + CPS #SYS_MODE // Enter SYS mode + MOV r0, lr // Pickup lr + MOV r1, sp // Pickup sp + CPS #ABT_MODE // Back to ABT mode + STR r0, [r3, #80] // Save lr + STR r1, [r3, #24] // Save sp + MRS r0, SPSR // Pickup SPSR + STR r0, [r3, #84] // Save SPSR + ORR r0, r0, #SYS_MODE // Return into SYS mode + BIC r0, r0, #THUMB_MASK // Clear THUMB mode + MSR SPSR_c, r0 // Save SPSR + + // Call memory manager fault handler + BL _txm_module_manager_memory_fault_handler + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + /* Call the thread exit function to indicate the thread is no longer executing. */ + BL _tx_execution_thread_exit // Call the thread exit function +#endif + + LDR r0, =_tx_thread_system_state // Pickup address of system state + LDR r1, [r0] // Pickup system state + SUB r1, r1, #1 // Decrement + STR r1, [r0] // Store new system state + + MOV r1, #0 // Build NULL value + LDR r0, =_tx_thread_current_ptr // Pickup address of current thread pointer + STR r1, [r0] // Clear current thread pointer + + // Return from exception + LDR lr, =_tx_thread_schedule // Load scheduler address + SUBS pc, lr, #0 // Return to scheduler +/******************************************************************** + End of MMU exception handling. +********************************************************************/ + + /* Reference build options and version ID to ensure they come in. */ + + LDR r2, =_tx_build_options // Pickup build options variable address + LDR r0, [r2, #0] // Pickup build options content + LDR r2, =_tx_version_id // Pickup version ID variable address + LDR r0, [r2, #0] // Pickup version ID content diff --git a/ports_module/cortex-r4/ac6/example_build/sample_threadx_module_manager/txm_cortex_r4.launch b/ports_module/cortex-r4/ac6/example_build/sample_threadx_module_manager/txm_cortex_r4.launch new file mode 100644 index 00000000..9a6bfc71 --- /dev/null +++ b/ports_module/cortex-r4/ac6/example_build/sample_threadx_module_manager/txm_cortex_r4.launch @@ -0,0 +1,463 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_module/cortex-r4/ac6/example_build/tx/.cproject b/ports_module/cortex-r4/ac6/example_build/tx/.cproject new file mode 100644 index 00000000..e8a43e7a --- /dev/null +++ b/ports_module/cortex-r4/ac6/example_build/tx/.cproject @@ -0,0 +1,140 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_module/cortex-r4/ac6/example_build/tx/.project b/ports_module/cortex-r4/ac6/example_build/tx/.project new file mode 100644 index 00000000..107bae7f --- /dev/null +++ b/ports_module/cortex-r4/ac6/example_build/tx/.project @@ -0,0 +1,63 @@ + + + tx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + inc_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/inc + + + inc_generic_module_manager + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common_modules/module_manager/inc + + + inc_generic_modules + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common_modules/inc + + + inc_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/inc + + + src_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/src + + + src_generic_module_manager + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common_modules/module_manager/src + + + src_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/module_manager/src + + + diff --git a/ports_module/cortex-r4/ac6/example_build/tx/.settings/language.settings.xml b/ports_module/cortex-r4/ac6/example_build/tx/.settings/language.settings.xml new file mode 100644 index 00000000..8a6b8b17 --- /dev/null +++ b/ports_module/cortex-r4/ac6/example_build/tx/.settings/language.settings.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_module/cortex-r4/ac6/example_build/txm/.cproject b/ports_module/cortex-r4/ac6/example_build/txm/.cproject new file mode 100644 index 00000000..562815d3 --- /dev/null +++ b/ports_module/cortex-r4/ac6/example_build/txm/.cproject @@ -0,0 +1,152 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_module/cortex-r4/ac6/example_build/txm/.project b/ports_module/cortex-r4/ac6/example_build/txm/.project new file mode 100644 index 00000000..e68229d8 --- /dev/null +++ b/ports_module/cortex-r4/ac6/example_build/txm/.project @@ -0,0 +1,54 @@ + + + txm + + + tx + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + inc_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/inc + + + inc_generic_modules + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common_modules/inc + + + inc_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/inc + + + src_generic_module + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common_modules/module_lib/src + + + src_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/module_lib/src + + + diff --git a/ports_module/cortex-r4/ac6/example_build/txm/.settings/language.settings.xml b/ports_module/cortex-r4/ac6/example_build/txm/.settings/language.settings.xml new file mode 100644 index 00000000..23f4ab94 --- /dev/null +++ b/ports_module/cortex-r4/ac6/example_build/txm/.settings/language.settings.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_module/cortex-r4/ac6/inc/tx_port.h b/ports_module/cortex-r4/ac6/inc/tx_port.h new file mode 100644 index 00000000..52efe1bf --- /dev/null +++ b/ports_module/cortex-r4/ac6/inc/tx_port.h @@ -0,0 +1,357 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-R4/AC6 */ +/* 6.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + +/* Define compiler intrinsics. */ + +#include "arm_compat.h" + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ + VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef __thumb + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + b = (ULONG) __clz((unsigned int) m); \ + b = 31 - b; +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifndef __thumb + +#define TX_INTERRUPT_SAVE_AREA register unsigned int interrupt_save_disabled; + +#ifdef TX_ENABLE_FIQ_SUPPORT + +/* IRQ and FIQ support. */ + +#define TX_DISABLE __memory_changed(), interrupt_save_disabled = __disable_irq(); \ + __disable_fiq(); + +#define TX_RESTORE if (!interrupt_save_disabled) \ + { \ + __enable_irq(); \ + __enable_fiq(); \ + } + +#else + +#define TX_DISABLE __memory_changed(), interrupt_save_disabled = __disable_irq(); + +#define TX_RESTORE if (!interrupt_save_disabled) \ + { \ + __enable_irq(); \ + } +#endif + +#else + +unsigned int _tx_thread_interrupt_disable(void); +unsigned int _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); +#endif + + +/* Define VFP extension for the Cortex-R4. Each is assumed to be called in the context of the executing + thread. */ + +void tx_thread_vfp_enable(void); +void tx_thread_vfp_disable(void); + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/AC6 Version 6.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + + + + + diff --git a/ports_module/cortex-r4/ac6/inc/txm_module_port.h b/ports_module/cortex-r4/ac6/inc/txm_module_port.h new file mode 100644 index 00000000..15f7ec88 --- /dev/null +++ b/ports_module/cortex-r4/ac6/inc/txm_module_port.h @@ -0,0 +1,366 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* txm_module_port.h Cortex-R4/MPU/ARM */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the basic module constants, interface structures, */ +/* and function prototypes. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TXM_MODULE_PORT_H +#define TXM_MODULE_PORT_H + +/* It is assumed that the base ThreadX tx_port.h file has been modified to add the + following extensions to the ThreadX thread control block (this code should replace + the corresponding macro define in tx_port.h): + +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ + VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; + +The following extensions must also be defined in tx_port.h: + +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); + +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); + + +*/ + +/* Size of module heap. */ +#define TXM_MODULE_HEAP_SIZE 1024 + +/* Define the kernel stack size for a module thread. */ +#ifndef TXM_MODULE_KERNEL_STACK_SIZE +#define TXM_MODULE_KERNEL_STACK_SIZE 1024 +#endif + +/* Defined, these options allows a memory-protected module to access kernel objects. + For example, when a module needs to send/receive a message from a kernel queue. + This does not allow modules to create or delete objects outside of their memory. + Default setting for these values is undefined. */ +/* #define TXM_MODULE_ENABLE_KERNEL_BLOCK_POOL_ACCESS */ +/* #define TXM_MODULE_ENABLE_KERNEL_BYTE_POOL_ACCESS */ +/* #define TXM_MODULE_ENABLE_KERNEL_EVENT_FLAGS_ACCESS */ +/* #define TXM_MODULE_ENABLE_KERNEL_MUTEX_ACCESS */ +/* #define TXM_MODULE_ENABLE_KERNEL_QUEUE_ACCESS */ +/* #define TXM_MODULE_ENABLE_KERNEL_SEMAPHORE_ACCESS */ + + +/* For the following 3 access control settings, change TEX and C, B, S (bits 5 through 0) + * to reflect your system memory attributes (cache, shareable, memory type). */ +/* Code region access control: read-only, outer & inner write-back, normal memory, shareable. */ +#define TXM_MODULE_MPU_CODE_ACCESS_CONTROL 0x00000607 +/* Data region access control: execute never, read/write, outer & inner write-back, normal memory, shareable. */ +#define TXM_MODULE_MPU_DATA_ACCESS_CONTROL 0x00001307 +/* Shared region access control: execute never, read-only, outer & inner write-back, normal memory, shareable. */ +#define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x00001207 + +/* Define constants specific to the tools the module can be built with for this particular modules port. */ + +#define TXM_MODULE_IAR_COMPILER 0x00000000 +#define TXM_MODULE_RVDS_COMPILER 0x01000000 +#define TXM_MODULE_GNU_COMPILER 0x02000000 +#define TXM_MODULE_COMPILER_MASK 0xFF000000 +#define TXM_MODULE_OPTIONS_MASK 0x000000FF + + +/* Define the properties for this particular module port. */ + +#define TXM_MODULE_MEMORY_PROTECTION_ENABLED + +#ifdef TXM_MODULE_MEMORY_PROTECTION_ENABLED +#define TXM_MODULE_REQUIRE_ALLOCATED_OBJECT_MEMORY +#define TXM_MODULE_MANAGER_DISABLE_INTERRUPT_CONTROL +#else +#define TXM_MODULE_REQUIRE_LOCAL_OBJECT_MEMORY +#endif + +#define TXM_MODULE_USER_MODE 0x00000001 +#define TXM_MODULE_MEMORY_PROTECTION 0x00000001 + + +/* Define the supported options for this module. */ + +#define TXM_MODULE_MANAGER_SUPPORTED_OPTIONS (TXM_MODULE_MEMORY_PROTECTION) +#define TXM_MODULE_MANAGER_REQUIRED_OPTIONS 0 + + +/* Define offset adjustments according to the compiler used to build the module. */ + +#define TXM_MODULE_IAR_SHELL_ADJUST 24 +#define TXM_MODULE_IAR_START_ADJUST 28 +#define TXM_MODULE_IAR_STOP_ADJUST 32 +#define TXM_MODULE_IAR_CALLBACK_ADJUST 44 + +#define TXM_MODULE_RVDS_SHELL_ADJUST 0 +#define TXM_MODULE_RVDS_START_ADJUST 0 +#define TXM_MODULE_RVDS_STOP_ADJUST 0 +#define TXM_MODULE_RVDS_CALLBACK_ADJUST 0 + +#define TXM_MODULE_GNU_SHELL_ADJUST 24 +#define TXM_MODULE_GNU_START_ADJUST 28 +#define TXM_MODULE_GNU_STOP_ADJUST 32 +#define TXM_MODULE_GNU_CALLBACK_ADJUST 44 + + +/* Define other module port-specific constants. */ + + +/* Define INLINE_DECLARE to inline for IAR compiler. */ + +#define INLINE_DECLARE inline + +/* Define the number of MPU entries assigned to the code and data sections. + On Cortex-R parts, there are 12 total entries. ThreadX uses one for access + to the kernel entry function, thus 11 remain for code and data protection. */ +#define TXM_MODULE_MPU_TOTAL_ENTRIES 12 +#define TXM_MODULE_MPU_CODE_ENTRIES 4 +#define TXM_MODULE_MPU_DATA_ENTRIES 4 +#define TXM_MODULE_MPU_SHARED_ENTRIES 3 + +#define TXM_MODULE_MPU_KERNEL_ENTRY_INDEX 0 +#define TXM_MODULE_MPU_SHARED_INDEX 9 + +/* There are 3 registers to set up each MPU region: DRACR, DRBAR, DRSR. */ +#define TXM_MODULE_MPU_REGISTER_COUNT 3 + +#define TXM_ENABLE_REGION 0x01 + +/* Shared memory region attributes. */ +#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 +#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x00000100 + +typedef struct TXM_MODULE_MPU_INFO_STRUCT +{ + ULONG txm_module_mpu_region_address; + ULONG txm_module_mpu_region_size; + ULONG txm_module_mpu_region_attributes; +} TXM_MODULE_MPU_INFO; +/* Define the port-extensions to the module manager instance structure. */ + +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_count; \ + ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES]; + + +/* Define the memory fault information structure that is populated when a memory fault occurs. */ + + +typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT +{ + TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr; + VOID *txm_module_manager_memory_fault_info_code_location; + ULONG txm_module_manager_memory_fault_info_dfar; + ULONG txm_module_manager_memory_fault_info_dfsr; + ULONG txm_module_manager_memory_fault_info_ifar; + ULONG txm_module_manager_memory_fault_info_ifsr; + ULONG txm_module_manager_memory_fault_info_sp; + ULONG txm_module_manager_memory_fault_info_r0; + ULONG txm_module_manager_memory_fault_info_r1; + ULONG txm_module_manager_memory_fault_info_r2; + ULONG txm_module_manager_memory_fault_info_r3; + ULONG txm_module_manager_memory_fault_info_r4; + ULONG txm_module_manager_memory_fault_info_r5; + ULONG txm_module_manager_memory_fault_info_r6; + ULONG txm_module_manager_memory_fault_info_r7; + ULONG txm_module_manager_memory_fault_info_r8; + ULONG txm_module_manager_memory_fault_info_r9; + ULONG txm_module_manager_memory_fault_info_r10; + ULONG txm_module_manager_memory_fault_info_r11; + ULONG txm_module_manager_memory_fault_info_r12; + ULONG txm_module_manager_memory_fault_info_lr; + ULONG txm_module_manager_memory_fault_info_cpsr; +} TXM_MODULE_MANAGER_MEMORY_FAULT_INFO; + + +#define TXM_MODULE_MANAGER_FAULT_INFO \ + TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info; + +/* Define the macro to check the stack available in dispatch. */ +#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE + +/* Define the macro to check the module properties. */ + +#define TXM_MODULE_MANAGER_CHECK_PROPERTIES(properties) \ + if ((properties & _txm_module_manager_properties_supported) != (properties & ~((ULONG) TXM_MODULE_COMPILER_MASK))) \ + { \ + _tx_mutex_put(&_txm_module_manager_mutex); \ + return(TXM_MODULE_INVALID_PROPERTIES); \ + } \ + if ((_txm_module_manager_properties_required & properties) != _txm_module_manager_properties_required) \ + { \ + _tx_mutex_put(&_txm_module_manager_mutex); \ + return(TXM_MODULE_INVALID_PROPERTIES); \ + } + + +/* Define the macro to check the code alignment. */ + +#define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment) \ + { \ + ULONG temp; \ + temp = (ULONG) module_location; \ + temp = temp & (code_alignment - 1); \ + if (temp) \ + { \ + _tx_mutex_put(&_txm_module_manager_mutex); \ + return(TXM_MODULE_ALIGNMENT_ERROR); \ + } \ + } + + +/* Define the macro to adjust the alignment and size for code/data areas. */ + +#define TXM_MODULE_MANAGER_ALIGNMENT_ADJUST(module_preamble, code_size, code_alignment, data_size, data_alignment) _txm_module_manager_alignment_adjust(module_preamble, &code_size, &code_alignment, &data_size, &data_alignment); + + +/* Define the macro to adjust the symbols in the module preamble. */ + +#define TXM_MODULE_MANAGER_CALCULATE_ADJUSTMENTS(properties, shell_function_adjust, start_function_adjust, stop_function_adjust, callback_function_adjust) \ + if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_IAR_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_IAR_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_IAR_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_IAR_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_IAR_CALLBACK_ADJUST; \ + } \ + else if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_RVDS_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_RVDS_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_RVDS_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_RVDS_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_RVDS_CALLBACK_ADJUST; \ + } \ + else \ + { \ + shell_function_adjust = TXM_MODULE_GNU_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_GNU_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_GNU_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_GNU_CALLBACK_ADJUST; \ + } + + +/* Define the macro to populate the thread control block with module port-specific information. + Check if the module is in user mode and set up txm_module_thread_entry_info_kernel_call_dispatcher accordingly. +*/ + +#define TXM_MODULE_MANAGER_THREAD_SETUP(thread_ptr, module_instance) \ + thread_ptr -> tx_thread_module_current_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION; \ + thread_ptr -> tx_thread_module_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION; \ + if (thread_ptr -> tx_thread_module_user_mode) \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_user_mode_entry; \ + } \ + else \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_kernel_dispatch; \ + } + + +/* Define the macro to populate the module control block with module port-specific information. + If memory protection is enabled, set up the MPU registers. +*/ +#define TXM_MODULE_MANAGER_MODULE_SETUP(module_instance) \ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) \ + { \ + _txm_module_manager_mm_register_setup(module_instance); \ + } \ + else \ + { \ + /* Do nothing. */ \ + } + +/* Define the macro to perform port-specific functions when unloading the module. */ +/* Nothing needs to be done for this port. */ +#define TXM_MODULE_MANAGER_MODULE_UNLOAD(module_instance) + + +/* Define the macros to perform port-specific checks when passing pointers to the kernel. */ + +/* Define macro to make sure object is inside the module's data. */ +#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ + _txm_module_manager_inside_data_check(module_instance, obj_ptr, obj_size) + + +/* Define some internal prototypes to this module port. */ + +#ifndef TX_SOURCE_CODE +#define txm_module_manager_memory_fault_notify _txm_module_manager_memory_fault_notify +#endif + + +#define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES \ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment); \ +ULONG _txm_module_manager_data_pointer_check(TXM_MODULE_INSTANCE *module_instance, ULONG pointer); \ +VOID _txm_module_manager_memory_fault_handler(VOID); \ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)); \ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \ +ULONG _txm_power_of_two_block_size(ULONG size); \ +ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); \ +ULONG _txm_module_manager_region_size_get(ULONG block_size); \ +UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size); + +#define TXM_MODULE_MANAGER_VERSION_ID \ +CHAR _txm_module_manager_version_id[] = \ + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-R4/MPU/ARM Version 6.1 *"; + +#endif + diff --git a/ports_module/cortex-r4/ac6/module_lib/src/txm_module_initialize.S b/ports_module/cortex-r4/ac6/module_lib/src/txm_module_initialize.S new file mode 100644 index 00000000..6ee089f2 --- /dev/null +++ b/ports_module/cortex-r4/ac6/module_lib/src/txm_module_initialize.S @@ -0,0 +1,104 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Module */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" + + + + .global __scatterload + +#ifdef TX_THUMB_MODE + .thumb +#else + .arm +#endif + .text + .eabi_attribute Tag_ABI_align_preserved, 1 + .eabi_attribute Tag_ABI_PCS_RO_data, 1 + .eabi_attribute Tag_ABI_PCS_R9_use, 1 + .eabi_attribute Tag_ABI_PCS_RW_data, 2 + .arm +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_initialize Cortex-R4/MPU/ARM */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes the module c runtime. */ +/* */ +/* INPUT */ +/* */ +/* heap_base Pointer to bottom of heap */ +/* heap_top Pointer to top of heap */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __scatterload Initialize C runtime */ +/* __rt_lib_init Initialize heap */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_thread_shell_entry Start module thread */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _txm_module_initialize(VOID *heap_base, VOID *heap_top) */ + .global _txm_module_initialize + .type _txm_module_initialize, %function + +_txm_module_initialize: + PUSH {r0-r12,lr} // Save dregs and LR + + B __scatterload // Call ARM func to initialize variables + + + .global __rt_entry + .type __rt_entry, %function +__rt_entry: + POP {r0-r1} + BL __rt_lib_init + POP {r2-r12,lr} // Restore dregs and LR + BX lr // Return to caller + + diff --git a/ports_module/cortex-r4/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex-r4/ac6/module_lib/src/txm_module_thread_shell_entry.c new file mode 100644 index 00000000..3415c85c --- /dev/null +++ b/ports_module/cortex-r4/ac6/module_lib/src/txm_module_thread_shell_entry.c @@ -0,0 +1,176 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#ifndef TXM_MODULE +#define TXM_MODULE +#endif + +#ifndef TX_SOURCE_CODE +#define TX_SOURCE_CODE +#endif + + +/* Include necessary system files. */ + +#include "txm_module.h" +#include "tx_thread.h" + +/* Define the global module entry pointer from the start thread of the module. */ + +TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; + + +/* Define the dispatch function pointer used in the module implementation. */ + +ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3); + +/* Define the module's heap and align it to 8 bytes. */ +__attribute__((aligned(8))) UCHAR txm_heap[TXM_MODULE_HEAP_SIZE]; + +/* Must use two region memory - heap and stack are not next to each other. */ +__asm(".global __use_two_region_memory\n\t"); + +/* Use our asm routine that calls the ARM code to initialize data and heap. */ +extern VOID _txm_module_initialize(VOID *heap_base, VOID *heap_top); + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_thread_shell_entry Cortex-R4/MPU/ARM */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calls the specified entry function of the thread. It */ +/* also provides a place for the thread's entry function to return. */ +/* If the thread returns, this function places the thread in a */ +/* "COMPLETED" state. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to current thread */ +/* thread_info Pointer to thread entry info */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_initialize cstartup initialization */ +/* thread_entry Thread's entry function */ +/* tx_thread_resume Resume the module callback thread */ +/* _txm_module_thread_system_suspend Module thread suspension routine */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) +{ + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + VOID (*entry_exit_notify)(TX_THREAD *, UINT); +#endif + + + /* Determine if this is the start thread. If so, we must prepare the module for + execution. If not, simply skip the C startup code. */ + if (thread_info -> txm_module_thread_entry_info_start_thread) + { + /* Initialize the ARM C environment. */ + _txm_module_initialize(&txm_heap[0], &txm_heap[TXM_MODULE_HEAP_SIZE-1]); + + /* Save the entry info pointer, for later use. */ + _txm_module_entry_info = thread_info; + + /* Save the kernel function dispatch address. This is used to make all resident calls from + the module. */ + _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; + + /* Ensure that we have a valid pointer. */ + while (!_txm_module_kernel_call_dispatcher) + { + /* Loop here, if an error is present getting the dispatch function pointer! + An error here typically indicates the resident portion of _tx_thread_schedule + is not supporting the trap to obtain the function pointer. */ + } + + /* Resume the module's callback thread, already created in the manager. */ + _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); + } + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has been entered! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_ENTRY); + } +#endif + + /* Call current thread's entry function. */ + (thread_info -> txm_module_thread_entry_info_entry) (thread_info -> txm_module_thread_entry_info_parameter); + + /* Suspend thread with a "completed" state. */ + + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine again. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has exited! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_EXIT); + } +#endif + + /* Call actual thread suspension routine. */ + _txm_module_thread_system_suspend(thread_ptr); + +#ifdef TX_SAFETY_CRITICAL + + /* If we ever get here, raise safety critical exception. */ + TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0); +#endif +} + diff --git a/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_context_restore.S new file mode 100644 index 00000000..d739d0e1 --- /dev/null +++ b/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_context_restore.S @@ -0,0 +1,259 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + +#define IRQ_MODE 0x12 // IRQ mode +#define SYS_MODE 0x1F // SYS mode +#define THUMB_MASK 0x20 // Thumb bit mask + + + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + .global _tx_execution_isr_exit +#endif + + +#ifdef TX_THUMB_MODE + .thumb +#else + .arm +#endif + .text + .eabi_attribute Tag_ABI_align_preserved, 1 + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore Cortex-R4/MPU/ARM */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores the interrupt context if it is processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_restore(VOID) +{ */ + .global _tx_thread_context_restore + .type _tx_thread_context_restore, "function" +_tx_thread_context_restore: + + /* Lockout interrupts. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Disable IRQ and FIQ interrupts +#else + CPSID i // Disable IRQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR exit function to indicate an ISR is complete. */ + + BL _tx_execution_isr_exit // Call the ISR exit function +#endif + + /* Determine if interrupts are nested. */ + /* if (--_tx_thread_system_state) + { */ + + LDR r3, =_tx_thread_system_state // Pickup address of system state var + LDR r2, [r3, #0] // Pickup system state + SUB r2, r2, #1 // Decrement the counter + STR r2, [r3, #0] // Store the counter + CMP r2, #0 // Was this the first interrupt? + BEQ __tx_thread_not_nested_restore // If so, not a nested restore + + /* Interrupts are nested. */ + + /* Just recover the saved registers and return to the point of + interrupt. */ + + LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 // Put SPSR back + LDMIA sp!, {r0-r3} // Recover r0-r3 + SUBS pc, lr, #0 // Return to point of interrupt + + /* } */ +__tx_thread_not_nested_restore: + + /* Determine if a thread was interrupted and no preemption is required. */ + /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) + (_tx_thread_preempt_disable)) + { */ + + LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr + LDR r0, [r1, #0] // Pickup actual current thread pointer + CMP r0, #0 // Is it NULL? + BEQ __tx_thread_idle_system_restore // Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable // Pickup preempt disable address + LDR r2, [r3, #0] // Pickup actual preempt disable flag + CMP r2, #0 // Is it set? + BNE __tx_thread_no_preempt_restore // Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr // Pickup address of execute thread ptr + LDR r2, [r3, #0] // Pickup actual execute thread pointer + CMP r0, r2 // Is the same thread highest priority? + BNE __tx_thread_preempt_restore // No, preemption needs to happen + + +__tx_thread_no_preempt_restore: + + /* Restore interrupted thread or ISR. */ + + /* Pickup the saved stack pointer. */ + /* tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; */ + + /* Recover the saved context and return to the point of interrupt. */ + + LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 // Put SPSR back + LDMIA sp!, {r0-r3} // Recover r0-r3 + SUBS pc, lr, #0 // Return to point of interrupt + + /* } + else + { */ +__tx_thread_preempt_restore: + + LDMIA sp!, {r3, r10, r12, lr} // Recover temporarily saved registers + MOV r1, lr // Save lr (point of interrupt) + CPS #SYS_MODE // Switch to SYS mode to save context on thread stack + STR r1, [sp, #-4]! // Save point of interrupt + STMDB sp!, {r4-r12, lr} // Save registers + MOV r4, r3 // Save SPSR in r4 + + CPS #IRQ_MODE // Switch back to IRQ mode + LDMIA sp!, {r0-r3} // Recover r0-r3 + + CPS #SYS_MODE // Switch to SYS mode to save remaining context on thread stack + STMDB sp!, {r0-r3} // Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr + LDR r0, [r1, #0] // Pickup current thread pointer + +#ifdef __ARM_FP + LDR r2, [r0, #144] // Pickup the VFP enabled flag + CMP r2, #0 // Is the VFP enabled? + BEQ _tx_skip_irq_vfp_save // No, skip VFP IRQ save + VMRS r2, FPSCR // Pickup the FPSCR + STR r2, [sp, #-4]! // Save FPSCR + VSTMDB sp!, {D0-D15} // Save D0-D15 +_tx_skip_irq_vfp_save: +#endif + + MOV r3, #1 // Build interrupt stack type + STMDB sp!, {r3, r4} // Save interrupt stack type and SPSR + STR sp, [r0, #8] // Save stack pointer in thread control + // block + + /* Save the remaining time-slice and disable it. */ + /* if (_tx_timer_time_slice) + { */ + + LDR r3, =_tx_timer_time_slice // Pickup time-slice variable address + LDR r2, [r3, #0] // Pickup time-slice + CMP r2, #0 // Is it active? + BEQ __tx_thread_dont_save_ts // No, don't save it + + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; */ + /* _tx_timer_time_slice = 0; */ + + STR r2, [r0, #24] // Save thread's time-slice + MOV r2, #0 // Clear value + STR r2, [r3, #0] // Disable global time-slice flag + + /* } */ +__tx_thread_dont_save_ts: + + + /* Clear the current task pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + MOV r0, #0 // NULL value + STR r0, [r1, #0] // Clear current thread pointer + + /* Return to the scheduler. */ + /* _tx_thread_schedule(); */ + + CPS #IRQ_MODE // Enter IRQ mode + MRS r1, SPSR // Get SPSR + ORR r1, r1, #SYS_MODE // Change to SYS Mode + BIC r1, r1, #THUMB_MASK // Clear thumb bit + MSR SPSR_cxsf, r1 // Put SYS Mode in SPSR + LDR lr, =_tx_thread_schedule // Load scheduler address + SUBS pc, lr, #0 // Return to scheduler + /* } */ + +__tx_thread_idle_system_restore: + + /* Just return back to the scheduler! */ + + LDR lr, =_tx_thread_schedule // Load scheduler address + SUBS pc, lr, #0 // Return to scheduler +/* } */ diff --git a/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_context_save.S new file mode 100644 index 00000000..a935546f --- /dev/null +++ b/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_context_save.S @@ -0,0 +1,202 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" */ +/* #include "tx_thread.h" */ + + + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global __tx_irq_processing_return +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + .global _tx_execution_isr_enter +#endif + + +#ifdef TX_THUMB_MODE + .thumb +#else + .arm +#endif + .text + .eabi_attribute Tag_ABI_align_preserved, 1 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save Cortex-R4/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_save(VOID) +{ */ + .global _tx_thread_context_save + .type _tx_thread_context_save, "function" +_tx_thread_context_save: + + /* Upon entry to this routine, it is assumed that IRQ interrupts are locked + out, we are in IRQ mode, and all registers are intact. */ + + /* Check for a nested interrupt condition. */ + /* if (_tx_thread_system_state++) + { */ + + STMDB sp!, {r0-r3} // Save some working registers +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Disable FIQ interrupts +#endif + LDR r3, =_tx_thread_system_state // Pickup address of system state var + LDR r2, [r3, #0] // Pickup system state + CMP r2, #0 // Is this the first interrupt? + BEQ __tx_thread_not_nested_save // Yes, not a nested context save + + /* Nested interrupt condition. */ + + ADD r2, r2, #1 // Increment the interrupt counter + STR r2, [r3, #0] // Store it back in the variable + + /* Save the rest of the scratch registers on the stack and return to the + calling ISR. */ + + MRS r0, SPSR // Pickup saved SPSR + SUB lr, lr, #4 // Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} // Store other registers + + /* Return to the ISR. */ + + MOV r10, #0 // Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} // Save ISR lr + BL _tx_execution_isr_enter // Call the ISR enter function + POP {lr} // Recover ISR lr +#endif + + B __tx_irq_processing_return // Continue IRQ processing + +__tx_thread_not_nested_save: + /* } */ + + /* Otherwise, not nested, check to see if a thread was running. */ + /* else if (_tx_thread_current_ptr) + { */ + + ADD r2, r2, #1 // Increment the interrupt counter + STR r2, [r3, #0] // Store it back in the variable + LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr + LDR r0, [r1, #0] // Pickup current thread pointer + CMP r0, #0 // Is it NULL? + BEQ __tx_thread_idle_system_save // If so, interrupt occurred in + // scheduling loop - nothing needs saving! + + /* Save minimal context of interrupted thread. */ + + MRS r2, SPSR // Pickup saved SPSR + SUB lr, lr, #4 // Adjust point of interrupt + STMDB sp!, {r2, r10, r12, lr} // Store other registers + + /* Save the current stack pointer in the thread's control block. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ + + /* Switch to the system stack. */ + /* sp = _tx_thread_system_stack_ptr; */ + + MOV r10, #0 // Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} // Save ISR lr + BL _tx_execution_isr_enter // Call the ISR enter function + POP {lr} // Recover ISR lr +#endif + + B __tx_irq_processing_return // Continue IRQ processing + + /* } + else + { */ + +__tx_thread_idle_system_save: + + /* Interrupt occurred in the scheduling loop. */ + + /* Not much to do here, just adjust the stack pointer, and return to IRQ + processing. */ + + MOV r10, #0 // Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} // Save ISR lr + BL _tx_execution_isr_enter // Call the ISR enter function + POP {lr} // Recover ISR lr +#endif + + ADD sp, sp, #16 // Recover saved registers + B __tx_irq_processing_return // Continue IRQ processing + + /* } */ +/* } */ diff --git a/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_fiq_context_restore.S b/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_fiq_context_restore.S new file mode 100644 index 00000000..c480e844 --- /dev/null +++ b/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_fiq_context_restore.S @@ -0,0 +1,260 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" */ +/* #include "tx_thread.h" */ +/* #include "tx_timer.h" */ + + +#define FIQ_MODE 0x11 // FIQ mode +#define SVC_MODE 0x13 // SVC mode +#define MODE_MASK 0x1F // Mode mask +#define IRQ_MODE_BITS 0x12 // IRQ mode bits + + + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_system_stack_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + .global _tx_execution_isr_exit +#endif + + +#ifdef TX_THUMB_MODE + .thumb +#else + .arm +#endif + .text + .eabi_attribute Tag_ABI_align_preserved, 1 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_context_restore Cortex-R4/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores the fiq interrupt context when processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* FIQ ISR Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_fiq_context_restore(VOID) */ +/* { */ + .global _tx_thread_fiq_context_restore + .type _tx_thread_fiq_context_restore, "function" +_tx_thread_fiq_context_restore: + + /* Lockout interrupts. */ + + CPSID if // Disable IRQ and FIQ interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR exit function to indicate an ISR is complete. */ + + BL _tx_execution_isr_exit // Call the ISR exit function +#endif + + /* Determine if interrupts are nested. */ + /* if (--_tx_thread_system_state) */ + /* { */ + + LDR r3, =_tx_thread_system_state // Pickup address of system state var + LDR r2, [r3] // Pickup system state + SUB r2, r2, #1 // Decrement the counter + STR r2, [r3] // Store the counter + CMP r2, #0 // Was this the first interrupt? + BEQ __tx_thread_fiq_not_nested_restore // If so, not a nested restore + + /* Interrupts are nested. */ + + /* Just recover the saved registers and return to the point of + interrupt. */ + + LDMIA sp!, {r0, r10, r12, lr} // Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 // Put SPSR back + LDMIA sp!, {r0-r3} // Recover r0-r3 + SUBS pc, lr, #0 // Return to point of interrupt + + + /* } */ +__tx_thread_fiq_not_nested_restore: + + /* Determine if a thread was interrupted and no preemption is required. */ + /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) */ + /* (_tx_thread_preempt_disable)) */ + /* { */ + + LDR r1, [sp] // Pickup the saved SPSR + MOV r2, #MODE_MASK // Build mask to isolate the interrupted mode + AND r1, r1, r2 // Isolate mode bits + CMP r1, #IRQ_MODE_BITS // Was an interrupt taken in IRQ mode before we + // got to context save? */ + BEQ __tx_thread_fiq_no_preempt_restore // Yes, just go back to point of interrupt + + + LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr + LDR r0, [r1] // Pickup actual current thread pointer + CMP r0, #0 // Is it NULL? + BEQ __tx_thread_fiq_idle_system_restore // Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable // Pickup preempt disable address + LDR r2, [r3] // Pickup actual preempt disable flag + CMP r2, #0 // Is it set? + BNE __tx_thread_fiq_no_preempt_restore // Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr // Pickup address of execute thread ptr + LDR r2, [r3] // Pickup actual execute thread pointer + CMP r0, r2 // Is the same thread highest priority? + BNE __tx_thread_fiq_preempt_restore // No, preemption needs to happen + + +__tx_thread_fiq_no_preempt_restore: + + /* Restore interrupted thread or ISR. */ + + /* Pickup the saved stack pointer. */ + /* tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; */ + + /* Recover the saved context and return to the point of interrupt. */ + + LDMIA sp!, {r0, lr} // Recover SPSR and POI + MSR SPSR_cxsf, r0 // Put SPSR back + LDMIA sp!, {r0-r3} // Recover r0-r3 + SUBS pc, lr, #0 // Return to point of interrupt + + /* } */ + /* else */ + /* { */ +__tx_thread_fiq_preempt_restore: + + LDMIA sp!, {r3, lr} // Recover temporarily saved registers + MOV r1, lr // Save lr (point of interrupt) + + CPS #SVC_MODE // Switch to SVC mode to save context on thread stack + STR r1, [sp, #-4]! // Save point of interrupt + STMDB sp!, {r4-r12, lr} // Save upper half of registers + MOV r4, r3 // Save SPSR in r4 + + CPS #FIQ_MODE // Switch back to FIQ mode + LDMIA sp!, {r0-r3} // Recover r0-r3 + + CPS #SVC_MODE // Switch to SVC mode to save remaining context on thread stack + STMDB sp!, {r0-r3} // Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr + LDR r0, [r1] // Pickup current thread pointer + +#ifdef __ARM_FP + LDR r2, [r0, #144] // Pickup the VFP enabled flag + CMP r2, #0 // Is the VFP enabled? + BEQ _tx_skip_fiq_vfp_save // No, skip VFP FIQ save + VMRS r2, FPSCR // Pickup the FPSCR + STR r2, [sp, #-4]! // Save FPSCR + VSTMDB sp!, {D0-D15} // Save D0-D15 +_tx_skip_fiq_vfp_save: +#endif + + MOV r3, #1 // Build interrupt stack type + STMDB sp!, {r3, r4} // Save interrupt stack type and SPSR + STR sp, [r0, #8] // Save stack pointer in thread control + // block + + /* Save the remaining time-slice and disable it. */ + /* if (_tx_timer_time_slice) */ + /* { */ + + LDR r3, =_tx_timer_time_slice // Pickup time-slice variable address + LDR r2, [r3] // Pickup time-slice + CMP r2, #0 // Is it active? + BEQ __tx_thread_fiq_dont_save_ts // No, don't save it + + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; */ + /* _tx_timer_time_slice = 0; */ + + STR r2, [r0, #24] // Save thread's time-slice + MOV r2, #0 // Clear value + STR r2, [r3] // Disable global time-slice flag + + /* } */ +__tx_thread_fiq_dont_save_ts: + + + /* Clear the current task pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + MOV r0, #0 // NULL value + STR r0, [r1] // Clear current thread pointer + + /* Return to the scheduler. */ + /* _tx_thread_schedule(); */ + + B _tx_thread_schedule // Return to scheduler + /* } */ + +__tx_thread_fiq_idle_system_restore: + + /* Just return back to the scheduler! */ + + ADD sp, sp, #24 // Recover FIQ stack space + CPS #SVC_MODE // Switch to SVC mode + B _tx_thread_schedule // Return to scheduler + +/* } */ diff --git a/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_fiq_context_save.S b/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_fiq_context_save.S new file mode 100644 index 00000000..18d6d587 --- /dev/null +++ b/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_fiq_context_save.S @@ -0,0 +1,209 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#ifdef TX_ENABLE_FIQ_SUPPORT + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" */ +/* #include "tx_thread.h" */ + + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global __tx_fiq_processing_return +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + .global _tx_execution_isr_enter +#endif + + +#ifdef TX_THUMB_MODE + .thumb +#else + .arm +#endif + .text + .eabi_attribute Tag_ABI_align_preserved, 1 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_context_save Cortex-R4/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + /* VOID _tx_thread_fiq_context_save(VOID) */ +/* { */ + + .global _tx_thread_fiq_context_save + .type _tx_thread_fiq_context_save, "function" +_tx_thread_fiq_context_save: + + /* Upon entry to this routine, it is assumed that IRQ interrupts are locked + out, we are in IRQ mode, and all registers are intact. */ + + /* Check for a nested interrupt condition. */ + /* if (_tx_thread_system_state++) */ + /* { */ + + STMDB sp!, {r0-r3} // Save some working registers + LDR r3, =_tx_thread_system_state // Pickup address of system state var + LDR r2, [r3] // Pickup system state + CMP r2, #0 // Is this the first interrupt? + BEQ __tx_thread_fiq_not_nested_save // Yes, not a nested context save + + /* Nested interrupt condition. */ + + ADD r2, r2, #1 // Increment the interrupt counter + STR r2, [r3] // Store it back in the variable + + /* Save the rest of the scratch registers on the stack and return to the + calling ISR. */ + + MRS r0, SPSR // Pickup saved SPSR + SUB lr, lr, #4 // Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} // Store other registers + + /* Return to the ISR. */ + + MOV r10, #0 // Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} // Save ISR lr + BL _tx_execution_isr_enter // Call the ISR enter function + POP {lr} // Recover ISR lr +#endif + + B __tx_fiq_processing_return // Continue FIQ processing + +__tx_thread_fiq_not_nested_save: + /* } */ + + /* Otherwise, not nested, check to see if a thread was running. */ + /* else if (_tx_thread_current_ptr) */ + /* { */ + + ADD r2, r2, #1 // Increment the interrupt counter + STR r2, [r3] // Store it back in the variable + LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr + LDR r0, [r1] // Pickup current thread pointer + CMP r0, #0 // Is it NULL? + BEQ __tx_thread_fiq_idle_system_save // If so, interrupt occurred in + // scheduling loop - nothing needs saving! + + /* Save minimal context of interrupted thread. */ + + MRS r2, SPSR // Pickup saved SPSR + SUB lr, lr, #4 // Adjust point of interrupt + STMDB sp!, {r2, lr} // Store other registers, Note that we don't + // need to save sl and ip since FIQ has + // copies of these registers. Nested + // interrupt processing does need to save + // these registers. + + /* Save the current stack pointer in the thread's control block. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ + + /* Switch to the system stack. */ + /* sp = _tx_thread_system_stack_ptr; */ + + MOV r10, #0 // Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} // Save ISR lr + BL _tx_execution_isr_enter // Call the ISR enter function + POP {lr} // Recover ISR lr +#endif + + B __tx_fiq_processing_return // Continue FIQ processing + + /* } */ + /* else */ + /* { */ + +__tx_thread_fiq_idle_system_save: + + /* Interrupt occurred in the scheduling loop. */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} // Save ISR lr + BL _tx_execution_isr_enter // Call the ISR enter function + POP {lr} // Recover ISR lr +#endif + + /* Not much to do here, save the current SPSR and LR for possible + use in IRQ interrupted in idle system conditions, and return to + FIQ interrupt processing. */ + + MRS r0, SPSR // Pickup saved SPSR + SUB lr, lr, #4 // Adjust point of interrupt + STMDB sp!, {r0, lr} // Store other registers that will get used + // or stripped off the stack in context + // restore + B __tx_fiq_processing_return // Continue FIQ processing + + /* } */ +/* } */ + +#endif diff --git a/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_fiq_nesting_end.S b/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_fiq_nesting_end.S new file mode 100644 index 00000000..58dad6f1 --- /dev/null +++ b/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_fiq_nesting_end.S @@ -0,0 +1,108 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" */ +/* #include "tx_thread.h" */ + +#define FIQ_MODE 0x11 // FIQ Mode bits + +#ifdef TX_THUMB_MODE + .thumb +#else + .arm +#endif + .text + .eabi_attribute Tag_ABI_align_preserved, 1 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_nesting_end Cortex-R4/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from FIQ mode after */ +/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +/* processing from system mode back to FIQ mode prior to the ISR */ +/* calling _tx_thread_fiq_context_restore. Note that this function */ +/* assumes the system stack pointer is in the same position after */ +/* nesting start function was called. */ +/* */ +/* This function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.s). */ +/* */ +/* This function returns with FIQ interrupts disabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_fiq_nesting_end(VOID) */ +/* { */ + .global _tx_thread_fiq_nesting_end + .type _tx_thread_fiq_nesting_end, "function" +_tx_thread_fiq_nesting_end: + MOV r3, lr // Save ISR return address + + #ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Disable IRQ and FIQ interrupts + #else + CPSID i // Disable IRQ interrupts + #endif + + LDMIA sp!, {r1, lr} // Pickup saved lr (and r1 throw-away for + // 8-byte alignment logic) + CPS #FIQ_MODE // Switch back to FIQ mode + BX r3 // Return to caller +/* } */ + + + diff --git a/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_fiq_nesting_start.S b/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_fiq_nesting_start.S new file mode 100644 index 00000000..a4ccd9f3 --- /dev/null +++ b/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_fiq_nesting_start.S @@ -0,0 +1,96 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" */ +/* #include "tx_thread.h" */ + +#define SYS_MODE 0x12 // System mode + +#ifdef TX_THUMB_MODE + .thumb +#else + .arm +#endif + .text + .eabi_attribute Tag_ABI_align_preserved, 1 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fiq_nesting_start Cortex-R4/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from FIQ mode after */ +/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +/* processing to the system mode so nested FIQ interrupt processing */ +/* is possible (system mode has its own "lr" register). Note that */ +/* this function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.s). */ +/* */ +/* This function returns with FIQ interrupts enabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_fiq_nesting_start(VOID) */ +/* { */ + .global _tx_thread_fiq_nesting_start + .type _tx_thread_fiq_nesting_start, "function" +_tx_thread_fiq_nesting_start: + MOV r3, lr // Save ISR return address + CPS #SYS_MODE // Switch to system mode + STMDB sp!, {r1, lr} // Push the system mode lr on the system mode stack + // and push r1 just to keep 8-byte alignment + CPSIE f // Enable FIQ interrupts + BX r3 // Return to caller +/* } */ diff --git a/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..e8c2259c --- /dev/null +++ b/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_interrupt_control.S @@ -0,0 +1,102 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" */ +/* #include "tx_thread.h" */ + + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define INT_MASK 0xC0 // Interrupt bit mask +#else +#define INT_MASK 0x80 // Interrupt bit mask +#endif + + +#ifdef TX_THUMB_MODE + .thumb +#else + .arm +#endif + .text + .eabi_attribute Tag_ABI_align_preserved, 1 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control Cortex-R4/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_control(UINT new_posture) */ +/* { */ + .global _tx_thread_interrupt_control + .type _tx_thread_interrupt_control, "function" +_tx_thread_interrupt_control: + + /* Pickup current interrupt lockout posture. */ + + MRS r3, CPSR // Pickup current CPSR + BIC r1, r3, #INT_MASK // Clear interrupt lockout bits + ORR r1, r1, r0 // Or-in new interrupt lockout bits + + /* Apply the new interrupt posture. */ + + MSR CPSR_c, r1 // Setup new CPSR + AND r0, r3, #INT_MASK // Return previous interrupt mask + BX lr // Return to caller + +/* } */ diff --git a/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_interrupt_disable.S new file mode 100644 index 00000000..35e9aad5 --- /dev/null +++ b/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_interrupt_disable.S @@ -0,0 +1,96 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" */ +/* #include "tx_thread.h" */ + + +#ifdef TX_THUMB_MODE + .thumb +#else + .arm +#endif + .text + .eabi_attribute Tag_ABI_align_preserved, 1 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_disable Cortex-R4/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for disabling interrupts */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_disable(void) */ +/* { */ + .global _tx_thread_interrupt_disable + .type _tx_thread_interrupt_disable, "function" +_tx_thread_interrupt_disable: + + /* Pickup current interrupt lockout posture. */ + + MRS r0, CPSR // Pickup current CPSR + + /* Mask interrupts. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Disable IRQ and FIQ +#else + CPSID i // Disable IRQ +#endif + + BX lr // Return to caller + +/* } */ diff --git a/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_interrupt_restore.S new file mode 100644 index 00000000..24e04df0 --- /dev/null +++ b/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_interrupt_restore.S @@ -0,0 +1,90 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" */ +/* #include "tx_thread.h" */ + + +#ifdef TX_THUMB_MODE + .thumb +#else + .arm +#endif + .text + .eabi_attribute Tag_ABI_align_preserved, 1 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_restore Cortex-R4/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for restoring interrupts to the state */ +/* returned by a previous _tx_thread_interrupt_disable call. */ +/* */ +/* INPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_restore(UINT old_posture) */ +/* { */ + .global _tx_thread_interrupt_restore + .type _tx_thread_interrupt_restore, "function" +_tx_thread_interrupt_restore: + + /* Apply the new interrupt posture. */ + + MSR CPSR_c, r0 // Setup new CPSR + BX lr // Return to caller +/* } */ + + + diff --git a/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_irq_nesting_end.S b/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_irq_nesting_end.S new file mode 100644 index 00000000..5e3c5794 --- /dev/null +++ b/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_irq_nesting_end.S @@ -0,0 +1,105 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" */ +/* #include "tx_thread.h" */ + +#define IRQ_MODE 0x12 // IRQ Mode bits + +#ifdef TX_THUMB_MODE + .thumb +#else + .arm +#endif + .text + .eabi_attribute Tag_ABI_align_preserved, 1 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_irq_nesting_end Cortex-R4/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from IRQ mode after */ +/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +/* processing from system mode back to IRQ mode prior to the ISR */ +/* calling _tx_thread_context_restore. Note that this function */ +/* assumes the system stack pointer is in the same position after */ +/* nesting start function was called. */ +/* */ +/* This function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.s). */ +/* */ +/* This function returns with IRQ interrupts disabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_irq_nesting_end(VOID) */ +/* { */ + .global _tx_thread_irq_nesting_end + .type _tx_thread_irq_nesting_end, "function" +_tx_thread_irq_nesting_end: + MOV r3, lr // Save ISR return address + + #ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Disable IRQ and FIQ interrupts + #else + CPSID i // Disable IRQ interrupts + #endif + + LDMIA sp!, {r1, lr} // Pickup saved lr (and r1 throw-away for + // 8-byte alignment logic) + CPS #IRQ_MODE // Switch back to IRQ mode + BX r3 // Return to caller +/* } */ diff --git a/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_irq_nesting_start.S b/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_irq_nesting_start.S new file mode 100644 index 00000000..84f55aca --- /dev/null +++ b/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_irq_nesting_start.S @@ -0,0 +1,96 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" */ +/* #include "tx_thread.h" */ + +#define SYS_MODE 0x1F // System mode bits + +#ifdef TX_THUMB_MODE + .thumb +#else + .arm +#endif + .text + .eabi_attribute Tag_ABI_align_preserved, 1 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_irq_nesting_start Cortex-R4/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the application from IRQ mode after */ +/* _tx_thread_context_save has been called and switches the IRQ */ +/* processing to the system mode so nested IRQ interrupt processing */ +/* is possible (system mode has its own "lr" register). Note that */ +/* this function assumes that the system mode stack pointer was setup */ +/* during low-level initialization (tx_initialize_low_level.s). */ +/* */ +/* This function returns with IRQ interrupts enabled. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_irq_nesting_start(VOID) */ +/* { */ + .global _tx_thread_irq_nesting_start + .type _tx_thread_irq_nesting_start, "function" +_tx_thread_irq_nesting_start: + MOV r3, lr // Save ISR return address + CPS #SYS_MODE // Switch to System Mode + STMDB sp!, {r1, lr} // Push the system mode lr on the system mode stack + // and push r1 just to keep 8-byte alignment + CPSIE i // Enable IRQ interrupts + BX r3 // Return to caller +/* } */ diff --git a/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_schedule.S new file mode 100644 index 00000000..bd37aff2 --- /dev/null +++ b/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_schedule.S @@ -0,0 +1,469 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" */ +/* #include "tx_thread.h" */ +/* #include "tx_timer.h" */ + + + .global _tx_thread_execute_ptr + .global _tx_thread_current_ptr + .global _tx_timer_time_slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + .global _tx_execution_thread_enter +#endif + +#define THUMB_MASK 0x20 // Thumb bit (5) of CPSR/SPSR. +#define IRQ_MODE 0x12 // IRQ mode +#define USR_MODE 0x10 // USR mode +#define SVC_MODE 0x13 // SVC mode +#define SYS_MODE 0x1F // SYS mode +#define MODE_MASK 0x1F // Mode mask + .arm + .text + .eabi_attribute Tag_ABI_align_preserved, 1 + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule Cortex-R4/MPU/ARM */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* _tx_thread_context_restore Restore thread's context */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_schedule(VOID) */ +/* { */ + .global _tx_thread_schedule + .type _tx_thread_schedule, "function" +_tx_thread_schedule: + + /* Enter the scheduler. */ + SVC 0 + + /* We should never get here - ever! */ +_tx_scheduler_fault__: + B _tx_scheduler_fault__ +/* } */ +/**************************************************************************/ + + +/**************************************************************************/ +/* SWI_Handler */ +/**************************************************************************/ + + .global SWI_Handler + .type SWI_Handler, "function" + .global __tx_svc_interrupt + .type __tx_svc_interrupt, "function" +SWI_Handler: +__tx_svc_interrupt: + STMFD sp!, {r0-r3, r12, lr} // Store the registers + MOV r1, sp // Set pointer to parameters + MRS r0, spsr // Get spsr + STMFD sp!, {r0, r3} // Store spsr onto stack and another + // register to maintain 8-byte-aligned stack + TST r0, #THUMB_MASK // Occurred in Thumb state? + LDRHNE r0, [lr,#-2] // Yes: Load halfword and... + BICNE r0, r0, #0xFF00 // ...extract comment field + LDREQ r0, [lr,#-4] // No: Load word and... + BICEQ r0, r0, #0xFF000000 // ...extract comment field + + // r0 now contains SVC number + // r1 now contains pointer to stacked registers + + CMP r0, #0 // Is it a schedule request? + BEQ _tx_handler_svc_schedule // Yes, go there + + CMP r0, #1 // Is it a system mode enter request? + BEQ _tx_handler_svc_super_enter // Yes, go there + + CMP r0, #2 // Is it a system mode exit request? + BEQ _tx_handler_svc_super_exit // Yes, go there + + LDR r2, =0x123456 + CMP r0, r2 // Is it an ARM request? + BEQ _tx_handler_svc_arm // Yes, go there + +/**************************************************************************/ +/* Unknown SVC argument */ +/**************************************************************************/ + /* Unrecognized service call */ +_tx_handler_svc_unrecognized: + +_tx_handler_svc_unrecognized_loop: /* We should never get here */ + B _tx_handler_svc_unrecognized_loop + + +/**************************************************************************/ +/* SVC 1 */ +/**************************************************************************/ + /* At this point we have an SVC 1, which means we are entering + supervisor mode to service a kernel call. */ +_tx_handler_svc_super_enter: + // Make sure that we have been called from the system mode enter location (security). + LDR r2, =_txm_system_mode_enter // Load the address of the known call point + SUB r1, lr, #4 // Calculate the address of the actual call + CMP r1, r2 // Did we come from txm_module_manager_user_mode_entry? + BNE _tx_handler_svc_unrecognized // Return to where we came + + // Clear the user mode flag in the thread structure. + LDR r1, =_tx_thread_current_ptr // Load the current thread pointer address + LDR r2, [r1] // Load current thread location from the pointer (pointer indirection) + MOV r1, #0 // Load the new user mode flag value (user mode flag clear -> not user mode -> system) + STR r1, [r2, #0x9C] // Clear the current user mode selection for thread + + // Now we enter the system mode and return. + LDMFD sp!, {r0, r3} // Get spsr from the stack + BIC r0, r0, #MODE_MASK // clear mode field + ORR r0, r0, #SYS_MODE // system mode code + MSR SPSR_cxsf, r0 // Restore the spsr + + LDR r1, [r2, #0xA8] // Load the module kernel stack pointer + CPS #SYS_MODE // Switch to SYS mode + MOV r3, sp // Grab thread stack pointer + MOV sp, r1 // Set SP to kernel stack pointer + CPS #SVC_MODE // Switch back to SVC mode + STR r3, [r2, #0xB0] // Save thread stack pointer +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + LDR r3, [r2, #0xAC] // Load the module kernel stack size + STR r3, [r2, #20] // Set stack size + LDRD r0, r1, [r2, #0xA4] // Load the module kernel stack start and end + STRD r0, r1, [r2, #0x0C] // Set stack start and end +#endif + LDMFD sp!, {r0-r3, r12, pc}^ // Restore the registers and return + +/**************************************************************************/ +/* SVC 2 */ +/**************************************************************************/ + /* At this point we have an SVC 2, which means we are exiting + supervisor mode after servicing a kernel call. */ +_tx_handler_svc_super_exit: + // Make sure that we have been called from the system mode exit location (security). + LDR r2, =_txm_system_mode_exit // Load the address of the known call point + SUB r1, lr, #4 // Calculate the address of the actual call + CMP r1, r2 // Did we come from txm_module_manager_user_mode_entry? + BNE _tx_handler_svc_unrecognized // Return to where we came + + // Set the user mode flag into the thread structure. + LDR r1, =_tx_thread_current_ptr // Load the current thread pointer address + LDR r2, [r1] // Load the current thread location from the pointer (pointer indirection) + MOV r1, #1 // Load the new user mode flag value (user mode enabled -> not system anymore) + STR r1, [r2, #0x9C] // Clear the current user mode selection for thread + + // Now we enter user mode (exit the system mode) and return. + LDMFD sp!, {r0, r3} // Get spsr from the stack + BIC r0, r0, #MODE_MASK // clear mode field + ORR r0, r0, #USR_MODE // user mode code + MSR SPSR_cxsf, r0 // Restore the spsr + + LDR r1, [r2, #0xB0] // Load the module thread stack pointer + CPS #SYS_MODE // Switch to SYS mode + MOV sp, r1 // Set SP back to thread stack pointer + CPS #SVC_MODE // Switch back to SVC mode +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + LDR r3, [r2, #0xBC] // Load the module thread stack size + STR r3, [r2, #20] // Set stack size + LDRD r0, r1, [r2, #0xB4] // Load the module thread stack start and end + STRD r0, r1, [r2, #0x0C] // Set stack start and end +#endif + LDMFD sp!, {r0-r3, r12, pc}^ // Restore the registers and return + +/**************************************************************************/ +/* ARM Semihosting */ +/**************************************************************************/ +_tx_handler_svc_arm: + + /**** TODO: handle semihosting requests or ARM angel requests ****/ + + /* Just return. */ + LDMFD sp!, {r0, r3} // Get spsr from the stack + MSR SPSR_cxsf, r0 // Restore the spsr + LDMFD sp!, {r0-r3, r12, pc}^ // Restore the registers and return + +/**************************************************************************/ +/* SVC 0 */ +/**************************************************************************/ + /* At this point we have an SVC 0: enter the scheduler. */ +_tx_handler_svc_schedule: + + LDMFD sp!, {r0, r3} // Get spsr from stack + MSR SPSR_cxsf, r0 // Restore spsr + LDMFD sp!, {r0-r3, r12, lr} // Restore the registers + + /* This code waits for a thread control block pointer to appear in + the _tx_thread_execute_ptr variable. Once a thread pointer appears + in the variable, the corresponding thread is resumed. */ + + /* Enable interrupts. */ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSIE if // Enable IRQ and FIQ interrupts +#else + CPSIE i // Enable IRQ interrupts +#endif + + /* Wait for a thread to execute. */ + /* do */ + /* { */ + LDR r1, =_tx_thread_execute_ptr // Address of thread execute ptr + +__tx_thread_schedule_loop: + + LDR r0, [r1, #0] // Pickup next thread to execute + CMP r0, #0 // Is it NULL? + BEQ __tx_thread_schedule_loop // If so, keep looking for a thread + + /* } */ + /* while(_tx_thread_execute_ptr == TX_NULL); */ + + /* Yes! We have a thread to execute. Lockout interrupts and + transfer control to it. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Disable IRQ and FIQ interrupts +#else + CPSID i // Disable IRQ interrupts +#endif + + /* Setup the current thread pointer. */ + /* _tx_thread_current_ptr = _tx_thread_execute_ptr; */ + + LDR r1, =_tx_thread_current_ptr // Pickup address of current thread + STR r0, [r1, #0] // Setup current thread pointer + + /* Increment the run count for this thread. */ + /* _tx_thread_current_ptr -> tx_thread_run_count++; */ + + LDR r2, [r0, #4] // Pickup run counter + LDR r3, [r0, #24] // Pickup time-slice for this thread + ADD r2, r2, #1 // Increment thread run-counter + STR r2, [r0, #4] // Store the new run counter + + /* Setup time-slice, if present. */ + /* _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; */ + + LDR r2, =_tx_timer_time_slice // Pickup address of time slice variable + STR r3, [r2, #0] // Setup time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread entry function to indicate the thread is executing. */ + + MOV r5, r0 // Save r0 + BL _tx_execution_thread_enter // Call the thread execution enter function + MOV r0, r5 // Restore r0 +#endif + + /* Determine if an interrupt frame or a synchronous task suspension frame is present. */ + CPS #SYS_MODE // Enter SYS mode + LDR sp, [r0, #8] // Switch to thread stack pointer + LDMIA sp!, {r4, r5} // Pickup the stack type and saved CPSR + CPS #SVC_MODE // Enter SVC mode + + /***************************************************************************/ + /* Set up MPU for module. */ + LDR r1, [r0, #0x94] // Pickup module instance pointer + CMP r1, #0 // Valid module pointer? + BEQ _tx_end_mpu_update // No - skip memory protection setup + LDR r2, [r0, #0xA0] // Pickup tx_thread_module_user_mode + CMP r2, #1 // In user mode? + BNE _tx_end_mpu_update // No - skip memory protection setup + /* Is the MPU already set up for this module? */ + /* Pickup the first data entry to check (txm_module_instance_mpu_registers[5]) */ + LDR r2, [r1, #0xA0] // Pickup txm_module_instance_mpu_registers[5] + MOV r3, #5 // Select region 5 + MCR p15, 0, r3, c6, c2, 0 // Select region 5 + MRC p15, 0, r3, c6, c1, 0 // Read DRBAR into r3 + CMP r2, r3 // Is module already loaded? + BEQ _tx_end_mpu_update // Yes - skip memory protection setup + + /* Disable MPU before applying new regions. */ + MRC p15, 0, r2, c1, c0, 0 // Read SCTLR + BIC r2, r2, #1 // Disable MPU + DSB + MCR p15, 0, r2, c1, c0, 0 // Write to SCTLR + ISB + /* Loop to load MPU registers */ + MOV r3, #0 // Loop index + ADD r1, r1, #0x64 // Build address of MPU register table +_tx_mpu_loop: + LDR r2, [r1] // Pickup txm_module_mpu_region_address + MCR p15, 0, r3, c6, c2, 0 // Select region + MCR p15, 0, r2, c6, c1, 0 // Write to DRBAR + ADD r1, r1, #4 // Increment to next MPU parameter + LDR r2, [r1] // Pickup txm_module_mpu_region_size + MCR p15, 0, r2, c6, c1, 2 // Write to DRSR + ADD r1, r1, #4 // Increment to next MPU parameter + LDR r2, [r1] // Pickup txm_module_mpu_region_attributes + MCR p15, 0, r2, c6, c1, 4 // Write to DRACR + ADD r1, r1, #4 // Increment to next MPU parameter + ADD r3, r3, #1 // Increment loop index + CMP r3, #0xB // Check the limit + BLE _tx_mpu_loop // Loop if not finished + + /* Enable MPU with new regions. */ + MRC p15, 0, r2, c1, c0, 0 // Read SCTLR + ORR r2, r2, #1 // Enable MPU + ORR r2, r2, #0x20000 // Enable Background Region + DSB + MCR p15, 0, r2, c1, c0, 0 // Write to SCTLR + ISB + +_tx_end_mpu_update: + /***************************************************************************/ + + CMP r4, #0 // Check for synchronous context switch + BEQ _tx_solicited_return + + MSR SPSR_cxsf, r5 // Setup SPSR for return + LDR r1, [r0, #8] // Get thread SP + LDR lr, [r1, #0x40] // Get thread PC + CPS #SYS_MODE // Enter SYS mode + +#ifdef __ARM_FP + LDR r2, [r0, #144] // Pickup the VFP enabled flag + CMP r2, #0 // Is the VFP enabled? + BEQ _tx_skip_interrupt_vfp_restore // No, skip VFP interrupt restore + VLDMIA sp!, {D0-D15} // Recover D0-D15 + LDR r4, [sp], #4 // Pickup FPSCR + VMSR FPSCR, r4 // Restore FPSCR + CPS #SVC_MODE // Enter SVC mode + LDR lr, [r1, #0x144] // Get thread PC + CPS #SYS_MODE // Enter SYS mode +_tx_skip_interrupt_vfp_restore: +#endif + + LDMIA sp!, {r0-r12, lr} // Restore registers + ADD sp, sp, #4 // Fix stack pointer + CPS #SVC_MODE // Enter SVC mode + SUBS pc, lr, #0 // Return to point of thread interrupt + +_tx_solicited_return: + MOV r2, r5 // Move CPSR to scratch register + CPS #SYS_MODE // Enter SYS mode + +#ifdef __ARM_FP + LDR r1, [r0, #144] // Pickup the VFP enabled flag + CMP r1, #0 // Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_restore // No, skip VFP solicited restore + VLDMIA sp!, {D8-D15} // Recover D8-D15 + LDR r4, [sp], #4 // Pickup FPSCR + VMSR FPSCR, r4 // Restore FPSCR +_tx_skip_solicited_vfp_restore: +#endif + + LDMIA sp!, {r4-r11, lr} // Restore registers + MOV r1, lr // Copy lr to r1 to preserve across mode change + CPS #SVC_MODE // Enter SVC mode + TST r1, #1 // Test LSB to see if we're returning to Thumb mode + ORRNE r2, r2, #THUMB_MASK // If so, set Thumb bit + BICEQ r2, r2, #THUMB_MASK // If not, clear Thumb bit + MSR SPSR_cxsf, r2 // Recover CPSR + MOV lr, r1 // Move r1 back to lr for a proper exception return + SUBS pc, lr, #0 // Return to thread synchronously + +/**************************************************************************/ +/* End __tx_svc_interrupt */ +/**************************************************************************/ + + + + + +#ifdef __ARM_FP + .global tx_thread_vfp_enable + .type tx_thread_vfp_enable, "function" +tx_thread_vfp_enable: + MRS r2, CPSR // Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Disable IRQ and FIQ interrupts +#else + CPSID i // Disable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r0] // Pickup current thread pointer + CMP r1, #0 // Check for NULL thread pointer + BEQ __tx_no_thread_to_enable // If NULL, skip VFP enable + MOV r0, #1 // Build enable value + STR r0, [r1, #144] // Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_enable: + MSR CPSR_cxsf, r2 // Recover CPSR + BX LR // Return to caller + + .global tx_thread_vfp_disable + .type tx_thread_vfp_disable, "function" +tx_thread_vfp_disable: + MRS r2, CPSR // Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Disable IRQ and FIQ interrupts +#else + CPSID i // Disable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r0] // Pickup current thread pointer + CMP r1, #0 // Check for NULL thread pointer + BEQ __tx_no_thread_to_disable // If NULL, skip VFP disable + MOV r0, #0 // Build disable value + STR r0, [r1, #144] // Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_disable: + MSR CPSR_cxsf, r2 // Recover CPSR + BX LR // Return to caller +#endif diff --git a/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_stack_build.S new file mode 100644 index 00000000..f3d4ac6c --- /dev/null +++ b/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_stack_build.S @@ -0,0 +1,164 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" */ +/* #include "tx_thread.h" */ + + +#define SYS_MODE 0x1F // SYS mode +#define THUMB_BIT 0x20 // Thumb-bit + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define CPSR_MASK 0xDF // Mask initial CPSR, IRQ & FIQ ints enabled +#else +#define CPSR_MASK 0x9F // Mask initial CPSR, IRQ ints enabled +#endif + +#ifdef TX_THUMB_MODE + .thumb +#else + .arm +#endif + .text + .eabi_attribute Tag_ABI_align_preserved, 1 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build Cortex-R4/MPU/ARM */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) */ +/* { */ + .global _tx_thread_stack_build + .type _tx_thread_stack_build, "function" +_tx_thread_stack_build: + + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-R4 should look like the following after it is built: + + Stack Top: 1 Interrupt stack frame type + CPSR Initial value for CPSR + a1 (r0) Initial value for a1 + a2 (r1) Initial value for a2 + a3 (r2) Initial value for a3 + a4 (r3) Initial value for a4 + v1 (r4) Initial value for v1 + v2 (r5) Initial value for v2 + v3 (r6) Initial value for v3 + v4 (r7) Initial value for v4 + v5 (r8) Initial value for v5 + sb (r9) Initial value for sb + sl (r10) Initial value for sl + fp (r11) Initial value for fp + ip (r12) Initial value for ip + lr (r14) Initial value for lr + pc (r15) Initial value for pc + 0 For stack backtracing */ + + /* Stack Bottom: (higher memory address) */ + + LDR r2, [r0, #16] // Pickup end of stack area + BIC r2, r2, #7 // Ensure 8-byte alignment + SUB r2, r2, #76 // Allocate space for the stack frame + + /* Actually build the stack frame. */ + + MOV r3, #1 // Build interrupt stack type + STR r3, [r2, #0] // Store stack type + MOV r3, #0 // Build initial register value + STR r3, [r2, #8] // Store initial r0 + STR r3, [r2, #12] // Store initial r1 + STR r3, [r2, #16] // Store initial r2 + STR r3, [r2, #20] // Store initial r3 + STR r3, [r2, #24] // Store initial r4 + STR r3, [r2, #28] // Store initial r5 + STR r3, [r2, #32] // Store initial r6 + STR r3, [r2, #36] // Store initial r7 + STR r3, [r2, #40] // Store initial r8 + STR r3, [r2, #44] // Store initial r9 + LDR r3, [r0, #12] // Pickup stack starting address + STR r3, [r2, #48] // Store initial r10 (sl) + MOV r3, #0 // Build initial register value + STR r3, [r2, #52] // Store initial r11 + STR r3, [r2, #56] // Store initial r12 + STR r3, [r2, #60] // Store initial lr + STR r1, [r2, #64] // Store initial pc + STR r3, [r2, #68] // 0 for back-trace + + MRS r3, CPSR // Pickup CPSR + BIC r3, r3, #CPSR_MASK // Mask mode bits of CPSR + ORR r3, r3, #SYS_MODE // Build CPSR, SYS mode, interrupts enabled + + TST r1, 1 // Test if Thumb bit is set in entry function address + ITE NE + ORRNE r3, r3, #THUMB_BIT // Yes, set the Thumb bit + BICEQ r3, r3, #THUMB_BIT // No, clear the Thumb bit + STR r3, [r2, #4] // Store initial CPSR + + /* Setup stack pointer. */ + /* thread_ptr -> tx_thread_stack_ptr = r2; */ + + STR r2, [r0, #8] // Save stack pointer in thread's + // control block + BX lr // Return to caller +/* } */ diff --git a/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_system_return.S new file mode 100644 index 00000000..ecc3d388 --- /dev/null +++ b/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_system_return.S @@ -0,0 +1,162 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" */ +/* #include "tx_thread.h" */ +/* #include "tx_timer.h" */ + + + .global _tx_thread_current_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + .global _tx_execution_thread_exit +#endif + + +#ifdef TX_THUMB_MODE + .thumb +#else + .arm +#endif + .text + .eabi_attribute Tag_ABI_align_preserved, 1 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return Cortex-R4/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the ThreadX system. Only a */ +/* minimal context is saved since the compiler assumes temp registers */ +/* are going to get slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_system_return(VOID) */ +/* { */ + .global _tx_thread_system_return + .type _tx_thread_system_return, "function" +_tx_thread_system_return: + + /* Save minimal context on the stack. */ + + STMDB sp!, {r4-r11, lr} // Save minimal context + LDR r5, =_tx_thread_current_ptr // Pickup address of current ptr + LDR r6, [r5, #0] // Pickup current thread pointer + +#ifdef __ARM_FP + LDR r0, [r6, #144] // Pickup the VFP enabled flag + CMP r0, #0 // Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_save // No, skip VFP solicited save + VMRS r4, FPSCR // Pickup the FPSCR + STR r4, [sp, #-4]! // Save FPSCR + VSTMDB sp!, {D8-D15} // Save D8-D15 +_tx_skip_solicited_vfp_save: +#endif + + MOV r0, #0 // Build a solicited stack type + MRS r1, CPSR // Pickup the CPSR + STMDB sp!, {r0-r1} // Save type and CPSR + + /* Lockout interrupts. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Disable IRQ and FIQ interrupts +#else + CPSID i // Disable IRQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread exit function to indicate the thread is no longer executing. */ + + BL _tx_execution_thread_exit // Call the thread exit function +#endif + LDR r2, =_tx_timer_time_slice // Pickup address of time slice + LDR r1, [r2, #0] // Pickup current time slice + + /* Save current stack and switch to system stack. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ + /* sp = _tx_thread_system_stack_ptr; */ + + STR sp, [r6, #8] // Save thread stack pointer + + /* Determine if the time-slice is active. */ + /* if (_tx_timer_time_slice) */ + /* { */ + + MOV r4, #0 // Build clear value + CMP r1, #0 // Is a time-slice active? + BEQ __tx_thread_dont_save_ts // No, don't save the time-slice + + /* Save the current remaining time-slice. */ + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; */ + /* _tx_timer_time_slice = 0; */ + + STR r4, [r2, #0] // Clear time-slice + STR r1, [r6, #24] // Store current time-slice + + /* } */ +__tx_thread_dont_save_ts: + + /* Clear the current thread pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + STR r4, [r5, #0] // Clear current thread pointer + + B _tx_thread_schedule // Jump to scheduler! + +/* } */ diff --git a/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_vectored_context_save.S b/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_vectored_context_save.S new file mode 100644 index 00000000..c070adae --- /dev/null +++ b/ports_module/cortex-r4/ac6/module_manager/src/tx_thread_vectored_context_save.S @@ -0,0 +1,193 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" */ +/* #include "tx_thread.h" */ + + + .global _tx_thread_system_state + .global _tx_thread_current_ptr +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + .global _tx_execution_isr_enter +#endif + + +#ifdef TX_THUMB_MODE + .thumb +#else + .arm +#endif + .text + .eabi_attribute Tag_ABI_align_preserved, 1 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_vectored_context_save Cortex-R4/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_vectored_context_save(VOID) */ +/* { */ + .global _tx_thread_vectored_context_save + .type _tx_thread_vectored_context_save, "function" +_tx_thread_vectored_context_save: + + /* Upon entry to this routine, it is assumed that IRQ interrupts are locked + out, we are in IRQ mode, and all registers are intact. */ + + /* Check for a nested interrupt condition. */ + /* if (_tx_thread_system_state++) */ + /* { */ + +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if // Disable IRQ and FIQ interrupts +#endif + LDR r3, =_tx_thread_system_state // Pickup address of system state var + LDR r2, [r3, #0] // Pickup system state + CMP r2, #0 // Is this the first interrupt? + BEQ __tx_thread_not_nested_save // Yes, not a nested context save + + /* Nested interrupt condition. */ + + ADD r2, r2, #1 // Increment the interrupt counter + STR r2, [r3, #0] // Store it back in the variable + + /* Note: Minimal context of interrupted thread is already saved. */ + + /* Return to the ISR. */ + + MOV r10, #0 // Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} // Save ISR lr + BL _tx_execution_isr_enter // Call the ISR enter function + POP {lr} // Recover ISR lr +#endif + + BX lr // Return to caller + + +__tx_thread_not_nested_save: + /* } */ + + /* Otherwise, not nested, check to see if a thread was running. */ + /* else if (_tx_thread_current_ptr) */ + /* { */ + + ADD r2, r2, #1 // Increment the interrupt counter + STR r2, [r3, #0] // Store it back in the variable + LDR r1, =_tx_thread_current_ptr // Pickup address of current thread ptr + LDR r0, [r1, #0] // Pickup current thread pointer + CMP r0, #0 // Is it NULL? + BEQ __tx_thread_idle_system_save // If so, interrupt occurred in + // scheduling loop - nothing needs saving! + + /* Note: Minimal context of interrupted thread is already saved. */ + + /* Save the current stack pointer in the thread's control block. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ + + /* Switch to the system stack. */ + /* sp = _tx_thread_system_stack_ptr; */ + + MOV r10, #0 // Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} // Save ISR lr + BL _tx_execution_isr_enter // Call the ISR enter function + POP {lr} // Recover ISR lr +#endif + + BX lr // Return to caller + + /* } */ + /* else */ + /* { */ + +__tx_thread_idle_system_save: + + /* Interrupt occurred in the scheduling loop. */ + + /* Not much to do here, just adjust the stack pointer, and return to IRQ + processing. */ + + MOV r10, #0 // Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + PUSH {lr} // Save ISR lr + BL _tx_execution_isr_enter // Call the ISR enter function + POP {lr} // Recover ISR lr +#endif + + ADD sp, sp, #32 // Recover saved registers + + BX lr // Return to caller + + /* } */ +/* } */ diff --git a/ports_module/cortex-r4/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex-r4/ac6/module_manager/src/tx_timer_interrupt.S new file mode 100644 index 00000000..12bb4a5d --- /dev/null +++ b/ports_module/cortex-r4/ac6/module_manager/src/tx_timer_interrupt.S @@ -0,0 +1,257 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* #include "tx_api.h" */ +/* #include "tx_timer.h" */ +/* #include "tx_thread.h" */ + + +/* Define Assembly language external references... */ + + .global _tx_timer_time_slice + .global _tx_timer_system_clock + .global _tx_timer_current_ptr + .global _tx_timer_list_start + .global _tx_timer_list_end + .global _tx_timer_expired_time_slice + .global _tx_timer_expired + .global _tx_thread_time_slice + .global _tx_timer_expiration_process + + +#ifdef TX_THUMB_MODE + .thumb +#else + .arm +#endif + .text + .eabi_attribute Tag_ABI_align_preserved, 1 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt Cortex-R4/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_timer_interrupt(VOID) */ +/* { */ + .global _tx_timer_interrupt + .type _tx_timer_interrupt, "function" +_tx_timer_interrupt: + + /* Upon entry to this routine, it is assumed that context save has already + been called, and therefore the compiler scratch registers are available + for use. */ + + /* Increment the system clock. */ + /* _tx_timer_system_clock++; */ + + LDR r1, =_tx_timer_system_clock // Pickup address of system clock + LDR r0, [r1, #0] // Pickup system clock + ADD r0, r0, #1 // Increment system clock + STR r0, [r1, #0] // Store new system clock + + /* Test for time-slice expiration. */ + /* if (_tx_timer_time_slice) */ + /* { */ + + LDR r3, =_tx_timer_time_slice // Pickup address of time-slice + LDR r2, [r3, #0] // Pickup time-slice + CMP r2, #0 // Is it non-active? + BEQ __tx_timer_no_time_slice // Yes, skip time-slice processing + + /* Decrement the time_slice. */ + /* _tx_timer_time_slice--; */ + + SUB r2, r2, #1 // Decrement the time-slice + STR r2, [r3, #0] // Store new time-slice value + + /* Check for expiration. */ + /* if (__tx_timer_time_slice == 0) */ + + CMP r2, #0 // Has it expired? + BNE __tx_timer_no_time_slice // No, skip expiration processing + + /* Set the time-slice expired flag. */ + /* _tx_timer_expired_time_slice = TX_TRUE; */ + + LDR r3, =_tx_timer_expired_time_slice // Pickup address of expired flag + MOV r0, #1 // Build expired value + STR r0, [r3, #0] // Set time-slice expiration flag + + /* } */ + +__tx_timer_no_time_slice: + + /* Test for timer expiration. */ + /* if (*_tx_timer_current_ptr) */ + /* { */ + + LDR r1, =_tx_timer_current_ptr // Pickup current timer pointer addr + LDR r0, [r1, #0] // Pickup current timer + LDR r2, [r0, #0] // Pickup timer list entry + CMP r2, #0 // Is there anything in the list? + BEQ __tx_timer_no_timer // No, just increment the timer + + /* Set expiration flag. */ + /* _tx_timer_expired = TX_TRUE; */ + + LDR r3, =_tx_timer_expired // Pickup expiration flag address + MOV r2, #1 // Build expired value + STR r2, [r3, #0] // Set expired flag + B __tx_timer_done // Finished timer processing + + /* } */ + /* else */ + /* { */ +__tx_timer_no_timer: + + /* No timer expired, increment the timer pointer. */ + /* _tx_timer_current_ptr++; */ + + ADD r0, r0, #4 // Move to next timer + + /* Check for wrap-around. */ + /* if (_tx_timer_current_ptr == _tx_timer_list_end) */ + + LDR r3, =_tx_timer_list_end // Pickup addr of timer list end + LDR r2, [r3, #0] // Pickup list end + CMP r0, r2 // Are we at list end? + BNE __tx_timer_skip_wrap // No, skip wrap-around logic + + /* Wrap to beginning of list. */ + /* _tx_timer_current_ptr = _tx_timer_list_start; */ + + LDR r3, =_tx_timer_list_start // Pickup addr of timer list start + LDR r0, [r3, #0] // Set current pointer to list start + +__tx_timer_skip_wrap: + + STR r0, [r1, #0] // Store new current timer pointer + /* } */ + +__tx_timer_done: + + + /* See if anything has expired. */ + /* if ((_tx_timer_expired_time_slice) (_tx_timer_expired)) */ + /* { */ + + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of expired flag + LDR r2, [r3, #0] // Pickup time-slice expired flag + CMP r2, #0 // Did a time-slice expire? + BNE __tx_something_expired // If non-zero, time-slice expired + LDR r1, =_tx_timer_expired // Pickup addr of other expired flag + LDR r0, [r1, #0] // Pickup timer expired flag + CMP r0, #0 // Did a timer expire? + BEQ __tx_timer_nothing_expired // No, nothing expired + +__tx_something_expired: + + + STMDB sp!, {r0, lr} // Save the lr register on the stack + // and save r0 just to keep 8-byte alignment + + /* Did a timer expire? */ + /* if (_tx_timer_expired) */ + /* { */ + + LDR r1, =_tx_timer_expired // Pickup addr of expired flag + LDR r0, [r1, #0] // Pickup timer expired flag + CMP r0, #0 // Check for timer expiration + BEQ __tx_timer_dont_activate // If not set, skip timer activation + + /* Process timer expiration. */ + /* _tx_timer_expiration_process(); */ + + BL _tx_timer_expiration_process // Call the timer expiration handling routine + + /* } */ +__tx_timer_dont_activate: + + /* Did time slice expire? */ + /* if (_tx_timer_expired_time_slice) */ + /* { */ + + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of time-slice expired + LDR r2, [r3, #0] // Pickup the actual flag + CMP r2, #0 // See if the flag is set + BEQ __tx_timer_not_ts_expiration // No, skip time-slice processing + + /* Time slice interrupted thread. */ + /* _tx_thread_time_slice(); */ + + BL _tx_thread_time_slice // Call time-slice processing + + /* } */ + +__tx_timer_not_ts_expiration: + + LDMIA sp!, {r0, lr} // Recover lr register (r0 is just there for + // the 8-byte stack alignment + + /* } */ + +__tx_timer_nothing_expired: + BX lr // Return to caller + +/* } */ diff --git a/ports_module/cortex-r4/ac6/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex-r4/ac6/module_manager/src/txm_module_manager_alignment_adjust.c new file mode 100644 index 00000000..0b412241 --- /dev/null +++ b/ports_module/cortex-r4/ac6/module_manager/src/txm_module_manager_alignment_adjust.c @@ -0,0 +1,189 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_power_of_two_block_size Cortex-R4/MPU/ARM */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calculates a power of two size at or immediately above*/ +/* the input size and returns it to the caller. */ +/* */ +/* INPUT */ +/* */ +/* size Block size */ +/* */ +/* OUTPUT */ +/* */ +/* calculated size Rounded up to power of two */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-R */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_power_of_two_block_size(ULONG size) +{ + /* Check for 0 size. */ + if(size == 0) + { + return 0; + } + + /* Minimum MPU block size is 32. */ + if(size <= 32) + { + return 32; + } + + /* Bit twiddling trick to round to next high power of 2 + (if original size is power of 2, it will return original size. Perfect!) */ + size--; + size |= size >> 1; + size |= size >> 2; + size |= size >> 4; + size |= size >> 8; + size |= size >> 16; + size++; + + /* Return a power of 2 size at or above the input size. */ + return(size); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_alignment_adjust Cortex-R4/MPU/ARM */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function adjusts the alignment and size of the code and data */ +/* section for a given module implementation. */ +/* */ +/* INPUT */ +/* */ +/* module_preamble Pointer to module preamble */ +/* code_size Size of the code area (updated) */ +/* code_alignment Code area alignment (updated) */ +/* data_size Size of data area (updated) */ +/* data_alignment Data area alignment (updated) */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_power_of_two_block_size Calculate power of two size */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, + ULONG *code_size, + ULONG *code_alignment, + ULONG *data_size, + ULONG *data_alignment) +{ + +ULONG local_code_size; +ULONG local_code_alignment; +ULONG local_data_size; +ULONG local_data_alignment; +ULONG code_size_accum; +ULONG data_size_accum; + + /* Copy the input parameters into local variables for ease of use. */ + local_code_size = *code_size; + local_code_alignment = *code_alignment; + local_data_size = *data_size; + local_data_alignment = *data_alignment; + + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + local_code_alignment = _txm_power_of_two_block_size(local_code_size) >> 2; + code_size_accum = local_code_alignment + local_code_alignment; + code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); + code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); + local_code_size = code_size_accum; + + /* Determine data block sizes. Minimize the alignment requirement. + There are 4 MPU data entries available. The following is how the data size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to data size. + 2. 1/4 of the largest power of two that is greater than or equal to data size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + local_data_alignment = _txm_power_of_two_block_size(local_data_size) >> 2; + data_size_accum = local_data_alignment + local_data_alignment; + data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); + data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); + local_data_size = data_size_accum; + + /* Return all the information to the caller. */ + *code_size = local_code_size; + *code_alignment = local_code_alignment; + *data_size = local_data_size; + *data_alignment = local_data_alignment; +} diff --git a/ports_module/cortex-r4/ac6/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex-r4/ac6/module_manager/src/txm_module_manager_external_memory_enable.c new file mode 100644 index 00000000..d58987c8 --- /dev/null +++ b/ports_module/cortex-r4/ac6/module_manager/src/txm_module_manager_external_memory_enable.c @@ -0,0 +1,189 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_mutex.h" +#include "tx_queue.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_external_memory_enable Cortex-R4/MPU/ARM */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function adds an entry in the MPU table for a shared */ +/* memory space. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* start_address Start address of memory */ +/* length Length of external memory */ +/* attributes Memory attributes (r/w) */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_mutex_get Get protection mutex */ +/* _tx_mutex_put Release protection mutex */ +/* _txm_power_of_two_block_size Round length to power of two */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, + VOID *start_address, + ULONG length, + UINT attributes) +{ + +ULONG block_size; +ULONG region_size; +ULONG srd_bits; +ULONG size_register; +ULONG address; +ULONG shared_index; +ULONG attributes_check = 0; + + /* Determine if the module manager has been initialized. */ + if (_txm_module_manager_ready != TX_TRUE) + { + /* Module manager has not been initialized. */ + return(TX_NOT_AVAILABLE); + } + + /* Determine if the module is valid. */ + if (module_instance == TX_NULL) + { + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Get module manager protection mutex. */ + _tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER); + + /* Determine if the module instance is valid. */ + if (module_instance -> txm_module_instance_id != TXM_MODULE_ID) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Determine if the module instance is in the loaded state. */ + if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if the module is not ready. */ + return(TX_START_ERROR); + } + + /* Determine if there are shared memory entries available. */ + if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* No more entries available. */ + return(TX_NO_MEMORY); + } + + /* Start address and length must adhere to Cortex-R MPU. + The address must align with the block size. */ + + block_size = _txm_power_of_two_block_size(length); + address = (ULONG) start_address; + if(address != (address & ~(block_size - 1))) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return alignment error. */ + return(TXM_MODULE_ALIGNMENT_ERROR); + } + + /* At this point, we have a valid address and block size. + Set up MPU registers. */ + + /* Generate index into shared memory entries. */ + shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; + + /* Save address register. */ + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address; + + /* Calculate the region size. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + /* Calculate the subregion bits. */ + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); + + /* Save size register. */ + size_register = srd_bits | region_size | TXM_ENABLE_REGION; + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_size = size_register; + + /* Check for optional attributes. */ + if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) + { + attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; + } + + /* Save attributes register. */ + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attributes = attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; + + /* Keep track of shared memory address and length in module instance. */ + module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; + module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; + + /* Increment counter. */ + module_instance -> txm_module_instance_shared_memory_count++; + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/ports_module/cortex-r4/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex-r4/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c new file mode 100644 index 00000000..29eab3c3 --- /dev/null +++ b/ports_module/cortex-r4/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -0,0 +1,112 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + +/* Define a macro that can be used to allocate global variables useful to + store information about the last fault. This macro is defined in + txm_module_port.h and is usually populated in the assembly language + fault handling prior to the code calling _txm_module_manager_memory_fault_handler. */ + +TXM_MODULE_MANAGER_FAULT_INFO + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_handler Cortex-R4/MPU/ARM */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles a fault associated with a memory protected */ +/* module. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_terminate Terminate thread */ +/* */ +/* CALLED BY */ +/* */ +/* Fault handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_memory_fault_handler(VOID) +{ + +TXM_MODULE_INSTANCE *module_instance_ptr; +TX_THREAD *thread_ptr; + + + /* Pickup the current thread. */ + thread_ptr = _tx_thread_current_ptr; + + /* Initialize the module instance pointer to NULL. */ + module_instance_ptr = TX_NULL; + + /* Is there a thread? */ + if (thread_ptr) + { + /* Pickup the module instance. */ + module_instance_ptr = thread_ptr -> tx_thread_module_instance_ptr; + + /* Terminate the current thread. */ + _tx_thread_terminate(_tx_thread_current_ptr); + } + + /* Determine if there is a user memory fault notification callback. */ + if (_txm_module_manager_fault_notify) + { + /* Yes, call the user's notification memory fault callback. */ + (_txm_module_manager_fault_notify)(thread_ptr, module_instance_ptr); + } +} + diff --git a/ports_module/cortex-r4/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex-r4/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c new file mode 100644 index 00000000..35ef0416 --- /dev/null +++ b/ports_module/cortex-r4/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -0,0 +1,85 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the external user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_notify Cortex-R4/MPU/ARM */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application callback when/if a memory */ +/* fault occurs. The supplied thread is automatically terminated, but */ +/* any other threads in the same module may still execute. */ +/* */ +/* INPUT */ +/* */ +/* notify_function Memory fault notification */ +/* function, NULL disables. */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +{ + /* Setup notification function. */ + _txm_module_manager_fault_notify = notify_function; + + /* Return success. */ + return(TX_SUCCESS); +} + diff --git a/ports_module/cortex-r4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex-r4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c new file mode 100644 index 00000000..524f67b5 --- /dev/null +++ b/ports_module/cortex-r4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c @@ -0,0 +1,538 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_region_size_get Cortex-R4/MPU/ARM */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function converts the region size in bytes to the block size */ +/* for the Cortex-R4 MPU specification. */ +/* */ +/* INPUT */ +/* */ +/* block_size Size of the block in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* MPU size specification */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_module_manager_region_size_get(ULONG block_size) +{ + +ULONG return_value; + + + /* Process relative to the input block size. */ + if (block_size == 32) + { + return_value = 0x04; + } + else if (block_size == 64) + { + return_value = 0x05; + } + else if (block_size == 128) + { + return_value = 0x06; + } + else if (block_size == 256) + { + return_value = 0x07; + } + else if (block_size == 512) + { + return_value = 0x08; + } + else if (block_size == 1024) + { + return_value = 0x09; + } + else if (block_size == 2048) + { + return_value = 0x0A; + } + else if (block_size == 4096) + { + return_value = 0x0B; + } + else if (block_size == 8192) + { + return_value = 0x0C; + } + else if (block_size == 16384) + { + return_value = 0x0D; + } + else if (block_size == 32768) + { + return_value = 0x0E; + } + else if (block_size == 65536) + { + return_value = 0x0F; + } + else if (block_size == 131072) + { + return_value = 0x10; + } + else if (block_size == 262144) + { + return_value = 0x11; + } + else if (block_size == 524288) + { + return_value = 0x12; + } + else if (block_size == 1048576) + { + return_value = 0x13; + } + else if (block_size == 2097152) + { + return_value = 0x14; + } + else + { + /* Max 4MB MPU pages for modules. */ + return_value = 0x15; + } + + return(return_value); +} + + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_calculate_srd_bits Cortex-R4/MPU/ARM */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calculates the SRD bits that need to be set to */ +/* protect "length" bytes in a block. */ +/* */ +/* INPUT */ +/* */ +/* block_size Size of the block in bytes */ +/* length Actual length in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* SRD bits to be OR'ed with region attribute register. */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) +{ + +ULONG srd_bits = 0; +UINT srd_bit_index; + + /* length is smaller than block_size, set SRD bits if block_size is 256 or more. */ + if((block_size >= 256) && (length < block_size)) + { + /* Divide block_size by 8 by shifting right 3. Result is size of subregion. */ + block_size = block_size >> 3; + + /* Set SRD index into attribute register. */ + srd_bit_index = 8; + + /* If subregion overlaps length, move to the next subregion. */ + while(length > block_size) + { + length = length - block_size; + srd_bit_index++; + } + + /* Check for a portion of code remaining. */ + if(length) + { + srd_bit_index++; + } + + /* Set unused subregion bits. */ + while(srd_bit_index < 16) + { + srd_bits = srd_bits | (0x1 << srd_bit_index); + srd_bit_index++; + } + } + + return(srd_bits); +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_mm_register_setup Cortex-R4/MPU/ARM */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets up the MPU register definitions based on the */ +/* module's memory characteristics. */ +/* MPU layout for the Cortex-R4: */ +/* Entry Description */ +/* 0 Kernel mode entry */ +/* 1 Module code region */ +/* 2 Module code region */ +/* 3 Module code region */ +/* 4 Module code region */ +/* 5 Module data region */ +/* 6 Module data region */ +/* 7 Module data region */ +/* 8 Module data region */ +/* 9 Module shared memory region */ +/* 10 Module shared memory region */ +/* 11 Module shared memory region */ +/* */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* */ +/* OUTPUT */ +/* */ +/* MPU specifications for module in module_instance */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_manager_region_size_get */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_thread_create */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) +{ + +ULONG code_address; +ULONG code_size; +ULONG data_address; +ULONG data_size; +ULONG start_stop_stack_size; +ULONG callback_stack_size; +ULONG block_size; +ULONG base_address_register; +ULONG size_register; +ULONG region_size; +ULONG srd_bits = 0; +UINT mpu_table_index; +UINT i; + + + /* Setup the first region for kernel mode entry. */ + + /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = (ULONG) _txm_module_manager_user_mode_entry; + + /* Set the size (32 bytes) and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_size = (_txm_module_manager_region_size_get(32) << 1) | TXM_ENABLE_REGION; + + /* Set attributes. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attributes = TXM_MODULE_MPU_CODE_ACCESS_CONTROL; + + /* End of kernel mode entry setup. */ + + /* Setup code protection. */ + + /* Initialize the MPU table index. */ + mpu_table_index = 1; + + /* Pickup code starting address and actual size. */ + code_address = (ULONG) module_instance -> txm_module_instance_code_start; + code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; + + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + + /* Now loop through to setup MPU protection for the code area. */ + for (i = 0; i < TXM_MODULE_MPU_CODE_ENTRIES; i++) + { + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + if (i < 2) + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + } + + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ + else if (i == 2) + { + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size) >> 1; + } + + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + else + { + /* Calculate remaining space. */ + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + + /* Build the base address register. */ + base_address_register = (code_address & ~(block_size - 1)); + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Build the size register. */ + size_register = srd_bits | region_size | TXM_ENABLE_REGION; + + /* Setup the MPU address, size, and attribute registers. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = base_address_register; + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_size = size_register; + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attributes = TXM_MODULE_MPU_CODE_ACCESS_CONTROL; + + /* Adjust the code address. */ + code_address = code_address + block_size; + + /* Increment MPU table index. */ + mpu_table_index++; + } + /* End of code protection. */ + + /* Setup data protection. */ + + /* Reset SRD bitfield. */ + srd_bits = 0; + + /* Pickup data starting address and actual size. */ + data_address = (ULONG) module_instance -> txm_module_instance_data_start; + + /* Adjust the size of the module elements to be aligned to the default alignment. We do this + so that when we partition the allocated memory, we can simply place these regions right beside + each other without having to align their pointers. Note this only works when they all have + the same alignment. */ + + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; + start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; + callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; + + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + /* Update the data size to include thread stacks. */ + data_size = data_size + start_stop_stack_size + callback_stack_size; + + + /* Determine data block sizes. Minimize the alignment requirement. + There are 4 MPU data entries available. The following is how the data size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to data size. + 2. 1/4 of the largest power of two that is greater than or equal to data size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + + /* Now loop through to setup MPU protection for the data area. */ + for (i = 0; i < TXM_MODULE_MPU_DATA_ENTRIES; i++) + { + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to data size. */ + if (i < 2) + { + block_size = _txm_power_of_two_block_size(data_size) >> 2; + } + + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ + else if (i == 2) + { + /* Subtract (block_size*2) from data_size to calculate remaining space. */ + data_size = data_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(data_size) >> 1; + } + + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + else + { + /* Calculate remaining space. */ + data_size = data_size - block_size; + block_size = _txm_power_of_two_block_size(data_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + } + + /* Build the base address register. */ + base_address_register = (data_address & ~(block_size - 1)); + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Build the size register. */ + size_register = srd_bits | region_size | TXM_ENABLE_REGION; + + /* Setup the MPU address, size, and attribute registers. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = base_address_register; + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_size = size_register; + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attributes = TXM_MODULE_MPU_DATA_ACCESS_CONTROL; + + /* Adjust the data address. */ + data_address = data_address + block_size; + + /* Increment MPU table index. */ + mpu_table_index++; + } +} + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_inside_data_check Cortex-R4/MPU/ARM */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks if the specified object is inside shared */ +/* memory. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* obj_ptr Pointer to the object */ +/* obj_size Size of the object */ +/* */ +/* OUTPUT */ +/* */ +/* Whether the object is inside the shared memory region. */ +/* */ +/* CALLS */ +/* */ +/* N/A */ +/* */ +/* CALLED BY */ +/* */ +/* Module dispatch check functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) +{ + +UINT shared_memory_index; +UINT num_shared_memory_mpu_entries; +ALIGN_TYPE shared_memory_address_start; +ALIGN_TYPE shared_memory_address_end; + + /* Check if the object is inside the module data. */ + if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && + ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) + { + return(TX_TRUE); + } + + /* Check if the object is inside the shared memory. */ + num_shared_memory_mpu_entries = module_instance -> txm_module_instance_shared_memory_count; + for (shared_memory_index = 0; shared_memory_index < num_shared_memory_mpu_entries; shared_memory_index++) + { + + shared_memory_address_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address[shared_memory_index]; + shared_memory_address_end = shared_memory_address_start + module_instance -> txm_module_instance_shared_memory_length[shared_memory_index]; + + if ((obj_ptr >= (ALIGN_TYPE) shared_memory_address_start) && + ((obj_ptr + obj_size) <= (ALIGN_TYPE) shared_memory_address_end)) + { + return(TX_TRUE); + } + } + + return(TX_FALSE); +} diff --git a/ports_module/cortex-r4/ac6/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex-r4/ac6/module_manager/src/txm_module_manager_thread_stack_build.S new file mode 100644 index 00000000..08d09003 --- /dev/null +++ b/ports_module/cortex-r4/ac6/module_manager/src/txm_module_manager_thread_stack_build.S @@ -0,0 +1,146 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +#define THUMB_MASK 0x20 // THUMB bit +#define USR_MODE 0x10 // USR mode +#define SYS_MODE 0x1F // SYS mode +#define CPSR_MASK 0xBF // Mask initial CPSR, IRQ ints enabled + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_thread_stack_build Cortex-R4/MPU/ARM */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) + { */ + .text + .global _txm_module_manager_thread_stack_build + .type _txm_module_manager_thread_stack_build, "function" +_txm_module_manager_thread_stack_build: + + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-R4 should look like the following after it is built: + + Stack Top: 1 Interrupt stack frame type + CPSR Initial value for CPSR + r0 Initial value for r0 + r1 Initial value for r1 + r2 Initial value for r2 + r3 Initial value for r3 + r4 Initial value for r4 + r5 Initial value for r5 + r6 Initial value for r6 + r7 Initial value for r7 + r8 Initial value for r8 + r9 Initial value for r9 + r10 Initial value for r10 + r11 Initial value for r11 + r12 Initial value for r12 + lr Initial value for lr (r14) + pc Initial value for pc (r15) + 0 For stack backtracing + + Stack Bottom: (higher memory address) */ + + LDR r2, [r0, #16] // Pickup end of stack area + BIC r2, r2, #7 // Ensure 8-byte alignment + SUB r2, r2, #76 // Allocate space for the stack frame + + /* Actually build the stack frame. */ + + MOV r3, #1 // Build interrupt stack type + STR r3, [r2, #0] // Store stack type + STR r0, [r2, #8] // Store initial r0 (thread pointer) + LDR r3, [r0, #8] // Pickup thread info pointer (it's in the stack pointer location right now) + STR r3, [r2, #12] // Store initial r1 + LDR r3, [r3, #8] // Pickup data base register + STR r3, [r2, #44] // Store initial r9 + MOV r3, #0 // Build initial register value + STR r3, [r2, #16] // Store initial r2 + STR r3, [r2, #20] // Store initial r3 + STR r3, [r2, #24] // Store initial r4 + STR r3, [r2, #28] // Store initial r5 + STR r3, [r2, #32] // Store initial r6 + STR r3, [r2, #36] // Store initial r7 + STR r3, [r2, #40] // Store initial r8 + LDR r3, [r0, #12] // Pickup stack starting address + STR r3, [r2, #48] // Store initial r10 (sl) + MOV r3, #0 // Build initial register value + STR r3, [r2, #52] // Store initial r11 + STR r3, [r2, #56] // Store initial r12 + STR r3, [r2, #60] // Store initial lr + STR r1, [r2, #64] // Store initial pc + STR r3, [r2, #68] // 0 for back-trace + MRS r3, CPSR // Pickup CPSR + BIC r3, r3, #CPSR_MASK // Mask mode bits of CPSR + TST r1, #1 // Test if THUMB bit set in initial PC + ORRNE r3, r3, #THUMB_MASK // Set T bit if set + LDR r1, [r0, #156] // Load tx_thread_module_user_mode + TST r1, #1 // Test if the user mode flag is set + ORREQ r3, r3, #SYS_MODE // Flag not set: Build CPSR, SYS mode, IRQ enabled + ORRNE r3, r3, #USR_MODE // Flag set: Build CPSR, USR mode, IRQ enabled + STR r3, [r2, #4] // Store initial CPSR + + /* Setup stack pointer. */ + /* thread_ptr -> tx_thread_stack_ptr = r2; */ + + STR r2, [r0, #8] // Save stack pointer in thread's control block + BX lr // Return to caller +/* } */ diff --git a/ports_module/cortex-r4/ac6/module_manager/src/txm_module_manager_user_mode_entry.S b/ports_module/cortex-r4/ac6/module_manager/src/txm_module_manager_user_mode_entry.S new file mode 100644 index 00000000..88145fa2 --- /dev/null +++ b/ports_module/cortex-r4/ac6/module_manager/src/txm_module_manager_user_mode_entry.S @@ -0,0 +1,86 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .global _txm_module_manager_kernel_dispatch + .global _txm_system_mode_enter + .global _txm_system_mode_exit + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_user_mode_entry Cortex-R4/MPU/ARM */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function allows modules to enter kernel mode. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* SVC 1 Enter kernel mode */ +/* SVC 2 Exit kernel mode */ +/* */ +/* CALLED BY */ +/* */ +/* Modules in user mode */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ + .text + .align 12 + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _txm_module_manager_user_mode_entry + .type _txm_module_manager_user_mode_entry, "function" +_txm_module_manager_user_mode_entry: +_txm_system_mode_enter: + SVC 1 // Get out of user mode. +_txm_module_priv: + /* At this point, we are in system mode. + Save LR (and r3 for 8 byte aligned stack) and call the kernel dispatch function. */ + PUSH {r3, lr} + BL _txm_module_manager_kernel_dispatch + POP {r3, lr} + +_txm_system_mode_exit: + /* Trap to restore user mode while inside of ThreadX. */ + SVC 2 + + BX lr // Return to the caller. + NOP + NOP diff --git a/ports_module/cortex-r4/iar/example_build/azure_rtos.eww b/ports_module/cortex-r4/iar/example_build/azure_rtos.eww new file mode 100644 index 00000000..a8dd1c9e --- /dev/null +++ b/ports_module/cortex-r4/iar/example_build/azure_rtos.eww @@ -0,0 +1,19 @@ + + + + $WS_DIR$\sample_threadx.ewp + + + $WS_DIR$\sample_threadx_module.ewp + + + $WS_DIR$\sample_threadx_module_manager.ewp + + + $WS_DIR$\tx.ewp + + + $WS_DIR$\txm.ewp + + + diff --git a/ports_module/cortex-r4/iar/example_build/cstartup.s b/ports_module/cortex-r4/iar/example_build/cstartup.s new file mode 100644 index 00000000..6953baa8 --- /dev/null +++ b/ports_module/cortex-r4/iar/example_build/cstartup.s @@ -0,0 +1,177 @@ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Part one of the system initialization code, +;; contains low-level +;; initialization. +;; +;; Copyright 2007-2017 IAR Systems AB. +;; +;; $Revision: 112610 $ +;; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION IRQ_STACK:DATA:NOROOT(3) + SECTION FIQ_STACK:DATA:NOROOT(3) + SECTION CSTACK:DATA:NOROOT(3) + SECTION SVC_STACK:DATA:NOROOT(3) + SECTION ABT_STACK:DATA:NOROOT(3) +; +; The module in this file are included in the libraries, and may be +; replaced by any user-defined modules that define the PUBLIC symbol +; __iar_program_start or a user defined start symbol. +; +; To override the cstartup defined in the library, simply add your +; modified version to the workbench project. + + SECTION .intvec:CODE:NOROOT(2) + + PUBLIC __vector + PUBLIC __iar_program_start + EXTERN Undefined_Handler + EXTERN SWI_Handler + EXTERN Prefetch_Handler + EXTERN Abort_Handler + EXTERN IRQ_Handler + EXTERN FIQ_Handler + + DATA + +__iar_init$$done: ; The vector table is not needed + ; until after copy initialization is done + +__vector: ; Make this a DATA label, so that stack usage + ; analysis doesn't consider it an uncalled fun + + ARM + + ; All default exception handlers (except reset) are + ; defined as weak symbol definitions. + ; If a handler is defined by the application it will take precedence. + LDR PC,Reset_Addr ; Reset + LDR PC,Undefined_Addr ; Undefined instructions + LDR PC,SWI_Addr ; Software interrupt (SWI/SVC) + LDR PC,Prefetch_Addr ; Prefetch abort + LDR PC,Abort_Addr ; Data abort + DCD 0 ; RESERVED + LDR PC,IRQ_Addr ; IRQ + LDR PC,FIQ_Addr ; FIQ + + DATA + +Reset_Addr: DCD __iar_program_start +Undefined_Addr: DCD Undefined_Handler +SWI_Addr: DCD SWI_Handler +Prefetch_Addr: DCD Prefetch_Handler +Abort_Addr: DCD Abort_Handler +IRQ_Addr: DCD IRQ_Handler +FIQ_Addr: DCD FIQ_Handler + + +; -------------------------------------------------- +; ?cstartup -- low-level system initialization code. +; +; After a reset execution starts here, the mode is ARM, supervisor +; with interrupts disabled. +; + + + + SECTION .text:CODE:NOROOT(2) + + EXTERN __cmain + REQUIRE __vector + EXTWEAK __iar_init_core + EXTWEAK __iar_init_vfp + + + ARM + +__iar_program_start: +?cstartup: + +; +; Add initialization needed before setup of stackpointers here. +; + +; +; Initialize the stack pointers. +; The pattern below can be used for any of the exception stacks: +; FIQ, IRQ, SVC, ABT, UND, SYS. +; The USR mode uses the same stack as SYS. +; The stack segments must be defined in the linker command file, +; and be declared above. +; + + +; -------------------- +; Mode, correspords to bits 0-5 in CPSR + +#define MODE_MSK 0x1F ; Bit mask for mode bits in CPSR + +#define USR_MODE 0x10 ; User mode +#define FIQ_MODE 0x11 ; Fast Interrupt Request mode +#define IRQ_MODE 0x12 ; Interrupt Request mode +#define SVC_MODE 0x13 ; Supervisor mode +#define ABT_MODE 0x17 ; Abort mode +#define UND_MODE 0x1B ; Undefined Instruction mode +#define SYS_MODE 0x1F ; System mode + + + MRS r0, cpsr ; Original PSR value + + ;; Set up the interrupt stack pointer. + + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits + MSR cpsr_c, r0 ; Change the mode + LDR r1, =SFE(IRQ_STACK) ; End of IRQ_STACK + BIC sp,r1,#0x7 ; Make sure SP is 8 aligned + + ;; Set up the fast interrupt stack pointer. + + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #FIQ_MODE ; Set FIR mode bits + MSR cpsr_c, r0 ; Change the mode + LDR r1, =SFE(FIQ_STACK) ; End of FIQ_STACK + BIC sp,r1,#0x7 ; Make sure SP is 8 aligned + + ;; Set up the SVC stack pointer. + + CPS #SVC_MODE + LDR r1, =SFE(SVC_STACK) ; End of SVC_STACK + BIC sp,r1,#0x7 ; Make sure SP is 8 aligned + + ;; Set up the abort stack pointer. + + CPS #ABT_MODE + LDR r1, =SFE(ABT_STACK) ; End of ABT_STACK + BIC sp,r1,#0x7 ; Make sure SP is 8 aligned + + ;; Set up the normal stack pointer. + + BIC r0 ,r0, #MODE_MSK ; Clear the mode bits + ORR r0 ,r0, #SYS_MODE ; Set System mode bits + MSR cpsr_c, r0 ; Change the mode + LDR r1, =SFE(CSTACK) ; End of CSTACK + BIC sp,r1,#0x7 ; Make sure SP is 8 aligned + + ;; Turn on core features assumed to be enabled. + FUNCALL __iar_program_start, __iar_init_core + BL __iar_init_core + + ;; Initialize VFP (if needed). + FUNCALL __iar_program_start, __iar_init_vfp + BL __iar_init_vfp + +;;; +;;; Add more initialization here +;;; + +;;; Continue to __cmain for C-level initialization. + + FUNCALL __iar_program_start, __cmain + B __cmain + + END diff --git a/ports_module/cortex-r4/iar/example_build/sample_threadx.c b/ports_module/cortex-r4/iar/example_build/sample_threadx.c new file mode 100644 index 00000000..983109cc --- /dev/null +++ b/ports_module/cortex-r4/iar/example_build/sample_threadx.c @@ -0,0 +1,376 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + + +/* Define byte pool memory. */ + +UCHAR byte_pool_memory[DEMO_BYTE_POOL_SIZE]; + + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", byte_pool_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports_module/cortex-r4/iar/example_build/sample_threadx.ewd b/ports_module/cortex-r4/iar/example_build/sample_threadx.ewd new file mode 100644 index 00000000..26f5640d --- /dev/null +++ b/ports_module/cortex-r4/iar/example_build/sample_threadx.ewd @@ -0,0 +1,2974 @@ + + + 3 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 32 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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Debug + + ARM + + 1 + + General + 3 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 36 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 23 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + Coder + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 36 + 1 + 0 + + + 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b/ports_module/cortex-r4/iar/example_build/sample_threadx.icf @@ -0,0 +1,49 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000040; +define symbol __ICFEDIT_region_ROM_end__ = 0x0013FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x08000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x0802FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x200; +define symbol __ICFEDIT_size_svcstack__ = 0x100; +define symbol __ICFEDIT_size_irqstack__ = 0x100; +define symbol __ICFEDIT_size_fiqstack__ = 0x100; +define symbol __ICFEDIT_size_undstack__ = 0x100; +define symbol __ICFEDIT_size_abtstack__ = 0x100; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define symbol __region_DRAM_start__ = 0x80000000; +define symbol __region_DRAM_end__ = 0x807FFFFF; +define region DRAM_region = mem:[from __region_DRAM_start__ to __region_DRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; +define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; +define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, + block UND_STACK, block ABT_STACK, block HEAP}; +place in DRAM_region { section DRAM }; + +place in RAM_region { last section FREE_MEM}; \ No newline at end of file diff --git a/ports_module/cortex-r4/iar/example_build/sample_threadx_module.c b/ports_module/cortex-r4/iar/example_build/sample_threadx_module.c new file mode 100644 index 00000000..203cbba2 --- /dev/null +++ b/ports_module/cortex-r4/iar/example_build/sample_threadx_module.c @@ -0,0 +1,425 @@ +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, + event flags group, byte pool, and block pool. */ + +/* Specify that this is a module! */ + +#define TXM_MODULE + + +/* Include the ThreadX module definitions. */ + +#include "txm_module.h" + + +/* Define constants. */ + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the pool space in the bss section of the module. ULONG is used to + get the word alignment. */ + +ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD *thread_0; +TX_THREAD *thread_1; +TX_THREAD *thread_2; +TX_THREAD *thread_3; +TX_THREAD *thread_4; +TX_THREAD *thread_5; +TX_THREAD *thread_6; +TX_THREAD *thread_7; +TX_QUEUE *queue_0; +TX_SEMAPHORE *semaphore_0; +TX_MUTEX *mutex_0; +TX_EVENT_FLAGS_GROUP *event_flags_0; +TX_BYTE_POOL *byte_pool_0; +TX_BLOCK_POOL *block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; +ULONG semaphore_0_puts; +ULONG event_0_sets; +ULONG queue_0_sends; + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + +void semaphore_0_notify(TX_SEMAPHORE *semaphore_ptr) +{ + + if (semaphore_ptr == semaphore_0) + semaphore_0_puts++; +} + + +void event_0_notify(TX_EVENT_FLAGS_GROUP *event_flag_group_ptr) +{ + + if (event_flag_group_ptr == event_flags_0) + event_0_sets++; +} + + +void queue_0_notify(TX_QUEUE *queue_ptr) +{ + + if (queue_ptr == queue_0) + queue_0_sends++; +} + + +/* Define the module start function. */ + +void demo_module_start(ULONG id) +{ + +CHAR *pointer; + + /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + the control block(s). */ + txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_2, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_3, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_4, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_5, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_6, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_7, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&queue_0, sizeof(TX_QUEUE)); + txm_module_object_allocate((void*)&semaphore_0, sizeof(TX_SEMAPHORE)); + txm_module_object_allocate((void*)&mutex_0, sizeof(TX_MUTEX)); + txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); + txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); + txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(queue_0, "module queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + tx_queue_send_notify(queue_0, queue_0_notify); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(semaphore_0, "module semaphore 0", 1); + + tx_semaphore_put_notify(semaphore_0, semaphore_0_notify); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(event_flags_0, "module event flags 0"); + + tx_event_flags_set_notify(event_flags_0, event_0_notify); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(mutex_0, "module mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(block_pool_0, "module block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + diff --git a/ports_module/cortex-r4/iar/example_build/sample_threadx_module.ewd b/ports_module/cortex-r4/iar/example_build/sample_threadx_module.ewd new file mode 100644 index 00000000..ddf484db --- /dev/null +++ b/ports_module/cortex-r4/iar/example_build/sample_threadx_module.ewd @@ -0,0 +1,2974 @@ + + + 3 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 32 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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b/ports_module/cortex-r4/iar/example_build/sample_threadx_module.icf @@ -0,0 +1,44 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00100000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0013FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x08000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x0800FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0; +define symbol __ICFEDIT_size_svcstack__ = 0; +define symbol __ICFEDIT_size_irqstack__ = 0; +define symbol __ICFEDIT_size_fiqstack__ = 0; +define symbol __ICFEDIT_size_undstack__ = 0; +define symbol __ICFEDIT_size_abtstack__ = 0; +define symbol __ICFEDIT_size_heap__ = 0x100; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +define movable block ROPI with alignment = 4, fixed order +{ + ro object txm_module_preamble.o, + ro, + ro data +}; + +define movable block RWPI with alignment = 8, fixed order, static base +{ + rw, + block HEAP +}; + +place in ROM_region { block ROPI }; +place in RAM_region { block RWPI }; + diff --git a/ports_module/cortex-r4/iar/example_build/sample_threadx_module_manager.c b/ports_module/cortex-r4/iar/example_build/sample_threadx_module_manager.c new file mode 100644 index 00000000..8c319878 --- /dev/null +++ b/ports_module/cortex-r4/iar/example_build/sample_threadx_module_manager.c @@ -0,0 +1,104 @@ +/* Small demonstration of the ThreadX module manager. */ + +#include "tx_api.h" +#include "txm_module.h" + +#define DEMO_STACK_SIZE 1024 + +/* Define the ThreadX object control blocks... */ + +TX_THREAD module_manager; +TXM_MODULE_INSTANCE my_module; + +UCHAR manager_stack[1024]; + +/* Define the object pool area. */ + +UCHAR object_memory[8192]; + + +/* Define the count of memory faults. */ + +ULONG memory_faults; + + +/* Define thread prototypes. */ + +void module_manager_entry(ULONG thread_input); + + +/* Define fault handler. */ + +VOID module_fault_handler(TX_THREAD *thread, TXM_MODULE_INSTANCE *module) +{ + + /* Just increment the fault counter. */ + memory_faults++; +} + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + manager_stack, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); +} + + + + +/* Define the test threads. */ + +void module_manager_entry(ULONG thread_input) +{ + + /* Initialize the module manager. */ + txm_module_manager_initialize((VOID *) 0x08020000, 0x10000); + + txm_module_manager_object_pool_create(object_memory, sizeof(object_memory)); + + /* Register a fault handler. */ + txm_module_manager_memory_fault_notify(module_fault_handler); + + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ + txm_module_manager_in_place_load(&my_module, "my module", (VOID *) 0x00100000); + + /* Enable 128 byte read/write shared memory region at 0x08025000. */ + txm_module_manager_external_memory_enable(&my_module, (void *) 0x08025000, 128, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); + + /* Start the module. */ + txm_module_manager_start(&my_module); + + /* Sleep for a while.... */ + tx_thread_sleep(300); + + /* Stop the module. */ + txm_module_manager_stop(&my_module); + + /* Unload the module. */ + txm_module_manager_unload(&my_module); + + /* Load the module that is already there. */ + txm_module_manager_in_place_load(&my_module, "my module", (VOID *) 0x00100000); + + /* Start the module again. */ + txm_module_manager_start(&my_module); + + /* Now just spin... */ + while(1) + { + + tx_thread_sleep(100); + } +} diff --git a/ports_module/cortex-r4/iar/example_build/sample_threadx_module_manager.ewd b/ports_module/cortex-r4/iar/example_build/sample_threadx_module_manager.ewd new file mode 100644 index 00000000..a6d416f4 --- /dev/null +++ b/ports_module/cortex-r4/iar/example_build/sample_threadx_module_manager.ewd @@ -0,0 +1,2974 @@ + + + 3 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 32 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\RemedyRtosViewer\RemedyRtosViewer.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8b.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8bBE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 1 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 32 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 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0 + + + $TOOLKIT_DIR$\plugins\rtos\RemedyRtosViewer\RemedyRtosViewer.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8b.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8bBE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/ports_module/cortex-r4/iar/example_build/sample_threadx_module_manager.ewp b/ports_module/cortex-r4/iar/example_build/sample_threadx_module_manager.ewp new file mode 100644 index 00000000..07de5bec --- /dev/null +++ b/ports_module/cortex-r4/iar/example_build/sample_threadx_module_manager.ewp @@ -0,0 +1,2138 @@ + + + 3 + + Debug + + ARM + + 1 + + General + 3 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 36 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 23 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + 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$PROJ_DIR$\tx_initialize_low_level.s + + diff --git a/ports_module/cortex-r4/iar/example_build/sample_threadx_module_manager.icf b/ports_module/cortex-r4/iar/example_build/sample_threadx_module_manager.icf new file mode 100644 index 00000000..f974729e --- /dev/null +++ b/ports_module/cortex-r4/iar/example_build/sample_threadx_module_manager.icf @@ -0,0 +1,49 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000040; +define symbol __ICFEDIT_region_ROM_end__ = 0x000FFFFF; //Module in 0x00100000-0x0013FFFF +define symbol __ICFEDIT_region_RAM_start__ = 0x08000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x0801FFFF; //Module in 0x08020000-0x0802FFFF +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x200; +define symbol __ICFEDIT_size_svcstack__ = 0x100; +define symbol __ICFEDIT_size_irqstack__ = 0x100; +define symbol __ICFEDIT_size_fiqstack__ = 0x100; +define symbol __ICFEDIT_size_undstack__ = 0x100; +define symbol __ICFEDIT_size_abtstack__ = 0x100; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define symbol __region_DRAM_start__ = 0x80000000; +define symbol __region_DRAM_end__ = 0x807FFFFF; +define region DRAM_region = mem:[from __region_DRAM_start__ to __region_DRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; +define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; +define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, + block UND_STACK, block ABT_STACK, block HEAP}; +place in DRAM_region { section DRAM }; + +place in RAM_region { last section FREE_MEM}; \ No newline at end of file diff --git a/ports_module/cortex-r4/iar/example_build/settings/sample_threadx.dnx b/ports_module/cortex-r4/iar/example_build/settings/sample_threadx.dnx new file mode 100644 index 00000000..92ef0faa --- /dev/null +++ b/ports_module/cortex-r4/iar/example_build/settings/sample_threadx.dnx @@ -0,0 +1,100 @@ + + + + 0 + 1 + 90 + 1 + 1 + 1 + main + 0 + 50 + + + 0 + 1 + + + 157308190 + + + 0 + 1 + + + 0 + 0 + 0 + + + 0 + 1 + 0 + 0 + + + 0 + + + 1 + + + _ 0 + _ 0 + + + _ 0 + _ "" + + + _ 0 + _ "" + _ 0 + + + 0 + + + 0 + 0 + 1 + 0 + 1 + 0 + + + 0 + 0 + 1 + 0 + 1 + + + 0 + + + 0 + + + 1 + _ 0 10000 0 10000 1 0 0 100 0 1 "IRQ 1 0x18 CPSR.I" + 1 + + + 1 + 0 + 1 + 0 + 1 + + + 0 + 0 + + + 10000000 + 0 + 1 + + diff --git a/ports_module/cortex-r4/iar/example_build/settings/sample_threadx_module_manager.dnx b/ports_module/cortex-r4/iar/example_build/settings/sample_threadx_module_manager.dnx new file mode 100644 index 00000000..74f3730a --- /dev/null +++ b/ports_module/cortex-r4/iar/example_build/settings/sample_threadx_module_manager.dnx @@ -0,0 +1,100 @@ + + + + 1819642867 + + + 0 + 1 + 90 + 1 + 1 + 1 + main + 0 + 50 + + + 0 + 1 + + + 0 + 0 + 0 + + + 0 + 1 + + + _ 0 + _ 0 + + + 0 + + + 0 + 1 + 0 + 0 + + + 0 + + + 1 + + + _ 0 + _ "" + + + _ 0 + _ "" + _ 0 + + + 0 + 0 + 1 + 0 + 1 + 0 + + + 0 + 0 + 1 + 0 + 1 + + + 0 + + + 0 + + + 1 + _ 0 10000 0 10000 1 0 0 100 0 1 "IRQ 1 0x18 CPSR.I" + 1 + + + 1 + 0 + 1 + 0 + 1 + + + 0 + 0 + + + 10000000 + 0 + 1 + + diff --git a/ports_module/cortex-r4/iar/example_build/tx.ewd b/ports_module/cortex-r4/iar/example_build/tx.ewd new file mode 100644 index 00000000..49662d42 --- /dev/null +++ b/ports_module/cortex-r4/iar/example_build/tx.ewd @@ -0,0 +1,2974 @@ + + + 3 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 32 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\common\src\txe_thread_reset.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_resume.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_suspend.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_terminate.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_time_slice_change.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_wait_abort.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_activate.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_change.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_deactivate.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_info_get.c + + + $PROJ_DIR$\..\module_manager\src\txm_module_manager_alignment_adjust.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_application_request.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_callback_request.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_event_flags_notify_trampoline.c + + + $PROJ_DIR$\..\module_manager\src\txm_module_manager_external_memory_enable.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_file_load.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_in_place_load.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_initialize.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_internal_load.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_kernel_dispatch.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_maximum_module_priority_set.c + + + $PROJ_DIR$\..\module_manager\src\txm_module_manager_memory_fault_handler.c + + + $PROJ_DIR$\..\module_manager\src\txm_module_manager_memory_fault_notify.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_memory_load.c + + + $PROJ_DIR$\..\module_manager\src\txm_module_manager_mm_register_setup.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_object_allocate.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_object_deallocate.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_object_pointer_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_object_pointer_get_extended.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_object_pool_create.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_properties_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_queue_notify_trampoline.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_semaphore_notify_trampoline.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_start.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_stop.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_thread_create.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_thread_notify_trampoline.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_thread_reset.c + + + $PROJ_DIR$\..\module_manager\src\txm_module_manager_thread_stack_build.s + + + $PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_timer_notify_trampoline.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_unload.c + + + $PROJ_DIR$\..\module_manager\src\txm_module_manager_user_mode_entry.s + + + $PROJ_DIR$\..\..\..\..\common_modules\module_manager\src\txm_module_manager_util.c + + + diff --git a/ports_module/cortex-r4/iar/example_build/tx_initialize_low_level.s b/ports_module/cortex-r4/iar/example_build/tx_initialize_low_level.s new file mode 100644 index 00000000..2e9c4519 --- /dev/null +++ b/ports_module/cortex-r4/iar/example_build/tx_initialize_low_level.s @@ -0,0 +1,408 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_initialize.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +SVC_MODE DEFINE 0x13 ; SVC mode +ABT_MODE DEFINE 0x17 ; ABT mode +SYS_MODE DEFINE 0x1F ; SYS mode +THUMB_MASK DEFINE 0x20 ; Thumb bit (5) of CPSR/SPSR +; + + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_initialize_unused_memory + EXTERN _tx_thread_context_save +; EXTERN _tx_thread_vectored_context_save + EXTERN _tx_thread_context_restore + +#ifdef TX_ENABLE_IRQ_NESTING + EXTERN _tx_thread_irq_nesting_start + EXTERN _tx_thread_irq_nesting_end +#endif + + EXTERN _tx_timer_interrupt + EXTERN ?cstartup + EXTERN _tx_build_options + EXTERN _tx_version_id +; +; +; +;/* Define the FREE_MEM segment that will specify where free memory is +; defined. This must also be located in at the end of other RAM segments +; in the linker control file. The value of this segment is what is passed +; to tx_application_define. */ +; + RSEG FREE_MEM:DATA + PUBLIC __tx_free_memory_start +__tx_free_memory_start + DS32 4 +; +; +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-R4/MPU/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + ARM + PUBLIC _tx_initialize_low_level +_tx_initialize_low_level +; +; /****** NOTE ****** The IAR 4.11a and above releases call main in SYS mode. */ +; + ; /* For modules, stay in SYS mode and disable interrupts. */ + CPSID i +; +; /* Pickup the start of free memory. */ +; + LDR r0, =__tx_free_memory_start ; Get end of non-initialized RAM area +; +; /* Save the system stack pointer. */ +; _tx_thread_system_stack_ptr = (VOID_PTR) (sp); +; +; /* Save the first available memory address. */ +; _tx_initialize_unused_memory = (VOID_PTR) FREE_MEM; +; + LDR r2, =_tx_initialize_unused_memory ; Pickup unused memory ptr address + STR r0, [r2, #0] ; Save first free memory address +; +; /* Setup Timer for periodic interrupts. */ +; +; /* Done, return to caller. */ +; + BX lr ; Return to caller +;} +; +;/* Define shells for each of the interrupt vectors. */ +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_undefined +__tx_undefined + B __tx_undefined ; Undefined handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_reserved_handler +__tx_reserved_handler + B __tx_reserved_handler ; Reserved exception handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_irq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_irq_processing_return + PUBLIC IRQ_Handler +__tx_irq_handler +IRQ_Handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. In +; addition, IRQ interrupts may be re-enabled - with certain restrictions - +; if nested IRQ interrupts are desired. Interrupts may be re-enabled over +; small code sequences where lr is saved before enabling interrupts and +; restored after interrupts are again disabled. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; from IRQ mode with interrupts disabled. This routine switches to the +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared +; prior to enabling nested IRQ interrupts. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_start +#endif +; +; /* For debug purpose, execute the timer interrupt processing here. In +; a real system, some kind of status indication would have to be checked +; before the timer interrupt handler could be called. */ +; + BL _tx_timer_interrupt ; Timer interrupt handler +; +; /* Application IRQ handlers can be called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_context_restore. +; This routine returns in processing in IRQ mode with interrupts disabled. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_end +#endif +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore +; +; +; /* This is an example of a vectored IRQ handler. */ +; +; RSEG .text:CODE:NOROOT(2) +; PUBLIC __tx_example_vectored_irq_handler +;__tx_example_vectored_irq_handler +; +; /* Jump to context save to save system context. */ +; STMDB sp!, {r0-r3} ; Save some scratch registers +; MRS r0, SPSR ; Pickup saved SPSR +; SUB lr, lr, #4 ; Adjust point of interrupt +; STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; BL _tx_thread_vectored_context_save +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. In +; addition, IRQ interrupts may be re-enabled - with certain restrictions - +; if nested IRQ interrupts are desired. Interrupts may be re-enabled over +; small code sequences where lr is saved before enabling interrupts and +; restored after interrupts are again disabled. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; from IRQ mode with interrupts disabled. This routine switches to the +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared +; prior to enabling nested IRQ interrupts. */ +;#ifdef TX_ENABLE_IRQ_NESTING +; BL _tx_thread_irq_nesting_start +;#endif +; +; /* Application IRQ handler is called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_context_restore. +; This routine returns in processing in IRQ mode with interrupts disabled. */ +;#ifdef TX_ENABLE_IRQ_NESTING +; BL _tx_thread_irq_nesting_end +;#endif +; +; /* Jump to context restore to restore system context. */ +; B _tx_thread_context_restore +; +; +; /* FIQ Handler */ + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_handler +__tx_fiq_handler + B __tx_fiq_handler ; FIQ interrupt handler +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* __tx_prefetch_handler & __tx_abort_handler Cortex-R4/MPU/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function handles MPU exceptions and fills the */ +;/* _txm_module_manager_memory_fault_info struct. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _txm_module_manager_memory_fault_handler */ +;/* _tx_execution_thread_exit */ +;/* _tx_thread_schedule */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* MMU exceptions */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ + +; ******************************************************************* +; MPU Exception Handling +; ******************************************************************* + EXTERN _tx_thread_system_state + EXTERN _txm_module_manager_memory_fault_info + EXTERN _tx_thread_current_ptr + EXTERN _txm_module_manager_memory_fault_handler + EXTERN _tx_execution_thread_exit + EXTERN _tx_thread_schedule + + RSEG .text:CODE:NOROOT(2) + PUBLIC Prefetch_Handler + PUBLIC Abort_Handler + PUBLIC __tx_prefetch_handler + PUBLIC __tx_abort_handler +__tx_prefetch_handler +__tx_abort_handler +Prefetch_Handler +Abort_Handler + STMDB sp!, {r0-r3} ; Save some working registers + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Now pickup and store all the fault related information. */ +; + ; Pickup the memory fault info struct + LDR r3, =_txm_module_manager_memory_fault_info + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup the current thread pointer + STR r1, [r3, #0] ; Save current thread pointer + + MRC p15, 0, r0, c6, c0, 0 ; Read DFAR + STR r0, [r3, #8] ; Save DFAR + + CMP r0, #0 ; Was it a data or instruction fault? + SUBEQ lr, lr, #4 ; Adjust point of exception for instruction + SUBNE lr, lr, #8 ; Adjust point of exception for data + STR lr, [r3, #4] ; Save point of fault + + MRC p15, 0, r0, c5, c0, 0 ; Read DFSR + STR r0, [r3, #12] ; Save DFSR + MRC p15, 0, r0, c6, c0, 2 ; Read IFAR + STR r0, [r3, #16] ; Save IFAR + MRC p15, 0, r0, c5, c0, 1 ; Read IFSR + STR r0, [r3, #20] ; Save IFSR + MOV r0, #0 ; Build zero register + MCR p15, 0, r0, c6, c0, 0 ; Clear DFAR + MCR p15, 0, r0, c5, c0, 0 ; Clear DFSR + MCR p15, 0, r0, c6, c0, 2 ; Clear IFAR + MCR p15, 0, r0, c5, c0, 1 ; Clear IFSR + + ; Save registers r0-r12 + POP {r0-r2} + STR r0, [r3, #28] ; Save r0 + STR r1, [r3, #32] ; Save r1 + STR r2, [r3, #36] ; Save r2 + POP {r0} + STR r0, [r3, #40] ; Save r3 + STR r4, [r3, #44] ; Save r4 + STR r5, [r3, #48] ; Save r5 + STR r6, [r3, #52] ; Save r6 + STR r7, [r3, #56] ; Save r7 + STR r8, [r3, #60] ; Save r8 + STR r9, [r3, #64] ; Save r9 + STR r10,[r3, #68] ; Save r10 + STR r11,[r3, #72] ; Save r11 + STR r12,[r3, #76] ; Save r12 + + CPS #SYS_MODE ; Enter SYS mode + MOV r0, lr ; Pickup lr + MOV r1, sp ; Pickup sp + CPS #ABT_MODE ; Back to ABT mode + STR r0, [r3, #80] ; Save lr + STR r1, [r3, #24] ; Save sp + MRS r0, SPSR ; Pickup SPSR + STR r0, [r3, #84] ; Save SPSR + ORR r0, r0, #SYS_MODE ; Return into SYS mode + BIC r0, r0, #THUMB_MASK ; Clear THUMB mode + MSR SPSR_c, r0 ; Save SPSR + + ; Call memory manager fault handler + BL _txm_module_manager_memory_fault_handler + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + BL _tx_execution_thread_exit ; Call the thread exit function +#endif + + LDR r0, =_tx_thread_system_state ; Pickup address of system state + LDR r1, [r0] ; Pickup system state + SUB r1, r1, #1 ; Decrement + STR r1, [r0] ; Store new system state + + MOV r1, #0 ; Build NULL value + LDR r0, =_tx_thread_current_ptr ; Pickup address of current thread pointer + STR r1, [r0] ; Clear current thread pointer + + ; Return from exception + LDR lr, =_tx_thread_schedule ; Load scheduler address + MOVS pc, lr ; Return to scheduler +; ******************************************************************* +; End of MMU exception handling. +; ******************************************************************* +; +BUILD_OPTIONS + DC32 _tx_build_options ; Reference to ensure it comes in +VERSION_ID + DC32 _tx_version_id ; Reference to ensure it comes in + END + diff --git a/ports_module/cortex-r4/iar/example_build/txm.ewp b/ports_module/cortex-r4/iar/example_build/txm.ewp new file mode 100644 index 00000000..af145c0c --- /dev/null +++ b/ports_module/cortex-r4/iar/example_build/txm.ewp @@ -0,0 +1,2477 @@ + + + 3 + + Debug + + ARM + + 1 + + General + 3 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 36 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 23 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + Coder + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 36 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\common\inc\tx_thread.h + + + $PROJ_DIR$\..\..\..\..\common\inc\tx_timer.h + + + $PROJ_DIR$\..\..\..\..\common\inc\tx_trace.h + + + $PROJ_DIR$\..\..\..\..\common\inc\tx_user_sample.h + + + $PROJ_DIR$\..\..\..\..\common_modules\inc\txm_module.h + + + $PROJ_DIR$\..\inc\txm_module_port.h + + + $PROJ_DIR$\..\..\..\..\common_modules\inc\txm_module_user.h + + + + src + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_block_allocate.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_block_pool_create.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_block_pool_delete.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_block_pool_info_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_block_pool_performance_info_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_block_pool_performance_system_info_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_block_pool_prioritize.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_block_release.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_byte_allocate.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_byte_pool_create.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_byte_pool_delete.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_byte_pool_info_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_byte_pool_performance_info_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_byte_pool_performance_system_info_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_byte_pool_prioritize.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_byte_release.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_event_flags_create.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_event_flags_delete.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_event_flags_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_event_flags_info_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_event_flags_performance_info_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_event_flags_performance_system_info_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_event_flags_set.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_event_flags_set_notify.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_module_application_request.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_module_callback_request_thread_entry.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_module_object_allocate.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_module_object_deallocate.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_module_object_pointer_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_module_object_pointer_get_extended.c + + + $PROJ_DIR$\..\module_lib\src\txm_module_thread_shell_entry.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_module_thread_system_suspend.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_mutex_create.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_mutex_delete.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_mutex_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_mutex_info_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_mutex_performance_info_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_mutex_performance_system_info_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_mutex_prioritize.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_mutex_put.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_queue_create.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_queue_delete.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_queue_flush.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_queue_front_send.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_queue_info_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_queue_performance_info_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_queue_performance_system_info_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_queue_prioritize.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_queue_receive.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_queue_send.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_queue_send_notify.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_semaphore_ceiling_put.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_semaphore_create.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_semaphore_delete.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_semaphore_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_semaphore_info_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_semaphore_performance_info_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_semaphore_performance_system_info_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_semaphore_prioritize.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_semaphore_put.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_semaphore_put_notify.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_create.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_delete.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_entry_exit_notify.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_identify.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_info_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_interrupt_control.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_performance_info_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_performance_system_info_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_preemption_change.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_priority_change.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_relinquish.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_reset.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_resume.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_sleep.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_stack_error_notify.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_suspend.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_terminate.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_time_slice_change.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_thread_wait_abort.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_time_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_time_set.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_timer_activate.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_timer_change.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_timer_create.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_timer_deactivate.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_timer_delete.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_timer_info_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_timer_performance_info_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_timer_performance_system_info_get.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_trace_buffer_full_notify.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_trace_disable.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_trace_enable.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_trace_event_filter.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_trace_event_unfilter.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_trace_interrupt_control.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_trace_isr_enter_insert.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_trace_isr_exit_insert.c + + + $PROJ_DIR$\..\..\..\..\common_modules\module_lib\src\txm_trace_user_event_insert.c + + + diff --git a/ports_module/cortex-r4/iar/example_build/txm_module_preamble.s b/ports_module/cortex-r4/iar/example_build/txm_module_preamble.s new file mode 100644 index 00000000..31ccca5b --- /dev/null +++ b/ports_module/cortex-r4/iar/example_build/txm_module_preamble.s @@ -0,0 +1,67 @@ + SECTION .text:CODE + + AAPCS INTERWORK, ROPI, RWPI_COMPATIBLE, VFP_COMPATIBLE + PRESERVE8 + + /* Define public symbols. */ + + PUBLIC __txm_module_preamble + + + /* Define application-specific start/stop entry points for the module. */ + + EXTERN demo_module_start + + + /* Define common external refrences. */ + + EXTERN _txm_module_thread_shell_entry + EXTERN _txm_module_callback_request_thread_entry + EXTERN ROPI$$Length + EXTERN RWPI$$Length + + DATA +__txm_module_preamble: + DC32 0x4D4F4455 ; Module ID + DC32 0x6 ; Module Major Version + DC32 0x1 ; Module Minor Version + DC32 32 ; Module Preamble Size in 32-bit words + DC32 0x12345678 ; Module ID (application defined) + DC32 0x00000001 ; Module Properties where: + ; Bits 31-24: Compiler ID + ; 0 -> IAR + ; 1 -> RVDS + ; 2 -> GNU + ; Bits 23-1: Reserved + ; Bit 0: 0 -> Privileged mode execution (no MPU protection) + ; 1 -> User mode execution (MPU protection) + DC32 _txm_module_thread_shell_entry - . - 0 ; Module Shell Entry Point + DC32 demo_module_start - . - 0 ; Module Start Thread Entry Point + DC32 0 ; Module Stop Thread Entry Point + DC32 1 ; Module Start/Stop Thread Priority + DC32 1022 ; Module Start/Stop Thread Stack Size + DC32 _txm_module_callback_request_thread_entry - . - 0 ; Module Callback Thread Entry + DC32 1 ; Module Callback Thread Priority + DC32 1022 ; Module Callback Thread Stack Size + DC32 ROPI$$Length ; Module Code Size + DC32 RWPI$$Length ; Module Data Size + DC32 0 ; Reserved 0 + DC32 0 ; Reserved 1 + DC32 0 ; Reserved 2 + DC32 0 ; Reserved 3 + DC32 0 ; Reserved 4 + DC32 0 ; Reserved 5 + DC32 0 ; Reserved 6 + DC32 0 ; Reserved 7 + DC32 0 ; Reserved 8 + DC32 0 ; Reserved 9 + DC32 0 ; Reserved 10 + DC32 0 ; Reserved 11 + DC32 0 ; Reserved 12 + DC32 0 ; Reserved 13 + DC32 0 ; Reserved 14 + DC32 0 ; Reserved 15 + + END + + diff --git a/ports_module/cortex-r4/iar/inc/tx_port.h b/ports_module/cortex-r4/iar/inc/tx_port.h new file mode 100644 index 00000000..34a300e5 --- /dev/null +++ b/ports_module/cortex-r4/iar/inc/tx_port.h @@ -0,0 +1,408 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-R4/IAR */ +/* 6.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include +#include +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#else +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif + +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 1 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (TX_IRQ_NESTING_ENABLED) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ + VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; \ + VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ + VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; +#endif +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#if (__VER__ < 8000000) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); +#else +void *_tx_iar_create_per_thread_tls_area(void); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); +void __iar_Initlocks(void); + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#endif +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#if __CORE__ > __ARM4TM__ + +#if __CPU_MODE__ == 2 + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + b = (UINT) __CLZ(m); \ + b = 31 - b; +#endif +#endif +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + + +/* First, check and see what mode the file is being compiled in. The IAR compiler + defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode + is present. If ARM 32-bit mode is present, the fast CPSR manipulation macros + are available. Otherwise, if Thumb mode is present, we must use function calls. */ + +#ifdef TX_DISABLE_INLINE + +UINT _tx_thread_interrupt_disable(void); +void _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else +#if __CPU_MODE__ == 2 + +#if (__VER__ < 8002000) +__intrinsic unsigned long __get_CPSR(); +__intrinsic void __set_CPSR( unsigned long ); +#endif + + +#if (__VER__ < 8002000) +#define TX_INTERRUPT_SAVE_AREA unsigned long interrupt_save; +#else +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#endif + +#define TX_DISABLE interrupt_save = __get_CPSR(); \ + __set_CPSR(interrupt_save | TX_INT_DISABLE); +#define TX_RESTORE __set_CPSR(interrupt_save); + +#else + +UINT _tx_thread_interrupt_disable(void); +void _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#endif +#endif + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define VFP extension for the Cortex-R4. Each is assumed to be called in the context of the executing + thread. */ + +void tx_thread_vfp_enable(void); +void tx_thread_vfp_disable(void); + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/IAR Version 6.1 *"; +#else +#ifdef TX_MISRA_ENABLE +extern CHAR _tx_version_id[100]; +#else +extern CHAR _tx_version_id[]; +#endif +#endif + + +#endif + + + diff --git a/ports_module/cortex-r4/iar/inc/txm_module_port.h b/ports_module/cortex-r4/iar/inc/txm_module_port.h new file mode 100644 index 00000000..ecc2b290 --- /dev/null +++ b/ports_module/cortex-r4/iar/inc/txm_module_port.h @@ -0,0 +1,347 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* txm_module_port.h Cortex-R4/MPU/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the basic module constants, interface structures, */ +/* and function prototypes. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TXM_MODULE_PORT_H +#define TXM_MODULE_PORT_H + +/* Determine if the optional Modules user define file should be used. */ + +#ifdef TXM_MODULE_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in txm_module_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "txm_module_user.h" +#endif + +/* It is assumed that the base ThreadX tx_port.h file has been modified to add the + following extensions to the ThreadX thread control block (this code should replace + the corresponding macro define in tx_port.h): + +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ + VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; \ + VOID *tx_thread_iar_tls_pointer; + +The following extensions must also be defined in tx_port.h: + +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); + +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); + + +*/ + +/* Define the kernel stack size for a module thread. */ +#ifndef TXM_MODULE_KERNEL_STACK_SIZE +#define TXM_MODULE_KERNEL_STACK_SIZE 512 +#endif + +/* For the following 3 access control settings, change TEX and C, B, S (bits 5 through 0) + * to reflect your system memory attributes (cache, shareable, memory type). */ +/* Code region access control: read-only, outer & inner write-back, normal memory, shareable. */ +#define TXM_MODULE_MPU_CODE_ACCESS_CONTROL 0x00000607 +/* Data region access control: execute never, read/write, outer & inner write-back, normal memory, shareable. */ +#define TXM_MODULE_MPU_DATA_ACCESS_CONTROL 0x00001307 +/* Shared region access control: execute never, read-only, outer & inner write-back, normal memory, shareable. */ +#define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x00001207 + +/* Define constants specific to the tools the module can be built with for this particular modules port. */ + +#define TXM_MODULE_IAR_COMPILER 0x00000000 +#define TXM_MODULE_RVDS_COMPILER 0x01000000 +#define TXM_MODULE_GNU_COMPILER 0x02000000 +#define TXM_MODULE_COMPILER_MASK 0xFF000000 +#define TXM_MODULE_OPTIONS_MASK 0x000000FF + + +/* Define the properties for this particular module port. */ + +#define TXM_MODULE_MEMORY_PROTECTION_ENABLED + +#ifdef TXM_MODULE_MEMORY_PROTECTION_ENABLED +#define TXM_MODULE_REQUIRE_ALLOCATED_OBJECT_MEMORY +#else +#define TXM_MODULE_REQUIRE_LOCAL_OBJECT_MEMORY +#endif + +#define TXM_MODULE_USER_MODE 0x00000001 +#define TXM_MODULE_MEMORY_PROTECTION 0x00000001 + + +/* Define the supported options for this module. */ + +#define TXM_MODULE_MANAGER_SUPPORTED_OPTIONS (TXM_MODULE_MEMORY_PROTECTION) +#define TXM_MODULE_MANAGER_REQUIRED_OPTIONS 0 + + +/* Define offset adjustments according to the compiler used to build the module. */ + +#define TXM_MODULE_IAR_SHELL_ADJUST 24 +#define TXM_MODULE_IAR_START_ADJUST 28 +#define TXM_MODULE_IAR_STOP_ADJUST 32 +#define TXM_MODULE_IAR_CALLBACK_ADJUST 44 + +#define TXM_MODULE_RVDS_SHELL_ADJUST 0 +#define TXM_MODULE_RVDS_START_ADJUST 0 +#define TXM_MODULE_RVDS_STOP_ADJUST 0 +#define TXM_MODULE_RVDS_CALLBACK_ADJUST 0 + +#define TXM_MODULE_GNU_SHELL_ADJUST 24 +#define TXM_MODULE_GNU_START_ADJUST 28 +#define TXM_MODULE_GNU_STOP_ADJUST 32 +#define TXM_MODULE_GNU_CALLBACK_ADJUST 44 + + +/* Define other module port-specific constants. */ + + +/* Define INLINE_DECLARE to inline for IAR compiler. */ + +#define INLINE_DECLARE inline + +/* Define the number of MPU entries assigned to the code and data sections. + On Cortex-R parts, there are 12 total entries. ThreadX uses one for access + to the kernel entry function, thus 11 remain for code and data protection. */ +#define TXM_MODULE_MPU_TOTAL_ENTRIES 12 +#define TXM_MODULE_MPU_CODE_ENTRIES 4 +#define TXM_MODULE_MPU_DATA_ENTRIES 4 +#define TXM_MODULE_MPU_SHARED_ENTRIES 3 + +#define TXM_MODULE_MPU_KERNEL_ENTRY_INDEX 0 +#define TXM_MODULE_MPU_SHARED_INDEX 9 + +/* There are 3 registers to set up each MPU region: DRACR, DRBAR, DRSR. */ +#define TXM_MODULE_MPU_REGISTER_COUNT 3 + +#define TXM_ENABLE_REGION 0x01 + +/* Shared memory region attributes. */ +#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 +#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x00000100 + +typedef struct TXM_MODULE_MPU_INFO_STRUCT +{ + ULONG txm_module_mpu_region_address; + ULONG txm_module_mpu_region_size; + ULONG txm_module_mpu_region_attributes; +} TXM_MODULE_MPU_INFO; +/* Define the port-extensions to the module manager instance structure. */ + +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_count; \ + ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES]; + + +/* Define the memory fault information structure that is populated when a memory fault occurs. */ + + +typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT +{ + TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr; + VOID *txm_module_manager_memory_fault_info_code_location; + ULONG txm_module_manager_memory_fault_info_dfar; + ULONG txm_module_manager_memory_fault_info_dfsr; + ULONG txm_module_manager_memory_fault_info_ifar; + ULONG txm_module_manager_memory_fault_info_ifsr; + ULONG txm_module_manager_memory_fault_info_sp; + ULONG txm_module_manager_memory_fault_info_r0; + ULONG txm_module_manager_memory_fault_info_r1; + ULONG txm_module_manager_memory_fault_info_r2; + ULONG txm_module_manager_memory_fault_info_r3; + ULONG txm_module_manager_memory_fault_info_r4; + ULONG txm_module_manager_memory_fault_info_r5; + ULONG txm_module_manager_memory_fault_info_r6; + ULONG txm_module_manager_memory_fault_info_r7; + ULONG txm_module_manager_memory_fault_info_r8; + ULONG txm_module_manager_memory_fault_info_r9; + ULONG txm_module_manager_memory_fault_info_r10; + ULONG txm_module_manager_memory_fault_info_r11; + ULONG txm_module_manager_memory_fault_info_r12; + ULONG txm_module_manager_memory_fault_info_lr; + ULONG txm_module_manager_memory_fault_info_cpsr; +} TXM_MODULE_MANAGER_MEMORY_FAULT_INFO; + + +#define TXM_MODULE_MANAGER_FAULT_INFO \ + TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info; + +/* Define the macro to check the stack available in dispatch. */ +#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE + + +/* Define the macro to check the code alignment. */ + +#define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment) \ + { \ + ULONG temp; \ + temp = (ULONG) module_location; \ + temp = temp & (code_alignment - 1); \ + if (temp) \ + { \ + _tx_mutex_put(&_txm_module_manager_mutex); \ + return(TXM_MODULE_ALIGNMENT_ERROR); \ + } \ + } + + +/* Define the macro to adjust the alignment and size for code/data areas. */ + +#define TXM_MODULE_MANAGER_ALIGNMENT_ADJUST(module_preamble, code_size, code_alignment, data_size, data_alignment) _txm_module_manager_alignment_adjust(module_preamble, &code_size, &code_alignment, &data_size, &data_alignment); + + +/* Define the macro to adjust the symbols in the module preamble. */ + +#define TXM_MODULE_MANAGER_CALCULATE_ADJUSTMENTS(properties, shell_function_adjust, start_function_adjust, stop_function_adjust, callback_function_adjust) \ + if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_IAR_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_IAR_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_IAR_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_IAR_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_IAR_CALLBACK_ADJUST; \ + } \ + else if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_RVDS_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_RVDS_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_RVDS_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_RVDS_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_RVDS_CALLBACK_ADJUST; \ + } \ + else \ + { \ + shell_function_adjust = TXM_MODULE_GNU_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_GNU_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_GNU_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_GNU_CALLBACK_ADJUST; \ + } + + +/* Define the macro to populate the thread control block with module port-specific information. + Check if the module is in user mode and set up txm_module_thread_entry_info_kernel_call_dispatcher accordingly. +*/ + +#define TXM_MODULE_MANAGER_THREAD_SETUP(thread_ptr, module_instance) \ + thread_ptr -> tx_thread_module_current_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION; \ + thread_ptr -> tx_thread_module_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION; \ + if (thread_ptr -> tx_thread_module_user_mode) \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_user_mode_entry; \ + } \ + else \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_kernel_dispatch; \ + } + + +/* Define the macro to populate the module control block with module port-specific information. + If memory protection is enabled, set up the MPU registers. +*/ +#define TXM_MODULE_MANAGER_MODULE_SETUP(module_instance) \ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) \ + { \ + _txm_module_manager_mm_register_setup(module_instance); \ + } \ + else \ + { \ + /* Do nothing. */ \ + } + +/* Define the macro to perform port-specific functions when unloading the module. */ +/* Nothing needs to be done for this port. */ +#define TXM_MODULE_MANAGER_MODULE_UNLOAD(module_instance) + + +/* Define the macros to perform port-specific checks when passing pointers to the kernel. */ + +/* Define macro to make sure object is inside the module's data. */ +#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ + _txm_module_manager_inside_data_check(module_instance, obj_ptr, obj_size) + +/* Define some internal prototypes to this module port. */ + +#ifndef TX_SOURCE_CODE +#define txm_module_manager_memory_fault_notify _txm_module_manager_memory_fault_notify +#endif + + +#define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES \ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment); \ +ULONG _txm_module_manager_data_pointer_check(TXM_MODULE_INSTANCE *module_instance, ULONG pointer); \ +VOID _txm_module_manager_memory_fault_handler(VOID); \ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)); \ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \ +ULONG _txm_power_of_two_block_size(ULONG size); \ +ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); \ +ULONG _txm_module_manager_region_size_get(ULONG block_size); \ +UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ULONG obj_ptr, UINT obj_size); + +#define TXM_MODULE_MANAGER_VERSION_ID \ +CHAR _txm_module_manager_version_id[] = \ + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-R4/MPU/IAR Version 6.1 *"; + +#endif + diff --git a/ports_module/cortex-r4/iar/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex-r4/iar/module_lib/src/txm_module_thread_shell_entry.c new file mode 100644 index 00000000..be6d16fd --- /dev/null +++ b/ports_module/cortex-r4/iar/module_lib/src/txm_module_thread_shell_entry.c @@ -0,0 +1,174 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#ifndef TXM_MODULE +#define TXM_MODULE +#endif + +#ifndef TX_SOURCE_CODE +#define TX_SOURCE_CODE +#endif + + +/* Include necessary system files. */ + +#include "txm_module.h" +#include "tx_thread.h" + +/* Define the global module entry pointer from the start thread of the module. */ + +TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; + + +/* Define the dispatch function pointer used in the module implementation. */ + +ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3); + + +/* Define the IAR startup code that clears the uninitialized global data and sets up the + preset global variables. */ + +extern VOID __iar_data_init3(VOID); + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_thread_shell_entry Cortex-R4/MPU/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calls the specified entry function of the thread. It */ +/* also provides a place for the thread's entry function to return. */ +/* If the thread returns, this function places the thread in a */ +/* "COMPLETED" state. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to current thread */ +/* thread_info Pointer to thread entry info */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __iar_data_init3 IAR global initialization function*/ +/* thread_entry Thread's entry function */ +/* tx_thread_resume Resume the module callback thread */ +/* _txm_module_thread_system_suspend Module thread suspension routine */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) +{ + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + VOID (*entry_exit_notify)(TX_THREAD *, UINT); +#endif + + + /* Determine if this is the start thread. If so, we must prepare the module for + execution. If not, simply skip the C startup code. */ + if (thread_info -> txm_module_thread_entry_info_start_thread) + { + /* Initialize the IAR C environment. */ + __iar_data_init3(); + + /* Save the entry info pointer, for later use. */ + _txm_module_entry_info = thread_info; + + /* Save the kernel function dispatch address. This is used to make all resident calls from + the module. */ + _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; + + /* Ensure that we have a valid pointer. */ + while (!_txm_module_kernel_call_dispatcher) + { + /* Loop here, if an error is present getting the dispatch function pointer! + An error here typically indicates the resident portion of _tx_thread_schedule + is not supporting the trap to obtain the function pointer. */ + } + + /* Resume the module's callback thread, already created in the manager. */ + _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); + } + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has been entered! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_ENTRY); + } +#endif + + /* Call current thread's entry function. */ + (thread_info -> txm_module_thread_entry_info_entry) (thread_info -> txm_module_thread_entry_info_parameter); + + /* Suspend thread with a "completed" state. */ + + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine again. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has exited! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_EXIT); + } +#endif + + /* Call actual thread suspension routine. */ + _txm_module_thread_system_suspend(thread_ptr); + +#ifdef TX_SAFETY_CRITICAL + + /* If we ever get here, raise safety critical exception. */ + TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0); +#endif +} + diff --git a/ports_module/cortex-r4/iar/module_manager/src/tx_iar.c b/ports_module/cortex-r4/iar/module_manager/src/tx_iar.c new file mode 100644 index 00000000..11fcefb3 --- /dev/null +++ b/ports_module/cortex-r4/iar/module_manager/src/tx_iar.c @@ -0,0 +1,804 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** IAR Multithreaded Library Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Define IAR library for tools prior to version 8. */ + +#if (__VER__ < 8000000) + + +/* IAR version 7 and below. */ + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_mutex.h" + + +/* This implementation requires that the following macros are defined in the + tx_port.h file and is included with the following code segments: + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. + + Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. +*/ + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT + +#include + + +#if _MULTI_THREAD + +TX_MUTEX __tx_iar_system_lock_mutexes[_MAX_LOCK]; +UINT __tx_iar_system_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_system_lock_no_mutexes; +UINT __tx_iar_system_lock_internal_errors; +UINT __tx_iar_system_lock_isr_caller; + + +/* Define the TLS access function for the IAR library. */ + +void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) +{ + +char _DLIB_TLS_MEMORY *p = 0; + + /* Is there a current thread? */ + if (_tx_thread_current_ptr) + p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; + else + p = (void _DLIB_TLS_MEMORY *) __segment_begin("__DLIB_PERTHREAD"); + p += __IAR_DLIB_PERTHREAD_SYMBOL_OFFSET(symbp); + return (void _DLIB_TLS_MEMORY *) p; +} + + +/* Define mutexes for IAR library. */ + +void __iar_system_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_LOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_system_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_system_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_system_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_system_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_system_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } +} + +void __iar_system_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } +} + + +#if _DLIB_FILE_DESCRIPTOR + +TX_MUTEX __tx_iar_file_lock_mutexes[_MAX_FLOCK]; +UINT __tx_iar_file_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_file_lock_no_mutexes; +UINT __tx_iar_file_lock_internal_errors; +UINT __tx_iar_file_lock_isr_caller; + + +void __iar_file_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_FLOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_file_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_file_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_file_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_file_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_file_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} + +void __iar_file_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} +#endif /* _DLIB_FILE_DESCRIPTOR */ + +#endif /* _MULTI_THREAD */ + +#endif /* TX_ENABLE_IAR_LIBRARY_SUPPORT */ + +#else /* IAR version 8 and above. */ + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_mutex.h" + +/* This implementation requires that the following macros are defined in the + tx_port.h file and is included with the following code segments: + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +void *_tx_iar_create_per_thread_tls_area(void); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); +void __iar_Initlocks(void); + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. + + Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. +*/ + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT + +#include + + +void * __aeabi_read_tp(); + +void* _tx_iar_create_per_thread_tls_area(); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); + +#pragma section="__iar_tls$$DATA" + +/* Define the TLS access function for the IAR library. */ +void * __aeabi_read_tp(void) +{ + void *p = 0; + TX_THREAD *thread_ptr = _tx_thread_current_ptr; + if (thread_ptr) + { + p = thread_ptr->tx_thread_iar_tls_pointer; + } + else + { + p = __section_begin("__iar_tls$$DATA"); + } + return p; +} + +/* Define the TLS creation and destruction to use malloc/free. */ + +void* _tx_iar_create_per_thread_tls_area() +{ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ + void *p = malloc(tls_size); + + /* Initialize TLS-area and run constructors for objects in TLS */ + __iar_tls_init(p); + return p; +} + +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) +{ + /* Destroy objects living in TLS */ + __call_thread_dtors(); + free(tls_ptr); +} + +#ifndef _MAX_LOCK +#define _MAX_LOCK 4 +#endif + +static TX_MUTEX __tx_iar_system_lock_mutexes[_MAX_LOCK]; +static UINT __tx_iar_system_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_system_lock_no_mutexes; +UINT __tx_iar_system_lock_internal_errors; +UINT __tx_iar_system_lock_isr_caller; + + +/* Define mutexes for IAR library. */ + +void __iar_system_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_LOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_system_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_system_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_system_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_system_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_system_Mtxlock(__iar_Rmtx *m) +{ + if (*m) + { + UINT status; + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } + } +} + +void __iar_system_Mtxunlock(__iar_Rmtx *m) +{ + if (*m) + { + UINT status; + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } + } +} + + +#if _DLIB_FILE_DESCRIPTOR + +#include /* Added to get access to FOPEN_MAX */ +#ifndef _MAX_FLOCK +#define _MAX_FLOCK FOPEN_MAX /* Define _MAX_FLOCK as the maximum number of open files */ +#endif + + +TX_MUTEX __tx_iar_file_lock_mutexes[_MAX_FLOCK]; +UINT __tx_iar_file_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_file_lock_no_mutexes; +UINT __tx_iar_file_lock_internal_errors; +UINT __tx_iar_file_lock_isr_caller; + + +void __iar_file_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_FLOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_file_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_file_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_file_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_file_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_file_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} + +void __iar_file_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} +#endif /* _DLIB_FILE_DESCRIPTOR */ + +#endif /* TX_ENABLE_IAR_LIBRARY_SUPPORT */ + +#endif /* IAR version 8 and above. */ diff --git a/ports_module/cortex-r4/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex-r4/iar/module_manager/src/tx_thread_context_restore.s new file mode 100644 index 00000000..4c267979 --- /dev/null +++ b/ports_module/cortex-r4/iar/module_manager/src/tx_thread_context_restore.s @@ -0,0 +1,239 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + +IRQ_MODE EQU 0x12 ; IRQ mode +SVC_MODE EQU 0x13 ; SVC mode +SYS_MODE EQU 0x1F ; SYS mode +DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts +THUMB_MASK DEFINE 0x20 ; Thumb bit mask + +; + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_schedule + EXTERN _tx_thread_preempt_disable + EXTERN _tx_execution_isr_exit +; +; + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-R4/MPU/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_context_restore + ARM +_tx_thread_context_restore +; +; /* Lockout interrupts. */ +; + CPSID i ; Disable IRQ interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + BL _tx_execution_isr_exit ; Call the ISR exit function +#endif +; +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state) +; { +; + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3] ; Pickup system state + SUB r2, r2, #1 ; Decrement the counter + STR r2, [r3] ; Store the counter + CMP r2, #0 ; Was this the first interrupt? + BEQ __tx_thread_not_nested_restore ; If so, not a nested restore +; +; /* Interrupts are nested. */ +; +; /* Just recover the saved registers and return to the point of +; interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +__tx_thread_not_nested_restore +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; || (_tx_thread_preempt_disable)) +; { +; + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup actual current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_restore ; Yes, idle system was interrupted +; + LDR r3, =_tx_thread_preempt_disable ; Pickup preempt disable address + LDR r2, [r3] ; Pickup actual preempt disable flag + CMP r2, #0 ; Is it set? + BNE __tx_thread_no_preempt_restore ; Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr ; Pickup address of execute thread ptr + LDR r2, [r3] ; Pickup actual execute thread pointer + CMP r0, r2 ; Is the same thread highest priority? + BNE __tx_thread_preempt_restore ; No, preemption needs to happen +; +; +__tx_thread_no_preempt_restore +; +; /* Restore interrupted thread or ISR. */ +; +; /* Pickup the saved stack pointer. */ +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; +; /* Recover the saved context and return to the point of interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +; else +; { +__tx_thread_preempt_restore +; + LDMIA sp!, {r3, r10, r12, lr} ; Recover temporarily saved registers + MOV r1, lr ; Save lr (point of interrupt) + CPS #SYS_MODE ; Enter SYS mode + STR r1, [sp, #-4]! ; Save point of interrupt on thread's stack + STMDB sp!, {r4-r12, lr} ; Save upper half of registers on thread's stack + MOV r4, r3 ; Save SPSR in r4 + CPS #IRQ_MODE ; Enter IRQ mode + LDMIA sp!, {r0-r3} ; Recover r0-r3 + CPS #SYS_MODE ; Enter SYS mode + STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + +#ifdef __ARMVFP__ + LDR r2, [r0, #144] ; Pickup the VFP enabled flag + CMP r2, #0 ; Is the VFP enabled? + BEQ _tx_skip_irq_vfp_save ; No, skip VFP IRQ save + VMRS r2, FPSCR ; Pickup the FPSCR + STR r2, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D0-D15} ; Save D0-D15 +_tx_skip_irq_vfp_save +#endif + + MOV r3, #1 ; Build interrupt stack type + STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR + STR sp, [r0, #8] ; Save stack pointer in thread control + ; block +; +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup time-slice variable address + LDR r2, [r3] ; Pickup time-slice + CMP r2, #0 ; Is it active? + BEQ __tx_thread_dont_save_ts ; No, don't save it +; +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r2, [r0, #24] ; Save thread's time-slice + MOV r2, #0 ; Clear value + STR r2, [r3] ; Disable global time-slice flag +; +; } +__tx_thread_dont_save_ts +; +; +; /* Clear the current task pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + MOV r0, #0 ; NULL value + STR r0, [r1] ; Clear current thread pointer +; +; /* Return to the scheduler. */ +; _tx_thread_schedule(); +; + CPS #IRQ_MODE ; Enter IRQ mode + MRS r1, SPSR ; Get SPSR + ORR r1, r1, #SYS_MODE ; Change to SYS Mode + BIC r1, r1, #THUMB_MASK ; Clear thumb bit - slarson + MSR SPSR_cxsf, r1 ; Put SYS Mode in SPSR + LDR lr, =_tx_thread_schedule ; Load scheduler address + MOVS pc, lr ; Return to scheduler +; } +; +__tx_thread_idle_system_restore +; +; /* Just return back to the scheduler! */ +; + LDR lr, =_tx_thread_schedule ; Load scheduler address + MOVS pc, lr ; Return to scheduler +;} +; + END + diff --git a/ports_module/cortex-r4/iar/module_manager/src/tx_thread_context_save.s b/ports_module/cortex-r4/iar/module_manager/src/tx_thread_context_save.s new file mode 100644 index 00000000..3842aa3f --- /dev/null +++ b/ports_module/cortex-r4/iar/module_manager/src/tx_thread_context_save.s @@ -0,0 +1,188 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN __tx_irq_processing_return + EXTERN _tx_execution_isr_enter +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-R4/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_context_save + ARM +_tx_thread_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + STMDB sp!, {r0-r3} ; Save some working registers + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Save the rest of the scratch registers on the stack and return to the +; calling ISR. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + B __tx_irq_processing_return ; Continue IRQ processing +; +__tx_thread_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_save ; If so, interrupt occured in + ; scheduling loop - nothing needs saving! +; +; /* Save minimal context of interrupted thread. */ +; + MRS r2, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r2, r10, r12, lr} ; Store other registers +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + B __tx_irq_processing_return ; Continue IRQ processing +; +; } +; else +; { +; +__tx_thread_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; processing. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + ADD sp, sp, #16 ; Recover saved registers + B __tx_irq_processing_return ; Continue IRQ processing +; +; } +;} +; + +; +; + END + diff --git a/ports_module/cortex-r4/iar/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex-r4/iar/module_manager/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..0ebee6a5 --- /dev/null +++ b/ports_module/cortex-r4/iar/module_manager/src/tx_thread_interrupt_control.s @@ -0,0 +1,89 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + +INT_MASK DEFINE 0x80 ; Interrupt bit mask +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-R4/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_interrupt_control + ARM +_tx_thread_interrupt_control +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r3, CPSR ; Pickup current CPSR + BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits + ORR r1, r1, r0 ; Or-in new interrupt lockout bits +; +; /* Apply the new interrupt posture. */ +; + MSR CPSR_cxsf, r1 ; Setup new CPSR + AND r0, r3, #INT_MASK ; Return previous interrupt mask + + BX lr ; Return to caller +; +;} +; +; + END diff --git a/ports_module/cortex-r4/iar/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex-r4/iar/module_manager/src/tx_thread_interrupt_disable.s new file mode 100644 index 00000000..ff63ba47 --- /dev/null +++ b/ports_module/cortex-r4/iar/module_manager/src/tx_thread_interrupt_disable.s @@ -0,0 +1,81 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled +; +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-R4/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_disable(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_interrupt_disable + ARM +_tx_thread_interrupt_disable??rA +_tx_thread_interrupt_disable +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r0, CPSR ; Pickup current CPSR + CPSID i ; Mask interrupts + BX lr ; Return to caller +;} +; +; + END diff --git a/ports_module/cortex-r4/iar/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex-r4/iar/module_manager/src/tx_thread_interrupt_restore.s new file mode 100644 index 00000000..f95c45a3 --- /dev/null +++ b/ports_module/cortex-r4/iar/module_manager/src/tx_thread_interrupt_restore.s @@ -0,0 +1,76 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-R4/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for restoring interrupts to the state */ +;/* returned by a previous _tx_thread_interrupt_disable call. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;void _tx_thread_interrupt_restore(UINT old_posture) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_interrupt_restore + ARM +_tx_thread_interrupt_restore +; +; /* Apply the new interrupt posture. */ +; + MSR CPSR_cxsf, r0 ; Setup new CPSR + + BX lr ; Return to caller +;} +; + END diff --git a/ports_module/cortex-r4/iar/module_manager/src/tx_thread_irq_nesting_end.s b/ports_module/cortex-r4/iar/module_manager/src/tx_thread_irq_nesting_end.s new file mode 100644 index 00000000..cac0f50f --- /dev/null +++ b/ports_module/cortex-r4/iar/module_manager/src/tx_thread_irq_nesting_end.s @@ -0,0 +1,89 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +IRQ_MODE DEFINE 0x12 ; IRQ mode +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end Cortex-R4/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_irq_nesting_end(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_irq_nesting_end + ARM +_tx_thread_irq_nesting_end + MOV r3, lr ; Save ISR return address + CPSID i ; Disable interrupts + POP {lr} ; Pickup saved lr + CPS #IRQ_MODE ; Switch to IRQ mode + MOV pc, r3 ; Return to ISR +;} +; +; + END + diff --git a/ports_module/cortex-r4/iar/module_manager/src/tx_thread_irq_nesting_start.s b/ports_module/cortex-r4/iar/module_manager/src/tx_thread_irq_nesting_start.s new file mode 100644 index 00000000..5feb87a4 --- /dev/null +++ b/ports_module/cortex-r4/iar/module_manager/src/tx_thread_irq_nesting_start.s @@ -0,0 +1,86 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +SYS_MODE DEFINE 0x1F ; System mode +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start Cortex-R4/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_irq_nesting_start(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_irq_nesting_start + ARM +_tx_thread_irq_nesting_start + MOV r3, lr ; Save ISR return address + CPS #SYS_MODE ; Enter SYS mode + PUSH {lr} ; Save system mode lr on the system mode stack + CPSIE i ; Enable interrupts + MOV pc, r3 ; Return to ISR +;} +; +; + END + diff --git a/ports_module/cortex-r4/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex-r4/iar/module_manager/src/tx_thread_schedule.s new file mode 100644 index 00000000..ebd24a4e --- /dev/null +++ b/ports_module/cortex-r4/iar/module_manager/src/tx_thread_schedule.s @@ -0,0 +1,443 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + EXTERN _tx_thread_execute_ptr + EXTERN _tx_thread_current_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_execution_thread_enter +; + IMPORT _txm_system_mode_enter + IMPORT _txm_system_mode_exit +; +THUMB_MASK EQU 0x20 ; Thumb bit (5) of CPSR/SPSR. +IRQ_MODE EQU 0x12 ; IRQ mode +USR_MODE EQU 0x10 ; USR mode +SVC_MODE EQU 0x13 ; SVC mode +SYS_MODE EQU 0x1F ; SYS mode +MODE_MASK EQU 0x1F ; Mode mask +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-R4/MPU/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_schedule + ARM +_tx_thread_schedule??rA +_tx_thread_schedule + + ; Enter the scheduler. + SVC 0 + + ; We should never get here - ever! +_tx_scheduler_fault__ + B _tx_scheduler_fault__ +;} +; **************************************************************************** + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; SWI_Handler +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + RSEG .text:CODE:NOROOT(2) + PUBLIC SWI_Handler + ARM +SWI_Handler + + STMFD sp!, {r0-r3, r12, lr} ; Store the registers + MOV r1, sp ; Set pointer to parameters + MRS r0, spsr ; Get spsr + STMFD sp!, {r0, r3} ; Store spsr onto stack and another + ; register to maintain 8-byte-aligned stack + TST r0, #THUMB_MASK ; Occurred in Thumb state? + LDRNEH r0, [lr,#-2] ; Yes: Load halfword and... + BICNE r0, r0, #0xFF00 ; ...extract comment field + LDREQ r0, [lr,#-4] ; No: Load word and... + BICEQ r0, r0, #0xFF000000 ; ...extract comment field + + ; r0 now contains SVC number + ; r1 now contains pointer to stacked registers + + ; + ; The service call is handled here + ; + + CMP r0, #0 ; Is it a schedule request? + BEQ _tx_handler_svc_schedule ; Yes, go there + + CMP r0, #1 ; Is it a system mode enter request? + BEQ _tx_handler_svc_super_enter ; Yes, go there + + CMP r0, #2 ; Is it a system mode exit request? + BEQ _tx_handler_svc_super_exit ; Yes, go there + + LDR r2, =0x123456 + CMP r0, r2 ; Is it an ARM request? + BEQ _tx_handler_svc_arm ; Yes, go there + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Unknown SVC argument +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + ; Unrecognized service call +_tx_handler_svc_unrecognized + +_tx_handler_svc_unrecognized_loop ; We should never get here + B _tx_handler_svc_unrecognized_loop + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; SVC 1 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + ; At this point we have an SVC 1, which means we are entering + ; supervisor mode to service a kernel call. +_tx_handler_svc_super_enter + ; Make sure that we have been called from the system mode enter location (security) + LDR r2, =_txm_system_mode_enter ; Load the address of the known call point + SUB r1, lr, #4 ; Calculate the address of the actual call + CMP r1, r2 ; Did we come from txm_module_manager_user_mode_entry? + BNE _tx_handler_svc_unrecognized ; Return to where we came + + ; Clear the user mode flag in the thread structure + LDR r1, =_tx_thread_current_ptr ; Load the current thread pointer address + LDR r2, [r1] ; Load current thread location from the pointer (pointer indirection) + MOV r1, #0 ; Load the new user mode flag value (user mode flag clear -> not user mode -> system) + STR r1, [r2, #0x9C] ; Clear the current user mode selection for thread + + ; Now we enter the system mode and return + LDMFD sp!, {r0, r3} ; Get spsr from the stack + BIC r0, r0, #MODE_MASK ; clear mode field + ORR r0, r0, #SYS_MODE ; system mode code + MSR SPSR_cxsf, r0 ; Restore the spsr + + LDR r1, [r2, #0xA8] ; Load the module kernel stack pointer + CPS #SYS_MODE ; Switch to SYS mode + MOV r3, sp ; Grab thread stack pointer + MOV sp, r1 ; Set SP to kernel stack pointer + CPS #SVC_MODE ; Switch back to SVC mode + STR r3, [r2, #0xB0] ; Save thread stack pointer +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + LDR r3, [r2, #0xAC] ; Load the module kernel stack size + STR r3, [r2, #20] ; Set stack size + LDRD r0, r1, [r2, #0xA4] ; Load the module kernel stack start and end + STRD r0, r1, [r2, #0x0C] ; Set stack start and end +#endif + LDMFD sp!, {r0-r3, r12, pc}^ ; Restore the registers and return + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; SVC 2 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + ; At this point we have an SVC 2, which means we are exiting + ; supervisor mode after servicing a kernel call. +_tx_handler_svc_super_exit + ; Make sure that we have been called from the system mode exit location (security) + LDR r2, =_txm_system_mode_exit ; Load the address of the known call point + SUB r1, lr, #4 ; Calculate the address of the actual call + CMP r1, r2 ; Did we come from txm_module_manager_user_mode_entry? + BNE _tx_handler_svc_unrecognized ; Return to where we came + + ; Set the user mode flag into the thread structure + LDR r1, =_tx_thread_current_ptr ; Load the current thread pointer address + LDR r2, [r1] ; Load the current thread location from the pointer (pointer indirection) + MOV r1, #1 ; Load the new user mode flag value (user mode enabled -> not system anymore) + STR r1, [r2, #0x9C] ; Clear the current user mode selection for thread + + ; Now we enter user mode (exit the system mode) and return + LDMFD sp!, {r0, r3} ; Get spsr from the stack + BIC r0, r0, #MODE_MASK ; clear mode field + ORR r0, r0, #USR_MODE ; user mode code + MSR SPSR_cxsf, r0 ; Restore the spsr + + LDR r1, [r2, #0xB0] ; Load the module thread stack pointer + CPS #SYS_MODE ; Switch to SYS mode + MOV sp, r1 ; Set SP back to thread stack pointer + CPS #SVC_MODE ; Switch back to SVC mode +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + LDR r3, [r2, #0xBC] ; Load the module thread stack size + STR r3, [r2, #20] ; Set stack size + LDRD r0, r1, [r2, #0xB4] ; Load the module thread stack start and end + STRD r0, r1, [r2, #0x0C] ; Set stack start and end +#endif + LDMFD sp!, {r0-r3, r12, pc}^ ; Restore the registers and return + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; ARM Semihosting +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +_tx_handler_svc_arm + + ; *** TODO: handle semihosting requests or ARM angel requests *** + + ; just return + LDMFD sp!, {r0, r3} ; Get spsr from the stack + MSR SPSR_cxsf, r0 ; Restore the spsr + LDMFD sp!, {r0-r3, r12, pc}^ ; Restore the registers and return + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; SVC 0 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + ; At this point we have an SVC 0: enter the scheduler. +_tx_handler_svc_schedule + + LDMFD sp!, {r0, r3} ; Get spsr from stack + MSR SPSR_cxsf, r0 ; Restore spsr + LDMFD sp!, {r0-r3, r12, lr} ; Restore the registers + + ; This code waits for a thread control block pointer to appear in + ; the _tx_thread_execute_ptr variable. Once a thread pointer appears + ; in the variable, the corresponding thread is resumed. +; +; /* Enable interrupts. */ +; + CPSIE i ; Enable IRQ interrupts + +; +; /* Wait for a thread to execute. */ +; do +; { + LDR r1, =_tx_thread_execute_ptr ; Address of thread execute ptr +; +__tx_thread_schedule_loop + LDR r0, [r1, #0] ; Pickup next thread to execute + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_schedule_loop ; If so, keep looking for a thread +; +; } +; while(_tx_thread_execute_ptr == TX_NULL); +; +; /* Yes! We have a thread to execute. Lockout interrupts and +; transfer control to it. */ +; + CPSID i ; Disable interrupts +; +; /* Setup the current thread pointer. */ +; _tx_thread_current_ptr = _tx_thread_execute_ptr; +; + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread + STR r0, [r1, #0] ; Setup current thread pointer +; +; /* Increment the run count for this thread. */ +; _tx_thread_current_ptr -> tx_thread_run_count++; +; + LDR r2, [r0, #4] ; Pickup run counter + LDR r3, [r0, #24] ; Pickup time-slice for this thread + ADD r2, r2, #1 ; Increment thread run-counter + STR r2, [r0, #4] ; Store the new run counter +; +; /* Setup time-slice, if present. */ +; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; +; + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice variable + STR r3, [r2, #0] ; Setup time-slice +; +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + MOV r5, r0 ; Save r0 + BL _tx_execution_thread_enter ; Call the thread execution enter function + MOV r0, r5 ; Restore r0 +#endif + + ; Determine if an interrupt frame or a synchronous task suspension frame is present. + CPS #SYS_MODE ; Enter SYS mode + LDR sp, [r0, #8] ; Switch to thread stack pointer + LDMIA sp!, {r4, r5} ; Pickup the stack type and saved CPSR + CPS #SVC_MODE ; Enter SVC mode + + ; ************************************************************************** + ; Set up MPU for module. + LDR r1, [r0, #0x94] ; Pickup module instance pointer + CMP r1, #0 ; Valid module pointer? + BEQ _tx_end_mpu_update ; No - skip memory protection setup + LDR r2, [r0, #0xA0] ; Pickup tx_thread_module_user_mode + CMP r2, #1 ; In user mode? + BNE _tx_end_mpu_update ; No - skip memory protection setup + ; Is the MPU already set up for this module? + ; Pickup the first data entry to check (txm_module_instance_mpu_registers[5]) + LDR r2, [r1, #0xA0] ; Pickup txm_module_instance_mpu_registers[5] + MOV r3, #5 ; Select region 5 + MCR p15, 0, r3, c6, c2, 0 ; Select region 5 + MRC p15, 0, r3, c6, c1, 0 ; Read DRBAR into r3 + CMP r2, r3 ; Is module already loaded? + BEQ _tx_end_mpu_update ; Yes - skip memory protection setup + + ; Disable MPU before applying new regions. + MRC p15, 0, r2, c1, c0, 0 ; Read SCTLR + BIC r2, r2, #1 ; Disable MPU + DSB + MCR p15, 0, r2, c1, c0, 0 ; Write to SCTLR + ISB + ; Loop to load MPU registers + MOV r3, #0 ; Loop index + ADD r1, r1, #0x64 ; Build address of MPU register table +_tx_mpu_loop + LDR r2, [r1] ; Pickup txm_module_mpu_region_address + MCR p15, 0, r3, c6, c2, 0 ; Select region + MCR p15, 0, r2, c6, c1, 0 ; Write to DRBAR + ADD r1, r1, #4 ; Increment to next MPU parameter + LDR r2, [r1] ; Pickup txm_module_mpu_region_size + MCR p15, 0, r2, c6, c1, 2 ; Write to DRSR + ADD r1, r1, #4 ; Increment to next MPU parameter + LDR r2, [r1] ; Pickup txm_module_mpu_region_attributes + MCR p15, 0, r2, c6, c1, 4 ; Write to DRACR + ADD r1, r1, #4 ; Increment to next MPU parameter + ADD r3, r3, #1 ; Increment loop index + CMP r3, #0xB ; Check the limit + BLE _tx_mpu_loop ; Loop if not finished + + ; Enable MPU with new regions. + MRC p15, 0, r2, c1, c0, 0 ; Read SCTLR + ORR r2, r2, #1 ; Enable MPU + ORR r2, r2, #0x20000 ; Enable Background Region + DSB + MCR p15, 0, r2, c1, c0, 0 ; Write to SCTLR + ISB + ; +_tx_end_mpu_update + ; ************************************************************************** + + CMP r4, #0 ; Check for synchronous context switch + BEQ _tx_solicited_return + + MSR SPSR_cxsf, r5 ; Setup SPSR for return + LDR r1, [r0, #8] ; Get thread SP + LDR lr, [r1, #0x40] ; Get thread PC + CPS #SYS_MODE ; Enter SYS mode + +#ifdef __ARMVFP__ + LDR r2, [r0, #144] ; Pickup the VFP enabled flag + CMP r2, #0 ; Is the VFP enabled? + BEQ _tx_skip_interrupt_vfp_restore ; No, skip VFP interrupt restore + VLDMIA sp!, {D0-D15} ; Recover D0-D15 + LDR r4, [sp], #4 ; Pickup FPSCR + VMSR FPSCR, r4 ; Restore FPSCR + CPS #SVC_MODE ; Enter SVC mode + LDR lr, [r1, #0x144] ; Get thread PC + CPS #SYS_MODE ; Enter SYS mode +_tx_skip_interrupt_vfp_restore +#endif + + LDMIA sp!, {r0-r12, lr} ; Restore registers + ADD sp, sp, #4 ; Fix stack pointer + CPS #SVC_MODE ; Enter SVC mode + SUBS pc, lr, #0 ; Return to point of thread interrupt + +_tx_solicited_return + MOV r2, r5 ; Move CPSR to scratch register + CPS #SYS_MODE ; Enter SYS mode + +#ifdef __ARMVFP__ + LDR r1, [r0, #144] ; Pickup the VFP enabled flag + CMP r1, #0 ; Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_restore ; No, skip VFP solicited restore + VLDMIA sp!, {D8-D15} ; Recover D8-D15 + LDR r4, [sp], #4 ; Pickup FPSCR + VMSR FPSCR, r4 ; Restore FPSCR +_tx_skip_solicited_vfp_restore +#endif + + LDMIA sp!, {r4-r11, lr} ; Restore registers + MOV r1, lr ; Copy lr to r1 to preserve across mode change + CPS #SVC_MODE ; Enter SVC mode + MSR SPSR_cxsf, r2 ; Recover CPSR + SUBS pc, r1, #0 ; Return to thread synchronously + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; End SWI_Handler +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +#ifdef __ARMVFP__ + PUBLIC tx_thread_vfp_enable + CODE32 +tx_thread_vfp_enable??rA +tx_thread_vfp_enable + MRS r2, CPSR ; Pickup the CPSR + CPSID i ; Disable IRQ interrupts + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup current thread pointer + CMP r1, #0 ; Check for NULL thread pointer + BEQ __tx_no_thread_to_enable ; If NULL, skip VFP enable + MOV r0, #1 ; Build enable value + STR r0, [r1, #144] ; Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_enable: + MSR CPSR_cxsf, r2 ; Recover CPSR + BX LR ; Return to caller + + PUBLIC tx_thread_vfp_disable + CODE32 +tx_thread_vfp_disable??rA +tx_thread_vfp_disable + MRS r2, CPSR ; Pickup the CPSR + CPSID i ; Disable IRQ interrupts + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup current thread pointer + CMP r1, #0 ; Check for NULL thread pointer + BEQ __tx_no_thread_to_disable ; If NULL, skip VFP disable + MOV r0, #0 ; Build disable value + STR r0, [r1, #144] ; Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_disable: + MSR CPSR_cxsf, r2 ; Recover CPSR + BX LR ; Return to caller +#endif + + END + diff --git a/ports_module/cortex-r4/iar/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex-r4/iar/module_manager/src/tx_thread_stack_build.s new file mode 100644 index 00000000..8795214a --- /dev/null +++ b/ports_module/cortex-r4/iar/module_manager/src/tx_thread_stack_build.s @@ -0,0 +1,142 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +SYS_MODE DEFINE 0x1F ; SYS mode +CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints enabled +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-R4/MPU/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_stack_build + + ARM +_tx_thread_stack_build +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-R4 should look like the following after it is built: +; +; Stack Top: 1 Interrupt stack frame type +; CPSR Initial value for CPSR +; a1 (r0) Initial value for a1 +; a2 (r1) Initial value for a2 +; a3 (r2) Initial value for a3 +; a4 (r3) Initial value for a4 +; v1 (r4) Initial value for v1 +; v2 (r5) Initial value for v2 +; v3 (r6) Initial value for v3 +; v4 (r7) Initial value for v4 +; v5 (r8) Initial value for v5 +; sb (r9) Initial value for sb +; sl (r10) Initial value for sl +; fp (r11) Initial value for fp +; ip (r12) Initial value for ip +; lr (r14) Initial value for lr +; pc (r15) Initial value for pc +; 0 For stack backtracing +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #7 ; Ensure 8-byte alignment + SUB r2, r2, #76 ; Allocate space for the stack frame +; +; /* Actually build the stack frame. */ +; + MOV r3, #1 ; Build interrupt stack type + STR r3, [r2, #0] ; Store stack type + MOV r3, #0 ; Build initial register value + STR r3, [r2, #8] ; Store initial r0 + STR r3, [r2, #12] ; Store initial r1 + STR r3, [r2, #16] ; Store initial r2 + STR r3, [r2, #20] ; Store initial r3 + STR r3, [r2, #24] ; Store initial r4 + STR r3, [r2, #28] ; Store initial r5 + STR r3, [r2, #32] ; Store initial r6 + STR r3, [r2, #36] ; Store initial r7 + STR r3, [r2, #40] ; Store initial r8 + STR r3, [r2, #44] ; Store initial r9 + LDR r3, [r0, #12] ; Pickup stack starting address + STR r3, [r2, #48] ; Store initial r10 (sl) + MOV r3, #0 ; Build initial register value + STR r3, [r2, #52] ; Store initial r11 + STR r3, [r2, #56] ; Store initial r12 + STR r3, [r2, #60] ; Store initial lr + STR r1, [r2, #64] ; Store initial pc + STR r3, [r2, #68] ; 0 for back-trace + MRS r1, CPSR ; Pickup CPSR + BIC r1, r1, #CPSR_MASK ; Mask mode bits of CPSR + ORR r3, r1, #SYS_MODE ; Build CPSR, SYS mode, interrupts enabled + STR r3, [r2, #4] ; Store initial CPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block + + BX lr ; Return to caller +;} + END + diff --git a/ports_module/cortex-r4/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex-r4/iar/module_manager/src/tx_thread_system_return.s new file mode 100644 index 00000000..68a53abe --- /dev/null +++ b/ports_module/cortex-r4/iar/module_manager/src/tx_thread_system_return.s @@ -0,0 +1,145 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + EXTERN _tx_thread_current_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_schedule + EXTERN _tx_execution_thread_exit +; +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-R4/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_system_return + ARM +_tx_thread_system_return??rA +_tx_thread_system_return +; +; /* Lockout interrupts. */ +; + MRS r1, CPSR ; Pickup the CPSR + CPSID i ; Disable interrupts +; /* Save minimal context on the stack. */ +; + STMDB sp!, {r4-r11, lr} ; Save minimal context + LDR r5, =_tx_thread_current_ptr ; Pickup address of current ptr + LDR r6, [r5, #0] ; Pickup current thread pointer + +#ifdef __ARMVFP__ + LDR r0, [r6, #144] ; Pickup the VFP enabled flag + CMP r0, #0 ; Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_save ; No, skip VFP solicited save + VMRS r4, FPSCR ; Pickup the FPSCR + STR r4, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D8-D15} ; Save D8-D15 +_tx_skip_solicited_vfp_save: +#endif + + MOV r0, #0 ; Build a solicited stack type + STMDB sp!, {r0-r1} ; Save type and CPSR +; +; +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + BL _tx_execution_thread_exit ; Call the thread exit function +#endif + + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + LDR r1, [r2, #0] ; Pickup current time slice +; +; /* Save current stack and switch to system stack. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; sp = _tx_thread_system_stack_ptr; +; + STR sp, [r6, #8] ; Save thread stack pointer +; +; /* Determine if the time-slice is active. */ +; if (_tx_timer_time_slice) +; { +; + MOV r4, #0 ; Build clear value + CMP r1, #0 ; Is a time-slice active? + BEQ __tx_thread_dont_save_ts ; No, don't save the time-slice +; +; /* Save time-slice for the thread and clear the current time-slice. */ +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r4, [r2, #0] ; Clear time-slice + STR r1, [r6, #24] ; Save current time-slice +; +; } +__tx_thread_dont_save_ts +; +; /* Clear the current thread pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + STR r4, [r5, #0] ; Clear current thread pointer + B _tx_thread_schedule ; Jump to scheduler! +; +;} + END + diff --git a/ports_module/cortex-r4/iar/module_manager/src/tx_thread_vectored_context_save.s b/ports_module/cortex-r4/iar/module_manager/src/tx_thread_vectored_context_save.s new file mode 100644 index 00000000..8eab53d2 --- /dev/null +++ b/ports_module/cortex-r4/iar/module_manager/src/tx_thread_vectored_context_save.s @@ -0,0 +1,174 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN _tx_execution_isr_enter +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save Cortex-R4/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_vectored_context_save(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_vectored_context_save + ARM +_tx_thread_vectored_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, the minimal context is already saved, and the +; lr register contains the return ISR address. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Note: Minimal context of interrupted thread is already saved. */ +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + BX lr ; Return to caller +; +__tx_thread_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_save ; If so, interrupt occured in + ; scheduling loop - nothing needs saving! +; +; /* Note: Minimal context of interrupted thread is already saved. */ +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + BX lr ; Return to caller +; +; } +; else +; { +; +__tx_thread_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; processing. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + ADD sp, sp, #32 ; Recover saved registers + MOV pc, lr ; Return to caller +; +; } +;} + END + diff --git a/ports_module/cortex-r4/iar/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex-r4/iar/module_manager/src/tx_timer_interrupt.s new file mode 100644 index 00000000..61578203 --- /dev/null +++ b/ports_module/cortex-r4/iar/module_manager/src/tx_timer_interrupt.s @@ -0,0 +1,247 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;Define Assembly language external references... +; + EXTERN _tx_timer_time_slice + EXTERN _tx_timer_system_clock + EXTERN _tx_timer_current_ptr + EXTERN _tx_timer_list_start + EXTERN _tx_timer_list_end + EXTERN _tx_timer_expired_time_slice + EXTERN _tx_timer_expired + EXTERN _tx_thread_time_slice + EXTERN _tx_timer_expiration_process +; +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-R4/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time-slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_timer_interrupt + ARM +_tx_timer_interrupt +; +; /* Upon entry to this routine, it is assumed that context save has already +; been called, and therefore the compiler scratch registers are available +; for use. */ +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + LDR r1, =_tx_timer_system_clock ; Pickup address of system clock + LDR r0, [r1, #0] ; Pickup system clock + ADD r0, r0, #1 ; Increment system clock + STR r0, [r1, #0] ; Store new system clock +; +; /* Test for time-slice expiration. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r2, [r3, #0] ; Pickup time-slice + CMP r2, #0 ; Is it non-active? + BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing +; +; /* Decrement the time_slice. */ +; _tx_timer_time_slice--; +; + SUB r2, r2, #1 ; Decrement the time-slice + STR r2, [r3, #0] ; Store new time-slice value +; +; /* Check for expiration. */ +; if (__tx_timer_time_slice == 0) +; + CMP r2, #0 ; Has it expired? + BNE __tx_timer_no_time_slice ; No, skip expiration processing +; +; /* Set the time-slice expired flag. */ +; _tx_timer_expired_time_slice = TX_TRUE; +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup address of expired flag + MOV r0, #1 ; Build expired value + STR r0, [r3, #0] ; Set time-slice expiration flag +; +; } +; +__tx_timer_no_time_slice +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + LDR r1, =_tx_timer_current_ptr ; Pickup current timer pointer addr + LDR r0, [r1, #0] ; Pickup current timer + LDR r2, [r0, #0] ; Pickup timer list entry + CMP r2, #0 ; Is there anything in the list? + BEQ __tx_timer_no_timer ; No, just increment the timer +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + LDR r3, =_tx_timer_expired ; Pickup expiration flag address + MOV r2, #1 ; Build expired value + STR r2, [r3, #0] ; Set expired flag + B __tx_timer_done ; Finished timer processing +; +; } +; else +; { +__tx_timer_no_timer +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ADD r0, r0, #4 ; Move to next timer +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + LDR r3, =_tx_timer_list_end ; Pickup addr of timer list end + LDR r2, [r3, #0] ; Pickup list end + CMP r0, r2 ; Are we at list end? + BNE __tx_timer_skip_wrap ; No, skip wrap-around logic +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + LDR r3, =_tx_timer_list_start ; Pickup addr of timer list start + LDR r0, [r3, #0] ; Set current pointer to list start +; +__tx_timer_skip_wrap +; + STR r0, [r1, #0] ; Store new current timer pointer +; } +; +__tx_timer_done +; +; +; /* See if anything has expired. */ +; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of expired flag + LDR r2, [r3, #0] ; Pickup time-slice expired flag + CMP r2, #0 ; Did a time-slice expire? + BNE __tx_something_expired ; If non-zero, time-slice expired + LDR r1, =_tx_timer_expired ; Pickup addr of other expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Did a timer expire? + BEQ __tx_timer_nothing_expired ; No, nothing expired +; +__tx_something_expired +; +; + STMDB sp!, {r0, lr} ; Save the lr register on the stack + ; and save r0 just to keep 8-byte alignment +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + LDR r1, =_tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Check for timer expiration + BEQ __tx_timer_dont_activate ; If not set, skip timer activation +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + BL _tx_timer_expiration_process ; Call the timer expiration handling routine +; +; } +__tx_timer_dont_activate +; +; /* Did time slice expire? */ +; if (_tx_timer_expired_time_slice) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r2, [r3, #0] ; Pickup the actual flag + CMP r2, #0 ; See if the flag is set + BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing +; +; /* Time slice interrupted thread. */ +; _tx_thread_time_slice(); + + BL _tx_thread_time_slice ; Call time-slice processing +; +; } +; +__tx_timer_not_ts_expiration +; +; + LDMIA sp!, {r0, lr} ; Recover lr register (r0 is just there for + ; the 8-byte stack alignment +; +; } +; +__tx_timer_nothing_expired +; + BX lr ; Return to caller +; +;} + END + diff --git a/ports_module/cortex-r4/iar/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex-r4/iar/module_manager/src/txm_module_manager_alignment_adjust.c new file mode 100644 index 00000000..2500314b --- /dev/null +++ b/ports_module/cortex-r4/iar/module_manager/src/txm_module_manager_alignment_adjust.c @@ -0,0 +1,188 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_power_of_two_block_size Cortex-R4/MPU/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calculates a power of two size at or immediately above*/ +/* the input size and returns it to the caller. */ +/* */ +/* INPUT */ +/* */ +/* size Block size */ +/* */ +/* OUTPUT */ +/* */ +/* calculated size Rounded up to power of two */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-R */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_power_of_two_block_size(ULONG size) +{ + /* Check for 0 size. */ + if(size == 0) + return 0; + + /* Minimum MPU block size is 32. */ + if(size <= 32) + return 32; + + /* Bit twiddling trick to round to next high power of 2 + (if original size is power of 2, it will return original size. Perfect!) */ + size--; + size |= size >> 1; + size |= size >> 2; + size |= size >> 4; + size |= size >> 8; + size |= size >> 16; + size++; + + /* Return a power of 2 size at or above the input size. */ + return(size); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_alignment_adjust Cortex-R4/MPU/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function adjusts the alignment and size of the code and data */ +/* section for a given module implementation. */ +/* */ +/* INPUT */ +/* */ +/* module_preamble Pointer to module preamble */ +/* code_size Size of the code area (updated) */ +/* code_alignment Code area alignment (updated) */ +/* data_size Size of data area (updated) */ +/* data_alignment Data area alignment (updated) */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_power_of_two_block_size Calculate power of two size */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, + ULONG *code_size, + ULONG *code_alignment, + ULONG *data_size, + ULONG *data_alignment) +{ + +ULONG local_code_size; +ULONG local_code_alignment; +ULONG local_data_size; +ULONG local_data_alignment; +ULONG code_size_accum; +ULONG data_size_accum; + + /* Copy the input parameters into local variables for ease of use. */ + local_code_size = *code_size; + local_code_alignment = *code_alignment; + local_data_size = *data_size; + local_data_alignment = *data_alignment; + + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + local_code_alignment = _txm_power_of_two_block_size(local_code_size) >> 2; + code_size_accum = local_code_alignment + local_code_alignment; + code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); + code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); + local_code_size = code_size_accum; + + /* Determine data block sizes. Minimize the alignment requirement. + There are 4 MPU data entries available. The following is how the data size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to data size. + 2. 1/4 of the largest power of two that is greater than or equal to data size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + local_data_alignment = _txm_power_of_two_block_size(local_data_size) >> 2; + data_size_accum = local_data_alignment + local_data_alignment; + data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); + data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); + local_data_size = data_size_accum; + + /* Return all the information to the caller. */ + *code_size = local_code_size; + *code_alignment = local_code_alignment; + *data_size = local_data_size; + *data_alignment = local_data_alignment; +} + + + diff --git a/ports_module/cortex-r4/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex-r4/iar/module_manager/src/txm_module_manager_external_memory_enable.c new file mode 100644 index 00000000..c59fc069 --- /dev/null +++ b/ports_module/cortex-r4/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -0,0 +1,189 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_mutex.h" +#include "tx_queue.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_external_memory_enable Cortex-R4/MPU/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function adds an entry in the MPU table for a shared */ +/* memory space. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* start_address Start address of memory */ +/* length Length of external memory */ +/* attributes Memory attributes (r/w) */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_mutex_get Get protection mutex */ +/* _tx_mutex_put Release protection mutex */ +/* _txm_power_of_two_block_size Round length to power of two */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, + VOID *start_address, + ULONG length, + UINT attributes) +{ + +ULONG block_size; +ULONG region_size; +ULONG srd_bits; +ULONG size_register; +ULONG address; +ULONG shared_index; +ULONG attributes_check = 0; + + /* Determine if the module manager has been initialized. */ + if (_txm_module_manager_ready != TX_TRUE) + { + /* Module manager has not been initialized. */ + return(TX_NOT_AVAILABLE); + } + + /* Determine if the module is valid. */ + if (module_instance == TX_NULL) + { + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Get module manager protection mutex. */ + _tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER); + + /* Determine if the module instance is valid. */ + if (module_instance -> txm_module_instance_id != TXM_MODULE_ID) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Determine if the module instance is in the loaded state. */ + if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if the module is not ready. */ + return(TX_START_ERROR); + } + + /* Determine if there are shared memory entries available. */ + if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* No more entries available. */ + return(TX_NO_MEMORY); + } + + /* Start address and length must adhere to Cortex-R MPU. + The address must align with the block size. */ + + block_size = _txm_power_of_two_block_size(length); + address = (ULONG) start_address; + if(address != (address & ~(block_size - 1))) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return alignment error. */ + return(TXM_MODULE_ALIGNMENT_ERROR); + } + + /* At this point, we have a valid address and block size. + Set up MPU registers. */ + + /* Generate index into shared memory entries. */ + shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; + + /* Save address register. */ + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address; + + /* Calculate the region size. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + /* Calculate the subregion bits. */ + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); + + /* Save size register. */ + size_register = srd_bits | region_size | TXM_ENABLE_REGION; + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_size = size_register; + + /* Check for optional attributes. */ + if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) + { + attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; + } + + /* Save attributes register. */ + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attributes = attributes_check | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; + + /* Keep track of shared memory address and length in module instance. */ + module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; + module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; + + /* Increment counter. */ + module_instance -> txm_module_instance_shared_memory_count++; + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/ports_module/cortex-r4/iar/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex-r4/iar/module_manager/src/txm_module_manager_memory_fault_handler.c new file mode 100644 index 00000000..4bc7c3aa --- /dev/null +++ b/ports_module/cortex-r4/iar/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -0,0 +1,112 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + +/* Define a macro that can be used to allocate global variables useful to + store information about the last fault. This macro is defined in + txm_module_port.h and is usually populated in the assembly language + fault handling prior to the code calling _txm_module_manager_memory_fault_handler. */ + +TXM_MODULE_MANAGER_FAULT_INFO + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_handler Cortex-R4/MPU/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles a fault associated with a memory protected */ +/* module. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_terminate Terminate thread */ +/* */ +/* CALLED BY */ +/* */ +/* Fault handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_memory_fault_handler(VOID) +{ + +TXM_MODULE_INSTANCE *module_instance_ptr; +TX_THREAD *thread_ptr; + + + /* Pickup the current thread. */ + thread_ptr = _tx_thread_current_ptr; + + /* Initialize the module instance pointer to NULL. */ + module_instance_ptr = TX_NULL; + + /* Is there a thread? */ + if (thread_ptr) + { + /* Pickup the module instance. */ + module_instance_ptr = thread_ptr -> tx_thread_module_instance_ptr; + + /* Terminate the current thread. */ + _tx_thread_terminate(_tx_thread_current_ptr); + } + + /* Determine if there is a user memory fault notification callback. */ + if (_txm_module_manager_fault_notify) + { + /* Yes, call the user's notification memory fault callback. */ + (_txm_module_manager_fault_notify)(thread_ptr, module_instance_ptr); + } +} + diff --git a/ports_module/cortex-r4/iar/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex-r4/iar/module_manager/src/txm_module_manager_memory_fault_notify.c new file mode 100644 index 00000000..c8244c2b --- /dev/null +++ b/ports_module/cortex-r4/iar/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -0,0 +1,84 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the external user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_notify Cortex-R4/MPU/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application callback when/if a memory */ +/* fault occurs. The supplied thread is automatically terminated, but */ +/* any other threads in the same module may still execute. */ +/* */ +/* INPUT */ +/* */ +/* notify_function Memory fault notification */ +/* function, NULL disables. */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +{ + /* Setup notification function. */ + _txm_module_manager_fault_notify = notify_function; + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/ports_module/cortex-r4/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex-r4/iar/module_manager/src/txm_module_manager_mm_register_setup.c new file mode 100644 index 00000000..b2c21835 --- /dev/null +++ b/ports_module/cortex-r4/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -0,0 +1,534 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_region_size_get Cortex-R4/MPU/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function converts the region size in bytes to the block size */ +/* for the Cortex-R4 MPU specification. */ +/* */ +/* INPUT */ +/* */ +/* block_size Size of the block in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* MPU size specification */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_module_manager_region_size_get(ULONG block_size) +{ + +ULONG return_value; + + /* Process relative to the input block size. */ + if (block_size == 32) + { + return_value = 0x04; + } + else if (block_size == 64) + { + return_value = 0x05; + } + else if (block_size == 128) + { + return_value = 0x06; + } + else if (block_size == 256) + { + return_value = 0x07; + } + else if (block_size == 512) + { + return_value = 0x08; + } + else if (block_size == 1024) + { + return_value = 0x09; + } + else if (block_size == 2048) + { + return_value = 0x0A; + } + else if (block_size == 4096) + { + return_value = 0x0B; + } + else if (block_size == 8192) + { + return_value = 0x0C; + } + else if (block_size == 16384) + { + return_value = 0x0D; + } + else if (block_size == 32768) + { + return_value = 0x0E; + } + else if (block_size == 65536) + { + return_value = 0x0F; + } + else if (block_size == 131072) + { + return_value = 0x10; + } + else if (block_size == 262144) + { + return_value = 0x11; + } + else if (block_size == 524288) + { + return_value = 0x12; + } + else if (block_size == 1048576) + { + return_value = 0x13; + } + else if (block_size == 2097152) + { + return_value = 0x14; + } + else + { + /* Max 4MB MPU pages for modules. */ + return_value = 0x15; + } + + return(return_value); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_calculate_srd_bits Cortex-R4/MPU/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calculates the SRD bits that need to be set to */ +/* protect "length" bytes in a block. */ +/* */ +/* INPUT */ +/* */ +/* block_size Size of the block in bytes */ +/* length Actual length in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* SRD bits to be OR'ed with region attribute register. */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) +{ + +ULONG srd_bits = 0; +UINT srd_bit_index; + + /* length is smaller than block_size, set SRD bits if block_size is 256 or more. */ + if((block_size >= 256) && (length < block_size)) + { + /* Divide block_size by 8 by shifting right 3. Result is size of subregion. */ + block_size = block_size >> 3; + + /* Set SRD index into attribute register. */ + srd_bit_index = 8; + + /* If subregion overlaps length, move to the next subregion. */ + while(length > block_size) + { + length = length - block_size; + srd_bit_index++; + } + + /* Check for a portion of code remaining. */ + if(length) + { + srd_bit_index++; + } + + /* Set unused subregion bits. */ + while(srd_bit_index < 16) + { + srd_bits = srd_bits | (0x1 << srd_bit_index); + srd_bit_index++; + } + } + + return(srd_bits); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_mm_register_setup Cortex-R4/MPU/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets up the MPU register definitions based on the */ +/* module's memory characteristics. */ +/* MPU layout for the Cortex-R4: */ +/* Entry Description */ +/* 0 Kernel mode entry */ +/* 1 Module code region */ +/* 2 Module code region */ +/* 3 Module code region */ +/* 4 Module code region */ +/* 5 Module data region */ +/* 6 Module data region */ +/* 7 Module data region */ +/* 8 Module data region */ +/* 9 Module shared memory region */ +/* 10 Module shared memory region */ +/* 11 Module shared memory region */ +/* */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* */ +/* OUTPUT */ +/* */ +/* MPU specifications for module in module_instance */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_manager_region_size_get */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_thread_create */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) +{ + +ULONG code_address; +ULONG code_size; +ULONG data_address; +ULONG data_size; +ULONG start_stop_stack_size; +ULONG callback_stack_size; +ULONG block_size; +ULONG base_address_register; +ULONG size_register; +ULONG region_size; +ULONG srd_bits = 0; +UINT mpu_table_index; +UINT i; + + + /* Setup the first region for kernel mode entry. */ + + /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = (ULONG) _txm_module_manager_user_mode_entry; + + /* Set the size (32 bytes) and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_size = (_txm_module_manager_region_size_get(32) << 1) | TXM_ENABLE_REGION; + + /* Set attributes. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attributes = TXM_MODULE_MPU_CODE_ACCESS_CONTROL; + + /* End of kernel mode entry setup. */ + + /* Setup code protection. */ + + /* Initialize the MPU table index. */ + mpu_table_index = 1; + + /* Pickup code starting address and actual size. */ + code_address = (ULONG) module_instance -> txm_module_instance_code_start; + code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; + + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + + /* Now loop through to setup MPU protection for the code area. */ + for (i = 0; i < TXM_MODULE_MPU_CODE_ENTRIES; i++) + { + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + if (i < 2) + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + } + + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ + else if (i == 2) + { + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size) >> 1; + } + + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + else + { + /* Calculate remaining space. */ + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + + /* Build the base address register. */ + base_address_register = (code_address & ~(block_size - 1)); + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Build the size register. */ + size_register = srd_bits | region_size | TXM_ENABLE_REGION; + + /* Setup the MPU address, size, and attribute registers. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = base_address_register; + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_size = size_register; + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attributes = TXM_MODULE_MPU_CODE_ACCESS_CONTROL; + + /* Adjust the code address. */ + code_address = code_address + block_size; + + /* Increment MPU table index. */ + mpu_table_index++; + } + /* End of code protection. */ + + /* Setup data protection. */ + + /* Reset SRD bitfield. */ + srd_bits = 0; + + /* Pickup data starting address and actual size. */ + data_address = (ULONG) module_instance -> txm_module_instance_data_start; + + /* Adjust the size of the module elements to be aligned to the default alignment. We do this + so that when we partition the allocated memory, we can simply place these regions right beside + each other without having to align their pointers. Note this only works when they all have + the same alignment. */ + + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; + start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; + callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; + + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + /* Update the data size to include thread stacks. */ + data_size = data_size + start_stop_stack_size + callback_stack_size; + + /* Determine data block sizes. Minimize the alignment requirement. + There are 4 MPU data entries available. The following is how the data size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to data size. + 2. 1/4 of the largest power of two that is greater than or equal to data size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + + /* Now loop through to setup MPU protection for the data area. */ + for (i = 0; i < TXM_MODULE_MPU_DATA_ENTRIES; i++) + { + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to data size. */ + if (i < 2) + { + block_size = _txm_power_of_two_block_size(data_size) >> 2; + } + + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ + else if (i == 2) + { + /* Subtract (block_size*2) from data_size to calculate remaining space. */ + data_size = data_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(data_size) >> 1; + } + + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + else + { + /* Calculate remaining space. */ + data_size = data_size - block_size; + block_size = _txm_power_of_two_block_size(data_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + } + + /* Build the base address register. */ + base_address_register = (data_address & ~(block_size - 1)); + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Build the size register. */ + size_register = srd_bits | region_size | TXM_ENABLE_REGION; + + /* Setup the MPU address, size, and attribute registers. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = base_address_register; + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_size = size_register; + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attributes = TXM_MODULE_MPU_DATA_ACCESS_CONTROL; + + /* Adjust the data address. */ + data_address = data_address + block_size; + + /* Increment MPU table index. */ + mpu_table_index++; + } +} + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_inside_data_check Cortex-R4/MPU/IAR */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks if the specified object is inside shared */ +/* memory. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* obj_ptr Pointer to the object */ +/* obj_size Size of the object */ +/* */ +/* OUTPUT */ +/* */ +/* Whether the object is inside the shared memory region. */ +/* */ +/* CALLS */ +/* */ +/* N/A */ +/* */ +/* CALLED BY */ +/* */ +/* Module dispatch check functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) +{ + +UINT shared_memory_index; +UINT num_shared_memory_mpu_entries; +ALIGN_TYPE shared_memory_address_start; +ALIGN_TYPE shared_memory_address_end; + + /* Check if the object is inside the module data. */ + if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && + ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) + { + return(TX_TRUE); + } + + /* Check if the object is inside the shared memory. */ + num_shared_memory_mpu_entries = module_instance -> txm_module_instance_shared_memory_count; + for (shared_memory_index = 0; shared_memory_index < num_shared_memory_mpu_entries; shared_memory_index++) + { + + shared_memory_address_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address[shared_memory_index]; + shared_memory_address_end = shared_memory_address_start + module_instance -> txm_module_instance_shared_memory_length[shared_memory_index]; + + if ((obj_ptr >= (ALIGN_TYPE) shared_memory_address_start) && + ((obj_ptr + obj_size) <= (ALIGN_TYPE) shared_memory_address_end)) + { + return(TX_TRUE); + } + } + + return(TX_FALSE); +} + diff --git a/ports_module/cortex-r4/iar/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex-r4/iar/module_manager/src/txm_module_manager_thread_stack_build.s new file mode 100644 index 00000000..78b016c5 --- /dev/null +++ b/ports_module/cortex-r4/iar/module_manager/src/txm_module_manager_thread_stack_build.s @@ -0,0 +1,148 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +THUMB_MASK DEFINE 0x20 ; THUMB bit +USR_MODE DEFINE 0x10 ; USR mode +SYS_MODE DEFINE 0x1F ; SYS mode +CPSR_MASK DEFINE 0xBF ; Mask initial CPSR, IRQ ints enabled +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _txm_module_manager_thread_stack_build Cortex-R4/MPU/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _txm_module_manager_thread_stack_build + ARM +_txm_module_manager_thread_stack_build +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-R4 should look like the following after it is built: +; +; Stack Top: 1 Interrupt stack frame type +; CPSR Initial value for CPSR +; r0 Initial value for r0 +; r1 Initial value for r1 +; r2 Initial value for r2 +; r3 Initial value for r3 +; r4 Initial value for r4 +; r5 Initial value for r5 +; r6 Initial value for r6 +; r7 Initial value for r7 +; r8 Initial value for r8 +; r9 Initial value for r9 +; r10 Initial value for r10 +; r11 Initial value for r11 +; r12 Initial value for r12 +; lr Initial value for lr (r14) +; pc Initial value for pc (r15) +; 0 For stack backtracing +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #7 ; Ensure 8-byte alignment + SUB r2, r2, #76 ; Allocate space for the stack frame +; +; /* Actually build the stack frame. */ +; + MOV r3, #1 ; Build interrupt stack type + STR r3, [r2, #0] ; Store stack type + STR r0, [r2, #8] ; Store initial r0 (thread pointer) + LDR r3, [r0, #8] ; Pickup thread info pointer (it's in the stack pointer location right now) + STR r3, [r2, #12] ; Store initial r1 + LDR r3, [r3, #8] ; Pickup data base register + STR r3, [r2, #44] ; Store initial r9 + MOV r3, #0 ; Build initial register value + STR r3, [r2, #16] ; Store initial r2 + STR r3, [r2, #20] ; Store initial r3 + STR r3, [r2, #24] ; Store initial r4 + STR r3, [r2, #28] ; Store initial r5 + STR r3, [r2, #32] ; Store initial r6 + STR r3, [r2, #36] ; Store initial r7 + STR r3, [r2, #40] ; Store initial r8 + LDR r3, [r0, #12] ; Pickup stack starting address + STR r3, [r2, #48] ; Store initial r10 (sl) + MOV r3, #0 ; Build initial register value + STR r3, [r2, #52] ; Store initial r11 + STR r3, [r2, #56] ; Store initial r12 + STR r3, [r2, #60] ; Store initial lr + STR r1, [r2, #64] ; Store initial pc + STR r3, [r2, #68] ; 0 for back-trace + MRS r3, CPSR ; Pickup CPSR + BIC r3, r3, #CPSR_MASK ; Mask mode bits of CPSR + TST r1, #1 ; Test if THUMB bit set in initial PC + ORRNE r3, r3, #THUMB_MASK ; Set T bit if set + LDR r1, [r0, #156] ; Load tx_thread_module_user_mode + TST r1, #1 ; Test if the user mode flag is set + ORREQ r3, r3, #SYS_MODE ; Flag not set: Build CPSR, SYS mode, IRQ enabled + ORRNE r3, r3, #USR_MODE ; Flag set: Build CPSR, USR mode, IRQ enabled + STR r3, [r2, #4] ; Store initial CPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's control block + BX lr ; Return to caller +;} + END + diff --git a/ports_module/cortex-r4/iar/module_manager/src/txm_module_manager_user_mode_entry.s b/ports_module/cortex-r4/iar/module_manager/src/txm_module_manager_user_mode_entry.s new file mode 100644 index 00000000..a14ef099 --- /dev/null +++ b/ports_module/cortex-r4/iar/module_manager/src/txm_module_manager_user_mode_entry.s @@ -0,0 +1,90 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; + EXTERN _tx_thread_current_ptr + EXTERN _txm_module_manager_kernel_dispatch + + + RSEG .text:CODE:NOROOT(5) + ARM +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _txm_module_manager_user_mode_entry Cortex-R4/MPU/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function allows modules to enter kernel mode. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* SVC 1 Enter kernel mode */ +;/* SVC 2 Exit kernel mode */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Modules in user mode */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ + PUBLIC _txm_module_manager_user_mode_entry +_txm_module_manager_user_mode_entry: + + EXPORT _txm_system_mode_enter +_txm_system_mode_enter + SVC 1 ; Get out of user mode +_txm_module_priv + ; At this point, we are in system mode. + ; Save LR (and r3 for 8 byte aligned stack) and call the kernel dispatch function. + PUSH {r3, lr} + BL _txm_module_manager_kernel_dispatch + POP {r3, lr} + + EXPORT _txm_system_mode_exit +_txm_system_mode_exit + ; Trap to restore user mode while inside of ThreadX + SVC 2 + + BX lr ; Return to the caller + NOP + NOP +_txm_module_manager_user_mode_end + + END diff --git a/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/tx_initialize_low_level.s b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/tx_initialize_low_level.s index 00cdffa2..e8e4304d 100644 --- a/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/tx_initialize_low_level.s +++ b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/tx_initialize_low_level.s @@ -41,7 +41,7 @@ _tx_first_free_address: ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level SMP/ARC_HS/MetaWare */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -74,7 +74,7 @@ _tx_first_free_address: ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports_smp/arc_hs_smp/metaware/inc/tx_port.h b/ports_smp/arc_hs_smp/metaware/inc/tx_port.h index 4513cc1d..8b60f7e7 100644 --- a/ports_smp/arc_hs_smp/metaware/inc/tx_port.h +++ b/ports_smp/arc_hs_smp/metaware/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h SMP/ARC_HS/MetaWare */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -401,7 +401,7 @@ typedef struct TX_THREAD_SMP_PROTECT_STRUCT #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/ARC_HS/MetaWare Version 6.0.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/ARC_HS/MetaWare Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/arc_hs_smp/metaware/readme_threadx.txt b/ports_smp/arc_hs_smp/metaware/readme_threadx.txt index 512488da..60271d41 100644 --- a/ports_smp/arc_hs_smp/metaware/readme_threadx.txt +++ b/ports_smp/arc_hs_smp/metaware/readme_threadx.txt @@ -195,7 +195,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX 6.0.1 for ARC HS using MetaWare tools. +09-30-2020 Initial ThreadX 6.1 for ARC HS using MetaWare tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_context_restore.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_context_restore.s index e11426d0..4305420d 100644 --- a/ports_smp/arc_hs_smp/metaware/src/tx_thread_context_restore.s +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_context_restore.s @@ -37,7 +37,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore SMP/ARC_HS/MetaWare */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -69,7 +69,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_context_save.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_context_save.s index 20fcf44b..ab600bd3 100644 --- a/ports_smp/arc_hs_smp/metaware/src/tx_thread_context_save.s +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_context_save.s @@ -37,7 +37,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save SMP/ARC_HS/MetaWare */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -68,7 +68,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_interrupt_control.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_interrupt_control.s index a3602006..9a08ef74 100644 --- a/ports_smp/arc_hs_smp/metaware/src/tx_thread_interrupt_control.s +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_interrupt_control.s @@ -34,7 +34,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control SMP/ARC_HS/MetaWare */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -64,7 +64,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_schedule.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_schedule.s index f72b0106..e7c6fcf4 100644 --- a/ports_smp/arc_hs_smp/metaware/src/tx_thread_schedule.s +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_schedule.s @@ -59,7 +59,7 @@ _tx_thread_schedule_lock: ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule SMP/ARC_HS/MetaWare */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -92,7 +92,7 @@ _tx_thread_schedule_lock: ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_core_get.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_core_get.s index 7c100af2..fe8f4568 100644 --- a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_core_get.s +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_core_get.s @@ -36,7 +36,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_smp_core_get SMP/ARC_HS/MetaWare */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -65,7 +65,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ .global _tx_thread_smp_core_get diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_core_preempt.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_core_preempt.s index dde6dda2..cc184c11 100644 --- a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_core_preempt.s +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_core_preempt.s @@ -36,7 +36,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_smp_core_preempt SMP/ARC_HS/MetaWare */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -69,7 +69,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ .global _tx_thread_smp_core_preempt diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_current_state_get.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_current_state_get.s index bd886a8c..19f63b2e 100644 --- a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_current_state_get.s +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_current_state_get.s @@ -36,7 +36,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_smp_current_state_get SMP/ARC_HS/MetaWare */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -65,7 +65,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ .global _tx_thread_smp_current_state_get diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_current_thread_get.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_current_thread_get.s index 8dbcfe91..72b0533e 100644 --- a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_current_thread_get.s +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_current_thread_get.s @@ -36,7 +36,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_smp_current_thread_get SMP/ARC_HS/MetaWare */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -65,7 +65,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ .global _tx_thread_smp_current_thread_get diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_initialize_wait.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_initialize_wait.s index a12afad5..739dd62e 100644 --- a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_initialize_wait.s +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_initialize_wait.s @@ -36,7 +36,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_smp_initialize_wait SMP/ARC_HS/MetaWare */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -67,7 +67,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ .global _tx_thread_smp_initialize_wait diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_low_level_initialize.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_low_level_initialize.s index 6dec565b..d8ba19ca 100644 --- a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_low_level_initialize.s +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_low_level_initialize.s @@ -36,7 +36,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_smp_low_level_initialize SMP/ARC_HS/MetaWare */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -66,7 +66,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ .global _tx_thread_smp_low_level_initialize diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_protect.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_protect.s index ea9e174a..e661b3a4 100644 --- a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_protect.s +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_protect.s @@ -36,7 +36,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_smp_protect SMP/ARC_HS/MetaWare */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -67,7 +67,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ .global _tx_thread_smp_protect diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_time_get.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_time_get.s index 97e46261..a6d28a82 100644 --- a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_time_get.s +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_time_get.s @@ -36,7 +36,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_smp_time_get SMP/ARC_HS/MetaWare */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -66,7 +66,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ .global _tx_thread_smp_time_get diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_unprotect.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_unprotect.s index 8fb802b3..2788dcc0 100644 --- a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_unprotect.s +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_unprotect.s @@ -36,7 +36,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_smp_unprotect SMP/ARC_HS/MetaWare */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -68,7 +68,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ .global _tx_thread_smp_unprotect diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_stack_build.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_stack_build.s index 5c9f5d48..d065a584 100644 --- a/ports_smp/arc_hs_smp/metaware/src/tx_thread_stack_build.s +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_stack_build.s @@ -39,7 +39,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build SMP/ARC_HS/MetaWare */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_system_return.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_system_return.s index 176cd79f..e8d80a73 100644 --- a/ports_smp/arc_hs_smp/metaware/src/tx_thread_system_return.s +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_system_return.s @@ -35,7 +35,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return SMP/ARC_HS/MetaWare */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -67,7 +67,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_timer_interrupt.s b/ports_smp/arc_hs_smp/metaware/src/tx_timer_interrupt.s index 22111e76..8aca6e89 100644 --- a/ports_smp/arc_hs_smp/metaware/src/tx_timer_interrupt.s +++ b/ports_smp/arc_hs_smp/metaware/src/tx_timer_interrupt.s @@ -35,7 +35,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt SMP/ARC_HS/MetaWare */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) diff --git a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/.cproject b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/.cproject new file mode 100644 index 00000000..76fbcbed --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/.cproject @@ -0,0 +1,148 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/.project b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/.project new file mode 100644 index 00000000..a1b15572 --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/.project @@ -0,0 +1,26 @@ + + + sample_threadx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/.settings/language.settings.xml b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/.settings/language.settings.xml new file mode 100644 index 00000000..006b16bf --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/.settings/language.settings.xml @@ -0,0 +1,4594 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/GICv3.h b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/GICv3.h new file mode 100644 index 00000000..b04cd97b --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/GICv3.h @@ -0,0 +1,561 @@ +/* + * GICv3.h - data types and function prototypes for GICv3 utility routines + * + * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. + * Use, modification and redistribution of this file is subject to your + * possession of a valid DS-5 end user licence agreement and your compliance + * with all applicable terms and conditions of such licence agreement. + */ +#ifndef GICV3_h +#define GICV3_h + +#include + +/* + * extra flags for GICD enable + */ +typedef enum +{ + gicdctlr_EnableGrp0 = (1 << 0), + gicdctlr_EnableGrp1NS = (1 << 1), + gicdctlr_EnableGrp1A = (1 << 1), + gicdctlr_EnableGrp1S = (1 << 2), + gicdctlr_EnableAll = (1 << 2) | (1 << 1) | (1 << 0), + gicdctlr_ARE_S = (1 << 4), /* Enable Secure state affinity routing */ + gicdctlr_ARE_NS = (1 << 5), /* Enable Non-Secure state affinity routing */ + gicdctlr_DS = (1 << 6), /* Disable Security support */ + gicdctlr_E1NWF = (1 << 7) /* Enable "1-of-N" wakeup model */ +} GICDCTLRFlags_t; + +/* + * modes for SPI routing + */ +typedef enum +{ + gicdirouter_ModeSpecific = 0, + gicdirouter_ModeAny = (1 << 31) +} GICDIROUTERBits_t; + +typedef enum +{ + gicdicfgr_Level = 0, + gicdicfgr_Edge = (1 << 1) +} GICDICFGRBits_t; + +typedef enum +{ + gicigroupr_G0S = 0, + gicigroupr_G1NS = (1 << 0), + gicigroupr_G1S = (1 << 2) +} GICIGROUPRBits_t; + +typedef enum +{ + gicrwaker_ProcessorSleep = (1 << 1), + gicrwaker_ChildrenAsleep = (1 << 2) +} GICRWAKERBits_t; + +/**********************************************************************/ + +/* + * Utility macros & functions + */ +#define RANGE_LIMIT(x) ((sizeof(x) / sizeof((x)[0])) - 1) + +static inline uint64_t gicv3PackAffinity(uint32_t aff3, uint32_t aff2, + uint32_t aff1, uint32_t aff0) +{ + /* + * only need to cast aff3 to get type promotion for all affinities + */ + return ((((uint64_t)aff3 & 0xff) << 32) | + ((aff2 & 0xff) << 16) | + ((aff1 & 0xff) << 8) | aff0); +} + +/**********************************************************************/ + +/* + * GIC Distributor Function Prototypes + */ + +/* + * ConfigGICD - configure GIC Distributor prior to enabling it + * + * Inputs: + * + * control - control flags + * + * Returns: + * + * + * + * NOTE: + * + * ConfigGICD() will set an absolute flags value, whereas + * {En,Dis}ableGICD() will only {set,clear} the flag bits + * passed as a parameter + */ +void ConfigGICD(GICDCTLRFlags_t flags); + +/* + * EnableGICD - top-level enable for GIC Distributor + * + * Inputs: + * + * flags - new control flags to set + * + * Returns: + * + * + * + * NOTE: + * + * ConfigGICD() will set an absolute flags value, whereas + * {En,Dis}ableGICD() will only {set,clear} the flag bits + * passed as a parameter + */ +void EnableGICD(GICDCTLRFlags_t flags); + +/* + * DisableGICD - top-level disable for GIC Distributor + * + * Inputs + * + * flags - control flags to clear + * + * Returns + * + * + * + * NOTE: + * + * ConfigGICD() will set an absolute flags value, whereas + * {En,Dis}ableGICD() will only {set,clear} the flag bits + * passed as a parameter + */ +void DisableGICD(GICDCTLRFlags_t flags); + +/* + * SyncAREinGICD - synchronise GICD Address Routing Enable bits + * + * Inputs + * + * flags - absolute flag bits to set in GIC Distributor + * + * dosync - flag whether to wait for ARE bits to match passed + * flag field (dosync = true), or whether to set absolute + * flag bits (dosync = false) + * + * Returns + * + * + * + * NOTE: + * + * This function is used to resolve a race in an MP system whereby secondary + * CPUs cannot reliably program all Redistributor registers until the + * primary CPU has enabled Address Routing. The primary CPU will call this + * function with dosync = false, while the secondaries will call it with + * dosync = true. + */ +void SyncAREinGICD(GICDCTLRFlags_t flags, uint32_t dosync); + +/* + * EnableSPI - enable a specific shared peripheral interrupt + * + * Inputs: + * + * id - which interrupt to enable + * + * Returns: + * + * + */ +void EnableSPI(uint32_t id); + +/* + * DisableSPI - disable a specific shared peripheral interrupt + * + * Inputs: + * + * id - which interrupt to disable + * + * Returns: + * + * + */ +void DisableSPI(uint32_t id); + +/* + * SetSPIPriority - configure the priority for a shared peripheral interrupt + * + * Inputs: + * + * id - interrupt identifier + * + * priority - 8-bit priority to program (see note below) + * + * Returns: + * + * + * + * Note: + * + * The GICv3 architecture makes this function sensitive to the Security + * context in terms of what effect it has on the programmed priority: no + * attempt is made to adjust for the reduced priority range available + * when making Non-Secure accesses to the GIC + */ +void SetSPIPriority(uint32_t id, uint32_t priority); + +/* + * GetSPIPriority - determine the priority for a shared peripheral interrupt + * + * Inputs: + * + * id - interrupt identifier + * + * Returns: + * + * interrupt priority in the range 0 - 0xff + */ +uint32_t GetSPIPriority(uint32_t id); + +/* + * SetSPIRoute - specify interrupt routing when gicdctlr_ARE is enabled + * + * Inputs: + * + * id - interrupt identifier + * + * affinity - prepacked "dotted quad" affinity routing. NOTE: use the + * gicv3PackAffinity() helper routine to generate this input + * + * mode - select routing mode (specific affinity, or any recipient) + * + * Returns: + * + * + */ +void SetSPIRoute(uint32_t id, uint64_t affinity, GICDIROUTERBits_t mode); + +/* + * GetSPIRoute - read ARE-enabled interrupt routing information + * + * Inputs: + * + * id - interrupt identifier + * + * Returns: + * + * routing configuration + */ +uint64_t GetSPIRoute(uint32_t id); + +/* + * SetSPITarget - configure the set of processor targets for an interrupt + * + * Inputs + * + * id - interrupt identifier + * + * target - 8-bit target bitmap + * + * Returns + * + * + */ +void SetSPITarget(uint32_t id, uint32_t target); + +/* + * GetSPITarget - read the set of processor targets for an interrupt + * + * Inputs + * + * id - interrupt identifier + * + * Returns + * + * 8-bit target bitmap + */ +uint32_t GetSPITarget(uint32_t id); + +/* + * ConfigureSPI - setup an interrupt as edge- or level-triggered + * + * Inputs + * + * id - interrupt identifier + * + * config - desired configuration + * + * Returns + * + * + */ +void ConfigureSPI(uint32_t id, GICDICFGRBits_t config); + +/* + * SetSPIPending - mark an interrupt as pending + * + * Inputs + * + * id - interrupt identifier + * + * Returns + * + * + */ +void SetSPIPending(uint32_t id); + +/* + * ClearSPIPending - mark an interrupt as not pending + * + * Inputs + * + * id - interrupt identifier + * + * Returns + * + * + */ +void ClearSPIPending(uint32_t id); + +/* + * GetSPIPending - query whether an interrupt is pending + * + * Inputs + * + * id - interrupt identifier + * + * Returns + * + * pending status + */ +uint32_t GetSPIPending(uint32_t id); + +/* + * SetSPISecurity - mark a shared peripheral interrupt as + * security + * + * Inputs + * + * id - which interrupt to mark + * + * group - the group for the interrupt + * + * Returns + * + * + */ +void SetSPISecurity(uint32_t id, GICIGROUPRBits_t group); + +/* + * SetSPISecurityBlock - mark a block of 32 shared peripheral + * interrupts as security + * + * Inputs: + * + * block - which block to mark (e.g. 1 = Ints 32-63) + * + * group - the group for the interrupts + * + * Returns: + * + * + */ +void SetSPISecurityBlock(uint32_t block, GICIGROUPRBits_t group); + +/* + * SetSPISecurityAll - mark all shared peripheral interrupts + * as security + * + * Inputs: + * + * group - the group for the interrupts + * + * Returns: + * + * + */ +void SetSPISecurityAll(GICIGROUPRBits_t group); + +/**********************************************************************/ + +/* + * GIC Re-Distributor Function Prototypes + * + * The model for calling Redistributor functions is that, rather than + * identifying the target redistributor with every function call, the + * SelectRedistributor() function is used to identify which redistributor + * is to be used for all functions until a different redistributor is + * explicitly selected + */ + +/* + * WakeupGICR - wake up a Redistributor + * + * Inputs: + * + * gicr - which Redistributor to wakeup + * + * Returns: + * + * + */ +void WakeupGICR(uint32_t gicr); + +/* + * EnablePrivateInt - enable a private (SGI/PPI) interrupt + * + * Inputs: + * + * gicr - which Redistributor to program + * + * id - which interrupt to enable + * + * Returns: + * + * + */ +void EnablePrivateInt(uint32_t gicr, uint32_t id); + +/* + * DisablePrivateInt - disable a private (SGI/PPI) interrupt + * + * Inputs: + * + * gicr - which Redistributor to program + * + * id - which interrupt to disable + * + * Returns: + * + * + */ +void DisablePrivateInt(uint32_t gicr, uint32_t id); + +/* + * SetPrivateIntPriority - configure the priority for a private + * (SGI/PPI) interrupt + * + * Inputs: + * + * gicr - which Redistributor to program + * + * id - interrupt identifier + * + * priority - 8-bit priority to program (see note below) + * + * Returns: + * + * + * + * Note: + * + * The GICv3 architecture makes this function sensitive to the Security + * context in terms of what effect it has on the programmed priority: no + * attempt is made to adjust for the reduced priority range available + * when making Non-Secure accesses to the GIC + */ +void SetPrivateIntPriority(uint32_t gicr, uint32_t id, uint32_t priority); + +/* + * GetPrivateIntPriority - configure the priority for a private + * (SGI/PPI) interrupt + * + * Inputs: + * + * gicr - which Redistributor to program + * + * id - interrupt identifier + * + * Returns: + * + * Int priority + */ +uint32_t GetPrivateIntPriority(uint32_t gicr, uint32_t id); + +/* + * SetPrivateIntPending - mark a private (SGI/PPI) interrupt as pending + * + * Inputs + * + * gicr - which Redistributor to program + * + * id - interrupt identifier + * + * Returns + * + * + */ +void SetPrivateIntPending(uint32_t gicr, uint32_t id); + +/* + * ClearPrivateIntPending - mark a private (SGI/PPI) interrupt as not pending + * + * Inputs + * + * gicr - which Redistributor to program + * + * id - interrupt identifier + * + * Returns + * + * + */ +void ClearPrivateIntPending(uint32_t gicr, uint32_t id); + +/* + * GetPrivateIntPending - query whether a private (SGI/PPI) interrupt is pending + * + * Inputs + * + * gicr - which Redistributor to program + * + * id - interrupt identifier + * + * Returns + * + * pending status + */ +uint32_t GetPrivateIntPending(uint32_t gicr, uint32_t id); + +/* + * SetPrivateIntSecurity - mark a private (SGI/PPI) interrupt as + * security + * + * Inputs + * + * gicr - which Redistributor to program + * + * id - which interrupt to mark + * + * group - the group for the interrupt + * + * Returns + * + * + */ +void SetPrivateIntSecurity(uint32_t gicr, uint32_t id, GICIGROUPRBits_t group); + +/* + * SetPrivateIntSecurityBlock - mark all 32 private (SGI/PPI) + * interrupts as security + * + * Inputs: + * + * gicr - which Redistributor to program + * + * group - the group for the interrupt + * + * Returns: + * + * + */ +void SetPrivateIntSecurityBlock(uint32_t gicr, GICIGROUPRBits_t group); + +#endif /* ndef GICV3_h */ + +/* EOF GICv3.h */ diff --git a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/GICv3_gicc.h b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/GICv3_gicc.h new file mode 100644 index 00000000..bc2da074 --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/GICv3_gicc.h @@ -0,0 +1,249 @@ +/* + * GICv3_gicc.h - prototypes and inline functions for GICC system register operations + * + * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. + * Use, modification and redistribution of this file is subject to your + * possession of a valid DS-5 end user licence agreement and your compliance + * with all applicable terms and conditions of such licence agreement. + */ +#ifndef GICV3_gicc_h +#define GICV3_gicc_h + +/**********************************************************************/ + +typedef enum +{ + sreSRE = (1 << 0), + sreDFB = (1 << 1), + sreDIB = (1 << 2), + sreEnable = (1 << 3) +} ICC_SREBits_t; + +static inline void setICC_SRE_EL1(ICC_SREBits_t mode) +{ + asm("msr ICC_SRE_EL1, %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline uint64_t getICC_SRE_EL1(void) +{ + uint64_t retc; + + asm("mrs %0, ICC_SRE_EL1\n" : "=r" (retc)); + + return retc; +} + +static inline void setICC_SRE_EL2(ICC_SREBits_t mode) +{ + asm("msr ICC_SRE_EL2, %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline uint64_t getICC_SRE_EL2(void) +{ + uint64_t retc; + + asm("mrs %0, ICC_SRE_EL2\n" : "=r" (retc)); + + return retc; +} + +static inline void setICC_SRE_EL3(ICC_SREBits_t mode) +{ + asm("msr ICC_SRE_EL3, %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline uint64_t getICC_SRE_EL3(void) +{ + uint64_t retc; + + asm("mrs %0, ICC_SRE_EL3\n" : "=r" (retc)); + + return retc; +} + +/**********************************************************************/ + +typedef enum +{ + igrpEnable = (1 << 0), + igrpEnableGrp1NS = (1 << 0), + igrpEnableGrp1S = (1 << 2) +} ICC_IGRPBits_t; + +static inline void setICC_IGRPEN0_EL1(ICC_IGRPBits_t mode) +{ + asm("msr ICC_IGRPEN0_EL1, %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline void setICC_IGRPEN1_EL1(ICC_IGRPBits_t mode) +{ + asm("msr ICC_IGRPEN1_EL1, %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline void setICC_IGRPEN1_EL3(ICC_IGRPBits_t mode) +{ + asm("msr ICC_IGRPEN1_EL3, %0\n; isb" :: "r" ((uint64_t)mode)); +} + +/**********************************************************************/ + +typedef enum +{ + ctlrCBPR = (1 << 0), + ctlrCBPR_EL1S = (1 << 0), + ctlrEOImode = (1 << 1), + ctlrCBPR_EL1NS = (1 << 1), + ctlrEOImode_EL3 = (1 << 2), + ctlrEOImode_EL1S = (1 << 3), + ctlrEOImode_EL1NS = (1 << 4), + ctlrRM = (1 << 5), + ctlrPMHE = (1 << 6) +} ICC_CTLRBits_t; + +static inline void setICC_CTLR_EL1(ICC_CTLRBits_t mode) +{ + asm("msr ICC_CTLR_EL1, %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline uint64_t getICC_CTLR_EL1(void) +{ + uint64_t retc; + + asm("mrs %0, ICC_CTLR_EL1\n" : "=r" (retc)); + + return retc; +} + +static inline void setICC_CTLR_EL3(ICC_CTLRBits_t mode) +{ + asm("msr ICC_CTLR_EL3, %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline uint64_t getICC_CTLR_EL3(void) +{ + uint64_t retc; + + asm("mrs %0, ICC_CTLR_EL3\n" : "=r" (retc)); + + return retc; +} + +/**********************************************************************/ + +static inline uint64_t getICC_IAR0(void) +{ + uint64_t retc; + + asm("mrs %0, ICC_IAR0_EL1\n" : "=r" (retc)); + + return retc; +} + +static inline uint64_t getICC_IAR1(void) +{ + uint64_t retc; + + asm("mrs %0, ICC_IAR1_EL1\n" : "=r" (retc)); + + return retc; +} + +static inline void setICC_EOIR0(uint32_t interrupt) +{ + asm("msr ICC_EOIR0_EL1, %0\n; isb" :: "r" ((uint64_t)interrupt)); +} + +static inline void setICC_EOIR1(uint32_t interrupt) +{ + asm("msr ICC_EOIR1_EL1, %0\n; isb" :: "r" ((uint64_t)interrupt)); +} + +static inline void setICC_DIR(uint32_t interrupt) +{ + asm("msr ICC_DIR_EL1, %0\n; isb" :: "r" ((uint64_t)interrupt)); +} + +static inline void setICC_PMR(uint32_t priority) +{ + asm("msr ICC_PMR_EL1, %0\n; isb" :: "r" ((uint64_t)priority)); +} + +static inline void setICC_BPR0(uint32_t binarypoint) +{ + asm("msr ICC_BPR0_EL1, %0\n; isb" :: "r" ((uint64_t)binarypoint)); +} + +static inline void setICC_BPR1(uint32_t binarypoint) +{ + asm("msr ICC_BPR1_EL1, %0\n; isb" :: "r" ((uint64_t)binarypoint)); +} + +static inline uint64_t getICC_BPR0(void) +{ + uint64_t retc; + + asm("mrs %0, ICC_BPR0_EL1\n" : "=r" (retc)); + + return retc; +} + +static inline uint64_t getICC_BPR1(void) +{ + uint64_t retc; + + asm("mrs %0, ICC_BPR1_EL1\n" : "=r" (retc)); + + return retc; +} + +static inline uint64_t getICC_RPR(void) +{ + uint64_t retc; + + asm("mrs %0, ICC_RPR_EL1\n" : "=r" (retc)); + + return retc; +} + +/**********************************************************************/ + +typedef enum +{ + sgirIRMTarget = 0, + sgirIRMAll = (1ull << 40) +} ICC_SGIRBits_t; + +static inline void setICC_SGI0R(uint8_t aff3, uint8_t aff2, + uint8_t aff1, ICC_SGIRBits_t irm, + uint16_t targetlist, uint8_t intid) +{ + uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \ + ((uint64_t)aff1 << 16) | irm | targetlist | \ + ((uint64_t)(intid & 0x0f) << 24)); + + asm("msr ICC_SGI0R_EL1, %0\n; isb" :: "r" (packedbits)); +} + +static inline void setICC_SGI1R(uint8_t aff3, uint8_t aff2, + uint8_t aff1, ICC_SGIRBits_t irm, + uint16_t targetlist, uint8_t intid) +{ + uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \ + ((uint64_t)aff1 << 16) | irm | targetlist | \ + ((uint64_t)(intid & 0x0f) << 24)); + + asm("msr ICC_SGI1R_EL1, %0\n; isb" :: "r" (packedbits)); +} + +static inline void setICC_ASGI1R(uint8_t aff3, uint8_t aff2, + uint8_t aff1, ICC_SGIRBits_t irm, + uint16_t targetlist, uint8_t intid) +{ + uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \ + ((uint64_t)aff1 << 16) | irm | targetlist | \ + ((uint64_t)(intid & 0x0f) << 24)); + + asm("msr ICC_ASGI1R_EL1, %0\n; isb" :: "r" (packedbits)); +} + +#endif /* ndef GICV3_gicc_h */ diff --git a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/GICv3_gicd.c b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/GICv3_gicd.c new file mode 100644 index 00000000..e176b206 --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/GICv3_gicd.c @@ -0,0 +1,339 @@ +/* + * GICv3_gicd.c - generic driver code for GICv3 distributor + * + * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. + * Use, modification and redistribution of this file is subject to your + * possession of a valid DS-5 end user licence agreement and your compliance + * with all applicable terms and conditions of such licence agreement. + */ +#include + +#include "GICv3.h" + +typedef struct +{ + volatile uint32_t GICD_CTLR; // +0x0000 + const volatile uint32_t GICD_TYPER; // +0x0004 + const volatile uint32_t GICD_IIDR; // +0x0008 + + const volatile uint32_t padding0; // +0x000c + + volatile uint32_t GICD_STATUSR; // +0x0010 + + const volatile uint32_t padding1[3]; // +0x0014 + + volatile uint32_t IMP_DEF[8]; // +0x0020 + + volatile uint32_t GICD_SETSPI_NSR; // +0x0040 + const volatile uint32_t padding2; // +0x0044 + volatile uint32_t GICD_CLRSPI_NSR; // +0x0048 + const volatile uint32_t padding3; // +0x004c + volatile uint32_t GICD_SETSPI_SR; // +0x0050 + const volatile uint32_t padding4; // +0x0054 + volatile uint32_t GICD_CLRSPI_SR; // +0x0058 + + const volatile uint32_t padding5[3]; // +0x005c + + volatile uint32_t GICD_SEIR; // +0x0068 + + const volatile uint32_t padding6[5]; // +0x006c + + volatile uint32_t GICD_IGROUPR[32]; // +0x0080 + + volatile uint32_t GICD_ISENABLER[32]; // +0x0100 + volatile uint32_t GICD_ICENABLER[32]; // +0x0180 + volatile uint32_t GICD_ISPENDR[32]; // +0x0200 + volatile uint32_t GICD_ICPENDR[32]; // +0x0280 + volatile uint32_t GICD_ISACTIVER[32]; // +0x0300 + volatile uint32_t GICD_ICACTIVER[32]; // +0x0380 + + volatile uint8_t GICD_IPRIORITYR[1024]; // +0x0400 + volatile uint8_t GICD_ITARGETSR[1024]; // +0x0800 + volatile uint32_t GICD_ICFGR[64]; // +0x0c00 + volatile uint32_t GICD_IGRPMODR[32]; // +0x0d00 + const volatile uint32_t padding7[32]; // +0x0d80 + volatile uint32_t GICD_NSACR[64]; // +0x0e00 + + volatile uint32_t GICD_SGIR; // +0x0f00 + + const volatile uint32_t padding8[3]; // +0x0f04 + + volatile uint32_t GICD_CPENDSGIR[4]; // +0x0f10 + volatile uint32_t GICD_SPENDSGIR[4]; // +0x0f20 + + const volatile uint32_t padding9[52]; // +0x0f30 + const volatile uint32_t padding10[5120]; // +0x1000 + + volatile uint64_t GICD_IROUTER[1024]; // +0x6000 +} GICv3_distributor; + +/* + * use the scatter file to place GICD + */ +static GICv3_distributor __attribute__((section(".bss.distributor"))) gicd; + +void ConfigGICD(GICDCTLRFlags_t flags) +{ + gicd.GICD_CTLR = flags; +} + +void EnableGICD(GICDCTLRFlags_t flags) +{ + gicd.GICD_CTLR |= flags; +} + +void DisableGICD(GICDCTLRFlags_t flags) +{ + gicd.GICD_CTLR &= ~flags; +} + +void SyncAREinGICD(GICDCTLRFlags_t flags, uint32_t dosync) +{ + if (dosync) + { + const uint32_t tmask = gicdctlr_ARE_S | gicdctlr_ARE_NS; + const uint32_t tval = flags & tmask; + + while ((gicd.GICD_CTLR & tmask) != tval) + continue; + } + else + gicd.GICD_CTLR = flags; +} + +void EnableSPI(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_ISENABLER has 32 interrupts per register + */ + bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); + id &= 32 - 1; + + gicd.GICD_ISENABLER[bank] = 1 << id; + + return; +} + +void DisableSPI(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_ISENABLER has 32 interrupts per register + */ + bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); + id &= 32 - 1; + + gicd.GICD_ICENABLER[bank] = 1 << id; + + return; +} + +void SetSPIPriority(uint32_t id, uint32_t priority) +{ + uint32_t bank; + + /* + * GICD_IPRIORITYR has one byte-wide entry per interrupt + */ + bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR); + + gicd.GICD_IPRIORITYR[bank] = priority; +} + +uint32_t GetSPIPriority(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_IPRIORITYR has one byte-wide entry per interrupt + */ + bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR); + + return (uint32_t)(gicd.GICD_IPRIORITYR[bank]); +} + +void SetSPIRoute(uint32_t id, uint64_t affinity, GICDIROUTERBits_t mode) +{ + uint32_t bank; + + /* + * GICD_IROUTER has one doubleword-wide entry per interrupt + */ + bank = id & RANGE_LIMIT(gicd.GICD_IROUTER); + + gicd.GICD_IROUTER[bank] = affinity | (uint64_t)mode; +} + +uint64_t GetSPIRoute(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_IROUTER has one doubleword-wide entry per interrupt + */ + bank = id & RANGE_LIMIT(gicd.GICD_IROUTER); + + return gicd.GICD_IROUTER[bank]; +} + +void SetSPITarget(uint32_t id, uint32_t target) +{ + uint32_t bank; + + /* + * GICD_ITARGETSR has one byte-wide entry per interrupt + */ + bank = id & RANGE_LIMIT(gicd.GICD_ITARGETSR); + + gicd.GICD_ITARGETSR[bank] = target; +} + +uint32_t GetSPITarget(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_ITARGETSR has one byte-wide entry per interrupt + */ + /* + * GICD_ITARGETSR has 4 interrupts per register, i.e. 8-bits of + * target bitmap per register + */ + bank = id & RANGE_LIMIT(gicd.GICD_ITARGETSR); + + return (uint32_t)(gicd.GICD_ITARGETSR[bank]); +} + +void ConfigureSPI(uint32_t id, GICDICFGRBits_t config) +{ + uint32_t bank, tmp; + + /* + * GICD_ICFGR has 16 interrupts per register, i.e. 2-bits of + * configuration per register + */ + bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); + config &= 3; + + id = (id & 0xf) << 1; + + tmp = gicd.GICD_ICFGR[bank]; + tmp &= ~(3 << id); + tmp |= config << id; + gicd.GICD_ICFGR[bank] = tmp; +} + +void SetSPIPending(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_ISPENDR has 32 interrupts per register + */ + bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISPENDR); + id &= 0x1f; + + gicd.GICD_ISPENDR[bank] = 1 << id; +} + +void ClearSPIPending(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_ICPENDR has 32 interrupts per register + */ + bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICPENDR); + id &= 0x1f; + + gicd.GICD_ICPENDR[bank] = 1 << id; +} + +uint32_t GetSPIPending(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_ICPENDR has 32 interrupts per register + */ + bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICPENDR); + id &= 0x1f; + + return (gicd.GICD_ICPENDR[bank] >> id) & 1; +} + +void SetSPISecurity(uint32_t id, GICIGROUPRBits_t group) +{ + uint32_t bank, groupmod; + + /* + * GICD_IGROUPR has 32 interrupts per register + */ + bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_IGROUPR); + id &= 0x1f; + + /* + * the single group argument is split into two separate + * registers, so filter out and remove the (new to gicv3) + * group modifier bit + */ + groupmod = (group >> 1) & 1; + group &= 1; + + /* + * either set or clear the Group bit for the interrupt as appropriate + */ + if (group) + gicd.GICD_IGROUPR[bank] |= 1 << id; + else + gicd.GICD_IGROUPR[bank] &= ~(1 << id); + + /* + * now deal with groupmod + */ + if (groupmod) + gicd.GICD_IGRPMODR[bank] |= 1 << id; + else + gicd.GICD_IGRPMODR[bank] &= ~(1 << id); +} + +void SetSPISecurityBlock(uint32_t block, GICIGROUPRBits_t group) +{ + uint32_t groupmod; + const uint32_t nbits = (sizeof group * 8) - 1; + + /* + * GICD_IGROUPR has 32 interrupts per register + */ + block &= RANGE_LIMIT(gicd.GICD_IGROUPR); + + /* + * get each bit of group config duplicated over all 32-bits in a word + */ + groupmod = (uint32_t)(((int32_t)group << (nbits - 1)) >> 31); + group = (uint32_t)(((int32_t)group << nbits) >> 31); + + /* + * set the security state for this block of SPIs + */ + gicd.GICD_IGROUPR[block] = group; + gicd.GICD_IGRPMODR[block] = groupmod; +} + +void SetSPISecurityAll(GICIGROUPRBits_t group) +{ + uint32_t block; + + /* + * GICD_TYPER.ITLinesNumber gives (No. SPIS / 32) - 1, and we + * want to iterate over all blocks excluding 0 (which are the + * SGI/PPI interrupts, and not relevant here) + */ + for (block = (gicd.GICD_TYPER & ((1 << 5) - 1)); block > 0; --block) + SetSPISecurityBlock(block, group); +} + +/* EOF GICv3_gicd.c */ diff --git a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/GICv3_gicr.c b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/GICv3_gicr.c new file mode 100644 index 00000000..59ed616a --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/GICv3_gicr.c @@ -0,0 +1,279 @@ +/* + * GICv3_gicr.c - generic driver code for GICv3 redistributor + * + * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. + * Use, modification and redistribution of this file is subject to your + * possession of a valid DS-5 end user licence agreement and your compliance + * with all applicable terms and conditions of such licence agreement. + */ +#include "GICv3.h" + +/* + * physical LPI Redistributor register map + */ +typedef struct +{ + volatile uint32_t GICR_CTLR; // +0x0000 - RW - Redistributor Control Register + const volatile uint32_t GICR_IIDR; // +0x0004 - RO - Implementer Identification Register + const volatile uint32_t GICR_TYPER[2]; // +0x0008 - RO - Redistributor Type Register + volatile uint32_t GICR_STATUSR; // +0x0010 - RW - Error Reporting Status Register, optional + volatile uint32_t GICR_WAKER; // +0x0014 - RW - Redistributor Wake Register + const volatile uint32_t padding1[2]; // +0x0018 - RESERVED + volatile uint32_t IMPDEF1 ; // +0x0020 - ?? - IMPLEMENTATION DEFINED + const volatile uint32_t padding2[7]; // +0x0024 - RESERVED + volatile uint64_t GICR_SETLPIR; // +0x0040 - WO - Set LPI Pending Register + volatile uint64_t GICR_CLRLPIR; // +0x0048 - WO - Clear LPI Pending Register + const volatile uint32_t padding3[8]; // +0x0050 - RESERVED + volatile uint64_t GICR_PROPBASER; // +0x0070 - RW - Redistributor Properties Base Address Register + volatile uint64_t GICR_PENDBASER; // +0x0078 - RW - Redistributor LPI Pending Table Base Address Register + const volatile uint32_t padding4[8]; // +0x0080 - RESERVED + volatile uint64_t GICR_INVLPIR; // +0x00A0 - WO - Redistributor Invalidate LPI Register + const volatile uint32_t padding5[2]; // +0x00A8 - RESERVED + volatile uint64_t GICR_INVALLR; // +0x00B0 - WO - Redistributor Invalidate All Register + const volatile uint32_t padding6[2]; // +0x00B8 - RESERVED + volatile uint64_t GICR_SYNCR; // +0x00C0 - RO - Redistributor Synchronize Register + const volatile uint32_t padding7[2]; // +0x00C8 - RESERVED + const volatile uint32_t padding8[12]; // +0x00D0 - RESERVED + volatile uint64_t IMPDEF2; // +0x0100 - WO - IMPLEMENTATION DEFINED + const volatile uint32_t padding9[2]; // +0x0108 - RESERVED + volatile uint64_t IMPDEF3; // +0x0110 - WO - IMPLEMENTATION DEFINED + const volatile uint32_t padding10[2]; // +0x0118 - RESERVED +} GICv3_redistributor_RD; + +/* + * SGI and PPI Redistributor register map + */ +typedef struct +{ + const volatile uint32_t padding1[32]; // +0x0000 - RESERVED + volatile uint32_t GICR_IGROUPR0; // +0x0080 - RW - Interrupt Group Registers (Security Registers in GICv1) + const volatile uint32_t padding2[31]; // +0x0084 - RESERVED + volatile uint32_t GICR_ISENABLER; // +0x0100 - RW - Interrupt Set-Enable Registers + const volatile uint32_t padding3[31]; // +0x0104 - RESERVED + volatile uint32_t GICR_ICENABLER; // +0x0180 - RW - Interrupt Clear-Enable Registers + const volatile uint32_t padding4[31]; // +0x0184 - RESERVED + volatile uint32_t GICR_ISPENDR; // +0x0200 - RW - Interrupt Set-Pending Registers + const volatile uint32_t padding5[31]; // +0x0204 - RESERVED + volatile uint32_t GICR_ICPENDR; // +0x0280 - RW - Interrupt Clear-Pending Registers + const volatile uint32_t padding6[31]; // +0x0284 - RESERVED + volatile uint32_t GICR_ISACTIVER; // +0x0300 - RW - Interrupt Set-Active Register + const volatile uint32_t padding7[31]; // +0x0304 - RESERVED + volatile uint32_t GICR_ICACTIVER; // +0x0380 - RW - Interrupt Clear-Active Register + const volatile uint32_t padding8[31]; // +0x0184 - RESERVED + volatile uint8_t GICR_IPRIORITYR[32]; // +0x0400 - RW - Interrupt Priority Registers + const volatile uint32_t padding9[504]; // +0x0420 - RESERVED + volatile uint32_t GICR_ICnoFGR[2]; // +0x0C00 - RW - Interrupt Configuration Registers + const volatile uint32_t padding10[62]; // +0x0C08 - RESERVED + volatile uint32_t GICR_IGRPMODR0; // +0x0D00 - RW - ???? + const volatile uint32_t padding11[63]; // +0x0D04 - RESERVED + volatile uint32_t GICR_NSACR; // +0x0E00 - RW - Non-Secure Access Control Register +} GICv3_redistributor_SGI; + +/* + * We have a multiplicity of GIC Redistributors; on the GIC-AEM and + * GIC-500 they are arranged as one 128KB region per redistributor: one + * 64KB page of GICR LPI registers, and one 64KB page of GICR Private + * Int registers + */ +typedef struct +{ + union + { + GICv3_redistributor_RD RD_base; + uint8_t padding[64 * 1024]; + } RDblock; + + union + { + GICv3_redistributor_SGI SGI_base; + uint8_t padding[64 * 1024]; + } SGIblock; +} GICv3_GICR; + +/* + * use the scatter file to place GIC Redistributor base address + * + * although this code doesn't know how many Redistributor banks + * a particular system will have, we declare gicrbase as an array + * to avoid unwanted compiler optimisations when calculating the + * base of a particular Redistributor bank + */ +static const GICv3_GICR gicrbase[2] __attribute__((section (".bss.redistributor"))); + +/**********************************************************************/ + +/* + * utility functions to calculate base of a particular + * Redistributor bank + */ + +static inline GICv3_redistributor_RD *const getgicrRD(uint32_t gicr) +{ + GICv3_GICR *const arraybase = (GICv3_GICR *const)&gicrbase; + + return &((arraybase + gicr)->RDblock.RD_base); +} + +static inline GICv3_redistributor_SGI *const getgicrSGI(uint32_t gicr) +{ + GICv3_GICR *arraybase = (GICv3_GICR *)(&gicrbase); + + return &(arraybase[gicr].SGIblock.SGI_base); +} + +/**********************************************************************/ + +void WakeupGICR(uint32_t gicr) +{ + GICv3_redistributor_RD *const gicrRD = getgicrRD(gicr); + + /* + * step 1 - ensure GICR_WAKER.ProcessorSleep is off + */ + gicrRD->GICR_WAKER &= ~gicrwaker_ProcessorSleep; + + /* + * step 2 - wait for children asleep to be cleared + */ + while ((gicrRD->GICR_WAKER & gicrwaker_ChildrenAsleep) != 0) + continue; + + /* + * OK, GICR is go + */ + return; +} + +void EnablePrivateInt(uint32_t gicr, uint32_t id) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + id &= 0x1f; + + gicrSGI->GICR_ISENABLER = 1 << id; +} + +void DisablePrivateInt(uint32_t gicr, uint32_t id) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + id &= 0x1f; + + gicrSGI->GICR_ICENABLER = 1 << id; +} + +void SetPrivateIntPriority(uint32_t gicr, uint32_t id, uint32_t priority) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + /* + * GICD_IPRIORITYR has one byte-wide entry per interrupt + */ + id &= RANGE_LIMIT(gicrSGI->GICR_IPRIORITYR); + + gicrSGI->GICR_IPRIORITYR[id] = priority; +} + +uint32_t GetPrivateIntPriority(uint32_t gicr, uint32_t id) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + /* + * GICD_IPRIORITYR has one byte-wide entry per interrupt + */ + id &= RANGE_LIMIT(gicrSGI->GICR_IPRIORITYR); + + return (uint32_t)(gicrSGI->GICR_IPRIORITYR[id]); +} + +void SetPrivateIntPending(uint32_t gicr, uint32_t id) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + /* + * GICR_ISPENDR is one 32-bit register + */ + id &= 0x1f; + + gicrSGI->GICR_ISPENDR = 1 << id; +} + +void ClearPrivateIntPending(uint32_t gicr, uint32_t id) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + /* + * GICR_ICPENDR is one 32-bit register + */ + id &= 0x1f; + + gicrSGI->GICR_ICPENDR = 1 << id; +} + +uint32_t GetPrivateIntPending(uint32_t gicr, uint32_t id) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + /* + * GICR_ISPENDR is one 32-bit register + */ + id &= 0x1f; + + return (gicrSGI->GICR_ISPENDR >> id) & 0x01; +} + +void SetPrivateIntSecurity(uint32_t gicr, uint32_t id, GICIGROUPRBits_t group) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + uint32_t groupmod; + + /* + * GICR_IGROUPR0 is one 32-bit register + */ + id &= 0x1f; + + /* + * the single group argument is split into two separate + * registers, so filter out and remove the (new to gicv3) + * group modifier bit + */ + groupmod = (group >> 1) & 1; + group &= 1; + + /* + * either set or clear the Group bit for the interrupt as appropriate + */ + if (group) + gicrSGI->GICR_IGROUPR0 |= 1 << id; + else + gicrSGI->GICR_IGROUPR0 &= ~(1 << id); + + /* + * now deal with groupmod + */ + if (groupmod) + gicrSGI->GICR_IGRPMODR0 |= 1 << id; + else + gicrSGI->GICR_IGRPMODR0 &= ~(1 << id); +} + +void SetPrivateIntSecurityBlock(uint32_t gicr, GICIGROUPRBits_t group) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + const uint32_t nbits = (sizeof group * 8) - 1; + uint32_t groupmod; + + /* + * get each bit of group config duplicated over all 32-bits + */ + groupmod = (uint32_t)(((int32_t)group << (nbits - 1)) >> 31); + group = (uint32_t)(((int32_t)group << nbits) >> 31); + + /* + * set the security state for this block of SPIs + */ + gicrSGI->GICR_IGROUPR0 = group; + gicrSGI->GICR_IGRPMODR0 = groupmod; +} + +/* EOF GICv3_gicr.c */ diff --git a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/MP_Mutexes.S b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/MP_Mutexes.S new file mode 100644 index 00000000..d5dfd898 --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/MP_Mutexes.S @@ -0,0 +1,86 @@ +// +// Armv8-A AArch64 - Basic Mutex Example +// +// Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your +// possession of a valid DS-5 end user licence agreement and your compliance +// with all applicable terms and conditions of such licence agreement. +// + + + .text + .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + + + .global _mutex_initialize + .global _mutex_acquire + .global _mutex_release + +// +// These routines implement the mutex management functions required for running +// the Arm C library in a multi-threaded environment. +// +// They use a value of 0 to represent an unlocked mutex, and 1 for a locked mutex +// +// ********************************************************************** +// + + .type _mutex_initialize, "function" + .cfi_startproc +_mutex_initialize: + + // + // mark the mutex as unlocked + // + mov w1, #0 + str w1, [x0] + + // + // we are running multi-threaded, so set a non-zero return + // value (function prototype says use 1) + // + mov w0, #1 + ret + .cfi_endproc + + + .type _mutex_acquire, "function" + .cfi_startproc +_mutex_acquire: + + // + // send ourselves an event, so we don't stick on the wfe at the + // top of the loop + // + sevl + + // + // wait until the mutex is available + // +loop: + wfe + ldaxr w1, [x0] + cbnz w1, loop + + // + // mutex is (at least, it was) available - try to claim it + // + mov w1, #1 + stxr w2, w1, [x0] + cbnz w2, loop + + // + // OK, we have the mutex, our work is done here + // + ret + .cfi_endproc + + + .type _mutex_release, "function" + .cfi_startproc +_mutex_release: + + mov w1, #0 + stlr w1, [x0] + ret + .cfi_endproc diff --git a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/PPM_AEM.h b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/PPM_AEM.h new file mode 100644 index 00000000..da19e9b1 --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/PPM_AEM.h @@ -0,0 +1,66 @@ +// +// Private Peripheral Map for the v8 Architecture Envelope Model +// +// Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your +// possession of a valid DS-5 end user licence agreement and your compliance +// with all applicable terms and conditions of such licence agreement. +// + +#ifndef PPM_AEM_H +#define PPM_AEM_H + +// +// Distributor layout +// +#define GICD_CTLR 0x0000 +#define GICD_TYPER 0x0004 +#define GICD_IIDR 0x0008 +#define GICD_IGROUP 0x0080 +#define GICD_ISENABLE 0x0100 +#define GICD_ICENABLE 0x0180 +#define GICD_ISPEND 0x0200 +#define GICD_ICPEND 0x0280 +#define GICD_ISACTIVE 0x0300 +#define GICD_ICACTIVE 0x0380 +#define GICD_IPRIORITY 0x0400 +#define GICD_ITARGETS 0x0800 +#define GICD_ICFG 0x0c00 +#define GICD_PPISR 0x0d00 +#define GICD_SPISR 0x0d04 +#define GICD_SGIR 0x0f00 +#define GICD_CPENDSGI 0x0f10 +#define GICD_SPENDSGI 0x0f20 +#define GICD_PIDR4 0x0fd0 +#define GICD_PIDR5 0x0fd4 +#define GICD_PIDR6 0x0fd8 +#define GICD_PIDR7 0x0fdc +#define GICD_PIDR0 0x0fe0 +#define GICD_PIDR1 0x0fe4 +#define GICD_PIDR2 0x0fe8 +#define GICD_PIDR3 0x0fec +#define GICD_CIDR0 0x0ff0 +#define GICD_CIDR1 0x0ff4 +#define GICD_CIDR2 0x0ff8 +#define GICD_CIDR3 0x0ffc + +// +// CPU Interface layout +// +#define GICC_CTLR 0x0000 +#define GICC_PMR 0x0004 +#define GICC_BPR 0x0008 +#define GICC_IAR 0x000c +#define GICC_EOIR 0x0010 +#define GICC_RPR 0x0014 +#define GICC_HPPIR 0x0018 +#define GICC_ABPR 0x001c +#define GICC_AIAR 0x0020 +#define GICC_AEOIR 0x0024 +#define GICC_AHPPIR 0x0028 +#define GICC_APR0 0x00d0 +#define GICC_NSAPR0 0x00e0 +#define GICC_IIDR 0x00fc +#define GICC_DIR 0x1000 + +#endif // PPM_AEM_H diff --git a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.c new file mode 100644 index 00000000..eea35faa --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.c @@ -0,0 +1,389 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" +#include + +extern void init_timer(void); /* in timer_interrupts.c */ + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 0x20000 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define a memory area to create a byte pool in. */ + +UCHAR memory_area[DEMO_BYTE_POOL_SIZE] __attribute__((aligned (8))); + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_TIMER timer_0; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +#ifdef TX_ENABLE_EVENT_TRACE + +UCHAR event_buffer[65536]; + +#endif + + +int main(void) +{ + + /* Initialize timer. */ + init_timer(); + + /* Enter ThreadX. */ + tx_kernel_enter(); + + return 0; +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + +#ifdef TX_ENABLE_EVENT_TRACE + + tx_trace_enable(event_buffer, sizeof(event_buffer), 32); +#endif + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEMO_BYTE_POOL_SIZE); + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + diff --git a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.launch b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.launch new file mode 100644 index 00000000..c5a3a4b2 --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.launch @@ -0,0 +1,405 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.sct b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.sct new file mode 100644 index 00000000..1288a328 --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.sct @@ -0,0 +1,262 @@ +;******************************************************** +; Scatter file for Armv8-A Startup code on FVP Base model +; Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. +; Use, modification and redistribution of this file is subject to your +; possession of a valid DS-5 end user licence agreement and your compliance +; with all applicable terms and conditions of such licence agreement. +;******************************************************** + +LOAD 0x80000000 +{ + EXEC +0 + { + startup.o (StartUp, +FIRST) + * (+RO, +RW, +ZI) + + } + ;XTABLES +0 ALIGN 0x1000 + ;{ + ; xtables.o (*) + ;} + + SYS_STACK +0 ALIGN 8 EMPTY 0x1000 + { + } + + ; + ; Separate heap - import symbol __use_two_region_memory + ; in source code for this to work correctly + ; + ARM_LIB_HEAP +0 ALIGN 64 EMPTY 0xA0000 {} + + ; + ; App stacks for all CPUs + ; All stacks and heap are aligned to a cache-line boundary + ; + ARM_LIB_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} + + ; + ; Handler stacks for all CPUs + ; All stacks and heap are aligned to a cache-line boundary + ; + HANDLER_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} + + ; + ; Stacks for EL3 + ; + EL3_STACKS +0 ALIGN 64 EMPTY 4 * 0x1000 {} + ; + ; Strictly speaking, the L1 tables don't need to + ; be so strongly aligned, but no matter + ; + TTB0_L1 +0 ALIGN 4096 EMPTY 0x1000 {} + + ; + ; Various sets of L2 tables + ; + ; Alignment is 4KB, since the code uses a 4K page + ; granularity - larger granularities would require + ; correspondingly stricter alignment + ; + TTB0_L2_RAM +0 ALIGN 4096 EMPTY 0x1000 {} + + TTB0_L2_PRIVATE +0 ALIGN 4096 EMPTY 0x1000 {} + + TTB0_L2_PERIPH +0 ALIGN 4096 EMPTY 0x1000 {} + + ; + ; The startup code uses the end of this region to calculate + ; the top of memory - don't place any RAM regions after it + ; + TOP_OF_RAM +0 EMPTY 4 {} + + ; + ; CS3 Peripherals is a 64MB region from 0x1c000000 + ; that includes the following: + ; System Registers at 0x1C010000 + ; UART0 (PL011) at 0x1C090000 + ; Color LCD Controller (PL111) at 0x1C1F0000 + ; plus a number of others. + ; CS3_PERIPHERALS is used by the startup code for page-table generation + ; This region is not truly empty, but we have no + ; predefined objects that live within it + ; + CS3_PERIPHERALS 0x1c000000 EMPTY 0x90000 {} + + ; + ; Place the UART peripheral registers data structure + ; This is only really needed if USE_SERIAL_PORT is defined, but + ; the linker will remove unused sections if not needed +; PL011 0x1c090000 UNINIT 0x1000 +; { +; uart.o (+ZI) +; } + ; Note that some other CS3_PERIPHERALS follow this + + ; + ; GICv3 distributor + ; + GICD 0x2f000000 UNINIT 0x8000 + { + GICv3_gicd.o (.bss.distributor) + } + + ; + ; GICv3 redistributors + ; 128KB for each redistributor in the system + ; + GICR 0x2f100000 UNINIT 0x80000 + { + GICv3_gicr.o (.bss.redistributor) + } +} + + + + + +; Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; Redistributions of source code must retain the above copyright notice, this +; list of conditions and the following disclaimer. +; +; Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; +; Neither the name of ARM nor the names of its contributors may be used +; to endorse or promote products derived from this software without specific +; prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. + +;RO AlignExpr(0x80000000, 0x1000) +;{ +; C_SYNCH_SP0 +0 ALIGN 0x80 +; { +; vectors.o (_c_synch_sp0) +; } +; C_IRQ_SP0 +0 ALIGN 0x80 +; { +; vectors.o (_c_irq_sp0) +; } +; C_FIQ_SP0 +0 ALIGN 0x80 +; { +; vectors.o (_c_fiq_sp0) +; } +; C_SERROR_SP0 +0 ALIGN 0x80 +; { +; vectors.o (_c_serror_sp0) +; } +; +; C_SYNCH_SPX +0 ALIGN 0x80 +; { +; vectors.o (_c_synch_spx) +; } +; C_IRQ_SPX +0 ALIGN 0x80 +; { +; vectors.o (_c_irq_spx) +; } +; C_FIQ_SPX +0 ALIGN 0x80 +; { +; vectors.o (_c_fiq_spx) +; } +; C_SERROR_SPX +0 ALIGN 0x80 +; { +; vectors.o (_c_serror_spx) +; } +; +; L64_SYNCH +0 ALIGN 0x80 +; { +; vectors.o (_l64_synch) +; } +; L64_IRQ +0 ALIGN 0x80 +; { +; vectors.o (_l64_irq) +; } +; L64_FIQ +0 ALIGN 0x80 +; { +; vectors.o (_l64_fiq) +; } +; L64_SERROR +0 ALIGN 0x80 +; { +; vectors.o (_l64_serror) +; } +; +; L32_SYNCH +0 ALIGN 0x80 +; { +; vectors.o (_l32_synch) +; } +; L32_IRQ +0 ALIGN 0x80 +; { +; vectors.o (_l32_irq) +; } +; L32_FIQ +0 ALIGN 0x80 +; { +; vectors.o (_l32_fiq) +; } +; L32_SERROR +0 ALIGN 0x80 +; { +; vectors.o (_l32_serror) +; } +; +; ROSEC +0 ALIGN 8 +; { +; *( +RO ) +; } +; +; XTABLES +0 ALIGN 0x1000 +; { +; xtables.o (*) +; } +;} +; +;RW AlignExpr(ImageLimit(XTABLES), 0x1000) +;{ +; RWSEC +0 +; { +; *( +RW ) +; } +; +; ZISEC +0 +; { +; *( +ZI ) +; } +; +; SYS_STACK +0 ALIGN 8 EMPTY 0x1000 +; { +; } +; +; ; 512 MiB heap +; HEAP +0 ALIGN 8 EMPTY 0x10000000 +; { +; } +; +; ; Free Memory section +; FREE_MEMORY +0 ALIGN 8 EMPTY 0x10000000 +; { +; } +; +; ; Per-CPU 128 MiB task stacks +; TASK_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) +; { +; } +; +; ; Per-CPU 128 MiB handler stacks +; HANDLER_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) +; { +; } +;} diff --git a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/sp804_timer.c b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/sp804_timer.c new file mode 100644 index 00000000..4a454f16 --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/sp804_timer.c @@ -0,0 +1,122 @@ +// ------------------------------------------------------------ +// SP804 Dual Timer +// +// Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your +// possession of a valid DS-5 end user licence agreement and your compliance +// with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#include "sp804_timer.h" + +#define TIMER_SP804_CTRL_TIMEREN (1 << 7) +#define TIMER_SP804_CTRL_TIMERMODE (1 << 6) // Bit 6: +#define TIMER_SP804_CTRL_INTENABLE (1 << 5) +#define TIMER_SP804_CTRL_TIMERSIZE (1 << 1) // Bit 1: 0=16-bit, 1=32-bit +#define TIMER_SP804_CTRL_ONESHOT (1 << 0) // Bit 0: 0=wrapping, 1=one-shot + +#define TIMER_SP804_CTRL_PRESCALE_1 (0 << 2) // clk/1 +#define TIMER_SP804_CTRL_PRESCALE_4 (1 << 2) // clk/4 +#define TIMER_SP804_CTRL_PRESCALE_8 (2 << 2) // clk/8 + +struct sp804_timer +{ + volatile uint32_t Time1Load; // +0x00 + const volatile uint32_t Time1Value; // +0x04 - RO + volatile uint32_t Timer1Control; // +0x08 + volatile uint32_t Timer1IntClr; // +0x0C - WO + const volatile uint32_t Timer1RIS; // +0x10 - RO + const volatile uint32_t Timer1MIS; // +0x14 - RO + volatile uint32_t Timer1BGLoad; // +0x18 + + volatile uint32_t Time2Load; // +0x20 + volatile uint32_t Time2Value; // +0x24 + volatile uint8_t Timer2Control; // +0x28 + volatile uint32_t Timer2IntClr; // +0x2C - WO + const volatile uint32_t Timer2RIS; // +0x30 - RO + const volatile uint32_t Timer2MIS; // +0x34 - RO + volatile uint32_t Timer2BGLoad; // +0x38 + + // Not including ID registers + +}; + +// Instance of the dual timer, will be placed using the scatter file +struct sp804_timer* dual_timer; + + +// Set base address of timer +// address - virtual address of SP804 timer +void setTimerBaseAddress(uint64_t address) +{ + dual_timer = (struct sp804_timer*)address; + return; +} + + +// Sets up the private timer +// load_value - Initial value of timer +// auto_reload - Periodic (SP804_AUTORELOAD) or one shot (SP804_SINGLESHOT) +// interrupt - Whether to generate an interrupt +void initTimer(uint32_t load_value, uint32_t auto_reload, uint32_t interrupt) +{ + uint32_t tmp = 0; + + dual_timer->Time1Load = load_value; + + // Fixed setting: 32-bit, no prescaling + tmp = TIMER_SP804_CTRL_TIMERSIZE | TIMER_SP804_CTRL_PRESCALE_1 | TIMER_SP804_CTRL_TIMERMODE; + + // Settings from parameters: interrupt generation & reload + tmp = tmp | interrupt | auto_reload; + + // Write control register + dual_timer->Timer1Control = tmp; + + return; +} + + +// Starts the timer +void startTimer(void) +{ + uint32_t tmp; + + tmp = dual_timer->Timer1Control; + tmp = tmp | TIMER_SP804_CTRL_TIMEREN; // Set TimerEn (bit 7) + dual_timer->Timer1Control = tmp; + + return; +} + + +// Stops the timer +void stopTimer(void) +{ + uint32_t tmp; + + tmp = dual_timer->Timer1Control; + tmp = tmp & ~TIMER_SP804_CTRL_TIMEREN; // Clear TimerEn (bit 7) + dual_timer->Timer1Control = tmp; + + return; +} + + +// Returns the current timer count +uint32_t getTimerCount(void) +{ + return dual_timer->Time1Value; +} + + +void clearTimerIrq(void) +{ + // A write to this register, of any value, clears the interrupt + dual_timer->Timer1IntClr = 1; +} + + +// ------------------------------------------------------------ +// End of sp804_timer.c +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/sp804_timer.h b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/sp804_timer.h new file mode 100644 index 00000000..d4c6d9e2 --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/sp804_timer.h @@ -0,0 +1,53 @@ +// ------------------------------------------------------------ +// SP804 Dual Timer +// Header Filer +// +// Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your +// possession of a valid DS-5 end user licence agreement and your compliance +// with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#ifndef _SP804_TIMER_ +#define _SP804_TIMER_ + +#include + +// Set base address of timer +// address - virtual address of SP804 timer +void setTimerBaseAddress(uint64_t address); + + +// Sets up the private timer +// load_value - Initial value of timer +// auto_reload - Periodic (SP804_AUTORELOAD) or one shot (SP804_SINGLESHOT) +// interrupt - Whether to generate an interrupt + +#define SP804_AUTORELOAD (0) +#define SP804_SINGLESHOT (1) +#define SP804_GENERATE_IRQ (1 << 5) +#define SP804_NO_IRQ (0) + +void initTimer(uint32_t load_value, uint32_t auto_reload, uint32_t interrupt); + + +// Starts the timer +void startTimer(void); + + +// Stops the timer +void stopTimer(void); + + +// Returns the current timer count +uint32_t getTimerCount(void); + + +// Clears the timer interrupt +void clearTimerIrq(void); + +#endif + +// ------------------------------------------------------------ +// End of sp804_timer.h +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/startup.S b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/startup.S new file mode 100644 index 00000000..eea65315 --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/startup.S @@ -0,0 +1,803 @@ +// ------------------------------------------------------------ +// Armv8-A MPCore EL3 AArch64 Startup Code +// +// Basic Vectors, MMU, caches and GICv3 initialization +// +// Exits in EL1 AArch64 +// +// Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your +// possession of a valid DS-5 end user licence agreement and your compliance +// with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#include "v8_mmu.h" +#include "v8_system.h" + + + .section StartUp, "ax" + .balign 4 + .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + + + .global el1_vectors + .global el2_vectors + .global el3_vectors + + .global InvalidateUDCaches + .global ZeroBlock + + .global SetPrivateIntSecurityBlock + .global SetSPISecurityAll + .global SetPrivateIntPriority + + .global WakeupGICR + .global SyncAREinGICD + .global EnableGICD + .global EnablePrivateInt + .global GetPrivateIntPending + .global ClearPrivateIntPending + + .global __main + + .global Image$$EXEC$$RO$$Base + .global Image$$TTB0_L1$$ZI$$Base + .global Image$$TTB0_L2_RAM$$ZI$$Base + .global Image$$TTB0_L2_PERIPH$$ZI$$Base + .global Image$$TOP_OF_RAM$$ZI$$Base + .global Image$$GICD$$ZI$$Base + .global Image$$ARM_LIB_STACK$$ZI$$Limit + .global Image$$EL3_STACKS$$ZI$$Limit + .global Image$$CS3_PERIPHERALS$$ZI$$Base + // use separate stack and heap, as anticipated by scatter.scat + .global __use_two_region_memory + +is_mmu_ready: +.word 0 + + +// ------------------------------------------------------------ + + .global start64 + .type start64, "function" +start64: + + // + // program the VBARs + // + ldr x1, =el1_vectors + msr VBAR_EL1, x1 + + ldr x1, =el2_vectors + msr VBAR_EL2, x1 + + ldr x1, =el3_vectors + msr VBAR_EL3, x1 + + + // GIC-500 comes out of reset in GICv2 compatibility mode - first set + // system register enables for all relevant exception levels, and + // select GICv3 operating mode + // + msr SCR_EL3, xzr // Ensure NS bit is initially clear, so secure copy of ICC_SRE_EL1 can be configured + isb + + mov x0, #15 + msr ICC_SRE_EL3, x0 + isb + msr ICC_SRE_EL1, x0 // Secure copy of ICC_SRE_EL1 + + // + // set lower exception levels as non-secure, with no access + // back to EL2 or EL3, and are AArch64 capable + // + mov x3, #(SCR_EL3_RW | \ + SCR_EL3_SMD | \ + SCR_EL3_NS) // Set NS bit, to access Non-secure registers + msr SCR_EL3, x3 + isb + + mov x0, #15 + msr ICC_SRE_EL2, x0 + isb + msr ICC_SRE_EL1, x0 // Non-secure copy of ICC_SRE_EL1 + + + // + // no traps or VM modifications from the Hypervisor, EL1 is AArch64 + // + mov x2, #HCR_EL2_RW + msr HCR_EL2, x2 + + // + // VMID is still significant, even when virtualisation is not + // being used, so ensure VTTBR_EL2 is properly initialised + // + msr VTTBR_EL2, xzr + + // + // VMPIDR_EL2 holds the value of the Virtualization Multiprocessor ID. This is the value returned by Non-secure EL1 reads of MPIDR_EL1. + // VPIDR_EL2 holds the value of the Virtualization Processor ID. This is the value returned by Non-secure EL1 reads of MIDR_EL1. + // Both of these registers are architecturally UNKNOWN at reset, and so they must be set to the correct value + // (even if EL2/virtualization is not being used), otherwise non-secure EL1 reads of MPIDR_EL1/MIDR_EL1 will return garbage values. + // This guarantees that any future reads of MPIDR_EL1 and MIDR_EL1 from Non-secure EL1 will return the correct value. + // + mrs x0, MPIDR_EL1 + msr VMPIDR_EL2, x0 + mrs x0, MIDR_EL1 + msr VPIDR_EL2, x0 + + // extract the core number from MPIDR_EL1 and store it in + // x19 (defined by the AAPCS as callee-saved), so we can re-use + // the number later + // + bl GetCPUID + mov x19, x0 + + // + // neither EL3 nor EL2 trap floating point or accesses to CPACR + // + msr CPTR_EL3, xzr + msr CPTR_EL2, xzr + + // + // SCTLR_ELx may come out of reset with UNKNOWN values so we will + // set the fields to 0 except, possibly, the endianess field(s). + // Note that setting SCTLR_EL2 or the EL0 related fields of SCTLR_EL1 + // is not strictly needed, since we're never in EL2 or EL0 + // +#ifdef __ARM_BIG_ENDIAN + mov x0, #(SCTLR_ELx_EE | SCTLR_EL1_E0E) +#else + mov x0, #0 +#endif + msr SCTLR_EL3, x0 + msr SCTLR_EL2, x0 + msr SCTLR_EL1, x0 + +#ifdef CORTEXA + // + // Configure ACTLR_EL[23] + // ---------------------- + // + // These bits are IMPLEMENTATION DEFINED, so are different for + // different processors + // + // For Cortex-A57, the controls we set are: + // + // Enable lower level access to CPUACTLR_EL1 + // Enable lower level access to CPUECTLR_EL1 + // Enable lower level access to L2CTLR_EL1 + // Enable lower level access to L2ECTLR_EL1 + // Enable lower level access to L2ACTLR_EL1 + // + mov x0, #((1 << 0) | \ + (1 << 1) | \ + (1 << 4) | \ + (1 << 5) | \ + (1 << 6)) + + msr ACTLR_EL3, x0 + msr ACTLR_EL2, x0 + + // + // configure CPUECTLR_EL1 + // + // These bits are IMP DEF, so need to different for different + // processors + // + // SMPEN - bit 6 - Enables the processor to receive cache + // and TLB maintenance operations + // + // Note: For Cortex-A57/53 SMPEN should be set before enabling + // the caches and MMU, or performing any cache and TLB + // maintenance operations. + // + // This register has a defined reset value, so we use a + // read-modify-write sequence to set SMPEN + // + mrs x0, S3_1_c15_c2_1 // Read EL1 CPU Extended Control Register + orr x0, x0, #(1 << 6) // Set the SMPEN bit + msr S3_1_c15_c2_1, x0 // Write EL1 CPU Extended Control Register + + isb +#endif + + // + // That's the last of the control settings for now + // + // Note: no ISB after all these changes, as registers won't be + // accessed until after an exception return, which is itself a + // context synchronisation event + // + + // + // Setup some EL3 stack space, ready for calling some subroutines, below. + // + // Stack space allocation is CPU-specific, so use CPU + // number already held in x19 + // + // 2^12 bytes per CPU for the EL3 stacks + // + ldr x0, =Image$$EL3_STACKS$$ZI$$Limit + sub x0, x0, x19, lsl #12 + mov sp, x0 + + // + // we need to configure the GIC while still in secure mode, specifically + // all PPIs and SPIs have to be programmed as Group1 interrupts + // + + // + // Before the GIC can be reliably programmed, we need to + // enable Affinity Routing, as this affects where the configuration + // registers are (with Affinity Routing enabled, some registers are + // in the Redistributor, whereas those same registers are in the + // Distributor with Affinity Routing disabled (i.e. when in GICv2 + // compatibility mode). + // + mov x0, #(1 << 4) | (1 << 5) // gicdctlr_ARE_S | gicdctlr_ARE_NS + mov x1, x19 + bl SyncAREinGICD + + // + // The Redistributor comes out of reset assuming the processor is + // asleep - correct that assumption + // + mov w0, w19 + bl WakeupGICR + + // + // Now we're ready to set security and other initialisations + // + // This is a per-CPU configuration for these interrupts + // + // for the first cluster, CPU number is the redistributor index + // + mov w0, w19 + mov w1, #1 // gicigroupr_G1NS + bl SetPrivateIntSecurityBlock + + // + // While we're in the Secure World, set the priority mask low enough + // for it to be writable in the Non-Secure World + // + //mov x0, #16 << 3 // 5 bits of priority in the Secure world + mov x0, #0xFF // for Non-Secure interrupts + msr ICC_PMR_EL1, x0 + + // + // there's more GIC setup to do, but only for the primary CPU + // + cbnz x19, drop_to_el1 + + // + // There's more to do to the GIC - call the utility routine to set + // all SPIs to Group1 + // + mov w0, #1 // gicigroupr_G1NS + bl SetSPISecurityAll + + // + // Set up EL1 entry point and "dummy" exception return information, + // then perform exception return to enter EL1 + // + .global drop_to_el1 +drop_to_el1: + adr x1, el1_entry_aarch64 + msr ELR_EL3, x1 + mov x1, #(AARCH64_SPSR_EL1h | \ + AARCH64_SPSR_F | \ + AARCH64_SPSR_I | \ + AARCH64_SPSR_A) + msr SPSR_EL3, x1 + eret + + + +// ------------------------------------------------------------ +// EL1 - Common start-up code +// ------------------------------------------------------------ + + .global el1_entry_aarch64 + .type el1_entry_aarch64, "function" +el1_entry_aarch64: + + // + // Now we're in EL1, setup the application stack + // the scatter file allocates 2^14 bytes per app stack + // + ldr x0, =Image$$HANDLER_STACK$$ZI$$Limit + sub x0, x0, x19, lsl #14 + mov sp, x0 + MSR SPSel, #0 + ISB + ldr x0, =Image$$ARM_LIB_STACK$$ZI$$Limit + sub x0, x0, x19, lsl #14 + mov sp, x0 + + // + // Enable floating point + // + mov x0, #CPACR_EL1_FPEN + msr CPACR_EL1, x0 + + // + // Invalidate caches and TLBs for all stage 1 + // translations used at EL1 + // + // Cortex-A processors automatically invalidate their caches on reset + // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins). + // It is therefore not necessary for software to invalidate the caches + // on startup, however, this is done here in case of a warm reset. + bl InvalidateUDCaches + tlbi VMALLE1 + + + // + // Set TTBR0 Base address + // + // The CPUs share one set of translation tables that are + // generated by CPU0 at run-time + // + // TTBR1_EL1 is not used in this example + // + ldr x1, =Image$$TTB0_L1$$ZI$$Base + msr TTBR0_EL1, x1 + + + // + // Set up memory attributes + // + // These equate to: + // + // 0 -> 0b01000100 = 0x00000044 = Normal, Inner/Outer Non-Cacheable + // 1 -> 0b11111111 = 0x0000ff00 = Normal, Inner/Outer WriteBack Read/Write Allocate + // 2 -> 0b00000100 = 0x00040000 = Device-nGnRE + // + mov x1, #0xff44 + movk x1, #4, LSL #16 // equiv to: movk x1, #0x0000000000040000 + msr MAIR_EL1, x1 + + + // + // Set up TCR_EL1 + // + // We're using only TTBR0 (EPD1 = 1), and the page table entries: + // - are using an 8-bit ASID from TTBR0 + // - have a 4K granularity (TG0 = 0b00) + // - are outer-shareable (SH0 = 0b10) + // - are using Inner & Outer WBWA Normal memory ([IO]RGN0 = 0b01) + // - map + // + 32 bits of VA space (T0SZ = 0x20) + // + into a 32-bit PA space (IPS = 0b000) + // + // 36 32 28 24 20 16 12 8 4 0 + // -----+----+----+----+----+----+----+----+----+----+ + // | | |OOII| | | |OOII| | | + // TT | | |RRRR|E T | T| |RRRR|E T | T| + // BB | I I|TTSS|GGGG|P 1 | 1|TTSS|GGGG|P 0 | 0| + // IIA| P P|GGHH|NNNN|DAS | S|GGHH|NNNN|D S | S| + // 10S| S-S|1111|1111|11Z-|---Z|0000|0000|0 Z-|---Z| + // + // 000 0000 0000 0000 1000 0000 0010 0101 0010 0000 + // + // 0x 8 0 2 5 2 0 + // + // Note: the ISB is needed to ensure the changes to system + // context are before the write of SCTLR_EL1.M to enable + // the MMU. It is likely on a "real" implementation that + // this setup would work without an ISB, due to the + // amount of code that gets executed before enabling the + // MMU, but that would not be architecturally correct. + // + ldr x1, =0x0000000000802520 + msr TCR_EL1, x1 + isb + + // + // the primary CPU is going to use SGI 15 as a wakeup event + // to let us know when it is OK to proceed, so prepare for + // receiving that interrupt + // + // NS interrupt priorities run from 0 to 15, with 15 being + // too low a priority to ever raise an interrupt, so let's + // use 14 + // + mov w0, w19 + mov w1, #0 + mov w2, #14 << 4 // we're in NS world, so 4 bits of priority, + // 8-bit field, - 4 = 4-bit shift + bl SetPrivateIntPriority + + mov w0, w19 + mov w1, #0 + bl EnablePrivateInt + + // + // set priority mask as low as possible; although,being in the + // NS World, we can't set bit[7] of the priority, we still + // write all 8-bits of priority to an ICC register + // + mov x0, #31 << 3 + msr ICC_PMR_EL1, x0 + + // + // set global enable and wait for our interrupt to arrive + // + mov x0, #1 + msr ICC_IGRPEN1_EL1, x0 + isb + + // + // x19 already contains the CPU number, so branch to secondary + // code if we're not on CPU0 + // + cbnz x19, el1_secondary + + // + // Fall through to primary code + // + + +// +// ------------------------------------------------------------ +// +// EL1 - primary CPU init code +// +// This code is run on CPU0, while the other CPUs are in the +// holding pen +// + + .global el1_primary + .type el1_primary, "function" +el1_primary: + + // + // Turn on the banked GIC distributor enable, + // ready for individual CPU enables later + // + mov w0, #(1 << 1) // gicdctlr_EnableGrp1A + bl EnableGICD + + // + // Generate TTBR0 L1 + // + // at 4KB granularity, 32-bit VA space, table lookup starts at + // L1, with 1GB regions + // + // we are going to create entries pointing to L2 tables for a + // couple of these 1GB regions, the first of which is the + // RAM on the VE board model - get the table addresses and + // start by emptying out the L1 page tables (4 entries at L1 + // for a 4K granularity) + // + // x21 = address of L1 tables + // + ldr x21, =Image$$TTB0_L1$$ZI$$Base + mov x0, x21 + mov x1, #(4 << 3) + bl ZeroBlock + + // + // time to start mapping the RAM regions - clear out the + // L2 tables and point to them from the L1 tables + // + // x22 = address of L2 tables, needs to be remembered in case + // we want to re-use the tables for mapping peripherals + // + ldr x22, =Image$$TTB0_L2_RAM$$ZI$$Base + mov x1, #(512 << 3) + mov x0, x22 + bl ZeroBlock + + // + // Get the start address of RAM (the EXEC region) into x4 + // and calculate the offset into the L1 table (1GB per region, + // max 4GB) + // + // x23 = L1 table offset, saved for later comparison against + // peripheral offset + // + ldr x4, =Image$$EXEC$$RO$$Base + ubfx x23, x4, #30, #2 + + orr x1, x22, #TT_S1_ATTR_PAGE + str x1, [x21, x23, lsl #3] + + // + // we've already used the RAM start address in x4 - we now need + // to get this in terms of an offset into the L2 page tables, + // where each entry covers 2MB + // + ubfx x2, x4, #21, #9 + + // + // TOP_OF_RAM in the scatter file marks the end of the + // Execute region in RAM: convert the end of this region to an + // offset too, being careful to round up, then calculate the + // number of entries to write + // + ldr x5, =Image$$TOP_OF_RAM$$ZI$$Base + sub x3, x5, #1 + ubfx x3, x3, #21, #9 + add x3, x3, #1 + sub x3, x3, x2 + + // + // set x1 to the required page table attributes, then orr + // in the start address (modulo 2MB) + // + // L2 tables in our configuration cover 2MB per entry - map + // memory as Shared, Normal WBWA (MAIR[1]) with a flat + // VA->PA translation + // + bic x4, x4, #((1 << 21) - 1) + mov x1, #(TT_S1_ATTR_BLOCK | \ + (1 << TT_S1_ATTR_MATTR_LSB) | \ + TT_S1_ATTR_NS | \ + TT_S1_ATTR_AP_RW_PL1 | \ + TT_S1_ATTR_SH_INNER | \ + TT_S1_ATTR_AF | \ + TT_S1_ATTR_nG) + orr x1, x1, x4 + + // + // factor the offset into the page table address and then write + // the entries + // + add x0, x22, x2, lsl #3 + +loop1: + subs x3, x3, #1 + str x1, [x0], #8 + add x1, x1, #0x200, LSL #12 // equiv to add x1, x1, #(1 << 21) // 2MB per entry + bne loop1 + + + // + // now mapping the Peripheral regions - clear out the + // L2 tables and point to them from the L1 tables + // + // The assumption here is that all peripherals live within + // a common 1GB region (i.e. that there's a single set of + // L2 pages for all the peripherals). We only use a UART + // and the GIC in this example, so the assumption is sound + // + // x24 = address of L2 peripheral tables + // + ldr x24, =Image$$TTB0_L2_PERIPH$$ZI$$Base + + // + // get the GICD address into x4 and calculate + // the offset into the L1 table + // + // x25 = L1 table offset + // + ldr x4, =Image$$GICD$$ZI$$Base + ubfx x25, x4, #30, #2 + + // + // here's the tricky bit: it's possible that the peripherals are + // in the same 1GB region as the RAM, in which case we don't need + // to prime a separate set of L2 page tables, nor add them to the + // L1 tables + // + // if we're going to re-use the TTB0_L2_RAM tables, get their + // address into x24, which is used later on to write the PTEs + // + cmp x25, x23 + csel x24, x22, x24, EQ + b.eq nol2setup + + // + // Peripherals are in a separate 1GB region, and so have their own + // set of L2 tables - clean out the tables and add them to the L1 + // table + // + mov x0, x24 + mov x1, #512 << 3 + bl ZeroBlock + + orr x1, x24, #TT_S1_ATTR_PAGE + str x1, [x21, x25, lsl #3] + + // + // there's only going to be a single 2MB region for GICD (in + // x4) - get this in terms of an offset into the L2 page tables + // + // with larger systems, it is possible that the GIC redistributor + // registers require extra 2MB pages, in which case extra code + // would be required here + // +nol2setup: + ubfx x2, x4, #21, #9 + + // + // set x1 to the required page table attributes, then orr + // in the start address (modulo 2MB) + // + // L2 tables in our configuration cover 2MB per entry - map + // memory as NS Device-nGnRE (MAIR[2]) with a flat VA->PA + // translation + // + bic x4, x4, #((1 << 21) - 1) // start address mod 2MB + mov x1, #(TT_S1_ATTR_BLOCK | \ + (2 << TT_S1_ATTR_MATTR_LSB) | \ + TT_S1_ATTR_NS | \ + TT_S1_ATTR_AP_RW_PL1 | \ + TT_S1_ATTR_AF | \ + TT_S1_ATTR_nG) + orr x1, x1, x4 + + // + // only a single L2 entry for this, so no loop as we have for RAM, above + // + str x1, [x24, x2, lsl #3] + + // + // we have CS3_PERIPHERALS that include the UART controller + // + // Again, the code is making assumptions - this time that the CS3_PERIPHERALS + // region uses the same 1GB portion of the address space as the GICD, + // and thus shares the same set of L2 page tables + // + // Get CS3_PERIPHERALS address into x4 and calculate the offset into the + // L2 tables + // + ldr x4, =Image$$CS3_PERIPHERALS$$ZI$$Base + ubfx x2, x4, #21, #9 + + // + // set x1 to the required page table attributes, then orr + // in the start address (modulo 2MB) + // + // L2 tables in our configuration cover 2MB per entry - map + // memory as NS Device-nGnRE (MAIR[2]) with a flat VA->PA + // translation + // + bic x4, x4, #((1 << 21) - 1) // start address mod 2MB + mov x1, #(TT_S1_ATTR_BLOCK | \ + (2 << TT_S1_ATTR_MATTR_LSB) | \ + TT_S1_ATTR_NS | \ + TT_S1_ATTR_AP_RW_PL1 | \ + TT_S1_ATTR_AF | \ + TT_S1_ATTR_nG) + orr x1, x1, x4 + + // + // only a single L2 entry again - write it + // + str x1, [x24, x2, lsl #3] + + // + // issue a barrier to ensure all table entry writes are complete + // + dsb ish + + ldr x1, =is_mmu_ready + mov x2, #1 + str x2, [x1] + + // + // Enable the MMU. Caches will be enabled later, after scatterloading. + // + mrs x1, SCTLR_EL1 + orr x1, x1, #SCTLR_ELx_M + bic x1, x1, #SCTLR_ELx_A // Disable alignment fault checking. To enable, change bic to orr + msr SCTLR_EL1, x1 + isb + + // + // Branch to C library init code + // + b __main + + +// ------------------------------------------------------------ + +// AArch64 Arm C library startup add-in: + +// The Arm Architecture Reference Manual for Armv8-A states: +// +// Instruction accesses to Non-cacheable Normal memory can be held in instruction caches. +// Correspondingly, the sequence for ensuring that modifications to instructions are available +// for execution must include invalidation of the modified locations from the instruction cache, +// even if the instructions are held in Normal Non-cacheable memory. +// This includes cases where the instruction cache is disabled. +// +// To invalidate the AArch64 instruction cache after scatter-loading and before initialization of the stack and heap, +// it is necessary for the user to: +// +// * Implement instruction cache invalidation code in _platform_pre_stackheap_init. +// * Ensure all code on the path from the program entry up to and including _platform_pre_stackheap_init is located in a root region. +// +// In this example, this function is only called once, by the primary core + + .global _platform_pre_stackheap_init + .type _platform_pre_stackheap_init, "function" + .cfi_startproc +_platform_pre_stackheap_init: + dsb ish // ensure all previous stores have completed before invalidating + ic ialluis // I cache invalidate all inner shareable to PoU (which includes secondary cores) + dsb ish // ensure completion on inner shareable domain (which includes secondary cores) + isb + + // Scatter-loading is complete, so enable the caches here, so that the C-library's mutex initialization later will work + mrs x1, SCTLR_EL1 + orr x1, x1, #SCTLR_ELx_C + orr x1, x1, #SCTLR_ELx_I + msr SCTLR_EL1, x1 + isb + + ret + .cfi_endproc + + +// ------------------------------------------------------------ +// EL1 - secondary CPU init code +// +// This code is run on CPUs 1, 2, 3 etc.... +// ------------------------------------------------------------ + + .global el1_secondary + .type el1_secondary, "function" +el1_secondary: + +wait_for_mmu_ready: + ldr x1, =is_mmu_ready + ldr x1, [x1] + cmp x1, #1 + b.ne wait_for_mmu_ready + + // + // Enable the MMU and caches + // + mrs x1, SCTLR_EL1 + orr x1, x1, #SCTLR_ELx_M + orr x1, x1, #SCTLR_ELx_C + orr x1, x1, #SCTLR_ELx_I + bic x1, x1, #SCTLR_ELx_A // Disable alignment fault checking. To enable, change bic to orr + msr SCTLR_EL1, x1 + isb + + /* EL: Secondary core entrance. */ + B _tx_thread_smp_initialize_wait + +loop_wfi: + dsb SY // Clear all pending data accesses + wfi // Go to sleep + + // + // something woke us from our wait, was it the required interrupt? + // + mov w0, w19 + mov w1, #15 + bl GetPrivateIntPending + cbz w0, loop_wfi + + // + // it was - there's no need to actually take the interrupt, + // so just clear it + // + mov w0, w19 + mov w1, #15 + bl ClearPrivateIntPending + + // + // Branch to thread start + // + // B MainApp + + /** + * Retargeted to prevent the C library from doing its own stack and heap + * initialisation. + */ + .type __user_setup_stackheap, @function +__user_setup_stackheap: + ADRP X0, Image$$SYS_STACK$$ZI$$Limit + MOV SP, X0 + ADRP X0, Image$$ARM_LIB_HEAP$$ZI$$Base + ADRP X2, Image$$ARM_LIB_HEAP$$ZI$$Limit + RET + diff --git a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/timer_interrupts.c b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/timer_interrupts.c new file mode 100644 index 00000000..7b0996ef --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/timer_interrupts.c @@ -0,0 +1,152 @@ +/* Bare-metal example for Armv8-A FVP Base model */ + +/* Timer and interrupts */ + +/* Copyright (c) 2016 Arm Limited (or its affiliates). All rights reserved. */ +/* Use, modification and redistribution of this file is subject to your */ +/* possession of a valid DS-5 end user licence agreement and your compliance */ +/* with all applicable terms and conditions of such licence agreement. */ + +#include + +#include "GICv3.h" +#include "GICv3_gicc.h" +#include "sp804_timer.h" + +void _tx_timer_interrupt(void); + +// LED Base address +#define LED_BASE (volatile unsigned int *)0x1C010008 + + +void nudge_leds(void) // Move LEDs along +{ + static int state = 1; + static int value = 1; + + if (state) + { + int max = (1 << 7); + value <<= 1; + if (value == max) + state = 0; + } + else + { + value >>= 1; + if (value == 1) + state = 1; + } + + *LED_BASE = value; // Update LEDs hardware +} + + +// Initialize Timer 0 and Interrupt Controller +void init_timer(void) +{ + // Enable interrupts + __asm("MSR DAIFClr, #0xF"); + setICC_IGRPEN1_EL1(igrpEnable); + + // Configure the SP804 timer to generate an interrupt + setTimerBaseAddress(0x1C110000); + initTimer(0x200, SP804_AUTORELOAD, SP804_GENERATE_IRQ); + startTimer(); + + // The SP804 timer generates SPI INTID 34. Enable + // this ID, and route it to core 0.0.0.0 (this one!) + SetSPIRoute(34, 0, gicdirouter_ModeSpecific); // Route INTID 34 to 0.0.0.0 (this core) + SetSPIPriority(34, 0); // Set INTID 34 to priority to 0 + ConfigureSPI(34, gicdicfgr_Level); // Set INTID 34 as level-sensitive + EnableSPI(34); // Enable INTID 34 +} + + +// -------------------------------------------------------- + +void irqHandler(void) +{ + unsigned int ID; + + ID = getICC_IAR1(); // readIntAck(); + + // Check for reserved IDs + if ((1020 <= ID) && (ID <= 1023)) + { + //printf("irqHandler() - Reserved INTID %d\n\n", ID); + return; + } + + switch(ID) + { + case 34: + // Dual-Timer 0 (SP804) + //printf("irqHandler() - External timer interrupt\n\n"); + nudge_leds(); + clearTimerIrq(); + + /* Call ThreadX timer interrupt processing. */ + _tx_timer_interrupt(); + + break; + + default: + // Unexpected ID value + //printf("irqHandler() - Unexpected INTID %d\n\n", ID); + break; + } + + // Write the End of Interrupt register to tell the GIC + // we've finished handling the interrupt + setICC_EOIR1(ID); // writeAliasedEOI(ID); +} + +// -------------------------------------------------------- + +// Not actually used in this example, but provided for completeness + +void fiqHandler(void) +{ + unsigned int ID; + unsigned int aliased = 0; + + ID = getICC_IAR0(); // readIntAck(); + printf("fiqHandler() - Read %d from IAR0\n", ID); + + // Check for reserved IDs + if ((1020 <= ID) && (ID <= 1023)) + { + printf("fiqHandler() - Reserved INTID %d\n\n", ID); + ID = getICC_IAR1(); // readAliasedIntAck(); + printf("fiqHandler() - Read %d from AIAR\n", ID); + aliased = 1; + + // If still spurious then simply return + if ((1020 <= ID) && (ID <= 1023)) + return; + } + + switch(ID) + { + case 34: + // Dual-Timer 0 (SP804) + printf("fiqHandler() - External timer interrupt\n\n"); + clearTimerIrq(); + break; + + default: + // Unexpected ID value + printf("fiqHandler() - Unexpected INTID %d\n\n", ID); + break; + } + + // Write the End of Interrupt register to tell the GIC + // we've finished handling the interrupt + // NOTE: If the ID was read from the Aliased IAR, then + // the aliased EOI register must be used + if (aliased == 0) + setICC_EOIR0(ID); // writeEOI(ID); + else + setICC_EOIR1(ID); // writeAliasedEOI(ID); +} diff --git a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/use_model_semihosting.ds b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/use_model_semihosting.ds new file mode 100644 index 00000000..6fde52b2 --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/use_model_semihosting.ds @@ -0,0 +1 @@ +set semihosting enabled off diff --git a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/v8_aarch64.S b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/v8_aarch64.S new file mode 100644 index 00000000..e2d81e5e --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/v8_aarch64.S @@ -0,0 +1,161 @@ +// ------------------------------------------------------------ +// Armv8-A AArch64 - Common helper functions +// +// Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your +// possession of a valid DS-5 end user licence agreement and your compliance +// with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#include "v8_system.h" + + .text + .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + + .global EnableCachesEL1 + .global DisableCachesEL1 + .global InvalidateUDCaches + .global GetMIDR + .global GetMPIDR + .global GetCPUID + +// ------------------------------------------------------------ + +// +// void EnableCachesEL1(void) +// +// enable Instruction and Data caches +// + .type EnableCachesEL1, "function" + .cfi_startproc +EnableCachesEL1: + + mrs x0, SCTLR_EL1 + orr x0, x0, #SCTLR_ELx_I + orr x0, x0, #SCTLR_ELx_C + msr SCTLR_EL1, x0 + + isb + ret + .cfi_endproc + + +// ------------------------------------------------------------ + + .type DisableCachesEL1, "function" + .cfi_startproc +DisableCachesEL1: + + mrs x0, SCTLR_EL1 + bic x0, x0, #SCTLR_ELx_I + bic x0, x0, #SCTLR_ELx_C + msr SCTLR_EL1, x0 + + isb + ret + .cfi_endproc + + +// ------------------------------------------------------------ + +// +// void InvalidateUDCaches(void) +// +// Invalidate data and unified caches +// + .type InvalidateUDCaches, "function" + .cfi_startproc +InvalidateUDCaches: + // From the Armv8-A Architecture Reference Manual + + dmb ish // ensure all prior inner-shareable accesses have been observed + + mrs x0, CLIDR_EL1 + and w3, w0, #0x07000000 // get 2 x level of coherence + lsr w3, w3, #23 + cbz w3, finished + mov w10, #0 // w10 = 2 x cache level + mov w8, #1 // w8 = constant 0b1 +loop_level: + add w2, w10, w10, lsr #1 // calculate 3 x cache level + lsr w1, w0, w2 // extract 3-bit cache type for this level + and w1, w1, #0x7 + cmp w1, #2 + b.lt next_level // no data or unified cache at this level + msr CSSELR_EL1, x10 // select this cache level + isb // synchronize change of csselr + mrs x1, CCSIDR_EL1 // read ccsidr + and w2, w1, #7 // w2 = log2(linelen)-4 + add w2, w2, #4 // w2 = log2(linelen) + ubfx w4, w1, #3, #10 // w4 = max way number, right aligned + clz w5, w4 // w5 = 32-log2(ways), bit position of way in dc operand + lsl w9, w4, w5 // w9 = max way number, aligned to position in dc operand + lsl w16, w8, w5 // w16 = amount to decrement way number per iteration +loop_way: + ubfx w7, w1, #13, #15 // w7 = max set number, right aligned + lsl w7, w7, w2 // w7 = max set number, aligned to position in dc operand + lsl w17, w8, w2 // w17 = amount to decrement set number per iteration +loop_set: + orr w11, w10, w9 // w11 = combine way number and cache number ... + orr w11, w11, w7 // ... and set number for dc operand + dc isw, x11 // do data cache invalidate by set and way + subs w7, w7, w17 // decrement set number + b.ge loop_set + subs x9, x9, x16 // decrement way number + b.ge loop_way +next_level: + add w10, w10, #2 // increment 2 x cache level + cmp w3, w10 + b.gt loop_level + dsb sy // ensure completion of previous cache maintenance operation + isb +finished: + ret + .cfi_endproc + + +// ------------------------------------------------------------ + +// +// ID Register functions +// + + .type GetMIDR, "function" + .cfi_startproc +GetMIDR: + + mrs x0, MIDR_EL1 + ret + .cfi_endproc + + + .type GetMPIDR, "function" + .cfi_startproc +GetMPIDR: + + mrs x0, MPIDR_EL1 + ret + .cfi_endproc + + + .type GetCPUID, "function" + .cfi_startproc +GetCPUID: + + mrs x0, MIDR_EL1 + ubfx x0, x0, #4, #12 // extract PartNum + cmp x0, #0xD0A // Cortex-A75 + b.eq DynamIQ + cmp x0, #0xD05 // Cortex-A55 + b.eq DynamIQ + b Others +DynamIQ: + mrs x0, MPIDR_EL1 + ubfx x0, x0, #MPIDR_EL1_AFF1_LSB, #MPIDR_EL1_AFF_WIDTH + ret + +Others: + mrs x0, MPIDR_EL1 + ubfx x0, x0, #MPIDR_EL1_AFF0_LSB, #MPIDR_EL1_AFF_WIDTH + ret + .cfi_endproc diff --git a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/v8_mmu.h b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/v8_mmu.h new file mode 100644 index 00000000..afb8b923 --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/v8_mmu.h @@ -0,0 +1,118 @@ +// +// Defines for v8 Memory Model +// +// Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your +// possession of a valid DS-5 end user licence agreement and your compliance +// with all applicable terms and conditions of such licence agreement. +// + +#ifndef V8_MMU_H +#define V8_MMU_H + +// +// Translation Control Register fields +// +// RGN field encodings +// +#define TCR_RGN_NC 0b00 +#define TCR_RGN_WBWA 0b01 +#define TCR_RGN_WT 0b10 +#define TCR_RGN_WBRA 0b11 + +// +// Shareability encodings +// +#define TCR_SHARE_NONE 0b00 +#define TCR_SHARE_OUTER 0b10 +#define TCR_SHARE_INNER 0b11 + +// +// Granule size encodings +// +#define TCR_GRANULE_4K 0b00 +#define TCR_GRANULE_64K 0b01 +#define TCR_GRANULE_16K 0b10 + +// +// Physical Address sizes +// +#define TCR_SIZE_4G 0b000 +#define TCR_SIZE_64G 0b001 +#define TCR_SIZE_1T 0b010 +#define TCR_SIZE_4T 0b011 +#define TCR_SIZE_16T 0b100 +#define TCR_SIZE_256T 0b101 + +// +// Translation Control Register fields +// +#define TCR_EL1_T0SZ_SHIFT 0 +#define TCR_EL1_EPD0 (1 << 7) +#define TCR_EL1_IRGN0_SHIFT 8 +#define TCR_EL1_ORGN0_SHIFT 10 +#define TCR_EL1_SH0_SHIFT 12 +#define TCR_EL1_TG0_SHIFT 14 + +#define TCR_EL1_T1SZ_SHIFT 16 +#define TCR_EL1_A1 (1 << 22) +#define TCR_EL1_EPD1 (1 << 23) +#define TCR_EL1_IRGN1_SHIFT 24 +#define TCR_EL1_ORGN1_SHIFT 26 +#define TCR_EL1_SH1_SHIFT 28 +#define TCR_EL1_TG1_SHIFT 30 +#define TCR_EL1_IPS_SHIFT 32 +#define TCR_EL1_AS (1 << 36) +#define TCR_EL1_TBI0 (1 << 37) +#define TCR_EL1_TBI1 (1 << 38) + +// +// Stage 1 Translation Table descriptor fields +// +#define TT_S1_ATTR_FAULT (0b00 << 0) +#define TT_S1_ATTR_BLOCK (0b01 << 0) // Level 1/2 +#define TT_S1_ATTR_TABLE (0b11 << 0) // Level 0/1/2 +#define TT_S1_ATTR_PAGE (0b11 << 0) // Level 3 + +#define TT_S1_ATTR_MATTR_LSB 2 + +#define TT_S1_ATTR_NS (1 << 5) + +#define TT_S1_ATTR_AP_RW_PL1 (0b00 << 6) +#define TT_S1_ATTR_AP_RW_ANY (0b01 << 6) +#define TT_S1_ATTR_AP_RO_PL1 (0b10 << 6) +#define TT_S1_ATTR_AP_RO_ANY (0b11 << 6) + +#define TT_S1_ATTR_SH_NONE (0b00 << 8) +#define TT_S1_ATTR_SH_OUTER (0b10 << 8) +#define TT_S1_ATTR_SH_INNER (0b11 << 8) + +#define TT_S1_ATTR_AF (1 << 10) +#define TT_S1_ATTR_nG (1 << 11) + +#define TT_S1_ATTR_CONTIG (1 << 52) +#define TT_S1_ATTR_PXN (1 << 53) +#define TT_S1_ATTR_UXN (1 << 54) + +#define TT_S1_MAIR_DEV_nGnRnE 0b00000000 +#define TT_S1_MAIR_DEV_nGnRE 0b00000100 +#define TT_S1_MAIR_DEV_nGRE 0b00001000 +#define TT_S1_MAIR_DEV_GRE 0b00001100 + +// +// Inner and Outer Normal memory attributes use the same bit patterns +// Outer attributes just need to be shifted up +// +#define TT_S1_MAIR_OUTER_SHIFT 4 + +#define TT_S1_MAIR_WT_TRANS_RA 0b0010 + +#define TT_S1_MAIR_WB_TRANS_RA 0b0110 +#define TT_S1_MAIR_WB_TRANS_RWA 0b0111 + +#define TT_S1_MAIR_WT_RA 0b1010 + +#define TT_S1_MAIR_WB_RA 0b1110 +#define TT_S1_MAIR_WB_RWA 0b1111 + +#endif // V8_MMU_H diff --git a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/v8_system.h b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/v8_system.h new file mode 100644 index 00000000..e54f2fc7 --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/v8_system.h @@ -0,0 +1,115 @@ +// +// Defines for v8 System Registers +// +// Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your +// possession of a valid DS-5 end user licence agreement and your compliance +// with all applicable terms and conditions of such licence agreement. +// + +#ifndef V8_SYSTEM_H +#define V8_SYSTEM_H + +// +// AArch64 SPSR +// +#define AARCH64_SPSR_EL3h 0b1101 +#define AARCH64_SPSR_EL3t 0b1100 +#define AARCH64_SPSR_EL2h 0b1001 +#define AARCH64_SPSR_EL2t 0b1000 +#define AARCH64_SPSR_EL1h 0b0101 +#define AARCH64_SPSR_EL1t 0b0100 +#define AARCH64_SPSR_EL0t 0b0000 +#define AARCH64_SPSR_RW (1 << 4) +#define AARCH64_SPSR_F (1 << 6) +#define AARCH64_SPSR_I (1 << 7) +#define AARCH64_SPSR_A (1 << 8) +#define AARCH64_SPSR_D (1 << 9) +#define AARCH64_SPSR_IL (1 << 20) +#define AARCH64_SPSR_SS (1 << 21) +#define AARCH64_SPSR_V (1 << 28) +#define AARCH64_SPSR_C (1 << 29) +#define AARCH64_SPSR_Z (1 << 30) +#define AARCH64_SPSR_N (1 << 31) + +// +// Multiprocessor Affinity Register +// +#define MPIDR_EL1_AFF3_LSB 32 +#define MPIDR_EL1_U (1 << 30) +#define MPIDR_EL1_MT (1 << 24) +#define MPIDR_EL1_AFF2_LSB 16 +#define MPIDR_EL1_AFF1_LSB 8 +#define MPIDR_EL1_AFF0_LSB 0 +#define MPIDR_EL1_AFF_WIDTH 8 + +// +// Data Cache Zero ID Register +// +#define DCZID_EL0_BS_LSB 0 +#define DCZID_EL0_BS_WIDTH 4 +#define DCZID_EL0_DZP_LSB 5 +#define DCZID_EL0_DZP (1 << 5) + +// +// System Control Register +// +#define SCTLR_EL1_UCI (1 << 26) +#define SCTLR_ELx_EE (1 << 25) +#define SCTLR_EL1_E0E (1 << 24) +#define SCTLR_ELx_WXN (1 << 19) +#define SCTLR_EL1_nTWE (1 << 18) +#define SCTLR_EL1_nTWI (1 << 16) +#define SCTLR_EL1_UCT (1 << 15) +#define SCTLR_EL1_DZE (1 << 14) +#define SCTLR_ELx_I (1 << 12) +#define SCTLR_EL1_UMA (1 << 9) +#define SCTLR_EL1_SED (1 << 8) +#define SCTLR_EL1_ITD (1 << 7) +#define SCTLR_EL1_THEE (1 << 6) +#define SCTLR_EL1_CP15BEN (1 << 5) +#define SCTLR_EL1_SA0 (1 << 4) +#define SCTLR_ELx_SA (1 << 3) +#define SCTLR_ELx_C (1 << 2) +#define SCTLR_ELx_A (1 << 1) +#define SCTLR_ELx_M (1 << 0) + +// +// Architectural Feature Access Control Register +// +#define CPACR_EL1_TTA (1 << 28) +#define CPACR_EL1_FPEN (3 << 20) + +// +// Architectural Feature Trap Register +// +#define CPTR_ELx_TCPAC (1 << 31) +#define CPTR_ELx_TTA (1 << 20) +#define CPTR_ELx_TFP (1 << 10) + +// +// Secure Configuration Register +// +#define SCR_EL3_TWE (1 << 13) +#define SCR_EL3_TWI (1 << 12) +#define SCR_EL3_ST (1 << 11) +#define SCR_EL3_RW (1 << 10) +#define SCR_EL3_SIF (1 << 9) +#define SCR_EL3_HCE (1 << 8) +#define SCR_EL3_SMD (1 << 7) +#define SCR_EL3_EA (1 << 3) +#define SCR_EL3_FIQ (1 << 2) +#define SCR_EL3_IRQ (1 << 1) +#define SCR_EL3_NS (1 << 0) + +// +// Hypervisor Configuration Register +// +#define HCR_EL2_ID (1 << 33) +#define HCR_EL2_CD (1 << 32) +#define HCR_EL2_RW (1 << 31) +#define HCR_EL2_TRVM (1 << 30) +#define HCR_EL2_HVC (1 << 29) +#define HCR_EL2_TDZ (1 << 28) + +#endif // V8_SYSTEM_H diff --git a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/v8_utils.S b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/v8_utils.S new file mode 100644 index 00000000..750488b7 --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/v8_utils.S @@ -0,0 +1,69 @@ +// +// Simple utility routines for baremetal v8 code +// +// Copyright (c) 2013-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your +// possession of a valid DS-5 end user licence agreement and your compliance +// with all applicable terms and conditions of such licence agreement. +// + +#include "v8_system.h" + + .text + .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + +// +// void *ZeroBlock(void *blockPtr, unsigned int nBytes) +// +// Zero fill a block of memory +// Fill memory pages or similar structures with zeros. +// The byte count must be a multiple of the block fill size (16 bytes) +// +// Inputs: +// blockPtr - base address of block to fill +// nBytes - block size, in bytes +// +// Returns: +// pointer to just filled block, NULL if nBytes is +// incompatible with block fill size +// + .global ZeroBlock + .type ZeroBlock, "function" + .cfi_startproc +ZeroBlock: + + // + // we fill data by steam, 16 bytes at a time: check that + // blocksize is a multiple of that + // + ubfx x2, x1, #0, #4 + cbnz x2, incompatible + + // + // we already have one register full of zeros, get another + // + mov x3, x2 + + // + // OK, set temporary pointer and away we go + // + add x0, x0, x1 + +loop0: + subs x1, x1, #16 + stp x2, x3, [x0, #-16]! + b.ne loop0 + + // + // that's all - x0 will be back to its start value + // + ret + + // + // parameters are incompatible with block size - return + // an indication that this is so + // +incompatible: + mov x0,#0 + ret + .cfi_endproc diff --git a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/vectors.S b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/vectors.S new file mode 100644 index 00000000..be6d28a3 --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/vectors.S @@ -0,0 +1,252 @@ +// ------------------------------------------------------------ +// Armv8-A Vector tables +// +// Copyright (c) 2014-2016 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your +// possession of a valid DS-5 end user licence agreement and your compliance +// with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + + + .global el1_vectors + .global el2_vectors + .global el3_vectors + .global c0sync1 + .global irqHandler + .global fiqHandler + .global irqFirstLevelHandler + .global fiqFirstLevelHandler + + .section EL1VECTORS, "ax" + .align 11 + +// +// Current EL with SP0 +// +el1_vectors: +c0sync1: B c0sync1 + + .balign 0x80 +c0irq1: B irqFirstLevelHandler + + .balign 0x80 +c0fiq1: B fiqFirstLevelHandler + + .balign 0x80 +c0serr1: B c0serr1 + +// +// Current EL with SPx +// + .balign 0x80 +cxsync1: B cxsync1 + + .balign 0x80 +cxirq1: B irqFirstLevelHandler + + .balign 0x80 +cxfiq1: B fiqFirstLevelHandler + + .balign 0x80 +cxserr1: B cxserr1 + +// +// Lower EL using AArch64 +// + .balign 0x80 +l64sync1: B l64sync1 + + .balign 0x80 +l64irq1: B irqFirstLevelHandler + + .balign 0x80 +l64fiq1: B fiqFirstLevelHandler + + .balign 0x80 +l64serr1: B l64serr1 + +// +// Lower EL using AArch32 +// + .balign 0x80 +l32sync1: B l32sync1 + + .balign 0x80 +l32irq1: B irqFirstLevelHandler + + .balign 0x80 +l32fiq1: B fiqFirstLevelHandler + + .balign 0x80 +l32serr1: B l32serr1 + +//---------------------------------------------------------------- + + .section EL2VECTORS, "ax" + .align 11 + +// +// Current EL with SP0 +// +el2_vectors: +c0sync2: B c0sync2 + + .balign 0x80 +c0irq2: B irqFirstLevelHandler + + .balign 0x80 +c0fiq2: B fiqFirstLevelHandler + + .balign 0x80 +c0serr2: B c0serr2 + +// +// Current EL with SPx +// + .balign 0x80 +cxsync2: B cxsync2 + + .balign 0x80 +cxirq2: B irqFirstLevelHandler + + .balign 0x80 +cxfiq2: B fiqFirstLevelHandler + + .balign 0x80 +cxserr2: B cxserr2 + +// +// Lower EL using AArch64 +// + .balign 0x80 +l64sync2: B l64sync2 + + .balign 0x80 +l64irq2: B irqFirstLevelHandler + + .balign 0x80 +l64fiq2: B fiqFirstLevelHandler + + .balign 0x80 +l64serr2: B l64serr2 + +// +// Lower EL using AArch32 +// + .balign 0x80 +l32sync2: B l32sync2 + + .balign 0x80 +l32irq2: B irqFirstLevelHandler + + .balign 0x80 +l32fiq2: B fiqFirstLevelHandler + + .balign 0x80 +l32serr2: B l32serr2 + +//---------------------------------------------------------------- + + .section EL3VECTORS, "ax" + .align 11 + +// +// Current EL with SP0 +// +el3_vectors: +c0sync3: B c0sync3 + + .balign 0x80 +c0irq3: B irqFirstLevelHandler + + .balign 0x80 +c0fiq3: B fiqFirstLevelHandler + + .balign 0x80 +c0serr3: B c0serr3 + +// +// Current EL with SPx +// + .balign 0x80 +cxsync3: B cxsync3 + + .balign 0x80 +cxirq3: B irqFirstLevelHandler + + .balign 0x80 +cxfiq3: B fiqFirstLevelHandler + + .balign 0x80 +cxserr3: B cxserr3 + +// +// Lower EL using AArch64 +// + .balign 0x80 +l64sync3: B l64sync3 + + .balign 0x80 +l64irq3: B irqFirstLevelHandler + + .balign 0x80 +l64fiq3: B fiqFirstLevelHandler + + .balign 0x80 +l64serr3: B l64serr3 + +// +// Lower EL using AArch32 +// + .balign 0x80 +l32sync3: B l32sync3 + + .balign 0x80 +l32irq3: B irqFirstLevelHandler + + .balign 0x80 +l32fiq3: B fiqFirstLevelHandler + + .balign 0x80 +l32serr3: B l32serr3 + + + .section InterruptHandlers, "ax" + .balign 4 + + .type irqFirstLevelHandler, "function" +irqFirstLevelHandler: + MSR SPSel, 0 + STP x29, x30, [sp, #-16]! + BL _tx_thread_context_save + BL irqHandler + B _tx_thread_context_restore + + .type fiqFirstLevelHandler, "function" +fiqFirstLevelHandler: + STP x29, x30, [sp, #-16]! + STP x18, x19, [sp, #-16]! + STP x16, x17, [sp, #-16]! + STP x14, x15, [sp, #-16]! + STP x12, x13, [sp, #-16]! + STP x10, x11, [sp, #-16]! + STP x8, x9, [sp, #-16]! + STP x6, x7, [sp, #-16]! + STP x4, x5, [sp, #-16]! + STP x2, x3, [sp, #-16]! + STP x0, x1, [sp, #-16]! + + BL fiqHandler + + LDP x0, x1, [sp], #16 + LDP x2, x3, [sp], #16 + LDP x4, x5, [sp], #16 + LDP x6, x7, [sp], #16 + LDP x8, x9, [sp], #16 + LDP x10, x11, [sp], #16 + LDP x12, x13, [sp], #16 + LDP x14, x15, [sp], #16 + LDP x16, x17, [sp], #16 + LDP x18, x19, [sp], #16 + LDP x29, x30, [sp], #16 + ERET diff --git a/ports_smp/cortex_a35_smp/ac6/example_build/tx/.cproject b/ports_smp/cortex_a35_smp/ac6/example_build/tx/.cproject new file mode 100644 index 00000000..70870f3f --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/example_build/tx/.cproject @@ -0,0 +1,232 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/cortex_a35_smp/ac6/example_build/tx/.project b/ports_smp/cortex_a35_smp/ac6/example_build/tx/.project new file mode 100644 index 00000000..10681969 --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/example_build/tx/.project @@ -0,0 +1,48 @@ + + + tx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + inc_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common_smp/inc + + + inc_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/inc + + + src_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common_smp/src + + + src_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/src + + + diff --git a/ports_smp/cortex_a35_smp/ac6/example_build/tx/.settings/language.settings.xml b/ports_smp/cortex_a35_smp/ac6/example_build/tx/.settings/language.settings.xml new file mode 100644 index 00000000..4cc349c4 --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/example_build/tx/.settings/language.settings.xml @@ -0,0 +1,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/cortex_a35_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a35_smp/ac6/inc/tx_port.h new file mode 100644 index 00000000..ea59fe6c --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/inc/tx_port.h @@ -0,0 +1,432 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A35-SMP/AC6 */ +/* 6.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/************* Define ThreadX SMP constants. *************/ + +/* Define the ThreadX SMP maximum number of cores. */ + +#ifndef TX_THREAD_SMP_MAX_CORES +#define TX_THREAD_SMP_MAX_CORES 4 +#endif + + +/* Define the ThreadX SMP core mask. */ + +#ifndef TX_THREAD_SMP_CORE_MASK +#define TX_THREAD_SMP_CORE_MASK 0xF /* Where bit 0 represents Core 0, bit 1 represents Core 1, etc. */ +#endif + + +/* Define INLINE_DECLARE to whitespace for ARM compiler. */ + +#define INLINE_DECLARE + + +/* Define ThreadX SMP initialization macro. */ + +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION + + +/* Define ThreadX SMP pre-scheduler initialization. */ + +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION + + +/* Enable the inter-core interrupt logic. */ + +#define TX_THREAD_SMP_INTER_CORE_INTERRUPT + + +/* Determine if there is customer-specific wakeup logic needed. */ + +#ifdef TX_THREAD_SMP_WAKEUP_LOGIC + +/* Include customer-specific wakeup code. */ + +#include "tx_thread_smp_core_wakeup.h" +#else + +#ifdef TX_THREAD_SMP_DEFAULT_WAKEUP_LOGIC + +/* Default wakeup code. */ +#define TX_THREAD_SMP_WAKEUP_LOGIC +#define TX_THREAD_SMP_WAKEUP(i) _tx_thread_smp_core_preempt(i) +#endif +#endif + + +/* Ensure that the in-line resume/suspend define is not allowed. */ + +#ifdef TX_INLINE_THREAD_RESUME_SUSPEND +#undef TX_INLINE_THREAD_RESUME_SUSPEND +#endif + + +/************* End ThreadX SMP constants. *************/ + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef int LONG; +typedef unsigned int ULONG; +typedef unsigned long long ULONG64; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Override the alignment type to use 64-bit alignment and storage for pointers. */ + +#define ALIGN_TYPE_DEFINED +typedef unsigned long long ALIGN_TYPE; + + +/* Override the free block marker for byte pools to be a 64-bit constant. */ + +#define TX_BYTE_BLOCK_FREE ((ALIGN_TYPE) 0xFFFFEEEEFFFFEEEE) + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 4096 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#define TX_INT_ENABLE 0x00 /* Enable IRQ & FIQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE _tx_thread_smp_time_get() +#endif +#else +#ifndef TX_TRACE_TIME_SOURCE +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_fp_enable; +#define TX_THREAD_EXTENSION_3 VOID *tx_thread_extension_ptr; + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) b = (UINT) __builtin_ctz((unsigned int) m); + +#endif + + +/* Define the internal timer extension to also hold the thread pointer such that _tx_thread_timeout + can figure out what thread timeout to process. */ + +#define TX_TIMER_INTERNAL_EXTENSION VOID *tx_timer_internal_extension_ptr; + + +/* Define the thread timeout setup logic in _tx_thread_create. */ + +#define TX_THREAD_CREATE_TIMEOUT_SETUP(t) (t) -> tx_thread_timer.tx_timer_internal_timeout_function = &(_tx_thread_timeout); \ + (t) -> tx_thread_timer.tx_timer_internal_timeout_param = 0; \ + (t) -> tx_thread_timer.tx_timer_internal_extension_ptr = (VOID *) (t); + + +/* Define the thread timeout pointer setup in _tx_thread_timeout. */ + +#define TX_THREAD_TIMEOUT_POINTER_SETUP(t) (t) = (TX_THREAD *) _tx_timer_expired_timer_ptr -> tx_timer_internal_extension_ptr; + + +/************* Define ThreadX SMP data types and function prototypes. *************/ + +struct TX_THREAD_STRUCT; + + +/* Define the ThreadX SMP protection structure. */ + +typedef struct TX_THREAD_SMP_PROTECT_STRUCT +{ + ULONG tx_thread_smp_protect_in_force; + ULONG tx_thread_smp_protect_core; + ULONG tx_thread_smp_protect_count; + ULONG tx_thread_smp_protect_pad_0; + ULONG tx_thread_smp_protect_pad_1; + ULONG tx_thread_smp_protect_pad_2; + ULONG tx_thread_smp_protect_pad_3; +} TX_THREAD_SMP_PROTECT; + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_smp_protect(); +#define TX_RESTORE _tx_thread_smp_unprotect(interrupt_save); + +/************* End ThreadX SMP data type and function prototype definitions. *************/ + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define VFP extension for the Cortex-A35. Each is assumed to be called in the context of the executing + thread. */ + +#ifndef TX_SOURCE_CODE +#define tx_thread_fp_enable _tx_thread_fp_enable +#define tx_thread_fp_disable _tx_thread_fp_disable +#endif + +VOID tx_thread_fp_enable(VOID); +VOID tx_thread_fp_disable(VOID); + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A35-SMP/AC6 Version 6.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + + + + + diff --git a/ports_smp/cortex_a35_smp/ac6/readme_threadx.txt b/ports_smp/cortex_a35_smp/ac6/readme_threadx.txt new file mode 100644 index 00000000..a865af42 --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/readme_threadx.txt @@ -0,0 +1,254 @@ + Microsoft's Azure RTOS ThreadX SMP for Cortex-A35 + + Using the ARM Compiler 6 & DS + +1. Import the ThreadX Projects + +In order to build the ThreadX SMP library and the ThreadX SMP demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +into your DS workspace. + + +2. Building the ThreadX SMP run-time Library + +Building the ThreadX SMP library is easy; simply select the Eclipse project file +"tx" and then select the build button. You should now observe the compilation +and assembly of the ThreadX SMP library. This project build produces the ThreadX SMP +library file tx.a. + + +3. Demonstration System + +The ThreadX SMP demonstration is designed to execute under the DS debugger on the +'Debug Cortex-A35x4 SMP' FVP which must be downloaded from the ARM website and +requires a license. + +Building the demonstration is easy; simply select the sample_threadx project, and +select the build button. Next, in the sample_threadx project, right-click on the +sample_threadx.launch file and select 'Debug As -> sample_threadx'. The debugger is +setup for the Cortex-35x4 SMP FVP, so selecting "Debug" will launch the FVP, load +the sample_threadx.axf ELF file and run to main. You are now ready to execute the +ThreadX SMP demonstration. + + +4. System Initialization + +The entry point in ThreadX SMP for the Cortex-A35 using AC6 tools is at label +"start64". This is defined within the AC6 compiler's startup code. In addition, +this is where all static and global pre-set C variable initialization processing +takes place. + +The ThreadX SMP tx_initialize_low_level.s file is responsible for determining the +first available RAM address for use by the application, which is supplied as the +sole input parameter to your application definition function, tx_application_define. + + +5. Register Usage and Stack Frames + +The 64-bit AC6 compiler assumes that registers x0-x18 are scratch registers +for each function. All other registers used by a C function must be preserved +by the function. ThreadX SMP takes advantage of this in situations where a context +switch happens as a result of making a ThreadX SMP service call (which is itself a +C function). In such cases, the saved context of a thread is only the +non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + +FP not enabled and TX_THREAD.tx_thread_fp_enable == 0: + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x000 SPSR DAIF + 0x008 ELR 0 + 0x010 x28 x27 + 0x018 reserved x28 + 0x020 x26 x25 + 0x028 x27 x26 + 0x030 x24 x23 + 0x038 x25 x24 + 0x040 x22 x21 + 0x048 x23 x22 + 0x050 x20 x19 + 0x058 x21 x20 + 0x060 x18 x29 + 0x068 x19 x30 + 0x070 x16 + 0x078 x17 + 0x080 x14 + 0x088 x15 + 0x090 x12 + 0x098 x13 + 0x0A0 x10 + 0x0A8 x11 + 0x0B0 x8 + 0x0B8 x9 + 0x0C0 x6 + 0x0C8 x7 + 0x0D0 x4 + 0x0D8 x5 + 0x0E0 x2 + 0x0E8 x3 + 0x0F0 x0 + 0x0F8 x1 + 0x100 x29 + 0x108 x30 + + +FP enabled and TX_THREAD.tx_thread_fp_enable == 1: + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x000 SPSR DAIF + 0x008 ELR 0 + 0x010 FPSR FPSR + 0x018 FPCR FPCR + 0x020 q30 q14 + 0x030 q31 q15 + 0x040 q28 q12 + 0x050 q29 q13 + 0x060 q26 q10 + 0x070 q27 q11 + 0x080 q24 q8 + 0x090 q25 q9 + 0x0A0 q22 x27 + 0x0A8 x28 + 0x0B0 q23 x25 + 0x0B8 x26 + 0x0C0 q20 x23 + 0x0C8 x24 + 0x0D0 q21 x21 + 0x0D8 x22 + 0x0E0 q18 x19 + 0x0E8 x20 + 0x0F0 q19 x29 + 0x0F8 x30 + 0x100 q16 + 0x110 q17 + 0x120 q14 + 0x130 q15 + 0x140 q12 + 0x150 q13 + 0x160 q10 + 0x170 q11 + 0x180 q8 + 0x190 q9 + 0x1A0 q6 + 0x1B0 q7 + 0x1C0 q4 + 0x1D0 q5 + 0x1E0 q2 + 0x1F0 q3 + 0x200 q0 + 0x210 q1 + 0x220 x28 + 0x228 reserved + 0x230 x26 + 0x238 x27 + 0x240 x24 + 0x248 x25 + 0x250 x22 + 0x258 x23 + 0x260 x20 + 0x268 x21 + 0x270 x18 + 0x278 x19 + 0x280 x16 + 0x288 x17 + 0x290 x14 + 0x298 x15 + 0x2A0 x12 + 0x2A8 x13 + 0x2B0 x10 + 0x2B8 x11 + 0x2C0 x8 + 0x2C8 x9 + 0x2D0 x6 + 0x2D8 x7 + 0x2E0 x4 + 0x2E8 x5 + 0x2F0 x2 + 0x2F8 x3 + 0x300 x0 + 0x308 x1 + 0x310 x29 + 0x318 x30 + + + +6. Improving Performance + +The distribution version of ThreadX SMP is built without any compiler optimizations. +This makes it easy to debug because you can trace or set breakpoints inside of +ThreadX SMP itself. Of course, this costs some performance. To make it run faster, +you can change the project settings to the desired compiler optimization level. + +In addition, you can eliminate the ThreadX SMP basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX SMP provides complete and high-performance interrupt handling for Cortex-A35 +targets. Interrupts handlers for the 64-bit mode of the Cortex-A35 have the following +format: + + .global irq_handler +irq_handler: + MSR SPSel, 0 + STP x29, x30, [sp, #-16]! + BL _tx_thread_context_save + + /* Your ISR call goes here! */ + BL application_isr_handler + + B _tx_thread_context_restore + +By default, ThreadX SMP assumes EL3 level of execution. Running and taking exceptions in EL1 +and EL2 can be done by simply building the ThreadX library with either EL1 or EL2 defined. + + +8. ThreadX SMP Timer Interrupt + +ThreadX SMP requires a periodic interrupt source to manage all time-slicing, thread sleeps, +timeouts, and application timers. Without such a timer interrupt source, these services +are not functional. However, all other ThreadX services are operational without a +periodic timer source. + + +9. ARM FP Support + +By default, FP support is disabled for each thread. If saving the context of the FP registers +is needed, the following API call must be made from the context of the application thread - before +the FP usage: + +void tx_thread_fp_enable(void); + +After this API is called in the application, FP registers will be saved/restored for this thread if it +is preempted via an interrupt. All other suspension of the this thread will not require the FP registers +to be saved/restored. + +To disable FP register context saving, simply call the following API: + +void tx_thread_fp_disable(void); + + +10. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +09-30-2020 Initial ThreadX 6.1 version for Cortex-A35 using AC6 tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_initialize_low_level.S b/ports_smp/cortex_a35_smp/ac6/src/tx_initialize_low_level.S new file mode 100644 index 00000000..fd95aae8 --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_initialize_low_level.S @@ -0,0 +1,114 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-A35-SMP/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_initialize_low_level(VOID) +{ */ + .global _tx_initialize_low_level + .type _tx_initialize_low_level, @function +_tx_initialize_low_level: + + MSR DAIFSet, 0x3 // Lockout interrupts + + + /* Save the system stack pointer. */ + /* _tx_thread_system_stack_ptr = (VOID_PTR) (sp); */ + + LDR x0, =_tx_thread_system_stack_ptr // Pickup address of system stack ptr + MOV x1, sp // Pickup SP + SUB x1, x1, #15 // + BIC x1, x1, #0xF // Get 16-bit alignment + STR x1, [x0] // Store system stack + + /* Save the first available memory address. */ + /* _tx_initialize_unused_memory = (VOID_PTR) Image$$HEAP$$ZI$$Limit; */ + + LDR x0, =_tx_initialize_unused_memory // Pickup address of unused memory ptr + LDR x1, =heap_limit // Pickup unused memory address - A free + LDR x1, [x1] // memory section must be setup after the + // heap section. + STR x1, [x0] // Store unused memory address + + /* Done, return to caller. */ + + RET // Return to caller +/* } */ + + .align 3 +heap_limit: + .quad (Image$$TOP_OF_RAM$$ZI$$Limit) + diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_context_restore.S b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_context_restore.S new file mode 100644 index 00000000..1e24e169 --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_context_restore.S @@ -0,0 +1,393 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + +/* Include macros for modifying the wait list. */ +#include "tx_thread_smp_protection_wait_list_macros.h" + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore Cortex-A35-SMP/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores the interrupt context if it is processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_restore(VOID) +{ */ + .global _tx_thread_context_restore + .type _tx_thread_context_restore, @function +_tx_thread_context_restore: + + /* Lockout interrupts. */ + + MSR DAIFSet, 0x3 // Lockout interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR exit function to indicate an ISR is complete. */ + + BL _tx_execution_isr_exit // Call the ISR exit function +#endif + + /* Pickup the CPU ID. */ + + MRS x8, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x2, x8, #8, #8 // Isolate cluster ID +#endif + UBFX x8, x8, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x8, x8, x2, LSL #2 // Calculate CPU ID +#endif + + /* Determine if interrupts are nested. */ + /* if (--_tx_thread_system_state) + { */ + + LDR x3, =_tx_thread_system_state // Pickup address of system state var + LDR w2, [x3, x8, LSL #2] // Pickup system state + SUB w2, w2, #1 // Decrement the counter + STR w2, [x3, x8, LSL #2] // Store the counter + CMP w2, #0 // Was this the first interrupt? + BEQ __tx_thread_not_nested_restore // If so, not a nested restore + + /* Interrupts are nested. */ + + /* Just recover the saved registers and return to the point of + interrupt. */ + + LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL +#ifdef EL1 + MSR SPSR_EL1, x4 // Setup SPSR for return + MSR ELR_EL1, x5 // Setup point of interrupt +#else +#ifdef EL2 + MSR SPSR_EL2, x4 // Setup SPSR for return + MSR ELR_EL2, x5 // Setup point of interrupt +#else + MSR SPSR_EL3, x4 // Setup SPSR for return + MSR ELR_EL3, x5 // Setup point of interrupt +#endif +#endif + LDP x18, x19, [sp], #16 // Recover x18, x19 + LDP x16, x17, [sp], #16 // Recover x16, x17 + LDP x14, x15, [sp], #16 // Recover x14, x15 + LDP x12, x13, [sp], #16 // Recover x12, x13 + LDP x10, x11, [sp], #16 // Recover x10, x11 + LDP x8, x9, [sp], #16 // Recover x8, x9 + LDP x6, x7, [sp], #16 // Recover x6, x7 + LDP x4, x5, [sp], #16 // Recover x4, x5 + LDP x2, x3, [sp], #16 // Recover x2, x3 + LDP x0, x1, [sp], #16 // Recover x0, x1 + LDP x29, x30, [sp], #16 // Recover x29, x30 + ERET // Return to point of interrupt + + /* } */ +__tx_thread_not_nested_restore: + + /* Determine if a thread was interrupted and no preemption is required. */ + /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) + || (_tx_thread_preempt_disable)) + { */ + + LDR x1, =_tx_thread_current_ptr // Pickup address of current thread ptr + LDR x0, [x1, x8, LSL #3] // Pickup actual current thread pointer + CMP x0, #0 // Is it NULL? + BEQ __tx_thread_idle_system_restore // Yes, idle system was interrupted + LDR x3, =_tx_thread_execute_ptr // Pickup address of execute thread ptr + LDR x2, [x3, x8, LSL #3] // Pickup actual execute thread pointer + CMP x0, x2 // Is the same thread highest priority? + BEQ __tx_thread_no_preempt_restore // Same thread in the execute list, + // no preemption needs to happen + LDR x3, =_tx_thread_smp_protection // Build address to protection structure + LDR w3, [x3, #4] // Pickup the owning core + CMP w3, w8 // Is it this core? + BNE __tx_thread_preempt_restore // No, proceed to preempt thread + + LDR x3, =_tx_thread_preempt_disable // Pickup preempt disable address + LDR w2, [x3, #0] // Pickup actual preempt disable flag + CMP w2, #0 // Is it set? + BEQ __tx_thread_preempt_restore // No, okay to preempt this thread + +__tx_thread_no_preempt_restore: + + /* Restore interrupted thread or ISR. */ + + /* Pickup the saved stack pointer. */ + /* sp = _tx_thread_current_ptr -> tx_thread_stack_ptr; */ + + LDR x4, [x0, #8] // Switch to thread stack pointer + MOV sp, x4 // + + /* Recover the saved context and return to the point of interrupt. */ + + LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL1 +#ifdef EL1 + MSR SPSR_EL1, x4 // Setup SPSR for return + MSR ELR_EL1, x5 // Setup point of interrupt +#else +#ifdef EL2 + MSR SPSR_EL2, x4 // Setup SPSR for return + MSR ELR_EL2, x5 // Setup point of interrupt +#else + MSR SPSR_EL3, x4 // Setup SPSR for return + MSR ELR_EL3, x5 // Setup point of interrupt +#endif +#endif + LDP x18, x19, [sp], #16 // Recover x18, x19 + LDP x16, x17, [sp], #16 // Recover x16, x17 + LDP x14, x15, [sp], #16 // Recover x14, x15 + LDP x12, x13, [sp], #16 // Recover x12, x13 + LDP x10, x11, [sp], #16 // Recover x10, x11 + LDP x8, x9, [sp], #16 // Recover x8, x9 + LDP x6, x7, [sp], #16 // Recover x6, x7 + LDP x4, x5, [sp], #16 // Recover x4, x5 + LDP x2, x3, [sp], #16 // Recover x2, x3 + LDP x0, x1, [sp], #16 // Recover x0, x1 + LDP x29, x30, [sp], #16 // Recover x29, x30 + ERET // Return to point of interrupt + + /* } + else + { */ +__tx_thread_preempt_restore: + + /* Was the thread being preempted waiting for the lock? */ + /* if (_tx_thread_smp_protect_wait_counts[this_core] != 0) + { */ + + LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list + LDR w3, [x2, x8, LSL #2] // Load waiting value for this core + CMP w3, #0 + BEQ _nobody_waiting_for_lock // Is the core waiting for the lock? + + /* Do we not have the lock? This means the ISR never got the inter-core lock. */ + /* if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core) + { */ + + LDR x2, =_tx_thread_smp_protection // Load address of protection structure + LDR w3, [x2, #4] // Pickup the owning core + CMP w8, w3 // Compare our core to the owning core + BEQ _this_core_has_lock // Do we have the lock? + + /* We don't have the lock. This core should be in the list. Remove it. */ + /* _tx_thread_smp_protect_wait_list_remove(this_core); */ + + _tx_thread_smp_protect_wait_list_remove // Call macro to remove core from the list + B _nobody_waiting_for_lock // Leave + + /* } + else + { */ + /* We have the lock. This means the ISR got the inter-core lock, but + never released it because it saw that there was someone waiting. + Note this core is not in the list. */ + +_this_core_has_lock: + + /* We're no longer waiting. Note that this should be zero since this happens during thread preemption. */ + /* _tx_thread_smp_protect_wait_counts[core]--; */ + + LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list + LDR w3, [x2, x8, LSL #2] // Load waiting value for this core + SUB w3, w3, #1 // Decrement waiting value. Should be zero now + STR w3, [x2, x8, LSL #2] // Store new waiting value + + /* Now release the inter-core lock. */ + + /* Set protected core as invalid. */ + /* _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF; */ + + LDR x2, =_tx_thread_smp_protection // Load address of protection structure + MOV w3, #0xFFFFFFFF // Build invalid value + STR w3, [x2, #4] // Mark the protected core as invalid + DMB ISH // Ensure that accesses to shared resource have completed + + /* Release protection. */ + /* _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0; */ + + MOV w3, #0 // Build release protection value + STR w3, [x2, #0] // Release the protection + DSB ISH // To ensure update of the protection occurs before other CPUs awake + + /* Wake up waiting processors. Note interrupts are already enabled. */ + +#ifdef TX_ENABLE_WFE + SEV // Send event to other CPUs +#endif + + /* } + } */ + +_nobody_waiting_for_lock: + + LDR x4, [x0, #8] // Switch to thread stack pointer + MOV sp, x4 // + + LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL1 + STP x20, x21, [sp, #-16]! // Save x20, x21 + STP x22, x23, [sp, #-16]! // Save x22, x23 + STP x24, x25, [sp, #-16]! // Save x24, x25 + STP x26, x27, [sp, #-16]! // Save x26, x27 + STP x28, x29, [sp, #-16]! // Save x28, x29 +#ifdef ENABLE_ARM_FP + LDR w3, [x0, #268] // Pickup FP enable flag + CMP w3, #0 // Is FP enabled? + BEQ _skip_fp_save // No, skip FP save + STP q0, q1, [sp, #-32]! // Save q0, q1 + STP q2, q3, [sp, #-32]! // Save q2, q3 + STP q4, q5, [sp, #-32]! // Save q4, q5 + STP q6, q7, [sp, #-32]! // Save q6, q7 + STP q8, q9, [sp, #-32]! // Save q8, q9 + STP q10, q11, [sp, #-32]! // Save q10, q11 + STP q12, q13, [sp, #-32]! // Save q12, q13 + STP q14, q15, [sp, #-32]! // Save q14, q15 + STP q16, q17, [sp, #-32]! // Save q16, q17 + STP q18, q19, [sp, #-32]! // Save q18, q19 + STP q20, q21, [sp, #-32]! // Save q20, q21 + STP q22, q23, [sp, #-32]! // Save q22, q23 + STP q24, q25, [sp, #-32]! // Save q24, q25 + STP q26, q27, [sp, #-32]! // Save q26, q27 + STP q28, q29, [sp, #-32]! // Save q28, q29 + STP q30, q31, [sp, #-32]! // Save q30, q31 + MRS x2, FPSR // Pickup FPSR + MRS x3, FPCR // Pickup FPCR + STP x2, x3, [sp, #-16]! // Save FPSR, FPCR +_skip_fp_save: +#endif + STP x4, x5, [sp, #-16]! // Save x4 (SPSR_EL3), x5 (ELR_E3) + + MOV x3, sp // Move sp into x3 + STR x3, [x0, #8] // Save stack pointer in thread control + // block + LDR x3, =_tx_thread_system_stack_ptr // Pickup address of system stack + LDR x4, [x3, x8, LSL #3] // Pickup system stack pointer + MOV sp, x4 // Setup system stack pointer + + + /* Save the remaining time-slice and disable it. */ + /* if (_tx_timer_time_slice) + { */ + + LDR x3, =_tx_timer_time_slice // Pickup time-slice variable address + LDR w2, [x3, x8, LSL #2] // Pickup time-slice + CMP w2, #0 // Is it active? + BEQ __tx_thread_dont_save_ts // No, don't save it + + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + STR w2, [x0, #36] // Save thread's time-slice + MOV w2, #0 // Clear value + STR w2, [x3, x8, LSL #2] // Disable global time-slice flag + + /* } */ +__tx_thread_dont_save_ts: + + + /* Clear the current task pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + MOV x2, #0 // NULL value + STR x2, [x1, x8, LSL #3] // Clear current thread pointer + + /* Set bit indicating this thread is ready for execution. */ + + MOV x2, #1 // Build ready flag + DMB ISH // Ensure that accesses to shared resource have completed + STR w2, [x0, #260] // Set thread's ready flag + + /* Return to the scheduler. */ + /* _tx_thread_schedule(); */ + + /* } */ + +__tx_thread_idle_system_restore: + + /* Just return back to the scheduler! */ + + LDR x1, =_tx_thread_schedule // Build address for _tx_thread_schedule +#ifdef EL1 + MSR ELR_EL1, x1 // Setup point of interrupt +// MOV x1, #0x4 // Setup EL1 return +// MSR spsr_el1, x1 // Move into SPSR +#else +#ifdef EL2 + MSR ELR_EL2, x1 // Setup point of interrupt +// MOV x1, #0x8 // Setup EL2 return +// MSR spsr_el2, x1 // Move into SPSR +#else + MSR ELR_EL3, x1 // Setup point of interrupt +// MOV x1, #0xC // Setup EL3 return +// MSR spsr_el3, x1 // Move into SPSR +#endif +#endif + ERET // Return to scheduler +/* } */ + + diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_context_save.S b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_context_save.S new file mode 100644 index 00000000..5939a41c --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_context_save.S @@ -0,0 +1,249 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save Cortex-A35-SMP/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_save(VOID) +{ */ + .global _tx_thread_context_save + .type _tx_thread_context_save, @function +_tx_thread_context_save: + + /* Upon entry to this routine, it is assumed that IRQ/FIQ interrupts are locked + out, x29 (frame pointer), x30 (link register) are saved, we are in the proper EL, + and all other registers are intact. */ + + /* Check for a nested interrupt condition. */ + /* if (_tx_thread_system_state++) + { */ + + STP x0, x1, [sp, #-16]! // Save x0, x1 + STP x2, x3, [sp, #-16]! // Save x2, x3 + + /* Pickup the CPU ID. */ + + MRS x1, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x2, x1, #8, #8 // Isolate cluster ID +#endif + UBFX x1, x1, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x1, x1, x2, LSL #2 // Calculate CPU ID +#endif + + LDR x3, =_tx_thread_system_state // Pickup address of system state var + LDR w2, [x3, x1, LSL #2] // Pickup system state + CMP w2, #0 // Is this the first interrupt? + BEQ __tx_thread_not_nested_save // Yes, not a nested context save + + /* Nested interrupt condition. */ + + ADD w2, w2, #1 // Increment the nested interrupt counter + STR w2, [x3, x1, LSL #2] // Store it back in the variable + + /* Save the rest of the scratch registers on the stack and return to the + calling ISR. */ + + STP x4, x5, [sp, #-16]! // Save x4, x5 + STP x6, x7, [sp, #-16]! // Save x6, x7 + STP x8, x9, [sp, #-16]! // Save x8, x9 + STP x10, x11, [sp, #-16]! // Save x10, x11 + STP x12, x13, [sp, #-16]! // Save x12, x13 + STP x14, x15, [sp, #-16]! // Save x14, x15 + STP x16, x17, [sp, #-16]! // Save x16, x17 + STP x18, x19, [sp, #-16]! // Save x18, x19 +#ifdef EL1 + MRS x0, SPSR_EL1 // Pickup SPSR + MRS x1, ELR_EL1 // Pickup ELR (point of interrupt) +#else +#ifdef EL2 + MRS x0, SPSR_EL2 // Pickup SPSR + MRS x1, ELR_EL2 // Pickup ELR (point of interrupt) +#else + MRS x0, SPSR_EL3 // Pickup SPSR + MRS x1, ELR_EL3 // Pickup ELR (point of interrupt) +#endif +#endif + STP x0, x1, [sp, #-16]! // Save SPSR, ELR + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + STP x29, x30, [sp, #-16]! // Save x29, x30 + BL _tx_execution_isr_enter // Call the ISR enter function + LDP x29, x30, [sp], #16 // Recover x29, x30 +#endif + + /* Return to the ISR. */ + + RET // Return to ISR + +__tx_thread_not_nested_save: + /* } */ + + /* Otherwise, not nested, check to see if a thread was running. */ + /* else if (_tx_thread_current_ptr) + { */ + + ADD w2, w2, #1 // Increment the interrupt counter + STR w2, [x3, x1, LSL #2] // Store it back in the variable + LDR x2, =_tx_thread_current_ptr // Pickup address of current thread ptr + LDR x0, [x2, x1, LSL #3] // Pickup current thread pointer + CMP x0, #0 // Is it NULL? + BEQ __tx_thread_idle_system_save // If so, interrupt occurred in + // scheduling loop - nothing needs saving! + + /* Save minimal context of interrupted thread. */ + + STP x4, x5, [sp, #-16]! // Save x4, x5 + STP x6, x7, [sp, #-16]! // Save x6, x7 + STP x8, x9, [sp, #-16]! // Save x8, x9 + STP x10, x11, [sp, #-16]! // Save x10, x11 + STP x12, x13, [sp, #-16]! // Save x12, x13 + STP x14, x15, [sp, #-16]! // Save x14, x15 + STP x16, x17, [sp, #-16]! // Save x16, x17 + STP x18, x19, [sp, #-16]! // Save x18, x19 +#ifdef EL1 + MRS x4, SPSR_EL1 // Pickup SPSR + MRS x5, ELR_EL1 // Pickup ELR (point of interrupt) +#else +#ifdef EL2 + MRS x4, SPSR_EL2 // Pickup SPSR + MRS x5, ELR_EL2 // Pickup ELR (point of interrupt) +#else + MRS x4, SPSR_EL3 // Pickup SPSR + MRS x5, ELR_EL3 // Pickup ELR (point of interrupt) +#endif +#endif + STP x4, x5, [sp, #-16]! // Save SPSR, ELR + + /* Save the current stack pointer in the thread's control block. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ + + MOV x4, sp // + STR x4, [x0, #8] // Save thread stack pointer + + /* Switch to the system stack. */ + /* sp = _tx_thread_system_stack_ptr; */ + + LDR x3, =_tx_thread_system_stack_ptr // Pickup address of system stack + MRS x1, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x2, x1, #8, #8 // Isolate cluster ID +#endif + UBFX x1, x1, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x1, x1, x2, LSL #2 // Calculate CPU ID +#endif + + LDR x4, [x3, x1, LSL #3] // Pickup system stack pointer + MOV sp, x4 // Setup system stack pointer + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + STP x29, x30, [sp, #-16]! // Save x29, x30 + BL _tx_execution_isr_enter // Call the ISR enter function + LDP x29, x30, [sp], #16 // Recover x29, x30 +#endif + + RET // Return to caller + + /* } + else + { */ + +__tx_thread_idle_system_save: + + /* Interrupt occurred in the scheduling loop. */ + + /* Not much to do here, just adjust the stack pointer, and return to IRQ + processing. */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + STP x29, x30, [sp, #-16]! // Save x29, x30 + BL _tx_execution_isr_enter // Call the ISR enter function + LDP x29, x30, [sp], #16 // Recover x29, x30 +#endif + + ADD sp, sp, #48 // Recover saved registers + RET // Continue IRQ processing + + /* } +} */ + + diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_fp_disable.c b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_fp_disable.c new file mode 100644 index 00000000..bbb9d50a --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_fp_disable.c @@ -0,0 +1,95 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fp_disable Cortex-A35-SMP/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function disables the FP for the currently executing thread. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_fp_disable(VOID) +{ + +TX_THREAD *thread_ptr; +ULONG system_state; + + + /* Pickup the current thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr); + + /* Get the system state. */ + system_state = TX_THREAD_GET_SYSTEM_STATE(); + + /* Make sure it is not NULL. */ + if (thread_ptr != TX_NULL) + { + + /* Thread is running... make sure the call is from the thread context. */ + if (system_state == 0) + { + + /* Yes, now set the FP enable flag to false in the TX_THREAD structure. */ + thread_ptr -> tx_thread_fp_enable = TX_FALSE; + } + } +} + diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_fp_enable.c b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_fp_enable.c new file mode 100644 index 00000000..5b064f22 --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_fp_enable.c @@ -0,0 +1,95 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fp_enable Cortex-A35-SMP/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function enabled the FP for the currently executing thread. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_fp_enable(VOID) +{ + +TX_THREAD *thread_ptr; +ULONG system_state; + + + /* Pickup the current thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr); + + /* Get the system state. */ + system_state = TX_THREAD_GET_SYSTEM_STATE(); + + /* Make sure it is not NULL. */ + if (thread_ptr != TX_NULL) + { + + /* Thread is running... make sure the call is from the thread context. */ + if (system_state == 0) + { + + /* Yes, now setup the FP enable flag in the TX_THREAD structure. */ + thread_ptr -> tx_thread_fp_enable = TX_TRUE; + } + } +} + diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..eb1007e4 --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_interrupt_control.S @@ -0,0 +1,89 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/*#define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control Cortex-A35-SMP/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_control(UINT new_posture) +{ */ + .global _tx_thread_interrupt_control + .type _tx_thread_interrupt_control, @function +_tx_thread_interrupt_control: + + /* Pickup current interrupt lockout posture. */ + + MRS x1, DAIF // Pickup current interrupt posture + + /* Apply the new interrupt posture. */ + + MSR DAIF, x0 // Set new interrupt posture + MOV x0, x1 // Setup return value + RET // Return to caller +/* } */ + diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_interrupt_disable.S new file mode 100644 index 00000000..f357d90d --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_interrupt_disable.S @@ -0,0 +1,87 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_disable Cortex-A35-SMP/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for disabling interrupts */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_disable(void) +{ */ + .global _tx_thread_interrupt_disable + .type _tx_thread_interrupt_disable, @function +_tx_thread_interrupt_disable: + + /* Pickup current interrupt lockout posture. */ + + MRS x0, DAIF // Pickup current interrupt lockout posture + + /* Mask interrupts. */ + + MSR DAIFSet, 0x3 // Lockout interrupts + RET // Return to caller +/* } */ + diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_interrupt_restore.S new file mode 100644 index 00000000..f9b49a89 --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_interrupt_restore.S @@ -0,0 +1,85 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_restore Cortex-A35-SMP/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for restoring interrupts to the state */ +/* returned by a previous _tx_thread_interrupt_disable call. */ +/* */ +/* INPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_restore(UINT old_posture) +{ */ + .global _tx_thread_interrupt_restore + .type _tx_thread_interrupt_restore, @function +_tx_thread_interrupt_restore: + + /* Restore the old interrupt posture. */ + + MSR DAIF, x0 // Setup the old posture + RET // Return to caller + +/* } */ + diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_schedule.S b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_schedule.S new file mode 100644 index 00000000..d5c75650 --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_schedule.S @@ -0,0 +1,307 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule Cortex-A35-SMP/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* _tx_thread_context_restore Restore thread's context */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_schedule(VOID) +{ */ + .global _tx_thread_schedule + .type _tx_thread_schedule, @function +_tx_thread_schedule: + + /* Enable interrupts. */ + + MSR DAIFClr, 0x3 // Enable interrupts + + /* Pickup the CPU ID. */ + + MRS x20, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x1, x20, #8, #8 // Isolate cluster ID +#endif + UBFX x20, x20, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x20, x20, x1, LSL #2 // Calculate CPU ID +#endif + + /* Wait for a thread to execute. */ + /* do + { */ + + LDR x1, =_tx_thread_execute_ptr // Address of thread execute ptr + +#ifdef TX_ENABLE_WFI +__tx_thread_schedule_loop: + MSR DAIFSet, 0x3 // Lockout interrupts + LDR x0, [x1, x20, LSL #3] // Pickup next thread to execute + CMP x0, #0 // Is it NULL? + BNE _tx_thread_schedule_thread // + MSR DAIFClr, 0x3 // Enable interrupts + WFI // + B __tx_thread_schedule_loop // Keep looking for a thread +_tx_thread_schedule_thread: +#else + MSR DAIFSet, 0x3 // Lockout interrupts + LDR x0, [x1, x20, LSL #3] // Pickup next thread to execute + CMP x0, #0 // Is it NULL? + BEQ _tx_thread_schedule // Keep looking for a thread +#endif + + /* } + while(_tx_thread_execute_ptr == TX_NULL); */ + + /* Get the lock for accessing the thread's ready bit. */ + + MOV w2, #280 // Build offset to the lock + ADD x2, x0, x2 // Get the address to the lock + LDAXR w3, [x2] // Pickup the lock value + CMP w3, #0 // Check if it's available + BNE _tx_thread_schedule // No, lock not available + MOV w3, #1 // Build the lock set value + STXR w4, w3, [x2] // Try to get the lock + CMP w4, #0 // Check if we got the lock + BNE _tx_thread_schedule // No, another core got it first + DMB ISH // Ensure write to lock completes + + /* Now make sure the thread's ready bit is set. */ + + LDR w3, [x0, #260] // Pickup the thread ready bit + CMP w3, #0 // Is it set? + BNE _tx_thread_ready_for_execution // Yes, schedule the thread + + /* The ready bit isn't set. Release the lock and jump back to the scheduler. */ + + MOV w3, #0 // Build clear value + STR w3, [x2] // Release the lock + DMB ISH // Ensure write to lock completes + B _tx_thread_schedule // Jump back to the scheduler + +_tx_thread_ready_for_execution: + + /* We have a thread to execute. */ + + /* Clear the ready bit and release the lock. */ + + MOV w3, #0 // Build clear value + STR w3, [x0, #260] // Store it back in the thread control block + DMB ISH + MOV w3, #0 // Build clear value for the lock + STR w3, [x2] // Release the lock + DMB ISH + + /* Setup the current thread pointer. */ + /* _tx_thread_current_ptr = _tx_thread_execute_ptr; */ + + LDR x2, =_tx_thread_current_ptr // Pickup address of current thread + STR x0, [x2, x20, LSL #3] // Setup current thread pointer + + LDR x1, [x1, x20, LSL #3] // Reload the execute pointer + CMP w0, w1 // Did it change? + BEQ _execute_pointer_did_not_change // If not, skip handling + + /* In the time between reading the execute pointer and assigning + it to the current pointer, the execute pointer was changed by + some external code. If the current pointer was still null when + the external code checked if a core preempt was necessary, then + it wouldn't have done it and a preemption will be missed. To + handle this, undo some things and jump back to the scheduler so + it can schedule the new thread. */ + + MOV w1, #0 // Build clear value + STR x1, [x2, x20, LSL #3] // Clear current thread pointer + + MOV w1, #1 // Build set value + STR w1, [x0, #260] // Re-set the ready bit + DMB ISH // + + B _tx_thread_schedule // Jump back to the scheduler to schedule the new thread + +_execute_pointer_did_not_change: + /* Increment the run count for this thread. */ + /* _tx_thread_current_ptr -> tx_thread_run_count++; */ + + LDR w2, [x0, #4] // Pickup run counter + LDR w3, [x0, #36] // Pickup time-slice for this thread + ADD w2, w2, #1 // Increment thread run-counter + STR w2, [x0, #4] // Store the new run counter + + /* Setup time-slice, if present. */ + /* _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; */ + + LDR x2, =_tx_timer_time_slice // Pickup address of time slice + // variable + LDR x4, [x0, #8] // Switch stack pointers + MOV sp, x4 // + STR w3, [x2, x20, LSL #2] // Setup time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread entry function to indicate the thread is executing. */ + + MOV x19, x0 // Save x0 + BL _tx_execution_thread_enter // Call the thread execution enter function + MOV x0, x19 // Restore x0 +#endif + + /* Switch to the thread's stack. */ + /* sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; */ + + /* Determine if an interrupt frame or a synchronous task suspension frame + is present. */ + + LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL1 + CMP x5, #0 // Check for synchronous context switch (ELR_EL1 = NULL) + BEQ _tx_solicited_return +#ifdef EL1 + MSR SPSR_EL1, x4 // Setup SPSR for return + MSR ELR_EL1, x5 // Setup point of interrupt +#else +#ifdef EL2 + MSR SPSR_EL2, x4 // Setup SPSR for return + MSR ELR_EL2, x5 // Setup point of interrupt +#else + MSR SPSR_EL3, x4 // Setup SPSR for return + MSR ELR_EL3, x5 // Setup point of interrupt +#endif +#endif +#ifdef ENABLE_ARM_FP + LDR w1, [x0, #268] // Pickup FP enable flag + CMP w1, #0 // Is FP enabled? + BEQ _skip_interrupt_fp_restore // No, skip FP restore + LDP x0, x1, [sp], #16 // Pickup FPSR, FPCR + MSR FPSR, x0 // Recover FPSR + MSR FPCR, x1 // Recover FPCR + LDP q30, q31, [sp], #32 // Recover q30, q31 + LDP q28, q29, [sp], #32 // Recover q28, q29 + LDP q26, q27, [sp], #32 // Recover q26, q27 + LDP q24, q25, [sp], #32 // Recover q24, q25 + LDP q22, q23, [sp], #32 // Recover q22, q23 + LDP q20, q21, [sp], #32 // Recover q20, q21 + LDP q18, q19, [sp], #32 // Recover q18, q19 + LDP q16, q17, [sp], #32 // Recover q16, q17 + LDP q14, q15, [sp], #32 // Recover q14, q15 + LDP q12, q13, [sp], #32 // Recover q12, q13 + LDP q10, q11, [sp], #32 // Recover q10, q11 + LDP q8, q9, [sp], #32 // Recover q8, q9 + LDP q6, q7, [sp], #32 // Recover q6, q7 + LDP q4, q5, [sp], #32 // Recover q4, q5 + LDP q2, q3, [sp], #32 // Recover q2, q3 + LDP q0, q1, [sp], #32 // Recover q0, q1 +_skip_interrupt_fp_restore: +#endif + LDP x28, x29, [sp], #16 // Recover x28 + LDP x26, x27, [sp], #16 // Recover x26, x27 + LDP x24, x25, [sp], #16 // Recover x24, x25 + LDP x22, x23, [sp], #16 // Recover x22, x23 + LDP x20, x21, [sp], #16 // Recover x20, x21 + LDP x18, x19, [sp], #16 // Recover x18, x19 + LDP x16, x17, [sp], #16 // Recover x16, x17 + LDP x14, x15, [sp], #16 // Recover x14, x15 + LDP x12, x13, [sp], #16 // Recover x12, x13 + LDP x10, x11, [sp], #16 // Recover x10, x11 + LDP x8, x9, [sp], #16 // Recover x8, x9 + LDP x6, x7, [sp], #16 // Recover x6, x7 + LDP x4, x5, [sp], #16 // Recover x4, x5 + LDP x2, x3, [sp], #16 // Recover x2, x3 + LDP x0, x1, [sp], #16 // Recover x0, x1 + LDP x29, x30, [sp], #16 // Recover x29, x30 + ERET // Return to point of interrupt + +_tx_solicited_return: + +#ifdef ENABLE_ARM_FP + LDR w1, [x0, #268] // Pickup FP enable flag + CMP w1, #0 // Is FP enabled? + BEQ _skip_solicited_fp_restore // No, skip FP restore + LDP x0, x1, [sp], #16 // Pickup FPSR, FPCR + MSR FPSR, x0 // Recover FPSR + MSR FPCR, x1 // Recover FPCR + LDP q14, q15, [sp], #32 // Recover q14, q15 + LDP q12, q13, [sp], #32 // Recover q12, q13 + LDP q10, q11, [sp], #32 // Recover q10, q11 + LDP q8, q9, [sp], #32 // Recover q8, q9 +_skip_solicited_fp_restore: +#endif + LDP x27, x28, [sp], #16 // Recover x27, x28 + LDP x25, x26, [sp], #16 // Recover x25, x26 + LDP x23, x24, [sp], #16 // Recover x23, x24 + LDP x21, x22, [sp], #16 // Recover x21, x22 + LDP x19, x20, [sp], #16 // Recover x19, x20 + LDP x29, x30, [sp], #16 // Recover x29, x30 + MSR DAIF, x4 // Recover DAIF + RET // Return to caller +/* } */ + + diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_core_get.S new file mode 100644 index 00000000..4243df5f --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_core_get.S @@ -0,0 +1,89 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_core_get Cortex-A35-SMP/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets the currently running core number and returns it.*/ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* Core ID */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Source */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_core_get + .type _tx_thread_smp_core_get, @function +_tx_thread_smp_core_get: + MRS x0, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x1, x0, #8, #8 // Isolate cluster ID +#endif + UBFX x0, x0, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x0, x0, x1, LSL #2 // Calculate CPU ID +#endif + RET + + diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_core_preempt.S new file mode 100644 index 00000000..a24a5ed7 --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_core_preempt.S @@ -0,0 +1,87 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_core_preempt Cortex-A35-SMP/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function preempts the specified core in situations where the */ +/* thread corresponding to this core is no longer ready or when the */ +/* core must be used for a higher-priority thread. If the specified is */ +/* the current core, this processing is skipped since the will give up */ +/* control subsequently on its own. */ +/* */ +/* INPUT */ +/* */ +/* core The core to preempt */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Source */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_core_preempt + .type _tx_thread_smp_core_preempt, @function +_tx_thread_smp_core_preempt: + DSB ISH + MOV x2, #0x1 // + LSL x2, x2, x0 // Shift by the core ID + MSR ICC_SGI1R_EL1, x2 // Issue inter-core interrupt + RET + diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_current_state_get.S new file mode 100644 index 00000000..740bc209 --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_current_state_get.S @@ -0,0 +1,95 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_current_state_get Cortex-A35-SMP/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is gets the current state of the calling core. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_current_state_get + .type _tx_thread_smp_current_state_get, @function +_tx_thread_smp_current_state_get: + + MRS x1, DAIF // Pickup current interrupt posture + MSR DAIFSet, 0x3 // Lockout interrupts + MRS x2, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x3, x2, #8, #8 // Isolate cluster ID +#endif + UBFX x2, x2, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x2, x2, x3, LSL #2 // Calculate CPU ID +#endif + LDR x3, =_tx_thread_system_state // Pickup the base of the current system state array + LDR w0, [x3, x2, LSL #2] // Pickup the current system state for this core + MSR DAIF, x1 // Restore interrupt posture + RET + + diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_current_thread_get.S new file mode 100644 index 00000000..8bfdb219 --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_current_thread_get.S @@ -0,0 +1,94 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_current_thread_get Cortex-A35-SMP/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is gets the current thread of the calling core. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_current_thread_get + .type _tx_thread_smp_current_thread_get, @function +_tx_thread_smp_current_thread_get: + + MRS x1, DAIF // Pickup current interrupt posture + MSR DAIFSet, 0x3 // Lockout interrupts + MRS x2, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x3, x2, #8, #8 // Isolate cluster ID +#endif + UBFX x2, x2, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x2, x2, x3, LSL #2 // Calculate CPU ID +#endif + LDR x3, =_tx_thread_current_ptr // Pickup the base of the current thread pointer array + LDR x0, [x3, x2, LSL #3] // Pickup the current thread pointer for this core + MSR DAIF, x1 // Restore interrupt posture + RET + diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_initialize_wait.S new file mode 100644 index 00000000..faaea401 --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_initialize_wait.S @@ -0,0 +1,143 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_initialize_wait Cortex-A35-SMP/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is the place where additional cores wait until */ +/* initialization is complete before they enter the thread scheduling */ +/* loop. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* Hardware */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_initialize_wait + .type _tx_thread_smp_initialize_wait, @function +_tx_thread_smp_initialize_wait: + + /* Lockout interrupts. */ + + MSR DAIFSet, 0x3 // Lockout interrupts + + /* Pickup the Core ID. */ + + MRS x2, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x3, x2, #8, #8 // Isolate cluster ID +#endif + UBFX x2, x2, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x2, x2, x3, LSL #2 // Calculate CPU ID +#endif + + /* Make sure the system state for this core is TX_INITIALIZE_IN_PROGRESS before we check the release + flag. */ + + LDR w1, =0xF0F0F0F0 // Build TX_INITIALIZE_IN_PROGRESS flag + LDR x3, =_tx_thread_system_state // Pickup the base of the current system state array +wait_for_initialize: + LDR w0, [x3, x2, LSL #2] // Pickup the current system state for this core + CMP w0, w1 // Make sure the TX_INITIALIZE_IN_PROGRESS flag is set + BNE wait_for_initialize // Not equal, just spin here + + /* Save the system stack pointer for this core. */ + + LDR x0, =_tx_thread_system_stack_ptr // Pickup address of system stack ptr + MOV x1, sp // Pickup SP + SUB x1, x1, #15 // + BIC x1, x1, #0xF // Get 16-bit alignment + STR x1, [x0, x2, LSL #3] // Store system stack pointer + + + /* Pickup the release cores flag. */ + + LDR x4, =_tx_thread_smp_release_cores_flag // Build address of release cores flag +wait_for_release: + LDR w0, [x4, #0] // Pickup the flag + CMP w0, #0 // Is it set? + BEQ wait_for_release // Wait for the flag to be set + + /* Core 0 has released this core. */ + + /* Clear this core's system state variable. */ + + MOV x0, #0 // Build clear value + STR w0, [x3, x2, LSL #2] // Set the current system state for this core to zero + + /* Now wait for core 0 to finish it's initialization. */ + +core_0_wait_loop: + LDR w0, [x3, #0] // Pickup the current system state for core 0 + CMP w0, #0 // Is it 0? + BNE core_0_wait_loop // No, keep waiting for core 0 to finish its initialization + + /* Initialization is complete, enter the scheduling loop! */ + + B _tx_thread_schedule // Enter the scheduling loop for this core + + RET + diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_low_level_initialize.S new file mode 100644 index 00000000..d038a26a --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_low_level_initialize.S @@ -0,0 +1,80 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_low_level_initialize Cortex-A35-SMP/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function performs low-level initialization of the booting */ +/* core. */ +/* */ +/* INPUT */ +/* */ +/* number_of_cores Number of cores */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_high_level ThreadX high-level init */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_low_level_initialize + .type _tx_thread_smp_low_level_initialize, @function +_tx_thread_smp_low_level_initialize: + + RET diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_protect.S b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_protect.S new file mode 100644 index 00000000..98cc9f95 --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_protect.S @@ -0,0 +1,364 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + +/* Include macros for modifying the wait list. */ +#include "tx_thread_smp_protection_wait_list_macros.h" + + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_protect Cortex-A35-SMP/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets protection for running inside the ThreadX */ +/* source. This is acomplished by a combination of a test-and-set */ +/* flag and periodically disabling interrupts. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* Previous Status Register */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Source */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_protect + .type _tx_thread_smp_protect, @function +_tx_thread_smp_protect: + + /* Disable interrupts so we don't get preempted. */ + + MRS x0, DAIF // Pickup current interrupt posture + MSR DAIFSet, 0x3 // Lockout interrupts + + /* Pickup the CPU ID. */ + + MRS x1, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x7, x1, #8, #8 // Isolate cluster ID +#endif + UBFX x1, x1, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x1, x1, x7, LSL #2 // Calculate CPU ID +#endif + + /* Do we already have protection? */ + /* if (this_core == _tx_thread_smp_protection.tx_thread_smp_protect_core) + { */ + + LDR x2, =_tx_thread_smp_protection // Build address to protection structure + LDR w3, [x2, #4] // Pickup the owning core + CMP w1, w3 // Is it not this core? + BNE _protection_not_owned // No, the protection is not already owned + + /* We already have protection. */ + + /* Increment the protection count. */ + /* _tx_thread_smp_protection.tx_thread_smp_protect_count++; */ + + LDR w3, [x2, #8] // Pickup ownership count + ADD w3, w3, #1 // Increment ownership count + STR w3, [x2, #8] // Store ownership count + DMB ISH + + B _return + +_protection_not_owned: + + /* Is the lock available? */ + /* if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0) + { */ + + LDAXR w3, [x2, #0] // Pickup the protection flag + CMP w3, #0 + BNE _start_waiting // No, protection not available + + /* Is the list empty? */ + /* if (_tx_thread_smp_protect_wait_list_head == _tx_thread_smp_protect_wait_list_tail) + { */ + + LDR x3, =_tx_thread_smp_protect_wait_list_head + LDR w3, [x3] + LDR x4, =_tx_thread_smp_protect_wait_list_tail + LDR w4, [x4] + CMP w3, w4 + BNE _list_not_empty + + /* Try to get the lock. */ + /* if (write_exclusive(&_tx_thread_smp_protection.tx_thread_smp_protect_in_force, 1) == SUCCESS) + { */ + + MOV w3, #1 // Build lock value + STXR w4, w3, [x2, #0] // Attempt to get the protection + CMP w4, #0 + BNE _start_waiting // Did it fail? + + /* We got the lock! */ + /* _tx_thread_smp_protect_lock_got(); */ + + DMB ISH // Ensure write to protection finishes + _tx_thread_smp_protect_lock_got // Call the lock got function + + B _return + +_list_not_empty: + + /* Are we at the front of the list? */ + /* if (this_core == _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head]) + { */ + + LDR x3, =_tx_thread_smp_protect_wait_list_head // Get the address of the head + LDR w3, [x3] // Get the value of the head + LDR x4, =_tx_thread_smp_protect_wait_list // Get the address of the list + LDR w4, [x4, x3, LSL #2] // Get the value at the head index + + CMP w1, w4 + BNE _start_waiting + + /* Is the lock still available? */ + /* if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0) + { */ + + LDR w3, [x2, #0] // Pickup the protection flag + CMP w3, #0 + BNE _start_waiting // No, protection not available + + /* Get the lock. */ + /* _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1; */ + + MOV w3, #1 // Build lock value + STR w3, [x2, #0] // Store lock value + DMB ISH // + + /* Got the lock. */ + /* _tx_thread_smp_protect_lock_got(); */ + + _tx_thread_smp_protect_lock_got + + /* Remove this core from the wait list. */ + /* _tx_thread_smp_protect_remove_from_front_of_list(); */ + + _tx_thread_smp_protect_remove_from_front_of_list + + B _return + +_start_waiting: + + /* For one reason or another, we didn't get the lock. */ + + /* Increment wait count. */ + /* _tx_thread_smp_protect_wait_counts[this_core]++; */ + + LDR x3, =_tx_thread_smp_protect_wait_counts // Load wait list counts + LDR w4, [x3, x1, LSL #2] // Load waiting value for this core + ADD w4, w4, #1 // Increment wait value + STR w4, [x3, x1, LSL #2] // Store new wait value + + /* Have we not added ourselves to the list yet? */ + /* if (_tx_thread_smp_protect_wait_counts[this_core] == 1) + { */ + + CMP w4, #1 + BNE _already_in_list0 // Is this core already waiting? + + /* Add ourselves to the list. */ + /* _tx_thread_smp_protect_wait_list_add(this_core); */ + + _tx_thread_smp_protect_wait_list_add // Call macro to add ourselves to the list + + /* } */ + +_already_in_list0: + + /* Restore interrupts. */ + + MSR DAIF, x0 // Restore interrupts + ISB // +#ifdef TX_ENABLE_WFE + WFE // Go into standby +#endif + + /* We do this until we have the lock. */ + /* while (1) + { */ + +_try_to_get_lock: + + /* Disable interrupts so we don't get preempted. */ + + MRS x0, DAIF // Pickup current interrupt posture + MSR DAIFSet, 0x3 // Lockout interrupts + + /* Pickup the CPU ID. */ + + MRS x1, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x7, x1, #8, #8 // Isolate cluster ID +#endif + UBFX x1, x1, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x1, x1, x7, LSL #2 // Calculate CPU ID +#endif + + /* Do we already have protection? */ + /* if (this_core == _tx_thread_smp_protection.tx_thread_smp_protect_core) + { */ + + LDR w3, [x2, #4] // Pickup the owning core + CMP w3, w1 // Is it this core? + BEQ _got_lock_after_waiting // Yes, the protection is already owned. This means + // an ISR preempted us and got protection + + /* } */ + + /* Are we at the front of the list? */ + /* if (this_core == _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head]) + { */ + + LDR x3, =_tx_thread_smp_protect_wait_list_head // Get the address of the head + LDR w3, [x3] // Get the value of the head + LDR x4, =_tx_thread_smp_protect_wait_list // Get the address of the list + LDR w4, [x4, x3, LSL #2] // Get the value at the head index + + CMP w1, w4 + BNE _did_not_get_lock + + /* Is the lock still available? */ + /* if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0) + { */ + + LDR w3, [x2, #0] // Pickup the protection flag + CMP w3, #0 + BNE _did_not_get_lock // No, protection not available + + /* Get the lock. */ + /* _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1; */ + + MOV w3, #1 // Build lock value + STR w3, [x2, #0] // Store lock value + DMB ISH // + + /* Got the lock. */ + /* _tx_thread_smp_protect_lock_got(); */ + + _tx_thread_smp_protect_lock_got + + /* Remove this core from the wait list. */ + /* _tx_thread_smp_protect_remove_from_front_of_list(); */ + + _tx_thread_smp_protect_remove_from_front_of_list + + B _got_lock_after_waiting + +_did_not_get_lock: + + /* For one reason or another, we didn't get the lock. */ + + /* Were we removed from the list? This can happen if we're a thread + and we got preempted. */ + /* if (_tx_thread_smp_protect_wait_counts[this_core] == 0) + { */ + + LDR x3, =_tx_thread_smp_protect_wait_counts // Load wait list counts + LDR w4, [x3, x1, LSL #2] // Load waiting value for this core + CMP w4, #0 + BNE _already_in_list1 // Is this core already in the list? + + /* Add ourselves to the list. */ + /* _tx_thread_smp_protect_wait_list_add(this_core); */ + + _tx_thread_smp_protect_wait_list_add // Call macro to add ourselves to the list + + /* Our waiting count was also reset when we were preempted. Increment it again. */ + /* _tx_thread_smp_protect_wait_counts[this_core]++; */ + + LDR x3, =_tx_thread_smp_protect_wait_counts // Load wait list counts + LDR w4, [x3, x1, LSL #2] // Load waiting value for this core + ADD w4, w4, #1 // Increment wait value + STR w4, [x3, x1, LSL #2] // Store new wait value value + + /* } */ + +_already_in_list1: + + /* Restore interrupts and try again. */ + + MSR DAIF, x0 // Restore interrupts + ISB // +#ifdef TX_ENABLE_WFE + WFE // Go into standby +#endif + B _try_to_get_lock // On waking, restart the protection attempt + +_got_lock_after_waiting: + + /* We're no longer waiting. */ + /* _tx_thread_smp_protect_wait_counts[this_core]--; */ + + LDR x3, =_tx_thread_smp_protect_wait_counts // Load waiting list + LDR w4, [x3, x1, LSL #2] // Load current wait value + SUB w4, w4, #1 // Decrement wait value + STR w4, [x3, x1, LSL #2] // Store new wait value value + + /* Restore registers and return. */ + +_return: + + RET + diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h new file mode 100644 index 00000000..5c33d940 --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h @@ -0,0 +1,296 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .macro _tx_thread_smp_protect_lock_got + + /* Set the currently owned core. */ + /* _tx_thread_smp_protection.tx_thread_smp_protect_core = this_core; */ + + STR w1, [x2, #4] // Store this core + + /* Increment the protection count. */ + /* _tx_thread_smp_protection.tx_thread_smp_protect_count++; */ + + LDR w3, [x2, #8] // Pickup ownership count + ADD w3, w3, #1 // Increment ownership count + STR w3, [x2, #8] // Store ownership count + DMB ISH + + .endm + + .macro _tx_thread_smp_protect_remove_from_front_of_list + + /* Remove ourselves from the list. */ + /* _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head++] = 0xFFFFFFFF; */ + + MOV w3, #0xFFFFFFFF // Build the invalid core value + LDR x4, =_tx_thread_smp_protect_wait_list_head // Get the address of the head + LDR w5, [x4] // Get the value of the head + LDR x6, =_tx_thread_smp_protect_wait_list // Get the address of the list + STR w3, [x6, x5, LSL #2] // Store the invalid core value + ADD w5, w5, #1 // Increment the head + + /* Did we wrap? */ + /* if (_tx_thread_smp_protect_wait_list_head == TX_THREAD_SMP_MAX_CORES + 1) + { */ + + LDR x3, =_tx_thread_smp_protect_wait_list_size // Load address of core list size + LDR w3, [x3] // Load the max cores value + CMP w5, w3 // Compare the head to it + BNE _store_new_head\@ // Are we at the max? + + /* _tx_thread_smp_protect_wait_list_head = 0; */ + + EOR w5, w5, w5 // We're at the max. Set it to zero + + /* } */ + +_store_new_head\@: + + STR w5, [x4] // Store the new head + + /* We have the lock! */ + /* return; */ + + .endm + + + .macro _tx_thread_smp_protect_wait_list_lock_get +/* VOID _tx_thread_smp_protect_wait_list_lock_get() +{ */ + /* We do this until we have the lock. */ + /* while (1) + { */ + +_tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@: + + /* Is the list lock available? */ + /* _tx_thread_smp_protect_wait_list_lock_protect_in_force = load_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force); */ + + LDR x1, =_tx_thread_smp_protect_wait_list_lock_protect_in_force + LDAXR w2, [x1] // Pickup the protection flag + + /* if (protect_in_force == 0) + { */ + + CMP w2, #0 + BNE _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@ // No, protection not available + + /* Try to get the list. */ + /* int status = store_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force, 1); */ + + MOV w2, #1 // Build lock value + STXR w3, w2, [x1] // Attempt to get the protection + + /* if (status == SUCCESS) */ + + CMP w3, #0 + BNE _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@ // Did it fail? If so, try again. + + /* We have the lock! */ + /* return; */ + + .endm + + + .macro _tx_thread_smp_protect_wait_list_add +/* VOID _tx_thread_smp_protect_wait_list_add(UINT new_core) +{ */ + + /* We're about to modify the list, so get the list lock. */ + /* _tx_thread_smp_protect_wait_list_lock_get(); */ + + STP x1, x2, [sp, #-16]! // Save registers we'll be using + + _tx_thread_smp_protect_wait_list_lock_get + + LDP x1, x2, [sp], #16 + + /* Add this core. */ + /* _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_tail++] = new_core; */ + + LDR x3, =_tx_thread_smp_protect_wait_list_tail // Get the address of the tail + LDR w4, [x3] // Get the value of tail + LDR x5, =_tx_thread_smp_protect_wait_list // Get the address of the list + STR w1, [x5, x4, LSL #2] // Store the new core value + ADD w4, w4, #1 // Increment the tail + + /* Did we wrap? */ + /* if (_tx_thread_smp_protect_wait_list_tail == _tx_thread_smp_protect_wait_list_size) + { */ + + LDR x5, =_tx_thread_smp_protect_wait_list_size // Load max cores address + LDR w5, [x5] // Load max cores value + CMP w4, w5 // Compare max cores to tail + BNE _tx_thread_smp_protect_wait_list_add__no_wrap\@ // Did we wrap? + + /* _tx_thread_smp_protect_wait_list_tail = 0; */ + + MOV w4, #0 + + /* } */ + +_tx_thread_smp_protect_wait_list_add__no_wrap\@: + + STR w4, [x3] // Store the new tail value. + + /* Release the list lock. */ + /* _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; */ + + MOV w3, #0 // Build lock value + LDR x4, =_tx_thread_smp_protect_wait_list_lock_protect_in_force + STR w3, [x4] // Store the new value + + .endm + + + .macro _tx_thread_smp_protect_wait_list_remove +/* VOID _tx_thread_smp_protect_wait_list_remove(UINT core) +{ */ + + /* Get the core index. */ + /* UINT core_index; + for (core_index = 0;; core_index++) */ + + EOR w4, w4, w4 // Clear for 'core_index' + LDR x2, =_tx_thread_smp_protect_wait_list // Get the address of the list + + /* { */ + +_tx_thread_smp_protect_wait_list_remove__check_cur_core\@: + + /* Is this the core? */ + /* if (_tx_thread_smp_protect_wait_list[core_index] == core) + { + break; */ + + LDR w3, [x2, x4, LSL #2] // Get the value at the current index + CMP w3, w8 // Did we find the core? + BEQ _tx_thread_smp_protect_wait_list_remove__found_core\@ + + /* } */ + + ADD w4, w4, #1 // Increment cur index + B _tx_thread_smp_protect_wait_list_remove__check_cur_core\@ // Restart the loop + + /* } */ + +_tx_thread_smp_protect_wait_list_remove__found_core\@: + + /* We're about to modify the list. Get the lock. We need the lock because another + core could be simultaneously adding (a core is simultaneously trying to get + the inter-core lock) or removing (a core is simultaneously being preempted, + like what is currently happening). */ + /* _tx_thread_smp_protect_wait_list_lock_get(); */ + + MOV x6, x1 + _tx_thread_smp_protect_wait_list_lock_get + MOV x1, x6 + + /* We remove by shifting. */ + /* while (core_index != _tx_thread_smp_protect_wait_list_tail) + { */ + +_tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@: + + LDR x2, =_tx_thread_smp_protect_wait_list_tail // Load tail address + LDR w2, [x2] // Load tail value + CMP w4, w2 // Compare cur index and tail + BEQ _tx_thread_smp_protect_wait_list_remove__removed\@ + + /* UINT next_index = core_index + 1; */ + + MOV w2, w4 // Move current index to next index register + ADD w2, w2, #1 // Add 1 + + /* if (next_index == _tx_thread_smp_protect_wait_list_size) + { */ + + LDR x3, =_tx_thread_smp_protect_wait_list_size + LDR w3, [x3] + CMP w2, w3 + BNE _tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@ + + /* next_index = 0; */ + + MOV w2, #0 + + /* } */ + +_tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@: + + /* list_cores[core_index] = list_cores[next_index]; */ + + LDR x5, =_tx_thread_smp_protect_wait_list // Get the address of the list + LDR w3, [x5, x2, LSL #2] // Get the value at the next index + STR w3, [x5, x4, LSL #2] // Store the value at the current index + + /* core_index = next_index; */ + + MOV w4, w2 + + B _tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@ + + /* } */ + +_tx_thread_smp_protect_wait_list_remove__removed\@: + + /* Now update the tail. */ + /* if (_tx_thread_smp_protect_wait_list_tail == 0) + { */ + + LDR x5, =_tx_thread_smp_protect_wait_list_tail // Load tail address + LDR w4, [x5] // Load tail value + CMP w4, #0 + BNE _tx_thread_smp_protect_wait_list_remove__tail_not_zero\@ + + /* _tx_thread_smp_protect_wait_list_tail = _tx_thread_smp_protect_wait_list_size; */ + + LDR x2, =_tx_thread_smp_protect_wait_list_size + LDR w4, [x2] + + /* } */ + +_tx_thread_smp_protect_wait_list_remove__tail_not_zero\@: + + /* _tx_thread_smp_protect_wait_list_tail--; */ + + SUB w4, w4, #1 + STR w4, [x5] // Store new tail value + + /* Release the list lock. */ + /* _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; */ + + MOV w2, #0 // Build lock value + LDR x4, =_tx_thread_smp_protect_wait_list_lock_protect_in_force // Load lock address + STR w2, [x4] // Store the new value + + /* We're no longer waiting. Note that this should be zero since, again, + this function is only called when a thread preemption is occurring. */ + /* _tx_thread_smp_protect_wait_counts[core]--; */ + LDR x4, =_tx_thread_smp_protect_wait_counts // Load wait list counts + LDR w2, [x4, x8, LSL #2] // Load waiting value + SUB w2, w2, #1 // Subtract 1 + STR w2, [x4, x8, LSL #2] // Store new waiting value + + .endm + diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_time_get.S new file mode 100644 index 00000000..b9e02c86 --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_time_get.S @@ -0,0 +1,83 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_time_get Cortex-A35-SMP/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets the global time value that is used for debug */ +/* information and event tracing. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* 32-bit time stamp */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Source */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_time_get + .type _tx_thread_smp_time_get, @function +_tx_thread_smp_time_get: + MOV x0, #0 // FIXME: Get timer + RET + + diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_unprotect.S new file mode 100644 index 00000000..07e6c5ed --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_unprotect.S @@ -0,0 +1,130 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_unprotect Cortex-A35-SMP/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function releases previously obtained protection. The supplied */ +/* previous SR is restored. If the value of _tx_thread_system_state */ +/* and _tx_thread_preempt_disable are both zero, then multithreading */ +/* is enabled as well. */ +/* */ +/* INPUT */ +/* */ +/* Previous Status Register */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Source */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_unprotect + .type _tx_thread_smp_unprotect, @function +_tx_thread_smp_unprotect: + MSR DAIFSet, 0x3 // Lockout interrupts + + MRS x1, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x2, x1, #8, #8 // Isolate cluster ID +#endif + UBFX x1, x1, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x1, x1, x2, LSL #2 // Calculate CPU ID +#endif + + LDR x2,=_tx_thread_smp_protection // Build address of protection structure + LDR w3, [x2, #4] // Pickup the owning core + CMP w1, w3 // Is it this core? + BNE _still_protected // If this is not the owning core, protection is in force elsewhere + + LDR w3, [x2, #8] // Pickup the protection count + CMP w3, #0 // Check to see if the protection is still active + BEQ _still_protected // If the protection count is zero, protection has already been cleared + + SUB w3, w3, #1 // Decrement the protection count + STR w3, [x2, #8] // Store the new count back + CMP w3, #0 // Check to see if the protection is still active + BNE _still_protected // If the protection count is non-zero, protection is still in force + LDR x2,=_tx_thread_preempt_disable // Build address of preempt disable flag + LDR w3, [x2] // Pickup preempt disable flag + CMP w3, #0 // Is the preempt disable flag set? + BNE _still_protected // Yes, skip the protection release + + LDR x2,=_tx_thread_smp_protect_wait_counts // Build build address of wait counts + LDR w3, [x2, x1, LSL #2] // Pickup wait list value + CMP w3, #0 // Are any entities on this core waiting? + BNE _still_protected // Yes, skip the protection release + + LDR x2,=_tx_thread_smp_protection // Build address of protection structure + MOV w3, #0xFFFFFFFF // Build invalid value + STR w3, [x2, #4] // Mark the protected core as invalid + DMB ISH // Ensure that accesses to shared resource have completed + MOV w3, #0 // Build release protection value + STR w3, [x2, #0] // Release the protection + DSB ISH // To ensure update of the protection occurs before other CPUs awake + +_still_protected: +#ifdef TX_ENABLE_WFE + SEV // Send event to other CPUs, wakes anyone waiting on the protection (using WFE) +#endif + MSR DAIF, x0 // Restore interrupt posture + RET + diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_stack_build.S b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_stack_build.S new file mode 100644 index 00000000..46dd7f4d --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_stack_build.S @@ -0,0 +1,172 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build Cortex-A35-SMP/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +{ */ + .global _tx_thread_stack_build + .type _tx_thread_stack_build, @function +_tx_thread_stack_build: + + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-A35 should look like the following after it is built: + + Stack Top: SSPR Initial SSPR + ELR Point of interrupt + x28 Initial value for x28 + not used Not used + x26 Initial value for x26 + x27 Initial value for x27 + x24 Initial value for x24 + x25 Initial value for x25 + x22 Initial value for x22 + x23 Initial value for x23 + x20 Initial value for x20 + x21 Initial value for x21 + x18 Initial value for x18 + x19 Initial value for x19 + x16 Initial value for x16 + x17 Initial value for x17 + x14 Initial value for x14 + x15 Initial value for x15 + x12 Initial value for x12 + x13 Initial value for x13 + x10 Initial value for x10 + x11 Initial value for x11 + x8 Initial value for x8 + x9 Initial value for x9 + x6 Initial value for x6 + x7 Initial value for x7 + x4 Initial value for x4 + x5 Initial value for x5 + x2 Initial value for x2 + x3 Initial value for x3 + x0 Initial value for x0 + x1 Initial value for x1 + x29 Initial value for x29 (frame pointer) + x30 Initial value for x30 (link register) + 0 For stack backtracing + + Stack Bottom: (higher memory address) */ + + LDR x4, [x0, #24] // Pickup end of stack area + BIC x4, x4, #0xF // Ensure 16-byte alignment + + /* Actually build the stack frame. */ + + MOV x2, #0 // Build clear value + MOV x3, #0 // + + STP x2, x3, [x4, #-16]! // Set backtrace to 0 + STP x2, x3, [x4, #-16]! // Set initial x29, x30 + STP x2, x3, [x4, #-16]! // Set initial x0, x1 + STP x2, x3, [x4, #-16]! // Set initial x2, x3 + STP x2, x3, [x4, #-16]! // Set initial x4, x5 + STP x2, x3, [x4, #-16]! // Set initial x6, x7 + STP x2, x3, [x4, #-16]! // Set initial x8, x9 + STP x2, x3, [x4, #-16]! // Set initial x10, x11 + STP x2, x3, [x4, #-16]! // Set initial x12, x13 + STP x2, x3, [x4, #-16]! // Set initial x14, x15 + STP x2, x3, [x4, #-16]! // Set initial x16, x17 + STP x2, x3, [x4, #-16]! // Set initial x18, x19 + STP x2, x3, [x4, #-16]! // Set initial x20, x21 + STP x2, x3, [x4, #-16]! // Set initial x22, x23 + STP x2, x3, [x4, #-16]! // Set initial x24, x25 + STP x2, x3, [x4, #-16]! // Set initial x26, x27 + STP x2, x3, [x4, #-16]! // Set initial x28 +#ifdef EL1 + MOV x2, #0x4 // Build initial SPSR (EL1) +#else +#ifdef EL2 + MOV x2, #0x8 // Build initial SPSR (EL2) +#else + MOV x2, #0xC // Build initial SPSR (EL3) +#endif +#endif + MOV x3, x1 // Build initial ELR + STP x2, x3, [x4, #-16]! // Set initial SPSR & ELR + + /* Setup stack pointer. */ + /* thread_ptr -> tx_thread_stack_ptr = x2; */ + + STR x4, [x0, #8] // Save stack pointer in thread's + MOV x3, #1 // Build ready flag + STR w3, [x0, #260] // Set ready flag + RET // Return to caller + +/* } */ + + diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_system_return.S b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_system_return.S new file mode 100644 index 00000000..f6f119b6 --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_system_return.S @@ -0,0 +1,191 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return Cortex-A35-SMP/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the ThreadX system. Only a */ +/* minimal context is saved since the compiler assumes temp registers */ +/* are going to get slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_system_return(VOID) +{ */ + .global _tx_thread_system_return + .type _tx_thread_system_return, @function +_tx_thread_system_return: +; +; /* Save minimal context on the stack. */ +; + MRS x0, DAIF // Pickup DAIF + MSR DAIFSet, 0x3 // Lockout interrupts + STP x29, x30, [sp, #-16]! // Save x29 (frame pointer), x30 (link register) + STP x19, x20, [sp, #-16]! // Save x19, x20 + STP x21, x22, [sp, #-16]! // Save x21, x22 + STP x23, x24, [sp, #-16]! // Save x23, x24 + STP x25, x26, [sp, #-16]! // Save x25, x26 + STP x27, x28, [sp, #-16]! // Save x27, x28 + MRS x8, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x3, x8, #8, #8 // Isolate cluster ID +#endif + UBFX x8, x8, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x8, x8, x3, LSL #2 // Calculate CPU ID +#endif + LDR x5, =_tx_thread_current_ptr // Pickup address of current ptr + LDR x6, [x5, x8, LSL #3] // Pickup current thread pointer + +#ifdef ENABLE_ARM_FP + LDR w7, [x6, #268] // Pickup FP enable flag + CMP w7, #0 // Is FP enabled? + BEQ _skip_fp_save // No, skip FP save + STP q8, q9, [sp, #-32]! // Save q8, q9 + STP q10, q11, [sp, #-32]! // Save q10, q11 + STP q12, q13, [sp, #-32]! // Save q12, q13 + STP q14, q15, [sp, #-32]! // Save q14, q15 + MRS x2, FPSR // Pickup FPSR + MRS x3, FPCR // Pickup FPCR + STP x2, x3, [sp, #-16]! // Save FPSR, FPCR +_skip_fp_save: +#endif + + MOV x1, #0 // Clear x1 + STP x0, x1, [sp, #-16]! // Save DAIF and clear value for ELR_EK1 + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread exit function to indicate the thread is no longer executing. */ + + MOV x19, x5 // Save x5 + MOV x20, x6 // Save x6 + MOV x21, x8 // Save x2 + BL _tx_execution_thread_exit // Call the thread exit function + MOV x8, x21 // Restore x2 + MOV x5, x19 // Restore x5 + MOV x6, x20 // Restore x6 +#endif + + LDR x2, =_tx_timer_time_slice // Pickup address of time slice + LDR w1, [x2, x8, LSL #2] // Pickup current time slice + + /* Save current stack and switch to system stack. */ + /* _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; */ + /* sp = _tx_thread_system_stack_ptr[core]; */ + + MOV x4, sp // + STR x4, [x6, #8] // Save thread stack pointer + LDR x3, =_tx_thread_system_stack_ptr // Pickup address of system stack + LDR x4, [x3, x8, LSL #3] // Pickup system stack pointer + MOV sp, x4 // Setup system stack pointer + + /* Determine if the time-slice is active. */ + /* if (_tx_timer_time_slice[core]) + { */ + + MOV x4, #0 // Build clear value + CMP w1, #0 // Is a time-slice active? + BEQ __tx_thread_dont_save_ts // No, don't save the time-slice + + /* Save the current remaining time-slice. */ + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + STR w4, [x2, x8, LSL #2] // Clear time-slice + STR w1, [x6, #36] // Store current time-slice + + /* } */ +__tx_thread_dont_save_ts: + + /* Clear the current thread pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + STR x4, [x5, x8, LSL #3] // Clear current thread pointer + + /* Set ready bit in thread control block. */ + + MOV x3, #1 // Build ready value + STR w3, [x6, #260] // Make the thread ready + DMB ISH // + + /* Now clear protection. It is assumed that protection is in force whenever this routine is called. */ + + LDR x3, =_tx_thread_smp_protection // Pickup address of protection structure + LDR x1, =_tx_thread_preempt_disable // Build address to preempt disable flag + STR w4, [x1, #0] // Clear preempt disable flag + STR w4, [x3, #8] // Cear protection count + MOV x1, #0xFFFFFFFF // Build invalid value + STR w1, [x3, #4] // Set core to an invalid value + DMB ISH // Ensure that accesses to shared resource have completed + STR w4, [x3, #0] // Clear protection + DSB ISH // To ensure update of the shared resource occurs before other CPUs awake + SEV // Send event to other CPUs, wakes anyone waiting on a mutex (using WFE) + B _tx_thread_schedule // Jump to scheduler! + +/* } */ + + diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_thread_timeout.c b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_timeout.c new file mode 100644 index 00000000..85d2a509 --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_thread_timeout.c @@ -0,0 +1,165 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_timeout Cortex-A35-SMP */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles thread timeout processing. Timeouts occur in */ +/* two flavors, namely the thread sleep timeout and all other service */ +/* call timeouts. Thread sleep timeouts are processed locally, while */ +/* the others are processed by the appropriate suspension clean-up */ +/* service. */ +/* */ +/* INPUT */ +/* */ +/* timeout_input Contains the thread pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* Suspension Cleanup Functions */ +/* _tx_thread_system_resume Resume thread */ +/* _tx_thread_system_ni_resume Non-interruptable resume thread */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_timer_expiration_process Timer expiration function */ +/* _tx_timer_thread_entry Timer thread function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_timeout(ULONG timeout_input) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_THREAD *thread_ptr; +VOID (*suspend_cleanup)(struct TX_THREAD_STRUCT *suspend_thread_ptr, ULONG suspension_sequence); +ULONG suspension_sequence; + + + /* Pickup the thread pointer. */ + TX_THREAD_TIMEOUT_POINTER_SETUP(thread_ptr) + + /* Disable interrupts. */ + TX_DISABLE + + /* Determine how the thread is currently suspended. */ + if (thread_ptr -> tx_thread_state == TX_SLEEP) + { + +#ifdef TX_NOT_INTERRUPTABLE + + /* Resume the thread! */ + _tx_thread_system_ni_resume(thread_ptr); + + /* Restore interrupts. */ + TX_RESTORE +#else + + /* Increment the disable preemption flag. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Lift the suspension on the sleeping thread. */ + _tx_thread_system_resume(thread_ptr); +#endif + } + else + { + + /* Process all other suspension timeouts. */ + +#ifdef TX_THREAD_ENABLE_PERFORMANCE_INFO + + /* Increment the total number of thread timeouts. */ + _tx_thread_performance_timeout_count++; + + /* Increment the number of timeouts for this thread. */ + thread_ptr -> tx_thread_performance_timeout_count++; +#endif + + /* Pickup the cleanup routine address. */ + suspend_cleanup = thread_ptr -> tx_thread_suspend_cleanup; + +#ifndef TX_NOT_INTERRUPTABLE + + /* Pickup the suspension sequence number that is used later to verify that the + cleanup is still necessary. */ + suspension_sequence = thread_ptr -> tx_thread_suspension_sequence; +#else + + /* When not interruptable is selected, the suspension sequence is not used - just set to 0. */ + suspension_sequence = ((ULONG) 0); +#endif + +#ifndef TX_NOT_INTERRUPTABLE + + /* Restore interrupts. */ + TX_RESTORE +#endif + + /* Call any cleanup routines. */ + if (suspend_cleanup != TX_NULL) + { + + /* Yes, there is a function to call. */ + (suspend_cleanup)(thread_ptr, suspension_sequence); + } + +#ifdef TX_NOT_INTERRUPTABLE + + /* Restore interrupts. */ + TX_RESTORE +#endif + } +} + diff --git a/ports_smp/cortex_a35_smp/ac6/src/tx_timer_interrupt.S b/ports_smp/cortex_a35_smp/ac6/src/tx_timer_interrupt.S new file mode 100644 index 00000000..9b9be578 --- /dev/null +++ b/ports_smp/cortex_a35_smp/ac6/src/tx_timer_interrupt.S @@ -0,0 +1,198 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_timer.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt Cortex-A35-SMP/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_timer_interrupt(VOID) +{ */ + .global _tx_timer_interrupt + .type _tx_timer_interrupt, @function +_tx_timer_interrupt: + + MRS x2, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x3, x2, #8, #8 // Isolate cluster ID +#endif + UBFX x2, x2, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x2, x2, x3, LSL #2 // Calculate CPU ID +#endif + CMP x2, #0 // Is this core 0? + BEQ __tx_process_timer // If desired core, continue processing + RET // Simply return if different core +__tx_process_timer: + + /* Upon entry to this routine, it is assumed that context save has already + been called, and therefore the compiler scratch registers are available + for use. */ + + STP x27, x28, [sp, #-16]! // Save x27, x28 + STP x29, x30, [sp, #-16]! // Save x29 (frame pointer), x30 (link register) + + /* Get inter-core protection. */ + + BL _tx_thread_smp_protect // Get inter-core protection + MOV x28, x0 // Save the return value in preserved register + + /* Increment the system clock. */ + /* _tx_timer_system_clock++; */ + + LDR x1, =_tx_timer_system_clock // Pickup address of system clock + LDR w0, [x1, #0] // Pickup system clock + ADD w0, w0, #1 // Increment system clock + STR w0, [x1, #0] // Store new system clock + + /* Test for timer expiration. */ + /* if (*_tx_timer_current_ptr) + { */ + + LDR x1, =_tx_timer_current_ptr // Pickup current timer pointer addr + LDR x0, [x1, #0] // Pickup current timer + LDR x2, [x0, #0] // Pickup timer list entry + CMP x2, #0 // Is there anything in the list? + BEQ __tx_timer_no_timer // No, just increment the timer + + /* Set expiration flag. */ + /* _tx_timer_expired = TX_TRUE; */ + + LDR x3, =_tx_timer_expired // Pickup expiration flag address + MOV w2, #1 // Build expired value + STR w2, [x3, #0] // Set expired flag + B __tx_timer_done // Finished timer processing + + /* } + else + { */ +__tx_timer_no_timer: + + /* No timer expired, increment the timer pointer. */ + /* _tx_timer_current_ptr++; */ + + ADD x0, x0, #8 // Move to next timer + + /* Check for wrap-around. */ + /* if (_tx_timer_current_ptr == _tx_timer_list_end) */ + + LDR x3, =_tx_timer_list_end // Pickup addr of timer list end + LDR x2, [x3, #0] // Pickup list end + CMP x0, x2 // Are we at list end? + BNE __tx_timer_skip_wrap // No, skip wrap-around logic + + /* Wrap to beginning of list. */ + /* _tx_timer_current_ptr = _tx_timer_list_start; */ + + LDR x3, =_tx_timer_list_start // Pickup addr of timer list start + LDR x0, [x3, #0] // Set current pointer to list start + +__tx_timer_skip_wrap: + + STR x0, [x1, #0] // Store new current timer pointer + /* } */ + +__tx_timer_done: + + /* Did a timer expire? */ + /* if (_tx_timer_expired) + { */ + + LDR x1, =_tx_timer_expired // Pickup addr of expired flag + LDR w0, [x1, #0] // Pickup timer expired flag + CMP w0, #0 // Check for timer expiration + BEQ __tx_timer_dont_activate // If not set, skip timer activation + + /* Process timer expiration. */ + /* _tx_timer_expiration_process(); */ + + BL _tx_timer_expiration_process // Call the timer expiration handling routine + + /* } */ +__tx_timer_dont_activate: + + /* Call time-slice processing. */ + /* _tx_thread_time_slice(); */ + BL _tx_thread_time_slice // Call time-slice processing + + /* Release inter-core protection. */ + + MOV x0, x28 // Pass the previous status register back + BL _tx_thread_smp_unprotect // Release protection + + LDP x29, x30, [sp], #16 // Recover x29, x30 + LDP x27, x28, [sp], #16 // Recover x27, x28 + RET // Return to caller + +/* } */ + + diff --git a/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/.cproject b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/.cproject new file mode 100644 index 00000000..9ff6439f --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/.cproject @@ -0,0 +1,246 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/.project b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/.project new file mode 100644 index 00000000..a1b15572 --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/.project @@ -0,0 +1,26 @@ + + + sample_threadx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/.settings/language.settings.xml b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/.settings/language.settings.xml new file mode 100644 index 00000000..1988c9a3 --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/.settings/language.settings.xml @@ -0,0 +1,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3.h b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3.h new file mode 100644 index 00000000..23bc7fd8 --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3.h @@ -0,0 +1,561 @@ +/* + * GICv3.h - data types and function prototypes for GICv3 utility routines + * + * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. + * Use, modification and redistribution of this file is subject to your possession of a + * valid End User License Agreement for the Arm Product of which these examples are part of + * and your compliance with all applicable terms and conditions of such licence agreement. + */ +#ifndef GICV3_h +#define GICV3_h + +#include + +/* + * extra flags for GICD enable + */ +typedef enum +{ + gicdctlr_EnableGrp0 = (1 << 0), + gicdctlr_EnableGrp1NS = (1 << 1), + gicdctlr_EnableGrp1A = (1 << 1), + gicdctlr_EnableGrp1S = (1 << 2), + gicdctlr_EnableAll = (1 << 2) | (1 << 1) | (1 << 0), + gicdctlr_ARE_S = (1 << 4), /* Enable Secure state affinity routing */ + gicdctlr_ARE_NS = (1 << 5), /* Enable Non-Secure state affinity routing */ + gicdctlr_DS = (1 << 6), /* Disable Security support */ + gicdctlr_E1NWF = (1 << 7) /* Enable "1-of-N" wakeup model */ +} GICDCTLRFlags_t; + +/* + * modes for SPI routing + */ +typedef enum +{ + gicdirouter_ModeSpecific = 0, + gicdirouter_ModeAny = (1 << 31) +} GICDIROUTERBits_t; + +typedef enum +{ + gicdicfgr_Level = 0, + gicdicfgr_Edge = (1 << 1) +} GICDICFGRBits_t; + +typedef enum +{ + gicigroupr_G0S = 0, + gicigroupr_G1NS = (1 << 0), + gicigroupr_G1S = (1 << 2) +} GICIGROUPRBits_t; + +typedef enum +{ + gicrwaker_ProcessorSleep = (1 << 1), + gicrwaker_ChildrenAsleep = (1 << 2) +} GICRWAKERBits_t; + +/**********************************************************************/ + +/* + * Utility macros & functions + */ +#define RANGE_LIMIT(x) ((sizeof(x) / sizeof((x)[0])) - 1) + +static inline uint64_t gicv3PackAffinity(uint32_t aff3, uint32_t aff2, + uint32_t aff1, uint32_t aff0) +{ + /* + * only need to cast aff3 to get type promotion for all affinities + */ + return ((((uint64_t)aff3 & 0xff) << 32) | + ((aff2 & 0xff) << 16) | + ((aff1 & 0xff) << 8) | aff0); +} + +/**********************************************************************/ + +/* + * GIC Distributor Function Prototypes + */ + +/* + * ConfigGICD - configure GIC Distributor prior to enabling it + * + * Inputs: + * + * control - control flags + * + * Returns: + * + * + * + * NOTE: + * + * ConfigGICD() will set an absolute flags value, whereas + * {En,Dis}ableGICD() will only {set,clear} the flag bits + * passed as a parameter + */ +void ConfigGICD(GICDCTLRFlags_t flags); + +/* + * EnableGICD - top-level enable for GIC Distributor + * + * Inputs: + * + * flags - new control flags to set + * + * Returns: + * + * + * + * NOTE: + * + * ConfigGICD() will set an absolute flags value, whereas + * {En,Dis}ableGICD() will only {set,clear} the flag bits + * passed as a parameter + */ +void EnableGICD(GICDCTLRFlags_t flags); + +/* + * DisableGICD - top-level disable for GIC Distributor + * + * Inputs + * + * flags - control flags to clear + * + * Returns + * + * + * + * NOTE: + * + * ConfigGICD() will set an absolute flags value, whereas + * {En,Dis}ableGICD() will only {set,clear} the flag bits + * passed as a parameter + */ +void DisableGICD(GICDCTLRFlags_t flags); + +/* + * SyncAREinGICD - synchronise GICD Address Routing Enable bits + * + * Inputs + * + * flags - absolute flag bits to set in GIC Distributor + * + * dosync - flag whether to wait for ARE bits to match passed + * flag field (dosync = true), or whether to set absolute + * flag bits (dosync = false) + * + * Returns + * + * + * + * NOTE: + * + * This function is used to resolve a race in an MP system whereby secondary + * CPUs cannot reliably program all Redistributor registers until the + * primary CPU has enabled Address Routing. The primary CPU will call this + * function with dosync = false, while the secondaries will call it with + * dosync = true. + */ +void SyncAREinGICD(GICDCTLRFlags_t flags, uint32_t dosync); + +/* + * EnableSPI - enable a specific shared peripheral interrupt + * + * Inputs: + * + * id - which interrupt to enable + * + * Returns: + * + * + */ +void EnableSPI(uint32_t id); + +/* + * DisableSPI - disable a specific shared peripheral interrupt + * + * Inputs: + * + * id - which interrupt to disable + * + * Returns: + * + * + */ +void DisableSPI(uint32_t id); + +/* + * SetSPIPriority - configure the priority for a shared peripheral interrupt + * + * Inputs: + * + * id - interrupt identifier + * + * priority - 8-bit priority to program (see note below) + * + * Returns: + * + * + * + * Note: + * + * The GICv3 architecture makes this function sensitive to the Security + * context in terms of what effect it has on the programmed priority: no + * attempt is made to adjust for the reduced priority range available + * when making Non-Secure accesses to the GIC + */ +void SetSPIPriority(uint32_t id, uint32_t priority); + +/* + * GetSPIPriority - determine the priority for a shared peripheral interrupt + * + * Inputs: + * + * id - interrupt identifier + * + * Returns: + * + * interrupt priority in the range 0 - 0xff + */ +uint32_t GetSPIPriority(uint32_t id); + +/* + * SetSPIRoute - specify interrupt routing when gicdctlr_ARE is enabled + * + * Inputs: + * + * id - interrupt identifier + * + * affinity - prepacked "dotted quad" affinity routing. NOTE: use the + * gicv3PackAffinity() helper routine to generate this input + * + * mode - select routing mode (specific affinity, or any recipient) + * + * Returns: + * + * + */ +void SetSPIRoute(uint32_t id, uint64_t affinity, GICDIROUTERBits_t mode); + +/* + * GetSPIRoute - read ARE-enabled interrupt routing information + * + * Inputs: + * + * id - interrupt identifier + * + * Returns: + * + * routing configuration + */ +uint64_t GetSPIRoute(uint32_t id); + +/* + * SetSPITarget - configure the set of processor targets for an interrupt + * + * Inputs + * + * id - interrupt identifier + * + * target - 8-bit target bitmap + * + * Returns + * + * + */ +void SetSPITarget(uint32_t id, uint32_t target); + +/* + * GetSPITarget - read the set of processor targets for an interrupt + * + * Inputs + * + * id - interrupt identifier + * + * Returns + * + * 8-bit target bitmap + */ +uint32_t GetSPITarget(uint32_t id); + +/* + * ConfigureSPI - setup an interrupt as edge- or level-triggered + * + * Inputs + * + * id - interrupt identifier + * + * config - desired configuration + * + * Returns + * + * + */ +void ConfigureSPI(uint32_t id, GICDICFGRBits_t config); + +/* + * SetSPIPending - mark an interrupt as pending + * + * Inputs + * + * id - interrupt identifier + * + * Returns + * + * + */ +void SetSPIPending(uint32_t id); + +/* + * ClearSPIPending - mark an interrupt as not pending + * + * Inputs + * + * id - interrupt identifier + * + * Returns + * + * + */ +void ClearSPIPending(uint32_t id); + +/* + * GetSPIPending - query whether an interrupt is pending + * + * Inputs + * + * id - interrupt identifier + * + * Returns + * + * pending status + */ +uint32_t GetSPIPending(uint32_t id); + +/* + * SetSPISecurity - mark a shared peripheral interrupt as + * security + * + * Inputs + * + * id - which interrupt to mark + * + * group - the group for the interrupt + * + * Returns + * + * + */ +void SetSPISecurity(uint32_t id, GICIGROUPRBits_t group); + +/* + * SetSPISecurityBlock - mark a block of 32 shared peripheral + * interrupts as security + * + * Inputs: + * + * block - which block to mark (e.g. 1 = Ints 32-63) + * + * group - the group for the interrupts + * + * Returns: + * + * + */ +void SetSPISecurityBlock(uint32_t block, GICIGROUPRBits_t group); + +/* + * SetSPISecurityAll - mark all shared peripheral interrupts + * as security + * + * Inputs: + * + * group - the group for the interrupts + * + * Returns: + * + * + */ +void SetSPISecurityAll(GICIGROUPRBits_t group); + +/**********************************************************************/ + +/* + * GIC Re-Distributor Function Prototypes + * + * The model for calling Redistributor functions is that, rather than + * identifying the target redistributor with every function call, the + * SelectRedistributor() function is used to identify which redistributor + * is to be used for all functions until a different redistributor is + * explicitly selected + */ + +/* + * WakeupGICR - wake up a Redistributor + * + * Inputs: + * + * gicr - which Redistributor to wakeup + * + * Returns: + * + * + */ +void WakeupGICR(uint32_t gicr); + +/* + * EnablePrivateInt - enable a private (SGI/PPI) interrupt + * + * Inputs: + * + * gicr - which Redistributor to program + * + * id - which interrupt to enable + * + * Returns: + * + * + */ +void EnablePrivateInt(uint32_t gicr, uint32_t id); + +/* + * DisablePrivateInt - disable a private (SGI/PPI) interrupt + * + * Inputs: + * + * gicr - which Redistributor to program + * + * id - which interrupt to disable + * + * Returns: + * + * + */ +void DisablePrivateInt(uint32_t gicr, uint32_t id); + +/* + * SetPrivateIntPriority - configure the priority for a private + * (SGI/PPI) interrupt + * + * Inputs: + * + * gicr - which Redistributor to program + * + * id - interrupt identifier + * + * priority - 8-bit priority to program (see note below) + * + * Returns: + * + * + * + * Note: + * + * The GICv3 architecture makes this function sensitive to the Security + * context in terms of what effect it has on the programmed priority: no + * attempt is made to adjust for the reduced priority range available + * when making Non-Secure accesses to the GIC + */ +void SetPrivateIntPriority(uint32_t gicr, uint32_t id, uint32_t priority); + +/* + * GetPrivateIntPriority - configure the priority for a private + * (SGI/PPI) interrupt + * + * Inputs: + * + * gicr - which Redistributor to program + * + * id - interrupt identifier + * + * Returns: + * + * Int priority + */ +uint32_t GetPrivateIntPriority(uint32_t gicr, uint32_t id); + +/* + * SetPrivateIntPending - mark a private (SGI/PPI) interrupt as pending + * + * Inputs + * + * gicr - which Redistributor to program + * + * id - interrupt identifier + * + * Returns + * + * + */ +void SetPrivateIntPending(uint32_t gicr, uint32_t id); + +/* + * ClearPrivateIntPending - mark a private (SGI/PPI) interrupt as not pending + * + * Inputs + * + * gicr - which Redistributor to program + * + * id - interrupt identifier + * + * Returns + * + * + */ +void ClearPrivateIntPending(uint32_t gicr, uint32_t id); + +/* + * GetPrivateIntPending - query whether a private (SGI/PPI) interrupt is pending + * + * Inputs + * + * gicr - which Redistributor to program + * + * id - interrupt identifier + * + * Returns + * + * pending status + */ +uint32_t GetPrivateIntPending(uint32_t gicr, uint32_t id); + +/* + * SetPrivateIntSecurity - mark a private (SGI/PPI) interrupt as + * security + * + * Inputs + * + * gicr - which Redistributor to program + * + * id - which interrupt to mark + * + * group - the group for the interrupt + * + * Returns + * + * + */ +void SetPrivateIntSecurity(uint32_t gicr, uint32_t id, GICIGROUPRBits_t group); + +/* + * SetPrivateIntSecurityBlock - mark all 32 private (SGI/PPI) + * interrupts as security + * + * Inputs: + * + * gicr - which Redistributor to program + * + * group - the group for the interrupt + * + * Returns: + * + * + */ +void SetPrivateIntSecurityBlock(uint32_t gicr, GICIGROUPRBits_t group); + +#endif /* ndef GICV3_h */ + +/* EOF GICv3.h */ diff --git a/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_aliases.h b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_aliases.h new file mode 100644 index 00000000..0928d14c --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_aliases.h @@ -0,0 +1,113 @@ +// +// Aliases for GICv3 registers +// +// Copyright (c) 2016-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// + +#ifndef GICV3_ALIASES_H +#define GICV3_ALIASES_H + +#ifndef __clang__ + +/* + * Mapping of MSR and MRS to physical and virtual CPU interface registers + * + * Arm Generic Interrupt Controller Architecture Specification + * GIC architecture version 3.0 and version 4.0 + * Table 8-5 + */ +#define ICC_AP0R0_EL1 S3_0_C12_C8_4 +#define ICC_AP0R1_EL1 S3_0_C12_C8_5 +#define ICC_AP0R2_EL1 S3_0_C12_C8_6 +#define ICC_AP0R3_EL1 S3_0_C12_C8_7 + +#define ICC_AP1R0_EL1 S3_0_C12_C9_0 +#define ICC_AP1R1_EL1 S3_0_C12_C9_1 +#define ICC_AP1R2_EL1 S3_0_C12_C9_2 +#define ICC_AP1R3_EL1 S3_0_C12_C9_3 + +#define ICC_ASGI1R_EL1 S3_0_C12_C11_6 + +#define ICC_BPR0_EL1 S3_0_C12_C8_3 +#define ICC_BPR1_EL1 S3_0_C12_C12_3 + +#define ICC_CTLR_EL1 S3_0_C12_C12_4 +#define ICC_CTLR_EL3 S3_6_C12_C12_4 + +#define ICC_DIR_EL1 S3_0_C12_C11_1 + +#define ICC_EOIR0_EL1 S3_0_C12_C8_1 +#define ICC_EOIR1_EL1 S3_0_C12_C12_1 + +#define ICC_HPPIR0_EL1 S3_0_C12_C8_2 +#define ICC_HPPIR1_EL1 S3_0_C12_C12_2 + +#define ICC_IAR0_EL1 S3_0_C12_C8_0 +#define ICC_IAR1_EL1 S3_0_C12_C12_0 + +#define ICC_IGRPEN0_EL1 S3_0_C12_C12_6 +#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 +#define ICC_IGRPEN1_EL3 S3_6_C12_C12_7 + +#define ICC_PMR_EL1 S3_0_C4_C6_0 +#define ICC_RPR_EL1 S3_0_C12_C11_3 + +#define ICC_SGI0R_EL1 S3_0_C12_C11_7 +#define ICC_SGI1R_EL1 S3_0_C12_C11_5 + +#define ICC_SRE_EL1 S3_0_C12_C12_5 +#define ICC_SRE_EL2 S3_4_C12_C9_5 +#define ICC_SRE_EL3 S3_6_C12_C12_5 + +/* + * Mapping of MSR and MRS to virtual interface control registers + * + * Arm Generic Interrupt Controller Architecture Specification + * GIC architecture version 3.0 and version 4.0 + * Table 8-6 + */ +#define ICH_AP0R0_EL2 S3_4_C12_C8_0 +#define ICH_AP0R1_EL2 S3_4_C12_C8_1 +#define ICH_AP0R2_EL2 S3_4_C12_C8_2 +#define ICH_AP0R3_EL2 S3_4_C12_C8_3 + +#define ICH_AP1R0_EL2 S3_4_C12_C9_0 +#define ICH_AP1R1_EL2 S3_4_C12_C9_1 +#define ICH_AP1R2_EL2 S3_4_C12_C9_2 +#define ICH_AP1R3_EL2 S3_4_C12_C9_3 + +#define ICH_HCR_EL2 S3_4_C12_C11_0 + +#define ICH_VTR_EL2 S3_4_C12_C11_1 + +#define ICH_MISR_EL2 S3_4_C12_C11_2 + +#define ICH_EISR_EL2 S3_4_C12_C11_3 + +#define ICH_ELRSR_EL2 S3_4_C12_C11_5 + +#define ICH_VMCR_EL2 S3_4_C12_C11_7 + +#define ICH_LR0_EL2 S3_4_C12_C12_0 +#define ICH_LR1_EL2 S3_4_C12_C12_1 +#define ICH_LR2_EL2 S3_4_C12_C12_2 +#define ICH_LR3_EL2 S3_4_C12_C12_3 +#define ICH_LR4_EL2 S3_4_C12_C12_4 +#define ICH_LR5_EL2 S3_4_C12_C12_5 +#define ICH_LR6_EL2 S3_4_C12_C12_6 +#define ICH_LR7_EL2 S3_4_C12_C12_7 +#define ICH_LR8_EL2 S3_4_C12_C13_0 +#define ICH_LR9_EL2 S3_4_C12_C13_1 +#define ICH_LR10_EL2 S3_4_C12_C13_2 +#define ICH_LR11_EL2 S3_4_C12_C13_3 +#define ICH_LR12_EL2 S3_4_C12_C13_4 +#define ICH_LR13_EL2 S3_4_C12_C13_5 +#define ICH_LR14_EL2 S3_4_C12_C13_6 +#define ICH_LR15_EL2 S3_4_C12_C13_7 + +#endif /* not __clang__ */ + +#endif /* GICV3_ALIASES */ diff --git a/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_gicc.h b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_gicc.h new file mode 100644 index 00000000..2b8a2d3e --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_gicc.h @@ -0,0 +1,254 @@ +/* + * GICv3_gicc.h - prototypes and inline functions for GICC system register operations + * + * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. + * Use, modification and redistribution of this file is subject to your possession of a + * valid End User License Agreement for the Arm Product of which these examples are part of + * and your compliance with all applicable terms and conditions of such licence agreement. + */ +#ifndef GICV3_gicc_h +#define GICV3_gicc_h + +#include "GICv3_aliases.h" + +#define stringify_no_expansion(x) #x +#define stringify(x) stringify_no_expansion(x) + +/**********************************************************************/ + +typedef enum +{ + sreSRE = (1 << 0), + sreDFB = (1 << 1), + sreDIB = (1 << 2), + sreEnable = (1 << 3) +} ICC_SREBits_t; + +static inline void setICC_SRE_EL1(ICC_SREBits_t mode) +{ + asm("msr "stringify(ICC_SRE_EL1)", %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline uint64_t getICC_SRE_EL1(void) +{ + uint64_t retc; + + asm("mrs %0, "stringify(ICC_SRE_EL1)"\n" : "=r" (retc)); + + return retc; +} + +static inline void setICC_SRE_EL2(ICC_SREBits_t mode) +{ + asm("msr "stringify(ICC_SRE_EL2)", %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline uint64_t getICC_SRE_EL2(void) +{ + uint64_t retc; + + asm("mrs %0, "stringify(ICC_SRE_EL2)"\n" : "=r" (retc)); + + return retc; +} + +static inline void setICC_SRE_EL3(ICC_SREBits_t mode) +{ + asm("msr "stringify(ICC_SRE_EL3)", %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline uint64_t getICC_SRE_EL3(void) +{ + uint64_t retc; + + asm("mrs %0, "stringify(ICC_SRE_EL3)"\n" : "=r" (retc)); + + return retc; +} + +/**********************************************************************/ + +typedef enum +{ + igrpEnable = (1 << 0), + igrpEnableGrp1NS = (1 << 0), + igrpEnableGrp1S = (1 << 2) +} ICC_IGRPBits_t; + +static inline void setICC_IGRPEN0_EL1(ICC_IGRPBits_t mode) +{ + asm("msr "stringify(ICC_IGRPEN0_EL1)", %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline void setICC_IGRPEN1_EL1(ICC_IGRPBits_t mode) +{ + asm("msr "stringify(ICC_IGRPEN1_EL1)", %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline void setICC_IGRPEN1_EL3(ICC_IGRPBits_t mode) +{ + asm("msr "stringify(ICC_IGRPEN1_EL3)", %0\n; isb" :: "r" ((uint64_t)mode)); +} + +/**********************************************************************/ + +typedef enum +{ + ctlrCBPR = (1 << 0), + ctlrCBPR_EL1S = (1 << 0), + ctlrEOImode = (1 << 1), + ctlrCBPR_EL1NS = (1 << 1), + ctlrEOImode_EL3 = (1 << 2), + ctlrEOImode_EL1S = (1 << 3), + ctlrEOImode_EL1NS = (1 << 4), + ctlrRM = (1 << 5), + ctlrPMHE = (1 << 6) +} ICC_CTLRBits_t; + +static inline void setICC_CTLR_EL1(ICC_CTLRBits_t mode) +{ + asm("msr "stringify(ICC_CTLR_EL1)", %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline uint64_t getICC_CTLR_EL1(void) +{ + uint64_t retc; + + asm("mrs %0, "stringify(ICC_CTLR_EL1)"\n" : "=r" (retc)); + + return retc; +} + +static inline void setICC_CTLR_EL3(ICC_CTLRBits_t mode) +{ + asm("msr "stringify(ICC_CTLR_EL3)", %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline uint64_t getICC_CTLR_EL3(void) +{ + uint64_t retc; + + asm("mrs %0, "stringify(ICC_CTLR_EL3)"\n" : "=r" (retc)); + + return retc; +} + +/**********************************************************************/ + +static inline uint64_t getICC_IAR0(void) +{ + uint64_t retc; + + asm("mrs %0, "stringify(ICC_IAR0_EL1)"\n" : "=r" (retc)); + + return retc; +} + +static inline uint64_t getICC_IAR1(void) +{ + uint64_t retc; + + asm("mrs %0, "stringify(ICC_IAR1_EL1)"\n" : "=r" (retc)); + + return retc; +} + +static inline void setICC_EOIR0(uint32_t interrupt) +{ + asm("msr "stringify(ICC_EOIR0_EL1)", %0\n; isb" :: "r" ((uint64_t)interrupt)); +} + +static inline void setICC_EOIR1(uint32_t interrupt) +{ + asm("msr "stringify(ICC_EOIR1_EL1)", %0\n; isb" :: "r" ((uint64_t)interrupt)); +} + +static inline void setICC_DIR(uint32_t interrupt) +{ + asm("msr "stringify(ICC_DIR_EL1)", %0\n; isb" :: "r" ((uint64_t)interrupt)); +} + +static inline void setICC_PMR(uint32_t priority) +{ + asm("msr "stringify(ICC_PMR_EL1)", %0\n; isb" :: "r" ((uint64_t)priority)); +} + +static inline void setICC_BPR0(uint32_t binarypoint) +{ + asm("msr "stringify(ICC_BPR0_EL1)", %0\n; isb" :: "r" ((uint64_t)binarypoint)); +} + +static inline void setICC_BPR1(uint32_t binarypoint) +{ + asm("msr "stringify(ICC_BPR1_EL1)", %0\n; isb" :: "r" ((uint64_t)binarypoint)); +} + +static inline uint64_t getICC_BPR0(void) +{ + uint64_t retc; + + asm("mrs %0, "stringify(ICC_BPR0_EL1)"\n" : "=r" (retc)); + + return retc; +} + +static inline uint64_t getICC_BPR1(void) +{ + uint64_t retc; + + asm("mrs %0, "stringify(ICC_BPR1_EL1)"\n" : "=r" (retc)); + + return retc; +} + +static inline uint64_t getICC_RPR(void) +{ + uint64_t retc; + + asm("mrs %0, "stringify(ICC_RPR_EL1)"\n" : "=r" (retc)); + + return retc; +} + +/**********************************************************************/ + +typedef enum +{ + sgirIRMTarget = 0, + sgirIRMAll = (1ull << 40) +} ICC_SGIRBits_t; + +static inline void setICC_SGI0R(uint8_t aff3, uint8_t aff2, + uint8_t aff1, ICC_SGIRBits_t irm, + uint16_t targetlist, uint8_t intid) +{ + uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \ + ((uint64_t)aff1 << 16) | irm | targetlist | \ + ((uint64_t)(intid & 0x0f) << 24)); + + asm("msr "stringify(ICC_SGI0R_EL1)", %0\n; isb" :: "r" (packedbits)); +} + +static inline void setICC_SGI1R(uint8_t aff3, uint8_t aff2, + uint8_t aff1, ICC_SGIRBits_t irm, + uint16_t targetlist, uint8_t intid) +{ + uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \ + ((uint64_t)aff1 << 16) | irm | targetlist | \ + ((uint64_t)(intid & 0x0f) << 24)); + + asm("msr "stringify(ICC_SGI1R_EL1)", %0\n; isb" :: "r" (packedbits)); +} + +static inline void setICC_ASGI1R(uint8_t aff3, uint8_t aff2, + uint8_t aff1, ICC_SGIRBits_t irm, + uint16_t targetlist, uint8_t intid) +{ + uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \ + ((uint64_t)aff1 << 16) | irm | targetlist | \ + ((uint64_t)(intid & 0x0f) << 24)); + + asm("msr "stringify(ICC_ASGI1R_EL1)", %0\n; isb" :: "r" (packedbits)); +} + +#endif /* ndef GICV3_gicc_h */ diff --git a/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_gicd.c b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_gicd.c new file mode 100644 index 00000000..2cf9e843 --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_gicd.c @@ -0,0 +1,339 @@ +/* + * GICv3_gicd.c - generic driver code for GICv3 distributor + * + * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. + * Use, modification and redistribution of this file is subject to your possession of a + * valid End User License Agreement for the Arm Product of which these examples are part of + * and your compliance with all applicable terms and conditions of such licence agreement. + */ +#include + +#include "GICv3.h" + +typedef struct +{ + volatile uint32_t GICD_CTLR; // +0x0000 + const volatile uint32_t GICD_TYPER; // +0x0004 + const volatile uint32_t GICD_IIDR; // +0x0008 + + const volatile uint32_t padding0; // +0x000c + + volatile uint32_t GICD_STATUSR; // +0x0010 + + const volatile uint32_t padding1[3]; // +0x0014 + + volatile uint32_t IMP_DEF[8]; // +0x0020 + + volatile uint32_t GICD_SETSPI_NSR; // +0x0040 + const volatile uint32_t padding2; // +0x0044 + volatile uint32_t GICD_CLRSPI_NSR; // +0x0048 + const volatile uint32_t padding3; // +0x004c + volatile uint32_t GICD_SETSPI_SR; // +0x0050 + const volatile uint32_t padding4; // +0x0054 + volatile uint32_t GICD_CLRSPI_SR; // +0x0058 + + const volatile uint32_t padding5[3]; // +0x005c + + volatile uint32_t GICD_SEIR; // +0x0068 + + const volatile uint32_t padding6[5]; // +0x006c + + volatile uint32_t GICD_IGROUPR[32]; // +0x0080 + + volatile uint32_t GICD_ISENABLER[32]; // +0x0100 + volatile uint32_t GICD_ICENABLER[32]; // +0x0180 + volatile uint32_t GICD_ISPENDR[32]; // +0x0200 + volatile uint32_t GICD_ICPENDR[32]; // +0x0280 + volatile uint32_t GICD_ISACTIVER[32]; // +0x0300 + volatile uint32_t GICD_ICACTIVER[32]; // +0x0380 + + volatile uint8_t GICD_IPRIORITYR[1024]; // +0x0400 + volatile uint8_t GICD_ITARGETSR[1024]; // +0x0800 + volatile uint32_t GICD_ICFGR[64]; // +0x0c00 + volatile uint32_t GICD_IGRPMODR[32]; // +0x0d00 + const volatile uint32_t padding7[32]; // +0x0d80 + volatile uint32_t GICD_NSACR[64]; // +0x0e00 + + volatile uint32_t GICD_SGIR; // +0x0f00 + + const volatile uint32_t padding8[3]; // +0x0f04 + + volatile uint32_t GICD_CPENDSGIR[4]; // +0x0f10 + volatile uint32_t GICD_SPENDSGIR[4]; // +0x0f20 + + const volatile uint32_t padding9[52]; // +0x0f30 + const volatile uint32_t padding10[5120]; // +0x1000 + + volatile uint64_t GICD_IROUTER[1024]; // +0x6000 +} GICv3_distributor; + +/* + * use the scatter file to place GICD + */ +GICv3_distributor __attribute__((section(".gicd"))) gicd; + +void ConfigGICD(GICDCTLRFlags_t flags) +{ + gicd.GICD_CTLR = flags; +} + +void EnableGICD(GICDCTLRFlags_t flags) +{ + gicd.GICD_CTLR |= flags; +} + +void DisableGICD(GICDCTLRFlags_t flags) +{ + gicd.GICD_CTLR &= ~flags; +} + +void SyncAREinGICD(GICDCTLRFlags_t flags, uint32_t dosync) +{ + if (dosync) + { + const uint32_t tmask = gicdctlr_ARE_S | gicdctlr_ARE_NS; + const uint32_t tval = flags & tmask; + + while ((gicd.GICD_CTLR & tmask) != tval) + continue; + } + else + gicd.GICD_CTLR = flags; +} + +void EnableSPI(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_ISENABLER has 32 interrupts per register + */ + bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); + id &= 32 - 1; + + gicd.GICD_ISENABLER[bank] = 1 << id; + + return; +} + +void DisableSPI(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_ISENABLER has 32 interrupts per register + */ + bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); + id &= 32 - 1; + + gicd.GICD_ICENABLER[bank] = 1 << id; + + return; +} + +void SetSPIPriority(uint32_t id, uint32_t priority) +{ + uint32_t bank; + + /* + * GICD_IPRIORITYR has one byte-wide entry per interrupt + */ + bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR); + + gicd.GICD_IPRIORITYR[bank] = priority; +} + +uint32_t GetSPIPriority(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_IPRIORITYR has one byte-wide entry per interrupt + */ + bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR); + + return (uint32_t)(gicd.GICD_IPRIORITYR[bank]); +} + +void SetSPIRoute(uint32_t id, uint64_t affinity, GICDIROUTERBits_t mode) +{ + uint32_t bank; + + /* + * GICD_IROUTER has one doubleword-wide entry per interrupt + */ + bank = id & RANGE_LIMIT(gicd.GICD_IROUTER); + + gicd.GICD_IROUTER[bank] = affinity | (uint64_t)mode; +} + +uint64_t GetSPIRoute(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_IROUTER has one doubleword-wide entry per interrupt + */ + bank = id & RANGE_LIMIT(gicd.GICD_IROUTER); + + return gicd.GICD_IROUTER[bank]; +} + +void SetSPITarget(uint32_t id, uint32_t target) +{ + uint32_t bank; + + /* + * GICD_ITARGETSR has one byte-wide entry per interrupt + */ + bank = id & RANGE_LIMIT(gicd.GICD_ITARGETSR); + + gicd.GICD_ITARGETSR[bank] = target; +} + +uint32_t GetSPITarget(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_ITARGETSR has one byte-wide entry per interrupt + */ + /* + * GICD_ITARGETSR has 4 interrupts per register, i.e. 8-bits of + * target bitmap per register + */ + bank = id & RANGE_LIMIT(gicd.GICD_ITARGETSR); + + return (uint32_t)(gicd.GICD_ITARGETSR[bank]); +} + +void ConfigureSPI(uint32_t id, GICDICFGRBits_t config) +{ + uint32_t bank, tmp; + + /* + * GICD_ICFGR has 16 interrupts per register, i.e. 2-bits of + * configuration per register + */ + bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); + config &= 3; + + id = (id & 0xf) << 1; + + tmp = gicd.GICD_ICFGR[bank]; + tmp &= ~(3 << id); + tmp |= config << id; + gicd.GICD_ICFGR[bank] = tmp; +} + +void SetSPIPending(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_ISPENDR has 32 interrupts per register + */ + bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISPENDR); + id &= 0x1f; + + gicd.GICD_ISPENDR[bank] = 1 << id; +} + +void ClearSPIPending(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_ICPENDR has 32 interrupts per register + */ + bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICPENDR); + id &= 0x1f; + + gicd.GICD_ICPENDR[bank] = 1 << id; +} + +uint32_t GetSPIPending(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_ICPENDR has 32 interrupts per register + */ + bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICPENDR); + id &= 0x1f; + + return (gicd.GICD_ICPENDR[bank] >> id) & 1; +} + +void SetSPISecurity(uint32_t id, GICIGROUPRBits_t group) +{ + uint32_t bank, groupmod; + + /* + * GICD_IGROUPR has 32 interrupts per register + */ + bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_IGROUPR); + id &= 0x1f; + + /* + * the single group argument is split into two separate + * registers, so filter out and remove the (new to gicv3) + * group modifier bit + */ + groupmod = (group >> 1) & 1; + group &= 1; + + /* + * either set or clear the Group bit for the interrupt as appropriate + */ + if (group) + gicd.GICD_IGROUPR[bank] |= 1 << id; + else + gicd.GICD_IGROUPR[bank] &= ~(1 << id); + + /* + * now deal with groupmod + */ + if (groupmod) + gicd.GICD_IGRPMODR[bank] |= 1 << id; + else + gicd.GICD_IGRPMODR[bank] &= ~(1 << id); +} + +void SetSPISecurityBlock(uint32_t block, GICIGROUPRBits_t group) +{ + uint32_t groupmod; + const uint32_t nbits = (sizeof group * 8) - 1; + + /* + * GICD_IGROUPR has 32 interrupts per register + */ + block &= RANGE_LIMIT(gicd.GICD_IGROUPR); + + /* + * get each bit of group config duplicated over all 32-bits in a word + */ + groupmod = (uint32_t)(((int32_t)group << (nbits - 1)) >> 31); + group = (uint32_t)(((int32_t)group << nbits) >> 31); + + /* + * set the security state for this block of SPIs + */ + gicd.GICD_IGROUPR[block] = group; + gicd.GICD_IGRPMODR[block] = groupmod; +} + +void SetSPISecurityAll(GICIGROUPRBits_t group) +{ + uint32_t block; + + /* + * GICD_TYPER.ITLinesNumber gives (No. SPIS / 32) - 1, and we + * want to iterate over all blocks excluding 0 (which are the + * SGI/PPI interrupts, and not relevant here) + */ + for (block = (gicd.GICD_TYPER & ((1 << 5) - 1)); block > 0; --block) + SetSPISecurityBlock(block, group); +} + +/* EOF GICv3_gicd.c */ diff --git a/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_gicr.c b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_gicr.c new file mode 100644 index 00000000..ef5c8925 --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_gicr.c @@ -0,0 +1,289 @@ +/* + * GICv3_gicr.c - generic driver code for GICv3 redistributor + * + * Copyright (c) 2014-2018 Arm Limited (or its affiliates). All rights reserved. + * Use, modification and redistribution of this file is subject to your possession of a + * valid End User License Agreement for the Arm Product of which these examples are part of + * and your compliance with all applicable terms and conditions of such licence agreement. + */ +#include "GICv3.h" + +/* + * physical LPI Redistributor register map + */ +typedef struct +{ + volatile uint32_t GICR_CTLR; // +0x0000 - RW - Redistributor Control Register + const volatile uint32_t GICR_IIDR; // +0x0004 - RO - Implementer Identification Register + const volatile uint32_t GICR_TYPER[2]; // +0x0008 - RO - Redistributor Type Register + volatile uint32_t GICR_STATUSR; // +0x0010 - RW - Error Reporting Status Register, optional + volatile uint32_t GICR_WAKER; // +0x0014 - RW - Redistributor Wake Register + const volatile uint32_t padding1[2]; // +0x0018 - RESERVED +#ifndef USE_GIC600 + volatile uint32_t IMPDEF1[8]; // +0x0020 - ?? - IMPLEMENTATION DEFINED +#else + volatile uint32_t GICR_FCTLR; // +0x0020 - RW - Function Control Register + volatile uint32_t GICR_PWRR; // +0x0024 - RW - Power Management Control Register + volatile uint32_t GICR_CLASS; // +0x0028 - RW - Class Register + const volatile uint32_t padding2[5]; // +0x002C - RESERVED +#endif + volatile uint64_t GICR_SETLPIR; // +0x0040 - WO - Set LPI Pending Register + volatile uint64_t GICR_CLRLPIR; // +0x0048 - WO - Clear LPI Pending Register + const volatile uint32_t padding3[8]; // +0x0050 - RESERVED + volatile uint64_t GICR_PROPBASER; // +0x0070 - RW - Redistributor Properties Base Address Register + volatile uint64_t GICR_PENDBASER; // +0x0078 - RW - Redistributor LPI Pending Table Base Address Register + const volatile uint32_t padding4[8]; // +0x0080 - RESERVED + volatile uint64_t GICR_INVLPIR; // +0x00A0 - WO - Redistributor Invalidate LPI Register + const volatile uint32_t padding5[2]; // +0x00A8 - RESERVED + volatile uint64_t GICR_INVALLR; // +0x00B0 - WO - Redistributor Invalidate All Register + const volatile uint32_t padding6[2]; // +0x00B8 - RESERVED + volatile uint64_t GICR_SYNCR; // +0x00C0 - RO - Redistributor Synchronize Register + const volatile uint32_t padding7[2]; // +0x00C8 - RESERVED + const volatile uint32_t padding8[12]; // +0x00D0 - RESERVED + volatile uint64_t IMPDEF2; // +0x0100 - WO - IMPLEMENTATION DEFINED + const volatile uint32_t padding9[2]; // +0x0108 - RESERVED + volatile uint64_t IMPDEF3; // +0x0110 - WO - IMPLEMENTATION DEFINED + const volatile uint32_t padding10[2]; // +0x0118 - RESERVED +} GICv3_redistributor_RD; + +/* + * SGI and PPI Redistributor register map + */ +typedef struct +{ + const volatile uint32_t padding1[32]; // +0x0000 - RESERVED + volatile uint32_t GICR_IGROUPR0; // +0x0080 - RW - Interrupt Group Registers (Security Registers in GICv1) + const volatile uint32_t padding2[31]; // +0x0084 - RESERVED + volatile uint32_t GICR_ISENABLER; // +0x0100 - RW - Interrupt Set-Enable Registers + const volatile uint32_t padding3[31]; // +0x0104 - RESERVED + volatile uint32_t GICR_ICENABLER; // +0x0180 - RW - Interrupt Clear-Enable Registers + const volatile uint32_t padding4[31]; // +0x0184 - RESERVED + volatile uint32_t GICR_ISPENDR; // +0x0200 - RW - Interrupt Set-Pending Registers + const volatile uint32_t padding5[31]; // +0x0204 - RESERVED + volatile uint32_t GICR_ICPENDR; // +0x0280 - RW - Interrupt Clear-Pending Registers + const volatile uint32_t padding6[31]; // +0x0284 - RESERVED + volatile uint32_t GICR_ISACTIVER; // +0x0300 - RW - Interrupt Set-Active Register + const volatile uint32_t padding7[31]; // +0x0304 - RESERVED + volatile uint32_t GICR_ICACTIVER; // +0x0380 - RW - Interrupt Clear-Active Register + const volatile uint32_t padding8[31]; // +0x0184 - RESERVED + volatile uint8_t GICR_IPRIORITYR[32]; // +0x0400 - RW - Interrupt Priority Registers + const volatile uint32_t padding9[504]; // +0x0420 - RESERVED + volatile uint32_t GICR_ICnoFGR[2]; // +0x0C00 - RW - Interrupt Configuration Registers + const volatile uint32_t padding10[62]; // +0x0C08 - RESERVED + volatile uint32_t GICR_IGRPMODR0; // +0x0D00 - RW - ???? + const volatile uint32_t padding11[63]; // +0x0D04 - RESERVED + volatile uint32_t GICR_NSACR; // +0x0E00 - RW - Non-Secure Access Control Register +} GICv3_redistributor_SGI; + +/* + * We have a multiplicity of GIC Redistributors; on the GIC-AEM and + * GIC-500 they are arranged as one 128KB region per redistributor: one + * 64KB page of GICR LPI registers, and one 64KB page of GICR Private + * Int registers + */ +typedef struct +{ + union + { + GICv3_redistributor_RD RD_base; + uint8_t padding[64 * 1024]; + } RDblock; + + union + { + GICv3_redistributor_SGI SGI_base; + uint8_t padding[64 * 1024]; + } SGIblock; +} GICv3_GICR; + +/* + * use the scatter file to place GIC Redistributor base address + * + * although this code doesn't know how many Redistributor banks + * a particular system will have, we declare gicrbase as an array + * to avoid unwanted compiler optimisations when calculating the + * base of a particular Redistributor bank + */ +static const GICv3_GICR gicrbase[2] __attribute__((section (".gicr"))); + +/**********************************************************************/ + +/* + * utility functions to calculate base of a particular + * Redistributor bank + */ + +static inline GICv3_redistributor_RD *const getgicrRD(uint32_t gicr) +{ + GICv3_GICR *const arraybase = (GICv3_GICR *const)&gicrbase; + + return &((arraybase + gicr)->RDblock.RD_base); +} + +static inline GICv3_redistributor_SGI *const getgicrSGI(uint32_t gicr) +{ + GICv3_GICR *arraybase = (GICv3_GICR *)(&gicrbase); + + return &(arraybase[gicr].SGIblock.SGI_base); +} + +/**********************************************************************/ + +void WakeupGICR(uint32_t gicr) +{ + GICv3_redistributor_RD *const gicrRD = getgicrRD(gicr); +#ifdef USE_GIC600 + //Power up Re-distributor for GIC-600 + gicrRD->GICR_PWRR = 0x2; +#endif + + /* + * step 1 - ensure GICR_WAKER.ProcessorSleep is off + */ + gicrRD->GICR_WAKER &= ~gicrwaker_ProcessorSleep; + + /* + * step 2 - wait for children asleep to be cleared + */ + while ((gicrRD->GICR_WAKER & gicrwaker_ChildrenAsleep) != 0) + continue; + + /* + * OK, GICR is go + */ + return; +} + +void EnablePrivateInt(uint32_t gicr, uint32_t id) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + id &= 0x1f; + + gicrSGI->GICR_ISENABLER = 1 << id; +} + +void DisablePrivateInt(uint32_t gicr, uint32_t id) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + id &= 0x1f; + + gicrSGI->GICR_ICENABLER = 1 << id; +} + +void SetPrivateIntPriority(uint32_t gicr, uint32_t id, uint32_t priority) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + /* + * GICD_IPRIORITYR has one byte-wide entry per interrupt + */ + id &= RANGE_LIMIT(gicrSGI->GICR_IPRIORITYR); + + gicrSGI->GICR_IPRIORITYR[id] = priority; +} + +uint32_t GetPrivateIntPriority(uint32_t gicr, uint32_t id) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + /* + * GICD_IPRIORITYR has one byte-wide entry per interrupt + */ + id &= RANGE_LIMIT(gicrSGI->GICR_IPRIORITYR); + + return (uint32_t)(gicrSGI->GICR_IPRIORITYR[id]); +} + +void SetPrivateIntPending(uint32_t gicr, uint32_t id) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + /* + * GICR_ISPENDR is one 32-bit register + */ + id &= 0x1f; + + gicrSGI->GICR_ISPENDR = 1 << id; +} + +void ClearPrivateIntPending(uint32_t gicr, uint32_t id) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + /* + * GICR_ICPENDR is one 32-bit register + */ + id &= 0x1f; + + gicrSGI->GICR_ICPENDR = 1 << id; +} + +uint32_t GetPrivateIntPending(uint32_t gicr, uint32_t id) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + /* + * GICR_ISPENDR is one 32-bit register + */ + id &= 0x1f; + + return (gicrSGI->GICR_ISPENDR >> id) & 0x01; +} + +void SetPrivateIntSecurity(uint32_t gicr, uint32_t id, GICIGROUPRBits_t group) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + uint32_t groupmod; + + /* + * GICR_IGROUPR0 is one 32-bit register + */ + id &= 0x1f; + + /* + * the single group argument is split into two separate + * registers, so filter out and remove the (new to gicv3) + * group modifier bit + */ + groupmod = (group >> 1) & 1; + group &= 1; + + /* + * either set or clear the Group bit for the interrupt as appropriate + */ + if (group) + gicrSGI->GICR_IGROUPR0 |= 1 << id; + else + gicrSGI->GICR_IGROUPR0 &= ~(1 << id); + + /* + * now deal with groupmod + */ + if (groupmod) + gicrSGI->GICR_IGRPMODR0 |= 1 << id; + else + gicrSGI->GICR_IGRPMODR0 &= ~(1 << id); +} + +void SetPrivateIntSecurityBlock(uint32_t gicr, GICIGROUPRBits_t group) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + const uint32_t nbits = (sizeof group * 8) - 1; + uint32_t groupmod; + + /* + * get each bit of group config duplicated over all 32 bits + */ + groupmod = (uint32_t)(((int32_t)group << (nbits - 1)) >> 31); + group = (uint32_t)(((int32_t)group << nbits) >> 31); + + /* + * set the security state for this block of SPIs + */ + gicrSGI->GICR_IGROUPR0 = group; + gicrSGI->GICR_IGRPMODR0 = groupmod; +} + +/* EOF GICv3_gicr.c */ diff --git a/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/MP_Mutexes.S b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/MP_Mutexes.S new file mode 100644 index 00000000..77fa0a0f --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/MP_Mutexes.S @@ -0,0 +1,86 @@ +// +// Armv8-A AArch64 - Basic Mutex Example +// +// Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// + + + .text + .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + + + .global _mutex_initialize + .global _mutex_acquire + .global _mutex_release + +// +// These routines implement the mutex management functions required for running +// the Arm C library in a multi-threaded environment. +// +// They use a value of 0 to represent an unlocked mutex, and 1 for a locked mutex +// +// ********************************************************************** +// + + .type _mutex_initialize, "function" + .cfi_startproc +_mutex_initialize: + + // + // mark the mutex as unlocked + // + mov w1, #0 + str w1, [x0] + + // + // we are running multi-threaded, so set a non-zero return + // value (function prototype says use 1) + // + mov w0, #1 + ret + .cfi_endproc + + + .type _mutex_acquire, "function" + .cfi_startproc +_mutex_acquire: + + // + // send ourselves an event, so we don't stick on the wfe at the + // top of the loop + // + sevl + + // + // wait until the mutex is available + // +loop: + wfe + ldaxr w1, [x0] + cbnz w1, loop + + // + // mutex is (at least, it was) available - try to claim it + // + mov w1, #1 + stxr w2, w1, [x0] + cbnz w2, loop + + // + // OK, we have the mutex, our work is done here + // + ret + .cfi_endproc + + + .type _mutex_release, "function" + .cfi_startproc +_mutex_release: + + mov w1, #0 + stlr w1, [x0] + ret + .cfi_endproc diff --git a/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/PPM_AEM.h b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/PPM_AEM.h new file mode 100644 index 00000000..52c9a0fe --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/PPM_AEM.h @@ -0,0 +1,66 @@ +// +// Private Peripheral Map for the v8 Architecture Envelope Model +// +// Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// + +#ifndef PPM_AEM_H +#define PPM_AEM_H + +// +// Distributor layout +// +#define GICD_CTLR 0x0000 +#define GICD_TYPER 0x0004 +#define GICD_IIDR 0x0008 +#define GICD_IGROUP 0x0080 +#define GICD_ISENABLE 0x0100 +#define GICD_ICENABLE 0x0180 +#define GICD_ISPEND 0x0200 +#define GICD_ICPEND 0x0280 +#define GICD_ISACTIVE 0x0300 +#define GICD_ICACTIVE 0x0380 +#define GICD_IPRIORITY 0x0400 +#define GICD_ITARGETS 0x0800 +#define GICD_ICFG 0x0c00 +#define GICD_PPISR 0x0d00 +#define GICD_SPISR 0x0d04 +#define GICD_SGIR 0x0f00 +#define GICD_CPENDSGI 0x0f10 +#define GICD_SPENDSGI 0x0f20 +#define GICD_PIDR4 0x0fd0 +#define GICD_PIDR5 0x0fd4 +#define GICD_PIDR6 0x0fd8 +#define GICD_PIDR7 0x0fdc +#define GICD_PIDR0 0x0fe0 +#define GICD_PIDR1 0x0fe4 +#define GICD_PIDR2 0x0fe8 +#define GICD_PIDR3 0x0fec +#define GICD_CIDR0 0x0ff0 +#define GICD_CIDR1 0x0ff4 +#define GICD_CIDR2 0x0ff8 +#define GICD_CIDR3 0x0ffc + +// +// CPU Interface layout +// +#define GICC_CTLR 0x0000 +#define GICC_PMR 0x0004 +#define GICC_BPR 0x0008 +#define GICC_IAR 0x000c +#define GICC_EOIR 0x0010 +#define GICC_RPR 0x0014 +#define GICC_HPPIR 0x0018 +#define GICC_ABPR 0x001c +#define GICC_AIAR 0x0020 +#define GICC_AEOIR 0x0024 +#define GICC_AHPPIR 0x0028 +#define GICC_APR0 0x00d0 +#define GICC_NSAPR0 0x00e0 +#define GICC_IIDR 0x00fc +#define GICC_DIR 0x1000 + +#endif // PPM_AEM_H diff --git a/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.c new file mode 100644 index 00000000..b37d9d6f --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.c @@ -0,0 +1,389 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" +#include + +extern void init_timer(void); /* in timer_interrupts.c */ + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 0x20000 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define a memory area to create a byte pool in. */ + +UCHAR memory_area[DEMO_BYTE_POOL_SIZE] __attribute__((aligned (8))); + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_TIMER timer_0; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +#ifdef TX_ENABLE_EVENT_TRACE + +UCHAR event_buffer[65536]; + +#endif + + +int main(void) +{ + + /* Initialize timer. */ + init_timer(); + + /* Enter ThreadX. */ + tx_kernel_enter(); + + return 0; +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer; + + +#ifdef TX_ENABLE_EVENT_TRACE + + tx_trace_enable(event_buffer, sizeof(event_buffer), 32); +#endif + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEMO_BYTE_POOL_SIZE); + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + diff --git a/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.launch b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.launch new file mode 100644 index 00000000..cc8488d6 --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.launch @@ -0,0 +1,427 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.ld b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.ld new file mode 100644 index 00000000..e9b12a82 --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.ld @@ -0,0 +1,245 @@ +/* Linker script to place sections and symbol values. + * It references following symbols, which must be defined in code: + * start64 : Entry point + * + * It defines following symbols, which code can use without definition: + * __cs3_peripherals + * __code_start + * __exidx_start + * __exidx_end + * __data_start + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __bss_start__ + * __bss_end__ + * __end__ + * __stack + * __el3_stack + * __ttb0_l1 + * __ttb0_l2_ram + * __ttb0_l2_private + * __ttb0_l2_periph + * __top_of_ram + */ + +ENTRY(start64) + +SECTIONS +{ + /* + * CS3 Peripherals is a 64MB region from 0x1c000000 + * that includes the following: + * System Registers at 0x1C010000 + * UART0 (PL011) at 0x1C090000 + * Color LCD Controller (PL111) at 0x1C1F0000 + * plus a number of others. + * CS3_PERIPHERALS is used by the startup code for page-table generation + * This region is not truly empty, but we have no + * predefined objects that live within it + */ + __cs3_peripherals = 0x1c000000; + + /* + * GICv3 distributor + */ + .gicd 0x2f000000 (NOLOAD): + { + *(.gicd) + } + + /* + * GICv3 redistributors + * 128KB for each redistributor in the system + */ + .gicr 0x2f100000 (NOLOAD): + { + *(.gicr) + } + + .vectors 0x80000000: + { + __code_start = .; + KEEP(*(StartUp)) + KEEP(*(EL1VECTORS EL2VECTORS EL3VECTORS)) + } + + .init : + { + KEEP (*(SORT_NONE(.init))) + } + + .text : + { + *(.text*) + } + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } + + .rodata : + { + *(.rodata .rodata.* .gnu.linkonce.r.*) + } + + .eh_frame : + { + KEEP (*(.eh_frame)) + } + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } + + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array )) + PROVIDE_HIDDEN (__init_array_end = .); + } + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array )) + PROVIDE_HIDDEN (__fini_array_end = .); + } + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } + + .jcr : + { + KEEP (*(.jcr)) + } + + .data : + { + __data_start = . ; + *(.data .data.* .gnu.linkonce.d.*) + SORT(CONSTRUCTORS) + } + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } + + .heap (NOLOAD): + { + . = ALIGN(64); + __end__ = .; + PROVIDE(end = .); + . = . + 0x1000; + } + + .stack (NOLOAD): + { + . = ALIGN(64); + . = . + 4 * 0x8000; + __stack = .; + } + + .handler_stack_limit (NOLOAD): + { + . = ALIGN(64); + . = . + 4 * 0x4000; + handler_stack_limit = .; + } + + .el3_stack (NOLOAD): + { + . = ALIGN(64); + . = . + 4 * 0x1000; + __el3_stack = .; + } + + .ttb0_l1 (NOLOAD): + { + . = ALIGN(4096); + __ttb0_l1 = .; + . = . + 0x1000; + } + + .ttb0_l2_ram (NOLOAD): + { + . = ALIGN(4096); + __ttb0_l2_ram = .; + . = . + 0x1000; + } + + .ttb0_l2_private (NOLOAD): + { + . = ALIGN(4096); + __ttb0_l2_private = .; + . = . + 0x1000; + } + + .ttb0_l2_periph (NOLOAD): + { + . = ALIGN(4096); + __ttb0_l2_periph = .; + . = . + 0x1000; + } + + /* + * The startup code uses the end of this region to calculate + * the top of memory - don't place any RAM regions after it + */ + __top_of_ram = .; +} diff --git a/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/sp804_timer.c b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/sp804_timer.c new file mode 100644 index 00000000..4dc009b2 --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/sp804_timer.c @@ -0,0 +1,122 @@ +// ------------------------------------------------------------ +// SP804 Dual Timer +// +// Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#include "sp804_timer.h" + +#define TIMER_SP804_CTRL_TIMEREN (1 << 7) +#define TIMER_SP804_CTRL_TIMERMODE (1 << 6) // Bit 6: +#define TIMER_SP804_CTRL_INTENABLE (1 << 5) +#define TIMER_SP804_CTRL_TIMERSIZE (1 << 1) // Bit 1: 0=16-bit, 1=32-bit +#define TIMER_SP804_CTRL_ONESHOT (1 << 0) // Bit 0: 0=wrapping, 1=one-shot + +#define TIMER_SP804_CTRL_PRESCALE_1 (0 << 2) // clk/1 +#define TIMER_SP804_CTRL_PRESCALE_4 (1 << 2) // clk/4 +#define TIMER_SP804_CTRL_PRESCALE_8 (2 << 2) // clk/8 + +struct sp804_timer +{ + volatile uint32_t Time1Load; // +0x00 + const volatile uint32_t Time1Value; // +0x04 - RO + volatile uint32_t Timer1Control; // +0x08 + volatile uint32_t Timer1IntClr; // +0x0C - WO + const volatile uint32_t Timer1RIS; // +0x10 - RO + const volatile uint32_t Timer1MIS; // +0x14 - RO + volatile uint32_t Timer1BGLoad; // +0x18 + + volatile uint32_t Time2Load; // +0x20 + volatile uint32_t Time2Value; // +0x24 + volatile uint8_t Timer2Control; // +0x28 + volatile uint32_t Timer2IntClr; // +0x2C - WO + const volatile uint32_t Timer2RIS; // +0x30 - RO + const volatile uint32_t Timer2MIS; // +0x34 - RO + volatile uint32_t Timer2BGLoad; // +0x38 + + // Not including ID registers + +}; + +// Instance of the dual timer, will be placed using the scatter file +struct sp804_timer* dual_timer; + + +// Set base address of timer +// address - virtual address of SP804 timer +void setTimerBaseAddress(uint64_t address) +{ + dual_timer = (struct sp804_timer*)address; + return; +} + + +// Sets up the private timer +// load_value - Initial value of timer +// auto_reload - Periodic (SP804_AUTORELOAD) or one shot (SP804_SINGLESHOT) +// interrupt - Whether to generate an interrupt +void initTimer(uint32_t load_value, uint32_t auto_reload, uint32_t interrupt) +{ + uint32_t tmp = 0; + + dual_timer->Time1Load = load_value; + + // Fixed setting: 32-bit, no prescaling + tmp = TIMER_SP804_CTRL_TIMERSIZE | TIMER_SP804_CTRL_PRESCALE_1 | TIMER_SP804_CTRL_TIMERMODE; + + // Settings from parameters: interrupt generation & reload + tmp = tmp | interrupt | auto_reload; + + // Write control register + dual_timer->Timer1Control = tmp; + + return; +} + + +// Starts the timer +void startTimer(void) +{ + uint32_t tmp; + + tmp = dual_timer->Timer1Control; + tmp = tmp | TIMER_SP804_CTRL_TIMEREN; // Set TimerEn (bit 7) + dual_timer->Timer1Control = tmp; + + return; +} + + +// Stops the timer +void stopTimer(void) +{ + uint32_t tmp; + + tmp = dual_timer->Timer1Control; + tmp = tmp & ~TIMER_SP804_CTRL_TIMEREN; // Clear TimerEn (bit 7) + dual_timer->Timer1Control = tmp; + + return; +} + + +// Returns the current timer count +uint32_t getTimerCount(void) +{ + return dual_timer->Time1Value; +} + + +void clearTimerIrq(void) +{ + // A write to this register, of any value, clears the interrupt + dual_timer->Timer1IntClr = 1; +} + + +// ------------------------------------------------------------ +// End of sp804_timer.c +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/sp804_timer.h b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/sp804_timer.h new file mode 100644 index 00000000..777062cc --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/sp804_timer.h @@ -0,0 +1,53 @@ +// ------------------------------------------------------------ +// SP804 Dual Timer +// Header Filer +// +// Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#ifndef _SP804_TIMER_ +#define _SP804_TIMER_ + +#include + +// Set base address of timer +// address - virtual address of SP804 timer +void setTimerBaseAddress(uint64_t address); + + +// Sets up the private timer +// load_value - Initial value of timer +// auto_reload - Periodic (SP804_AUTORELOAD) or one shot (SP804_SINGLESHOT) +// interrupt - Whether to generate an interrupt + +#define SP804_AUTORELOAD (0) +#define SP804_SINGLESHOT (1) +#define SP804_GENERATE_IRQ (1 << 5) +#define SP804_NO_IRQ (0) + +void initTimer(uint32_t load_value, uint32_t auto_reload, uint32_t interrupt); + + +// Starts the timer +void startTimer(void); + + +// Stops the timer +void stopTimer(void); + + +// Returns the current timer count +uint32_t getTimerCount(void); + + +// Clears the timer interrupt +void clearTimerIrq(void); + +#endif + +// ------------------------------------------------------------ +// End of sp804_timer.h +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/startup.S b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/startup.S new file mode 100644 index 00000000..53f02e37 --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/startup.S @@ -0,0 +1,798 @@ +// ------------------------------------------------------------ +// Armv8-A MPCore EL3 AArch64 Startup Code +// +// Basic Vectors, MMU, caches and GICv3 initialization +// +// Exits in EL1 AArch64 +// +// Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#include "v8_mmu.h" +#include "v8_system.h" +#include "GICv3_aliases.h" + + .section StartUp, "ax" + .balign 4 + + + .global el1_vectors + .global el2_vectors + .global el3_vectors + + .global InvalidateUDCaches + .global ZeroBlock + + .global SetPrivateIntSecurityBlock + .global SetSPISecurityAll + .global SetPrivateIntPriority + + .global WakeupGICR + .global SyncAREinGICD + .global EnableGICD + .global EnablePrivateInt + .global GetPrivateIntPending + .global ClearPrivateIntPending + + .global _start + .global MainApp + + .global __code_start + .global __ttb0_l1 + .global __ttb0_l2_ram + .global __ttb0_l2_periph + .global __top_of_ram + .global gicd + .global __stack + .global __el3_stack + .global __cs3_peripherals + +is_mmu_ready: +.word 0 + + +// ------------------------------------------------------------ + + .global start64 + .type start64, "function" +start64: + + // + // program the VBARs + // + ldr x1, =el1_vectors + msr VBAR_EL1, x1 + + ldr x1, =el2_vectors + msr VBAR_EL2, x1 + + ldr x1, =el3_vectors + msr VBAR_EL3, x1 + + + // GIC-500 comes out of reset in GICv2 compatibility mode - first set + // system register enables for all relevant exception levels, and + // select GICv3 operating mode + // + msr SCR_EL3, xzr // Ensure NS bit is initially clear, so secure copy of ICC_SRE_EL1 can be configured + isb + + mov x0, #15 + msr ICC_SRE_EL3, x0 + isb + msr ICC_SRE_EL1, x0 // Secure copy of ICC_SRE_EL1 + + // + // set lower exception levels as non-secure, with no access + // back to EL2 or EL3, and are AArch64 capable + // + mov x3, #(SCR_EL3_RW | \ + SCR_EL3_SMD | \ + SCR_EL3_NS) // Set NS bit, to access Non-secure registers + msr SCR_EL3, x3 + isb + + mov x0, #15 + msr ICC_SRE_EL2, x0 + isb + msr ICC_SRE_EL1, x0 // Non-secure copy of ICC_SRE_EL1 + + + // + // no traps or VM modifications from the Hypervisor, EL1 is AArch64 + // + mov x2, #HCR_EL2_RW + msr HCR_EL2, x2 + + // + // VMID is still significant, even when virtualisation is not + // being used, so ensure VTTBR_EL2 is properly initialised + // + msr VTTBR_EL2, xzr + + // + // VMPIDR_EL2 holds the value of the Virtualization Multiprocessor ID. This is the value returned by Non-secure EL1 reads of MPIDR_EL1. + // VPIDR_EL2 holds the value of the Virtualization Processor ID. This is the value returned by Non-secure EL1 reads of MIDR_EL1. + // Both of these registers are architecturally UNKNOWN at reset, and so they must be set to the correct value + // (even if EL2/virtualization is not being used), otherwise non-secure EL1 reads of MPIDR_EL1/MIDR_EL1 will return garbage values. + // This guarantees that any future reads of MPIDR_EL1 and MIDR_EL1 from Non-secure EL1 will return the correct value. + // + mrs x0, MPIDR_EL1 + msr VMPIDR_EL2, x0 + mrs x0, MIDR_EL1 + msr VPIDR_EL2, x0 + + // extract the core number from MPIDR_EL1 and store it in + // x19 (defined by the AAPCS as callee-saved), so we can re-use + // the number later + // + bl GetCPUID + mov x19, x0 + + // + // neither EL3 nor EL2 trap floating point or accesses to CPACR + // + msr CPTR_EL3, xzr + msr CPTR_EL2, xzr + + // + // SCTLR_ELx may come out of reset with UNKNOWN values so we will + // set the fields to 0 except, possibly, the endianess field(s). + // Note that setting SCTLR_EL2 or the EL0 related fields of SCTLR_EL1 + // is not strictly needed, since we're never in EL2 or EL0 + // +#ifdef __ARM_BIG_ENDIAN + mov x0, #(SCTLR_ELx_EE | SCTLR_EL1_E0E) +#else + mov x0, #0 +#endif + msr SCTLR_EL3, x0 + msr SCTLR_EL2, x0 + msr SCTLR_EL1, x0 + +#ifdef CORTEXA + // + // Configure ACTLR_EL[23] + // ---------------------- + // + // These bits are IMPLEMENTATION DEFINED, so are different for + // different processors + // + // For Cortex-A57, the controls we set are: + // + // Enable lower level access to CPUACTLR_EL1 + // Enable lower level access to CPUECTLR_EL1 + // Enable lower level access to L2CTLR_EL1 + // Enable lower level access to L2ECTLR_EL1 + // Enable lower level access to L2ACTLR_EL1 + // + mov x0, #((1 << 0) | \ + (1 << 1) | \ + (1 << 4) | \ + (1 << 5) | \ + (1 << 6)) + + msr ACTLR_EL3, x0 + msr ACTLR_EL2, x0 + + // + // configure CPUECTLR_EL1 + // + // These bits are IMP DEF, so need to different for different + // processors + // + // SMPEN - bit 6 - Enables the processor to receive cache + // and TLB maintenance operations + // + // Note: For Cortex-A57/53 SMPEN should be set before enabling + // the caches and MMU, or performing any cache and TLB + // maintenance operations. + // + // This register has a defined reset value, so we use a + // read-modify-write sequence to set SMPEN + // + mrs x0, S3_1_c15_c2_1 // Read EL1 CPU Extended Control Register + orr x0, x0, #(1 << 6) // Set the SMPEN bit + msr S3_1_c15_c2_1, x0 // Write EL1 CPU Extended Control Register + + isb +#endif + + // + // That's the last of the control settings for now + // + // Note: no ISB after all these changes, as registers won't be + // accessed until after an exception return, which is itself a + // context synchronisation event + // + + // + // Setup some EL3 stack space, ready for calling some subroutines, below. + // + // Stack space allocation is CPU-specific, so use CPU + // number already held in x19 + // + // 2^12 bytes per CPU for the EL3 stacks + // + ldr x0, =__el3_stack + sub x0, x0, x19, lsl #12 + mov sp, x0 + + // + // we need to configure the GIC while still in secure mode, specifically + // all PPIs and SPIs have to be programmed as Group1 interrupts + // + + // + // Before the GIC can be reliably programmed, we need to + // enable Affinity Routing, as this affects where the configuration + // registers are (with Affinity Routing enabled, some registers are + // in the Redistributor, whereas those same registers are in the + // Distributor with Affinity Routing disabled (i.e. when in GICv2 + // compatibility mode). + // + mov x0, #(1 << 4) | (1 << 5) // gicdctlr_ARE_S | gicdctlr_ARE_NS + mov x1, x19 + bl SyncAREinGICD + + // + // The Redistributor comes out of reset assuming the processor is + // asleep - correct that assumption + // + mov w0, w19 + bl WakeupGICR + + // + // Now we're ready to set security and other initialisations + // + // This is a per-CPU configuration for these interrupts + // + // for the first cluster, CPU number is the redistributor index + // + mov w0, w19 + mov w1, #1 // gicigroupr_G1NS + bl SetPrivateIntSecurityBlock + + // + // While we're in the Secure World, set the priority mask low enough + // for it to be writable in the Non-Secure World + // + //mov x0, #16 << 3 // 5 bits of priority in the Secure world + mov x0, #0xFF // for Non-Secure interrupts + msr ICC_PMR_EL1, x0 + + // + // there's more GIC setup to do, but only for the primary CPU + // + cbnz x19, drop_to_el1 + + // + // There's more to do to the GIC - call the utility routine to set + // all SPIs to Group1 + // + mov w0, #1 // gicigroupr_G1NS + bl SetSPISecurityAll + + // + // Set up EL1 entry point and "dummy" exception return information, + // then perform exception return to enter EL1 + // + .global drop_to_el1 +drop_to_el1: + adr x1, el1_entry_aarch64 + msr ELR_EL3, x1 + mov x1, #(AARCH64_SPSR_EL1h | \ + AARCH64_SPSR_F | \ + AARCH64_SPSR_I | \ + AARCH64_SPSR_A) + msr SPSR_EL3, x1 + eret + + + +// ------------------------------------------------------------ +// EL1 - Common start-up code +// ------------------------------------------------------------ + + .global el1_entry_aarch64 + .type el1_entry_aarch64, "function" +el1_entry_aarch64: + + // + // Now we're in EL1, setup the application stack + // the scatter file allocates 2^14 bytes per app stack + // + ldr x0, =handler_stack_limit + sub x0, x0, x19, lsl #14 + mov sp, x0 + MSR SPSel, #0 + ISB + ldr x0, =__stack + sub x0, x0, x19, lsl #14 + mov sp, x0 + + // + // Enable floating point + // + mov x0, #CPACR_EL1_FPEN + msr CPACR_EL1, x0 + + // + // Invalidate caches and TLBs for all stage 1 + // translations used at EL1 + // + // Cortex-A processors automatically invalidate their caches on reset + // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins). + // It is therefore not necessary for software to invalidate the caches + // on startup, however, this is done here in case of a warm reset. + bl InvalidateUDCaches + tlbi VMALLE1 + + + // + // Set TTBR0 Base address + // + // The CPUs share one set of translation tables that are + // generated by CPU0 at run-time + // + // TTBR1_EL1 is not used in this example + // + ldr x1, =__ttb0_l1 + msr TTBR0_EL1, x1 + + + // + // Set up memory attributes + // + // These equate to: + // + // 0 -> 0b01000100 = 0x00000044 = Normal, Inner/Outer Non-Cacheable + // 1 -> 0b11111111 = 0x0000ff00 = Normal, Inner/Outer WriteBack Read/Write Allocate + // 2 -> 0b00000100 = 0x00040000 = Device-nGnRE + // + mov x1, #0xff44 + movk x1, #4, LSL #16 // equiv to: movk x1, #0x0000000000040000 + msr MAIR_EL1, x1 + + + // + // Set up TCR_EL1 + // + // We're using only TTBR0 (EPD1 = 1), and the page table entries: + // - are using an 8-bit ASID from TTBR0 + // - have a 4K granularity (TG0 = 0b00) + // - are outer-shareable (SH0 = 0b10) + // - are using Inner & Outer WBWA Normal memory ([IO]RGN0 = 0b01) + // - map + // + 32 bits of VA space (T0SZ = 0x20) + // + into a 32-bit PA space (IPS = 0b000) + // + // 36 32 28 24 20 16 12 8 4 0 + // -----+----+----+----+----+----+----+----+----+----+ + // | | |OOII| | | |OOII| | | + // TT | | |RRRR|E T | T| |RRRR|E T | T| + // BB | I I|TTSS|GGGG|P 1 | 1|TTSS|GGGG|P 0 | 0| + // IIA| P P|GGHH|NNNN|DAS | S|GGHH|NNNN|D S | S| + // 10S| S-S|1111|1111|11Z-|---Z|0000|0000|0 Z-|---Z| + // + // 000 0000 0000 0000 1000 0000 0010 0101 0010 0000 + // + // 0x 8 0 2 5 2 0 + // + // Note: the ISB is needed to ensure the changes to system + // context are before the write of SCTLR_EL1.M to enable + // the MMU. It is likely on a "real" implementation that + // this setup would work without an ISB, due to the + // amount of code that gets executed before enabling the + // MMU, but that would not be architecturally correct. + // + ldr x1, =0x0000000000802520 + msr TCR_EL1, x1 + isb + + // + // the primary CPU is going to use SGI 15 as a wakeup event + // to let us know when it is OK to proceed, so prepare for + // receiving that interrupt + // + // NS interrupt priorities run from 0 to 15, with 15 being + // too low a priority to ever raise an interrupt, so let's + // use 14 + // + mov w0, w19 + mov w1, #0 + mov w2, #14 << 4 // we're in NS world, so 4 bits of priority, + // 8-bit field, - 4 = 4-bit shift + bl SetPrivateIntPriority + + mov w0, w19 + mov w1, #0 + bl EnablePrivateInt + + // + // set priority mask as low as possible; although,being in the + // NS World, we can't set bit[7] of the priority, we still + // write all 8-bits of priority to an ICC register + // + mov x0, #31 << 3 + msr ICC_PMR_EL1, x0 + + // + // set global enable and wait for our interrupt to arrive + // + mov x0, #1 + msr ICC_IGRPEN1_EL1, x0 + isb + + // + // x19 already contains the CPU number, so branch to secondary + // code if we're not on CPU0 + // + cbnz x19, el1_secondary + + // + // Fall through to primary code + // + + +// +// ------------------------------------------------------------ +// +// EL1 - primary CPU init code +// +// This code is run on CPU0, while the other CPUs are in the +// holding pen +// + + .global el1_primary + .type el1_primary, "function" +el1_primary: + + // + // Turn on the banked GIC distributor enable, + // ready for individual CPU enables later + // + mov w0, #(1 << 1) // gicdctlr_EnableGrp1A + bl EnableGICD + + // + // Generate TTBR0 L1 + // + // at 4KB granularity, 32-bit VA space, table lookup starts at + // L1, with 1GB regions + // + // we are going to create entries pointing to L2 tables for a + // couple of these 1GB regions, the first of which is the + // RAM on the VE board model - get the table addresses and + // start by emptying out the L1 page tables (4 entries at L1 + // for a 4K granularity) + // + // x21 = address of L1 tables + // + ldr x21, =__ttb0_l1 + mov x0, x21 + mov x1, #(4 << 3) + bl ZeroBlock + + // + // time to start mapping the RAM regions - clear out the + // L2 tables and point to them from the L1 tables + // + // x22 = address of L2 tables, needs to be remembered in case + // we want to re-use the tables for mapping peripherals + // + ldr x22, =__ttb0_l2_ram + mov x1, #(512 << 3) + mov x0, x22 + bl ZeroBlock + + // + // Get the start address of RAM (the EXEC region) into x4 + // and calculate the offset into the L1 table (1GB per region, + // max 4GB) + // + // x23 = L1 table offset, saved for later comparison against + // peripheral offset + // + ldr x4, =__code_start + ubfx x23, x4, #30, #2 + + orr x1, x22, #TT_S1_ATTR_PAGE + str x1, [x21, x23, lsl #3] + + // + // we've already used the RAM start address in x4 - we now need + // to get this in terms of an offset into the L2 page tables, + // where each entry covers 2MB + // + ubfx x2, x4, #21, #9 + + // + // TOP_OF_RAM in the scatter file marks the end of the + // Execute region in RAM: convert the end of this region to an + // offset too, being careful to round up, then calculate the + // number of entries to write + // + ldr x5, =__top_of_ram + sub x3, x5, #1 + ubfx x3, x3, #21, #9 + add x3, x3, #1 + sub x3, x3, x2 + + // + // set x1 to the required page table attributes, then orr + // in the start address (modulo 2MB) + // + // L2 tables in our configuration cover 2MB per entry - map + // memory as Shared, Normal WBWA (MAIR[1]) with a flat + // VA->PA translation + // + bic x4, x4, #((1 << 21) - 1) + mov x1, #(TT_S1_ATTR_BLOCK | \ + (1 << TT_S1_ATTR_MATTR_LSB) | \ + TT_S1_ATTR_NS | \ + TT_S1_ATTR_AP_RW_PL1 | \ + TT_S1_ATTR_SH_INNER | \ + TT_S1_ATTR_AF | \ + TT_S1_ATTR_nG) + orr x1, x1, x4 + + // + // factor the offset into the page table address and then write + // the entries + // + add x0, x22, x2, lsl #3 + +loop1: + subs x3, x3, #1 + str x1, [x0], #8 + add x1, x1, #0x200, LSL #12 // equiv to add x1, x1, #(1 << 21) // 2MB per entry + bne loop1 + + + // + // now mapping the Peripheral regions - clear out the + // L2 tables and point to them from the L1 tables + // + // The assumption here is that all peripherals live within + // a common 1GB region (i.e. that there's a single set of + // L2 pages for all the peripherals). We only use a UART + // and the GIC in this example, so the assumption is sound + // + // x24 = address of L2 peripheral tables + // + ldr x24, =__ttb0_l2_periph + + // + // get the GICD address into x4 and calculate + // the offset into the L1 table + // + // x25 = L1 table offset + // + ldr x4, =gicd + ubfx x25, x4, #30, #2 + + // + // here's the tricky bit: it's possible that the peripherals are + // in the same 1GB region as the RAM, in which case we don't need + // to prime a separate set of L2 page tables, nor add them to the + // L1 tables + // + // if we're going to re-use the TTB0_L2_RAM tables, get their + // address into x24, which is used later on to write the PTEs + // + cmp x25, x23 + csel x24, x22, x24, EQ + b.eq nol2setup + + // + // Peripherals are in a separate 1GB region, and so have their own + // set of L2 tables - clean out the tables and add them to the L1 + // table + // + mov x0, x24 + mov x1, #512 << 3 + bl ZeroBlock + + orr x1, x24, #TT_S1_ATTR_PAGE + str x1, [x21, x25, lsl #3] + + // + // there's only going to be a single 2MB region for GICD (in + // x4) - get this in terms of an offset into the L2 page tables + // + // with larger systems, it is possible that the GIC redistributor + // registers require extra 2MB pages, in which case extra code + // would be required here + // +nol2setup: + ubfx x2, x4, #21, #9 + + // + // set x1 to the required page table attributes, then orr + // in the start address (modulo 2MB) + // + // L2 tables in our configuration cover 2MB per entry - map + // memory as NS Device-nGnRE (MAIR[2]) with a flat VA->PA + // translation + // + bic x4, x4, #((1 << 21) - 1) // start address mod 2MB + mov x1, #(TT_S1_ATTR_BLOCK | \ + (2 << TT_S1_ATTR_MATTR_LSB) | \ + TT_S1_ATTR_NS | \ + TT_S1_ATTR_AP_RW_PL1 | \ + TT_S1_ATTR_AF | \ + TT_S1_ATTR_nG) + orr x1, x1, x4 + + // + // only a single L2 entry for this, so no loop as we have for RAM, above + // + str x1, [x24, x2, lsl #3] + + // + // we have CS3_PERIPHERALS that include the UART controller + // + // Again, the code is making assumptions - this time that the CS3_PERIPHERALS + // region uses the same 1GB portion of the address space as the GICD, + // and thus shares the same set of L2 page tables + // + // Get CS3_PERIPHERALS address into x4 and calculate the offset into the + // L2 tables + // + ldr x4, =__cs3_peripherals + ubfx x2, x4, #21, #9 + + // + // set x1 to the required page table attributes, then orr + // in the start address (modulo 2MB) + // + // L2 tables in our configuration cover 2MB per entry - map + // memory as NS Device-nGnRE (MAIR[2]) with a flat VA->PA + // translation + // + bic x4, x4, #((1 << 21) - 1) // start address mod 2MB + mov x1, #(TT_S1_ATTR_BLOCK | \ + (2 << TT_S1_ATTR_MATTR_LSB) | \ + TT_S1_ATTR_NS | \ + TT_S1_ATTR_AP_RW_PL1 | \ + TT_S1_ATTR_AF | \ + TT_S1_ATTR_nG) + orr x1, x1, x4 + + // + // only a single L2 entry again - write it + // + str x1, [x24, x2, lsl #3] + + // + // issue a barrier to ensure all table entry writes are complete + // + dsb ish + + ldr x1, =is_mmu_ready + mov x2, #1 + str x2, [x1] + + // + // Enable the MMU. Caches will be enabled later, after scatterloading. + // + mrs x1, SCTLR_EL1 + orr x1, x1, #SCTLR_ELx_M + bic x1, x1, #SCTLR_ELx_A // Disable alignment fault checking. To enable, change bic to orr + msr SCTLR_EL1, x1 + isb + + // + // The Arm Architecture Reference Manual for Armv8-A states: + // + // Instruction accesses to Non-cacheable Normal memory can be held in instruction caches. + // Correspondingly, the sequence for ensuring that modifications to instructions are available + // for execution must include invalidation of the modified locations from the instruction cache, + // even if the instructions are held in Normal Non-cacheable memory. + // This includes cases where the instruction cache is disabled. + // + + dsb ish // ensure all previous stores have completed before invalidating + ic ialluis // I cache invalidate all inner shareable to PoU (which includes secondary cores) + dsb ish // ensure completion on inner shareable domain (which includes secondary cores) + isb + + // Scatter-loading is complete, so enable the caches here, so that the C-library's mutex initialization later will work + mrs x1, SCTLR_EL1 + orr x1, x1, #SCTLR_ELx_C + orr x1, x1, #SCTLR_ELx_I + msr SCTLR_EL1, x1 + isb + + // Zero the bss + ldr x0, =__bss_start__ // Start of block + mov x1, #0 // Fill value + ldr x2, =__bss_end__ // End of block + sub x2, x2, x0 // Length of block + bl memset + + // Set up the standard file handles + bl initialise_monitor_handles + + // Set up _fini and fini_array to be called at exit + ldr x0, =__libc_fini_array + bl atexit + + // Call preinit_array, _init and init_array + bl __libc_init_array + + // Set argc = 1, argv[0] = "" and then call main + .pushsection .data + .align 3 +argv: + .dword arg0 + .dword 0 +arg0: + .byte 0 + .popsection + + mov x0, #1 + ldr x1, =argv + bl main + + b exit // Will not return + +// ------------------------------------------------------------ +// EL1 - secondary CPU init code +// +// This code is run on CPUs 1, 2, 3 etc.... +// ------------------------------------------------------------ + + .global el1_secondary + .type el1_secondary, "function" +el1_secondary: + +wait_for_mmu_ready: + ldr x1, =is_mmu_ready + ldr x1, [x1] + cmp x1, #1 + b.ne wait_for_mmu_ready + + // + // Enable the MMU and caches + // + mrs x1, SCTLR_EL1 + orr x1, x1, #SCTLR_ELx_M + orr x1, x1, #SCTLR_ELx_C + orr x1, x1, #SCTLR_ELx_I + bic x1, x1, #SCTLR_ELx_A // Disable alignment fault checking. To enable, change bic to orr + msr SCTLR_EL1, x1 + isb + + /* EL: Secondary core entrance. */ + B _tx_thread_smp_initialize_wait + +loop_wfi: + dsb SY // Clear all pending data accesses + wfi // Go to sleep + + // + // something woke us from our wait, was it the required interrupt? + // + mov w0, w19 + mov w1, #15 + bl GetPrivateIntPending + cbz w0, loop_wfi + + // + // it was - there's no need to actually take the interrupt, + // so just clear it + // + mov w0, w19 + mov w1, #15 + bl ClearPrivateIntPending + + // + // Branch to thread start + // + //B MainApp + diff --git a/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/timer_interrupts.c b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/timer_interrupts.c new file mode 100644 index 00000000..7b0996ef --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/timer_interrupts.c @@ -0,0 +1,152 @@ +/* Bare-metal example for Armv8-A FVP Base model */ + +/* Timer and interrupts */ + +/* Copyright (c) 2016 Arm Limited (or its affiliates). All rights reserved. */ +/* Use, modification and redistribution of this file is subject to your */ +/* possession of a valid DS-5 end user licence agreement and your compliance */ +/* with all applicable terms and conditions of such licence agreement. */ + +#include + +#include "GICv3.h" +#include "GICv3_gicc.h" +#include "sp804_timer.h" + +void _tx_timer_interrupt(void); + +// LED Base address +#define LED_BASE (volatile unsigned int *)0x1C010008 + + +void nudge_leds(void) // Move LEDs along +{ + static int state = 1; + static int value = 1; + + if (state) + { + int max = (1 << 7); + value <<= 1; + if (value == max) + state = 0; + } + else + { + value >>= 1; + if (value == 1) + state = 1; + } + + *LED_BASE = value; // Update LEDs hardware +} + + +// Initialize Timer 0 and Interrupt Controller +void init_timer(void) +{ + // Enable interrupts + __asm("MSR DAIFClr, #0xF"); + setICC_IGRPEN1_EL1(igrpEnable); + + // Configure the SP804 timer to generate an interrupt + setTimerBaseAddress(0x1C110000); + initTimer(0x200, SP804_AUTORELOAD, SP804_GENERATE_IRQ); + startTimer(); + + // The SP804 timer generates SPI INTID 34. Enable + // this ID, and route it to core 0.0.0.0 (this one!) + SetSPIRoute(34, 0, gicdirouter_ModeSpecific); // Route INTID 34 to 0.0.0.0 (this core) + SetSPIPriority(34, 0); // Set INTID 34 to priority to 0 + ConfigureSPI(34, gicdicfgr_Level); // Set INTID 34 as level-sensitive + EnableSPI(34); // Enable INTID 34 +} + + +// -------------------------------------------------------- + +void irqHandler(void) +{ + unsigned int ID; + + ID = getICC_IAR1(); // readIntAck(); + + // Check for reserved IDs + if ((1020 <= ID) && (ID <= 1023)) + { + //printf("irqHandler() - Reserved INTID %d\n\n", ID); + return; + } + + switch(ID) + { + case 34: + // Dual-Timer 0 (SP804) + //printf("irqHandler() - External timer interrupt\n\n"); + nudge_leds(); + clearTimerIrq(); + + /* Call ThreadX timer interrupt processing. */ + _tx_timer_interrupt(); + + break; + + default: + // Unexpected ID value + //printf("irqHandler() - Unexpected INTID %d\n\n", ID); + break; + } + + // Write the End of Interrupt register to tell the GIC + // we've finished handling the interrupt + setICC_EOIR1(ID); // writeAliasedEOI(ID); +} + +// -------------------------------------------------------- + +// Not actually used in this example, but provided for completeness + +void fiqHandler(void) +{ + unsigned int ID; + unsigned int aliased = 0; + + ID = getICC_IAR0(); // readIntAck(); + printf("fiqHandler() - Read %d from IAR0\n", ID); + + // Check for reserved IDs + if ((1020 <= ID) && (ID <= 1023)) + { + printf("fiqHandler() - Reserved INTID %d\n\n", ID); + ID = getICC_IAR1(); // readAliasedIntAck(); + printf("fiqHandler() - Read %d from AIAR\n", ID); + aliased = 1; + + // If still spurious then simply return + if ((1020 <= ID) && (ID <= 1023)) + return; + } + + switch(ID) + { + case 34: + // Dual-Timer 0 (SP804) + printf("fiqHandler() - External timer interrupt\n\n"); + clearTimerIrq(); + break; + + default: + // Unexpected ID value + printf("fiqHandler() - Unexpected INTID %d\n\n", ID); + break; + } + + // Write the End of Interrupt register to tell the GIC + // we've finished handling the interrupt + // NOTE: If the ID was read from the Aliased IAR, then + // the aliased EOI register must be used + if (aliased == 0) + setICC_EOIR0(ID); // writeEOI(ID); + else + setICC_EOIR1(ID); // writeAliasedEOI(ID); +} diff --git a/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/use_model_semihosting.ds b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/use_model_semihosting.ds new file mode 100644 index 00000000..6fde52b2 --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/use_model_semihosting.ds @@ -0,0 +1 @@ +set semihosting enabled off diff --git a/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/v8_aarch64.S b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/v8_aarch64.S new file mode 100644 index 00000000..d86fecb6 --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/v8_aarch64.S @@ -0,0 +1,163 @@ +// ------------------------------------------------------------ +// Armv8-A AArch64 - Common helper functions +// +// Copyright (c) 2012-2018 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#include "v8_system.h" + + .text + .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + + .global EnableCachesEL1 + .global DisableCachesEL1 + .global InvalidateUDCaches + .global GetMIDR + .global GetMPIDR + .global GetCPUID + +// ------------------------------------------------------------ + +// +// void EnableCachesEL1(void) +// +// enable Instruction and Data caches +// + .type EnableCachesEL1, "function" + .cfi_startproc +EnableCachesEL1: + + mrs x0, SCTLR_EL1 + orr x0, x0, #SCTLR_ELx_I + orr x0, x0, #SCTLR_ELx_C + msr SCTLR_EL1, x0 + + isb + ret + .cfi_endproc + + +// ------------------------------------------------------------ + + .type DisableCachesEL1, "function" + .cfi_startproc +DisableCachesEL1: + + mrs x0, SCTLR_EL1 + bic x0, x0, #SCTLR_ELx_I + bic x0, x0, #SCTLR_ELx_C + msr SCTLR_EL1, x0 + + isb + ret + .cfi_endproc + + +// ------------------------------------------------------------ + +// +// void InvalidateUDCaches(void) +// +// Invalidate data and unified caches +// + .type InvalidateUDCaches, "function" + .cfi_startproc +InvalidateUDCaches: + // From the Armv8-A Architecture Reference Manual + + dmb ish // ensure all prior inner-shareable accesses have been observed + + mrs x0, CLIDR_EL1 + and w3, w0, #0x07000000 // get 2 x level of coherence + lsr w3, w3, #23 + cbz w3, finished + mov w10, #0 // w10 = 2 x cache level + mov w8, #1 // w8 = constant 0b1 +loop_level: + add w2, w10, w10, lsr #1 // calculate 3 x cache level + lsr w1, w0, w2 // extract 3-bit cache type for this level + and w1, w1, #0x7 + cmp w1, #2 + b.lt next_level // no data or unified cache at this level + msr CSSELR_EL1, x10 // select this cache level + isb // synchronize change of csselr + mrs x1, CCSIDR_EL1 // read ccsidr + and w2, w1, #7 // w2 = log2(linelen)-4 + add w2, w2, #4 // w2 = log2(linelen) + ubfx w4, w1, #3, #10 // w4 = max way number, right aligned + clz w5, w4 // w5 = 32-log2(ways), bit position of way in dc operand + lsl w9, w4, w5 // w9 = max way number, aligned to position in dc operand + lsl w16, w8, w5 // w16 = amount to decrement way number per iteration +loop_way: + ubfx w7, w1, #13, #15 // w7 = max set number, right aligned + lsl w7, w7, w2 // w7 = max set number, aligned to position in dc operand + lsl w17, w8, w2 // w17 = amount to decrement set number per iteration +loop_set: + orr w11, w10, w9 // w11 = combine way number and cache number ... + orr w11, w11, w7 // ... and set number for dc operand + dc isw, x11 // do data cache invalidate by set and way + subs w7, w7, w17 // decrement set number + b.ge loop_set + subs x9, x9, x16 // decrement way number + b.ge loop_way +next_level: + add w10, w10, #2 // increment 2 x cache level + cmp w3, w10 + b.gt loop_level + dsb sy // ensure completion of previous cache maintenance operation + isb +finished: + ret + .cfi_endproc + + +// ------------------------------------------------------------ + +// +// ID Register functions +// + + .type GetMIDR, "function" + .cfi_startproc +GetMIDR: + + mrs x0, MIDR_EL1 + ret + .cfi_endproc + + + .type GetMPIDR, "function" + .cfi_startproc +GetMPIDR: + + mrs x0, MPIDR_EL1 + ret + .cfi_endproc + + + .type GetCPUID, "function" + .cfi_startproc +GetCPUID: + + mrs x0, MIDR_EL1 + ubfx x0, x0, #4, #12 // extract PartNum + cmp x0, #0xD0B // Cortex-A76 + b.eq DynamIQ + cmp x0, #0xD0A // Cortex-A75 + b.eq DynamIQ + cmp x0, #0xD05 // Cortex-A55 + b.eq DynamIQ + b Others +DynamIQ: + mrs x0, MPIDR_EL1 + ubfx x0, x0, #MPIDR_EL1_AFF1_LSB, #MPIDR_EL1_AFF_WIDTH + ret + +Others: + mrs x0, MPIDR_EL1 + ubfx x0, x0, #MPIDR_EL1_AFF0_LSB, #MPIDR_EL1_AFF_WIDTH + ret + .cfi_endproc diff --git a/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/v8_mmu.h b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/v8_mmu.h new file mode 100644 index 00000000..0185feba --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/v8_mmu.h @@ -0,0 +1,118 @@ +// +// Defines for v8 Memory Model +// +// Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// + +#ifndef V8_MMU_H +#define V8_MMU_H + +// +// Translation Control Register fields +// +// RGN field encodings +// +#define TCR_RGN_NC 0b00 +#define TCR_RGN_WBWA 0b01 +#define TCR_RGN_WT 0b10 +#define TCR_RGN_WBRA 0b11 + +// +// Shareability encodings +// +#define TCR_SHARE_NONE 0b00 +#define TCR_SHARE_OUTER 0b10 +#define TCR_SHARE_INNER 0b11 + +// +// Granule size encodings +// +#define TCR_GRANULE_4K 0b00 +#define TCR_GRANULE_64K 0b01 +#define TCR_GRANULE_16K 0b10 + +// +// Physical Address sizes +// +#define TCR_SIZE_4G 0b000 +#define TCR_SIZE_64G 0b001 +#define TCR_SIZE_1T 0b010 +#define TCR_SIZE_4T 0b011 +#define TCR_SIZE_16T 0b100 +#define TCR_SIZE_256T 0b101 + +// +// Translation Control Register fields +// +#define TCR_EL1_T0SZ_SHIFT 0 +#define TCR_EL1_EPD0 (1 << 7) +#define TCR_EL1_IRGN0_SHIFT 8 +#define TCR_EL1_ORGN0_SHIFT 10 +#define TCR_EL1_SH0_SHIFT 12 +#define TCR_EL1_TG0_SHIFT 14 + +#define TCR_EL1_T1SZ_SHIFT 16 +#define TCR_EL1_A1 (1 << 22) +#define TCR_EL1_EPD1 (1 << 23) +#define TCR_EL1_IRGN1_SHIFT 24 +#define TCR_EL1_ORGN1_SHIFT 26 +#define TCR_EL1_SH1_SHIFT 28 +#define TCR_EL1_TG1_SHIFT 30 +#define TCR_EL1_IPS_SHIFT 32 +#define TCR_EL1_AS (1 << 36) +#define TCR_EL1_TBI0 (1 << 37) +#define TCR_EL1_TBI1 (1 << 38) + +// +// Stage 1 Translation Table descriptor fields +// +#define TT_S1_ATTR_FAULT (0b00 << 0) +#define TT_S1_ATTR_BLOCK (0b01 << 0) // Level 1/2 +#define TT_S1_ATTR_TABLE (0b11 << 0) // Level 0/1/2 +#define TT_S1_ATTR_PAGE (0b11 << 0) // Level 3 + +#define TT_S1_ATTR_MATTR_LSB 2 + +#define TT_S1_ATTR_NS (1 << 5) + +#define TT_S1_ATTR_AP_RW_PL1 (0b00 << 6) +#define TT_S1_ATTR_AP_RW_ANY (0b01 << 6) +#define TT_S1_ATTR_AP_RO_PL1 (0b10 << 6) +#define TT_S1_ATTR_AP_RO_ANY (0b11 << 6) + +#define TT_S1_ATTR_SH_NONE (0b00 << 8) +#define TT_S1_ATTR_SH_OUTER (0b10 << 8) +#define TT_S1_ATTR_SH_INNER (0b11 << 8) + +#define TT_S1_ATTR_AF (1 << 10) +#define TT_S1_ATTR_nG (1 << 11) + +#define TT_S1_ATTR_CONTIG (1 << 52) +#define TT_S1_ATTR_PXN (1 << 53) +#define TT_S1_ATTR_UXN (1 << 54) + +#define TT_S1_MAIR_DEV_nGnRnE 0b00000000 +#define TT_S1_MAIR_DEV_nGnRE 0b00000100 +#define TT_S1_MAIR_DEV_nGRE 0b00001000 +#define TT_S1_MAIR_DEV_GRE 0b00001100 + +// +// Inner and Outer Normal memory attributes use the same bit patterns +// Outer attributes just need to be shifted up +// +#define TT_S1_MAIR_OUTER_SHIFT 4 + +#define TT_S1_MAIR_WT_TRANS_RA 0b0010 + +#define TT_S1_MAIR_WB_TRANS_RA 0b0110 +#define TT_S1_MAIR_WB_TRANS_RWA 0b0111 + +#define TT_S1_MAIR_WT_RA 0b1010 + +#define TT_S1_MAIR_WB_RA 0b1110 +#define TT_S1_MAIR_WB_RWA 0b1111 + +#endif // V8_MMU_H diff --git a/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/v8_system.h b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/v8_system.h new file mode 100644 index 00000000..ff96deff --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/v8_system.h @@ -0,0 +1,115 @@ +// +// Defines for v8 System Registers +// +// Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// + +#ifndef V8_SYSTEM_H +#define V8_SYSTEM_H + +// +// AArch64 SPSR +// +#define AARCH64_SPSR_EL3h 0b1101 +#define AARCH64_SPSR_EL3t 0b1100 +#define AARCH64_SPSR_EL2h 0b1001 +#define AARCH64_SPSR_EL2t 0b1000 +#define AARCH64_SPSR_EL1h 0b0101 +#define AARCH64_SPSR_EL1t 0b0100 +#define AARCH64_SPSR_EL0t 0b0000 +#define AARCH64_SPSR_RW (1 << 4) +#define AARCH64_SPSR_F (1 << 6) +#define AARCH64_SPSR_I (1 << 7) +#define AARCH64_SPSR_A (1 << 8) +#define AARCH64_SPSR_D (1 << 9) +#define AARCH64_SPSR_IL (1 << 20) +#define AARCH64_SPSR_SS (1 << 21) +#define AARCH64_SPSR_V (1 << 28) +#define AARCH64_SPSR_C (1 << 29) +#define AARCH64_SPSR_Z (1 << 30) +#define AARCH64_SPSR_N (1 << 31) + +// +// Multiprocessor Affinity Register +// +#define MPIDR_EL1_AFF3_LSB 32 +#define MPIDR_EL1_U (1 << 30) +#define MPIDR_EL1_MT (1 << 24) +#define MPIDR_EL1_AFF2_LSB 16 +#define MPIDR_EL1_AFF1_LSB 8 +#define MPIDR_EL1_AFF0_LSB 0 +#define MPIDR_EL1_AFF_WIDTH 8 + +// +// Data Cache Zero ID Register +// +#define DCZID_EL0_BS_LSB 0 +#define DCZID_EL0_BS_WIDTH 4 +#define DCZID_EL0_DZP_LSB 5 +#define DCZID_EL0_DZP (1 << 5) + +// +// System Control Register +// +#define SCTLR_EL1_UCI (1 << 26) +#define SCTLR_ELx_EE (1 << 25) +#define SCTLR_EL1_E0E (1 << 24) +#define SCTLR_ELx_WXN (1 << 19) +#define SCTLR_EL1_nTWE (1 << 18) +#define SCTLR_EL1_nTWI (1 << 16) +#define SCTLR_EL1_UCT (1 << 15) +#define SCTLR_EL1_DZE (1 << 14) +#define SCTLR_ELx_I (1 << 12) +#define SCTLR_EL1_UMA (1 << 9) +#define SCTLR_EL1_SED (1 << 8) +#define SCTLR_EL1_ITD (1 << 7) +#define SCTLR_EL1_THEE (1 << 6) +#define SCTLR_EL1_CP15BEN (1 << 5) +#define SCTLR_EL1_SA0 (1 << 4) +#define SCTLR_ELx_SA (1 << 3) +#define SCTLR_ELx_C (1 << 2) +#define SCTLR_ELx_A (1 << 1) +#define SCTLR_ELx_M (1 << 0) + +// +// Architectural Feature Access Control Register +// +#define CPACR_EL1_TTA (1 << 28) +#define CPACR_EL1_FPEN (3 << 20) + +// +// Architectural Feature Trap Register +// +#define CPTR_ELx_TCPAC (1 << 31) +#define CPTR_ELx_TTA (1 << 20) +#define CPTR_ELx_TFP (1 << 10) + +// +// Secure Configuration Register +// +#define SCR_EL3_TWE (1 << 13) +#define SCR_EL3_TWI (1 << 12) +#define SCR_EL3_ST (1 << 11) +#define SCR_EL3_RW (1 << 10) +#define SCR_EL3_SIF (1 << 9) +#define SCR_EL3_HCE (1 << 8) +#define SCR_EL3_SMD (1 << 7) +#define SCR_EL3_EA (1 << 3) +#define SCR_EL3_FIQ (1 << 2) +#define SCR_EL3_IRQ (1 << 1) +#define SCR_EL3_NS (1 << 0) + +// +// Hypervisor Configuration Register +// +#define HCR_EL2_ID (1 << 33) +#define HCR_EL2_CD (1 << 32) +#define HCR_EL2_RW (1 << 31) +#define HCR_EL2_TRVM (1 << 30) +#define HCR_EL2_HVC (1 << 29) +#define HCR_EL2_TDZ (1 << 28) + +#endif // V8_SYSTEM_H diff --git a/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/v8_utils.S b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/v8_utils.S new file mode 100644 index 00000000..f0fcef26 --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/v8_utils.S @@ -0,0 +1,69 @@ +// +// Simple utility routines for baremetal v8 code +// +// Copyright (c) 2013-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// + +#include "v8_system.h" + + .text + .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + +// +// void *ZeroBlock(void *blockPtr, unsigned int nBytes) +// +// Zero fill a block of memory +// Fill memory pages or similar structures with zeros. +// The byte count must be a multiple of the block fill size (16 bytes) +// +// Inputs: +// blockPtr - base address of block to fill +// nBytes - block size, in bytes +// +// Returns: +// pointer to just filled block, NULL if nBytes is +// incompatible with block fill size +// + .global ZeroBlock + .type ZeroBlock, "function" + .cfi_startproc +ZeroBlock: + + // + // we fill data by steam, 16 bytes at a time: check that + // blocksize is a multiple of that + // + ubfx x2, x1, #0, #4 + cbnz x2, incompatible + + // + // we already have one register full of zeros, get another + // + mov x3, x2 + + // + // OK, set temporary pointer and away we go + // + add x0, x0, x1 + +loop0: + subs x1, x1, #16 + stp x2, x3, [x0, #-16]! + b.ne loop0 + + // + // that's all - x0 will be back to its start value + // + ret + + // + // parameters are incompatible with block size - return + // an indication that this is so + // +incompatible: + mov x0,#0 + ret + .cfi_endproc diff --git a/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/vectors.S b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/vectors.S new file mode 100644 index 00000000..9e60e001 --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/vectors.S @@ -0,0 +1,252 @@ +// ------------------------------------------------------------ +// Armv8-A Vector tables +// +// Copyright (c) 2014-2016 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + + + .global el1_vectors + .global el2_vectors + .global el3_vectors + .global c0sync1 + .global irqHandler + .global fiqHandler + .global irqFirstLevelHandler + .global fiqFirstLevelHandler + + .section EL1VECTORS, "ax" + .align 11 + +// +// Current EL with SP0 +// +el1_vectors: +c0sync1: B c0sync1 + + .balign 0x80 +c0irq1: B irqFirstLevelHandler + + .balign 0x80 +c0fiq1: B fiqFirstLevelHandler + + .balign 0x80 +c0serr1: B c0serr1 + +// +// Current EL with SPx +// + .balign 0x80 +cxsync1: B cxsync1 + + .balign 0x80 +cxirq1: B irqFirstLevelHandler + + .balign 0x80 +cxfiq1: B fiqFirstLevelHandler + + .balign 0x80 +cxserr1: B cxserr1 + +// +// Lower EL using AArch64 +// + .balign 0x80 +l64sync1: B l64sync1 + + .balign 0x80 +l64irq1: B irqFirstLevelHandler + + .balign 0x80 +l64fiq1: B fiqFirstLevelHandler + + .balign 0x80 +l64serr1: B l64serr1 + +// +// Lower EL using AArch32 +// + .balign 0x80 +l32sync1: B l32sync1 + + .balign 0x80 +l32irq1: B irqFirstLevelHandler + + .balign 0x80 +l32fiq1: B fiqFirstLevelHandler + + .balign 0x80 +l32serr1: B l32serr1 + +//---------------------------------------------------------------- + + .section EL2VECTORS, "ax" + .align 11 + +// +// Current EL with SP0 +// +el2_vectors: +c0sync2: B c0sync2 + + .balign 0x80 +c0irq2: B irqFirstLevelHandler + + .balign 0x80 +c0fiq2: B fiqFirstLevelHandler + + .balign 0x80 +c0serr2: B c0serr2 + +// +// Current EL with SPx +// + .balign 0x80 +cxsync2: B cxsync2 + + .balign 0x80 +cxirq2: B irqFirstLevelHandler + + .balign 0x80 +cxfiq2: B fiqFirstLevelHandler + + .balign 0x80 +cxserr2: B cxserr2 + +// +// Lower EL using AArch64 +// + .balign 0x80 +l64sync2: B l64sync2 + + .balign 0x80 +l64irq2: B irqFirstLevelHandler + + .balign 0x80 +l64fiq2: B fiqFirstLevelHandler + + .balign 0x80 +l64serr2: B l64serr2 + +// +// Lower EL using AArch32 +// + .balign 0x80 +l32sync2: B l32sync2 + + .balign 0x80 +l32irq2: B irqFirstLevelHandler + + .balign 0x80 +l32fiq2: B fiqFirstLevelHandler + + .balign 0x80 +l32serr2: B l32serr2 + +//---------------------------------------------------------------- + + .section EL3VECTORS, "ax" + .align 11 + +// +// Current EL with SP0 +// +el3_vectors: +c0sync3: B c0sync3 + + .balign 0x80 +c0irq3: B irqFirstLevelHandler + + .balign 0x80 +c0fiq3: B fiqFirstLevelHandler + + .balign 0x80 +c0serr3: B c0serr3 + +// +// Current EL with SPx +// + .balign 0x80 +cxsync3: B cxsync3 + + .balign 0x80 +cxirq3: B irqFirstLevelHandler + + .balign 0x80 +cxfiq3: B fiqFirstLevelHandler + + .balign 0x80 +cxserr3: B cxserr3 + +// +// Lower EL using AArch64 +// + .balign 0x80 +l64sync3: B l64sync3 + + .balign 0x80 +l64irq3: B irqFirstLevelHandler + + .balign 0x80 +l64fiq3: B fiqFirstLevelHandler + + .balign 0x80 +l64serr3: B l64serr3 + +// +// Lower EL using AArch32 +// + .balign 0x80 +l32sync3: B l32sync3 + + .balign 0x80 +l32irq3: B irqFirstLevelHandler + + .balign 0x80 +l32fiq3: B fiqFirstLevelHandler + + .balign 0x80 +l32serr3: B l32serr3 + + + .section InterruptHandlers, "ax" + .balign 4 + + .type irqFirstLevelHandler, "function" +irqFirstLevelHandler: + MSR SPSel, 0 + STP x29, x30, [sp, #-16]! + BL _tx_thread_context_save + BL irqHandler + B _tx_thread_context_restore + + .type fiqFirstLevelHandler, "function" +fiqFirstLevelHandler: + STP x29, x30, [sp, #-16]! + STP x18, x19, [sp, #-16]! + STP x16, x17, [sp, #-16]! + STP x14, x15, [sp, #-16]! + STP x12, x13, [sp, #-16]! + STP x10, x11, [sp, #-16]! + STP x8, x9, [sp, #-16]! + STP x6, x7, [sp, #-16]! + STP x4, x5, [sp, #-16]! + STP x2, x3, [sp, #-16]! + STP x0, x1, [sp, #-16]! + + BL fiqHandler + + LDP x0, x1, [sp], #16 + LDP x2, x3, [sp], #16 + LDP x4, x5, [sp], #16 + LDP x6, x7, [sp], #16 + LDP x8, x9, [sp], #16 + LDP x10, x11, [sp], #16 + LDP x12, x13, [sp], #16 + LDP x14, x15, [sp], #16 + LDP x16, x17, [sp], #16 + LDP x18, x19, [sp], #16 + LDP x29, x30, [sp], #16 + ERET diff --git a/ports_smp/cortex_a35_smp/gnu/example_build/tx/.cproject b/ports_smp/cortex_a35_smp/gnu/example_build/tx/.cproject new file mode 100644 index 00000000..57034c74 --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/example_build/tx/.cproject @@ -0,0 +1,276 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/cortex_a35_smp/gnu/example_build/tx/.project b/ports_smp/cortex_a35_smp/gnu/example_build/tx/.project new file mode 100644 index 00000000..10681969 --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/example_build/tx/.project @@ -0,0 +1,48 @@ + + + tx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + inc_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common_smp/inc + + + inc_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/inc + + + src_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common_smp/src + + + src_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/src + + + diff --git a/ports_smp/cortex_a35_smp/gnu/example_build/tx/.settings/language.settings.xml b/ports_smp/cortex_a35_smp/gnu/example_build/tx/.settings/language.settings.xml new file mode 100644 index 00000000..8a6c3806 --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/example_build/tx/.settings/language.settings.xml @@ -0,0 +1,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/cortex_a35_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a35_smp/gnu/inc/tx_port.h new file mode 100644 index 00000000..e9a401d9 --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/inc/tx_port.h @@ -0,0 +1,430 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A35-SMP/GNU */ +/* 6.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/************* Define ThreadX SMP constants. *************/ + +/* Define the ThreadX SMP maximum number of cores. */ + +#ifndef TX_THREAD_SMP_MAX_CORES +#define TX_THREAD_SMP_MAX_CORES 4 +#endif + + +/* Define the ThreadX SMP core mask. */ + +#ifndef TX_THREAD_SMP_CORE_MASK +#define TX_THREAD_SMP_CORE_MASK 0xF /* Where bit 0 represents Core 0, bit 1 represents Core 1, etc. */ +#endif + + +/* Define INLINE_DECLARE to whitespace for ARM compiler. */ + +#define INLINE_DECLARE + + +/* Define ThreadX SMP initialization macro. */ + +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION + + +/* Define ThreadX SMP pre-scheduler initialization. */ + +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION + + +/* Enable the inter-core interrupt logic. */ + +#define TX_THREAD_SMP_INTER_CORE_INTERRUPT + + +/* Determine if there is customer-specific wakeup logic needed. */ + +#ifdef TX_THREAD_SMP_WAKEUP_LOGIC + +/* Include customer-specific wakeup code. */ + +#include "tx_thread_smp_core_wakeup.h" +#else + +#ifdef TX_THREAD_SMP_DEFAULT_WAKEUP_LOGIC + +/* Default wakeup code. */ +#define TX_THREAD_SMP_WAKEUP_LOGIC +#define TX_THREAD_SMP_WAKEUP(i) _tx_thread_smp_core_preempt(i) +#endif +#endif + + +/* Ensure that the in-line resume/suspend define is not allowed. */ + +#ifdef TX_INLINE_THREAD_RESUME_SUSPEND +#undef TX_INLINE_THREAD_RESUME_SUSPEND +#endif + + +/************* End ThreadX SMP constants. *************/ + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef int LONG; +typedef unsigned int ULONG; +typedef unsigned long long ULONG64; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Override the alignment type to use 64-bit alignment and storage for pointers. */ + +#define ALIGN_TYPE_DEFINED +typedef unsigned long long ALIGN_TYPE; + + +/* Override the free block marker for byte pools to be a 64-bit constant. */ + +#define TX_BYTE_BLOCK_FREE ((ALIGN_TYPE) 0xFFFFEEEEFFFFEEEE) + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 4096 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#define TX_INT_ENABLE 0x00 /* Enable IRQ & FIQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE _tx_thread_smp_time_get() +#endif +#else +#ifndef TX_TRACE_TIME_SOURCE +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_fp_enable; +#define TX_THREAD_EXTENSION_3 VOID *tx_thread_extension_ptr; + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) b = (UINT) __builtin_ctz((unsigned int) m); + +#endif + + +/* Define the internal timer extension to also hold the thread pointer such that _tx_thread_timeout + can figure out what thread timeout to process. */ + +#define TX_TIMER_INTERNAL_EXTENSION VOID *tx_timer_internal_extension_ptr; + + +/* Define the thread timeout setup logic in _tx_thread_create. */ + +#define TX_THREAD_CREATE_TIMEOUT_SETUP(t) (t) -> tx_thread_timer.tx_timer_internal_timeout_function = &(_tx_thread_timeout); \ + (t) -> tx_thread_timer.tx_timer_internal_timeout_param = 0; \ + (t) -> tx_thread_timer.tx_timer_internal_extension_ptr = (VOID *) (t); + + +/* Define the thread timeout pointer setup in _tx_thread_timeout. */ + +#define TX_THREAD_TIMEOUT_POINTER_SETUP(t) (t) = (TX_THREAD *) _tx_timer_expired_timer_ptr -> tx_timer_internal_extension_ptr; + + +/************* Define ThreadX SMP data types and function prototypes. *************/ + +struct TX_THREAD_STRUCT; + + +/* Define the ThreadX SMP protection structure. */ + +typedef struct TX_THREAD_SMP_PROTECT_STRUCT +{ + ULONG tx_thread_smp_protect_in_force; + ULONG tx_thread_smp_protect_core; + ULONG tx_thread_smp_protect_count; + ULONG tx_thread_smp_protect_pad_0; + ULONG tx_thread_smp_protect_pad_1; + ULONG tx_thread_smp_protect_pad_2; + ULONG tx_thread_smp_protect_pad_3; +} TX_THREAD_SMP_PROTECT; + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_smp_protect(); +#define TX_RESTORE _tx_thread_smp_unprotect(interrupt_save); + +/************* End ThreadX SMP data type and function prototype definitions. *************/ + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define VFP extension for the Cortex-A35. Each is assumed to be called in the context of the executing + thread. */ + +#ifndef TX_SOURCE_CODE +#define tx_thread_fp_enable _tx_thread_fp_enable +#define tx_thread_fp_disable _tx_thread_fp_disable +#endif + +VOID tx_thread_fp_enable(VOID); +VOID tx_thread_fp_disable(VOID); + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A35-SMP/GNU Version 6.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + + + diff --git a/ports_smp/cortex_a35_smp/gnu/readme_threadx.txt b/ports_smp/cortex_a35_smp/gnu/readme_threadx.txt new file mode 100644 index 00000000..f1842fc7 --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/readme_threadx.txt @@ -0,0 +1,254 @@ + Microsoft's Azure RTOS ThreadX for Cortex-A35 + + Using the ARM GNU Compiler & DS + +1. Import the ThreadX Projects + +In order to build the ThreadX SMP library and the ThreadX SMP demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +into your DS workspace. + + +2. Building the ThreadX SMP run-time Library + +Building the ThreadX SMP library is easy; simply select the Eclipse project file +"tx" and then select the build button. You should now observe the compilation +and assembly of the ThreadX SMP library. This project build produces the ThreadX SMP +library file tx.a. + + +3. Demonstration System + +The ThreadX SMP demonstration is designed to execute under the DS-5 debugger on the +'Debug Cortex-A35x4 SMP' FVP which must be downloaded from the ARM website and +requires a license. + +Building the demonstration is easy; simply select the sample_threadx project, and +select the build button. Next, in the sample_threadx project, right-click on the +sample_threadx.launch file and select 'Debug As -> sample_threadx'. The debugger is +setup for the Cortex-35x4 SMP FVP, so selecting "Debug" will launch the FVP, load +the sample_threadx.axf ELF file and run to main. You are now ready to execute the +ThreadX SMP demonstration. + + +4. System Initialization + +The entry point in ThreadX SMP for the Cortex-A35 using GCC tools is at label +"start64". This is defined within the GCC compiler's startup code. In addition, +this is where all static and global pre-set C variable initialization processing +takes place. + +The ThreadX SMP tx_initialize_low_level.s file is responsible for determining the +first available RAM address for use by the application, which is supplied as the +sole input parameter to your application definition function, tx_application_define. + + +5. Register Usage and Stack Frames + +The 64-bit GCC compiler assumes that registers x0-x18 are scratch registers +for each function. All other registers used by a C function must be preserved +by the function. ThreadX SMP takes advantage of this in situations where a context +switch happens as a result of making a ThreadX SMP service call (which is itself a +C function). In such cases, the saved context of a thread is only the +non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + +FP not enabled and TX_THREAD.tx_thread_fp_enable == 0: + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x000 SPSR DAIF + 0x008 ELR 0 + 0x010 x28 x27 + 0x018 reserved x28 + 0x020 x26 x25 + 0x028 x27 x26 + 0x030 x24 x23 + 0x038 x25 x24 + 0x040 x22 x21 + 0x048 x23 x22 + 0x050 x20 x19 + 0x058 x21 x20 + 0x060 x18 x29 + 0x068 x19 x30 + 0x070 x16 + 0x078 x17 + 0x080 x14 + 0x088 x15 + 0x090 x12 + 0x098 x13 + 0x0A0 x10 + 0x0A8 x11 + 0x0B0 x8 + 0x0B8 x9 + 0x0C0 x6 + 0x0C8 x7 + 0x0D0 x4 + 0x0D8 x5 + 0x0E0 x2 + 0x0E8 x3 + 0x0F0 x0 + 0x0F8 x1 + 0x100 x29 + 0x108 x30 + + +FP enabled and TX_THREAD.tx_thread_fp_enable == 1: + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x000 SPSR DAIF + 0x008 ELR 0 + 0x010 FPSR FPSR + 0x018 FPCR FPCR + 0x020 q30 q14 + 0x030 q31 q15 + 0x040 q28 q12 + 0x050 q29 q13 + 0x060 q26 q10 + 0x070 q27 q11 + 0x080 q24 q8 + 0x090 q25 q9 + 0x0A0 q22 x27 + 0x0A8 x28 + 0x0B0 q23 x25 + 0x0B8 x26 + 0x0C0 q20 x23 + 0x0C8 x24 + 0x0D0 q21 x21 + 0x0D8 x22 + 0x0E0 q18 x19 + 0x0E8 x20 + 0x0F0 q19 x29 + 0x0F8 x30 + 0x100 q16 + 0x110 q17 + 0x120 q14 + 0x130 q15 + 0x140 q12 + 0x150 q13 + 0x160 q10 + 0x170 q11 + 0x180 q8 + 0x190 q9 + 0x1A0 q6 + 0x1B0 q7 + 0x1C0 q4 + 0x1D0 q5 + 0x1E0 q2 + 0x1F0 q3 + 0x200 q0 + 0x210 q1 + 0x220 x28 + 0x228 reserved + 0x230 x26 + 0x238 x27 + 0x240 x24 + 0x248 x25 + 0x250 x22 + 0x258 x23 + 0x260 x20 + 0x268 x21 + 0x270 x18 + 0x278 x19 + 0x280 x16 + 0x288 x17 + 0x290 x14 + 0x298 x15 + 0x2A0 x12 + 0x2A8 x13 + 0x2B0 x10 + 0x2B8 x11 + 0x2C0 x8 + 0x2C8 x9 + 0x2D0 x6 + 0x2D8 x7 + 0x2E0 x4 + 0x2E8 x5 + 0x2F0 x2 + 0x2F8 x3 + 0x300 x0 + 0x308 x1 + 0x310 x29 + 0x318 x30 + + + +6. Improving Performance + +The distribution version of ThreadX SMP is built without any compiler optimizations. +This makes it easy to debug because you can trace or set breakpoints inside of +ThreadX SMP itself. Of course, this costs some performance. To make it run faster, +you can change the project settings to the desired compiler optimization level. + +In addition, you can eliminate the ThreadX SMP basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX SMP provides complete and high-performance interrupt handling for Cortex-A35 +targets. Interrupts handlers for the 64-bit mode of the Cortex-A35 have the following +format: + + .global irq_handler +irq_handler: + MSR SPSel, 0 + STP x29, x30, [sp, #-16]! + BL _tx_thread_context_save + + /* Your ISR call goes here! */ + BL application_isr_handler + + B _tx_thread_context_restore + +By default, ThreadX SMP assumes EL3 level of execution. Running and taking exceptions in EL1 +and EL2 can be done by simply building the ThreadX library with either EL1 or EL2 defined. + + +8. ThreadX SMP Timer Interrupt + +ThreadX SMP requires a periodic interrupt source to manage all time-slicing, thread sleeps, +timeouts, and application timers. Without such a timer interrupt source, these services +are not functional. However, all other ThreadX services are operational without a +periodic timer source. + + +9. ARM FP Support + +By default, FP support is disabled for each thread. If saving the context of the FP registers +is needed, the following API call must be made from the context of the application thread - before +the FP usage: + +void tx_thread_fp_enable(void); + +After this API is called in the application, FP registers will be saved/restored for this thread if it +is preempted via an interrupt. All other suspension of the this thread will not require the FP registers +to be saved/restored. + +To disable FP register context saving, simply call the following API: + +void tx_thread_fp_disable(void); + + +10. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX SMP: + +09-30-2020 Initial ThreadX 6.1 version for Cortex-A35 using ARM GCC and DS tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_initialize_low_level.S b/ports_smp/cortex_a35_smp/gnu/src/tx_initialize_low_level.S new file mode 100644 index 00000000..8faa8569 --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_initialize_low_level.S @@ -0,0 +1,112 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-A35-SMP/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_initialize_low_level(VOID) +{ */ + .global _tx_initialize_low_level + .type _tx_initialize_low_level, @function +_tx_initialize_low_level: + + MSR DAIFSet, 0x3 // Lockout interrupts + + + /* Save the system stack pointer. */ + /* _tx_thread_system_stack_ptr = (VOID_PTR) (sp); */ + + LDR x0, =_tx_thread_system_stack_ptr // Pickup address of system stack ptr + MOV x1, sp // Pickup SP + SUB x1, x1, #15 // + BIC x1, x1, #0xF // Get 16-bit alignment + STR x1, [x0] // Store system stack + + /* Save the first available memory address. */ + /* _tx_initialize_unused_memory = (VOID_PTR) __top_of_ram; */ + + LDR x0, =_tx_initialize_unused_memory // Pickup address of unused memory ptr + LDR x1, =__top_of_ram // Pickup unused memory address - A free + // memory section must be setup after the + // heap section. + STR x1, [x0] // Store unused memory address + + /* Done, return to caller. */ + + RET // Return to caller +/* } */ + + .align 3 + diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_context_restore.S b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_context_restore.S new file mode 100644 index 00000000..c2d70f36 --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_context_restore.S @@ -0,0 +1,393 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + +/* Include macros for modifying the wait list. */ +#include "tx_thread_smp_protection_wait_list_macros.h" + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore Cortex-A35-SMP/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores the interrupt context if it is processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_restore(VOID) +{ */ + .global _tx_thread_context_restore + .type _tx_thread_context_restore, @function +_tx_thread_context_restore: + + /* Lockout interrupts. */ + + MSR DAIFSet, 0x3 // Lockout interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR exit function to indicate an ISR is complete. */ + + BL _tx_execution_isr_exit // Call the ISR exit function +#endif + + /* Pickup the CPU ID. */ + + MRS x8, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x2, x8, #8, #8 // Isolate cluster ID +#endif + UBFX x8, x8, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x8, x8, x2, LSL #2 // Calculate CPU ID +#endif + + /* Determine if interrupts are nested. */ + /* if (--_tx_thread_system_state) + { */ + + LDR x3, =_tx_thread_system_state // Pickup address of system state var + LDR w2, [x3, x8, LSL #2] // Pickup system state + SUB w2, w2, #1 // Decrement the counter + STR w2, [x3, x8, LSL #2] // Store the counter + CMP w2, #0 // Was this the first interrupt? + BEQ __tx_thread_not_nested_restore // If so, not a nested restore + + /* Interrupts are nested. */ + + /* Just recover the saved registers and return to the point of + interrupt. */ + + LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL +#ifdef EL1 + MSR SPSR_EL1, x4 // Setup SPSR for return + MSR ELR_EL1, x5 // Setup point of interrupt +#else +#ifdef EL2 + MSR SPSR_EL2, x4 // Setup SPSR for return + MSR ELR_EL2, x5 // Setup point of interrupt +#else + MSR SPSR_EL3, x4 // Setup SPSR for return + MSR ELR_EL3, x5 // Setup point of interrupt +#endif +#endif + LDP x18, x19, [sp], #16 // Recover x18, x19 + LDP x16, x17, [sp], #16 // Recover x16, x17 + LDP x14, x15, [sp], #16 // Recover x14, x15 + LDP x12, x13, [sp], #16 // Recover x12, x13 + LDP x10, x11, [sp], #16 // Recover x10, x11 + LDP x8, x9, [sp], #16 // Recover x8, x9 + LDP x6, x7, [sp], #16 // Recover x6, x7 + LDP x4, x5, [sp], #16 // Recover x4, x5 + LDP x2, x3, [sp], #16 // Recover x2, x3 + LDP x0, x1, [sp], #16 // Recover x0, x1 + LDP x29, x30, [sp], #16 // Recover x29, x30 + ERET // Return to point of interrupt + + /* } */ +__tx_thread_not_nested_restore: + + /* Determine if a thread was interrupted and no preemption is required. */ + /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) + || (_tx_thread_preempt_disable)) + { */ + + LDR x1, =_tx_thread_current_ptr // Pickup address of current thread ptr + LDR x0, [x1, x8, LSL #3] // Pickup actual current thread pointer + CMP x0, #0 // Is it NULL? + BEQ __tx_thread_idle_system_restore // Yes, idle system was interrupted + LDR x3, =_tx_thread_execute_ptr // Pickup address of execute thread ptr + LDR x2, [x3, x8, LSL #3] // Pickup actual execute thread pointer + CMP x0, x2 // Is the same thread highest priority? + BEQ __tx_thread_no_preempt_restore // Same thread in the execute list, + // no preemption needs to happen + LDR x3, =_tx_thread_smp_protection // Build address to protection structure + LDR w3, [x3, #4] // Pickup the owning core + CMP w3, w8 // Is it this core? + BNE __tx_thread_preempt_restore // No, proceed to preempt thread + + LDR x3, =_tx_thread_preempt_disable // Pickup preempt disable address + LDR w2, [x3, #0] // Pickup actual preempt disable flag + CMP w2, #0 // Is it set? + BEQ __tx_thread_preempt_restore // No, okay to preempt this thread + +__tx_thread_no_preempt_restore: + + /* Restore interrupted thread or ISR. */ + + /* Pickup the saved stack pointer. */ + /* sp = _tx_thread_current_ptr -> tx_thread_stack_ptr; */ + + LDR x4, [x0, #8] // Switch to thread stack pointer + MOV sp, x4 // + + /* Recover the saved context and return to the point of interrupt. */ + + LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL1 +#ifdef EL1 + MSR SPSR_EL1, x4 // Setup SPSR for return + MSR ELR_EL1, x5 // Setup point of interrupt +#else +#ifdef EL2 + MSR SPSR_EL2, x4 // Setup SPSR for return + MSR ELR_EL2, x5 // Setup point of interrupt +#else + MSR SPSR_EL3, x4 // Setup SPSR for return + MSR ELR_EL3, x5 // Setup point of interrupt +#endif +#endif + LDP x18, x19, [sp], #16 // Recover x18, x19 + LDP x16, x17, [sp], #16 // Recover x16, x17 + LDP x14, x15, [sp], #16 // Recover x14, x15 + LDP x12, x13, [sp], #16 // Recover x12, x13 + LDP x10, x11, [sp], #16 // Recover x10, x11 + LDP x8, x9, [sp], #16 // Recover x8, x9 + LDP x6, x7, [sp], #16 // Recover x6, x7 + LDP x4, x5, [sp], #16 // Recover x4, x5 + LDP x2, x3, [sp], #16 // Recover x2, x3 + LDP x0, x1, [sp], #16 // Recover x0, x1 + LDP x29, x30, [sp], #16 // Recover x29, x30 + ERET // Return to point of interrupt + + /* } + else + { */ +__tx_thread_preempt_restore: + + /* Was the thread being preempted waiting for the lock? */ + /* if (_tx_thread_smp_protect_wait_counts[this_core] != 0) + { */ + + LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list + LDR w3, [x2, x8, LSL #2] // Load waiting value for this core + CMP w3, #0 + BEQ _nobody_waiting_for_lock // Is the core waiting for the lock? + + /* Do we not have the lock? This means the ISR never got the inter-core lock. */ + /* if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core) + { */ + + LDR x2, =_tx_thread_smp_protection // Load address of protection structure + LDR w3, [x2, #4] // Pickup the owning core + CMP w8, w3 // Compare our core to the owning core + BEQ _this_core_has_lock // Do we have the lock? + + /* We don't have the lock. This core should be in the list. Remove it. */ + /* _tx_thread_smp_protect_wait_list_remove(this_core); */ + + _tx_thread_smp_protect_wait_list_remove // Call macro to remove core from the list + B _nobody_waiting_for_lock // Leave + + /* } + else + { */ + /* We have the lock. This means the ISR got the inter-core lock, but + never released it because it saw that there was someone waiting. + Note this core is not in the list. */ + +_this_core_has_lock: + + /* We're no longer waiting. Note that this should be zero since this happens during thread preemption. */ + /* _tx_thread_smp_protect_wait_counts[core]--; */ + + LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list + LDR w3, [x2, x8, LSL #2] // Load waiting value for this core + SUB w3, w3, #1 // Decrement waiting value. Should be zero now + STR w3, [x2, x8, LSL #2] // Store new waiting value + + /* Now release the inter-core lock. */ + + /* Set protected core as invalid. */ + /* _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF; */ + + LDR x2, =_tx_thread_smp_protection // Load address of protection structure + MOV w3, #0xFFFFFFFF // Build invalid value + STR w3, [x2, #4] // Mark the protected core as invalid + DMB ISH // Ensure that accesses to shared resource have completed + + /* Release protection. */ + /* _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0; */ + + MOV w3, #0 // Build release protection value + STR w3, [x2, #0] // Release the protection + DSB ISH // To ensure update of the protection occurs before other CPUs awake + + /* Wake up waiting processors. Note interrupts are already enabled. */ + +#ifdef TX_ENABLE_WFE + SEV // Send event to other CPUs +#endif + + /* } + } */ + +_nobody_waiting_for_lock: + + LDR x4, [x0, #8] // Switch to thread stack pointer + MOV sp, x4 // + + LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL1 + STP x20, x21, [sp, #-16]! // Save x20, x21 + STP x22, x23, [sp, #-16]! // Save x22, x23 + STP x24, x25, [sp, #-16]! // Save x24, x25 + STP x26, x27, [sp, #-16]! // Save x26, x27 + STP x28, x29, [sp, #-16]! // Save x28, x29 +#ifdef ENABLE_ARM_FP + LDR w3, [x0, #268] // Pickup FP enable flag + CMP w3, #0 // Is FP enabled? + BEQ _skip_fp_save // No, skip FP save + STP q0, q1, [sp, #-32]! // Save q0, q1 + STP q2, q3, [sp, #-32]! // Save q2, q3 + STP q4, q5, [sp, #-32]! // Save q4, q5 + STP q6, q7, [sp, #-32]! // Save q6, q7 + STP q8, q9, [sp, #-32]! // Save q8, q9 + STP q10, q11, [sp, #-32]! // Save q10, q11 + STP q12, q13, [sp, #-32]! // Save q12, q13 + STP q14, q15, [sp, #-32]! // Save q14, q15 + STP q16, q17, [sp, #-32]! // Save q16, q17 + STP q18, q19, [sp, #-32]! // Save q18, q19 + STP q20, q21, [sp, #-32]! // Save q20, q21 + STP q22, q23, [sp, #-32]! // Save q22, q23 + STP q24, q25, [sp, #-32]! // Save q24, q25 + STP q26, q27, [sp, #-32]! // Save q26, q27 + STP q28, q29, [sp, #-32]! // Save q28, q29 + STP q30, q31, [sp, #-32]! // Save q30, q31 + MRS x2, FPSR // Pickup FPSR + MRS x3, FPCR // Pickup FPCR + STP x2, x3, [sp, #-16]! // Save FPSR, FPCR +_skip_fp_save: +#endif + STP x4, x5, [sp, #-16]! // Save x4 (SPSR_EL3), x5 (ELR_E3) + + MOV x3, sp // Move sp into x3 + STR x3, [x0, #8] // Save stack pointer in thread control + // block + LDR x3, =_tx_thread_system_stack_ptr // Pickup address of system stack + LDR x4, [x3, x8, LSL #3] // Pickup system stack pointer + MOV sp, x4 // Setup system stack pointer + + + /* Save the remaining time-slice and disable it. */ + /* if (_tx_timer_time_slice) + { */ + + LDR x3, =_tx_timer_time_slice // Pickup time-slice variable address + LDR w2, [x3, x8, LSL #2] // Pickup time-slice + CMP w2, #0 // Is it active? + BEQ __tx_thread_dont_save_ts // No, don't save it + + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + STR w2, [x0, #36] // Save thread's time-slice + MOV w2, #0 // Clear value + STR w2, [x3, x8, LSL #2] // Disable global time-slice flag + + /* } */ +__tx_thread_dont_save_ts: + + + /* Clear the current task pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + MOV x2, #0 // NULL value + STR x2, [x1, x8, LSL #3] // Clear current thread pointer + + /* Set bit indicating this thread is ready for execution. */ + + MOV x2, #1 // Build ready flag + STR w2, [x0, #260] // Set thread's ready flag + DMB ISH // Ensure that accesses to shared resource have completed + + /* Return to the scheduler. */ + /* _tx_thread_schedule(); */ + + /* } */ + +__tx_thread_idle_system_restore: + + /* Just return back to the scheduler! */ + + LDR x1, =_tx_thread_schedule // Build address for _tx_thread_schedule +#ifdef EL1 + MSR ELR_EL1, x1 // Setup point of interrupt +// MOV x1, #0x4 // Setup EL1 return +// MSR spsr_el1, x1 // Move into SPSR +#else +#ifdef EL2 + MSR ELR_EL2, x1 // Setup point of interrupt +// MOV x1, #0x8 // Setup EL2 return +// MSR spsr_el2, x1 // Move into SPSR +#else + MSR ELR_EL3, x1 // Setup point of interrupt +// MOV x1, #0xC // Setup EL3 return +// MSR spsr_el3, x1 // Move into SPSR +#endif +#endif + ERET // Return to scheduler +/* } */ + + diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_context_save.S b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_context_save.S new file mode 100644 index 00000000..2ff09f73 --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_context_save.S @@ -0,0 +1,249 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save Cortex-A35-SMP/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_save(VOID) +{ */ + .global _tx_thread_context_save + .type _tx_thread_context_save, @function +_tx_thread_context_save: + + /* Upon entry to this routine, it is assumed that IRQ/FIQ interrupts are locked + out, x29 (frame pointer), x30 (link register) are saved, we are in the proper EL, + and all other registers are intact. */ + + /* Check for a nested interrupt condition. */ + /* if (_tx_thread_system_state++) + { */ + + STP x0, x1, [sp, #-16]! // Save x0, x1 + STP x2, x3, [sp, #-16]! // Save x2, x3 + + /* Pickup the CPU ID. */ + + MRS x1, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x2, x1, #8, #8 // Isolate cluster ID +#endif + UBFX x1, x1, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x1, x1, x2, LSL #2 // Calculate CPU ID +#endif + + LDR x3, =_tx_thread_system_state // Pickup address of system state var + LDR w2, [x3, x1, LSL #2] // Pickup system state + CMP w2, #0 // Is this the first interrupt? + BEQ __tx_thread_not_nested_save // Yes, not a nested context save + + /* Nested interrupt condition. */ + + ADD w2, w2, #1 // Increment the nested interrupt counter + STR w2, [x3, x1, LSL #2] // Store it back in the variable + + /* Save the rest of the scratch registers on the stack and return to the + calling ISR. */ + + STP x4, x5, [sp, #-16]! // Save x4, x5 + STP x6, x7, [sp, #-16]! // Save x6, x7 + STP x8, x9, [sp, #-16]! // Save x8, x9 + STP x10, x11, [sp, #-16]! // Save x10, x11 + STP x12, x13, [sp, #-16]! // Save x12, x13 + STP x14, x15, [sp, #-16]! // Save x14, x15 + STP x16, x17, [sp, #-16]! // Save x16, x17 + STP x18, x19, [sp, #-16]! // Save x18, x19 +#ifdef EL1 + MRS x0, SPSR_EL1 // Pickup SPSR + MRS x1, ELR_EL1 // Pickup ELR (point of interrupt) +#else +#ifdef EL2 + MRS x0, SPSR_EL2 // Pickup SPSR + MRS x1, ELR_EL2 // Pickup ELR (point of interrupt) +#else + MRS x0, SPSR_EL3 // Pickup SPSR + MRS x1, ELR_EL3 // Pickup ELR (point of interrupt) +#endif +#endif + STP x0, x1, [sp, #-16]! // Save SPSR, ELR + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + STP x29, x30, [sp, #-16]! // Save x29, x30 + BL _tx_execution_isr_enter // Call the ISR enter function + LDP x29, x30, [sp], #16 // Recover x29, x30 +#endif + + /* Return to the ISR. */ + + RET // Return to ISR + +__tx_thread_not_nested_save: + /* } */ + + /* Otherwise, not nested, check to see if a thread was running. */ + /* else if (_tx_thread_current_ptr) + { */ + + ADD w2, w2, #1 // Increment the interrupt counter + STR w2, [x3, x1, LSL #2] // Store it back in the variable + LDR x2, =_tx_thread_current_ptr // Pickup address of current thread ptr + LDR x0, [x2, x1, LSL #3] // Pickup current thread pointer + CMP x0, #0 // Is it NULL? + BEQ __tx_thread_idle_system_save // If so, interrupt occurred in + // scheduling loop - nothing needs saving! + + /* Save minimal context of interrupted thread. */ + + STP x4, x5, [sp, #-16]! // Save x4, x5 + STP x6, x7, [sp, #-16]! // Save x6, x7 + STP x8, x9, [sp, #-16]! // Save x8, x9 + STP x10, x11, [sp, #-16]! // Save x10, x11 + STP x12, x13, [sp, #-16]! // Save x12, x13 + STP x14, x15, [sp, #-16]! // Save x14, x15 + STP x16, x17, [sp, #-16]! // Save x16, x17 + STP x18, x19, [sp, #-16]! // Save x18, x19 +#ifdef EL1 + MRS x4, SPSR_EL1 // Pickup SPSR + MRS x5, ELR_EL1 // Pickup ELR (point of interrupt) +#else +#ifdef EL2 + MRS x4, SPSR_EL2 // Pickup SPSR + MRS x5, ELR_EL2 // Pickup ELR (point of interrupt) +#else + MRS x4, SPSR_EL3 // Pickup SPSR + MRS x5, ELR_EL3 // Pickup ELR (point of interrupt) +#endif +#endif + STP x4, x5, [sp, #-16]! // Save SPSR, ELR + + /* Save the current stack pointer in the thread's control block. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ + + MOV x4, sp // + STR x4, [x0, #8] // Save thread stack pointer + + /* Switch to the system stack. */ + /* sp = _tx_thread_system_stack_ptr; */ + + LDR x3, =_tx_thread_system_stack_ptr // Pickup address of system stack + MRS x1, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x2, x1, #8, #8 // Isolate cluster ID +#endif + UBFX x1, x1, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x1, x1, x2, LSL #2 // Calculate CPU ID +#endif + + LDR x4, [x3, x1, LSL #3] // Pickup system stack pointer + MOV sp, x4 // Setup system stack pointer + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + STP x29, x30, [sp, #-16]! // Save x29, x30 + BL _tx_execution_isr_enter // Call the ISR enter function + LDP x29, x30, [sp], #16 // Recover x29, x30 +#endif + + RET // Return to caller + + /* } + else + { */ + +__tx_thread_idle_system_save: + + /* Interrupt occurred in the scheduling loop. */ + + /* Not much to do here, just adjust the stack pointer, and return to IRQ + processing. */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + STP x29, x30, [sp, #-16]! // Save x29, x30 + BL _tx_execution_isr_enter // Call the ISR enter function + LDP x29, x30, [sp], #16 // Recover x29, x30 +#endif + + ADD sp, sp, #48 // Recover saved registers + RET // Continue IRQ processing + + /* } +} */ + + diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_fp_disable.c b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_fp_disable.c new file mode 100644 index 00000000..6c7944bd --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_fp_disable.c @@ -0,0 +1,95 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fp_disable Cortex-A35-SMP/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function disables the FP for the currently executing thread. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_fp_disable(VOID) +{ + +TX_THREAD *thread_ptr; +ULONG system_state; + + + /* Pickup the current thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr); + + /* Get the system state. */ + system_state = TX_THREAD_GET_SYSTEM_STATE(); + + /* Make sure it is not NULL. */ + if (thread_ptr != TX_NULL) + { + + /* Thread is running... make sure the call is from the thread context. */ + if (system_state == 0) + { + + /* Yes, now set the FP enable flag to false in the TX_THREAD structure. */ + thread_ptr -> tx_thread_fp_enable = TX_FALSE; + } + } +} + diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_fp_enable.c b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_fp_enable.c new file mode 100644 index 00000000..d1ef9e34 --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_fp_enable.c @@ -0,0 +1,94 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fp_enable Cortex-A35-SMP/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function enabled the FP for the currently executing thread. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_fp_enable(VOID) +{ + +TX_THREAD *thread_ptr; +ULONG system_state; + + + /* Pickup the current thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr); + + /* Get the system state. */ + system_state = TX_THREAD_GET_SYSTEM_STATE(); + + /* Make sure it is not NULL. */ + if (thread_ptr != TX_NULL) + { + + /* Thread is running... make sure the call is from the thread context. */ + if (system_state == 0) + { + + /* Yes, now setup the FP enable flag in the TX_THREAD structure. */ + thread_ptr -> tx_thread_fp_enable = TX_TRUE; + } + } +} + diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..ec93cf89 --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_interrupt_control.S @@ -0,0 +1,89 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/*#define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control Cortex-A35-SMP/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_control(UINT new_posture) +{ */ + .global _tx_thread_interrupt_control + .type _tx_thread_interrupt_control, @function +_tx_thread_interrupt_control: + + /* Pickup current interrupt lockout posture. */ + + MRS x1, DAIF // Pickup current interrupt posture + + /* Apply the new interrupt posture. */ + + MSR DAIF, x0 // Set new interrupt posture + MOV x0, x1 // Setup return value + RET // Return to caller +/* } */ + diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_interrupt_disable.S new file mode 100644 index 00000000..c59bf57a --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_interrupt_disable.S @@ -0,0 +1,87 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_disable Cortex-A35-SMP/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for disabling interrupts */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_disable(void) +{ */ + .global _tx_thread_interrupt_disable + .type _tx_thread_interrupt_disable, @function +_tx_thread_interrupt_disable: + + /* Pickup current interrupt lockout posture. */ + + MRS x0, DAIF // Pickup current interrupt lockout posture + + /* Mask interrupts. */ + + MSR DAIFSet, 0x3 // Lockout interrupts + RET // Return to caller +/* } */ + diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_interrupt_restore.S new file mode 100644 index 00000000..7b3d9101 --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_interrupt_restore.S @@ -0,0 +1,85 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_restore Cortex-A35-SMP/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for restoring interrupts to the state */ +/* returned by a previous _tx_thread_interrupt_disable call. */ +/* */ +/* INPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_restore(UINT old_posture) +{ */ + .global _tx_thread_interrupt_restore + .type _tx_thread_interrupt_restore, @function +_tx_thread_interrupt_restore: + + /* Restore the old interrupt posture. */ + + MSR DAIF, x0 // Setup the old posture + RET // Return to caller + +/* } */ + diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_schedule.S b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_schedule.S new file mode 100644 index 00000000..235f8a20 --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_schedule.S @@ -0,0 +1,307 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule Cortex-A35-SMP/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* _tx_thread_context_restore Restore thread's context */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_schedule(VOID) +{ */ + .global _tx_thread_schedule + .type _tx_thread_schedule, @function +_tx_thread_schedule: + + /* Enable interrupts. */ + + MSR DAIFClr, 0x3 // Enable interrupts + + /* Pickup the CPU ID. */ + + MRS x20, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x1, x20, #8, #8 // Isolate cluster ID +#endif + UBFX x20, x20, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x20, x20, x1, LSL #2 // Calculate CPU ID +#endif + + /* Wait for a thread to execute. */ + /* do + { */ + + LDR x1, =_tx_thread_execute_ptr // Address of thread execute ptr + +#ifdef TX_ENABLE_WFI +__tx_thread_schedule_loop: + MSR DAIFSet, 0x3 // Lockout interrupts + LDR x0, [x1, x20, LSL #3] // Pickup next thread to execute + CMP x0, #0 // Is it NULL? + BNE _tx_thread_schedule_thread // + MSR DAIFClr, 0x3 // Enable interrupts + WFI // + B __tx_thread_schedule_loop // Keep looking for a thread +_tx_thread_schedule_thread: +#else + MSR DAIFSet, 0x3 // Lockout interrupts + LDR x0, [x1, x20, LSL #3] // Pickup next thread to execute + CMP x0, #0 // Is it NULL? + BEQ _tx_thread_schedule // Keep looking for a thread +#endif + + /* } + while(_tx_thread_execute_ptr == TX_NULL); */ + + /* Get the lock for accessing the thread's ready bit. */ + + MOV w2, #280 // Build offset to the lock + ADD x2, x0, x2 // Get the address to the lock + LDAXR w3, [x2] // Pickup the lock value + CMP w3, #0 // Check if it's available + BNE _tx_thread_schedule // No, lock not available + MOV w3, #1 // Build the lock set value + STXR w4, w3, [x2] // Try to get the lock + CMP w4, #0 // Check if we got the lock + BNE _tx_thread_schedule // No, another core got it first + DMB ISH // Ensure write to lock completes + + /* Now make sure the thread's ready bit is set. */ + + LDR w3, [x0, #260] // Pickup the thread ready bit + CMP w3, #0 // Is it set? + BNE _tx_thread_ready_for_execution // Yes, schedule the thread + + /* The ready bit isn't set. Release the lock and jump back to the scheduler. */ + + MOV w3, #0 // Build clear value + STR w3, [x2] // Release the lock + DMB ISH // Ensure write to lock completes + B _tx_thread_schedule // Jump back to the scheduler + +_tx_thread_ready_for_execution: + + /* We have a thread to execute. */ + + /* Clear the ready bit and release the lock. */ + + MOV w3, #0 // Build clear value + STR w3, [x0, #260] // Store it back in the thread control block + DMB ISH + MOV w3, #0 // Build clear value for the lock + STR w3, [x2] // Release the lock + DMB ISH + + /* Setup the current thread pointer. */ + /* _tx_thread_current_ptr = _tx_thread_execute_ptr; */ + + LDR x2, =_tx_thread_current_ptr // Pickup address of current thread + STR x0, [x2, x20, LSL #3] // Setup current thread pointer + + LDR x1, [x1, x20, LSL #3] // Reload the execute pointer + CMP w0, w1 // Did it change? + BEQ _execute_pointer_did_not_change // If not, skip handling + + /* In the time between reading the execute pointer and assigning + it to the current pointer, the execute pointer was changed by + some external code. If the current pointer was still null when + the external code checked if a core preempt was necessary, then + it wouldn't have done it and a preemption will be missed. To + handle this, undo some things and jump back to the scheduler so + it can schedule the new thread. */ + + MOV w1, #0 // Build clear value + STR x1, [x2, x20, LSL #3] // Clear current thread pointer + + MOV w1, #1 // Build set value + STR w1, [x0, #260] // Re-set the ready bit + DMB ISH // + + B _tx_thread_schedule // Jump back to the scheduler to schedule the new thread + +_execute_pointer_did_not_change: + /* Increment the run count for this thread. */ + /* _tx_thread_current_ptr -> tx_thread_run_count++; */ + + LDR w2, [x0, #4] // Pickup run counter + LDR w3, [x0, #36] // Pickup time-slice for this thread + ADD w2, w2, #1 // Increment thread run-counter + STR w2, [x0, #4] // Store the new run counter + + /* Setup time-slice, if present. */ + /* _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; */ + + LDR x2, =_tx_timer_time_slice // Pickup address of time slice + // variable + LDR x4, [x0, #8] // Switch stack pointers + MOV sp, x4 // + STR w3, [x2, x20, LSL #2] // Setup time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread entry function to indicate the thread is executing. */ + + MOV x19, x0 // Save x0 + BL _tx_execution_thread_enter // Call the thread execution enter function + MOV x0, x19 // Restore x0 +#endif + + /* Switch to the thread's stack. */ + /* sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; */ + + /* Determine if an interrupt frame or a synchronous task suspension frame + is present. */ + + LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL1 + CMP x5, #0 // Check for synchronous context switch (ELR_EL1 = NULL) + BEQ _tx_solicited_return +#ifdef EL1 + MSR SPSR_EL1, x4 // Setup SPSR for return + MSR ELR_EL1, x5 // Setup point of interrupt +#else +#ifdef EL2 + MSR SPSR_EL2, x4 // Setup SPSR for return + MSR ELR_EL2, x5 // Setup point of interrupt +#else + MSR SPSR_EL3, x4 // Setup SPSR for return + MSR ELR_EL3, x5 // Setup point of interrupt +#endif +#endif +#ifdef ENABLE_ARM_FP + LDR w1, [x0, #268] // Pickup FP enable flag + CMP w1, #0 // Is FP enabled? + BEQ _skip_interrupt_fp_restore // No, skip FP restore + LDP x0, x1, [sp], #16 // Pickup FPSR, FPCR + MSR FPSR, x0 // Recover FPSR + MSR FPCR, x1 // Recover FPCR + LDP q30, q31, [sp], #32 // Recover q30, q31 + LDP q28, q29, [sp], #32 // Recover q28, q29 + LDP q26, q27, [sp], #32 // Recover q26, q27 + LDP q24, q25, [sp], #32 // Recover q24, q25 + LDP q22, q23, [sp], #32 // Recover q22, q23 + LDP q20, q21, [sp], #32 // Recover q20, q21 + LDP q18, q19, [sp], #32 // Recover q18, q19 + LDP q16, q17, [sp], #32 // Recover q16, q17 + LDP q14, q15, [sp], #32 // Recover q14, q15 + LDP q12, q13, [sp], #32 // Recover q12, q13 + LDP q10, q11, [sp], #32 // Recover q10, q11 + LDP q8, q9, [sp], #32 // Recover q8, q9 + LDP q6, q7, [sp], #32 // Recover q6, q7 + LDP q4, q5, [sp], #32 // Recover q4, q5 + LDP q2, q3, [sp], #32 // Recover q2, q3 + LDP q0, q1, [sp], #32 // Recover q0, q1 +_skip_interrupt_fp_restore: +#endif + LDP x28, x29, [sp], #16 // Recover x28 + LDP x26, x27, [sp], #16 // Recover x26, x27 + LDP x24, x25, [sp], #16 // Recover x24, x25 + LDP x22, x23, [sp], #16 // Recover x22, x23 + LDP x20, x21, [sp], #16 // Recover x20, x21 + LDP x18, x19, [sp], #16 // Recover x18, x19 + LDP x16, x17, [sp], #16 // Recover x16, x17 + LDP x14, x15, [sp], #16 // Recover x14, x15 + LDP x12, x13, [sp], #16 // Recover x12, x13 + LDP x10, x11, [sp], #16 // Recover x10, x11 + LDP x8, x9, [sp], #16 // Recover x8, x9 + LDP x6, x7, [sp], #16 // Recover x6, x7 + LDP x4, x5, [sp], #16 // Recover x4, x5 + LDP x2, x3, [sp], #16 // Recover x2, x3 + LDP x0, x1, [sp], #16 // Recover x0, x1 + LDP x29, x30, [sp], #16 // Recover x29, x30 + ERET // Return to point of interrupt + +_tx_solicited_return: + +#ifdef ENABLE_ARM_FP + LDR w1, [x0, #268] // Pickup FP enable flag + CMP w1, #0 // Is FP enabled? + BEQ _skip_solicited_fp_restore // No, skip FP restore + LDP x0, x1, [sp], #16 // Pickup FPSR, FPCR + MSR FPSR, x0 // Recover FPSR + MSR FPCR, x1 // Recover FPCR + LDP q14, q15, [sp], #32 // Recover q14, q15 + LDP q12, q13, [sp], #32 // Recover q12, q13 + LDP q10, q11, [sp], #32 // Recover q10, q11 + LDP q8, q9, [sp], #32 // Recover q8, q9 +_skip_solicited_fp_restore: +#endif + LDP x27, x28, [sp], #16 // Recover x27, x28 + LDP x25, x26, [sp], #16 // Recover x25, x26 + LDP x23, x24, [sp], #16 // Recover x23, x24 + LDP x21, x22, [sp], #16 // Recover x21, x22 + LDP x19, x20, [sp], #16 // Recover x19, x20 + LDP x29, x30, [sp], #16 // Recover x29, x30 + MSR DAIF, x4 // Recover DAIF + RET // Return to caller +/* } */ + + diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_core_get.S new file mode 100644 index 00000000..d5216ced --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_core_get.S @@ -0,0 +1,89 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_core_get Cortex-A35-SMP/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets the currently running core number and returns it.*/ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* Core ID */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Source */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_core_get + .type _tx_thread_smp_core_get, @function +_tx_thread_smp_core_get: + MRS x0, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x1, x0, #8, #8 // Isolate cluster ID +#endif + UBFX x0, x0, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x0, x0, x1, LSL #2 // Calculate CPU ID +#endif + RET + + diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_core_preempt.S new file mode 100644 index 00000000..9805fd01 --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_core_preempt.S @@ -0,0 +1,89 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + +#define ICC_SGI1R_EL1 S3_0_C12_C11_5 + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_core_preempt Cortex-A35-SMP/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function preempts the specified core in situations where the */ +/* thread corresponding to this core is no longer ready or when the */ +/* core must be used for a higher-priority thread. If the specified is */ +/* the current core, this processing is skipped since the will give up */ +/* control subsequently on its own. */ +/* */ +/* INPUT */ +/* */ +/* core The core to preempt */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Source */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_core_preempt + .type _tx_thread_smp_core_preempt, @function +_tx_thread_smp_core_preempt: + DSB ISH + MOV x2, #0x1 // + LSL x2, x2, x0 // Shift by the core ID + MSR ICC_SGI1R_EL1, x2 // Issue inter-core interrupt + RET + diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_current_state_get.S new file mode 100644 index 00000000..a783be4d --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_current_state_get.S @@ -0,0 +1,95 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_current_state_get Cortex-A35-SMP/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is gets the current state of the calling core. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_current_state_get + .type _tx_thread_smp_current_state_get, @function +_tx_thread_smp_current_state_get: + + MRS x1, DAIF // Pickup current interrupt posture + MSR DAIFSet, 0x3 // Lockout interrupts + MRS x2, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x3, x2, #8, #8 // Isolate cluster ID +#endif + UBFX x2, x2, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x2, x2, x3, LSL #2 // Calculate CPU ID +#endif + LDR x3, =_tx_thread_system_state // Pickup the base of the current system state array + LDR w0, [x3, x2, LSL #2] // Pickup the current system state for this core + MSR DAIF, x1 // Restore interrupt posture + RET + + diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_current_thread_get.S new file mode 100644 index 00000000..08759e6c --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_current_thread_get.S @@ -0,0 +1,94 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_current_thread_get Cortex-A35-SMP/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is gets the current thread of the calling core. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_current_thread_get + .type _tx_thread_smp_current_thread_get, @function +_tx_thread_smp_current_thread_get: + + MRS x1, DAIF // Pickup current interrupt posture + MSR DAIFSet, 0x3 // Lockout interrupts + MRS x2, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x3, x2, #8, #8 // Isolate cluster ID +#endif + UBFX x2, x2, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x2, x2, x3, LSL #2 // Calculate CPU ID +#endif + LDR x3, =_tx_thread_current_ptr // Pickup the base of the current thread pointer array + LDR x0, [x3, x2, LSL #3] // Pickup the current thread pointer for this core + MSR DAIF, x1 // Restore interrupt posture + RET + diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_initialize_wait.S new file mode 100644 index 00000000..cf69da98 --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_initialize_wait.S @@ -0,0 +1,143 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_initialize_wait Cortex-A35-SMP/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is the place where additional cores wait until */ +/* initialization is complete before they enter the thread scheduling */ +/* loop. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* Hardware */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_initialize_wait + .type _tx_thread_smp_initialize_wait, @function +_tx_thread_smp_initialize_wait: + + /* Lockout interrupts. */ + + MSR DAIFSet, 0x3 // Lockout interrupts + + /* Pickup the Core ID. */ + + MRS x2, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x3, x2, #8, #8 // Isolate cluster ID +#endif + UBFX x2, x2, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x2, x2, x3, LSL #2 // Calculate CPU ID +#endif + + /* Make sure the system state for this core is TX_INITIALIZE_IN_PROGRESS before we check the release + flag. */ + + LDR w1, =0xF0F0F0F0 // Build TX_INITIALIZE_IN_PROGRESS flag + LDR x3, =_tx_thread_system_state // Pickup the base of the current system state array +wait_for_initialize: + LDR w0, [x3, x2, LSL #2] // Pickup the current system state for this core + CMP w0, w1 // Make sure the TX_INITIALIZE_IN_PROGRESS flag is set + BNE wait_for_initialize // Not equal, just spin here + + /* Save the system stack pointer for this core. */ + + LDR x0, =_tx_thread_system_stack_ptr // Pickup address of system stack ptr + MOV x1, sp // Pickup SP + SUB x1, x1, #15 // + BIC x1, x1, #0xF // Get 16-bit alignment + STR x1, [x0, x2, LSL #3] // Store system stack pointer + + + /* Pickup the release cores flag. */ + + LDR x4, =_tx_thread_smp_release_cores_flag // Build address of release cores flag +wait_for_release: + LDR w0, [x4, #0] // Pickup the flag + CMP w0, #0 // Is it set? + BEQ wait_for_release // Wait for the flag to be set + + /* Core 0 has released this core. */ + + /* Clear this core's system state variable. */ + + MOV x0, #0 // Build clear value + STR w0, [x3, x2, LSL #2] // Set the current system state for this core to zero + + /* Now wait for core 0 to finish it's initialization. */ + +core_0_wait_loop: + LDR w0, [x3, #0] // Pickup the current system state for core 0 + CMP w0, #0 // Is it 0? + BNE core_0_wait_loop // No, keep waiting for core 0 to finish its initialization + + /* Initialization is complete, enter the scheduling loop! */ + + B _tx_thread_schedule // Enter the scheduling loop for this core + + RET + diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_low_level_initialize.S new file mode 100644 index 00000000..cfcf6b4b --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_low_level_initialize.S @@ -0,0 +1,80 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_low_level_initialize Cortex-A35-SMP/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function performs low-level initialization of the booting */ +/* core. */ +/* */ +/* INPUT */ +/* */ +/* number_of_cores Number of cores */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_high_level ThreadX high-level init */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_low_level_initialize + .type _tx_thread_smp_low_level_initialize, @function +_tx_thread_smp_low_level_initialize: + + RET diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_protect.S b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_protect.S new file mode 100644 index 00000000..f0433b89 --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_protect.S @@ -0,0 +1,364 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + +/* Include macros for modifying the wait list. */ +#include "tx_thread_smp_protection_wait_list_macros.h" + + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_protect Cortex-A35-SMP/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets protection for running inside the ThreadX */ +/* source. This is acomplished by a combination of a test-and-set */ +/* flag and periodically disabling interrupts. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* Previous Status Register */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Source */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_protect + .type _tx_thread_smp_protect, @function +_tx_thread_smp_protect: + + /* Disable interrupts so we don't get preempted. */ + + MRS x0, DAIF // Pickup current interrupt posture + MSR DAIFSet, 0x3 // Lockout interrupts + + /* Pickup the CPU ID. */ + + MRS x1, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x7, x1, #8, #8 // Isolate cluster ID +#endif + UBFX x1, x1, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x1, x1, x7, LSL #2 // Calculate CPU ID +#endif + + /* Do we already have protection? */ + /* if (this_core == _tx_thread_smp_protection.tx_thread_smp_protect_core) + { */ + + LDR x2, =_tx_thread_smp_protection // Build address to protection structure + LDR w3, [x2, #4] // Pickup the owning core + CMP w1, w3 // Is it not this core? + BNE _protection_not_owned // No, the protection is not already owned + + /* We already have protection. */ + + /* Increment the protection count. */ + /* _tx_thread_smp_protection.tx_thread_smp_protect_count++; */ + + LDR w3, [x2, #8] // Pickup ownership count + ADD w3, w3, #1 // Increment ownership count + STR w3, [x2, #8] // Store ownership count + DMB ISH + + B _return + +_protection_not_owned: + + /* Is the lock available? */ + /* if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0) + { */ + + LDAXR w3, [x2, #0] // Pickup the protection flag + CMP w3, #0 + BNE _start_waiting // No, protection not available + + /* Is the list empty? */ + /* if (_tx_thread_smp_protect_wait_list_head == _tx_thread_smp_protect_wait_list_tail) + { */ + + LDR x3, =_tx_thread_smp_protect_wait_list_head + LDR w3, [x3] + LDR x4, =_tx_thread_smp_protect_wait_list_tail + LDR w4, [x4] + CMP w3, w4 + BNE _list_not_empty + + /* Try to get the lock. */ + /* if (write_exclusive(&_tx_thread_smp_protection.tx_thread_smp_protect_in_force, 1) == SUCCESS) + { */ + + MOV w3, #1 // Build lock value + STXR w4, w3, [x2, #0] // Attempt to get the protection + CMP w4, #0 + BNE _start_waiting // Did it fail? + + /* We got the lock! */ + /* _tx_thread_smp_protect_lock_got(); */ + + DMB ISH // Ensure write to protection finishes + _tx_thread_smp_protect_lock_got // Call the lock got function + + B _return + +_list_not_empty: + + /* Are we at the front of the list? */ + /* if (this_core == _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head]) + { */ + + LDR x3, =_tx_thread_smp_protect_wait_list_head // Get the address of the head + LDR w3, [x3] // Get the value of the head + LDR x4, =_tx_thread_smp_protect_wait_list // Get the address of the list + LDR w4, [x4, x3, LSL #2] // Get the value at the head index + + CMP w1, w4 + BNE _start_waiting + + /* Is the lock still available? */ + /* if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0) + { */ + + LDR w3, [x2, #0] // Pickup the protection flag + CMP w3, #0 + BNE _start_waiting // No, protection not available + + /* Get the lock. */ + /* _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1; */ + + MOV w3, #1 // Build lock value + STR w3, [x2, #0] // Store lock value + DMB ISH // + + /* Got the lock. */ + /* _tx_thread_smp_protect_lock_got(); */ + + _tx_thread_smp_protect_lock_got + + /* Remove this core from the wait list. */ + /* _tx_thread_smp_protect_remove_from_front_of_list(); */ + + _tx_thread_smp_protect_remove_from_front_of_list + + B _return + +_start_waiting: + + /* For one reason or another, we didn't get the lock. */ + + /* Increment wait count. */ + /* _tx_thread_smp_protect_wait_counts[this_core]++; */ + + LDR x3, =_tx_thread_smp_protect_wait_counts // Load wait list counts + LDR w4, [x3, x1, LSL #2] // Load waiting value for this core + ADD w4, w4, #1 // Increment wait value + STR w4, [x3, x1, LSL #2] // Store new wait value + + /* Have we not added ourselves to the list yet? */ + /* if (_tx_thread_smp_protect_wait_counts[this_core] == 1) + { */ + + CMP w4, #1 + BNE _already_in_list0 // Is this core already waiting? + + /* Add ourselves to the list. */ + /* _tx_thread_smp_protect_wait_list_add(this_core); */ + + _tx_thread_smp_protect_wait_list_add // Call macro to add ourselves to the list + + /* } */ + +_already_in_list0: + + /* Restore interrupts. */ + + MSR DAIF, x0 // Restore interrupts + ISB // +#ifdef TX_ENABLE_WFE + WFE // Go into standby +#endif + + /* We do this until we have the lock. */ + /* while (1) + { */ + +_try_to_get_lock: + + /* Disable interrupts so we don't get preempted. */ + + MRS x0, DAIF // Pickup current interrupt posture + MSR DAIFSet, 0x3 // Lockout interrupts + + /* Pickup the CPU ID. */ + + MRS x1, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x7, x1, #8, #8 // Isolate cluster ID +#endif + UBFX x1, x1, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x1, x1, x7, LSL #2 // Calculate CPU ID +#endif + + /* Do we already have protection? */ + /* if (this_core == _tx_thread_smp_protection.tx_thread_smp_protect_core) + { */ + + LDR w3, [x2, #4] // Pickup the owning core + CMP w3, w1 // Is it this core? + BEQ _got_lock_after_waiting // Yes, the protection is already owned. This means + // an ISR preempted us and got protection + + /* } */ + + /* Are we at the front of the list? */ + /* if (this_core == _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head]) + { */ + + LDR x3, =_tx_thread_smp_protect_wait_list_head // Get the address of the head + LDR w3, [x3] // Get the value of the head + LDR x4, =_tx_thread_smp_protect_wait_list // Get the address of the list + LDR w4, [x4, x3, LSL #2] // Get the value at the head index + + CMP w1, w4 + BNE _did_not_get_lock + + /* Is the lock still available? */ + /* if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0) + { */ + + LDR w3, [x2, #0] // Pickup the protection flag + CMP w3, #0 + BNE _did_not_get_lock // No, protection not available + + /* Get the lock. */ + /* _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1; */ + + MOV w3, #1 // Build lock value + STR w3, [x2, #0] // Store lock value + DMB ISH // + + /* Got the lock. */ + /* _tx_thread_smp_protect_lock_got(); */ + + _tx_thread_smp_protect_lock_got + + /* Remove this core from the wait list. */ + /* _tx_thread_smp_protect_remove_from_front_of_list(); */ + + _tx_thread_smp_protect_remove_from_front_of_list + + B _got_lock_after_waiting + +_did_not_get_lock: + + /* For one reason or another, we didn't get the lock. */ + + /* Were we removed from the list? This can happen if we're a thread + and we got preempted. */ + /* if (_tx_thread_smp_protect_wait_counts[this_core] == 0) + { */ + + LDR x3, =_tx_thread_smp_protect_wait_counts // Load wait list counts + LDR w4, [x3, x1, LSL #2] // Load waiting value for this core + CMP w4, #0 + BNE _already_in_list1 // Is this core already in the list? + + /* Add ourselves to the list. */ + /* _tx_thread_smp_protect_wait_list_add(this_core); */ + + _tx_thread_smp_protect_wait_list_add // Call macro to add ourselves to the list + + /* Our waiting count was also reset when we were preempted. Increment it again. */ + /* _tx_thread_smp_protect_wait_counts[this_core]++; */ + + LDR x3, =_tx_thread_smp_protect_wait_counts // Load wait list counts + LDR w4, [x3, x1, LSL #2] // Load waiting value for this core + ADD w4, w4, #1 // Increment wait value + STR w4, [x3, x1, LSL #2] // Store new wait value value + + /* } */ + +_already_in_list1: + + /* Restore interrupts and try again. */ + + MSR DAIF, x0 // Restore interrupts + ISB // +#ifdef TX_ENABLE_WFE + WFE // Go into standby +#endif + B _try_to_get_lock // On waking, restart the protection attempt + +_got_lock_after_waiting: + + /* We're no longer waiting. */ + /* _tx_thread_smp_protect_wait_counts[this_core]--; */ + + LDR x3, =_tx_thread_smp_protect_wait_counts // Load waiting list + LDR w4, [x3, x1, LSL #2] // Load current wait value + SUB w4, w4, #1 // Decrement wait value + STR w4, [x3, x1, LSL #2] // Store new wait value value + + /* Restore registers and return. */ + +_return: + + RET + diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h new file mode 100644 index 00000000..5c33d940 --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h @@ -0,0 +1,296 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .macro _tx_thread_smp_protect_lock_got + + /* Set the currently owned core. */ + /* _tx_thread_smp_protection.tx_thread_smp_protect_core = this_core; */ + + STR w1, [x2, #4] // Store this core + + /* Increment the protection count. */ + /* _tx_thread_smp_protection.tx_thread_smp_protect_count++; */ + + LDR w3, [x2, #8] // Pickup ownership count + ADD w3, w3, #1 // Increment ownership count + STR w3, [x2, #8] // Store ownership count + DMB ISH + + .endm + + .macro _tx_thread_smp_protect_remove_from_front_of_list + + /* Remove ourselves from the list. */ + /* _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head++] = 0xFFFFFFFF; */ + + MOV w3, #0xFFFFFFFF // Build the invalid core value + LDR x4, =_tx_thread_smp_protect_wait_list_head // Get the address of the head + LDR w5, [x4] // Get the value of the head + LDR x6, =_tx_thread_smp_protect_wait_list // Get the address of the list + STR w3, [x6, x5, LSL #2] // Store the invalid core value + ADD w5, w5, #1 // Increment the head + + /* Did we wrap? */ + /* if (_tx_thread_smp_protect_wait_list_head == TX_THREAD_SMP_MAX_CORES + 1) + { */ + + LDR x3, =_tx_thread_smp_protect_wait_list_size // Load address of core list size + LDR w3, [x3] // Load the max cores value + CMP w5, w3 // Compare the head to it + BNE _store_new_head\@ // Are we at the max? + + /* _tx_thread_smp_protect_wait_list_head = 0; */ + + EOR w5, w5, w5 // We're at the max. Set it to zero + + /* } */ + +_store_new_head\@: + + STR w5, [x4] // Store the new head + + /* We have the lock! */ + /* return; */ + + .endm + + + .macro _tx_thread_smp_protect_wait_list_lock_get +/* VOID _tx_thread_smp_protect_wait_list_lock_get() +{ */ + /* We do this until we have the lock. */ + /* while (1) + { */ + +_tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@: + + /* Is the list lock available? */ + /* _tx_thread_smp_protect_wait_list_lock_protect_in_force = load_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force); */ + + LDR x1, =_tx_thread_smp_protect_wait_list_lock_protect_in_force + LDAXR w2, [x1] // Pickup the protection flag + + /* if (protect_in_force == 0) + { */ + + CMP w2, #0 + BNE _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@ // No, protection not available + + /* Try to get the list. */ + /* int status = store_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force, 1); */ + + MOV w2, #1 // Build lock value + STXR w3, w2, [x1] // Attempt to get the protection + + /* if (status == SUCCESS) */ + + CMP w3, #0 + BNE _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@ // Did it fail? If so, try again. + + /* We have the lock! */ + /* return; */ + + .endm + + + .macro _tx_thread_smp_protect_wait_list_add +/* VOID _tx_thread_smp_protect_wait_list_add(UINT new_core) +{ */ + + /* We're about to modify the list, so get the list lock. */ + /* _tx_thread_smp_protect_wait_list_lock_get(); */ + + STP x1, x2, [sp, #-16]! // Save registers we'll be using + + _tx_thread_smp_protect_wait_list_lock_get + + LDP x1, x2, [sp], #16 + + /* Add this core. */ + /* _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_tail++] = new_core; */ + + LDR x3, =_tx_thread_smp_protect_wait_list_tail // Get the address of the tail + LDR w4, [x3] // Get the value of tail + LDR x5, =_tx_thread_smp_protect_wait_list // Get the address of the list + STR w1, [x5, x4, LSL #2] // Store the new core value + ADD w4, w4, #1 // Increment the tail + + /* Did we wrap? */ + /* if (_tx_thread_smp_protect_wait_list_tail == _tx_thread_smp_protect_wait_list_size) + { */ + + LDR x5, =_tx_thread_smp_protect_wait_list_size // Load max cores address + LDR w5, [x5] // Load max cores value + CMP w4, w5 // Compare max cores to tail + BNE _tx_thread_smp_protect_wait_list_add__no_wrap\@ // Did we wrap? + + /* _tx_thread_smp_protect_wait_list_tail = 0; */ + + MOV w4, #0 + + /* } */ + +_tx_thread_smp_protect_wait_list_add__no_wrap\@: + + STR w4, [x3] // Store the new tail value. + + /* Release the list lock. */ + /* _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; */ + + MOV w3, #0 // Build lock value + LDR x4, =_tx_thread_smp_protect_wait_list_lock_protect_in_force + STR w3, [x4] // Store the new value + + .endm + + + .macro _tx_thread_smp_protect_wait_list_remove +/* VOID _tx_thread_smp_protect_wait_list_remove(UINT core) +{ */ + + /* Get the core index. */ + /* UINT core_index; + for (core_index = 0;; core_index++) */ + + EOR w4, w4, w4 // Clear for 'core_index' + LDR x2, =_tx_thread_smp_protect_wait_list // Get the address of the list + + /* { */ + +_tx_thread_smp_protect_wait_list_remove__check_cur_core\@: + + /* Is this the core? */ + /* if (_tx_thread_smp_protect_wait_list[core_index] == core) + { + break; */ + + LDR w3, [x2, x4, LSL #2] // Get the value at the current index + CMP w3, w8 // Did we find the core? + BEQ _tx_thread_smp_protect_wait_list_remove__found_core\@ + + /* } */ + + ADD w4, w4, #1 // Increment cur index + B _tx_thread_smp_protect_wait_list_remove__check_cur_core\@ // Restart the loop + + /* } */ + +_tx_thread_smp_protect_wait_list_remove__found_core\@: + + /* We're about to modify the list. Get the lock. We need the lock because another + core could be simultaneously adding (a core is simultaneously trying to get + the inter-core lock) or removing (a core is simultaneously being preempted, + like what is currently happening). */ + /* _tx_thread_smp_protect_wait_list_lock_get(); */ + + MOV x6, x1 + _tx_thread_smp_protect_wait_list_lock_get + MOV x1, x6 + + /* We remove by shifting. */ + /* while (core_index != _tx_thread_smp_protect_wait_list_tail) + { */ + +_tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@: + + LDR x2, =_tx_thread_smp_protect_wait_list_tail // Load tail address + LDR w2, [x2] // Load tail value + CMP w4, w2 // Compare cur index and tail + BEQ _tx_thread_smp_protect_wait_list_remove__removed\@ + + /* UINT next_index = core_index + 1; */ + + MOV w2, w4 // Move current index to next index register + ADD w2, w2, #1 // Add 1 + + /* if (next_index == _tx_thread_smp_protect_wait_list_size) + { */ + + LDR x3, =_tx_thread_smp_protect_wait_list_size + LDR w3, [x3] + CMP w2, w3 + BNE _tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@ + + /* next_index = 0; */ + + MOV w2, #0 + + /* } */ + +_tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@: + + /* list_cores[core_index] = list_cores[next_index]; */ + + LDR x5, =_tx_thread_smp_protect_wait_list // Get the address of the list + LDR w3, [x5, x2, LSL #2] // Get the value at the next index + STR w3, [x5, x4, LSL #2] // Store the value at the current index + + /* core_index = next_index; */ + + MOV w4, w2 + + B _tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@ + + /* } */ + +_tx_thread_smp_protect_wait_list_remove__removed\@: + + /* Now update the tail. */ + /* if (_tx_thread_smp_protect_wait_list_tail == 0) + { */ + + LDR x5, =_tx_thread_smp_protect_wait_list_tail // Load tail address + LDR w4, [x5] // Load tail value + CMP w4, #0 + BNE _tx_thread_smp_protect_wait_list_remove__tail_not_zero\@ + + /* _tx_thread_smp_protect_wait_list_tail = _tx_thread_smp_protect_wait_list_size; */ + + LDR x2, =_tx_thread_smp_protect_wait_list_size + LDR w4, [x2] + + /* } */ + +_tx_thread_smp_protect_wait_list_remove__tail_not_zero\@: + + /* _tx_thread_smp_protect_wait_list_tail--; */ + + SUB w4, w4, #1 + STR w4, [x5] // Store new tail value + + /* Release the list lock. */ + /* _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; */ + + MOV w2, #0 // Build lock value + LDR x4, =_tx_thread_smp_protect_wait_list_lock_protect_in_force // Load lock address + STR w2, [x4] // Store the new value + + /* We're no longer waiting. Note that this should be zero since, again, + this function is only called when a thread preemption is occurring. */ + /* _tx_thread_smp_protect_wait_counts[core]--; */ + LDR x4, =_tx_thread_smp_protect_wait_counts // Load wait list counts + LDR w2, [x4, x8, LSL #2] // Load waiting value + SUB w2, w2, #1 // Subtract 1 + STR w2, [x4, x8, LSL #2] // Store new waiting value + + .endm + diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_time_get.S new file mode 100644 index 00000000..d0141dd2 --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_time_get.S @@ -0,0 +1,83 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_time_get Cortex-A35-SMP/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets the global time value that is used for debug */ +/* information and event tracing. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* 32-bit time stamp */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Source */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_time_get + .type _tx_thread_smp_time_get, @function +_tx_thread_smp_time_get: + MOV x0, #0 // FIXME: Get timer + RET + + diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_unprotect.S new file mode 100644 index 00000000..e70b62e6 --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_unprotect.S @@ -0,0 +1,130 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_unprotect Cortex-A35-SMP/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function releases previously obtained protection. The supplied */ +/* previous SR is restored. If the value of _tx_thread_system_state */ +/* and _tx_thread_preempt_disable are both zero, then multithreading */ +/* is enabled as well. */ +/* */ +/* INPUT */ +/* */ +/* Previous Status Register */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Source */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_unprotect + .type _tx_thread_smp_unprotect, @function +_tx_thread_smp_unprotect: + MSR DAIFSet, 0x3 // Lockout interrupts + + MRS x1, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x2, x1, #8, #8 // Isolate cluster ID +#endif + UBFX x1, x1, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x1, x1, x2, LSL #2 // Calculate CPU ID +#endif + + LDR x2,=_tx_thread_smp_protection // Build address of protection structure + LDR w3, [x2, #4] // Pickup the owning core + CMP w1, w3 // Is it this core? + BNE _still_protected // If this is not the owning core, protection is in force elsewhere + + LDR w3, [x2, #8] // Pickup the protection count + CMP w3, #0 // Check to see if the protection is still active + BEQ _still_protected // If the protection count is zero, protection has already been cleared + + SUB w3, w3, #1 // Decrement the protection count + STR w3, [x2, #8] // Store the new count back + CMP w3, #0 // Check to see if the protection is still active + BNE _still_protected // If the protection count is non-zero, protection is still in force + LDR x2,=_tx_thread_preempt_disable // Build address of preempt disable flag + LDR w3, [x2] // Pickup preempt disable flag + CMP w3, #0 // Is the preempt disable flag set? + BNE _still_protected // Yes, skip the protection release + + LDR x2,=_tx_thread_smp_protect_wait_counts // Build build address of wait counts + LDR w3, [x2, x1, LSL #2] // Pickup wait list value + CMP w3, #0 // Are any entities on this core waiting? + BNE _still_protected // Yes, skip the protection release + + LDR x2,=_tx_thread_smp_protection // Build address of protection structure + MOV w3, #0xFFFFFFFF // Build invalid value + STR w3, [x2, #4] // Mark the protected core as invalid + DMB ISH // Ensure that accesses to shared resource have completed + MOV w3, #0 // Build release protection value + STR w3, [x2, #0] // Release the protection + DSB ISH // To ensure update of the protection occurs before other CPUs awake + +_still_protected: +#ifdef TX_ENABLE_WFE + SEV // Send event to other CPUs, wakes anyone waiting on the protection (using WFE) +#endif + MSR DAIF, x0 // Restore interrupt posture + RET + diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_stack_build.S b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_stack_build.S new file mode 100644 index 00000000..5e485c1e --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_stack_build.S @@ -0,0 +1,172 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build Cortex-A35-SMP/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +{ */ + .global _tx_thread_stack_build + .type _tx_thread_stack_build, @function +_tx_thread_stack_build: + + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-A35 should look like the following after it is built: + + Stack Top: SSPR Initial SSPR + ELR Point of interrupt + x28 Initial value for x28 + not used Not used + x26 Initial value for x26 + x27 Initial value for x27 + x24 Initial value for x24 + x25 Initial value for x25 + x22 Initial value for x22 + x23 Initial value for x23 + x20 Initial value for x20 + x21 Initial value for x21 + x18 Initial value for x18 + x19 Initial value for x19 + x16 Initial value for x16 + x17 Initial value for x17 + x14 Initial value for x14 + x15 Initial value for x15 + x12 Initial value for x12 + x13 Initial value for x13 + x10 Initial value for x10 + x11 Initial value for x11 + x8 Initial value for x8 + x9 Initial value for x9 + x6 Initial value for x6 + x7 Initial value for x7 + x4 Initial value for x4 + x5 Initial value for x5 + x2 Initial value for x2 + x3 Initial value for x3 + x0 Initial value for x0 + x1 Initial value for x1 + x29 Initial value for x29 (frame pointer) + x30 Initial value for x30 (link register) + 0 For stack backtracing + + Stack Bottom: (higher memory address) */ + + LDR x4, [x0, #24] // Pickup end of stack area + BIC x4, x4, #0xF // Ensure 16-byte alignment + + /* Actually build the stack frame. */ + + MOV x2, #0 // Build clear value + MOV x3, #0 // + + STP x2, x3, [x4, #-16]! // Set backtrace to 0 + STP x2, x3, [x4, #-16]! // Set initial x29, x30 + STP x2, x3, [x4, #-16]! // Set initial x0, x1 + STP x2, x3, [x4, #-16]! // Set initial x2, x3 + STP x2, x3, [x4, #-16]! // Set initial x4, x5 + STP x2, x3, [x4, #-16]! // Set initial x6, x7 + STP x2, x3, [x4, #-16]! // Set initial x8, x9 + STP x2, x3, [x4, #-16]! // Set initial x10, x11 + STP x2, x3, [x4, #-16]! // Set initial x12, x13 + STP x2, x3, [x4, #-16]! // Set initial x14, x15 + STP x2, x3, [x4, #-16]! // Set initial x16, x17 + STP x2, x3, [x4, #-16]! // Set initial x18, x19 + STP x2, x3, [x4, #-16]! // Set initial x20, x21 + STP x2, x3, [x4, #-16]! // Set initial x22, x23 + STP x2, x3, [x4, #-16]! // Set initial x24, x25 + STP x2, x3, [x4, #-16]! // Set initial x26, x27 + STP x2, x3, [x4, #-16]! // Set initial x28 +#ifdef EL1 + MOV x2, #0x4 // Build initial SPSR (EL1) +#else +#ifdef EL2 + MOV x2, #0x8 // Build initial SPSR (EL2) +#else + MOV x2, #0xC // Build initial SPSR (EL3) +#endif +#endif + MOV x3, x1 // Build initial ELR + STP x2, x3, [x4, #-16]! // Set initial SPSR & ELR + + /* Setup stack pointer. */ + /* thread_ptr -> tx_thread_stack_ptr = x2; */ + + STR x4, [x0, #8] // Save stack pointer in thread's + MOV x3, #1 // Build ready flag + STR w3, [x0, #260] // Set ready flag + RET // Return to caller + +/* } */ + + diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_system_return.S new file mode 100644 index 00000000..7a68ef64 --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_system_return.S @@ -0,0 +1,191 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return Cortex-A35-SMP/ARM */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the ThreadX system. Only a */ +/* minimal context is saved since the compiler assumes temp registers */ +/* are going to get slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_system_return(VOID) +{ */ + .global _tx_thread_system_return + .type _tx_thread_system_return, @function +_tx_thread_system_return: +; +; /* Save minimal context on the stack. */ +; + MRS x0, DAIF // Pickup DAIF + MSR DAIFSet, 0x3 // Lockout interrupts + STP x29, x30, [sp, #-16]! // Save x29 (frame pointer), x30 (link register) + STP x19, x20, [sp, #-16]! // Save x19, x20 + STP x21, x22, [sp, #-16]! // Save x21, x22 + STP x23, x24, [sp, #-16]! // Save x23, x24 + STP x25, x26, [sp, #-16]! // Save x25, x26 + STP x27, x28, [sp, #-16]! // Save x27, x28 + MRS x8, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x3, x8, #8, #8 // Isolate cluster ID +#endif + UBFX x8, x8, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x8, x8, x3, LSL #2 // Calculate CPU ID +#endif + LDR x5, =_tx_thread_current_ptr // Pickup address of current ptr + LDR x6, [x5, x8, LSL #3] // Pickup current thread pointer + +#ifdef ENABLE_ARM_FP + LDR w7, [x6, #268] // Pickup FP enable flag + CMP w7, #0 // Is FP enabled? + BEQ _skip_fp_save // No, skip FP save + STP q8, q9, [sp, #-32]! // Save q8, q9 + STP q10, q11, [sp, #-32]! // Save q10, q11 + STP q12, q13, [sp, #-32]! // Save q12, q13 + STP q14, q15, [sp, #-32]! // Save q14, q15 + MRS x2, FPSR // Pickup FPSR + MRS x3, FPCR // Pickup FPCR + STP x2, x3, [sp, #-16]! // Save FPSR, FPCR +_skip_fp_save: +#endif + + MOV x1, #0 // Clear x1 + STP x0, x1, [sp, #-16]! // Save DAIF and clear value for ELR_EK1 + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread exit function to indicate the thread is no longer executing. */ + + MOV x19, x5 // Save x5 + MOV x20, x6 // Save x6 + MOV x21, x8 // Save x2 + BL _tx_execution_thread_exit // Call the thread exit function + MOV x8, x21 // Restore x2 + MOV x5, x19 // Restore x5 + MOV x6, x20 // Restore x6 +#endif + + LDR x2, =_tx_timer_time_slice // Pickup address of time slice + LDR w1, [x2, x8, LSL #2] // Pickup current time slice + + /* Save current stack and switch to system stack. */ + /* _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; */ + /* sp = _tx_thread_system_stack_ptr[core]; */ + + MOV x4, sp // + STR x4, [x6, #8] // Save thread stack pointer + LDR x3, =_tx_thread_system_stack_ptr // Pickup address of system stack + LDR x4, [x3, x8, LSL #3] // Pickup system stack pointer + MOV sp, x4 // Setup system stack pointer + + /* Determine if the time-slice is active. */ + /* if (_tx_timer_time_slice[core]) + { */ + + MOV x4, #0 // Build clear value + CMP w1, #0 // Is a time-slice active? + BEQ __tx_thread_dont_save_ts // No, don't save the time-slice + + /* Save the current remaining time-slice. */ + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + STR w4, [x2, x8, LSL #2] // Clear time-slice + STR w1, [x6, #36] // Store current time-slice + + /* } */ +__tx_thread_dont_save_ts: + + /* Clear the current thread pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + STR x4, [x5, x8, LSL #3] // Clear current thread pointer + + /* Set ready bit in thread control block. */ + + MOV x3, #1 // Build ready value + STR w3, [x6, #260] // Make the thread ready + DMB ISH // + + /* Now clear protection. It is assumed that protection is in force whenever this routine is called. */ + + LDR x3, =_tx_thread_smp_protection // Pickup address of protection structure + LDR x1, =_tx_thread_preempt_disable // Build address to preempt disable flag + STR w4, [x1, #0] // Clear preempt disable flag + STR w4, [x3, #8] // Cear protection count + MOV x1, #0xFFFFFFFF // Build invalid value + STR w1, [x3, #4] // Set core to an invalid value + DMB ISH // Ensure that accesses to shared resource have completed + STR w4, [x3, #0] // Clear protection + DSB ISH // To ensure update of the shared resource occurs before other CPUs awake + SEV // Send event to other CPUs, wakes anyone waiting on a mutex (using WFE) + B _tx_thread_schedule // Jump to scheduler! + +/* } */ + + diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_thread_timeout.c b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_timeout.c new file mode 100644 index 00000000..ad448f8c --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_thread_timeout.c @@ -0,0 +1,165 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_timeout Cortex-A35-SMP */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles thread timeout processing. Timeouts occur in */ +/* two flavors, namely the thread sleep timeout and all other service */ +/* call timeouts. Thread sleep timeouts are processed locally, while */ +/* the others are processed by the appropriate suspension clean-up */ +/* service. */ +/* */ +/* INPUT */ +/* */ +/* timeout_input Contains the thread pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* Suspension Cleanup Functions */ +/* _tx_thread_system_resume Resume thread */ +/* _tx_thread_system_ni_resume Non-interruptable resume thread */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_timer_expiration_process Timer expiration function */ +/* _tx_timer_thread_entry Timer thread function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_timeout(ULONG timeout_input) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_THREAD *thread_ptr; +VOID (*suspend_cleanup)(struct TX_THREAD_STRUCT *suspend_thread_ptr, ULONG suspension_sequence); +ULONG suspension_sequence; + + + /* Pickup the thread pointer. */ + TX_THREAD_TIMEOUT_POINTER_SETUP(thread_ptr) + + /* Disable interrupts. */ + TX_DISABLE + + /* Determine how the thread is currently suspended. */ + if (thread_ptr -> tx_thread_state == TX_SLEEP) + { + +#ifdef TX_NOT_INTERRUPTABLE + + /* Resume the thread! */ + _tx_thread_system_ni_resume(thread_ptr); + + /* Restore interrupts. */ + TX_RESTORE +#else + + /* Increment the disable preemption flag. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Lift the suspension on the sleeping thread. */ + _tx_thread_system_resume(thread_ptr); +#endif + } + else + { + + /* Process all other suspension timeouts. */ + +#ifdef TX_THREAD_ENABLE_PERFORMANCE_INFO + + /* Increment the total number of thread timeouts. */ + _tx_thread_performance_timeout_count++; + + /* Increment the number of timeouts for this thread. */ + thread_ptr -> tx_thread_performance_timeout_count++; +#endif + + /* Pickup the cleanup routine address. */ + suspend_cleanup = thread_ptr -> tx_thread_suspend_cleanup; + +#ifndef TX_NOT_INTERRUPTABLE + + /* Pickup the suspension sequence number that is used later to verify that the + cleanup is still necessary. */ + suspension_sequence = thread_ptr -> tx_thread_suspension_sequence; +#else + + /* When not interruptable is selected, the suspension sequence is not used - just set to 0. */ + suspension_sequence = ((ULONG) 0); +#endif + +#ifndef TX_NOT_INTERRUPTABLE + + /* Restore interrupts. */ + TX_RESTORE +#endif + + /* Call any cleanup routines. */ + if (suspend_cleanup != TX_NULL) + { + + /* Yes, there is a function to call. */ + (suspend_cleanup)(thread_ptr, suspension_sequence); + } + +#ifdef TX_NOT_INTERRUPTABLE + + /* Restore interrupts. */ + TX_RESTORE +#endif + } +} + diff --git a/ports_smp/cortex_a35_smp/gnu/src/tx_timer_interrupt.S b/ports_smp/cortex_a35_smp/gnu/src/tx_timer_interrupt.S new file mode 100644 index 00000000..57c27433 --- /dev/null +++ b/ports_smp/cortex_a35_smp/gnu/src/tx_timer_interrupt.S @@ -0,0 +1,198 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_timer.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt Cortex-A35-SMP/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_timer_interrupt(VOID) +{ */ + .global _tx_timer_interrupt + .type _tx_timer_interrupt, @function +_tx_timer_interrupt: + + MRS x2, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x3, x2, #8, #8 // Isolate cluster ID +#endif + UBFX x2, x2, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x2, x2, x3, LSL #2 // Calculate CPU ID +#endif + CMP x2, #0 // Is this core 0? + BEQ __tx_process_timer // If desired core, continue processing + RET // Simply return if different core +__tx_process_timer: + + /* Upon entry to this routine, it is assumed that context save has already + been called, and therefore the compiler scratch registers are available + for use. */ + + STP x27, x28, [sp, #-16]! // Save x27, x28 + STP x29, x30, [sp, #-16]! // Save x29 (frame pointer), x30 (link register) + + /* Get inter-core protection. */ + + BL _tx_thread_smp_protect // Get inter-core protection + MOV x28, x0 // Save the return value in preserved register + + /* Increment the system clock. */ + /* _tx_timer_system_clock++; */ + + LDR x1, =_tx_timer_system_clock // Pickup address of system clock + LDR w0, [x1, #0] // Pickup system clock + ADD w0, w0, #1 // Increment system clock + STR w0, [x1, #0] // Store new system clock + + /* Test for timer expiration. */ + /* if (*_tx_timer_current_ptr) + { */ + + LDR x1, =_tx_timer_current_ptr // Pickup current timer pointer addr + LDR x0, [x1, #0] // Pickup current timer + LDR x2, [x0, #0] // Pickup timer list entry + CMP x2, #0 // Is there anything in the list? + BEQ __tx_timer_no_timer // No, just increment the timer + + /* Set expiration flag. */ + /* _tx_timer_expired = TX_TRUE; */ + + LDR x3, =_tx_timer_expired // Pickup expiration flag address + MOV w2, #1 // Build expired value + STR w2, [x3, #0] // Set expired flag + B __tx_timer_done // Finished timer processing + + /* } + else + { */ +__tx_timer_no_timer: + + /* No timer expired, increment the timer pointer. */ + /* _tx_timer_current_ptr++; */ + + ADD x0, x0, #8 // Move to next timer + + /* Check for wrap-around. */ + /* if (_tx_timer_current_ptr == _tx_timer_list_end) */ + + LDR x3, =_tx_timer_list_end // Pickup addr of timer list end + LDR x2, [x3, #0] // Pickup list end + CMP x0, x2 // Are we at list end? + BNE __tx_timer_skip_wrap // No, skip wrap-around logic + + /* Wrap to beginning of list. */ + /* _tx_timer_current_ptr = _tx_timer_list_start; */ + + LDR x3, =_tx_timer_list_start // Pickup addr of timer list start + LDR x0, [x3, #0] // Set current pointer to list start + +__tx_timer_skip_wrap: + + STR x0, [x1, #0] // Store new current timer pointer + /* } */ + +__tx_timer_done: + + /* Did a timer expire? */ + /* if (_tx_timer_expired) + { */ + + LDR x1, =_tx_timer_expired // Pickup addr of expired flag + LDR w0, [x1, #0] // Pickup timer expired flag + CMP w0, #0 // Check for timer expiration + BEQ __tx_timer_dont_activate // If not set, skip timer activation + + /* Process timer expiration. */ + /* _tx_timer_expiration_process(); */ + + BL _tx_timer_expiration_process // Call the timer expiration handling routine + + /* } */ +__tx_timer_dont_activate: + + /* Call time-slice processing. */ + /* _tx_thread_time_slice(); */ + BL _tx_thread_time_slice // Call time-slice processing + + /* Release inter-core protection. */ + + MOV x0, x28 // Pass the previous status register back + BL _tx_thread_smp_unprotect // Release protection + + LDP x29, x30, [sp], #16 // Recover x29, x30 + LDP x27, x28, [sp], #16 // Recover x27, x28 + RET // Return to caller + +/* } */ + + diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/tx_initialize_low_level.s b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/tx_initialize_low_level.s index 36059fcc..1cdcaa64 100644 --- a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/tx_initialize_low_level.s +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/tx_initialize_low_level.s @@ -47,7 +47,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level SMP/Cortex-A5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -80,7 +80,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports_smp/cortex_a5_smp/ac5/inc/tx_port.h b/ports_smp/cortex_a5_smp/ac5/inc/tx_port.h index bcc092a5..d3881298 100644 --- a/ports_smp/cortex_a5_smp/ac5/inc/tx_port.h +++ b/ports_smp/cortex_a5_smp/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h SMP/Cortex-A5/AC5 */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -394,7 +394,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Cortex-A5/AC5 Version 6.0.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Cortex-A5/AC5 Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a5_smp/ac5/readme_threadx.txt b/ports_smp/cortex_a5_smp/ac5/readme_threadx.txt index 49cd8d4a..91cb43f4 100644 --- a/ports_smp/cortex_a5_smp/ac5/readme_threadx.txt +++ b/ports_smp/cortex_a5_smp/ac5/readme_threadx.txt @@ -351,7 +351,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A5 using AC5 tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-A5 using AC5 tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_context_restore.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_context_restore.s index 46a8080b..e3985428 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_context_restore.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_context_restore.s @@ -69,7 +69,7 @@ SVC_MODE EQU 0x93 ; SVC mode ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore SMP/Cortex-A5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -101,7 +101,7 @@ SVC_MODE EQU 0x93 ; SVC mode ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_context_save.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_context_save.s index 384ea930..5ab27d29 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_context_save.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_context_save.s @@ -45,7 +45,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save SMP/Cortex-A5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -76,7 +76,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_interrupt_control.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_interrupt_control.s index 44060077..6981bcc9 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_interrupt_control.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_interrupt_control.s @@ -42,7 +42,7 @@ INT_MASK EQU 0x80 ; Interrupt bit mask ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control SMP/Cortex-A5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ INT_MASK EQU 0x80 ; Interrupt bit mask ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_interrupt_disable.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_interrupt_disable.s index 58fa2e03..6b1ec090 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_interrupt_disable.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_interrupt_disable.s @@ -35,7 +35,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_disable SMP/Cortex-A5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -64,7 +64,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(void) diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_interrupt_restore.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_interrupt_restore.s index b6a46df8..84408ce9 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_interrupt_restore.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_interrupt_restore.s @@ -35,7 +35,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore SMP/Cortex-A5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -65,7 +65,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_irq_nesting_end.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_irq_nesting_end.s index 973cab86..3031285a 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_irq_nesting_end.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_irq_nesting_end.s @@ -45,7 +45,7 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_irq_nesting_end SMP/Cortex-A5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -84,7 +84,7 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_irq_nesting_start.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_irq_nesting_start.s index e3459234..b32e4baf 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_irq_nesting_start.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_irq_nesting_start.s @@ -41,7 +41,7 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_irq_nesting_start SMP/Cortex-A5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_schedule.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_schedule.s index d71b3666..d86e6713 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_schedule.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_schedule.s @@ -46,7 +46,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule SMP/Cortex-A5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -79,7 +79,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_core_get.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_core_get.s index fb3b07a4..e8f5f6cb 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_core_get.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_core_get.s @@ -38,7 +38,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_smp_core_get SMP/Cortex-A5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -67,7 +67,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_core_get diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_core_preempt.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_core_preempt.s index f64941ec..bb767369 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_core_preempt.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_core_preempt.s @@ -40,7 +40,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_smp_core_preempt SMP/Cortex-A5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -73,7 +73,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_core_preempt diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_current_state_get.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_current_state_get.s index ae77e525..000e46c2 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_current_state_get.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_current_state_get.s @@ -40,7 +40,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_smp_current_state_get SMP/Cortex-A5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -69,7 +69,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_current_state_get diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_current_thread_get.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_current_thread_get.s index 00b197d9..118327a0 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_current_thread_get.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_current_thread_get.s @@ -40,7 +40,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_smp_current_thread_get SMP/Cortex-A5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -69,7 +69,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_current_thread_get diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_initialize_wait.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_initialize_wait.s index 67571ac4..7b3fd990 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_initialize_wait.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_initialize_wait.s @@ -43,7 +43,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_smp_initialize_wait SMP/Cortex-A5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -74,7 +74,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_initialize_wait diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_low_level_initialize.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_low_level_initialize.s index 0d712322..8e720077 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_low_level_initialize.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_low_level_initialize.s @@ -38,7 +38,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_smp_low_level_initialize SMP/Cortex-A5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -68,7 +68,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_low_level_initialize diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_protect.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_protect.s index 517981fc..6ae42350 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_protect.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_protect.s @@ -51,7 +51,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_smp_protect SMP/Cortex-A5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_protect diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_time_get.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_time_get.s index 9f7d7388..8b47acd5 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_time_get.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_time_get.s @@ -39,7 +39,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_smp_time_get SMP/Cortex-A5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -69,7 +69,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_time_get diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_unprotect.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_unprotect.s index 80b174de..8b9f61af 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_unprotect.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_unprotect.s @@ -43,7 +43,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_smp_unprotect SMP/Cortex-A5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -75,7 +75,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_unprotect diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_stack_build.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_stack_build.s index 215bc0fc..4f48395f 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_stack_build.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_stack_build.s @@ -47,7 +47,7 @@ THUMB_BIT EQU 0x20 ; Thumb-bit ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build SMP/Cortex-A5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -79,7 +79,7 @@ THUMB_BIT EQU 0x20 ; Thumb-bit ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_system_return.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_system_return.s index 83ff71d6..c2aee72c 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_system_return.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_system_return.s @@ -47,7 +47,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return SMP/Cortex-A5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -79,7 +79,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_vectored_context_save.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_vectored_context_save.s index 5ed05531..cc0e510a 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_vectored_context_save.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_vectored_context_save.s @@ -44,7 +44,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_vectored_context_save SMP/Cortex-A5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -75,7 +75,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_timer_interrupt.s b/ports_smp/cortex_a5_smp/ac5/src/tx_timer_interrupt.s index 6ef1ec67..e1b62b09 100644 --- a/ports_smp/cortex_a5_smp/ac5/src/tx_timer_interrupt.s +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_timer_interrupt.s @@ -55,7 +55,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt SMP/Cortex-A5/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -91,7 +91,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) diff --git a/ports_smp/cortex_a5_smp/gnu/example_build/MP_GIC.S b/ports_smp/cortex_a5_smp/gnu/example_build/MP_GIC.S new file mode 100644 index 00000000..2ff179fb --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/example_build/MP_GIC.S @@ -0,0 +1,516 @@ +// ------------------------------------------------------------ +// Cortex-A MPCore - Interrupt Controller functions +// +// Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + + + .text + .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + + +// ------------------------------------------------------------ +// GIC +// ------------------------------------------------------------ + + // CPU Interface offset from base of private peripheral space --> 0x0100 + // Interrupt Distributor offset from base of private peripheral space --> 0x1000 + + // Typical calls to enable interrupt ID X: + // disableIntID(X) <-- Disable that ID + // setIntPriority(X, 0) <-- Set the priority of X to 0 (the max priority) + // setPriorityMask(0x1F) <-- Set CPU's priority mask to 0x1F (the lowest priority) + // enableGIC() <-- Enable the GIC (global) + // enableGICProcessorInterface() <-- Enable the CPU interface (local to the CPU) + + + .global enableGIC + // void enableGIC(void) + // Global enable of the Interrupt Distributor + .type enableGIC, "function" + .cfi_startproc +enableGIC: + + // Get base address of private peripheral space + MRC p15, 4, r0, c15, c0, 0 // Read periph base address + ADD r0, r0, #0x1000 // Add the GIC offset + + LDR r1, [r0] // Read the GIC Enable Register (ICDDCR) + ORR r1, r1, #0x01 // Set bit 0, the enable bit + STR r1, [r0] // Write the GIC Enable Register (ICDDCR) + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global disableGIC + // void disableGIC(void) + // Global disable of the Interrupt Distributor + .type disableGIC, "function" + .cfi_startproc +disableGIC: + + // Get base address of private peripheral space + MRC p15, 4, r0, c15, c0, 0 // Read periph base address + ADD r0, r0, #0x1000 // Add the GIC offset + + LDR r1, [r0] // Read the GIC Enable Register (ICDDCR) + BIC r1, r1, #0x01 // Clear bit 0, the enable bit + STR r1, [r0] // Write the GIC Enable Register (ICDDCR) + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global enableIntID + // void enableIntID(uint32_t ID) + // Enables the interrupt source number ID + .type enableIntID, "function" + .cfi_startproc +enableIntID: + + // Get base address of private peripheral space + MOV r1, r0 // Back up passed in ID value + MRC p15, 4, r0, c15, c0, 0 // Read periph base address + + // Each interrupt source has an enable bit in the GIC. These + // are grouped into registers, with 32 sources per register + // First, we need to identify which 32-bit block the interrupt lives in + MOV r2, r1 // Make working copy of ID in r2 + MOV r2, r2, LSR #5 // LSR by 5 places, affective divide by 32 + // r2 now contains the 32-bit block this ID lives in + MOV r2, r2, LSL #2 // Now multiply by 4, to convert offset into an address offset (four bytes per reg) + + // Now work out which bit within the 32-bit block the ID is + AND r1, r1, #0x1F // Mask off to give offset within 32-bit block + MOV r3, #1 // Move enable value into r3 + MOV r3, r3, LSL r1 // Shift it left to position of ID + + ADD r2, r2, #0x1100 // Add the base offset of the Enable Set registers to the offset for the ID + STR r3, [r0, r2] // Store out (ICDISER) + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global disableIntID + // void disableIntID(uint32_t ID) + // Disables the interrupt source number ID + .type disableIntID, "function" + .cfi_startproc +disableIntID: + + // Get base address of private peripheral space + MOV r1, r0 // Back up passed in ID value + MRC p15, 4, r0, c15, c0, 0 // Read periph base address + + // First, we need to identify which 32-bit block the interrupt lives in + MOV r2, r1 // Make working copy of ID in r2 + MOV r2, r2, LSR #5 // LSR by 5 places, affective divide by 32 + // r2 now contains the 32-bit block this ID lives in + MOV r2, r2, LSL #2 // Now multiply by 4, to convert offset into an address offset (four bytes per reg) + + // Now work out which bit within the 32-bit block the ID is + AND r1, r1, #0x1F // Mask off to give offset within 32-bit block + MOV r3, #1 // Move enable value into r3 + MOV r3, r3, LSL r1 // Shift it left to position of ID in 32-bit block + + ADD r2, r2, #0x1180 // Add the base offset of the Enable Clear registers to the offset for the ID + STR r3, [r0, r2] // Store out (ICDICER) + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global setIntPriority + // void setIntPriority(uint32_t ID, uint32_t priority) + // Sets the priority of the specified ID + // r0 = ID + // r1 = priority + .type setIntPriority, "function" + .cfi_startproc +setIntPriority: + + // Get base address of private peripheral space + MOV r2, r0 // Back up passed in ID value + MRC p15, 4, r0, c15, c0, 0 // Read periph base address + + // r0 = base addr + // r1 = priority + // r2 = ID + + // Make sure that priority value is only 5 bits, and convert to expected format + AND r1, r1, #0x1F + MOV r1, r1, LSL #3 + + // Find which register this ID lives in + BIC r3, r2, #0x03 // Make a copy of the ID, clearing off the bottom two bits + // There are four IDs per reg, by clearing the bottom two bits we get an address offset + ADD r3, r3, #0x1400 // Now add the offset of the Priority Level registers from the base of the private peripheral space + ADD r0, r0, r3 // Now add in the base address of the private peripheral space, giving us the absolute address + + + // Now work out which ID in the register it is + AND r2, r2, #0x03 // Clear all but the bottom two bits, leaves which ID in the reg it is (which byte) + MOV r2, r2, LSL #3 // Multiply by 8, this gives a bit offset + + // Read -> Modify -> Write + MOV r12, #0xFF // 8 bit field mask + MOV r12, r12, LSL r2 // Move mask into correct bit position + MOV r1, r1, LSL r2 // Also, move passed in priority value into correct bit position + + + LDR r3, [r0] // Read current value of the Priority Level register + BIC r3, r3, r12 // Clear appropriate field + ORR r3, r3, r1 // Now OR in the priority value + STR r3, [r0] // And store it back again (ICDIPR) + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global getIntPriority + // uint32_t getIntPriority(void) + // Returns the priority of the specified ID + .type getIntPriority, "function" + .cfi_startproc +getIntPriority: + + // TBD + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global setIntTarget + // void setIntTarget(uint32_t ID, uint32_t target) + // Sets the target CPUs of the specified ID + .type setIntTarget, "function" + .cfi_startproc +setIntTarget: + + // Get base address of private peripheral space + MRC p15, 4, r2, c15, c0, 0 // Read periph base address + + // r0 = ID + // r1 = target + // r2 = base addr + + // Clear unused bits + AND r1, r1, #0xF + + // Find which register this ID lives in + BIC r3, r0, #0x03 // Make a copy of the ID, clearing the bottom 2 bits + // There are four IDs per reg, by clearing the bottom two bits we get an address offset + ADD r3, r3, #0x1800 // Now add the offset of the Target registers from the base of the private peripheral space + ADD r2, r2, r3 // Now add in the base address of the private peripheral space, giving us the absolute address + + // Now work out which ID in the register it is + AND r0, r0, #0x03 // Clear all but the bottom two bits, leaves which ID in the reg it is (which byte) + MOV r0, r0, LSL #3 // Multiply by 8, this gives a bit offset + + // Read -> Modify -> Write + MOV r12, #0xFF // 8 bit field mask + MOV r12, r12, LSL r0 // Move mask into correct bit position + MOV r1, r1, LSL r0 // Also, move passed in target value into correct bit position + + LDR r3, [r2] // Read current value of the Target register + BIC r3, r3, r12 // Clear appropriate field + ORR r3, r3, r1 // Now OR in the target value + STR r3, [r2] // And store it back again + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global getIntTarget + // uint32_t getIntTarget(uint32_t ID) + // Returns the target CPUs of the specified ID + .type getIntTarget, "function" + .cfi_startproc +getIntTarget: + + // TBD + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global enableGICProcessorInterface + // void enableGICProcessorInterface(void) + // Enables the processor interface + // Must be done on each core separately + .type enableGICProcessorInterface, "function" + .cfi_startproc +enableGICProcessorInterface: + + MRC p15, 4, r0, c15, c0, 0 // Read periph base address + + LDR r1, [r0, #0x100] // Read the Processor Interface Control register (ICCICR/ICPICR) + ORR r1, r1, #0x03 // Bit 0: Enables secure interrupts, Bit 1: Enables Non-Secure interrupts + BIC r1, r1, #0x08 // Bit 3: Ensure Group 0 interrupts are signalled using IRQ, not FIQ + STR r1, [r0, #0x100] // Write the Processor Interface Control register (ICCICR/ICPICR) + + BX lr + .cfi_endproc + + + +// ------------------------------------------------------------ + + .global disableGICProcessorInterface + // void disableGICProcessorInterface(void) + // Disables the processor interface + // Must be done on each core separately + .type disableGICProcessorInterface, "function" + .cfi_startproc +disableGICProcessorInterface: + + MRC p15, 4, r0, c15, c0, 0 // Read periph base address + + LDR r1, [r0, #0x100] // Read the Processor Interface Control register (ICCICR/ICPICR) + BIC r1, r1, #0x03 // Bit 0: Enables secure interrupts, Bit 1: Enables Non-Secure interrupts + STR r1, [r0, #0x100] // Write the Processor Interface Control register (ICCICR/ICPICR) + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global setPriorityMask + // void setPriorityMask(uint32_t priority) + // Sets the Priority mask register for the CPU run on + // The reset value masks ALL interrupts! + .type setPriorityMask, "function" + .cfi_startproc +setPriorityMask: + MRC p15, 4, r1, c15, c0, 0 // Read periph base address + + STR r0, [r1, #0x0104] // Write the Priority Mask register + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global setBinaryPoint + // void setBinaryPoint(uint32_t priority) + // Sets the Binary Point Register for the CPU run on + .type setBinaryPoint, "function" + .cfi_startproc +setBinaryPoint: + MRC p15, 4, r1, c15, c0, 0 // Read periph base address + + STR r0, [r1, #0x0108] // Write the Priority Mask register (ICCPMR/ICCIPMR) + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global readIntAck + // uint32_t readIntAck(void) + // Returns the value of the Interrupt Acknowledge Register + .type readIntAck, "function" + .cfi_startproc +readIntAck: + MRC p15, 4, r0, c15, c0, 0 // Read periph base address + LDR r0, [r0, #0x010C] // Read the Interrupt Acknowledge Register + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global writeEOI + // void writeEOI(uint32_t ID) + // Writes ID to the End Of Interrupt register + .type writeEOI, "function" + .cfi_startproc +writeEOI: + MRC p15, 4, r1, c15, c0, 0 // Read periph base address + + STR r0, [r1, #0x0110] // Write ID to the End of Interrupt register + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ +// SGI +// ------------------------------------------------------------ + + .global sendSGI + // void sendSGI(uint32_t ID, uint32_t target_list, uint32_t filter_list) + // Send a software generate interrupt + .type sendSGI, "function" + .cfi_startproc +sendSGI: + + AND r3, r0, #0x0F // Mask off unused bits of ID, and move to r3 + AND r1, r1, #0x0F // Mask off unused bits of target_filter + AND r2, r2, #0x0F // Mask off unused bits of filter_list + + ORR r3, r3, r1, LSL #16 // Combine ID and target_filter + ORR r3, r3, r2, LSL #24 // and now the filter list + + // Get the address of the GIC + MRC p15, 4, r0, c15, c0, 0 // Read periph base address + ADD r0, r0, #0x1F00 // Add offset of the sgi_trigger reg + + STR r3, [r0] // Write to the Software Generated Interrupt Register (ICDSGIR) + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ +// TrustZone +// ------------------------------------------------------------ + + .global enableSecureFIQs + // void enableSecureFIQs(void) + // Enables the sending of secure interrupts as FIQs + .type enableSecureFIQs, "function" + .cfi_startproc +enableSecureFIQs: + + MRC p15, 4, r0, c15, c0, 0 // Read periph base address + + LDR r1, [r0, #0x100] // Read the Processor Interface Control register + ORR r1, r1, #0x08 // Bit 3: Controls whether secure interrupts are signalled as IRQs or FIQs + STR r1, [r0, #0x100] // Write the Processor Interface Control register + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global disableSecureFIQs + // void disableSecureFIQs(void) + // Disables the sending of secure interrupts as FIQs + .type disableSecureFIQs, "function" + .cfi_startproc +disableSecureFIQs: + + MRC p15, 4, r0, c15, c0, 0 // Read periph base address + + LDR r1, [r0, #0x100] // Read the Processor Interface Control register + BIC r1, r1, #0x08 // Bit 3: Controls whether secure interrupts are signalled as IRQs or FIQs + STR r1, [r0, #0x100] // Write the Processor Interface Control register + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global makeIntSecure + // void makeIntSecure(uint32_t ID) + // Sets the specified ID as being Secure + // r0 - ID + .type makeIntSecure, "function" + .cfi_startproc +makeIntSecure: + + MRC p15, 4, r1, c15, c0, 0 // Read periph base address + + // Each interrupt source has a secutiy bit in the GIC. These + // are grouped into registers, with 32 sources per register + // First, we need to identify which 32-bit block the interrupt lives in + MOV r2, r0 // Make working copy of ID in r2 + MOV r2, r2, LSR #5 // LSR by 5 places, affective divide by 32 + // r2 now contains the 32-bit block this ID lives in + MOV r2, r2, LSL #2 // Now multiply by 4, to convert offset into an address offset (four bytes per reg) + + // Now work out which bit within the 32-bit block the ID is + AND r0, r0, #0x1F // Mask off to give offset within 32-bit block + MOV r3, #1 // Move enable value into r3 + MOV r3, r3, LSL r0 // Shift it left to position of ID + + ADD r2, r2, #0x1080 // Add the base offset of the Interrupt Configuration registers to the offset for the ID + + LDR r0, [r1, r2] // Read appropriate Interrupt Configuration + BIC r0, r0, r3 // Clear bit (0 = secure) + STR r0, [r1, r2] // Store out + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global makeIntNonSecure + // void makeIntNonSecure(uint32_t ID) + // Sets the specified ID as being non-secure + // r0 - ID + .type makeIntNonSecure, "function" + .cfi_startproc +makeIntNonSecure: + + MRC p15, 4, r1, c15, c0, 0 // Read periph base address + + // Each interrupt source has a secutiy bit in the GIC. These + // are grouped into registers, with 32 sources per register + // First, we need to identify which 32-bit block the interrupt lives in + MOV r2, r0 // Make working copy of ID in r2 + MOV r2, r2, LSR #5 // LSR by 5 places, affective divide by 32 + // r2 now contains the 32-bit block this ID lives in + MOV r2, r2, LSL #2 // Now multiply by 4, to convert offset into an address offset (four bytes per reg) + + // Now work out which bit within the 32-bit block the ID is + AND r0, r0, #0x1F // Mask off to give offset within 32-bit block + MOV r3, #1 // Move enable value into r3 + MOV r3, r3, LSL r0 // Shift it left to position of ID + + ADD r2, r2, #0x1080 // Add the base offset of the Interrupt Configuration registers to the offset for the ID + + LDR r0, [r1, r2] // Read appropriate Interrupt Configuration + ORR r0, r0, r3 // Set bit (1 = secure) + STR r0, [r1, r2] // Store out + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global getIntSecurity + // uint32_t getIntSecurity(uint32_t ID, uint32_t security) + // Returns the security of the specified ID + .type getIntSecurity, "function" + .cfi_startproc +getIntSecurity: + + // TBD + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ +// End of MP_GIC.s +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a5_smp/gnu/example_build/MP_GIC.h b/ports_smp/cortex_a5_smp/gnu/example_build/MP_GIC.h new file mode 100644 index 00000000..1d047611 --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/example_build/MP_GIC.h @@ -0,0 +1,120 @@ +// ------------------------------------------------------------ +// Cortex-A MPCore - Interrupt Controller functions +// Header File +// +// Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#ifndef _CORTEXA_GIC_H +#define _CORTEXA_GIC_H + +#define SPURIOUS (255) + +// PPI IDs: +#define MPCORE_PPI_PRIVATE_TIMER (29) +#define MPCORE_PPI_PRIVATE_WD (30) +#define MPCORE_PPI_GLOBAL_TIMER (27) +#define MPCORE_PPI_LEGACY_IRQ (31) +#define MPCORE_PPI_LEGACY_FIQ (28) + +// ------------------------------------------------------------ +// GIC +// ------------------------------------------------------------ + +// Typical calls to enable interrupt ID X: +// enableIntID(X) <-- Enable that ID +// setIntPriority(X, 0) <-- Set the priority of X to 0 (the max priority) +// setPriorityMask(0x1F) <-- Set Core's priority mask to 0x1F (the lowest priority) +// enableGIC() <-- Enable the GIC (global) +// enableGICProcessorInterface() <-- Enable the CPU interface (local to the core) +// + + +// Global enable of the Interrupt Distributor +void enableGIC(void); + +// Global disable of the Interrupt Distributor +void disableGIC(void); + +// Enables the interrupt source number ID +void enableIntID(unsigned int ID); + +// Disables the interrupt source number ID +void disableIntID(unsigned int ID); + +// Enables the processor interface +// Must be done on each core separately +void enableGICProcessorInterface(void); + +// Disables the processor interface +// Must be done on each core separately +void disableGICProcessorInterface(void); + +// Sets the Priority mask register for the core run on +// The reset value masks ALL interrupts! +// +// NOTE: Bits 2:0 of this register are SBZ, the function does perform any shifting! +void setPriorityMask(unsigned int priority); + +// Sets the Binary Point Register for the core run on +void setBinaryPoint(unsigned int priority); + +// Sets the priority of the specified ID +void setIntPriority(unsigned int ID, unsigned int priority); + +// Returns the priority of the specified ID +unsigned int getIntPriority(unsigned int ID, unsigned int priority); + +#define MPCORE_IC_TARGET_NONE (0x0) +#define MPCORE_IC_TARGET_CPU0 (0x1) +#define MPCORE_IC_TARGET_CPU1 (0x2) +#define MPCORE_IC_TARGET_CPU2 (0x4) +#define MPCORE_IC_TARGET_CPU3 (0x8) + +// Sets the target CPUs of the specified ID +// For 'target' use one of the above defines +void setIntTarget(unsigned int ID, unsigned int target); + +// Returns the target CPUs of the specified ID +unsigned int getIntTarget(unsigned int ID); + +// Returns the value of the Interrupt Acknowledge Register +unsigned int readIntAck(void); + +// Writes ID to the End Of Interrupt register +void writeEOI(unsigned int ID); + +// ------------------------------------------------------------ +// SGI +// ------------------------------------------------------------ + +// Send a software generate interrupt +void sendSGI(unsigned int ID, unsigned int core_list, unsigned int filter_list); + +// ------------------------------------------------------------ +// TrustZone +// ------------------------------------------------------------ + +// Enables the sending of secure interrupts as FIQs +void enableSecureFIQs(void); + +// Disables the sending of secure interrupts as FIQs +void disableSecureFIQs(void); + +// Sets the specified ID as secure +void makeIntSecure(unsigned int ID); + +// Set the specified ID as non-secure +void makeIntNonSecure(unsigned int ID); + +// Returns the security of the specified ID +unsigned int getIntSecurity(unsigned int ID); + +#endif + +// ------------------------------------------------------------ +// End of MP_GIC.h +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a5_smp/gnu/example_build/MP_Mutexes.S b/ports_smp/cortex_a5_smp/gnu/example_build/MP_Mutexes.S new file mode 100644 index 00000000..771e3321 --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/example_build/MP_Mutexes.S @@ -0,0 +1,134 @@ +// ------------------------------------------------------------ +// Armv7-A MPCore - Mutex Code +// +// Copyright (c) 2011-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + + + .text + .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + + + //NOTES + // struct mutex_t defined in MP_Mutexes.h + // typedef struct mutex_t + // { + // unsigned int lock// <-- offset 0 + // } + // + // lock: 0xFF=unlocked 0x0 = Locked by CPU 0, 0x1 = Locked by CPU 1, 0x2 = Locked by CPU 2, 0x3 = Locked by CPU 3 + // + +.equ UNLOCKED, 0xFF + +// ------------------------------------------------------------ + + .global initMutex + // void initMutex(mutex_t* pMutex) + // Places mutex into a known state + // r0 = address of mutex_t + .type initMutex, "function" + .cfi_startproc +initMutex: + + MOV r1, #UNLOCKED // Mark as unlocked + STR r1, [r0] + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global lockMutex + // void lockMutex(mutex_t* pMutex) + // Blocking call, returns once successfully locked a mutex + // r0 = address of mutex_t + .type lockMutex, "function" + .cfi_startproc +lockMutex: + + // Is mutex locked? + // ----------------- + LDREX r1, [r0] // Read lock field + CMP r1, #UNLOCKED // Compare with "unlocked" + + WFENE // If mutex is locked, go into standby + BNE lockMutex // On waking re-check the mutex + + // Attempt to lock mutex + // ----------------------- + MRC p15, 0, r1, c0, c0, 5 // Read CPU ID register + AND r1, r1, #0x03 // Mask off, leaving the CPU ID field. + STREX r2, r1, [r0] // Attempt to lock mutex, by write CPU's ID to lock field + CMP r2, #0x0 // Check whether store completed successfully (0=succeeded) + BNE lockMutex // If store failed, go back to beginning and try again + + DMB + + BX lr // Return as mutex is now locked by this cpu + .cfi_endproc + + +// ------------------------------------------------------------ + + .global unlockMutex + // unsigned int unlockMutex(mutex_t* pMutex) + // Releases mutex, returns 0x0 for success and 0x1 for failure + // r0 = address of mutex_t + .type unlockMutex, "function" + .cfi_startproc +unlockMutex: + + // Does this CPU own the mutex? + // ----------------------------- + MRC p15, 0, r1, c0, c0, 5 // Read CPU ID register + AND r1, r1, #0x03 // Mask off, leaving the CPU ID in r1 + LDR r2, [r0] // Read the lock field of the mutex + CMP r1, r2 // Compare ID of this CPU with the lock owner + MOVNE r0, #0x1 // If ID doesn't match, return "fail" + BXNE lr + + + // Unlock mutex + // ------------- + DMB // Ensure that accesses to shared resource have completed + + MOV r1, #UNLOCKED // Write "unlocked" into lock field + STR r1, [r0] + + DSB // Ensure that no instructions following the barrier execute until + // all memory accesses prior to the barrier have completed. + + SEV // Send event to other CPUs, wakes anyone waiting on a mutex (using WFE) + + MOV r0, #0x0 // Return "success" + BX lr + .cfi_endproc + + + +// ------------------------------------------------------------ + + .global isMutexLocked + // unsigned int isMutexLocked(mutex_t* pMutex) + // Returns 0x0 if mutex unlocked, 0x1 is locked + // r0 = address of mutex_t + .type isMutexLocked, "function" + .cfi_startproc +isMutexLocked: + LDR r0, [r0] + CMP r0, #UNLOCKED + MOVEQ r0, #0x0 + MOVNE r0, #0x1 + BX lr + .cfi_endproc + + + +// ------------------------------------------------------------ +// End of MP_Mutexes.s +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a5_smp/gnu/example_build/MP_Mutexes.h b/ports_smp/cortex_a5_smp/gnu/example_build/MP_Mutexes.h new file mode 100644 index 00000000..e410677b --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/example_build/MP_Mutexes.h @@ -0,0 +1,40 @@ +// ------------------------------------------------------------ +// MP Mutex Header File +// +// Copyright (c) 2011-2014 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#ifndef MP_MUTEX_H +#define MP_MUTEX_H + +// 0xFF = unlocked +// 0x0 = Locked by CPU 0 +// 0x1 = Locked by CPU 1 +// 0x2 = Locked by CPU 2 +// 0x3 = Locked by CPU 3 +typedef struct +{ + unsigned int lock; +}mutex_t; + +// Places mutex into a known state +// r0 = address of mutex_t +void initMutex(mutex_t* pMutex); + +// Blocking call, returns once successfully locked a mutex +// r0 = address of mutex_t +void lockMutex(mutex_t* pMutex); + +// Releases (unlock) mutex. Fails if CPU not owner of mutex. +// returns 0x0 for success, and 0x1 for failure +// r0 = address of mutex_t +unsigned int unlockMutex(mutex_t* pMutex); + +// Returns 0x0 if mutex unlocked, 0x1 is locked +// r0 = address of mutex_t +unsigned int isMutexLocked(mutex_t* pMutex); + +#endif diff --git a/ports_smp/cortex_a5_smp/gnu/example_build/MP_PrivateTimer.S b/ports_smp/cortex_a5_smp/gnu/example_build/MP_PrivateTimer.S new file mode 100644 index 00000000..2077d917 --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/example_build/MP_PrivateTimer.S @@ -0,0 +1,118 @@ +// ------------------------------------------------------------ +// Cortex-A MPCore - Private timer functions +// +// Copyright ARM Ltd 2009. All rights reserved. +// ------------------------------------------------------------ + + .text + .align 3 + + // PPI ID 29 + + + // Typical set of calls to enable Timer: + // init_private_timer(0xXXXX, 0) <-- Counter down value of 0xXXXX, with auto-reload + // start_private_timer() + + // Timer offset from base of private peripheral space --> 0x600 + +// ------------------------------------------------------------ + + .global init_private_timer + .type init_private_timer,function + // void init_private_timer(unsigned int load_value, unsigned int auto_reload) + // Sets up the private timer + // r0: initial load value + // r1: IF 0 (AutoReload) ELSE (SingleShot) +init_private_timer: + + // Get base address of private perpherial space + MOV r2, r0 // Make a copy of r0 before corrupting + MRC p15, 4, r0, c15, c0, 0 // Read periph base address + + // Set the load value + STR r2, [r0, #0x600] + + // Control register bit layout + // Bit 0 - Enable + // Bit 1 - Auto-Reload // see DE681117 + // Bit 2 - IRQ Generation + + // Form control reg value + CMP r1, #0 // Check whether to enable auto-reload + MOVNE r2, #0x04 // No auto-reload + MOVEQ r2, #0x06 // With auto-reload + + // Store to control register + STR r2, [r0, #0x608] + + BX lr + +// ------------------------------------------------------------ + + // void start_private_timer(void) + // Starts the private timer + .global start_private_timer + .type start_private_timer,function +start_private_timer: + + MRC p15, 4, r0, c15, c0, 0 // Read periph base address + + LDR r1, [r0, #0x608] // Read control reg + ORR r1, r1, #0x01 // Set enable bit + STR r1, [r0, #0x608] // Write modified value back + + BX lr + +// ------------------------------------------------------------ + + // void stop_private_timer(void) + // Stops the private timer + .global stop_private_timer + .type stop_private_timer,function +stop_private_timer: + + MRC p15, 4, r0, c15, c0, 0 // Read periph base address + + LDR r1, [r0, #0x608] // Read control reg + BIC r1, r1, #0x01 // Clear enable bit + STR r1, [r0, #0x608] // Write modified value back + + BX lr + +// ------------------------------------------------------------ + + // unsigned int read_private_timer(void) + // Reads the current value of the timer count register + .global get_private_timer_count + .type get_private_timer_count,function +get_private_timer_count: + + MRC p15, 4, r0, c15, c0, 0 // Read periph base address + + LDR r0, [r0, #0x604] // Read count register + + BX lr + +// ------------------------------------------------------------ + + // void clear_private_timer_irq(void) + // Clears the private timer interrupt + .global clear_private_timer_irq + .type clear_private_timer_irq,function +clear_private_timer_irq: + MRC p15, 4, r0, c15, c0, 0 // Read periph base address + + // Clear the interrupt by writing 0x1 to the Timer's Interrupt Status register + MOV r1, #1 + STR r1, [r0, #0x60C] + + BX lr + +// ------------------------------------------------------------ +// End of code +// ------------------------------------------------------------ + +// ------------------------------------------------------------ +// End of MP_PrivateTimer.s +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a5_smp/gnu/example_build/MP_PrivateTimer.h b/ports_smp/cortex_a5_smp/gnu/example_build/MP_PrivateTimer.h new file mode 100644 index 00000000..b0ab212a --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/example_build/MP_PrivateTimer.h @@ -0,0 +1,36 @@ +// ------------------------------------------------------------ +// Cortex-A MPCore - Private timer functions +// Header Filer +// +// Copyright ARM Ltd 2009. All rights reserved. +// ------------------------------------------------------------ + +#ifndef _CORTEXA_PRIVATE_TIMER_ +#define _CORTEXA_PRIVATE_TIMER_ + +// Typical set of calls to enable Timer: +// init_private_timer(0xXXXX, 0) <-- Counter down value of 0xXXXX, with auto-reload +// start_private_timer() + +// Sets up the private timer +// r0: initial load value +// r1: IF 0 (AutoReload) ELSE (SingleShot) +void init_private_timer(unsigned int load_value, unsigned int auto_reload); + +// Starts the private timer +void start_private_timer(void); + +// Stops the private timer +void stop_private_timer(void); + +// Reads the current value of the timer count register +unsigned int get_private_timer_count(void); + +// Clears the private timer interrupt +void clear_private_timer_irq(void); + +#endif + +// ------------------------------------------------------------ +// End of MP_PrivateTimer.h +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a5_smp/gnu/example_build/MP_SCU.S b/ports_smp/cortex_a5_smp/gnu/example_build/MP_SCU.S new file mode 100644 index 00000000..bd4c667b --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/example_build/MP_SCU.S @@ -0,0 +1,188 @@ +// ------------------------------------------------------------ +// Cortex-A MPCore - Snoop Control Unit (SCU) +// Suitable for Cortex-A5 MPCore and Cortex-A9 MPCore +// +// Copyright (c) 2011-2015 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + + + .text + + +// ------------------------------------------------------------ +// Misc +// ------------------------------------------------------------ + + .global getNumCPUs + // uint32_t getNumCPUs(void) + // Returns the number of CPUs in the Cluster + .type getNumCPUs, "function" +getNumCPUs: + + // Get base address of private peripheral space + MRC p15, 4, r0, c15, c0, 0 // Read periph base address + + LDR r0, [r0, #0x004] // Read SCU Configuration register + AND r0, r0, #0x3 // Bits 1:0 gives the number of cores-1 + ADD r0, r0, #1 + BX lr + + +// ------------------------------------------------------------ +// SCU +// ------------------------------------------------------------ + + // SCU offset from base of private peripheral space --> 0x000 + + .global enableSCU + // void enableSCU(void) + // Enables the SCU + .type enableSCU, "function" +enableSCU: + + MRC p15, 4, r0, c15, c0, 0 // Read periph base address + + LDR r1, [r0, #0x0] // Read the SCU Control Register + ORR r1, r1, #0x1 // Set bit 0 (The Enable bit) + STR r1, [r0, #0x0] // Write back modifed value + + BX lr + + +// ------------------------------------------------------------ + + .global getCPUsInSMP + // uint32_t getCPUsInSMP(void) + // The return value is 1 bit per core: + // bit 0 - CPU 0 + // bit 1 - CPU 1 + // etc... + .type getCPUsInSMP, "function" +getCPUsInSMP: + + MRC p15, 4, r0, c15, c0, 0 // Read periph base address + + LDR r0, [r0, #0x004] // Read SCU Configuration register + MOV r0, r0, LSR #4 // Bits 7:4 gives the cores in SMP mode, shift then mask + AND r0, r0, #0x0F + + BX lr + + +// ------------------------------------------------------------ + + .global enableMaintenanceBroadcast + // void enableMaintenanceBroadcast(void) + // Enable the broadcasting of cache & TLB maintenance operations + // When enabled AND in SMP, broadcast all "inner sharable" + // cache and TLM maintenance operations to other SMP cores + .type enableMaintenanceBroadcast, "function" +enableMaintenanceBroadcast: + MRC p15, 0, r0, c1, c0, 1 // Read Aux Ctrl register + MOV r1, r0 + ORR r0, r0, #0x01 // Set the FW bit (bit 0) + CMP r0, r1 + MCRNE p15, 0, r0, c1, c0, 1 // Write Aux Ctrl register + + BX lr + + +// ------------------------------------------------------------ + + .global disableMaintenanceBroadcast + // void disableMaintenanceBroadcast(void) + // Disable the broadcasting of cache & TLB maintenance operations + .type disableMaintenanceBroadcast, "function" +disableMaintenanceBroadcast: + MRC p15, 0, r0, c1, c0, 1 // Read Aux Ctrl register + BIC r0, r0, #0x01 // Clear the FW bit (bit 0) + MCR p15, 0, r0, c1, c0, 1 // Write Aux Ctrl register + + BX lr + + +// ------------------------------------------------------------ + + .global secureSCUInvalidate + // void secureSCUInvalidate(uint32_t cpu, uint32_t ways) + // cpu: 0x0=CPU 0 0x1=CPU 1 etc... + // This function invalidates the SCU copy of the tag rams + // for the specified core. Typically only done at start-up. + // Possible flow: + // - Invalidate L1 caches + // - Invalidate SCU copy of TAG RAMs + // - Join SMP + .type secureSCUInvalidate, "function" +secureSCUInvalidate: + AND r0, r0, #0x03 // Mask off unused bits of CPU ID + MOV r0, r0, LSL #2 // Convert into bit offset (four bits per core) + + AND r1, r1, #0x0F // Mask off unused bits of ways + MOV r1, r1, LSL r0 // Shift ways into the correct CPU field + + MRC p15, 4, r2, c15, c0, 0 // Read periph base address + + STR r1, [r2, #0x0C] // Write to SCU Invalidate All in Secure State + + BX lr + + + +// ------------------------------------------------------------ +// TrustZone +// ------------------------------------------------------------ + + .global setPrivateTimersNonSecureAccess + // void setPrivateTimersNonSecureAccess(uint32_t secure, uint32_t cpu) + // Sets whether the Private Timer & Watchdog can be accessed in NS world + // r0 - IF 0 (secure access only) ELSE (ns access allowed) + .type setPrivateTimersNonSecureAccess, "function" +setPrivateTimersNonSecureAccess: + AND r0, r0, #0x01 // Mask + ADD r1, r1, #0x04 // Adjust r1, as field starts at bit 4 + MOV r0, r0, LSL r1 // Shift bit into correct position for CPU + + MOV r12, #1 + MOV r12, r12, LSL r1 // Form a mask to clear existing bit value + + MRC p15, 4, r2, c15, c0, 0 // Read periph base address + + LDR r3, [r2, #0x54] // Read SCU Secure Access Control (SSAC) register + BIC r3, r3, r12 // Clear current value + ORR r3, r3, r0 // Set to specified value + STR r3, [r2, #0x54] // Write SCU Secure Access Control (SSAC) register + + BX lr + + +// ------------------------------------------------------------ + + .global setGlobalTimerNonSecureAccess + // void setGlobalTimerNonSecureAccess(uint32_t secure, uint32_t cpu) + // Sets whether the Global Timer can be accessed in NS world + // r0 - IF 0 (secure access only) ELSE (ns access allowed) + .type setGlobalTimerNonSecureAccess, "function" +setGlobalTimerNonSecureAccess: + AND r0, r0, #0x01 // Mask + ADD r1, r1, #0x08 // Adjust r1, as field starts at bit 8 + MOV r0, r0, LSL r1 // Shift bit into correct position for CPU + + MOV r12, #1 + MOV r12, r12, LSL r1 // Form a mask to clear existing bit value + + MRC p15, 4, r2, c15, c0, 0 // Read periph base address + + LDR r3, [r2, #0x54] // Read SCU Secure Access Control (SSAC) register + BIC r3, r3, r12 // Clear current value + ORR r3, r3, r0 // Set to specified value + STR r3, [r2, #0x54] // Write SCU Secure Access Control (SSAC) register + + BX lr + + +// ------------------------------------------------------------ +// End of MP_SCU.s +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a5_smp/gnu/example_build/MP_SCU.h b/ports_smp/cortex_a5_smp/gnu/example_build/MP_SCU.h new file mode 100644 index 00000000..af4ccfb8 --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/example_build/MP_SCU.h @@ -0,0 +1,65 @@ +// ------------------------------------------------------------ +// Cortex-A MPCore - Snoop Control Unit (SCU) +// Suitable for Cortex-A5 MPCore and Cortex-A9 MPCore +// +// Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#ifndef _CORTEXA_SCU_H +#define _CORTEXA_SCU_H + +// ------------------------------------------------------------ +// SCU +// ------------------------------------------------------------ + +// Returns the number of cores in the cluster +unsigned int getNumCPUs(void); + +// ------------------------------------------------------------ +// SCU +// ------------------------------------------------------------ + +// Enables the SCU +void enableSCU(void); + +// The return value is 1 bit per core: +// bit 0 (0x1) - CPU 0 +// bit 1 (0x2) - CPU 1 +// bit 2 (0x4) - CPU 2 +// bit 3 (0x8) - CPU 3 +unsigned int getCPUsInSMP(void); + + //Enable the broadcasting of cache & TLB maintenance operations +// When enabled AND in SMP, broadcast all "inner sharable" +// cache and TLM maintenance operations to other SMP cores +void enableMaintenanceBroadcast(void); + +// Disable the broadcasting of cache & TLB maintenance operations +void disableMaintenanceBroadcast(void); + +// cpu: 0x0=CPU 0 0x1=CPU 1 etc... +// This function invalidates the SCU copy of the tag rams +// for the specified core. +void secureSCUInvalidate(unsigned int cpu, unsigned int ways); + +// ------------------------------------------------------------ +// TrustZone +// ------------------------------------------------------------ + +// Sets whether the Private Timer & Watchdog can be accessed in NS world +// secure - IF 0 (secure access only) ELSE (ns access allowed) +void setPrivateTimersNonSecureAccess(unsigned int secure, unsigned int cpu); + + +// Sets whether the Global Timer can be accessed in NS world +// secure - IF 0 (secure access only) ELSE (ns access allowed) +void setGlobalTimersNonSecureAccess(unsigned int secure, unsigned int cpu); + +#endif + +// ------------------------------------------------------------ +// End of MP_SCU.h +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a5_smp/gnu/example_build/build_threadx.bat b/ports_smp/cortex_a5_smp/gnu/example_build/build_threadx.bat new file mode 100644 index 00000000..a4025d79 --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/example_build/build_threadx.bat @@ -0,0 +1,257 @@ +del tx.a +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 tx_initialize_low_level.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 ../src/tx_thread_context_restore.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 ../src/tx_thread_context_save.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 ../src/tx_thread_interrupt_control.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 ../src/tx_thread_interrupt_disable.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 ../src/tx_thread_interrupt_restore.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 ../src/tx_thread_irq_nesting_end.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 ../src/tx_thread_irq_nesting_start.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 ../src/tx_thread_schedule.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 ../src/tx_thread_smp_core_get.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 ../src/tx_thread_smp_core_preempt.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 ../src/tx_thread_smp_current_state_get.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 ../src/tx_thread_smp_current_thread_get.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 ../src/tx_thread_smp_initialize_wait.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 ../src/tx_thread_smp_low_level_initialize.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 ../src/tx_thread_smp_protect.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 ../src/tx_thread_smp_time_get.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 ../src/tx_thread_smp_unprotect.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 ../src/tx_thread_stack_build.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 ../src/tx_thread_system_return.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 ../src/tx_thread_vectored_context_save.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 ../src/tx_timer_interrupt.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_block_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_block_pool_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_block_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_block_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_block_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_block_pool_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_block_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_block_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_block_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_block_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_byte_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_byte_pool_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_byte_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_byte_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_byte_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_byte_pool_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_byte_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_byte_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_byte_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_byte_pool_search.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_byte_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_event_flags_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_event_flags_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_event_flags_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_event_flags_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_event_flags_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_event_flags_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_event_flags_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_event_flags_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_event_flags_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_event_flags_set_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_initialize_high_level.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_initialize_kernel_enter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_initialize_kernel_setup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_mutex_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_mutex_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_mutex_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_mutex_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_mutex_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_mutex_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_mutex_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_mutex_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_mutex_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_mutex_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_mutex_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_queue_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_queue_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_queue_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_queue_flush.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_queue_front_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_queue_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_queue_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_queue_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_queue_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_queue_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_queue_receive.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_queue_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_queue_send_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_semaphore_ceiling_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_semaphore_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_semaphore_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_semaphore_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_semaphore_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_semaphore_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_semaphore_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_semaphore_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_semaphore_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_semaphore_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_semaphore_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_semaphore_put_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_entry_exit_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_identify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_preemption_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_relinquish.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_reset.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_shell_entry.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_sleep.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_stack_analyze.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_stack_error_handler.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_stack_error_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_system_preempt_check.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_system_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_system_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_terminate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_time_slice.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_time_slice_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_timeout.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_wait_abort.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_time_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_time_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_expiration_process.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_system_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_system_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_thread_entry.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_trace_enable.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_trace_disable.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_trace_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_trace_interrupt_control.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_trace_isr_enter_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_trace_isr_exit_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_trace_object_register.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_trace_object_unregister.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_trace_user_event_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_trace_buffer_full_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_trace_event_filter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_trace_event_unfilter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_block_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_block_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_block_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_block_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_block_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_block_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_byte_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_byte_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_byte_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_byte_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_byte_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_byte_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_event_flags_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_event_flags_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_event_flags_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_event_flags_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_event_flags_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_event_flags_set_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_mutex_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_mutex_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_mutex_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_mutex_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_mutex_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_mutex_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_queue_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_queue_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_queue_flush.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_queue_front_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_queue_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_queue_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_queue_receive.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_queue_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_queue_send_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_semaphore_ceiling_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_semaphore_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_semaphore_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_semaphore_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_semaphore_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_semaphore_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_semaphore_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_semaphore_put_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_thread_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_thread_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_thread_entry_exit_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_thread_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_thread_preemption_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_thread_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_thread_relinquish.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_thread_reset.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_thread_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_thread_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_thread_terminate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_thread_time_slice_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_thread_wait_abort.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_timer_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_timer_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_timer_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_timer_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_timer_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_timer_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_smp_current_state_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_smp_debug_entry_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_smp_high_level_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_smp_rebalance_execute_list.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_smp_core_exclude.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_smp_core_exclude_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_smp_core_exclude.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_smp_core_exclude_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_smp_utilities.c +arm-none-eabi-ar -r tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o +arm-none-eabi-ar -r tx.a tx_initialize_low_level.o tx_thread_interrupt_disable.o +arm-none-eabi-ar -r tx.a tx_thread_interrupt_restore.o tx_thread_irq_nesting_end.o tx_thread_irq_nesting_start.o +arm-none-eabi-ar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o +arm-none-eabi-ar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o +arm-none-eabi-ar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o +arm-none-eabi-ar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o +arm-none-eabi-ar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o +arm-none-eabi-ar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o +arm-none-eabi-ar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o +arm-none-eabi-ar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o +arm-none-eabi-ar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o +arm-none-eabi-ar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o +arm-none-eabi-ar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o +arm-none-eabi-ar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o +arm-none-eabi-ar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o +arm-none-eabi-ar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o +arm-none-eabi-ar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o +arm-none-eabi-ar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o +arm-none-eabi-ar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o +arm-none-eabi-ar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o +arm-none-eabi-ar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o +arm-none-eabi-ar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o +arm-none-eabi-ar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o +arm-none-eabi-ar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o +arm-none-eabi-ar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o +arm-none-eabi-ar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o +arm-none-eabi-ar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o +arm-none-eabi-ar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o +arm-none-eabi-ar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o +arm-none-eabi-ar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o +arm-none-eabi-ar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o +arm-none-eabi-ar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o +arm-none-eabi-ar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o +arm-none-eabi-ar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o +arm-none-eabi-ar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o +arm-none-eabi-ar -r tx.a tx_thread_smp_current_state_set.o tx_thread_smp_debug_entry_insert.o tx_thread_smp_high_level_initialize.o +arm-none-eabi-ar -r tx.a tx_thread_smp_rebalance_execute_list.o tx_thread_smp_core_exclude.o tx_thread_smp_core_exclude_get.o +arm-none-eabi-ar -r tx.a tx_timer_smp_core_exclude.o tx_timer_smp_core_exclude_get.o tx_thread_smp_utilities.o +arm-none-eabi-ar -r tx.a tx_thread_smp_core_get.o tx_thread_smp_core_preempt.o tx_thread_smp_current_state_get.o tx_thread_smp_current_thread_get.o tx_thread_smp_initialize_wait.o +arm-none-eabi-ar -r tx.a tx_thread_smp_low_level_initialize.o tx_thread_smp_protect.o tx_thread_smp_time_get.o tx_thread_smp_unprotect.o diff --git a/ports_smp/cortex_a5_smp/gnu/example_build/build_threadx_sample.bat b/ports_smp/cortex_a5_smp/gnu/example_build/build_threadx_sample.bat new file mode 100644 index 00000000..07ed3d36 --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/example_build/build_threadx_sample.bat @@ -0,0 +1,8 @@ +arm-none-eabi-gcc -c -g -I../../../../common_smp/inc -I../inc -mcpu=cortex-a5 sample_threadx.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 startup.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 MP_GIC.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 MP_SCU.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 MP_Mutexes.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 MP_PrivateTimer.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 v7.S +arm-none-eabi-gcc -T sample_threadx.ld -e Vectors -o sample_threadx.axf MP_PrivateTimer.o MP_GIC.o MP_Mutexes.o MP_SCU.o sample_threadx.o startup.o v7.o tx.a -Wl,-M > sample_threadx.map diff --git a/ports_smp/cortex_a5_smp/gnu/example_build/sample_threadx.c b/ports_smp/cortex_a5_smp/gnu/example_build/sample_threadx.c new file mode 100644 index 00000000..1b6df7c2 --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/example_build/sample_threadx.c @@ -0,0 +1,381 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_TIMER timer_0; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +#ifdef TX_ENABLE_EVENT_TRACE + +UCHAR event_buffer[65536]; + +#endif + + + +int main(void) +{ + + /* Enter ThreadX. */ + tx_kernel_enter(); + + return 0; +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + +#ifdef TX_ENABLE_EVENT_TRACE + + tx_trace_enable(event_buffer, sizeof(event_buffer), 32); +#endif + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + diff --git a/ports_smp/cortex_a5_smp/gnu/example_build/sample_threadx.ld b/ports_smp/cortex_a5_smp/gnu/example_build/sample_threadx.ld new file mode 100644 index 00000000..fb1ca03c --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/example_build/sample_threadx.ld @@ -0,0 +1,182 @@ +/* Linker script to place sections and symbol values. + * It references following symbols, which must be defined in code: + * Vectors : Entry point + * + * It defines following symbols, which code can use without definition: + * __code_start + * __exidx_start + * __exidx_end + * __data_start + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __bss_start__ + * __bss_end__ + * __end__ + * __stack + * __irq_stack + * __stack + * __pagetable_start + */ +ENTRY(Vectors) + +SECTIONS +{ + + .vectors 0x80008000: + { + _exec = .; + __code_start = .; + KEEP(*(VECTORS)) + } + + .init : + { + KEEP (*(SORT_NONE(.init))) + } + + .text : + { + KEEP(*(ENABLE_CACHES)) + *(.text*) + } + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } + + .rodata : + { + *(.rodata .rodata.* .gnu.linkonce.r.*) + } + + .eh_frame : + { + KEEP (*(.eh_frame)) + } + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } + + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array )) + PROVIDE_HIDDEN (__init_array_end = .); + } + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array )) + PROVIDE_HIDDEN (__fini_array_end = .); + } + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } + + .jcr : + { + KEEP (*(.jcr)) + } + + .data : + { + __data_start = . ; + *(.data .data.* .gnu.linkonce.d.*) + SORT(CONSTRUCTORS) + } + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } + + .heap (NOLOAD): + { + . = ALIGN(64); + __end__ = .; + PROVIDE(end = .); + . = . + 0xA0000; + } + + .stack (NOLOAD): + { + . = ALIGN(64); + . = . + 4 * 0x4000; + __stack = .; + _stack_init_usr = .; + } + + .irq_stacks (NOLOAD): + { + . = ALIGN(64); + . = . + 4 * 1024; + __irq_stack = .; + _stack_init_irq = .; + } + + _end = .; + + .pagetable 0x80100000 (NOLOAD): + { + _page_table_top = .; + __pagetable_start = .; + . = . + 0x4000; + } +} diff --git a/ports_smp/cortex_a5_smp/gnu/example_build/startup.S b/ports_smp/cortex_a5_smp/gnu/example_build/startup.S new file mode 100644 index 00000000..65b1ba90 --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/example_build/startup.S @@ -0,0 +1,690 @@ +@; ------------------------------------------------------------ +@; Cortex-A15 MPCore SMP Prime Number Generator Example +@; +@; Copyright (c) 2011-2012 ARM Ltd. All rights reserved. +@; ------------------------------------------------------------ +@ +@ PRESERVE8 +@ +@ AREA StartUp,CODE,READONLY +@ +@; Standard definitions of mode bits and interrupt (I&F) flags in PSRs +@ +Mode_USR = 0x10 +Mode_FIQ = 0x11 +Mode_IRQ = 0x12 +Mode_SVC = 0x13 +Mode_ABT = 0x17 +Mode_UNDEF = 0x1B +Mode_SYS = 0x1F + +I_Bit = 0x80 @ when I bit is set, IRQ is disabled +F_Bit = 0x40 @ when F bit is set, FIQ is disabled + +SYS_MODE = 0xDF +SVC_MODE = 0xD3 +IRQ_MODE = 0xD2 + +@; ------------------------------------------------------------ +@; Porting defines +@; ------------------------------------------------------------ +@ +L1_COHERENT = 0x00014c06 @ Template descriptor for coherent memory +L1_NONCOHERENT = 0x00000c1e @ Template descriptor for non-coherent memory +L1_DEVICE = 0x00000c06 @ Template descriptor for device memory + +.section VECTORS, "ax" +.align 3 +.cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + +@; ------------------------------------------------------------ +@ +@ ENTRY +@ + .global Vectors +Vectors: + B Reset_Handler + B Undefined_Handler + B SVC_Handler + B Prefetch_Handler + B Abort_Handler + B Hypervisor_Handler + B IRQ_Handler + B FIQ_Handler + +@; ------------------------------------------------------------ +@; Handlers for unused exceptions +@; ------------------------------------------------------------ +@ +Undefined_Handler: + B Undefined_Handler +SVC_Handler: + B SVC_Handler +Prefetch_Handler: + B Prefetch_Handler +Abort_Handler: + B Abort_Handler +Hypervisor_Handler: + B Hypervisor_Handler +FIQ_Handler: + B FIQ_Handler + +@; ------------------------------------------------------------ +@; Imports +@; ------------------------------------------------------------ + .global readIntAck + .global writeEOI + .global enableGIC + .global enableGICProcessorInterface + .global setPriorityMask + .global enableIntID + .global setIntPriority + .global joinSMP + + .global invalidateCaches + .global disableHighVecs + .global _start +@; [Grape Change Start] +@; IMPORT main_app + + .global _tx_thread_smp_initialize_wait + .global _tx_thread_smp_release_cores_flag + .global _tx_thread_context_save + .global _tx_thread_context_restore + .global _tx_timer_interrupt + .global _tx_thread_smp_inter_core_interrupts + + .global enableBranchPrediction + .global enableCaches + +VFPEnable = 0x40000000 @ VFP enable value + +@;/*------------------------------------------------------------------------*/ +@;/*--- Versatile Express(Timer0) ---*/ +GIC_DIST_CPUTARGET = 0x2C001820 +GIC_DIST_CPUTARGET_VALUE = 0x000f0000 + +GIC_DIST_CONFIG = 0x2C001C08 +GIC_DIST_CONFIG_VALUE = 0x00000000 + +GIC_DIST_PRIO = 0x2C001420 +GIC_DIST_PRIO_VALUE = 0x00a00000 + +GIC_DIST_CONTROL = 0x2C001000 +GIC_DIST_CONTROL_VALUE = 0x00000001 + +GIC_CPU_CONTROL = 0x2C002000 +GIC_CPU_CONTROL_VALUE = 0x00000001 + +GIC_CPU_PRIO_MASK = 0x2C002004 +GIC_CPU_PRIO_MASK_VALUE = 0x000000ff + +GIC_DIST_ENABLE_SET = 0x2C001104 +GIC_DIST_ENABLE_SET_VALUE = 0x00000004 + +GIC_CPU_INTACK = 0x2C00200C +GIC_CPU_EOI = 0x2C002010 +; +; +; +TIMCLK_CTRL = 0x1C020000 +TIMCLK_CTRL_VALUE = 0x00028000 @ Use EXTCLK (1MHz) for TIMCLK not REFCLK32KHZ + +TIMER_LOAD = 0x1C110000 +TIMER_LOAD_VALUE = 0x00000140 @ 10ms + +TIMER_CTRL = 0x1C110008 +TIMER_CTRL_STOP = 0x00000020 +TIMER_CTRL_VALUE = 0x000000E0 +TIMER_ACK = 34 @ Timer0 +TIMER_INT_CLR = 0x1C11000C +; +HANDLER_SET = 0x80000018 +HANDLER_SET_VALUE = 0xE59FF018 +HANDLER_ADDRESS = 0x80000038 @ irq + +@;/*--- Versatile Express(Timer0) ---*/ +@;/*------------------------------------------------------------------------*/ +@; [Grape Change End] + + .global _page_table_top + .global _exec + .global _stack_init_irq + .global _stack_init_usr + +@; ------------------------------------------------------------ +@; Interrupt Handler +@; ------------------------------------------------------------ +@ +@ EXPORT IRQ_Handler + .align 2 + .global IRQ_Handler + .type IRQ_Handler,function +IRQ_Handler: +@; [Grape Change Start] + .global __tx_irq_processing_return +@; SUB lr, lr, #4 ; Pre-adjust lr +@; SRSFD sp!, #Mode_IRQ ; Save lr and SPRS to IRQ mode stack +@; PUSH {r0-r4, r12} ; Save APCS corruptible registers to IRQ mode stack (and maintain 8 byte alignment) +@; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return: + PUSH {r4, r5} @ Save some preserved registers (r5 is saved just for 8-byte alignment) +@; [Grape Change End] + + @ Acknowledge the interrupt + BL readIntAck + MOV r4, r0 + + // + // This example only uses (and enables) one. At this point + // you would normally check the ID, and clear the source. + // + + // + // Additonal code to handler private timer interrupt on CPU0 + // + + CMP r0, #29 // If not Private Timer interrupt (ID 29), by pass + BNE by_pass + +// [EL Change Start] +// MOV r0, #0x04 // Code for SYS_WRITE0 +// LDR r1, =irq_handler_message0 +// SVC 0x123456 +// [EL Change End] + + // Clear timer interrupt + BL clear_private_timer_irq + DSB +// [EL Change Start] + BL _tx_timer_interrupt // Timer interrupt handler +// [EL Change End] + + B by_pass2 + +by_pass: + +// [EL Change Start] + // + // Additional code to handle SGI on CPU0 + // +// +// MRC p15, 0, r0, c0, c0, 5 // Read CPU ID register +// ANDS r0, r0, #0x03 // Mask off, leaving the CPU ID field +// BNE by_pass2 +// +// MOV r0, #0x04 // Code for SYS_WRITE0 +// LDR r1, =irq_handler_message1 +// SVC 0x123456 +// +// /* Just increment the per-thread interrupt count for analysis purposes. */ +// + MRC p15, 0, r0, c0, c0, 5 // Read CPU ID register + AND r0, r0, #0x03 // Mask off, leaving the CPU ID field + LSL r0, r0, #2 // Build offset to array indexes + LDR r1,=_tx_thread_smp_inter_core_interrupts // Pickup base address of core interrupt counter array + ADD r1, r1, r0 // Build array index + LDR r0, [r1] // Pickup counter + ADD r0, r0, #1 // Increment counter + STR r0, [r1] // Store back counter +// +// [EL Change End] + + +by_pass2: + // Write end of interrupt reg + MOV r0, r4 + BL writeEOI + +// [EL Change Start] + +// +// /* Jump to context restore to restore system context. */ + POP {r4, r5} // Recover preserved registers + B _tx_thread_context_restore + +// POP {r0-r4, r12} // Restore stacked APCS registers +// MOV r2, #0x01 // Set r2 so CPU leaves holding pen +// RFEFD sp! // Return from exception +// [EL Change End] + + + +@; ------------------------------------------------------------ +@; Reset Handler - Generic initialization, run by all CPUs +@; ------------------------------------------------------------ +@ +@ EXPORT Reset_Handler + .align 2 + .global $Reset_Handler + .type $Reset_Handler,function +Reset_Handler: + +@ ; +@ ; Set ACTLR.SMP bit +@ ; ------------------ + BL joinSMP + +@; +@; Disable caches, MMU and branch prediction in case they were left enabled from an earlier run +@; This does not need to be done from a cold reset +@; ------------------------------------------------------------ + MRC p15, 0, r0, c1, c0, 0 @ Read CP15 System Control register + BIC r0, r0, #(0x1 << 12) @ Clear I bit 12 to disable I Cache + BIC r0, r0, #(0x1 << 2) @ Clear C bit 2 to disable D Cache + BIC r0, r0, #0x1 @ Clear M bit 0 to disable MMU + BIC r0, r0, #(0x1 << 11) @ Clear Z bit 11 to disable branch prediction + MCR p15, 0, r0, c1, c0, 0 @ Write CP15 System Control register + +@; The MMU is enabled later, before calling main(). Caches and branch prediction are enabled inside main(), +@; after the MMU has been enabled and scatterloading has been performed. +@ +@ ; +@ ; Setup stacks +@ ;--------------- + + MRC p15, 0, r0, c0, c0, 5 @ Read CPU ID register + ANDS r0, r0, #0x03 @ Mask off, leaving the CPU ID field + +@; [Grape Change Start] +@; MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit +@; LDR r1, =_stack_init_irq ; IRQ stacks for CPU 0,1,2,3 +@; SUB r1, r1, r0, LSL #8 ; 256 bytes of IRQ stack per CPU (0,1,2,3) - see scatter.scat +@; MOV sp, r1 +@; +@; MSR CPSR_c, #Mode_SYS:OR:I_Bit:OR:F_Bit ; Interrupts initially disabled +@; LDR r1, =_stack_init_usr ; App stacks for all CPUs +@; SUB r1, r1, r0, LSL #12 ; 0x1000 bytes of App stack per CPU - see scatter.scat +@; MOV sp, r1 + + + MOV r1, #IRQ_MODE @ Build IRQ mode CPSR + MSR CPSR_c, r1 @ Enter IRQ mode +@ MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit + LDR r1, =_stack_init_irq @ IRQ stacks for CPU 0,1,2,3 + SUB r1, r1, r0, LSL #10 @ 1024 bytes of IRQ stack per CPU (0,1,2,3) - see scatter.scat + MOV sp, r1 + + MOV r1, #SYS_MODE @ Build SYS mode CPSR + MSR CPSR_c, r1 @ Enter SYS mode +@ MSR CPSR_c, #Mode_SYS:OR:I_Bit:OR:F_Bit @ Interrupts initially disabled + LDR r1, =_stack_init_usr @ App stacks for all CPUs + SUB r1, r1, r0, LSL #12 @ 0x1000 bytes of App stack per CPU - see scatter.scat + MOV sp, r1 + + MOV r2, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r2 @ Enter SVC mode +@ MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit @ Interrupts initially disabled + MOV sp, r1 +@; [Grape Change End] +@ +@ ; +@ ; Set vector base address +@ ; ------------------------ + LDR r0, =Vectors + MCR p15, 0, r0, c12, c0, 0 @ Write Secure or Non-secure Vector Base Address + BL disableHighVecs @ Ensure that V-bit is cleared + +@ ; +@ ; Invalidate caches +@ ; ------------------ + BL invalidateCaches + +@ ; +@ ; Clear Branch Prediction Array +@ ; ------------------------------ + MOV r0, #0x0 + MCR p15, 0, r0, c7, c5, 6 @ BPIALL - Invalidate entire branch predictor array + +@; [Grape Change Start] +@; ; Disable loop-buffer to fix errata on A15 r0p0 +@; MRC p15, 0, r0, c0, c0, 0 ; Read main ID register MIDR +@; MOV r1, r0, lsr #4 ; Extract Primary Part Number +@; LDR r2, =0xFFF +@; AND r1, r1, r2 +@; LDR r2, =0xC0F +@; CMP r1, r2 ; Is this an A15? +@; BNE notA15r0p0 ; Jump if not A15 +@; AND r5, r0, #0x00f00000 ; Variant +@; AND r6, r0, #0x0000000f ; Revision +@; ORRS r6, r6, r5 ; Combine variant and revision +@; BNE notA15r0p0 ; Jump if not r0p0 +@; MRC p15, 0, r0, c1, c0, 1 ; Read Aux Ctrl Reg +@; ORR r0, r0, #(1 << 1) ; Set bit 1 to Disable Loop Buffer +@; MCR p15, 0, r0, c1, c0, 1 ; Write Aux Ctrl Reg +@; ISB +@;notA15r0p0 +@; [Grape Change End] +@ +@ ; +@ ; Invalidate TLBs +@ ;------------------ + MOV r0, #0x0 + MCR p15, 0, r0, c8, c7, 0 @ TLBIALL - Invalidate entire Unified TLB + +@ ; +@ ; Set up Domain Access Control Reg +@ ; ---------------------------------- +@ ; b00 - No Access (abort) +@ ; b01 - Client (respect table entry) +@ ; b10 - RESERVED +@ ; b11 - Manager (ignore access permissions) + + MRC p15, 0, r0, c3, c0, 0 @ Read Domain Access Control Register + LDR r0, =0x55555555 @ Initialize every domain entry to b01 (client) + MCR p15, 0, r0, c3, c0, 0 @ Write Domain Access Control Register + +@ ;; +@ ;; Enable L1 Preloader - Auxiliary Control +@ ;; ----------------------------------------- +@ ;; Seems to undef on panda? +@ ;MRC p15, 0, r0, c1, c0, 1 ; Read ACTLR +@ ;ORR r0, r0, #0x4 +@ ;MCR p15, 0, r0, c1, c0, 1 ; Write ACTLR +@ +@ ; Page tables +@ ; ------------------------- +@ ; Each CPU will have its own L1 page table. The +@ ; code reads the base address from the scatter file +@ ; the uses the CPUID to calculate an offset for each +@ ; CPU. +@ ; +@ ; The page tables are generated at boot time. First +@ ; the table is zeroed. Then the individual valid +@ ; entries are written in +@ ; +@ +@ ; Calculate offset for this CPU + LDR r0, =_page_table_top + MRC p15, 0, r1, c0, c0, 5 @ Read Multiprocessor Affinity Register + ANDS r1, r1, #0x03 @ Mask off, leaving the CPU ID field + MOV r1, r1, LSL #14 @ Convert core ID into a 16K offset (this is the size of the table) + ADD r0, r1, r0 @ Add offset to current table location to get dst + + @ Fill table with zeros + MOV r2, #1024 @ Set r3 to loop count (4 entries per iteration, 1024 iterations) + MOV r1, r0 @ Make a copy of the base dst + MOV r3, #0 + MOV r4, #0 + MOV r5, #0 + MOV r6, #0 +ttb_zero_loop: + STMIA r1!, {r3-r6} @ Store out four entries + SUBS r2, r2, #1 @ Decrement counter + BNE ttb_zero_loop + +@ ; +@ ; STANDARD ENTRIES +@ ; +@ +@ ; Entry for VA 0x0 +@ ; This region must be coherent +@ ;LDR r1, =PABASE_VA0 ; Physical address +@ ;LDR r2, =L1_COHERENT ; Descriptor template +@ ;ORR r1, r1, r2 ; Combine address and template +@ ;STR r1, [r0] +@ +@ +@ ; If not flat mapping, you need a page table entry covering +@ ; the physical address of the boot code. +@ ; This region must be coherent + LDR r1,=_exec @ Base physical address of code segment + LSR r1,#20 @ Shift right to align to 1MB boundaries + LDR r3, =L1_COHERENT @ Descriptor template + ORR r3, r1, LSL#20 @ Setup the initial level1 descriptor again + STR r3, [r0, r1, LSL#2] @ str table entry + +@; [Grape Change Start] +@;/*------------------------------------------------------------------------*/ +@;/*--- Versatile Express(Timer0) ---*/ + LDR r1, =0x80000000 @ Physical address of HANDLER + LSR r1, r1, #20 @ Clear bottom 20 bits, to find which 1MB block it is in + LSL r2, r1, #2 @ Make a copy, and multiply by four. This gives offset into the page tables + LSL r1, r1, #20 @ Put back in address format + + LDR r3, =L1_COHERENT @ Descriptor template + ORR r1, r1, r3 @ Combine address and template + STR r1, [r0, r2] + + LDR r1, =0x2C000000 @ Physical address of GIC_DIST + LSR r1, r1, #20 @ Clear bottom 20 bits, to find which 1MB block it is in + LSL r2, r1, #2 @ Make a copy, and multiply by four. This gives offset into the page tables + LSL r1, r1, #20 @ Put back in address format + + LDR r3, =L1_DEVICE @ Descriptor template + ORR r1, r1, r3 @ Combine address and template + STR r1, [r0, r2] + + LDR r1, =0x1C000000 @ Physical address of TIMER + LSR r1, r1, #20 @ Clear bottom 20 bits, to find which 1MB block it is in + LSL r2, r1, #2 @ Make a copy, and multiply by four. This gives offset into the page tables + LSL r1, r1, #20 @ Put back in address format + + LDR r3, =L1_DEVICE @ Descriptor template + ORR r1, r1, r3 @ Combine address and template + STR r1, [r0, r2] + + LDR r1, =0x1C100000 @ Physical address of TIMER + LSR r1, r1, #20 @ Clear bottom 20 bits, to find which 1MB block it is in + LSL r2, r1, #2 @ Make a copy, and multiply by four. This gives offset into the page tables + LSL r1, r1, #20 @ Put back in address format + + LDR r3, =L1_DEVICE @ Descriptor template + ORR r1, r1, r3 @ Combine address and template + STR r1, [r0, r2] +@;/*--- Versatile Express(Timer0) ---*/ +@;/*------------------------------------------------------------------------*/ +@; [Grape Change End] +@ +@ ; Entry for private address space +@ ; Needs to be marked as Device memory + MRC p15, 4, r1, c15, c0, 0 @ Get base address of private address space + LSR r1, r1, #20 @ Clear bottom 20 bits, to find which 1MB block it is in + LSL r2, r1, #2 @ Make a copy, and multiply by four. This gives offset into the page tables + LSL r1, r1, #20 @ Put back in address format + + LDR r3, =L1_DEVICE @ Descriptor template + ORR r1, r1, r3 @ Combine address and template + STR r1, [r0, r2] + +@ ; +@ ; OPTIONAL ENTRIES +@ ; You will need additional translations if: +@ ; - No RAM at zero, so cannot use flat mapping +@ ; - You wish to retarget +@ ; +@ ; If you wish to output to stdio to a UART you will need +@ ; an additional entry +@ ;LDR r1, =PABASE_UART ; Physical address of UART +@ ;LSR r1, r1, #20 ; Mask off bottom 20 bits to find which 1MB it is within +@ ;LSL r2, r1, #2 ; Make a copy and multiply by 4 to get table offset +@ ;LSL r1, r1, #20 ; Put back into address format +@ ;LDR r3, =L1_DEVICE ; Descriptor template +@ ;ORR r1, r1, r3 ; Combine address and template +@ ;STR r1, [r0, r2] +@ +@ ; +@ ; Barrier +@ ; -------- + DSB + +@ ; +@ ; Set location of level 1 page table +@ ;------------------------------------ +@ ; 31:14 - Base addr: 0x8050,0000 (CPU0), 0x8050,4000 (CPU1) +@ ; 13:5 - 0x0 +@ ; 4:3 - RGN 0x0 (Outer Noncachable) +@ ; 2 - P 0x0 +@ ; 1 - S 0x0 (Non-shared) +@ ; 0 - C 0x0 (Inner Noncachable) + MCR p15, 0, r0, c2, c0 ,0 + + +@ ; Enable MMU +@ ;------------- +@ ; Leaving the caches disabled until after scatter loading. + MRC p15, 0, r0, c1, c0, 0 @ Read CP15 System Control register + BIC r0, r0, #(0x1 << 12) @ Clear I bit 12 to disable I Cache + BIC r0, r0, #(0x1 << 2) @ Clear C bit 2 to disable D Cache + BIC r0, r0, #0x2 @ Clear A bit 1 to disable strict alignment fault checking + ORR r0, r0, #0x1 @ Set M bit 0 to enable MMU before scatter loading + MCR p15, 0, r0, c1, c0, 0 @ Write CP15 System Control register + +@ ; +@ ; MMU now enabled - Virtual address system now active +@ ; +@; [Grape Change Start] +#ifdef TARGET_FPU_VFP + MRC p15, 0, r1, c1, c0, 2 @ r1 = Access Control Register + ORR r1, r1, #(0xf << 20) @ Enable full access for p10,11 + MCR p15, 0, r1, c1, c0, 2 @ Access Control Register = r1 + MOV r1, #0 + MCR p15, 0, r1, c7, c5, 4 @ Flush prefetch buffer because of FMXR below and + @ CP 10 & 11 were only just enabled + MOV r0, #VFPEnable @ Enable VFP itself + FMXR FPEXC, r0 @ FPEXC = r0 +#endif + + LDR r0, =_tx_thread_smp_release_cores_flag @ Build address of release cores flag + MOV r1, #0 + STR r1, [r0] +@; [Grape Change End] +@ +@ ; +@ ; SMP initialization +@ ; ------------------- + MRC p15, 0, r0, c0, c0, 5 @ Read CPU ID register + ANDS r0, r0, #0x03 @ Mask off, leaving the CPU ID field + BEQ primaryCPUInit + BNE secondaryCPUsInit + + + + +@; ------------------------------------------------------------ +@; Initialization for PRIMARY CPU +@; ------------------------------------------------------------ +@ +@ +@ EXPORT primaryCPUInit + .align 2 + .global primaryCPUInit + .type primaryCPUInit,function +primaryCPUInit: + +@ ; +@ ; GIC Init +@ ; --------- + BL enableGIC + BL enableGICProcessorInterface + + BL enableCaches + + // + // Enable Private Timer for periodic IRQ + // -------------------------------------- + MOV r0, #0x1F + BL setPriorityMask // Set priority mask (local) + + // [EL] Change start - don't enable interrupts here! + //CPSIE i // Clear CPSR I bit + // [EL] Change end + + // Enable the Private Timer Interrupt Source + MOV r0, #29 + MOV r1, #0 + BL enableIntID + + // Set the priority + MOV r0, #29 + MOV r1, #0 + BL setIntPriority + + // Configure Timer + MOV r0, #0xF0000 + MOV r1, #0x0 + BL init_private_timer + BL start_private_timer + + // + // Enable receipt of SGI 0 + // ------------------------ + MOV r0, #0x0 // ID + BL enableIntID + + MOV r0, #0x0 // ID + MOV r1, #0x0 // Priority + BL setIntPriority + +@ ; +@ ; Branch to C lib code +@ ; ---------------------- + B _start + +@; [Grape Change End] + + +@; ------------------------------------------------------------ +@; Initialization for SECONDARY CPUs +@; ------------------------------------------------------------ +@ +@ EXPORT secondaryCPUsInit + .align 2 + .global secondaryCPUsInit + .type secondaryCPUsInit,function +secondaryCPUsInit: + +@ ; +@ ; GIC Init +@ ; --------- + BL enableGICProcessorInterface + + MOV r0, #0x1F @ Priority + BL setPriorityMask + + MOV r0, #0x0 @ ID + BL enableIntID + + MOV r0, #0x0 @ ID + MOV r1, #0x0 @ Priority + BL setIntPriority + + +@ ; +@ ; Holding Pen +@ ; ------------ +@; [Grape Change Start] +@; MOV r2, #0x00 ; Clear r2 +@; CPSIE i ; Enable interrupts +@;holding_pen +@; CMP r2, #0x0 ; r2 will be set to 0x1 by IRQ handler on receiving SGI +@; WFIEQ +@; BEQ holding_pen +@; CPSID i ; IRQs not used in rest of example, so mask out interrupts +@; [Grape Change End] +@ +@ +@ ; +@ ; Branch to application +@ ; ---------------------- +@; [Grape Change Start] +@; B main_app + +@; BL enableBranchPrediction + BL enableCaches + + B _tx_thread_smp_initialize_wait +@; [Grape Change End] +@ + + +@; ------------------------------------------------------------ +@; End of code +@; ------------------------------------------------------------ +@ +@ END +@ +@; ------------------------------------------------------------ +@; End of startup.s +@; ------------------------------------------------------------ diff --git a/ports_smp/cortex_a5_smp/gnu/example_build/tx_initialize_low_level.s b/ports_smp/cortex_a5_smp/gnu/example_build/tx_initialize_low_level.s new file mode 100644 index 00000000..327ec978 --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/example_build/tx_initialize_low_level.s @@ -0,0 +1,122 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Initialize */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_initialize.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ +@ +@ + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global _tx_version_id + .global _tx_build_options + .global _end +@ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_initialize_low_level SMP/Cortex-A5/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for any low-level processor */ +@/* initialization, including setting up interrupt vectors, setting */ +@/* up a periodic timer interrupt source, saving the system stack */ +@/* pointer for use in ISR processing later, and finding the first */ +@/* available RAM memory address for tx_application_define. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_initialize_low_level(VOID) +@{ + .global _tx_initialize_low_level + .type _tx_initialize_low_level,function +_tx_initialize_low_level: +@ +@ /* Save the first available memory address. */ +@ _tx_initialize_unused_memory = (VOID_PTR) _end; +@ + LDR r0, =_end @ Get end of non-initialized RAM area + LDR r2, =_tx_initialize_unused_memory @ Pickup unused memory ptr address + ADD r0, r0, #8 @ Increment to next free word + STR r0, [r2, #0] @ Save first free memory address +@ +@ + +@ /* Done, return to caller. */ +@ +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} +@ +@ /* Reference build options and version ID to ensure they come in. */ +@ + LDR r2, =_tx_build_options @ Pickup build options variable address + LDR r0, [r2, #0] @ Pickup build options content + LDR r2, =_tx_version_id @ Pickup version ID variable address + LDR r0, [r2, #0] @ Pickup version ID content +@ +@ + + diff --git a/ports_smp/cortex_a5_smp/gnu/example_build/v7.S b/ports_smp/cortex_a5_smp/gnu/example_build/v7.S new file mode 100644 index 00000000..67ddb163 --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/example_build/v7.S @@ -0,0 +1,531 @@ +// ------------------------------------------------------------ +// v7-A Cache and Branch Prediction Maintenance Operations +// +// Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + + .text + .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + + +// ------------------------------------------------------------ +// Interrupt enable/disable +// ------------------------------------------------------------ + + // Could use compiler intrinsics instead of these + + .global enableInterrupts + // void enableInterrupts(void) + .type enableInterrupts, "function" + .cfi_startproc +enableInterrupts: + CPSIE i + BX lr + .cfi_endproc + + + .global disableInterrupts + // void disableInterrupts(void) + .type disableInterrupts, "function" + .cfi_startproc +disableInterrupts: + CPSID i + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ +// Cache Maintenance +// ------------------------------------------------------------ + + .global enableCaches + // void enableCaches(void) + .type enableCaches, "function" + .cfi_startproc +enableCaches: + MRC p15, 0, r0, c1, c0, 0 // Read System Control Register + ORR r0, r0, #(1 << 2) // Set C bit + ORR r0, r0, #(1 << 12) // Set I bit + MCR p15, 0, r0, c1, c0, 0 // Write System Control Register + ISB + BX lr + .cfi_endproc + + + + .global disableCaches + // void disableCaches(void) + .type disableCaches, "function" + .cfi_startproc +disableCaches: + MRC p15, 0, r0, c1, c0, 0 // Read System Control Register + BIC r0, r0, #(1 << 2) // Clear C bit + BIC r0, r0, #(1 << 12) // Clear I bit + MCR p15, 0, r0, c1, c0, 0 // Write System Control Register + ISB + BX lr + .cfi_endproc + + + + .global cleanDCache + // void cleanDCache(void) + .type cleanDCache, "function" + .cfi_startproc +cleanDCache: + PUSH {r4-r12} + + // + // Based on code example given in section 11.2.4 of Armv7-A/R Architecture Reference Manual (DDI 0406B) + // + + MRC p15, 1, r0, c0, c0, 1 // Read CLIDR + ANDS r3, r0, #0x7000000 + MOV r3, r3, LSR #23 // Cache level value (naturally aligned) + BEQ clean_dcache_finished + MOV r10, #0 + +clean_dcache_loop1: + ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel + MOV r1, r0, LSR r2 // bottom 3 bits are the Cache type for this level + AND r1, r1, #7 // get those 3 bits alone + CMP r1, #2 + BLT clean_dcache_skip // no cache or only instruction cache at this level + MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register + ISB // ISB to sync the change to the CacheSizeID reg + MRC p15, 1, r1, c0, c0, 0 // reads current Cache Size ID register + AND r2, r1, #7 // extract the line length field + ADD r2, r2, #4 // add 4 for the line length offset (log2 16 bytes) + LDR r4, =0x3FF + ANDS r4, r4, r1, LSR #3 // R4 is the max number on the way size (right aligned) + CLZ r5, r4 // R5 is the bit position of the way size increment + LDR r7, =0x00007FFF + ANDS r7, r7, r1, LSR #13 // R7 is the max number of the index size (right aligned) + +clean_dcache_loop2: + MOV r9, R4 // R9 working copy of the max way size (right aligned) + +clean_dcache_loop3: + ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11 + ORR r11, r11, r7, LSL r2 // factor in the index number + MCR p15, 0, r11, c7, c10, 2 // DCCSW - clean by set/way + SUBS r9, r9, #1 // decrement the way number + BGE clean_dcache_loop3 + SUBS r7, r7, #1 // decrement the index + BGE clean_dcache_loop2 + +clean_dcache_skip: + ADD r10, r10, #2 // increment the cache number + CMP r3, r10 + BGT clean_dcache_loop1 + +clean_dcache_finished: + POP {r4-r12} + + BX lr + .cfi_endproc + + + .global cleanInvalidateDCache + // void cleanInvalidateDCache(void) + .type cleanInvalidateDCache, "function" + .cfi_startproc +cleanInvalidateDCache: + PUSH {r4-r12} + + // + // Based on code example given in section 11.2.4 of Armv7-A/R Architecture Reference Manual (DDI 0406B) + // + + MRC p15, 1, r0, c0, c0, 1 // Read CLIDR + ANDS r3, r0, #0x7000000 + MOV r3, r3, LSR #23 // Cache level value (naturally aligned) + BEQ clean_invalidate_dcache_finished + MOV r10, #0 + +clean_invalidate_dcache_loop1: + ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel + MOV r1, r0, LSR r2 // bottom 3 bits are the Cache type for this level + AND r1, r1, #7 // get those 3 bits alone + CMP r1, #2 + BLT clean_invalidate_dcache_skip // no cache or only instruction cache at this level + MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register + ISB // ISB to sync the change to the CacheSizeID reg + MRC p15, 1, r1, c0, c0, 0 // reads current Cache Size ID register + AND r2, r1, #7 // extract the line length field + ADD r2, r2, #4 // add 4 for the line length offset (log2 16 bytes) + LDR r4, =0x3FF + ANDS r4, r4, r1, LSR #3 // R4 is the max number on the way size (right aligned) + CLZ r5, r4 // R5 is the bit position of the way size increment + LDR r7, =0x00007FFF + ANDS r7, r7, r1, LSR #13 // R7 is the max number of the index size (right aligned) + +clean_invalidate_dcache_loop2: + MOV r9, R4 // R9 working copy of the max way size (right aligned) + +clean_invalidate_dcache_loop3: + ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11 + ORR r11, r11, r7, LSL r2 // factor in the index number + MCR p15, 0, r11, c7, c14, 2 // DCCISW - clean and invalidate by set/way + SUBS r9, r9, #1 // decrement the way number + BGE clean_invalidate_dcache_loop3 + SUBS r7, r7, #1 // decrement the index + BGE clean_invalidate_dcache_loop2 + +clean_invalidate_dcache_skip: + ADD r10, r10, #2 // increment the cache number + CMP r3, r10 + BGT clean_invalidate_dcache_loop1 + +clean_invalidate_dcache_finished: + POP {r4-r12} + + BX lr + .cfi_endproc + + + + .global invalidateCaches + // void invalidateCaches(void) + .type invalidateCaches, "function" + .cfi_startproc +invalidateCaches: + PUSH {r4-r12} + + // + // Based on code example given in section B2.2.4/11.2.4 of Armv7-A/R Architecture Reference Manual (DDI 0406B) + // + + MOV r0, #0 + MCR p15, 0, r0, c7, c5, 0 // ICIALLU - Invalidate entire I Cache, and flushes branch target cache + + MRC p15, 1, r0, c0, c0, 1 // Read CLIDR + ANDS r3, r0, #0x7000000 + MOV r3, r3, LSR #23 // Cache level value (naturally aligned) + BEQ invalidate_caches_finished + MOV r10, #0 + +invalidate_caches_loop1: + ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel + MOV r1, r0, LSR r2 // bottom 3 bits are the Cache type for this level + AND r1, r1, #7 // get those 3 bits alone + CMP r1, #2 + BLT invalidate_caches_skip // no cache or only instruction cache at this level + MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register + ISB // ISB to sync the change to the CacheSizeID reg + MRC p15, 1, r1, c0, c0, 0 // reads current Cache Size ID register + AND r2, r1, #7 // extract the line length field + ADD r2, r2, #4 // add 4 for the line length offset (log2 16 bytes) + LDR r4, =0x3FF + ANDS r4, r4, r1, LSR #3 // R4 is the max number on the way size (right aligned) + CLZ r5, r4 // R5 is the bit position of the way size increment + LDR r7, =0x00007FFF + ANDS r7, r7, r1, LSR #13 // R7 is the max number of the index size (right aligned) + +invalidate_caches_loop2: + MOV r9, R4 // R9 working copy of the max way size (right aligned) + +invalidate_caches_loop3: + ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11 + ORR r11, r11, r7, LSL r2 // factor in the index number + MCR p15, 0, r11, c7, c6, 2 // DCISW - invalidate by set/way + SUBS r9, r9, #1 // decrement the way number + BGE invalidate_caches_loop3 + SUBS r7, r7, #1 // decrement the index + BGE invalidate_caches_loop2 + +invalidate_caches_skip: + ADD r10, r10, #2 // increment the cache number + CMP r3, r10 + BGT invalidate_caches_loop1 + +invalidate_caches_finished: + POP {r4-r12} + BX lr + .cfi_endproc + + + + .global invalidateCaches_IS + // void invalidateCaches_IS(void) + .type invalidateCaches_IS, "function" + .cfi_startproc +invalidateCaches_IS: + PUSH {r4-r12} + + MOV r0, #0 + MCR p15, 0, r0, c7, c1, 0 // ICIALLUIS - Invalidate entire I Cache inner shareable + + MRC p15, 1, r0, c0, c0, 1 // Read CLIDR + ANDS r3, r0, #0x7000000 + MOV r3, r3, LSR #23 // Cache level value (naturally aligned) + BEQ invalidate_caches_is_finished + MOV r10, #0 + +invalidate_caches_is_loop1: + ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel + MOV r1, r0, LSR r2 // bottom 3 bits are the Cache type for this level + AND r1, r1, #7 // get those 3 bits alone + CMP r1, #2 + BLT invalidate_caches_is_skip // no cache or only instruction cache at this level + MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register + ISB // ISB to sync the change to the CacheSizeID reg + MRC p15, 1, r1, c0, c0, 0 // reads current Cache Size ID register + AND r2, r1, #7 // extract the line length field + ADD r2, r2, #4 // add 4 for the line length offset (log2 16 bytes) + LDR r4, =0x3FF + ANDS r4, r4, r1, LSR #3 // R4 is the max number on the way size (right aligned) + CLZ r5, r4 // R5 is the bit position of the way size increment + LDR r7, =0x00007FFF + ANDS r7, r7, r1, LSR #13 // R7 is the max number of the index size (right aligned) + +invalidate_caches_is_loop2: + MOV r9, R4 // R9 working copy of the max way size (right aligned) + +invalidate_caches_is_loop3: + ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11 + ORR r11, r11, r7, LSL r2 // factor in the index number + MCR p15, 0, r11, c7, c6, 2 // DCISW - clean by set/way + SUBS r9, r9, #1 // decrement the way number + BGE invalidate_caches_is_loop3 + SUBS r7, r7, #1 // decrement the index + BGE invalidate_caches_is_loop2 + +invalidate_caches_is_skip: + ADD r10, r10, #2 // increment the cache number + CMP r3, r10 + BGT invalidate_caches_is_loop1 + +invalidate_caches_is_finished: + POP {r4-r12} + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ +// TLB +// ------------------------------------------------------------ + + .global invalidateUnifiedTLB + // void invalidateUnifiedTLB(void) + .type invalidateUnifiedTLB, "function" + .cfi_startproc +invalidateUnifiedTLB: + MOV r0, #0 + MCR p15, 0, r0, c8, c7, 0 // TLBIALL - Invalidate entire unified TLB + BX lr + .cfi_endproc + + + .global invalidateUnifiedTLB_IS + // void invalidateUnifiedTLB_IS(void) + .type invalidateUnifiedTLB_IS, "function" + .cfi_startproc +invalidateUnifiedTLB_IS: + MOV r0, #1 + MCR p15, 0, r0, c8, c3, 0 // TLBIALLIS - Invalidate entire unified TLB Inner Shareable + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ +// Branch Prediction +// ------------------------------------------------------------ + + .global flushBranchTargetCache + // void flushBranchTargetCache(void) + .type flushBranchTargetCache, "function" + .cfi_startproc +flushBranchTargetCache: + MOV r0, #0 + MCR p15, 0, r0, c7, c5, 6 // BPIALL - Invalidate entire branch predictor array + BX lr + .cfi_endproc + + + .global flushBranchTargetCache_IS + // void flushBranchTargetCache_IS(void) + .type flushBranchTargetCache_IS, "function" + .cfi_startproc +flushBranchTargetCache_IS: + MOV r0, #0 + MCR p15, 0, r0, c7, c1, 6 // BPIALLIS - Invalidate entire branch predictor array Inner Shareable + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ +// High Vecs +// ------------------------------------------------------------ + + .global enableHighVecs + // void enableHighVecs(void) + .type enableHighVecs, "function" + .cfi_startproc +enableHighVecs: + MRC p15, 0, r0, c1, c0, 0 // Read Control Register + ORR r0, r0, #(1 << 13) // Set the V bit (bit 13) + MCR p15, 0, r0, c1, c0, 0 // Write Control Register + ISB + BX lr + .cfi_endproc + + + .global disableHighVecs + // void disable_highvecs(void) + .type disableHighVecs, "function" + .cfi_startproc +disableHighVecs: + MRC p15, 0, r0, c1, c0, 0 // Read Control Register + BIC r0, r0, #(1 << 13) // Clear the V bit (bit 13) + MCR p15, 0, r0, c1, c0, 0 // Write Control Register + ISB + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ +// Context ID +// ------------------------------------------------------------ + + .global getContextID + // uint32_t getContextIDd(void) + .type getContextID, "function" + .cfi_startproc +getContextID: + MRC p15, 0, r0, c13, c0, 1 // Read Context ID Register + BX lr + .cfi_endproc + + + .global setContextID + // void setContextID(uint32_t) + .type setContextID, "function" + .cfi_startproc +setContextID: + MCR p15, 0, r0, c13, c0, 1 // Write Context ID Register + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ +// ID registers +// ------------------------------------------------------------ + + .global getMIDR + // uint32_t getMIDR(void) + .type getMIDR, "function" + .cfi_startproc +getMIDR: + MRC p15, 0, r0, c0, c0, 0 // Read Main ID Register (MIDR) + BX lr + .cfi_endproc + + + .global getMPIDR + // uint32_t getMPIDR(void) + .type getMPIDR, "function" + .cfi_startproc +getMPIDR: + MRC p15, 0, r0, c0 ,c0, 5 // Read Multiprocessor ID register (MPIDR) + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ +// CP15 SMP related +// ------------------------------------------------------------ + + .global getBaseAddr + // uint32_t getBaseAddr(void) + // Returns the value CBAR (base address of the private peripheral memory space) + .type getBaseAddr, "function" + .cfi_startproc +getBaseAddr: + MRC p15, 4, r0, c15, c0, 0 // Read peripheral base address + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global getCPUID + // uint32_t getCPUID(void) + // Returns the CPU ID (0 to 3) of the CPU executed on + .type getCPUID, "function" + .cfi_startproc +getCPUID: + MRC p15, 0, r0, c0, c0, 5 // Read CPU ID register + AND r0, r0, #0x03 // Mask off, leaving the CPU ID field + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global goToSleep + // void goToSleep(void) + .type goToSleep, "function" + .cfi_startproc +goToSleep: + DSB // Clear all pending data accesses + WFI // Go into standby + B goToSleep // Catch in case of rogue events + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global joinSMP + // void joinSMP(void) + // Sets the ACTRL.SMP bit + .type joinSMP, "function" + .cfi_startproc +joinSMP: + + // SMP status is controlled by bit 6 of the CP15 Aux Ctrl Reg + + MRC p15, 0, r0, c1, c0, 1 // Read ACTLR + MOV r1, r0 + ORR r0, r0, #0x040 // Set bit 6 + CMP r0, r1 + MCRNE p15, 0, r0, c1, c0, 1 // Write ACTLR + ISB + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global leaveSMP + // void leaveSMP(void) + // Clear the ACTRL.SMP bit + .type leaveSMP, "function" + .cfi_startproc +leaveSMP: + + // SMP status is controlled by bit 6 of the CP15 Aux Ctrl Reg + + MRC p15, 0, r0, c1, c0, 1 // Read ACTLR + BIC r0, r0, #0x040 // Clear bit 6 + MCR p15, 0, r0, c1, c0, 1 // Write ACTLR + ISB + + BX lr + .cfi_endproc + + .align 2 + .global _exit + .type _exit,function +_exit: + BX lr + + +// ------------------------------------------------------------ +// End of v7.s +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a5_smp/gnu/example_build/v7.h b/ports_smp/cortex_a5_smp/gnu/example_build/v7.h new file mode 100644 index 00000000..5a08b43f --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/example_build/v7.h @@ -0,0 +1,155 @@ +// ------------------------------------------------------------ +// v7-A Cache, TLB and Branch Prediction Maintenance Operations +// Header File +// +// Copyright (c) 2011-2016 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#ifndef _ARMV7A_GENERIC_H +#define _ARMV7A_GENERIC_H + +// ------------------------------------------------------------ +// Memory barrier mnemonics +enum MemBarOpt { + RESERVED_0 = 0, RESERVED_1 = 1, OSHST = 2, OSH = 3, + RESERVED_4 = 4, RESERVED_5 = 5, NSHST = 6, NSH = 7, + RESERVED_8 = 8, RESERVED_9 = 9, ISHST = 10, ISH = 11, + RESERVED_12 = 12, RESERVED_13 = 13, ST = 14, SY = 15 +}; + +// +// Note: +// *_IS() stands for "inner shareable" +// DO NOT USE THESE FUNCTIONS ON A CORTEX-A8 +// + +// ------------------------------------------------------------ +// Interrupts +// Enable/disables IRQs (not FIQs) +void enableInterrupts(void); +void disableInterrupts(void); + +// ------------------------------------------------------------ +// Caches + +void invalidateCaches_IS(void); +void cleanInvalidateDCache(void); +void invalidateCaches_IS(void); +void enableCaches(void); +void disableCaches(void); +void invalidateCaches(void); +void cleanDCache(void); + +// ------------------------------------------------------------ +// TLBs + +void invalidateUnifiedTLB(void); +void invalidateUnifiedTLB_IS(void); + +// ------------------------------------------------------------ +// Branch prediction + +void flushBranchTargetCache(void); +void flushBranchTargetCache_IS(void); + +// ------------------------------------------------------------ +// High Vecs + +void enableHighVecs(void); +void disableHighVecs(void); + +// ------------------------------------------------------------ +// ID Registers + +unsigned int getMIDR(void); + +#define MIDR_IMPL_SHIFT 24 +#define MIDR_IMPL_MASK 0xFF +#define MIDR_VAR_SHIFT 20 +#define MIDR_VAR_MASK 0xF +#define MIDR_ARCH_SHIFT 16 +#define MIDR_ARCH_MASK 0xF +#define MIDR_PART_SHIFT 4 +#define MIDR_PART_MASK 0xFFF +#define MIDR_REV_SHIFT 0 +#define MIDR_REV_MASK 0xF + +// tmp = get_MIDR(); +// implementor = (tmp >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; +// variant = (tmp >> MIDR_VAR_SHIFT) & MIDR_VAR_MASK; +// architecture= (tmp >> MIDR_ARCH_SHIFT) & MIDR_ARCH_MASK; +// part_number = (tmp >> MIDR_PART_SHIFT) & MIDR_PART_MASK; +// revision = tmp & MIDR_REV_MASK; + +#define MIDR_PART_CA5 0xC05 +#define MIDR_PART_CA8 0xC08 +#define MIDR_PART_CA9 0xC09 + +unsigned int getMPIDR(void); + +#define MPIDR_FORMAT_SHIFT 31 +#define MPIDR_FORMAT_MASK 0x1 +#define MPIDR_UBIT_SHIFT 30 +#define MPIDR_UBIT_MASK 0x1 +#define MPIDR_CLUSTER_SHIFT 7 +#define MPIDR_CLUSTER_MASK 0xF +#define MPIDR_CPUID_SHIFT 0 +#define MPIDR_CPUID_MASK 0x3 + +#define MPIDR_CPUID_CPU0 0x0 +#define MPIDR_CPUID_CPU1 0x1 +#define MPIDR_CPUID_CPU2 0x2 +#define MPIDR_CPUID_CPU3 0x3 + +#define MPIDR_UNIPROCESSPR 0x1 + +#define MPDIR_NEW_FORMAT 0x1 + +// ------------------------------------------------------------ +// Context ID + +unsigned int getContextID(void); + +void setContextID(unsigned int); + +#define CONTEXTID_ASID_SHIFT 0 +#define CONTEXTID_ASID_MASK 0xFF +#define CONTEXTID_PROCID_SHIFT 8 +#define CONTEXTID_PROCID_MASK 0x00FFFFFF + +// tmp = getContextID(); +// ASID = tmp & CONTEXTID_ASID_MASK; +// PROCID = (tmp >> CONTEXTID_PROCID_SHIFT) & CONTEXTID_PROCID_MASK; + +// ------------------------------------------------------------ +// SMP related for Armv7-A MPCore processors +// +// DO NOT CALL THESE FUNCTIONS ON A CORTEX-A8 + +// Returns the base address of the private peripheral memory space +unsigned int getBaseAddr(void); + +// Returns the CPU ID (0 to 3) of the CPU executed on +#define MP_CPU0 (0) +#define MP_CPU1 (1) +#define MP_CPU2 (2) +#define MP_CPU3 (3) +unsigned int getCPUID(void); + +// Set this core as participating in SMP +void joinSMP(void); + +// Set this core as NOT participating in SMP +void leaveSMP(void); + +// Go to sleep, never returns +void goToSleep(void); + +#endif + +// ------------------------------------------------------------ +// End of v7.h +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a5_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a5_smp/gnu/inc/tx_port.h new file mode 100644 index 00000000..f5324045 --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/inc/tx_port.h @@ -0,0 +1,409 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h SMP/Cortex-A5/GNU */ +/* 6.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/************* Define ThreadX SMP constants. *************/ + +/* Define the ThreadX SMP maximum number of cores. */ + +#ifndef TX_THREAD_SMP_MAX_CORES +#define TX_THREAD_SMP_MAX_CORES 2 +#endif + + +/* Define the ThreadX SMP core mask. */ + +#ifndef TX_THREAD_SMP_CORE_MASK +#define TX_THREAD_SMP_CORE_MASK 0x3 /* Where bit 0 represents Core 0, bit 1 represents Core 1, etc. */ +#endif + + +/* Define INLINE_DECLARE to whitespace for ARM compiler. */ + +#define INLINE_DECLARE + + +/* Define ThreadX SMP initialization macro. */ + +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION + + +/* Define ThreadX SMP pre-scheduler initialization. */ + +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION + + +/* Enable the inter-core interrupt logic. */ + +#define TX_THREAD_SMP_INTER_CORE_INTERRUPT + + +/* Determine if there is customer-specific wakeup logic needed. */ + +#ifdef TX_THREAD_SMP_WAKEUP_LOGIC + +/* Include customer-specific wakeup code. */ + +#include "tx_thread_smp_core_wakeup.h" +#else + +#ifdef TX_THREAD_SMP_DEFAULT_WAKEUP_LOGIC + +/* Default wakeup code. */ +#define TX_THREAD_SMP_WAKEUP_LOGIC +#define TX_THREAD_SMP_WAKEUP(i) _tx_thread_smp_core_preempt(i) +#endif +#endif + + +/* Ensure that the in-line resume/suspend define is not allowed. */ + +#ifdef TX_INLINE_THREAD_RESUME_SUSPEND +#undef TX_INLINE_THREAD_RESUME_SUSPEND +#endif + + +/************* End ThreadX SMP constants. *************/ + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE _tx_thread_smp_time_get() +#endif +#else +#ifndef TX_TRACE_TIME_SOURCE +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#if __TARGET_ARCH_ARM > 4 + +#ifndef __thumb__ + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + asm volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); \ + b = 31 - b; +#endif +#endif +#endif + + +/************* Define ThreadX SMP data types and function prototypes. *************/ + +struct TX_THREAD_STRUCT; + + +/* Define the ThreadX SMP protection structure. */ + +typedef struct TX_THREAD_SMP_PROTECT_STRUCT +{ + ULONG tx_thread_smp_protect_in_force; + struct TX_THREAD_STRUCT * + tx_thread_smp_protect_thread; + ULONG tx_thread_smp_protect_core; + ULONG tx_thread_smp_protect_count; + + /* Implementation specific information follows. */ + + ULONG tx_thread_smp_protect_get_caller; + ULONG tx_thread_smp_protect_sr; + ULONG tx_thread_smp_protect_release_caller; +} TX_THREAD_SMP_PROTECT; + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_smp_protect(); +#define TX_RESTORE _tx_thread_smp_unprotect(interrupt_save); + + +/************* End ThreadX SMP data type and function prototype definitions. *************/ + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define VFP extension for the Cortex-A5. Each is assumed to be called in the context of the executing + thread. */ + +void tx_thread_vfp_enable(void); +void tx_thread_vfp_disable(void); + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Cortex-A5/GNU Version 6.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + + + diff --git a/ports_smp/cortex_a5_smp/gnu/readme_threadx.txt b/ports_smp/cortex_a5_smp/gnu/readme_threadx.txt new file mode 100644 index 00000000..4495a618 --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/readme_threadx.txt @@ -0,0 +1,343 @@ + Microsoft's Azure RTOS ThreadX SMP for Cortex-A5 + + Using the GNU Tools + +1. Building the ThreadX run-time Library + +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the GNU +development environment. + +At this point you may run the build_threadx.bat batch file. This will build the +ThreadX run-time environment in the "example_build" directory. + +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your +application in order to use ThreadX. + + +2. Demonstration System + +The ThreadX demonstration is designed to execute under the ARM Cortex-A5x4 FVP. + +Building the demonstration is easy; simply execute the build_threadx_sample.bat +batch file while inside the "example_build" directory. + +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with TX.A. The resulting file DEMO is a binary file +that can be downloaded and executed. + + +3. System Initialization + +The entry point in ThreadX for the Cortex-A5 using GNU tools is at label +Reset_Handler in startup.s. After the basic core initialization is complete, +control will transfer to __main, which is where all static and global pre-set +C variable initialization processing takes place. + +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. By default, the vector area is defined to be located in the Init area, +which is defined at the top of tx_initialize_low_level.s. This area is typically +located at 0. In situations where this is impossible, the vectors at the beginning +of the Init area should be copied to address 0. + +This is also where initialization of a periodic timer interrupt source +should take place. + +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input +parameter to your application definition function, tx_application_define. + + +4. Register Usage and Stack Frames + +The GNU compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread +is only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 CPSR CPSR + 0x08 r0 (a1) r4 (v1) + 0x0C r1 (a2) r5 (v2) + 0x10 r2 (a3) r6 (v3) + 0x14 r3 (a4) r7 (v4) + 0x18 r4 (v1) r8 (v5) + 0x1C r5 (v2) r9 (v6) + 0x20 r6 (v3) r10 (v7) + 0x24 r7 (v4) r11 (fp) + 0x28 r8 (v5) r14 (lr) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) + 0x3C r14 (lr) + 0x40 PC + + +5. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the build_threadx.bat file to +remove the -g option and enable all compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +6. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-A5 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +6.1 Vector Area + +The Cortex-A5 vectors start at address zero. The demonstration system startup +Init area contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. + + +6.2 IRQ ISRs + +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested +IRQ interrupts. The following sub-sections define the IRQ capabilities. + + +6.2.1 Standard IRQ ISRs + +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +is the default IRQ handler defined in tx_initialize_low_level.s: + + EXPORT __tx_irq_handler + EXPORT __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save ; Jump to the context save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Application ISR call(s) go here! */ +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +6.2.2 Vectored IRQ ISRs + +The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified +by the particular implementation. The following is an example IRQ handler defined in +tx_initialize_low_level.s: + + EXPORT __tx_irq_example_handler +__tx_irq_example_handler +; +; /* Call context save to save system context. */ + + STMDB sp!, {r0-r3} ; Save some scratch registers + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers + BL _tx_thread_vectored_context_save ; Call the vectored IRQ context save +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Application ISR call goes here! */ +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +6.2.3 Nested IRQ Support + +By default, nested IRQ interrupt support is not enabled. To enable nested +IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING +defined. With this defined, two new IRQ interrupt management services are +available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. +These function should be called between the IRQ context save and restore +calls. + +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +by switching from IRQ mode to SYS mode and enabling IRQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested IRQ interrupts are no longer required, +calling the _tx_thread_irq_nesting_end service disables nesting by disabling +IRQ interrupts and switching back to IRQ mode in preparation for the IRQ +context restore service. + +The following is an example of enabling IRQ nested interrupts in a standard +IRQ handler: + + EXPORT __tx_irq_handler + EXPORT __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return +; +; /* Enable nested IRQ interrupts. NOTE: Since this service returns +; with IRQ interrupts enabled, all IRQ interrupt sources must be +; cleared prior to calling this service. */ + BL _tx_thread_irq_nesting_start +; +; /* Application ISR call(s) go here! */ +; +; /* Disable nested IRQ interrupts. The mode is switched back to +; IRQ mode and IRQ interrupts are disable upon return. */ + BL _tx_thread_irq_nesting_end +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +6.3 FIQ Interrupts + +By default, Cortex-A5 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made +from default FIQ ISRs, which is located in tx_initialize_low_level.s. + + +6.3.1 Managed FIQ Interrupts + +Full ThreadX management of FIQ interrupts is provided if the ThreadX sources +are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built +this way, the FIQ interrupt handlers are very similar to the IRQ interrupt +handlers defined previously. The following is default FIQ handler +defined in tx_initialize_low_level.s: + + + EXPORT __tx_fiq_handler + EXPORT __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Application FIQ handlers can be called here! */ +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +6.3.1.1 Nested FIQ Support + +By default, nested FIQ interrupt support is not enabled. To enable nested +FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING +defined. With this defined, two new FIQ interrupt management services are +available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. +These function should be called between the FIQ context save and restore +calls. + +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +by switching from FIQ mode to SYS mode and enabling FIQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested FIQ interrupts are no longer required, +calling the _tx_thread_fiq_nesting_end service disables nesting by disabling +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +context restore service. + +The following is an example of enabling FIQ nested interrupts in the +typical FIQ handler: + + + EXPORT __tx_fiq_handler + EXPORT __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Enable nested FIQ interrupts. NOTE: Since this service returns +; with FIQ interrupts enabled, all FIQ interrupt sources must be +; cleared prior to calling this service. */ + BL _tx_thread_fiq_nesting_start +; +; /* Application FIQ handlers can be called here! */ +; +; /* Disable nested FIQ interrupts. The mode is switched back to +; FIQ mode and FIQ interrupts are disable upon return. */ + BL _tx_thread_fiq_nesting_end +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +7. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional. However, all other +ThreadX services are operational without a periodic timer source. + +To add the timer interrupt processing, simply make a call to +_tx_timer_interrupt in the IRQ processing. An example of this can be +found in the file tx_initialize_low_level.s in the Integrator sub-directories. + + +8. VFP Support + +VFP support is optional, it can be enabled by building the ThreadX library +assembly code with the following command-line option: + +-mfpu=neon -DTARGET_FPU_VFP + +Note that if ISRs need to use VFP registers, their contents much be saved +before their use and restored after. + + +9. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +09-30-2020 Initial ThreadX 6.1 version for Cortex-A5 using GNU tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_context_restore.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_context_restore.S new file mode 100644 index 00000000..519596ab --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_context_restore.S @@ -0,0 +1,372 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@/* Include macros for modifying the wait list. */ +#include "tx_thread_smp_protection_wait_list_macros.h" + +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS = 0xC0 @ Disable IRQ & FIQ interrupts +IRQ_MODE = 0xD2 @ IRQ mode +SVC_MODE = 0xD3 @ SVC mode +#else +DISABLE_INTS = 0x80 @ Disable IRQ interrupts +IRQ_MODE = 0x92 @ IRQ mode +SVC_MODE = 0x93 @ SVC mode +#endif +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable + .global _tx_timer_interrupt_active + .global _tx_thread_smp_protection + .global _tx_thread_smp_protect_wait_counts + .global _tx_thread_smp_protect_wait_list + .global _tx_thread_smp_protect_wait_list_lock_protect_in_force + .global _tx_thread_smp_protect_wait_list_tail + .global _tx_thread_smp_protect_wait_list_size +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + .global _tx_execution_isr_exit +#endif +@ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_restore SMP/Cortex-A5/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function restores the interrupt context if it is processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs Interrupt Service Routines */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_restore(VOID) +@{ + .global _tx_thread_context_restore + .type _tx_thread_context_restore,function +_tx_thread_context_restore: +@ +@ /* Lockout interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR exit function to indicate an ISR is complete. */ +@ + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif + +@ /* Pickup the CPU ID. */ +@ + MRC p15, 0, r10, c0, c0, 5 @ Read CPU ID register + AND r10, r10, #0x03 @ Mask off, leaving the CPU ID field + LSL r12, r10, #2 @ Build offset to array indexes +@ +@ /* Determine if interrupts are nested. */ +@ if (--_tx_thread_system_state[core]) +@ { +@ + LDR r3, =_tx_thread_system_state @ Pickup address of system state var + ADD r3, r3, r12 @ Build array offset + LDR r2, [r3, #0] @ Pickup system state + SUB r2, r2, #1 @ Decrement the counter + STR r2, [r3, #0] @ Store the counter + CMP r2, #0 @ Was this the first interrupt? + BEQ __tx_thread_not_nested_restore @ If so, not a nested restore +@ +@ /* Interrupts are nested. */ +@ +@ /* Just recover the saved registers and return to the point of +@ interrupt. */ +@ + LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +__tx_thread_not_nested_restore: +@ +@ /* Determine if a thread was interrupted and no preemption is required. */ +@ else if (((_tx_thread_current_ptr[core]) && (_tx_thread_current_ptr[core] == _tx_thread_execute_ptr[core]) +@ || (_tx_thread_preempt_disable)) +@ { +@ + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + ADD r1, r1, r12 @ Build index to this core's current thread ptr + LDR r0, [r1, #0] @ Pickup actual current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_restore @ Yes, idle system was interrupted +@ + LDR r3, =_tx_thread_smp_protection @ Get address of protection structure + LDR r2, [r3, #8] @ Pickup owning core + CMP r2, r10 @ Is the owning core the same as the protected core? + BNE __tx_thread_skip_preempt_check @ No, skip the preempt disable check since this is only valid for the owning core + + LDR r3, =_tx_thread_preempt_disable @ Pickup preempt disable address + LDR r2, [r3, #0] @ Pickup actual preempt disable flag + CMP r2, #0 @ Is it set? + BNE __tx_thread_no_preempt_restore @ Yes, don't preempt this thread +__tx_thread_skip_preempt_check: + + LDR r3, =_tx_thread_execute_ptr @ Pickup address of execute thread ptr + ADD r3, r3, r12 @ Build index to this core's execute thread ptr + LDR r2, [r3, #0] @ Pickup actual execute thread pointer + CMP r0, r2 @ Is the same thread highest priority? + BNE __tx_thread_preempt_restore @ No, preemption needs to happen +@ +@ +__tx_thread_no_preempt_restore: +@ +@ /* Restore interrupted thread or ISR. */ +@ +@ /* Pickup the saved stack pointer. */ +@ tmp_ptr = _tx_thread_current_ptr[core] -> tx_thread_stack_ptr; +@ +@ /* Recover the saved context and return to the point of interrupt. */ +@ + LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +@ else +@ { +@ +__tx_thread_preempt_restore: +@ +@ /* Was the thread being preempted waiting for the lock? */ +@ if (_tx_thread_smp_protect_wait_counts[this_core] != 0) +@ { +@ + LDR r1, =_tx_thread_smp_protect_wait_counts @ Load waiting count list + LDR r2, [r1, r10, LSL #2] @ Load waiting value for this core + CMP r2, #0 + BEQ _nobody_waiting_for_lock @ Is the core waiting for the lock? +@ +@ /* Do we not have the lock? This means the ISR never got the inter-core lock. */ +@ if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core) +@ { +@ + LDR r1, =_tx_thread_smp_protection @ Load address of protection structure + LDR r2, [r1, #8] @ Pickup the owning core + CMP r10, r2 @ Compare our core to the owning core + BEQ _this_core_has_lock @ Do we have the lock? +@ +@ /* We don't have the lock. This core should be in the list. Remove it. */ +@ _tx_thread_smp_protect_wait_list_remove(this_core); +@ + MOV r0, r10 @ Move the core ID to r0 for the macro + _tx_thread_smp_protect_wait_list_remove @ Call macro to remove core from the list + B _nobody_waiting_for_lock @ Leave +@ +@ } +@ else +@ { +@ /* We have the lock. This means the ISR got the inter-core lock, but +@ never released it because it saw that there was someone waiting. +@ Note this core is not in the list. */ +@ +_this_core_has_lock: +@ +@ /* We're no longer waiting. Note that this should be zero since this happens during thread preemption. */ +@ _tx_thread_smp_protect_wait_counts[core]--; +@ + LDR r1, =_tx_thread_smp_protect_wait_counts @ Load waiting count list + LDR r2, [r1, r10, LSL #2] @ Load waiting value for this core + SUB r2, r2, #1 @ Decrement waiting value. Should be zero now + STR r2, [r1, r10, LSL #2] @ Store new waiting value +@ +@ /* Now release the inter-core lock. */ +@ +@ /* Set protected core as invalid. */ +@ _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF; +@ + LDR r1, =_tx_thread_smp_protection @ Load address of protection structure + MOV r2, #0xFFFFFFFF @ Build invalid value + STR r2, [r1, #8] @ Mark the protected core as invalid + DMB @ Ensure that accesses to shared resource have completed +@ +@ /* Release protection. */ +@ _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0; +@ + MOV r2, #0 @ Build release protection value + STR r2, [r1, #0] @ Release the protection + DSB ISH @ To ensure update of the protection occurs before other CPUs awake +@ +@ /* Wake up waiting processors. Note interrupts are already enabled. */ +@ +#ifdef TX_ENABLE_WFE + SEV @ Send event to other CPUs +#endif +@ +@ } +@ } +@ + +_nobody_waiting_for_lock: + + LDMIA sp!, {r3, r10, r12, lr} @ Recover temporarily saved registers + MOV r1, lr @ Save lr (point of interrupt) + MOV r2, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r2 @ Enter SVC mode + STR r1, [sp, #-4]! @ Save point of interrupt + STMDB sp!, {r4-r12, lr} @ Save upper half of registers + MOV r4, r3 @ Save SPSR in r4 + MOV r2, #IRQ_MODE @ Build IRQ mode CPSR + MSR CPSR_c, r2 @ Enter IRQ mode + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOV r5, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r5 @ Enter SVC mode + STMDB sp!, {r0-r3} @ Save r0-r3 on thread's stack + + MRC p15, 0, r10, c0, c0, 5 @ Read CPU ID register + AND r10, r10, #0x03 @ Mask off, leaving the CPU ID field + LSL r12, r10, #2 @ Build offset to array indexes + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + ADD r1, r1, r12 @ Build index to current thread ptr + LDR r0, [r1, #0] @ Pickup current thread pointer + +#ifdef TARGET_FPU_VFP + LDR r2, [r0, #160] @ Pickup the VFP enabled flag + CMP r2, #0 @ Is the VFP enabled? + BEQ _tx_skip_irq_vfp_save @ No, skip VFP IRQ save + VMRS r2, FPSCR @ Pickup the FPSCR + STR r2, [sp, #-4]! @ Save FPSCR + VSTMDB sp!, {D16-D31} @ Save D16-D31 + VSTMDB sp!, {D0-D15} @ Save D0-D15 +_tx_skip_irq_vfp_save: +#endif + + MOV r3, #1 @ Build interrupt stack type + STMDB sp!, {r3, r4} @ Save interrupt stack type and SPSR + STR sp, [r0, #8] @ Save stack pointer in thread control + @ block +@ +@ /* Save the remaining time-slice and disable it. */ +@ if (_tx_timer_time_slice[core]) +@ { +@ + LDR r3, =_tx_timer_interrupt_active @ Pickup timer interrupt active flag's address +_tx_wait_for_timer_to_finish: + LDR r2, [r3, #0] @ Pickup timer interrupt active flag + CMP r2, #0 @ Is the timer interrupt active? + BNE _tx_wait_for_timer_to_finish @ If timer interrupt is active, wait until it completes + + LDR r3, =_tx_timer_time_slice @ Pickup time-slice variable address + ADD r3, r3, r12 @ Build index to core's time slice + LDR r2, [r3, #0] @ Pickup time-slice + CMP r2, #0 @ Is it active? + BEQ __tx_thread_dont_save_ts @ No, don't save it +@ +@ _tx_thread_current_ptr[core] -> tx_thread_time_slice = _tx_timer_time_slice[core]; +@ _tx_timer_time_slice[core] = 0; +@ + STR r2, [r0, #24] @ Save thread's time-slice + MOV r2, #0 @ Clear value + STR r2, [r3, #0] @ Disable global time-slice flag +@ +@ } +__tx_thread_dont_save_ts: +@ +@ +@ /* Clear the current task pointer. */ +@ _tx_thread_current_ptr[core] = TX_NULL; +@ + MOV r2, #0 @ NULL value + STR r2, [r1, #0] @ Clear current thread pointer +@ +@ /* Set bit indicating this thread is ready for execution. */ +@ + LDR r2, [r0, #152] @ Pickup the ready bit + ORR r2, r2, #0x8000 @ Set ready bit (bit 15) + STR r2, [r0, #152] @ Make this thread ready for executing again + DMB @ Ensure that accesses to shared resource have completed +@ +@ /* Return to the scheduler. */ +@ _tx_thread_schedule(); +@ + B _tx_thread_schedule @ Return to scheduler +@ } +@ +__tx_thread_idle_system_restore: +@ +@ /* Just return back to the scheduler! */ +@ + MOV r3, #SVC_MODE @ Build SVC mode with interrupts disabled + MSR CPSR_c, r3 @ Change to SVC mode + B _tx_thread_schedule @ Return to scheduler +@} +@ + diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_context_save.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_context_save.S new file mode 100644 index 00000000..71a93419 --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_context_save.S @@ -0,0 +1,204 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global __tx_irq_processing_return +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + .global _tx_execution_isr_enter +#endif +@ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_save SMP/Cortex-A5/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_save(VOID) +@{ + .global _tx_thread_context_save + .type _tx_thread_context_save,function +_tx_thread_context_save: +@ +@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +@ out, we are in IRQ mode, and all registers are intact. */ +@ +@ /* Check for a nested interrupt condition. */ +@ if (_tx_thread_system_state[core]++) +@ { +@ + STMDB sp!, {r0-r3} @ Save some working registers +@ +@ /* Save the rest of the scratch registers on the stack and return to the +@ calling ISR. */ +@ + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} @ Store other registers +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable FIQ interrupts +#endif +@ +@ /* Pickup the CPU ID. */ +@ + MRC p15, 0, r10, c0, c0, 5 @ Read CPU ID register + AND r10, r10, #0x03 @ Mask off, leaving the CPU ID field + LSL r12, r10, #2 @ Build offset to array indexes +@ + LDR r3, =_tx_thread_system_state @ Pickup address of system state var + ADD r3, r3, r12 @ Build index into the system state array + LDR r2, [r3, #0] @ Pickup system state + CMP r2, #0 @ Is this the first interrupt? + BEQ __tx_thread_not_nested_save @ Yes, not a nested context save +@ +@ /* Nested interrupt condition. */ +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3, #0] @ Store it back in the variable +@ +@ /* Return to the ISR. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {r12, lr} @ Save ISR lr & r12 + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {r12, lr} @ Recover ISR lr & r12 +#endif + + B __tx_irq_processing_return @ Continue IRQ processing +@ +__tx_thread_not_nested_save: +@ } +@ +@ /* Otherwise, not nested, check to see if a thread was running. */ +@ else if (_tx_thread_current_ptr[core]) +@ { +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3, #0] @ Store it back in the variable + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + ADD r1, r1, r12 @ Build index into current thread ptr + LDR r0, [r1, #0] @ Pickup current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + @ scheduling loop - nothing needs saving! +@ +@ /* Save the current stack pointer in the thread's control block. */ +@ _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; +@ +@ /* Switch to the system stack. */ +@ sp = _tx_thread_system_stack_ptr; +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {r12, lr} @ Save ISR lr & r12 + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {r12, lr} @ Recover ISR lr & r12 +#endif + + B __tx_irq_processing_return @ Continue IRQ processing +@ +@ } +@ else +@ { +@ +__tx_thread_idle_system_save: +@ +@ /* Interrupt occurred in the scheduling loop. */ +@ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ processing. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {r12, lr} @ Save ISR lr & r12 + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {r12, lr} @ Recover ISR lr & r12 +#endif + + ADD sp, sp, #32 @ Recover saved registers + B __tx_irq_processing_return @ Continue IRQ processing +@ +@ } +@} +@ + diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..697b9380 --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_interrupt_control.S @@ -0,0 +1,104 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT +INT_MASK = 0xC0 @ Interrupt bit mask +#else +INT_MASK = 0x80 @ Interrupt bit mask +#endif +@ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_control SMP/Cortex-A5/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for changing the interrupt lockout */ +@/* posture of the system. */ +@/* */ +@/* INPUT */ +@/* */ +@/* new_posture New interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_control(UINT new_posture) +@{ + .global _tx_thread_interrupt_control + .type _tx_thread_interrupt_control,function +_tx_thread_interrupt_control: +@ +@ /* Pickup current interrupt lockout posture. */ +@ + MRS r3, CPSR @ Pickup current CPSR + BIC r1, r3, #INT_MASK @ Clear interrupt lockout bits + ORR r1, r1, r0 @ Or-in new interrupt lockout bits +@ +@ /* Apply the new interrupt posture. */ +@ + MSR CPSR_c, r1 @ Setup new CPSR + AND r0, r3, #INT_MASK @ Return previous interrupt mask +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@ +@} +@ + diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_interrupt_disable.S new file mode 100644 index 00000000..6e5a08cd --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_interrupt_disable.S @@ -0,0 +1,97 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_disable SMP/Cortex-A5/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for disabling interrupts */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_disable(void) +@{ + .global _tx_thread_interrupt_disable + .type _tx_thread_interrupt_disable,function +_tx_thread_interrupt_disable: +@ +@ /* Pickup current interrupt lockout posture. */ +@ + MRS r0, CPSR @ Pickup current CPSR +@ +@ /* Mask interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ +#else + CPSID i @ Disable IRQ +#endif + +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} +@ + diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_interrupt_restore.S new file mode 100644 index 00000000..a1b622f5 --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_interrupt_restore.S @@ -0,0 +1,89 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_restore SMP/Cortex-A5/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for restoring interrupts to the state */ +@/* returned by a previous _tx_thread_interrupt_disable call. */ +@/* */ +@/* INPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_restore(UINT old_posture) +@{ + .global _tx_thread_interrupt_restore + .type _tx_thread_interrupt_restore,function +_tx_thread_interrupt_restore: +@ +@ /* Apply the new interrupt posture. */ +@ + MSR CPSR_c, r0 @ Setup new CPSR +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} +@ + diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_irq_nesting_end.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_irq_nesting_end.S new file mode 100644 index 00000000..258ff227 --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_irq_nesting_end.S @@ -0,0 +1,112 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS = 0xC0 @ Disable IRQ & FIQ interrupts +#else +DISABLE_INTS = 0x80 @ Disable IRQ interrupts +#endif +MODE_MASK = 0x1F @ Mode mask +IRQ_MODE_BITS = 0x12 @ IRQ mode bits +@ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_end SMP/Cortex-A5/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +@/* processing from system mode back to IRQ mode prior to the ISR */ +@/* calling _tx_thread_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_irq_nesting_end(VOID) +@{ + .global _tx_thread_irq_nesting_end + .type _tx_thread_irq_nesting_end,function +_tx_thread_irq_nesting_end: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value + MSR CPSR_c, r0 @ Disable interrupts + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + @ 8-byte alignment logic) + BIC r0, r0, #MODE_MASK @ Clear mode bits + ORR r0, r0, #IRQ_MODE_BITS @ Build IRQ mode CPSR + MSR CPSR_c, r0 @ Re-enter IRQ mode +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_irq_nesting_start.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_irq_nesting_start.S new file mode 100644 index 00000000..2a20b0c1 --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_irq_nesting_start.S @@ -0,0 +1,106 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +IRQ_DISABLE = 0x80 @ IRQ disable bit +MODE_MASK = 0x1F @ Mode mask +SYS_MODE_BITS = 0x1F @ System mode bits +@ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_start SMP/Cortex-A5/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_context_save has been called and switches the IRQ */ +@/* processing to the system mode so nested IRQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_irq_nesting_start(VOID) +@{ + .global _tx_thread_irq_nesting_start + .type _tx_thread_irq_nesting_start,function +_tx_thread_irq_nesting_start: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + BIC r0, r0, #MODE_MASK @ Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS @ Build system mode CPSR + MSR CPSR_c, r0 @ Enter system mode + STMDB sp!, {r1, lr} @ Push the system mode lr on the system mode stack + @ and push r1 just to keep 8-byte alignment + BIC r0, r0, #IRQ_DISABLE @ Build enable IRQ CPSR + MSR CPSR_c, r0 @ Enter system mode +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} +@ + diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_schedule.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_schedule.S new file mode 100644 index 00000000..c3c092ad --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_schedule.S @@ -0,0 +1,315 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_execute_ptr + .global _tx_thread_current_ptr + .global _tx_timer_time_slice +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + .global _tx_execution_thread_enter +#endif +@ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_schedule SMP/Cortex-A5/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function waits for a thread control block pointer to appear in */ +@/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +@/* in the variable, the corresponding thread is resumed. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* _tx_thread_system_return Return to system from thread */ +@/* _tx_thread_context_restore Restore thread's context */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_schedule(VOID) +@{ + .global _tx_thread_schedule + .type _tx_thread_schedule,function +_tx_thread_schedule: +@ +@ /* Enable interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSIE if @ Enable IRQ and FIQ interrupts +#else + CPSIE i @ Enable IRQ interrupts +#endif +@ +@ /* Pickup the CPU ID. */ +@ + MRC p15, 0, r10, c0, c0, 5 @ Read CPU ID register + AND r10, r10, #0x03 @ Mask off, leaving the CPU ID field + LSL r12, r10, #2 @ Build offset to array indexes + + LDR r1, =_tx_thread_execute_ptr @ Address of thread execute ptr + ADD r1, r1, r12 @ Build offset to execute ptr for this core +@ +@ /* Lockout interrupts transfer control to it. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif +@ +@ /* Wait for a thread to execute. */ +@ do +@ { +@ +@ + LDR r0, [r1, #0] @ Pickup next thread to execute + CMP r0, #0 @ Is it NULL? + BEQ _tx_thread_schedule @ If so, keep looking for a thread +@ +@ } +@ while(_tx_thread_execute_ptr[core] == TX_NULL); +@ +@ +@ /* Get the lock for accessing the thread's ready bit. */ +@ + MOV r2, #172 @ Build offset to the lock + ADD r2, r0, r2 @ Get the address to the lock + LDREX r3, [r2] @ Pickup the lock value + CMP r3, #0 @ Check if it's available + BNE _tx_thread_schedule @ No, lock not available + MOV r3, #1 @ Build the lock set value + STREX r4, r3, [r2] @ Try to get the lock + CMP r4, #0 @ Check if we got the lock + BNE _tx_thread_schedule @ No, another core got it first + DMB @ Ensure write to lock completes +@ +@ /* Now make sure the thread's ready bit is set. */ +@ + LDR r3, [r0, #152] @ Pickup the thread ready bit + AND r4, r3, #0x8000 @ Isolate the ready bit + CMP r4, #0 @ Is it set? + BNE _tx_thread_ready_for_execution @ Yes, schedule the thread +@ +@ /* The ready bit isn't set. Release the lock and jump back to the scheduler. */ +@ + MOV r3, #0 @ Build clear value + STR r3, [r2] @ Release the lock + DMB @ Ensure write to lock completes + B _tx_thread_schedule @ Jump back to the scheduler +@ +_tx_thread_ready_for_execution: +@ +@ /* We have a thread to execute. */ +@ +@ /* Clear the ready bit and release the lock. */ +@ + BIC r3, r3, #0x8000 @ Clear ready bit + STR r3, [r0, #152] @ Store it back in the thread control block + DMB + MOV r3, #0 @ Build clear value for the lock + STR r3, [r2] @ Release the lock + DMB +@ +@ /* Setup the current thread pointer. */ +@ _tx_thread_current_ptr[core] = _tx_thread_execute_ptr[core]; +@ + LDR r2, =_tx_thread_current_ptr @ Pickup address of current thread + ADD r2, r2, r12 @ Build index into the current thread array + STR r0, [r2, #0] @ Setup current thread pointer +@ +@ /* In the time between reading the execute pointer and assigning +@ it to the current pointer, the execute pointer was changed by +@ some external code. If the current pointer was still null when +@ the external code checked if a core preempt was necessary, then +@ it wouldn't have done it and a preemption will be missed. To +@ handle this, undo some things and jump back to the scheduler so +@ it can schedule the new thread. */ +@ + LDR r1, [r1, #0] @ Reload the execute pointer + CMP r0, r1 @ Did it change? + BEQ _execute_pointer_did_not_change @ If not, skip handling + + MOV r1, #0 @ Build clear value + STR r1, [r2, #0] @ Clear current thread pointer + + LDR r1, [r0, #152] @ Pickup the ready bit + ORR r1, r1, #0x8000 @ Set ready bit (bit 15) + STR r1, [r0, #152] @ Make this thread ready for executing again + DMB @ Ensure that accesses to shared resource have completed + + B _tx_thread_schedule @ Jump back to the scheduler to schedule the new thread + +_execute_pointer_did_not_change: +@ /* Increment the run count for this thread. */ +@ _tx_thread_current_ptr[core] -> tx_thread_run_count++; +@ + LDR r2, [r0, #4] @ Pickup run counter + LDR r3, [r0, #24] @ Pickup time-slice for this thread + ADD r2, r2, #1 @ Increment thread run-counter + STR r2, [r0, #4] @ Store the new run counter +@ +@ /* Setup time-slice, if present. */ +@ _tx_timer_time_slice[core] = _tx_thread_current_ptr[core] -> tx_thread_time_slice; +@ + LDR r2, =_tx_timer_time_slice @ Pickup address of time slice + @ variable + ADD r2, r2, r12 @ Build index into the time-slice array + LDR sp, [r0, #8] @ Switch stack pointers + STR r3, [r2, #0] @ Setup time-slice +@ +@ /* Switch to the thread's stack. */ +@ sp = _tx_thread_execute_ptr[core] -> tx_thread_stack_ptr; +@ +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the thread entry function to indicate the thread is executing. */ +@ + MOV r5, r0 @ Save r0 + BL _tx_execution_thread_enter @ Call the thread execution enter function + MOV r0, r5 @ Restore r0 +#endif +@ +@ /* Determine if an interrupt frame or a synchronous task suspension frame +@ is present. */ +@ + LDMIA sp!, {r4, r5} @ Pickup the stack type and saved CPSR + CMP r4, #0 @ Check for synchronous context switch + BEQ _tx_solicited_return + MSR SPSR_cxsf, r5 @ Setup SPSR for return +#ifdef TARGET_FPU_VFP + LDR r1, [r0, #160] @ Pickup the VFP enabled flag + CMP r1, #0 @ Is the VFP enabled? + BEQ _tx_skip_interrupt_vfp_restore @ No, skip VFP interrupt restore + VLDMIA sp!, {D0-D15} @ Recover D0-D15 + VLDMIA sp!, {D16-D31} @ Recover D16-D31 + LDR r4, [sp], #4 @ Pickup FPSCR + VMSR FPSCR, r4 @ Restore FPSCR +_tx_skip_interrupt_vfp_restore: +#endif + LDMIA sp!, {r0-r12, lr, pc}^ @ Return to point of thread interrupt + +_tx_solicited_return: +#ifdef TARGET_FPU_VFP + MSR CPSR_cxsf, r5 @ Recover CPSR + LDR r1, [r0, #160] @ Pickup the VFP enabled flag + CMP r1, #0 @ Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_restore @ No, skip VFP solicited restore + VLDMIA sp!, {D8-D15} @ Recover D8-D15 + VLDMIA sp!, {D16-D31} @ Recover D16-D31 + LDR r4, [sp], #4 @ Pickup FPSCR + VMSR FPSCR, r4 @ Restore FPSCR +_tx_skip_solicited_vfp_restore: +#endif + MSR CPSR_cxsf, r5 @ Recover CPSR + LDMIA sp!, {r4-r11, lr} @ Return to thread synchronously + BX lr @ Return to caller +@ +@} +@ + +#ifdef TARGET_FPU_VFP + .global tx_thread_vfp_enable +tx_thread_vfp_enable: + MRS r2, CPSR @ Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif + MRC p15, 0, r1, c0, c0, 5 @ Read CPU ID register + AND r1, r1, #0x03 @ Mask off, leaving the CPU ID field + LSL r1, r1, #2 @ Build offset to array indexes + LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address + ADD r0, r0, r1 @ Build index into the current thread array + LDR r1, [r0] @ Pickup current thread pointer + CMP r1, #0 @ Check for NULL thread pointer + BEQ __tx_no_thread_to_enable @ If NULL, skip VFP enable + MOV r0, #1 @ Build enable value + STR r0, [r1, #160] @ Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_enable: + MSR CPSR_cxsf, r2 @ Recover CPSR + BX LR @ Return to caller + + .global tx_thread_vfp_disable +tx_thread_vfp_disable: + MRS r2, CPSR @ Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif + MRC p15, 0, r1, c0, c0, 5 @ Read CPU ID register + AND r1, r1, #0x03 @ Mask off, leaving the CPU ID field + LSL r1, r1, #2 @ Build offset to array indexes + LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address + ADD r0, r0, r1 @ Build index into the current thread array + LDR r1, [r0] @ Pickup current thread pointer + CMP r1, #0 @ Check for NULL thread pointer + BEQ __tx_no_thread_to_disable @ If NULL, skip VFP disable + MOV r0, #0 @ Build disable value + STR r0, [r1, #160] @ Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_disable: + MSR CPSR_cxsf, r2 @ Recover CPSR + BX LR @ Return to caller +#endif +@ +@} +@ + diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_core_get.S new file mode 100644 index 00000000..23d940d6 --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_core_get.S @@ -0,0 +1,86 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread - Low Level SMP Support */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@#define TX_THREAD_SMP_SOURCE_CODE +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" */ +@ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_core_get SMP/Cortex-A5/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function gets the currently running core number and returns it.*/ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* Core ID */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Source */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ + .global _tx_thread_smp_core_get + .type _tx_thread_smp_core_get,function +_tx_thread_smp_core_get: + MRC p15, 0, r0, c0, c0, 5 @ Read CPU ID register + AND r0, r0, #0x03 @ Mask off, leaving the CPU ID field + +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif + + diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_core_preempt.S new file mode 100644 index 00000000..4b614309 --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_core_preempt.S @@ -0,0 +1,102 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread - Low Level SMP Support */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@#define TX_THREAD_SMP_SOURCE_CODE +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" */ +@ +@ + .global sendSGI + + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_core_preempt SMP/Cortex-A5/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function preempts the specified core in situations where the */ +@/* thread corresponding to this core is no longer ready or when the */ +@/* core must be used for a higher-priority thread. If the specified is */ +@/* the current core, this processing is skipped since the will give up */ +@/* control subsequently on its own. */ +@/* */ +@/* INPUT */ +@/* */ +@/* core The core to preempt */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Source */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ + .global _tx_thread_smp_core_preempt + .type _tx_thread_smp_core_preempt,function +_tx_thread_smp_core_preempt: + + STMDB sp!, {r4, lr} @ Save the lr and r4 register on the stack +@ +@ /* Place call to send inter-processor interrupt here! */ +@ + DSB @ + MOV r1, #1 @ Build parameter list + LSL r1, r1, r0 @ + MOV r0, #0 @ + MOV r2, #0 @ + BL sendSGI @ Make call to send inter-processor interrupt + + LDMIA sp!, {r4, lr} @ Recover lr register and r4 +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif + + diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_current_state_get.S new file mode 100644 index 00000000..634d24fe --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_current_state_get.S @@ -0,0 +1,104 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread - Low Level SMP Support */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@#define TX_THREAD_SMP_SOURCE_CODE +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" */ +@ +@ + .global _tx_thread_system_state + + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_current_state_get SMP/Cortex-A5/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is gets the current state of the calling core. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Components */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ + .global _tx_thread_smp_current_state_get + .type _tx_thread_smp_current_state_get,function +_tx_thread_smp_current_state_get: + + MRS r3, CPSR @ Pickup current CPSR + +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif +@ +@ /* Pickup the CPU ID. */ +@ + MRC p15, 0, r2, c0, c0, 5 @ Read CPU ID register + AND r2, r2, #0x03 @ Mask off, leaving the CPU ID field + LSL r2, r2, #2 @ Build offset to array indexes + + LDR r1, =_tx_thread_system_state @ Pickup start of the current state array + ADD r1, r1, r2 @ Build index into the current state array + LDR r0, [r1] @ Pickup state for this core + MSR CPSR_c, r3 @ Restore CPSR +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif + + diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_current_thread_get.S new file mode 100644 index 00000000..11d85861 --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_current_thread_get.S @@ -0,0 +1,104 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread - Low Level SMP Support */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@#define TX_THREAD_SMP_SOURCE_CODE +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" */ +@ +@ + .global _tx_thread_current_ptr + + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_current_thread_get SMP/Cortex-A5/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is gets the current thread of the calling core. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Components */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ + .global _tx_thread_smp_current_thread_get + .type _tx_thread_smp_current_thread_get,function +_tx_thread_smp_current_thread_get: + + MRS r3, CPSR @ Pickup current CPSR + +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif +@ +@ /* Pickup the CPU ID. */ +@ + MRC p15, 0, r2, c0, c0, 5 @ Read CPU ID register + AND r2, r2, #0x03 @ Mask off, leaving the CPU ID field + LSL r2, r2, #2 @ Build offset to array indexes + + LDR r1, =_tx_thread_current_ptr @ Pickup start of the current thread array + ADD r1, r1, r2 @ Build index into the current thread array + LDR r0, [r1] @ Pickup current thread for this core + MSR CPSR_c, r3 @ Restore CPSR +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif + + diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_initialize_wait.S new file mode 100644 index 00000000..cc330a1e --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_initialize_wait.S @@ -0,0 +1,141 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread - Low Level SMP Support */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@#define TX_THREAD_SMP_SOURCE_CODE +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" */ +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_smp_release_cores_flag + .global _tx_thread_schedule + + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_initialize_wait SMP/Cortex-A5/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is the place where additional cores wait until */ +@/* initialization is complete before they enter the thread scheduling */ +@/* loop. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling loop */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Hardware */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ + .global _tx_thread_smp_initialize_wait + .type _tx_thread_smp_initialize_wait,function +_tx_thread_smp_initialize_wait: + +@ /* Lockout interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif +@ +@ /* Pickup the CPU ID. */ +@ + MRC p15, 0, r10, c0, c0, 5 @ Read CPU ID register + AND r10, r10, #0x03 @ Mask off, leaving the CPU ID field + LSL r10, r10, #2 @ Build offset to array indexes +@ +@ /* Make sure the system state for this core is TX_INITIALIZE_IN_PROGRESS before we check the release +@ flag. */ +@ + LDR r3, =_tx_thread_system_state @ Build address of system state variable + ADD r3, r3, r10 @ Build index into the system state array + LDR r2, =0xF0F0F0F0 @ Build TX_INITIALIZE_IN_PROGRESS flag +wait_for_initialize: + LDR r1, [r3] @ Pickup system state + CMP r1, r2 @ Has initialization completed? + BNE wait_for_initialize @ If different, wait here! +@ +@ /* Pickup the release cores flag. */ +@ + LDR r2, =_tx_thread_smp_release_cores_flag @ Build address of release cores flag + +wait_for_release: + LDR r3, [r2] @ Pickup the flag + CMP r3, #0 @ Is it set? + BEQ wait_for_release @ Wait for the flag to be set +@ +@ /* Core 0 has released this core. */ +@ +@ /* Clear this core's system state variable. */ +@ + LDR r3, =_tx_thread_system_state @ Build address of system state variable + ADD r3, r3, r10 @ Build index into the system state array + MOV r0, #0 @ Build clear value + STR r0, [r3] @ Clear this core's entry in the system state array +@ +@ /* Now wait for core 0 to finish it's initialization. */ +@ + LDR r3, =_tx_thread_system_state @ Build address of system state variable of logical 0 + +core_0_wait_loop: + LDR r2, [r3] @ Pickup system state for core 0 + CMP r2, #0 @ Is it 0? + BNE core_0_wait_loop @ No, keep waiting for core 0 to finish its initialization +@ +@ /* Initialize is complete, enter the scheduling loop! */ +@ + B _tx_thread_schedule @ Enter scheduling loop for this core! + + diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_low_level_initialize.S new file mode 100644 index 00000000..034eda3e --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_low_level_initialize.S @@ -0,0 +1,85 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread - Low Level SMP Support */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@#define TX_THREAD_SMP_SOURCE_CODE +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" */ +@ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_low_level_initialize SMP/Cortex-A5/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function performs low-level initialization of the booting */ +@/* core. */ +@/* */ +@/* INPUT */ +@/* */ +@/* number_of_cores Number of cores */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_high_level ThreadX high-level init */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ + .global _tx_thread_smp_low_level_initialize + .type _tx_thread_smp_low_level_initialize,function +_tx_thread_smp_low_level_initialize: + +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif + + diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_protect.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_protect.S new file mode 100644 index 00000000..5c1dd1c4 --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_protect.S @@ -0,0 +1,371 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread - Low Level SMP Support */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@#define TX_THREAD_SMP_SOURCE_CODE +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" */ +@ +@ + +@/* Include macros for modifying the wait list. */ +#include "tx_thread_smp_protection_wait_list_macros.h" + + .global _tx_thread_current_ptr + .global _tx_thread_smp_protection + .global _tx_thread_smp_protect_wait_counts + .global _tx_thread_smp_protect_wait_list + .global _tx_thread_smp_protect_wait_list_lock_protect_in_force + .global _tx_thread_smp_protect_wait_list_head + .global _tx_thread_smp_protect_wait_list_tail + .global _tx_thread_smp_protect_wait_list_size + + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_protect SMP/Cortex-A5/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function gets protection for running inside the ThreadX */ +@/* source. This is acomplished by a combination of a test-and-set */ +@/* flag and periodically disabling interrupts. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* Previous Status Register */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Source */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ + .global _tx_thread_smp_protect + .type _tx_thread_smp_protect,function +_tx_thread_smp_protect: + + PUSH {r4-r6} @ Save registers we'll be using +@ +@ /* Disable interrupts so we don't get preempted. */ +@ + MRS r0, CPSR @ Pickup current CPSR + +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif +@ +@ /* Do we already have protection? */ +@ if (this_core == _tx_thread_smp_protection.tx_thread_smp_protect_core) +@ { +@ + MRC p15, 0, r1, c0, c0, 5 @ Read CPU ID register + AND r1, r1, #0x03 @ Mask off, leaving the CPU ID field + LDR r2, =_tx_thread_smp_protection @ Build address to protection structure + LDR r3, [r2, #8] @ Pickup the owning core + CMP r1, r3 @ Is it not this core? + BNE _protection_not_owned @ No, the protection is not already owned +@ +@ /* We already have protection. */ +@ +@ /* Increment the protection count. */ +@ _tx_thread_smp_protection.tx_thread_smp_protect_count++; +@ + LDR r3, [r2, #12] @ Pickup ownership count + ADD r3, r3, #1 @ Increment ownership count + STR r3, [r2, #12] @ Store ownership count + DMB + + B _return + +_protection_not_owned: +@ +@ /* Is the lock available? */ +@ if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0) +@ { +@ + LDREX r3, [r2, #0] @ Pickup the protection flag + CMP r3, #0 + BNE _start_waiting @ No, protection not available +@ +@ /* Is the list empty? */ +@ if (_tx_thread_smp_protect_wait_list_head == _tx_thread_smp_protect_wait_list_tail) +@ { +@ + LDR r3, =_tx_thread_smp_protect_wait_list_head + LDR r3, [r3] + LDR r4, =_tx_thread_smp_protect_wait_list_tail + LDR r4, [r4] + CMP r3, r4 + BNE _list_not_empty +@ +@ /* Try to get the lock. */ +@ if (write_exclusive(&_tx_thread_smp_protection.tx_thread_smp_protect_in_force, 1) == SUCCESS) +@ { +@ + MOV r3, #1 @ Build lock value + STREX r4, r3, [r2, #0] @ Attempt to get the protection + CMP r4, #0 + BNE _start_waiting @ Did it fail? +@ +@ /* We got the lock! */ +@ _tx_thread_smp_protect_lock_got(); +@ + DMB @ Ensure write to protection finishes + _tx_thread_smp_protect_lock_got @ Call the lock got function + + B _return + +_list_not_empty: +@ +@ /* Are we at the front of the list? */ +@ if (this_core == _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head]) +@ { +@ + LDR r3, =_tx_thread_smp_protect_wait_list_head @ Get the address of the head + LDR r3, [r3] @ Get the value of the head + LDR r4, =_tx_thread_smp_protect_wait_list @ Get the address of the list + LDR r4, [r4, r3, LSL #2] @ Get the value at the head index + + CMP r1, r4 + BNE _start_waiting +@ +@ /* Is the lock still available? */ +@ if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0) +@ { +@ + LDR r3, [r2, #0] @ Pickup the protection flag + CMP r3, #0 + BNE _start_waiting @ No, protection not available +@ +@ /* Get the lock. */ +@ _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1; +@ + MOV r3, #1 @ Build lock value + STR r3, [r2, #0] @ Store lock value + DMB @ +@ +@ /* Got the lock. */ +@ _tx_thread_smp_protect_lock_got(); +@ + _tx_thread_smp_protect_lock_got +@ +@ /* Remove this core from the wait list. */ +@ _tx_thread_smp_protect_remove_from_front_of_list(); +@ + _tx_thread_smp_protect_remove_from_front_of_list + + B _return + +_start_waiting: +@ +@ /* For one reason or another, we didn't get the lock. */ +@ +@ /* Increment wait count. */ +@ _tx_thread_smp_protect_wait_counts[this_core]++; +@ + LDR r3, =_tx_thread_smp_protect_wait_counts @ Load wait list counts + LDR r4, [r3, r1, LSL #2] @ Load waiting value for this core + ADD r4, r4, #1 @ Increment wait value + STR r4, [r3, r1, LSL #2] @ Store new wait value +@ +@ /* Have we not added ourselves to the list yet? */ +@ if (_tx_thread_smp_protect_wait_counts[this_core] == 1) +@ { +@ + CMP r4, #1 + BNE _already_in_list0 @ Is this core already waiting? +@ +@ /* Add ourselves to the list. */ +@ _tx_thread_smp_protect_wait_list_add(this_core); +@ + _tx_thread_smp_protect_wait_list_add @ Call macro to add ourselves to the list +@ +@ } +@ +_already_in_list0: +@ +@ /* Restore interrupts. */ +@ + MSR CPSR_c, r0 @ Restore CPSR +#ifdef TX_ENABLE_WFE + WFE @ Go into standby +#endif +@ +@ /* We do this until we have the lock. */ +@ while (1) +@ { +@ +_try_to_get_lock: +@ +@ /* Disable interrupts so we don't get preempted. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif + + MRC p15, 0, r1, c0, c0, 5 @ Read CPU ID register + AND r1, r1, #0x03 @ Mask off, leaving the CPU ID field +@ +@ /* Do we already have protection? */ +@ if (this_core == _tx_thread_smp_protection.tx_thread_smp_protect_core) +@ { +@ + LDR r3, [r2, #8] @ Pickup the owning core + CMP r3, r1 @ Is it this core? + BEQ _got_lock_after_waiting @ Yes, the protection is already owned. This means + @ an ISR preempted us and got protection +@ +@ } +@ +@ /* Are we at the front of the list? */ +@ if (this_core == _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head]) +@ { +@ + LDR r3, =_tx_thread_smp_protect_wait_list_head @ Get the address of the head + LDR r3, [r3] @ Get the value of the head + LDR r4, =_tx_thread_smp_protect_wait_list @ Get the address of the list + LDR r4, [r4, r3, LSL #2] @ Get the value at the head index + + CMP r1, r4 + BNE _did_not_get_lock +@ +@ /* Is the lock still available? */ +@ if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0) +@ { +@ + LDR r3, [r2, #0] @ Pickup the protection flag + CMP r3, #0 + BNE _did_not_get_lock @ No, protection not available +@ +@ /* Get the lock. */ +@ _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1; +@ + MOV r3, #1 @ Build lock value + STR r3, [r2, #0] @ Store lock value + DMB @ +@ +@ /* Got the lock. */ +@ _tx_thread_smp_protect_lock_got(); +@ + _tx_thread_smp_protect_lock_got +@ +@ /* Remove this core from the wait list. */ +@ _tx_thread_smp_protect_remove_from_front_of_list(); +@ + _tx_thread_smp_protect_remove_from_front_of_list + + B _got_lock_after_waiting + +_did_not_get_lock: +@ +@ /* For one reason or another, we didn't get the lock. */ +@ +@ /* Were we removed from the list? This can happen if we're a thread +@ and we got preempted. */ +@ if (_tx_thread_smp_protect_wait_counts[this_core] == 0) +@ { +@ + LDR r3, =_tx_thread_smp_protect_wait_counts @ Load wait list counts + LDR r4, [r3, r1, LSL #2] @ Load waiting value for this core + CMP r4, #0 + BNE _already_in_list1 @ Is this core already in the list? +@ +@ /* Add ourselves to the list. */ +@ _tx_thread_smp_protect_wait_list_add(this_core); +@ + _tx_thread_smp_protect_wait_list_add @ Call macro to add ourselves to the list +@ +@ /* Our waiting count was also reset when we were preempted. Increment it again. */ +@ _tx_thread_smp_protect_wait_counts[this_core]++; +@ + LDR r3, =_tx_thread_smp_protect_wait_counts @ Load wait list counts + LDR r4, [r3, r1, LSL #2] @ Load waiting value for this core + ADD r4, r4, #1 @ Increment wait value + STR r4, [r3, r1, LSL #2] @ Store new wait value value +@ +@ } +@ +_already_in_list1: +@ +@ /* Restore interrupts and try again. */ +@ + MSR CPSR_c, r0 @ Restore CPSR +#ifdef TX_ENABLE_WFE + WFE @ Go into standby +#endif + B _try_to_get_lock @ On waking, restart the protection attempt + +_got_lock_after_waiting: +@ +@ /* We're no longer waiting. */ +@ _tx_thread_smp_protect_wait_counts[this_core]--; +@ + LDR r3, =_tx_thread_smp_protect_wait_counts @ Load waiting list + LDR r4, [r3, r1, LSL #2] @ Load current wait value + SUB r4, r4, #1 @ Decrement wait value + STR r4, [r3, r1, LSL #2] @ Store new wait value value + +@ +@ /* Restore link register and return. */ +@ +_return: + + POP {r4-r6} @ Restore registers + +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif + + diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h new file mode 100644 index 00000000..26beabbd --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h @@ -0,0 +1,310 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread - Low Level SMP Support */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ + + .macro _tx_thread_smp_protect_lock_got +@ +@ /* Set the currently owned core. */ +@ _tx_thread_smp_protection.tx_thread_smp_protect_core = this_core; +@ + STR r1, [r2, #8] @ Store this core +@ +@ /* Increment the protection count. */ +@ _tx_thread_smp_protection.tx_thread_smp_protect_count++; +@ + LDR r3, [r2, #12] @ Pickup ownership count + ADD r3, r3, #1 @ Increment ownership count + STR r3, [r2, #12] @ Store ownership count + DMB + +#ifdef TX_MPCORE_DEBUG_ENABLE + LSL r3, r1, #2 @ Build offset to array indexes + LDR r4, =_tx_thread_current_ptr @ Pickup start of the current thread array + ADD r4, r3, r4 @ Build index into the current thread array + LDR r3, [r4] @ Pickup current thread for this core + STR r3, [r2, #4] @ Save current thread pointer + STR LR, [r2, #16] @ Save caller's return address + STR r0, [r2, #20] @ Save CPSR +#endif + + .endm + + .macro _tx_thread_smp_protect_remove_from_front_of_list +@ +@ /* Remove ourselves from the list. */ +@ _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head++] = 0xFFFFFFFF; +@ + MOV r3, #0xFFFFFFFF @ Build the invalid core value + LDR r4, =_tx_thread_smp_protect_wait_list_head @ Get the address of the head + LDR r5, [r4] @ Get the value of the head + LDR r6, =_tx_thread_smp_protect_wait_list @ Get the address of the list + STR r3, [r6, r5, LSL #2] @ Store the invalid core value + ADD r5, r5, #1 @ Increment the head +@ +@ /* Did we wrap? */ +@ if (_tx_thread_smp_protect_wait_list_head == TX_THREAD_SMP_MAX_CORES + 1) +@ { +@ + LDR r3, =_tx_thread_smp_protect_wait_list_size @ Load address of core list size + LDR r3, [r3] @ Load the max cores value + CMP r5, r3 @ Compare the head to it + BNE _store_new_head\@ @ Are we at the max? +@ +@ _tx_thread_smp_protect_wait_list_head = 0; +@ + EOR r5, r5, r5 @ We're at the max. Set it to zero +@ +@ } +@ +_store_new_head\@: + + STR r5, [r4] @ Store the new head +@ +@ /* We have the lock! */ +@ return; +@ + .endm + + + .macro _tx_thread_smp_protect_wait_list_lock_get +@VOID _tx_thread_smp_protect_wait_list_lock_get() +@{ +@ /* We do this until we have the lock. */ +@ while (1) +@ { +@ +_tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@: +@ +@ /* Is the list lock available? */ +@ _tx_thread_smp_protect_wait_list_lock_protect_in_force = load_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force); +@ + LDR r1, =_tx_thread_smp_protect_wait_list_lock_protect_in_force + LDREX r2, [r1] @ Pickup the protection flag +@ +@ if (protect_in_force == 0) +@ { +@ + CMP r2, #0 + BNE _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@ @ No, protection not available +@ +@ /* Try to get the list. */ +@ int status = store_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force, 1); +@ + MOV r2, #1 @ Build lock value + STREX r3, r2, [r1] @ Attempt to get the protection +@ +@ if (status == SUCCESS) +@ + CMP r3, #0 + BNE _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@ @ Did it fail? If so, try again. +@ +@ /* We have the lock! */ +@ return; +@ + .endm + + + .macro _tx_thread_smp_protect_wait_list_add +@VOID _tx_thread_smp_protect_wait_list_add(UINT new_core) +@{ +@ +@ /* We're about to modify the list, so get the list lock. */ +@ _tx_thread_smp_protect_wait_list_lock_get(); +@ + PUSH {r1-r2} + + _tx_thread_smp_protect_wait_list_lock_get + + POP {r1-r2} +@ +@ /* Add this core. */ +@ _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_tail++] = new_core; +@ + LDR r3, =_tx_thread_smp_protect_wait_list_tail @ Get the address of the tail + LDR r4, [r3] @ Get the value of tail + LDR r5, =_tx_thread_smp_protect_wait_list @ Get the address of the list + STR r1, [r5, r4, LSL #2] @ Store the new core value + ADD r4, r4, #1 @ Increment the tail +@ +@ /* Did we wrap? */ +@ if (_tx_thread_smp_protect_wait_list_tail == _tx_thread_smp_protect_wait_list_size) +@ { +@ + LDR r5, =_tx_thread_smp_protect_wait_list_size @ Load max cores address + LDR r5, [r5] @ Load max cores value + CMP r4, r5 @ Compare max cores to tail + BNE _tx_thread_smp_protect_wait_list_add__no_wrap\@ @ Did we wrap? +@ +@ _tx_thread_smp_protect_wait_list_tail = 0; +@ + MOV r4, #0 +@ +@ } +@ +_tx_thread_smp_protect_wait_list_add__no_wrap\@: + + STR r4, [r3] @ Store the new tail value. +@ +@ /* Release the list lock. */ +@ _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; +@ + MOV r3, #0 @ Build lock value + LDR r4, =_tx_thread_smp_protect_wait_list_lock_protect_in_force + STR r3, [r4] @ Store the new value + + .endm + + + .macro _tx_thread_smp_protect_wait_list_remove +@VOID _tx_thread_smp_protect_wait_list_remove(UINT core) +@{ +@ +@ /* Get the core index. */ +@ UINT core_index; +@ for (core_index = 0;; core_index++) +@ + EOR r1, r1, r1 @ Clear for 'core_index' + LDR r2, =_tx_thread_smp_protect_wait_list @ Get the address of the list +@ +@ { +@ +_tx_thread_smp_protect_wait_list_remove__check_cur_core\@: +@ +@ /* Is this the core? */ +@ if (_tx_thread_smp_protect_wait_list[core_index] == core) +@ { +@ break; +@ + LDR r3, [r2, r1, LSL #2] @ Get the value at the current index + CMP r3, r0 @ Did we find the core? + BEQ _tx_thread_smp_protect_wait_list_remove__found_core\@ +@ +@ } +@ + ADD r1, r1, #1 @ Increment cur index + B _tx_thread_smp_protect_wait_list_remove__check_cur_core\@ @ Restart the loop +@ +@ } +@ +_tx_thread_smp_protect_wait_list_remove__found_core\@: +@ +@ /* We're about to modify the list. Get the lock. We need the lock because another +@ core could be simultaneously adding (a core is simultaneously trying to get +@ the inter-core lock) or removing (a core is simultaneously being preempted, +@ like what is currently happening). */ +@ _tx_thread_smp_protect_wait_list_lock_get(); +@ + PUSH {r1} + + _tx_thread_smp_protect_wait_list_lock_get + + POP {r1} +@ +@ /* We remove by shifting. */ +@ while (core_index != _tx_thread_smp_protect_wait_list_tail) +@ { +@ +_tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@: + + LDR r2, =_tx_thread_smp_protect_wait_list_tail @ Load tail address + LDR r2, [r2] @ Load tail value + CMP r1, r2 @ Compare cur index and tail + BEQ _tx_thread_smp_protect_wait_list_remove__removed\@ +@ +@ UINT next_index = core_index + 1; +@ + MOV r2, r1 @ Move current index to next index register + ADD r2, r2, #1 @ Add 1 +@ +@ if (next_index == _tx_thread_smp_protect_wait_list_size) +@ { +@ + LDR r3, =_tx_thread_smp_protect_wait_list_size + LDR r3, [r3] + CMP r2, r3 + BNE _tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@ +@ +@ next_index = 0; +@ + MOV r2, #0 +@ +@ } +@ +_tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@: +@ +@ list_cores[core_index] = list_cores[next_index]; +@ + LDR r0, =_tx_thread_smp_protect_wait_list @ Get the address of the list + LDR r3, [r0, r2, LSL #2] @ Get the value at the next index + STR r3, [r0, r1, LSL #2] @ Store the value at the current index +@ +@ core_index = next_index; +@ + MOV r1, r2 + + B _tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@ +@ +@ } +@ +_tx_thread_smp_protect_wait_list_remove__removed\@: +@ +@ /* Now update the tail. */ +@ if (_tx_thread_smp_protect_wait_list_tail == 0) +@ { +@ + LDR r0, =_tx_thread_smp_protect_wait_list_tail @ Load tail address + LDR r1, [r0] @ Load tail value + CMP r1, #0 + BNE _tx_thread_smp_protect_wait_list_remove__tail_not_zero\@ +@ +@ _tx_thread_smp_protect_wait_list_tail = _tx_thread_smp_protect_wait_list_size; +@ + LDR r2, =_tx_thread_smp_protect_wait_list_size + LDR r1, [r2] +@ +@ } +@ +_tx_thread_smp_protect_wait_list_remove__tail_not_zero\@: +@ +@ _tx_thread_smp_protect_wait_list_tail--; +@ + SUB r1, r1, #1 + STR r1, [r0] @ Store new tail value +@ +@ /* Release the list lock. */ +@ _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; +@ + MOV r0, #0 @ Build lock value + LDR r1, =_tx_thread_smp_protect_wait_list_lock_protect_in_force @ Load lock address + STR r0, [r1] @ Store the new value +@ +@ /* We're no longer waiting. Note that this should be zero since, again, +@ this function is only called when a thread preemption is occurring. */ +@ _tx_thread_smp_protect_wait_counts[core]--; +@ + MRC p15, 0, r0, c0, c0, 5 @ Read CPU ID register + AND r0, r0, #0x03 @ Mask off, leaving the CPU ID field + LDR r1, =_tx_thread_smp_protect_wait_counts @ Load wait list counts + LDR r2, [r1, r0, LSL #2] @ Load waiting value + SUB r2, r2, #1 @ Subtract 1 + STR r2, [r1, r0, LSL #2] @ Store new waiting value + .endm + diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_time_get.S new file mode 100644 index 00000000..3d3a3332 --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_time_get.S @@ -0,0 +1,89 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread - Low Level SMP Support */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@#define TX_THREAD_SMP_SOURCE_CODE +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" */ +@ +@ + + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_time_get SMP/Cortex-A5/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function gets the global time value that is used for debug */ +@/* information and event tracing. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* 32-bit time stamp */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Source */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ + .global _tx_thread_smp_time_get + .type _tx_thread_smp_time_get,function +_tx_thread_smp_time_get: + + MRC p15, 4, r0, c15, c0, 0 @ Read periph base address + LDR r0, [r0, #0x604] @ Read count register + +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif + + diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_unprotect.S new file mode 100644 index 00000000..b7f9f356 --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_smp_unprotect.S @@ -0,0 +1,143 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread - Low Level SMP Support */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@#define TX_THREAD_SMP_SOURCE_CODE +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" */ +@ +@ + .global _tx_thread_current_ptr + .global _tx_thread_smp_protection + .global _tx_thread_preempt_disable + .global _tx_thread_smp_protect_wait_counts + + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_unprotect SMP/Cortex-A5/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function releases previously obtained protection. The supplied */ +@/* previous SR is restored. If the value of _tx_thread_system_state */ +@/* and _tx_thread_preempt_disable are both zero, then multithreading */ +@/* is enabled as well. */ +@/* */ +@/* INPUT */ +@/* */ +@/* Previous Status Register */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Source */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ + .global _tx_thread_smp_unprotect + .type _tx_thread_smp_unprotect,function +_tx_thread_smp_unprotect: +@ +@ /* Lockout interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif + + MRC p15, 0, r1, c0, c0, 5 @ Read CPU ID register + AND r1, r1, #0x03 @ Mask off, leaving the CPU ID field + + LDR r2,=_tx_thread_smp_protection @ Build address of protection structure + LDR r3, [r2, #8] @ Pickup the owning core + CMP r1, r3 @ Is it this core? + BNE _still_protected @ If this is not the owning core, protection is in force elsewhere + + LDR r3, [r2, #12] @ Pickup the protection count + CMP r3, #0 @ Check to see if the protection is still active + BEQ _still_protected @ If the protection count is zero, protection has already been cleared + + SUB r3, r3, #1 @ Decrement the protection count + STR r3, [r2, #12] @ Store the new count back + CMP r3, #0 @ Check to see if the protection is still active + BNE _still_protected @ If the protection count is non-zero, protection is still in force + LDR r2,=_tx_thread_preempt_disable @ Build address of preempt disable flag + LDR r3, [r2] @ Pickup preempt disable flag + CMP r3, #0 @ Is the preempt disable flag set? + BNE _still_protected @ Yes, skip the protection release + + LDR r2,=_tx_thread_smp_protect_wait_counts @ Build build address of wait counts + LDR r3, [r2, r1, LSL #2] @ Pickup wait list value + CMP r3, #0 @ Are any entities on this core waiting? + BNE _still_protected @ Yes, skip the protection release + + LDR r2,=_tx_thread_smp_protection @ Build address of protection structure + MOV r3, #0xFFFFFFFF @ Build invalid value + STR r3, [r2, #8] @ Mark the protected core as invalid +#ifdef TX_MPCORE_DEBUG_ENABLE + STR LR, [r2, #16] @ Save caller's return address +#endif + DMB @ Ensure that accesses to shared resource have completed + MOV r3, #0 @ Build release protection value + STR r3, [r2, #0] @ Release the protection + DSB @ To ensure update of the protection occurs before other CPUs awake +#ifdef TX_ENABLE_WFE + SEV @ Send event to other CPUs, wakes anyone waiting on the protection (using WFE) +#endif + +_still_protected: + MSR CPSR_c, r0 @ Restore CPSR + +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif + + diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_stack_build.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_stack_build.S new file mode 100644 index 00000000..f7d8eb81 --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_stack_build.S @@ -0,0 +1,174 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +SVC_MODE = 0x13 @ SVC mode +#ifdef TX_ENABLE_FIQ_SUPPORT +CPSR_MASK = 0xDF @ Mask initial CPSR, IRQ & FIQ ints enabled +#else +CPSR_MASK = 0x9F @ Mask initial CPSR, IRQ ints enabled +#endif + +THUMB_BIT = 0x20 @ Thumb-bit + +@ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_stack_build SMP/Cortex-A5/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function builds a stack frame on the supplied thread's stack. */ +@/* The stack frame results in a fake interrupt return to the supplied */ +@/* function pointer. */ +@/* */ +@/* INPUT */ +@/* */ +@/* thread_ptr Pointer to thread control blk */ +@/* function_ptr Pointer to return function */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_thread_create Create thread service */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +@{ + .global _tx_thread_stack_build + .type _tx_thread_stack_build,function +_tx_thread_stack_build: +@ +@ +@ /* Build a fake interrupt frame. The form of the fake interrupt stack +@ on the Cortex-A5 should look like the following after it is built: +@ +@ Stack Top: 1 Interrupt stack frame type +@ CPSR Initial value for CPSR +@ a1 (r0) Initial value for a1 +@ a2 (r1) Initial value for a2 +@ a3 (r2) Initial value for a3 +@ a4 (r3) Initial value for a4 +@ v1 (r4) Initial value for v1 +@ v2 (r5) Initial value for v2 +@ v3 (r6) Initial value for v3 +@ v4 (r7) Initial value for v4 +@ v5 (r8) Initial value for v5 +@ sb (r9) Initial value for sb +@ sl (r10) Initial value for sl +@ fp (r11) Initial value for fp +@ ip (r12) Initial value for ip +@ lr (r14) Initial value for lr +@ pc (r15) Initial value for pc +@ 0 For stack backtracing +@ +@ Stack Bottom: (higher memory address) */ +@ + LDR r2, [r0, #16] @ Pickup end of stack area + BIC r2, r2, #7 @ Ensure 8-byte alignment + SUB r2, r2, #76 @ Allocate space for the stack frame +@ +@ /* Actually build the stack frame. */ +@ + MOV r3, #1 @ Build interrupt stack type + STR r3, [r2, #0] @ Store stack type + MOV r3, #0 @ Build initial register value + STR r3, [r2, #8] @ Store initial r0 + STR r3, [r2, #12] @ Store initial r1 + STR r3, [r2, #16] @ Store initial r2 + STR r3, [r2, #20] @ Store initial r3 + STR r3, [r2, #24] @ Store initial r4 + STR r3, [r2, #28] @ Store initial r5 + STR r3, [r2, #32] @ Store initial r6 + STR r3, [r2, #36] @ Store initial r7 + STR r3, [r2, #40] @ Store initial r8 + STR r3, [r2, #44] @ Store initial r9 + LDR r3, [r0, #12] @ Pickup stack starting address + STR r3, [r2, #48] @ Store initial r10 (sl) + MOV r3, #0 @ Build initial register value + STR r3, [r2, #52] @ Store initial r11 + STR r3, [r2, #56] @ Store initial r12 + STR r3, [r2, #60] @ Store initial lr + STR r1, [r2, #64] @ Store initial pc + STR r3, [r2, #68] @ 0 for back-trace + + MRS r3, CPSR @ Pickup CPSR + BIC r3, r3, #CPSR_MASK @ Mask mode bits of CPSR + ORR r3, r3, #SVC_MODE @ Build CPSR, SVC mode, interrupts enabled + BIC r3, r3, #THUMB_BIT @ Clear Thumb-bit by default + AND r1, r1, #1 @ Determine if the entry function is in Thumb mode + CMP r1, #1 @ Is the Thumb-bit set? + ORREQ r3, r3, #THUMB_BIT @ Yes, set the Thumb-bit + STR r3, [r2, #4] @ Store initial CPSR +@ +@ /* Setup stack pointer. */ +@ thread_ptr -> tx_thread_stack_ptr = r2; +@ + STR r2, [r0, #8] @ Save stack pointer in thread's + @ control block + +@ +@ /* Set ready bit in thread control block. */ +@ + LDR r2, [r0, #152] @ Pickup word with ready bit + ORR r2, r2, #0x8000 @ Build ready bit set + STR r2, [r0, #152] @ Set ready bit + +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_system_return.S new file mode 100644 index 00000000..24232edd --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_system_return.S @@ -0,0 +1,206 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_current_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable + .global _tx_thread_smp_protection +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + .global _tx_execution_thread_exit +#endif +@ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_system_return SMP/Cortex-A5/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is target processor specific. It is used to transfer */ +@/* control from a thread back to the ThreadX system. Only a */ +@/* minimal context is saved since the compiler assumes temp registers */ +@/* are going to get slicked by a function call anyway. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling loop */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX components */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_system_return(VOID) +@{ + .global _tx_thread_system_return + .type _tx_thread_system_return,function +_tx_thread_system_return: +@ +@ /* Save minimal context on the stack. */ +@ + STMDB sp!, {r4-r11, lr} @ Save minimal context +@ +@ /* Pickup the CPU ID. */ +@ + MRC p15, 0, r10, c0, c0, 5 @ Read CPU ID register + AND r10, r10, #0x03 @ Mask off, leaving the CPU ID field + LSL r12, r10, #2 @ Build offset to array indexes + + LDR r3, =_tx_thread_current_ptr @ Pickup address of current ptr + ADD r3, r3, r12 @ Build index into current ptr array + LDR r0, [r3, #0] @ Pickup current thread pointer +#ifdef TARGET_FPU_VFP + LDR r1, [r0, #160] @ Pickup the VFP enabled flag + CMP r1, #0 @ Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_save @ No, skip VFP solicited save + VMRS r4, FPSCR @ Pickup the FPSCR + STR r4, [sp, #-4]! @ Save FPSCR + VSTMDB sp!, {D16-D31} @ Save D16-D31 + VSTMDB sp!, {D8-D15} @ Save D8-D15 +_tx_skip_solicited_vfp_save: +#endif + MOV r4, #0 @ Build a solicited stack type + MRS r5, CPSR @ Pickup the CPSR + STMDB sp!, {r4-r5} @ Save type and CPSR +@ +@ /* Lockout interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the thread exit function to indicate the thread is no longer executing. */ +@ + MOV r4, r0 @ Save r0 + MOV r5, r3 @ Save r3 + MOV r6, r12 @ Save r12 + BL _tx_execution_thread_exit @ Call the thread exit function + MOV r3, r5 @ Recover r3 + MOV r0, r4 @ Recover r4 + MOV r12,r6 @ Recover r12 +#endif +@ + LDR r2, =_tx_timer_time_slice @ Pickup address of time slice + ADD r2, r2, r12 @ Build index into time-slice array + LDR r1, [r2, #0] @ Pickup current time slice +@ +@ /* Save current stack and switch to system stack. */ +@ _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; +@ sp = _tx_thread_system_stack_ptr[core]; +@ + STR sp, [r0, #8] @ Save thread stack pointer +@ +@ /* Determine if the time-slice is active. */ +@ if (_tx_timer_time_slice[core]) +@ { +@ + MOV r4, #0 @ Build clear value + CMP r1, #0 @ Is a time-slice active? + BEQ __tx_thread_dont_save_ts @ No, don't save the time-slice +@ +@ /* Save time-slice for the thread and clear the current time-slice. */ +@ _tx_thread_current_ptr[core] -> tx_thread_time_slice = _tx_timer_time_slice[core]; +@ _tx_timer_time_slice[core] = 0; +@ + STR r4, [r2, #0] @ Clear time-slice + STR r1, [r0, #24] @ Save current time-slice +@ +@ } +__tx_thread_dont_save_ts: +@ +@ /* Clear the current thread pointer. */ +@ _tx_thread_current_ptr[core] = TX_NULL; +@ + STR r4, [r3, #0] @ Clear current thread pointer +@ +@ /* Set ready bit in thread control block. */ +@ + LDR r2, [r0, #152] @ Pickup word with ready bit + ORR r2, r2, #0x8000 @ Build ready bit set + DMB @ Ensure that accesses to shared resource have completed + STR r2, [r0, #152] @ Set ready bit +@ +@ /* Now clear protection. It is assumed that protection is in force whenever this routine is called. */ +@ + LDR r3, =_tx_thread_smp_protection @ Pickup address of protection structure + +#ifdef TX_MPCORE_DEBUG_ENABLE + STR lr, [r3, #24] @ Save last caller + LDR r2, [r3, #4] @ Pickup owning thread + CMP r0, r2 @ Is it the same as the current thread? +__error_loop: + BNE __error_loop @ If not, we have a problem!! +#endif + + LDR r1, =_tx_thread_preempt_disable @ Build address to preempt disable flag + MOV r2, #0 @ Build clear value + STR r2, [r1, #0] @ Clear preempt disable flag + STR r2, [r3, #12] @ Clear protection count + MOV r1, #0xFFFFFFFF @ Build invalid value + STR r1, [r3, #8] @ Set core to an invalid value + DMB @ Ensure that accesses to shared resource have completed + STR r2, [r3] @ Clear protection + DSB @ To ensure update of the shared resource occurs before other CPUs awake + SEV @ Send event to other CPUs, wakes anyone waiting on a mutex (using WFE) + + B _tx_thread_schedule @ Jump to scheduler! +@ +@} + diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_thread_vectored_context_save.S b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_vectored_context_save.S new file mode 100644 index 00000000..e33197b2 --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_thread_vectored_context_save.S @@ -0,0 +1,210 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + .global _tx_execution_isr_enter +#endif +@ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_vectored_context_save SMP/Cortex-A5/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_vectored_context_save(VOID) +@{ + .global _tx_thread_vectored_context_save + .type _tx_thread_vectored_context_save,function +_tx_thread_vectored_context_save: +@ +@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +@ out, we are in IRQ mode, and all registers are intact. */ +@ +@ /* Check for a nested interrupt condition. */ +@ if (_tx_thread_system_state[core]++) +@ { +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#endif +@ +@ /* Pickup the CPU ID. */ +@ + MRC p15, 0, r10, c0, c0, 5 @ Read CPU ID register + AND r10, r10, #0x03 @ Mask off, leaving the CPU ID field + LSL r12, r10, #2 @ Build offset to array indexes + + LDR r3, =_tx_thread_system_state @ Pickup address of system state var + ADD r3, r3, r12 @ Build index into the system state array + LDR r2, [r3, #0] @ Pickup system state + CMP r2, #0 @ Is this the first interrupt? + BEQ __tx_thread_not_nested_save @ Yes, not a nested context save +@ +@ /* Nested interrupt condition. */ +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3, #0] @ Store it back in the variable +@ +@ /* Note: Minimal context of interrupted thread is already saved. */ +@ +@ /* Return to the ISR. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {r12, lr} @ Save ISR lr & r12 + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {r12, lr} @ Recover ISR lr & r12 +#endif + +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@ +__tx_thread_not_nested_save: +@ } +@ +@ /* Otherwise, not nested, check to see if a thread was running. */ +@ else if (_tx_thread_current_ptr[core]) +@ { +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3, #0] @ Store it back in the variable + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + ADD r1, r1, r12 @ Build index into current thread ptr + LDR r0, [r1, #0] @ Pickup current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + @ scheduling loop - nothing needs saving! +@ +@ /* Note: Minimal context of interrupted thread is already saved. */ +@ +@ /* Save the current stack pointer in the thread's control block. */ +@ _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; +@ +@ /* Switch to the system stack. */ +@ sp = _tx_thread_system_stack_ptr[core]; +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {r12, lr} @ Save ISR lr & r12 + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {r12, lr} @ Recover ISR lr & r12 +#endif + +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@ +@ } +@ else +@ { +@ +__tx_thread_idle_system_save: +@ +@ /* Interrupt occurred in the scheduling loop. */ +@ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ processing. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {r12, lr} @ Save ISR lr & r12 + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {r12, lr} @ Recover ISR lr & r12 +#endif + + ADD sp, sp, #32 @ Recover saved registers +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@ +@ } +@} +@ + diff --git a/ports_smp/cortex_a5_smp/gnu/src/tx_timer_interrupt.S b/ports_smp/cortex_a5_smp/gnu/src/tx_timer_interrupt.S new file mode 100644 index 00000000..b7d8f162 --- /dev/null +++ b/ports_smp/cortex_a5_smp/gnu/src/tx_timer_interrupt.S @@ -0,0 +1,230 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Timer */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_timer.h" +@#include "tx_thread.h" +@ +@ +@Define Assembly language external references... +@ + .global _tx_timer_time_slice + .global _tx_timer_system_clock + .global _tx_timer_current_ptr + .global _tx_timer_list_start + .global _tx_timer_list_end + .global _tx_timer_expired_time_slice + .global _tx_timer_expired + .global _tx_thread_time_slice + .global _tx_timer_expiration_process + .global _tx_timer_interrupt_active + .global _tx_thread_smp_protect + .global _tx_thread_smp_unprotect + .global _tx_trace_isr_enter_insert + .global _tx_trace_isr_exit_insert +@ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_timer_interrupt SMP/Cortex-A5/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function processes the hardware timer interrupt. This */ +@/* processing includes incrementing the system clock and checking for */ +@/* time slice and/or timer expiration. If either is found, the */ +@/* interrupt context save/restore functions are called along with the */ +@/* expiration functions. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_time_slice Time slice interrupted thread */ +@/* _tx_thread_smp_protect Get SMP protection */ +@/* _tx_thread_smp_unprotect Releast SMP protection */ +@/* _tx_timer_expiration_process Timer expiration processing */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* interrupt vector */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_timer_interrupt(VOID) +@{ + .global _tx_timer_interrupt + .type _tx_timer_interrupt,function +_tx_timer_interrupt: +@ +@ /* Upon entry to this routine, it is assumed that context save has already +@ been called, and therefore the compiler scratch registers are available +@ for use. */ +@ + MRC p15, 0, r0, c0, c0, 5 @ Read CPU ID register + AND r0, r0, #0x03 @ Mask off, leaving the CPU ID field + CMP r0, #0 @ Only process timer interrupts from core 0 (to change this simply change the constant!) + BEQ __tx_process_timer @ If the same process the interrupt + BX lr @ Return to caller if not matched +__tx_process_timer: + + STMDB sp!, {r4, lr} @ Save the lr and r4 register on the stack + BL _tx_thread_smp_protect @ Get protection + MOV r4, r0 @ Save the return value in preserved register + + LDR r1, =_tx_timer_interrupt_active @ Pickup address of timer interrupt active count + LDR r0, [r1, #0] @ Pickup interrupt active count + ADD r0, r0, #1 @ Increment interrupt active count + STR r0, [r1, #0] @ Store new interrupt active count + DMB @ Ensure that accesses to shared resource have completed +@ +@ /* Increment the system clock. */ +@ _tx_timer_system_clock++; +@ + LDR r1, =_tx_timer_system_clock @ Pickup address of system clock + LDR r0, [r1, #0] @ Pickup system clock + ADD r0, r0, #1 @ Increment system clock + STR r0, [r1, #0] @ Store new system clock +@ +@ /* Test for timer expiration. */ +@ if (*_tx_timer_current_ptr) +@ { +@ + LDR r1, =_tx_timer_expired @ Pickup addr of expired flag + LDR r0, [r1, #0] @ Pickup timer expired flag + CMP r0, #0 @ Check for previous timer expiration still active + BNE __tx_timer_done @ If so, skip timer processing + LDR r1, =_tx_timer_current_ptr @ Pickup current timer pointer addr + LDR r0, [r1, #0] @ Pickup current timer + LDR r2, [r0, #0] @ Pickup timer list entry + CMP r2, #0 @ Is there anything in the list? + BEQ __tx_timer_no_timer @ No, just increment the timer +@ +@ /* Set expiration flag. */ +@ _tx_timer_expired = TX_TRUE; +@ + LDR r3, =_tx_timer_expired @ Pickup expiration flag address + MOV r2, #1 @ Build expired value + STR r2, [r3, #0] @ Set expired flag + B __tx_timer_done @ Finished timer processing +@ +@ } +@ else +@ { +__tx_timer_no_timer: +@ +@ /* No timer expired, increment the timer pointer. */ +@ _tx_timer_current_ptr++; +@ + ADD r0, r0, #4 @ Move to next timer +@ +@ /* Check for wrap-around. */ +@ if (_tx_timer_current_ptr == _tx_timer_list_end) +@ + LDR r3, =_tx_timer_list_end @ Pickup addr of timer list end + LDR r2, [r3, #0] @ Pickup list end + CMP r0, r2 @ Are we at list end? + BNE __tx_timer_skip_wrap @ No, skip wrap-around logic +@ +@ /* Wrap to beginning of list. */ +@ _tx_timer_current_ptr = _tx_timer_list_start; +@ + LDR r3, =_tx_timer_list_start @ Pickup addr of timer list start + LDR r0, [r3, #0] @ Set current pointer to list start +@ +__tx_timer_skip_wrap: +@ + STR r0, [r1, #0] @ Store new current timer pointer +@ } +@ +__tx_timer_done: +@ +@ +@ /* Did a timer expire? */ +@ if (_tx_timer_expired) +@ { +@ + LDR r1, =_tx_timer_expired @ Pickup addr of expired flag + LDR r0, [r1, #0] @ Pickup timer expired flag + CMP r0, #0 @ Check for timer expiration + BEQ __tx_timer_dont_activate @ If not set, skip timer activation +@ +@ /* Process timer expiration. */ +@ _tx_timer_expiration_process(); +@ + BL _tx_timer_expiration_process @ Call the timer expiration handling routine +@ +@ } +__tx_timer_dont_activate: +@ +@ /* Call time-slice processing. */ +@ _tx_thread_time_slice(); + + BL _tx_thread_time_slice @ Call time-slice processing +@ +@ } +@ + LDR r1, =_tx_timer_interrupt_active @ Pickup address of timer interrupt active count + LDR r0, [r1, #0] @ Pickup interrupt active count + SUB r0, r0, #1 @ Decrement interrupt active count + STR r0, [r1, #0] @ Store new interrupt active count + DMB @ Ensure that accesses to shared resource have completed +@ +@ /* Release protection. */ +@ + MOV r0, r4 @ Pass the previous status register back + BL _tx_thread_smp_unprotect @ Release protection + + LDMIA sp!, {r4, lr} @ Recover lr register and r4 +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@ +@} + diff --git a/ports_smp/cortex_a5x_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a5x_smp/ac6/inc/tx_port.h index 728ab0d9..33e78618 100644 --- a/ports_smp/cortex_a5x_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a5x_smp/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A5x-SMP/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -418,7 +418,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 1996-2019 Express Logic Inc. * ThreadX Cortex-A5x-SMP/AC6 Version 6.0.1 *"; + "Copyright (c) 1996-2019 Express Logic Inc. * ThreadX Cortex-A5x-SMP/AC6 Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a5x_smp/ac6/readme_threadx.txt b/ports_smp/cortex_a5x_smp/ac6/readme_threadx.txt index d9459876..e41ff303 100644 --- a/ports_smp/cortex_a5x_smp/ac6/readme_threadx.txt +++ b/ports_smp/cortex_a5x_smp/ac6/readme_threadx.txt @@ -247,7 +247,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A5x using AC6 tools. +09/30/2020 Initial ThreadX 6.1 version for Cortex-A5x using AC6 tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_initialize_low_level.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_initialize_low_level.S index 564dcfcf..db8c084d 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_initialize_low_level.S +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_initialize_low_level.S @@ -40,7 +40,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_initialize_low_level Cortex-A5x-SMP/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -73,7 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_initialize_low_level(VOID) diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_context_restore.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_context_restore.S index 7de6aedf..49097357 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_context_restore.S @@ -42,7 +42,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore Cortex-A5x-SMP/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -74,7 +74,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_context_restore(VOID) @@ -97,10 +97,17 @@ _tx_thread_context_restore: /* Pickup the CPU ID. */ MRS x8, MPIDR_EL1 // Pickup the core ID +#ifdef TX_ARMV8_2 +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x2, x8, #16, #8 // Isolate cluster ID +#endif + UBFX x8, x8, #8, #8 // Isolate core ID +#else #if TX_THREAD_SMP_CLUSTERS > 1 UBFX x2, x8, #8, #8 // Isolate cluster ID #endif UBFX x8, x8, #0, #8 // Isolate core ID +#endif #if TX_THREAD_SMP_CLUSTERS > 1 ADDS x8, x8, x2, LSL #2 // Calculate CPU ID #endif diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_context_save.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_context_save.S index 3152c49e..abcd4c89 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_context_save.S @@ -38,7 +38,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save Cortex-A5x-SMP/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,7 +69,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_context_save(VOID) @@ -92,10 +92,17 @@ _tx_thread_context_save: /* Pickup the CPU ID. */ MRS x1, MPIDR_EL1 // Pickup the core ID +#ifdef TX_ARMV8_2 +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x2, x1, #16, #8 // Isolate cluster ID +#endif + UBFX x1, x1, #8, #8 // Isolate core ID +#else #if TX_THREAD_SMP_CLUSTERS > 1 UBFX x2, x1, #8, #8 // Isolate cluster ID #endif UBFX x1, x1, #0, #8 // Isolate core ID +#endif #if TX_THREAD_SMP_CLUSTERS > 1 ADDS x1, x1, x2, LSL #2 // Calculate CPU ID #endif @@ -198,10 +205,17 @@ __tx_thread_not_nested_save: LDR x3, =_tx_thread_system_stack_ptr // Pickup address of system stack MRS x1, MPIDR_EL1 // Pickup the core ID +#ifdef TX_ARMV8_2 +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x2, x1, #16, #8 // Isolate cluster ID +#endif + UBFX x1, x1, #8, #8 // Isolate core ID +#else #if TX_THREAD_SMP_CLUSTERS > 1 UBFX x2, x1, #8, #8 // Isolate cluster ID #endif UBFX x1, x1, #0, #8 // Isolate core ID +#endif #if TX_THREAD_SMP_CLUSTERS > 1 ADDS x1, x1, x2, LSL #2 // Calculate CPU ID #endif diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_fp_disable.c b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_fp_disable.c index 9ebe0e0e..3ba1331d 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_fp_disable.c +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_fp_disable.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_fp_disable Cortex-A5x-SMP/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -63,7 +63,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_fp_enable.c b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_fp_enable.c index 0c32b7fd..8e119eb1 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_fp_enable.c +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_fp_enable.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_fp_enable Cortex-A5x-SMP/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -63,7 +63,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_interrupt_control.S index 99a7323a..d257a66e 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_interrupt_control.S +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_interrupt_control.S @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control Cortex-A5x-SMP/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,7 +67,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_interrupt_disable.S index fb03b103..f6de1368 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_interrupt_disable.S +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_interrupt_disable.S @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable Cortex-A5x-SMP/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -66,7 +66,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* UINT _tx_thread_interrupt_disable(void) diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_interrupt_restore.S index baf8543c..a461734b 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_interrupt_restore.S +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_interrupt_restore.S @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore Cortex-A5x-SMP/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,7 +67,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_schedule.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_schedule.S index be186a65..ce38d84b 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_schedule.S @@ -39,7 +39,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-A5x-SMP/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_schedule(VOID) @@ -88,10 +88,17 @@ _tx_thread_schedule: /* Pickup the CPU ID. */ MRS x20, MPIDR_EL1 // Pickup the core ID +#ifdef TX_ARMV8_2 +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x1, x20, #16, #8 // Isolate cluster ID +#endif + UBFX x20, x20, #8, #8 // Isolate core ID +#else #if TX_THREAD_SMP_CLUSTERS > 1 UBFX x1, x20, #8, #8 // Isolate cluster ID #endif UBFX x20, x20, #0, #8 // Isolate core ID +#endif #if TX_THREAD_SMP_CLUSTERS > 1 ADDS x20, x20, x1, LSL #2 // Calculate CPU ID #endif diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_core_get.S index 9d1fc758..08f3bfcc 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_core_get.S +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_core_get.S @@ -41,7 +41,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_core_get Cortex-A5x-SMP/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,17 +70,24 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get, @function _tx_thread_smp_core_get: MRS x0, MPIDR_EL1 // Pickup the core ID +#ifdef TX_ARMV8_2 +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x1, x0, #16, #8 // Isolate cluster ID +#endif + UBFX x0, x0, #8, #8 // Isolate core ID +#else #if TX_THREAD_SMP_CLUSTERS > 1 UBFX x1, x0, #8, #8 // Isolate cluster ID #endif UBFX x0, x0, #0, #8 // Isolate core ID +#endif #if TX_THREAD_SMP_CLUSTERS > 1 ADDS x0, x0, x1, LSL #2 // Calculate CPU ID #endif diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_core_preempt.S index 0e615059..e0f28fef 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_core_preempt.S +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_core_preempt.S @@ -40,7 +40,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_core_preempt Cortex-A5x-SMP/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -73,15 +73,21 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ .global _tx_thread_smp_core_preempt .type _tx_thread_smp_core_preempt, @function _tx_thread_smp_core_preempt: DSB ISH +#ifdef TX_ARMV8_2 + MOV x2, #0x1 // Build the target list field + LSL x3, x0, #16 // Build the affinity1 field + ORR x2, x2, x3 // Combine the fields +#else MOV x2, #0x1 // LSL x2, x2, x0 // Shift by the core ID +#endif MSR ICC_SGI1R_EL1, x2 // Issue inter-core interrupt RET diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_current_state_get.S index 8b9d5dc3..8ca92372 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_current_state_get.S +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_current_state_get.S @@ -41,7 +41,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_current_state_get Cortex-A5x-SMP/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ .global _tx_thread_smp_current_state_get @@ -80,10 +80,17 @@ _tx_thread_smp_current_state_get: MRS x1, DAIF // Pickup current interrupt posture MSR DAIFSet, 0x3 // Lockout interrupts MRS x2, MPIDR_EL1 // Pickup the core ID +#ifdef TX_ARMV8_2 +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x3, x2, #16, #8 // Isolate cluster ID +#endif + UBFX x2, x2, #8, #8 // Isolate core ID +#else #if TX_THREAD_SMP_CLUSTERS > 1 UBFX x3, x2, #8, #8 // Isolate cluster ID #endif UBFX x2, x2, #0, #8 // Isolate core ID +#endif #if TX_THREAD_SMP_CLUSTERS > 1 ADDS x2, x2, x3, LSL #2 // Calculate CPU ID #endif diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_current_thread_get.S index 2013d4e6..7c1b5af8 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_current_thread_get.S +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_current_thread_get.S @@ -41,7 +41,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_current_thread_get Cortex-A5x-SMP/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ .global _tx_thread_smp_current_thread_get @@ -80,10 +80,17 @@ _tx_thread_smp_current_thread_get: MRS x1, DAIF // Pickup current interrupt posture MSR DAIFSet, 0x3 // Lockout interrupts MRS x2, MPIDR_EL1 // Pickup the core ID +#ifdef TX_ARMV8_2 +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x3, x2, #16, #8 // Isolate cluster ID +#endif + UBFX x2, x2, #8, #8 // Isolate core ID +#else #if TX_THREAD_SMP_CLUSTERS > 1 UBFX x3, x2, #8, #8 // Isolate cluster ID #endif UBFX x2, x2, #0, #8 // Isolate core ID +#endif #if TX_THREAD_SMP_CLUSTERS > 1 ADDS x2, x2, x3, LSL #2 // Calculate CPU ID #endif diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_initialize_wait.S index d81a2654..25195731 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_initialize_wait.S +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_initialize_wait.S @@ -41,7 +41,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_initialize_wait Cortex-A5x-SMP/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ .global _tx_thread_smp_initialize_wait @@ -86,10 +86,17 @@ _tx_thread_smp_initialize_wait: /* Pickup the Core ID. */ MRS x2, MPIDR_EL1 // Pickup the core ID +#ifdef TX_ARMV8_2 +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x3, x2, #16, #8 // Isolate cluster ID +#endif + UBFX x2, x2, #8, #8 // Isolate core ID +#else #if TX_THREAD_SMP_CLUSTERS > 1 UBFX x3, x2, #8, #8 // Isolate cluster ID #endif UBFX x2, x2, #0, #8 // Isolate core ID +#endif #if TX_THREAD_SMP_CLUSTERS > 1 ADDS x2, x2, x3, LSL #2 // Calculate CPU ID #endif diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_low_level_initialize.S index a3cf8f62..73384b5a 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_low_level_initialize.S +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_low_level_initialize.S @@ -40,7 +40,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_low_level_initialize Cortex-A5x-SMP/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ .global _tx_thread_smp_low_level_initialize diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_protect.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_protect.S index 0046488d..a208aa29 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_protect.S +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_protect.S @@ -44,7 +44,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_protect Cortex-A5x-SMP/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -75,7 +75,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ .global _tx_thread_smp_protect @@ -90,10 +90,17 @@ _tx_thread_smp_protect: /* Pickup the CPU ID. */ MRS x1, MPIDR_EL1 // Pickup the core ID +#ifdef TX_ARMV8_2 +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x7, x1, #16, #8 // Isolate cluster ID +#endif + UBFX x1, x1, #8, #8 // Isolate core ID +#else #if TX_THREAD_SMP_CLUSTERS > 1 UBFX x7, x1, #8, #8 // Isolate cluster ID #endif UBFX x1, x1, #0, #8 // Isolate core ID +#endif #if TX_THREAD_SMP_CLUSTERS > 1 ADDS x1, x1, x7, LSL #2 // Calculate CPU ID #endif @@ -248,10 +255,17 @@ _try_to_get_lock: /* Pickup the CPU ID. */ MRS x1, MPIDR_EL1 // Pickup the core ID +#ifdef TX_ARMV8_2 +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x7, x1, #16, #8 // Isolate cluster ID +#endif + UBFX x1, x1, #8, #8 // Isolate core ID +#else #if TX_THREAD_SMP_CLUSTERS > 1 UBFX x7, x1, #8, #8 // Isolate cluster ID #endif UBFX x1, x1, #0, #8 // Isolate core ID +#endif #if TX_THREAD_SMP_CLUSTERS > 1 ADDS x1, x1, x7, LSL #2 // Calculate CPU ID #endif diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_time_get.S index 1d2f4a96..35df86c7 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_time_get.S +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_time_get.S @@ -41,7 +41,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_time_get Cortex-A5x-SMP/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ .global _tx_thread_smp_time_get diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_unprotect.S index f8c31e60..cb3a0b7b 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_unprotect.S +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_unprotect.S @@ -41,7 +41,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_unprotect Cortex-A5x-SMP/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -73,7 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ .global _tx_thread_smp_unprotect @@ -82,10 +82,17 @@ _tx_thread_smp_unprotect: MSR DAIFSet, 0x3 // Lockout interrupts MRS x1, MPIDR_EL1 // Pickup the core ID +#ifdef TX_ARMV8_2 +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x2, x1, #16, #8 // Isolate cluster ID +#endif + UBFX x1, x1, #8, #8 // Isolate core ID +#else #if TX_THREAD_SMP_CLUSTERS > 1 UBFX x2, x1, #8, #8 // Isolate cluster ID #endif UBFX x1, x1, #0, #8 // Isolate core ID +#endif #if TX_THREAD_SMP_CLUSTERS > 1 ADDS x1, x1, x2, LSL #2 // Calculate CPU ID #endif diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_stack_build.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_stack_build.S index e4be8b6e..bf6879b5 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_stack_build.S +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_stack_build.S @@ -39,7 +39,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build Cortex-A5x-SMP/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_system_return.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_system_return.S index 31e3c42c..1a46f20a 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_system_return.S @@ -38,7 +38,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return Cortex-A5x-SMP/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_system_return(VOID) @@ -90,10 +90,17 @@ _tx_thread_system_return: STP x25, x26, [sp, #-16]! // Save x25, x26 STP x27, x28, [sp, #-16]! // Save x27, x28 MRS x8, MPIDR_EL1 // Pickup the core ID +#ifdef TX_ARMV8_2 +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x3, x8, #16, #8 // Isolate cluster ID +#endif + UBFX x8, x8, #8, #8 // Isolate core ID +#else #if TX_THREAD_SMP_CLUSTERS > 1 UBFX x3, x8, #8, #8 // Isolate cluster ID #endif UBFX x8, x8, #0, #8 // Isolate core ID +#endif #if TX_THREAD_SMP_CLUSTERS > 1 ADDS x8, x8, x3, LSL #2 // Calculate CPU ID #endif diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_timeout.c b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_timeout.c index 6e556c92..6b896c4c 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_timeout.c +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_timeout.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_timeout Cortex-A5x-SMP */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_timeout(ULONG timeout_input) diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_timer_interrupt.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_timer_interrupt.S index 92bc19df..889f8e4c 100644 --- a/ports_smp/cortex_a5x_smp/ac6/src/tx_timer_interrupt.S +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_timer_interrupt.S @@ -38,7 +38,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt Cortex-A5x-SMP/AC6 */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_timer_interrupt(VOID) @@ -82,10 +82,17 @@ _tx_timer_interrupt: MRS x2, MPIDR_EL1 // Pickup the core ID +#ifdef TX_ARMV8_2 +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x3, x2, #16, #8 // Isolate cluster ID +#endif + UBFX x2, x2, #8, #8 // Isolate core ID +#else #if TX_THREAD_SMP_CLUSTERS > 1 UBFX x3, x2, #8, #8 // Isolate cluster ID #endif UBFX x2, x2, #0, #8 // Isolate core ID +#endif #if TX_THREAD_SMP_CLUSTERS > 1 ADDS x2, x2, x3, LSL #2 // Calculate CPU ID #endif diff --git a/ports_smp/cortex_a5x_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a5x_smp/gnu/inc/tx_port.h index 362b2062..0860e74a 100644 --- a/ports_smp/cortex_a5x_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a5x_smp/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A5x-SMP/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -418,7 +418,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5x-SMP/GNU Version 6.0.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5x-SMP/GNU Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a5x_smp/gnu/readme_threadx.txt b/ports_smp/cortex_a5x_smp/gnu/readme_threadx.txt index 6786efdf..9dbdcb9e 100644 --- a/ports_smp/cortex_a5x_smp/gnu/readme_threadx.txt +++ b/ports_smp/cortex_a5x_smp/gnu/readme_threadx.txt @@ -247,7 +247,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX SMP: -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A5x using ARM GCC and DS-5 tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-A5x using ARM GCC and DS-5 tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_initialize_low_level.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_initialize_low_level.S index b411b1d7..be27e5bf 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_initialize_low_level.S +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_initialize_low_level.S @@ -40,7 +40,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_initialize_low_level Cortex-A5x-SMP/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -73,7 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_initialize_low_level(VOID) diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_context_restore.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_context_restore.S index 03335d82..b1dd2671 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_context_restore.S @@ -42,7 +42,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_restore Cortex-A5x-SMP/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -74,7 +74,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_context_restore(VOID) @@ -97,10 +97,17 @@ _tx_thread_context_restore: /* Pickup the CPU ID. */ MRS x8, MPIDR_EL1 // Pickup the core ID +#ifdef TX_ARMV8_2 +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x2, x8, #16, #8 // Isolate cluster ID +#endif + UBFX x8, x8, #8, #8 // Isolate core ID +#else #if TX_THREAD_SMP_CLUSTERS > 1 UBFX x2, x8, #8, #8 // Isolate cluster ID #endif UBFX x8, x8, #0, #8 // Isolate core ID +#endif #if TX_THREAD_SMP_CLUSTERS > 1 ADDS x8, x8, x2, LSL #2 // Calculate CPU ID #endif diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_context_save.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_context_save.S index 27e60ccc..bddad6e1 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_context_save.S @@ -38,7 +38,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_context_save Cortex-A5x-SMP/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -69,7 +69,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_context_save(VOID) @@ -92,10 +92,17 @@ _tx_thread_context_save: /* Pickup the CPU ID. */ MRS x1, MPIDR_EL1 // Pickup the core ID +#ifdef TX_ARMV8_2 +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x2, x1, #16, #8 // Isolate cluster ID +#endif + UBFX x1, x1, #8, #8 // Isolate core ID +#else #if TX_THREAD_SMP_CLUSTERS > 1 UBFX x2, x1, #8, #8 // Isolate cluster ID #endif UBFX x1, x1, #0, #8 // Isolate core ID +#endif #if TX_THREAD_SMP_CLUSTERS > 1 ADDS x1, x1, x2, LSL #2 // Calculate CPU ID #endif @@ -198,10 +205,17 @@ __tx_thread_not_nested_save: LDR x3, =_tx_thread_system_stack_ptr // Pickup address of system stack MRS x1, MPIDR_EL1 // Pickup the core ID +#ifdef TX_ARMV8_2 +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x2, x1, #16, #8 // Isolate cluster ID +#endif + UBFX x1, x1, #8, #8 // Isolate core ID +#else #if TX_THREAD_SMP_CLUSTERS > 1 UBFX x2, x1, #8, #8 // Isolate cluster ID #endif UBFX x1, x1, #0, #8 // Isolate core ID +#endif #if TX_THREAD_SMP_CLUSTERS > 1 ADDS x1, x1, x2, LSL #2 // Calculate CPU ID #endif diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_fp_disable.c b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_fp_disable.c index b38041d1..c7128843 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_fp_disable.c +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_fp_disable.c @@ -34,7 +34,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_fp_disable Cortex-A5x-SMP/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -63,7 +63,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_fp_disable(VOID) diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_fp_enable.c b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_fp_enable.c index 5fb43b8b..9124a5c5 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_fp_enable.c +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_fp_enable.c @@ -33,7 +33,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_fp_enable Cortex-A5x-SMP/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -62,7 +62,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_fp_enable(VOID) diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_interrupt_control.S index 880a629e..4377a66f 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_interrupt_control.S +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_interrupt_control.S @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_control Cortex-A5x-SMP/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,7 +67,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_interrupt_disable.S index 9bd1249d..bfe54e34 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_interrupt_disable.S +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_interrupt_disable.S @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_disable Cortex-A5x-SMP/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -66,7 +66,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* UINT _tx_thread_interrupt_disable(void) diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_interrupt_restore.S index a6ab9f51..f7f7f172 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_interrupt_restore.S +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_interrupt_restore.S @@ -37,7 +37,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_interrupt_restore Cortex-A5x-SMP/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -67,7 +67,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_schedule.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_schedule.S index 242778e2..e146a0f3 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_schedule.S @@ -39,7 +39,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-A5x-SMP/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_schedule(VOID) @@ -88,10 +88,17 @@ _tx_thread_schedule: /* Pickup the CPU ID. */ MRS x20, MPIDR_EL1 // Pickup the core ID +#ifdef TX_ARMV8_2 +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x1, x20, #16, #8 // Isolate cluster ID +#endif + UBFX x20, x20, #8, #8 // Isolate core ID +#else #if TX_THREAD_SMP_CLUSTERS > 1 UBFX x1, x20, #8, #8 // Isolate cluster ID #endif UBFX x20, x20, #0, #8 // Isolate core ID +#endif #if TX_THREAD_SMP_CLUSTERS > 1 ADDS x20, x20, x1, LSL #2 // Calculate CPU ID #endif diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_core_get.S index 679a59f0..3cf2607c 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_core_get.S +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_core_get.S @@ -41,7 +41,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_core_get Cortex-A5x-SMP/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,17 +70,24 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ .global _tx_thread_smp_core_get .type _tx_thread_smp_core_get, @function _tx_thread_smp_core_get: MRS x0, MPIDR_EL1 // Pickup the core ID +#ifdef TX_ARMV8_2 +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x1, x0, #16, #8 // Isolate cluster ID +#endif + UBFX x0, x0, #8, #8 // Isolate core ID +#else #if TX_THREAD_SMP_CLUSTERS > 1 UBFX x1, x0, #8, #8 // Isolate cluster ID #endif UBFX x0, x0, #0, #8 // Isolate core ID +#endif #if TX_THREAD_SMP_CLUSTERS > 1 ADDS x0, x0, x1, LSL #2 // Calculate CPU ID #endif diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_core_preempt.S index be75c89e..fea54077 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_core_preempt.S +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_core_preempt.S @@ -42,7 +42,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_core_preempt Cortex-A5x-SMP/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -75,15 +75,21 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ .global _tx_thread_smp_core_preempt .type _tx_thread_smp_core_preempt, @function _tx_thread_smp_core_preempt: - DSB ISH + DSB ISH +#ifdef TX_ARMV8_2 + MOV x2, #0x1 // Build the target list field + LSL x3, x0, #16 // Build the affinity1 field + ORR x2, x2, x3 // Combine the fields +#else MOV x2, #0x1 // LSL x2, x2, x0 // Shift by the core ID +#endif MSR ICC_SGI1R_EL1, x2 // Issue inter-core interrupt RET diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_current_state_get.S index 36284739..bd8f19c3 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_current_state_get.S +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_current_state_get.S @@ -41,7 +41,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_current_state_get Cortex-A5x-SMP/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ .global _tx_thread_smp_current_state_get @@ -80,10 +80,17 @@ _tx_thread_smp_current_state_get: MRS x1, DAIF // Pickup current interrupt posture MSR DAIFSet, 0x3 // Lockout interrupts MRS x2, MPIDR_EL1 // Pickup the core ID +#ifdef TX_ARMV8_2 +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x3, x2, #16, #8 // Isolate cluster ID +#endif + UBFX x2, x2, #8, #8 // Isolate core ID +#else #if TX_THREAD_SMP_CLUSTERS > 1 UBFX x3, x2, #8, #8 // Isolate cluster ID #endif UBFX x2, x2, #0, #8 // Isolate core ID +#endif #if TX_THREAD_SMP_CLUSTERS > 1 ADDS x2, x2, x3, LSL #2 // Calculate CPU ID #endif diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_current_thread_get.S index 8c33f3f7..8062bba6 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_current_thread_get.S +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_current_thread_get.S @@ -41,7 +41,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_current_thread_get Cortex-A5x-SMP/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ .global _tx_thread_smp_current_thread_get @@ -80,10 +80,17 @@ _tx_thread_smp_current_thread_get: MRS x1, DAIF // Pickup current interrupt posture MSR DAIFSet, 0x3 // Lockout interrupts MRS x2, MPIDR_EL1 // Pickup the core ID +#ifdef TX_ARMV8_2 +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x3, x2, #16, #8 // Isolate cluster ID +#endif + UBFX x2, x2, #8, #8 // Isolate core ID +#else #if TX_THREAD_SMP_CLUSTERS > 1 UBFX x3, x2, #8, #8 // Isolate cluster ID #endif UBFX x2, x2, #0, #8 // Isolate core ID +#endif #if TX_THREAD_SMP_CLUSTERS > 1 ADDS x2, x2, x3, LSL #2 // Calculate CPU ID #endif diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_initialize_wait.S index 7c59b770..276ef199 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_initialize_wait.S +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_initialize_wait.S @@ -41,7 +41,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_initialize_wait Cortex-A5x-SMP/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ .global _tx_thread_smp_initialize_wait @@ -86,10 +86,17 @@ _tx_thread_smp_initialize_wait: /* Pickup the Core ID. */ MRS x2, MPIDR_EL1 // Pickup the core ID +#ifdef TX_ARMV8_2 +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x3, x2, #16, #8 // Isolate cluster ID +#endif + UBFX x2, x2, #8, #8 // Isolate core ID +#else #if TX_THREAD_SMP_CLUSTERS > 1 UBFX x3, x2, #8, #8 // Isolate cluster ID #endif UBFX x2, x2, #0, #8 // Isolate core ID +#endif #if TX_THREAD_SMP_CLUSTERS > 1 ADDS x2, x2, x3, LSL #2 // Calculate CPU ID #endif diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_low_level_initialize.S index 6b8b582b..7509f39a 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_low_level_initialize.S +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_low_level_initialize.S @@ -40,7 +40,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_low_level_initialize Cortex-A5x-SMP/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ .global _tx_thread_smp_low_level_initialize diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_protect.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_protect.S index 48f37a7e..e28b87ac 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_protect.S +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_protect.S @@ -44,7 +44,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_protect Cortex-A5x-SMP/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -75,7 +75,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ .global _tx_thread_smp_protect @@ -90,10 +90,17 @@ _tx_thread_smp_protect: /* Pickup the CPU ID. */ MRS x1, MPIDR_EL1 // Pickup the core ID +#ifdef TX_ARMV8_2 +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x7, x1, #16, #8 // Isolate cluster ID +#endif + UBFX x1, x1, #8, #8 // Isolate core ID +#else #if TX_THREAD_SMP_CLUSTERS > 1 UBFX x7, x1, #8, #8 // Isolate cluster ID #endif UBFX x1, x1, #0, #8 // Isolate core ID +#endif #if TX_THREAD_SMP_CLUSTERS > 1 ADDS x1, x1, x7, LSL #2 // Calculate CPU ID #endif @@ -248,10 +255,17 @@ _try_to_get_lock: /* Pickup the CPU ID. */ MRS x1, MPIDR_EL1 // Pickup the core ID +#ifdef TX_ARMV8_2 +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x7, x1, #16, #8 // Isolate cluster ID +#endif + UBFX x1, x1, #8, #8 // Isolate core ID +#else #if TX_THREAD_SMP_CLUSTERS > 1 UBFX x7, x1, #8, #8 // Isolate cluster ID #endif UBFX x1, x1, #0, #8 // Isolate core ID +#endif #if TX_THREAD_SMP_CLUSTERS > 1 ADDS x1, x1, x7, LSL #2 // Calculate CPU ID #endif diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_time_get.S index df179adf..bed8873b 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_time_get.S +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_time_get.S @@ -41,7 +41,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_time_get Cortex-A5x-SMP/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ .global _tx_thread_smp_time_get diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_unprotect.S index 7eb5f68f..340a9709 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_unprotect.S +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_unprotect.S @@ -41,7 +41,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_smp_unprotect Cortex-A5x-SMP/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -73,7 +73,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ .global _tx_thread_smp_unprotect @@ -82,10 +82,17 @@ _tx_thread_smp_unprotect: MSR DAIFSet, 0x3 // Lockout interrupts MRS x1, MPIDR_EL1 // Pickup the core ID +#ifdef TX_ARMV8_2 +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x2, x1, #16, #8 // Isolate cluster ID +#endif + UBFX x1, x1, #8, #8 // Isolate core ID +#else #if TX_THREAD_SMP_CLUSTERS > 1 UBFX x2, x1, #8, #8 // Isolate cluster ID #endif UBFX x1, x1, #0, #8 // Isolate core ID +#endif #if TX_THREAD_SMP_CLUSTERS > 1 ADDS x1, x1, x2, LSL #2 // Calculate CPU ID #endif diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_stack_build.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_stack_build.S index 03183de1..0699940c 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_stack_build.S +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_stack_build.S @@ -39,7 +39,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_stack_build Cortex-A5x-SMP/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_system_return.S index ff9ce4e7..8837e115 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_system_return.S @@ -38,7 +38,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_system_return Cortex-A5x-SMP/ARM */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,7 +70,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_thread_system_return(VOID) @@ -90,10 +90,17 @@ _tx_thread_system_return: STP x25, x26, [sp, #-16]! // Save x25, x26 STP x27, x28, [sp, #-16]! // Save x27, x28 MRS x8, MPIDR_EL1 // Pickup the core ID +#ifdef TX_ARMV8_2 +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x3, x8, #16, #8 // Isolate cluster ID +#endif + UBFX x8, x8, #8, #8 // Isolate core ID +#else #if TX_THREAD_SMP_CLUSTERS > 1 UBFX x3, x8, #8, #8 // Isolate cluster ID #endif UBFX x8, x8, #0, #8 // Isolate core ID +#endif #if TX_THREAD_SMP_CLUSTERS > 1 ADDS x8, x8, x3, LSL #2 // Calculate CPU ID #endif diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_timeout.c b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_timeout.c index 635de647..bd8fb7dd 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_timeout.c +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_timeout.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_timeout Cortex-A5x-SMP */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -71,7 +71,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ VOID _tx_thread_timeout(ULONG timeout_input) diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_timer_interrupt.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_timer_interrupt.S index d89be120..8ad6372f 100644 --- a/ports_smp/cortex_a5x_smp/gnu/src/tx_timer_interrupt.S +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_timer_interrupt.S @@ -38,7 +38,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_timer_interrupt Cortex-A5x-SMP/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ /* VOID _tx_timer_interrupt(VOID) @@ -82,10 +82,17 @@ _tx_timer_interrupt: MRS x2, MPIDR_EL1 // Pickup the core ID +#ifdef TX_ARMV8_2 +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x3, x2, #16, #8 // Isolate cluster ID +#endif + UBFX x2, x2, #8, #8 // Isolate core ID +#else #if TX_THREAD_SMP_CLUSTERS > 1 UBFX x3, x2, #8, #8 // Isolate cluster ID #endif UBFX x2, x2, #0, #8 // Isolate core ID +#endif #if TX_THREAD_SMP_CLUSTERS > 1 ADDS x2, x2, x3, LSL #2 // Calculate CPU ID #endif diff --git a/ports_smp/cortex_a5x_smp/green/example_build/azure_rtos_workspace.gpj b/ports_smp/cortex_a5x_smp/green/example_build/azure_rtos_workspace.gpj new file mode 100644 index 00000000..ad7546de --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/example_build/azure_rtos_workspace.gpj @@ -0,0 +1,12 @@ +#!gbuild +defineConfig ("Debug" "DBG" "tgt\debug.gpc") +defineConfig ("Release" "REL" "tgt\release.gpc") +primaryTarget=arm64_standalone.tgt +#component top_level_project +[Project] + -bsp generic + -cpu=cortexa53 + :sourceDir=. +tx\libtx.gpj [Library] +sample_threadx\sample_threadx.gpj [Program] +tgt\resources.gpj [Project] diff --git a/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/sample_threadx.c new file mode 100644 index 00000000..698a92f0 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/sample_threadx.c @@ -0,0 +1,388 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" +#include + + + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +UCHAR memory_pool[DEMO_BYTE_POOL_SIZE]; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_pool, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Print results every second. */ + if (thread_0_counter % 10 == 1) + { + printf("**** ThreadX SMP Zynq UltraScale+ MPSoC/Cortex-A53 Demonstration **** (c) 1996-2018 Express Logic, Inc.\n\n"); + printf(" thread 0 events sent: %lu\n", thread_0_counter); + printf(" thread 1 messages sent: %lu\n", thread_1_counter); + printf(" thread 2 messages received: %lu\n", thread_2_counter); + printf(" thread 3 obtained semaphore: %lu\n", thread_3_counter); + printf(" thread 4 obtained semaphore: %lu\n", thread_4_counter); + printf(" thread 5 events received: %lu\n", thread_5_counter); + printf(" thread 6 mutex obtained: %lu\n", thread_6_counter); + printf(" thread 7 mutex obtained: %lu\n\n", thread_7_counter); + } + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/sample_threadx.gpj b/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/sample_threadx.gpj new file mode 100644 index 00000000..d4519068 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/sample_threadx.gpj @@ -0,0 +1,16 @@ +#!gbuild +[Program] + -object_dir=${%option_value(-object_dir)}/sample_threadx + -I../../../../../common_smp/inc + -I../../../../../ports_common_green/inc + -I../../inc + {config(DBG)} -L../bin/Debug + -ltx + -e _boot + -memory + --gnu_asm +tgt\standalone_ram.ld +sample_threadx.c +tx_boot.a64 +stdio_ghs.c +tx_zynqmp_low_level.c diff --git a/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/stdio_ghs.c b/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/stdio_ghs.c new file mode 100644 index 00000000..d780bd8f --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/stdio_ghs.c @@ -0,0 +1,35 @@ +#include + +/* + * Zynq Ultrascale+ MPSoC / GHS + * + * Implements standard I/O through UART + * + * XXX assume the UART has already been initialized by bootloader + */ +#define UART_BASE 0xff000000U /* UART0 */ + +#define UART_FIFO *((volatile uint32_t *)(UART_BASE+0x0030U)) +#define UART_SR *((volatile uint32_t *)(UART_BASE+0x002CU)) +#define UART_SR_TXFULL 0x00000010U + + +long write(int fno, const void *buf, long size) +{ + if (fno != 1) return -1; + + const char *p = buf; + const char *pmax = p + size; + while (p < pmax) { + char c = *p++; + if (c == '\n') { + /* expand LF to CR+LF */ + while ((UART_SR & UART_SR_TXFULL) != 0); + UART_FIFO = '\r'; + } + while ((UART_SR & UART_SR_TXFULL) != 0); + UART_FIFO = c; + } + + return size; +} diff --git a/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/tx_boot.a64 b/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/tx_boot.a64 new file mode 100644 index 00000000..4ea6fa35 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/tx_boot.a64 @@ -0,0 +1,276 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** bootstrap for Zynq UltraScale+ MPSoC / Cortex-A53-SMP */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* generic timer clock frequency */ +#define GENERIC_TIMER_FREQ 99990000 + +/* Zynq registers */ +#define RVBAR_BASE 0xFD5C0040 +#define RST_FPD_APU 0xFD1A0104 + +/* global symbols */ + +.global _boot +.global _vector_table + +.global _start +.global __tx_irq_handler +.global _tx_platform_smp_initialize_low_level +.global _tx_thread_smp_initialize_wait + +.global __el3_stack +.global __el3_1_stack +.global __el3_2_stack +.global __el3_3_stack + + +/* exception vector table */ + +.section .vectors, "ax" +.align 0x800 // 0x000 +_vector_table: + b _boot + +.align 0x80 // 0x080 + b . + +.align 0x80 // 0x100 + b . + +.align 0x80 // 0x180 + b . + +.align 0x80 // 0x200 + b . + +.align 0x80 // 0x280 + b __tx_irq_handler + +.align 0x80 // 0x300 + b . + +.align 0x80 // 0x380 + b . + +.align 0x80 // 0x400 + b . + +.align 0x80 // 0x480 + b . + +.align 0x80 // 0x500 + b . + +.align 0x80 // 0x580 + b . + +.align 0x80 // 0x600 + b . + +.align 0x80 // 0x680 + b . + +.align 0x80 // 0x700 + b . + +.align 0x80 // 0x780 + b . + +.align 0x80 // 0x800 + + +.section .boot, "ax" + +_boot: + // check that it is core 0 running + mrs x0, MPIDR_EL1 + ands x0, x0, #0xFF + b.eq core0 +not_core0: + wfi + b not_core0 + +core0: + // set cores 1-3 in reset state + ldr x0, =RST_FPD_APU + ldr w1, [x0] + orr w1, w1, #(7 << 1) // Hold cores 1-3 in reset + str w1, [x0] + and w1, w1, #~(7 << 11) // Remove the power-on reset on cores 1-3 + str w1, [x0] + + // set reset vector for cores 0-3 + ldr x0, =RVBAR_BASE + ldr x1, =_boot + str x1, [x0] + ldr x1, =_boot_smp + str x1, [x0, #8] + str x1, [x0, #16] + str x1, [x0, #24] + +/* common boot code */ +_boot_smp: + // reset all registers + mov x3, #0 + mov x4, #0 + mov x5, #0 + mov x6, #0 + mov x7, #0 + mov x8, #0 + mov x9, #0 + mov x10, #0 + mov x11, #0 + mov x12, #0 + mov x13, #0 + mov x14, #0 + mov x15, #0 + mov x16, #0 + mov x17, #0 + mov x18, #0 + mov x19, #0 + mov x20, #0 + mov x21, #0 + mov x22, #0 + mov x23, #0 + mov x24, #0 + mov x25, #0 + mov x26, #0 + mov x27, #0 + mov x28, #0 + mov x29, #0 + mov x30, #0 + + // go to error if current exception level not EL3 + mrs x0, CurrentEL + cmp x0, #0xC + b.ne error + + // set vector table base address + ldr x0, =_vector_table + msr VBAR_EL3, x0 + + // get core id in x0 + mrs x0, MPIDR_EL1 + and x0, x0, #0xFF + + // set stack pointer for current core + ldr x2, =EL3_stacks + lsl x1, x0, #3 // coreid * 8 + ldr x2, [x2, x1] + mov sp, x2 + + // disable trapping of SIMD/FPU registers + mov x1, #0 + msr CPTR_EL3, x1 + + // set SCR_EL3 + ldr x1, =0xC0E + msr SCR_EL3, x1 + + // set CPUACTLR_EL1 + ldr x1, =0x1000080CA000 + msr S3_1_C15_C2_0, x1 + + // set the generic timer frequency + ldr x1, =GENERIC_TIMER_FREQ + msr CNTFRQ_EL0, x1 + + // enable hardware coherency between cores + mrs x1, S3_1_C15_C2_1 + orr x1, x1, #(1 << 6) + msr S3_1_C15_C2_1, x1 + isb + + // invalidate caches + tlbi ALLE3 + ic IALLU + bl invalidate_dcaches + dsb sy + isb + + // jump to main only from core 0 + mrs x0, MPIDR_EL1 + ands x0, x0, #0xFF + b.ne cores_1_3_init + mov x2, 0 // Clear envp reg + mov x1, 0 // Clear argv reg + b _start // go to C land + +cores_1_3_init: + // low level initialization for cores 1-3 + bl _tx_platform_smp_initialize_low_level + // continue to threadx smp initialization + b _tx_thread_smp_initialize_wait + +error: + b error + + .align 8 +EL3_stacks: + .quad __el3_stack + .quad __el3_1_stack + .quad __el3_2_stack + .quad __el3_3_stack + + +invalidate_dcaches: + mrs x0, CLIDR_EL1 + and w3, w0, #0x07000000 // Get 2 x Level of Coherence + lsr w3, w3, #23 + cbz w3, Finished + mov w10, #0 // w10 = 2 x cache level + mov w8, #1 // w8 = constant 0b1 +Loop1: + add w2, w10, w10, lsr #1 // Calculate 3 x cache level + lsr w1, w0, w2 // extract 3-bit cache type for this level + and w1, w1, #0x7 + cmp W1, #2 + b.lt Skip // No data or unified cache at this level + msr CSSELR_EL1, x10 // Select this cache level + isb // Synchronize change of CSSELR + mrs x1, CCSIDR_EL1 // Read CCSIDR + and w2, w1, #7 // w2 = log2(linelen)-4 + add w2, w2, #4 // w2 = log2(linelen) + ubfx w4, w1, #3, #10 // w4 = max way number, right aligned + clz w5, w4 // w5 = 32-log2(ways), bit position of way in DC operand + lsl w9, w4, w5 // w9 = max way number, aligned to position in DC operand + lsl w16, w8, w5 // w16 = amount to decrement way number per iteration +Loop2: + ubfx w7, w1, #13, #15 // w7 = max set number, right aligned + lsl w7, w7, w2 // w7 = max set number, aligned to position in DC operand + lsl w17, w8, w2 // w17 = amount to decrement set number per iteration +Loop3: + orr w11, w10, w9 // w11 = combine way number and cache number... + orr w11, w11, w7 // ... and set number for DC operand + dc csw, x11 // Do data cache clean by set and way + subs w7, w7, w17 // Decrement set number + b.ge Loop3 + subs x9, x9, x16 // Decrement way number + b.ge Loop2 +Skip: + add w10, w10, #2 // Increment 2 x cache level + cmp w3, w10 + dsb sy // Ensure completion of previous cache maintenance operation + b.gt Loop1 +Finished: + ret + +.end diff --git a/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/tx_zynqmp.h b/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/tx_zynqmp.h new file mode 100644 index 00000000..4842e70a --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/tx_zynqmp.h @@ -0,0 +1,109 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Zynq UltraScale+ MPSoC / Cortex-A53-SMP - Low-level functions */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#ifndef TX_ZYNQMP_H +#define TX_ZYNQMP_H + +#include +#include + +#ifdef __cplusplus + +/* Yes, C++ compiler is present. Use standard C. */ +extern "C" { +#endif + + +/* Define Interrupt Handling Interface functions. */ + +void tx_zynqmp_irq_enable(unsigned id, void (*handler)(void *), void *data); +void tx_zynqmp_irq_disable(unsigned id); +void tx_zynqmp_irq_priority(unsigned id, unsigned prio); +void tx_zynqmp_irq_config(unsigned id, int edge); + + +/* ThreadX SMP Extensions */ + +void tx_zynqmp_irq_smp_core(unsigned irq_id, unsigned core_id); + + +/* Wait for small pauses */ + +void tx_zynqmp_udelay(unsigned usecs); + + +#if 1 /* need compiler option -gnu_asm */ + +/* Define the size of a cache line */ + +#define TX_ZYNQMP_DCACHE_LINE_SIZE 64 + +/* Flush (Clean & Invalidate) memory region */ + +static inline void tx_zynqmp_dcache_flush(uintptr_t ptr, uintptr_t ptr_max) +{ + while (ptr < ptr_max) + { + /* Clean & Invalidate data cache by VA to PoC */ + asm volatile ( "DC CIVAC, %0" : : "r" (ptr)); + ptr += TX_ZYNQMP_DCACHE_LINE_SIZE; + } + /* wait for completion */ + asm volatile ( "DSB SY"); +} + +/* Invalidate memory region */ + +static inline void tx_zynqmp_dcache_invalidate(uintptr_t ptr, uintptr_t ptr_max) +{ + while (ptr < ptr_max) + { + /* Invalidate data cache by VA to PoC */ + asm volatile ( "DC IVAC, %0" : : "r" (ptr)); + ptr += TX_ZYNQMP_DCACHE_LINE_SIZE; + } + /* wait for completion */ + asm volatile ( "DSB SY"); +} + +/* Clean memory region (without Invalidate) */ + +static inline void tx_zynqmp_dcache_clean(uintptr_t ptr, uintptr_t ptr_max) +{ + while (ptr < ptr_max) + { + /* Clean data cache by VA to PoC */ + asm volatile ( "DC CVAC, %0" : : "r" (ptr)); + ptr += TX_ZYNQMP_DCACHE_LINE_SIZE; + } + /* wait for completion */ + asm volatile ( "DSB SY"); +} + +#endif + +#ifdef __cplusplus +/* Yes, C++ compiler is present. Use standard C. */ + } +#endif + +#endif /* TX_ZYNQMP_H */ diff --git a/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/tx_zynqmp_low_level.c b/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/tx_zynqmp_low_level.c new file mode 100644 index 00000000..9b145f97 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/tx_zynqmp_low_level.c @@ -0,0 +1,805 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Zynq UltraScale+ MPSoC / Cortex-A53-SMP - Low-level functions */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#include "tx_api.h" +#include "tx_zynqmp.h" +#include +#include +#include + +/* Disable the data cache. By default the data cache is enabled. */ +/* +#define TX_DCACHE_OFF +*/ + +/* GIC base address (CBAR register) */ +#define INIT_CBAR uint64_t CBAR = __MRS(__GENERIC_SYS_REG(3,1,15,3,0)); + +/* GIC Distributor Registers */ +#define GIC_BASEADDR (CBAR+0x10000ull) +#define GIC_REG(offset) *((volatile uint32_t *)(GIC_BASEADDR+offset)) + +#define GICD_CTLR GIC_REG(0x000) +#define GICD_ISENABLER(i) GIC_REG(0x100 + 4*(i)) +#define GICD_ICENABLER(i) GIC_REG(0x180 + 4*(i)) +#define GICD_ICPENDR(i) GIC_REG(0x280 + 4*(i)) +#define GICD_ISACTIVER(i) GIC_REG(0x300 + 4*(i)) +#define GICD_ICACTIVER(i) GIC_REG(0x380 + 4*(i)) +#define GICD_IPRIORITY(i) GIC_REG(0x400 + 4*(i)) +#define GICD_IPRIORITYB(i) *((volatile uint8_t *)(GIC_BASEADDR+0x400+(i))) +#define GICD_ITARGETSR(i) GIC_REG(0x800 + 4*(i)) +#define GICD_ITARGETSRB(i) *((volatile uint8_t *)(GIC_BASEADDR+0x800+(i))) +#define GICD_ICFGR(i) GIC_REG(0xc00 + 4*(i)) + +/* GIC CPU Registers */ +#define GIC_CPU_BASEADDR (CBAR+0x20000ull) +#define GIC_CPU_REG(offset) *((volatile uint32_t *)(GIC_CPU_BASEADDR+offset)) + +#define GICC_CTLR GIC_CPU_REG(0x000) +#define GICC_PMR GIC_CPU_REG(0x004) +#define GICC_IAR GIC_CPU_REG(0x00c) +#define GICC_EOIR GIC_CPU_REG(0x010) + +/* CRF_APB Clock and Reset control registers */ +#define RST_FPD_APU *((volatile uint32_t *) 0xfd1a0104ull) + + +/* Interrupt handler table */ +#define IRQ_ID_MAX 192 +uint64_t _tx_platform_irq_handlers[2*IRQ_ID_MAX]; + +/* default handler */ +static void tx_irq_default_handler(uint64_t id) +{ + INIT_CBAR + + /* unexpected interrupt... disable it! */ + GICD_ICENABLER(id>>5) = 1 << (id & 0x1f); + +#if 0 /* debug */ + while(1); +#endif +} + +/* inter-processor software interrupt */ +static void tx_core_interrupt(void *data) +{ + /* nothing to do, just used to wakeup the core */ +} + + +/* Generic Timer Registers */ +static inline uint32_t CNTFRQ_READ(void) +{ + return __MRS(__CNTFRQ_EL0); +} + +static inline uint64_t CNTPCT_READ(void) +{ + return __MRS(__CNTPCT_EL0); +} + +static inline void CNTP_CTL_WRITE(uint32_t v) +{ + __MSR(__CNTPS_CTL_EL1, v); +} + +static inline uint64_t CNTP_CVAL_READ(void) +{ + return __MRS(__CNTPS_CVAL_EL1); +} + +static inline void CNTP_CVAL_WRITE(uint64_t v) +{ + __MSR(__CNTPS_CVAL_EL1, v); +} + +/* Generic Timer Interrupt */ +#define GENERIC_TIMER_IRQ_ID 29 + + +/* ThreadX timer interrupt */ +extern void _tx_timer_interrupt(void); + +static uint32_t tx_timer_delay; + +static void tx_generic_timer_interrupt(void *data) +{ + /* update next timer expiration */ + CNTP_CVAL_WRITE(CNTP_CVAL_READ() + tx_timer_delay); + + /* call ThreadX timer interrupt handler */ + _tx_timer_interrupt(); +} + +#ifndef TX_DCACHE_OFF + +/* MMU Tables */ + +#pragma ghs section bss=".mmu_tbl0" +static uint64_t mmu_tbl0[2]; + +#pragma ghs section bss=".mmu_tbl1" +static uint64_t mmu_tbl1[0x400]; + +#pragma ghs section bss=".mmu_tbl2" +static uint64_t mmu_tbl2[0x800]; + +#pragma ghs section bss=default + +/* set MMU tables */ +static void mmu_tbl_init(void) +{ + int i; + uint64_t sect; +/*| | Memory Range | Definition in Translation Table | + *|-----------------------|-----------------------------|-----------------------------------| + *| DDR | 0x0000000000 - 0x007FFFFFFF | Normal write-back Cacheable | + *| PL | 0x0080000000 - 0x00BFFFFFFF | Strongly Ordered | + *| QSPI, lower PCIe | 0x00C0000000 - 0x00EFFFFFFF | Strongly Ordered | + *| Reserved | 0x00F0000000 - 0x00F7FFFFFF | Unassigned | + *| STM Coresight | 0x00F8000000 - 0x00F8FFFFFF | Strongly Ordered | + *| GIC | 0x00F9000000 - 0x00F91FFFFF | Strongly Ordered | + *| Reserved | 0x00F9200000 - 0x00FCFFFFFF | Unassigned | + *| FPS, LPS slaves | 0x00FD000000 - 0x00FFBFFFFF | Strongly Ordered | + *| CSU, PMU | 0x00FFC00000 - 0x00FFDFFFFF | Strongly Ordered | + *| TCM, OCM | 0x00FFE00000 - 0x00FFFFFFFF | Normal inner write-back cacheable | + *| Reserved | 0x0100000000 - 0x03FFFFFFFF | Unassigned | + *| PL, PCIe | 0x0400000000 - 0x07FFFFFFFF | Strongly Ordered | + *| DDR | 0x0800000000 - 0x0FFFFFFFFF | Normal inner write-back cacheable | + *| PL, PCIe | 0x1000000000 - 0xBFFFFFFFFF | Strongly Ordered | + *| Reserved | 0xC000000000 - 0xFFFFFFFFFF | Unassigned |*/ + +#define MMU_RESERVED 0 +#define MMU_MEMORY 0x705 +#define MMU_DEVICE (0x409 | (1ull << 53) | (1ull << 54)) + + /* 0x00_0000_0000 - 0x7F_FFFF_FFFF */ + mmu_tbl0[0] = ((uint64_t) mmu_tbl1) + 0x3; + /* 0x80_0000_0000 - 0xFF_FFFF_FFFF */ + mmu_tbl0[1] = ((uint64_t) mmu_tbl1) + 0x1000 + 0x3; + + /* 0x00_0000_0000 - 0x00_FFFF_FFFF */ + /* 2GB DDR, PL, other devices memory */ + sect = (uint64_t) mmu_tbl2; + i = 0; + for (; i < 0x004; i++, sect += 0x1000) { + mmu_tbl1[i] = sect + 0x3; + } + /* 0x01_0000_0000 - 0x03_FFFF_FFFF */ + /* 16GB Reserved */ + sect = 0x100000000ull; + for (; i < 0x010; i++, sect += 0x40000000) { + mmu_tbl1[i] = sect + MMU_RESERVED; + } + /* 0x04_0000_0000 - 0x07_FFFF_FFFF */ + /* 8GB PL, 8GB PCIe */ + for (; i < 0x020; i++, sect += 0x40000000) { + mmu_tbl1[i] = sect + MMU_DEVICE; + } + /* 0x08_0000_0000 - 0x0F_7FFF_FFFF */ + /* 2GB DDR */ +#define DDR_1_SIZE 0x80000000u +#define DDR_1_REG (DDR_1_SIZE/0x40000000) + for (; i < (0x020 + DDR_1_REG); i++, sect += 0x40000000) { + mmu_tbl1[i] = sect + MMU_MEMORY; + } +#if DDR_1_REG < 0x20 + /* reserved for region where DDR is absent */ + for (; i < 0x040; i++, sect += 0x40000000) { + mmu_tbl1[i] = sect + MMU_RESERVED; + } +#endif + /* 0x10_0000_0000 - 0x7F_FFFF_FFFF */ + /* 448GB PL */ + for (; i < 0x200; i++, sect += 0x40000000) { + mmu_tbl1[i] = sect + MMU_DEVICE; + } + /* 0x80_0000_0000 - 0xBF_FFFF_FFFF */ + /* 256GB PCIe */ + for (; i < 0x300; i++, sect += 0x40000000) { + mmu_tbl1[i] = sect + MMU_DEVICE; + } + /* 0xC0_0000_0000 - 0xFF_FFFF_FFFF */ + /* 256GB reserved */ + for (; i < 0x400; i++, sect += 0x40000000) { + mmu_tbl1[i] = sect + MMU_RESERVED; + } + + sect = 0; + i = 0; + /* 0x0000_0000 - 0x7FFF_FFFF */ + /* 2GB DDR */ +#define DDR_0_SIZE 0x80000000u +#define DDR_0_REG (DDR_0_SIZE/0x200000) + for (; i < DDR_0_REG; i++, sect += 0x200000) { + mmu_tbl2[i] = sect + MMU_MEMORY; + } + /* reserved for region where DDR is absent */ + for (; i < 0x400; i++, sect += 0x200000) { + mmu_tbl2[i] = sect + MMU_RESERVED; + } + /* 0x8000_0000 - 0xBFFF_FFFF */ + /* 1GB lower PL */ + for (; i < 0x600; i++, sect += 0x200000) { + mmu_tbl2[i] = sect + MMU_DEVICE; + } + /* 0xC000_0000 - 0xDFFF_FFFF */ + /* 512MB QSPI */ + for (; i < 0x700; i++, sect += 0x200000) { + mmu_tbl2[i] = sect + MMU_DEVICE; + } + /* 0xE000_0000 - 0xEFFF_FFFF */ + /* 256MB lower PCIe */ + for (; i < 0x780; i++, sect += 0x200000) { + mmu_tbl2[i] = sect + MMU_DEVICE; + } + /* 0xF000_0000 - 0xF7FF_FFFF */ + /* 128MB Reserved */ + for (; i < 0x7c0; i++, sect += 0x200000) { + mmu_tbl2[i] = sect + MMU_RESERVED; + } + /* 0xF800_0000 - 0xFFDF_FFFF */ + /* set all range as device */ + for (; i < 0x7ff; i++, sect += 0x200000) { + mmu_tbl2[i] = sect + MMU_DEVICE; + } + /* 0xFFE0_0000 - 0xFFFF_FFFF*/ + /* 2MB OCM/TCM */ + for (; i < 0x800; i++, sect += 0x200000) { + mmu_tbl2[i] = sect + MMU_MEMORY; + } +} + +#endif /* !TX_DCACHE_OFF */ + +/* enable MMU and caches */ +static void tx_caches_enable(void) +{ +#ifndef TX_DCACHE_OFF + /* set level 0 TTBR0_EL3 */ + __DSB_OPT(__BARRIER_SY); + __MSR(__TTBR0_EL3, (uint64_t) mmu_tbl0); + /* set memory attributes */ + __MSR(__MAIR_EL3, 0x000000BB0400FF44ull); + /* set TCR_EL3 */ + __MSR(__TCR_EL3, 0x80823518ull); + + /* set SCTLR_EL3: enable mmu and caches + SP alignment check */ + __MSR(__SCTLR_EL3, __MRS(__SCTLR_EL3) | 0x100d); + + __DSB_OPT(__BARRIER_SY); + __ISB(); +#else + /* set SCTLR_EL3: enable instruction cache + SP alignment check */ + __MSR(__SCTLR_EL3, __MRS(__SCTLR_EL3) | 0x1008); +#endif +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_platform_initialize_low_level */ +/* Zynq UltraScale+ MPSoC Cortex-A53-SMP/GHS */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes the Interrupt Controller and configures */ +/* the Generic Timer for the ThreadX periodic timer interrupt source */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_low_level ThreadX low level initialization */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +void _tx_platform_initialize_low_level(void) +{ + INIT_CBAR + int i; + +#ifndef TX_DCACHE_OFF + /* initialize MMU tables */ + mmu_tbl_init(); +#endif + /* enable data and instruction caches */ + tx_caches_enable(); + + /* set default interrupt handlers */ + for (i=0; i= IRQ_ID_MAX) + { + return; + } + + /* set handler */ + _tx_platform_irq_handlers[2*id] = (uint64_t) handler; + _tx_platform_irq_handlers[2*id+1] = (uint64_t) data; + __DSB_OPT(__BARRIER_SY); // ensure we're in sync... + + /* enable interrupt */ + GICD_ISENABLER(id>>5) = 1 << (id & 0x1f); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* tx_zynqmp_irq_disable Zynq UltraScale+ MPSoC Cortex-A53-SMP/GHS */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function disables an interrupt and removes the previously */ +/* attached handler */ +/* */ +/* INPUT */ +/* */ +/* id The ID of the interrupt */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +void tx_zynqmp_irq_disable(unsigned id) +{ + INIT_CBAR + + if (id >= IRQ_ID_MAX) + { + return; + } + + /* disable interrupt */ + GICD_ICENABLER(id>>5) = 1 << (id & 0x1f); + + /* clear pending state */ + GICD_ICPENDR(id>>5) = 1 << (id & 0x1f); + + /* ensure the interrupt is not still active before returning */ + while (GICD_ISACTIVER(id>>5) & (1 << (id & 0x1f))) + { + } + + /* restore default handler */ + _tx_platform_irq_handlers[2*id] = (uint64_t) tx_irq_default_handler; + _tx_platform_irq_handlers[2*id+1] = (uint64_t) id; +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* tx_zynqmp_irq_priority Zynq UltraScale+ MPSoC Cortex-A53-SMP/GHS */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets the priority of an interrupt */ +/* */ +/* INPUT */ +/* */ +/* id The ID of the interrupt */ +/* prio The interrupt priority 0-255 */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +void tx_zynqmp_irq_priority(unsigned id, unsigned prio) +{ + INIT_CBAR + + if (id >= IRQ_ID_MAX) + { + return; + } + + /* set priority */ + GICD_IPRIORITYB(id) = (uint8_t) prio; +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* tx_zynqmp_irq_config Zynq UltraScale+ MPSoC Cortex-A53/GHS */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function configures an interrupt as level-sensitive or */ +/* edge-triggered */ +/* Only SPI interrupts (ID >= 32) can be configured */ +/* */ +/* INPUT */ +/* */ +/* id The ID of the interrupt */ +/* edge Configure the interrupt as */ +/* level-sensitive (0) or */ +/* edge-triggered (non 0) */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +void tx_zynqmp_irq_config(unsigned id, int edge) +{ + INIT_CBAR + TX_INTERRUPT_SAVE_AREA + uint32_t value; + + if (id < 32 || id >= IRQ_ID_MAX) + { + return; + } + + TX_DISABLE + + /* set edge or level sensitive */ + value = GICD_ICFGR(id>>4); + if (edge) + { + value |= 2 << (2*(id & 0xf)); + } + else + { + value &= ~(2 << (2*(id & 0xf))); + } + GICD_ICFGR(id>>4) = value; + + TX_RESTORE +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* tx_zynqmp_irq_smp_core Zynq UltraScale+ MPSoC Cortex-A53/GHS */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function selects on which core an interrupt will be handled */ +/* Only SPI interrupts (ID >= 32) can be configured */ +/* */ +/* INPUT */ +/* */ +/* irq_id The ID of the interrupt */ +/* core_id The ID of the core 0-3 */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +void tx_zynqmp_irq_smp_core(unsigned irq_id, unsigned core_id) +{ + INIT_CBAR + + if (irq_id < 32 || irq_id >= IRQ_ID_MAX || core_id >= TX_THREAD_SMP_MAX_CORES) + { + return; + } + + /* set interrupt processor target */ + GICD_ITARGETSRB(irq_id) = 1 << core_id; +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* tx_zynqmp_udelay Zynq UltraScale+ MPSoC Cortex-A53/GHS */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a given small delay expressed in */ +/* microseconds. */ +/* */ +/* INPUT */ +/* */ +/* usecs The number of microseconds */ +/* to wait for */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +void tx_zynqmp_udelay(unsigned usecs) +{ + uint64_t t; + /* get current time */ + t = CNTPCT_READ(); + /* compute expiration time */ + t += ((uint64_t) usecs * CNTFRQ_READ()) / 1000000U; + while ((int64_t) (t - CNTPCT_READ()) > 0) {} +} diff --git a/ports_smp/cortex_a5x_smp/green/example_build/tgt/debug.gpc b/ports_smp/cortex_a5x_smp/green/example_build/tgt/debug.gpc new file mode 100644 index 00000000..5b4d1d2a --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/example_build/tgt/debug.gpc @@ -0,0 +1,8 @@ +#!gbuild +macro __BINDIR=%expand_path(bin/debug) +[Build Configuration] + -G + -Odebug + -object_dir=objs/debug + :outputDir=objs/debug + :binDir=${__BINDIR} diff --git a/ports_smp/cortex_a5x_smp/green/example_build/tgt/default.con b/ports_smp/cortex_a5x_smp/green/example_build/tgt/default.con new file mode 100644 index 00000000..23dc2861 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/example_build/tgt/default.con @@ -0,0 +1,16 @@ +target_connection.0.type="Simulator for ARM64 (simarm64)" +target_connection.0.short_type="simarm64" +target_connection.0.args=" " +target_connection.0.title="Generic-ARM64 ARM Cortex-A53 with Simulator for ARM64 (simarm64)" +target_connection.0.command="simarm64 " +target_connection.0.logfile="simarm64" +target_connection.0.log="" +target_connection.0.sane="no" +target_connection.1.type="Green Hills Debug Probe (mpserv)" +target_connection.1.short_type="mpserv" +target_connection.1.args=" " +target_connection.1.title="Generic-ARM64 ARM Cortex-A53 with Green Hills Debug Probe (mpserv)" +target_connection.1.command="mpserv " +target_connection.1.logfile="mpserv" +target_connection.1.log="" +target_connection.1.sane="no" diff --git a/ports_smp/cortex_a5x_smp/green/example_build/tgt/release.gpc b/ports_smp/cortex_a5x_smp/green/example_build/tgt/release.gpc new file mode 100644 index 00000000..8af6070d --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/example_build/tgt/release.gpc @@ -0,0 +1,9 @@ +#!gbuild +macro __BINDIR=%expand_path(bin/release) +[Build Configuration] + -G + -O + -object_dir=objs/release + :outputDir=objs/release + :binDir=${__BINDIR} + diff --git a/ports_smp/cortex_a5x_smp/green/example_build/tgt/resource_readme.txt b/ports_smp/cortex_a5x_smp/green/example_build/tgt/resource_readme.txt new file mode 100644 index 00000000..f385e446 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/example_build/tgt/resource_readme.txt @@ -0,0 +1,61 @@ +Project File (resource.gpj) +------------------------------------------------------------------------------ +The files provided in this project are resources to help get your project +running on your target. You may use these files as is or use them as examples +to create your own. + +Unless the files here are included in the project file for your executable, +they will not impact your build. + + + +Board Setup Files (.mbs) +------------------------------------------------------------------------------ +The board setup files (.mbs) are used by MULTI to initialize target hardware +before beginning a debugging session. + +The automatically-created default.con connection file (located in +default.gpj) contains connection methods that reference the .mbs files +included in resource.gpj. + +You can modify the scripts in the board setup files to suit your specific +hardware configuration and connection needs. + +For more information about board setup files and connection files, see the +"MULTI: Configuring Connections" book for your target processor. + + + +Linker Directive Files (.ld) +------------------------------------------------------------------------------ +Linker directive files (.ld) are used when your program is linked to define +program sections and assign them to specific addresses in memory. + +The linker directive file from the project file for your executable will +be used when linking. + +If the .ld file included in the project for your executable does not suit +your hardware configuration or program layout needs, it can be modified or +replaced with a custom .ld file. + + +This resource.gpj contains example linker directives files: +** standalone_ram.ld -- For programs that are linked into and run + out of RAM. +** standalone_romcopy.ld -- For programs that are linked into ROM, but + run out of RAM. +** standalone_romrun.ld -- For programs that are linked into and run + out of ROM. + +Some configurations also contain other linker directives files: +** standalone_romdebug.ld -- For programs that are linked into and run + out of ROM with enhanced debugging capabilities. +** standalone_pic.ld -- For programs built with position independent + code. +** standalone_pid.ld -- For programs built with position independent + data. +** standalone_picpid.ld -- For programs built with position independent + code and data. + +For more information about linker directives files, see the "MULTI: Building +Applications" book for your processor. diff --git a/ports_smp/cortex_a5x_smp/green/example_build/tgt/resources.gpj b/ports_smp/cortex_a5x_smp/green/example_build/tgt/resources.gpj new file mode 100644 index 00000000..8200a470 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/example_build/tgt/resources.gpj @@ -0,0 +1,10 @@ +#!gbuild +#component target_resources +[Project] +default.con +resource_readme.txt +debug.gpc +release.gpc +standalone_ram.ld +standalone_romcopy.ld +standalone_romrun.ld diff --git a/ports_smp/cortex_a5x_smp/green/example_build/tgt/standalone_ram.ld b/ports_smp/cortex_a5x_smp/green/example_build/tgt/standalone_ram.ld new file mode 100644 index 00000000..2fbaebda --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/example_build/tgt/standalone_ram.ld @@ -0,0 +1,70 @@ +// +// memory map for the Xilinx ZCU102 with 2GB or SDRAM +// +MEMORY { + dram_rsvd1 : ORIGIN = 0x0000000000, LENGTH = 0 + dram_memory : ORIGIN = ., LENGTH = 2048M + dram_rsvd2 : ORIGIN = ., LENGTH = 0 +} +DEFAULTS { + + heap_reserve = 8M + stack_reserve = 16K + stack_1_3_reserve = 16K + +} +// +// Program layout for running out of RAM. +// +// + +SECTIONS +{ + +// +// The text segment +// + .vectors : > dram_memory + .boot : > . + .text : > . + .syscall : > . + .fixaddr : > . + .fixtype : > . + .rodata : > . + .secinfo : > . + +// +// The data segment +// + .data : > . + .bss : > . + .ghcovfz CLEAR : > . + .ghcovcz CLEAR : > . + .ghcovdz CLEAR : > . + + .mmu_tbl0 ALIGN(4096) : > . + .mmu_tbl1 ALIGN(4096) : > . + .mmu_tbl2 ALIGN(4096) : > . + + .stack ALIGN(16) PAD(stack_reserve) : > . + __el3_stack = .; + .stack_1 ALIGN(16) PAD(stack_1_3_reserve) : > . + __el3_1_stack = .; + .stack_2 ALIGN(16) PAD(stack_1_3_reserve) : > . + __el3_2_stack = .; + .stack_3 ALIGN(16) PAD(stack_1_3_reserve) : > . + __el3_3_stack = .; + .heap ALIGN(16) PAD(heap_reserve) : > . + + __ghsbegin_free_mem = .; + +// +// These special symbols mark the bounds of RAM and ROM memory. +// They are used by the MULTI debugger. +// +// __ghs_romstart = MEMADDR(flash_rsvd1); +// __ghs_romend = MEMENDADDR(flash_rsvd2); + __ghs_ramstart = MEMADDR(dram_rsvd1); + __ghs_ramend = MEMENDADDR(dram_rsvd2); + +} diff --git a/ports_smp/cortex_a5x_smp/green/example_build/tgt/standalone_romcopy.ld b/ports_smp/cortex_a5x_smp/green/example_build/tgt/standalone_romcopy.ld new file mode 100644 index 00000000..af8e0815 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/example_build/tgt/standalone_romcopy.ld @@ -0,0 +1,90 @@ +MEMORY { + flash_rsvd1 : ORIGIN = 0x10000000, LENGTH = 0 + flash_memory : ORIGIN = ., LENGTH = 128M + flash_rsvd2 : ORIGIN = ., LENGTH = 0 + + dram_rsvd1 : ORIGIN = 0x20000000, LENGTH = 0 + dram_memory : ORIGIN = ., LENGTH = 256M + dram_rsvd2 : ORIGIN = ., LENGTH = 0 +} +DEFAULTS { + + heap_reserve = 8M + stack_reserve = 1M + +} +// +// Program layout for starting in ROM, copying test and data to RAM, +// and then running out of RAM. +// + +SECTIONS +{ + +// +// ROM SECTIONS +// + + // The order and relative offsets of these + // ROM startup code sections must be the + // same in both the ROM and RAM copies. + .ROM.boottext ROM(.boottext ) : > flash_memory + .ROM.syscall ROM(.syscall) : > . + + .rodata : > flash_memory + .secinfo : > . + .fixaddr : > . + .fixtype : > . + + .CROM.data CROM(.data) : > . + .CROM.text CROM(.text) : > . + +// +// RAM SECTIONS +// + + .boottext : { + // All .text which is reachable between + // _start and __ghs_ind_crt1 needs to be + // pulled into .boottext and left uncompressed. + crt0.o(.text) + libboardinit.a(*)(.text) // optional library + libstartup.a(*)(.text) + libsys.a(ind_crt1.o)(.text) + } > dram_memory + .syscall : > . + .text : > . + + .data : > . + .bss : > . + .ghcovfz CLEAR : > . + .ghcovcz CLEAR : > . + .ghcovdz CLEAR : > . + .heap ALIGN(16) PAD(heap_reserve) : > . + .stack ALIGN(16) PAD(stack_reserve) : > . + +// +// These special symbols mark the bounds of RAM and ROM images of boot code. +// They are used by the GHS startup code (_start and __ghs_ind_crt0). +// + __ghs_rombootcodestart = ADDR(.ROM.boottext); + __ghs_rombootcodeend = ENDADDR(.fixtype); + __ghs_rambootcodestart = ADDR(.boottext); + __ghs_rambootcodeend = ENDADDR(.stack); + +// +// These special symbols mark the bounds of RAM and ROM memory. +// They are used by the MULTI debugger. +// + __ghs_romstart = MEMADDR(flash_rsvd1); + __ghs_romend = MEMENDADDR(flash_rsvd2); + __ghs_ramstart = MEMADDR(dram_rsvd1); + __ghs_ramend = MEMENDADDR(dram_rsvd2); + +// +// This special symbol marks the the first address executed after the +// ROM to RAM copy is complete. It is used by the MULTI debugger. +// + __ghs_after_romcopy = __ghs_ind_crt1; +} + diff --git a/ports_smp/cortex_a5x_smp/green/example_build/tgt/standalone_romrun.ld b/ports_smp/cortex_a5x_smp/green/example_build/tgt/standalone_romrun.ld new file mode 100644 index 00000000..0f01e6cc --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/example_build/tgt/standalone_romrun.ld @@ -0,0 +1,69 @@ +MEMORY { + flash_rsvd1 : ORIGIN = 0x10000000, LENGTH = 0 + flash_memory : ORIGIN = ., LENGTH = 128M + flash_rsvd2 : ORIGIN = ., LENGTH = 0 + + dram_rsvd1 : ORIGIN = 0x20000000, LENGTH = 0 + dram_memory : ORIGIN = ., LENGTH = 256M + dram_rsvd2 : ORIGIN = ., LENGTH = 0 +} +DEFAULTS { + + heap_reserve = 8M + stack_reserve = 1M + +} +// +// Program layout for starting in ROM, copying data to RAM, +// and continuing to execute out of ROM. +// + +SECTIONS +{ + +// +// ROM SECTIONS +// + + .text : > flash_memory + .syscall : > . + .rodata : > . + .secinfo : > . + .fixaddr : > . + .fixtype : > . + + .CROM.data CROM(.data) : > . + +// +// RAM SECTIONS +// + + .data : > dram_memory + .bss : > . + .ghcovfz CLEAR : > . + .ghcovcz CLEAR : > . + .ghcovdz CLEAR : > . + .heap ALIGN(16) PAD(heap_reserve) : > . + .stack ALIGN(16) PAD(stack_reserve) : > . + + +// +// These special symbols mark the bounds of RAM and ROM memory. +// They are used by the MULTI debugger. +// + __ghs_romstart = MEMADDR(flash_rsvd1); + __ghs_romend = MEMENDADDR(flash_rsvd2); + __ghs_ramstart = MEMADDR(dram_rsvd1); + __ghs_ramend = MEMENDADDR(dram_rsvd2); + +// +// These special symbols mark the bounds of RAM and ROM images of boot code. +// They are used by the GHS startup code (_start and __ghs_ind_crt0). +// + __ghs_rombootcodestart = ADDR(.text); + __ghs_rombootcodeend = ENDADDR(.fixtype); + __ghs_rambootcodestart = 0; + __ghs_rambootcodeend = 0; + +} + diff --git a/ports_smp/cortex_a5x_smp/green/example_build/tx/libtx.gpj b/ports_smp/cortex_a5x_smp/green/example_build/tx/libtx.gpj new file mode 100644 index 00000000..6cdf4f5d --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/example_build/tx/libtx.gpj @@ -0,0 +1,235 @@ +#!gbuild +[Library] + -object_dir=objs\libtx + -I../../../../../common_smp/inc + -I../../inc +..\..\..\..\..\common_smp\inc\tx_api.h +..\..\..\..\..\common_smp\inc\tx_block_pool.h +..\..\..\..\..\common_smp\inc\tx_byte_pool.h +..\..\..\..\..\common_smp\inc\tx_event_flags.h +..\..\..\..\..\common_smp\inc\tx_initialize.h +..\..\..\..\..\common_smp\inc\tx_mutex.h +..\..\..\..\..\common_smp\inc\tx_queue.h +..\..\..\..\..\common_smp\inc\tx_semaphore.h +..\..\..\..\..\common_smp\inc\tx_thread.h +..\..\..\..\..\common_smp\inc\tx_timer.h +..\..\..\..\..\common_smp\inc\tx_trace.h +..\..\..\..\..\common_smp\inc\tx_user.h +..\..\inc\tx_el.h +..\..\inc\tx_ghs.h +..\..\inc\tx_port.h +..\..\src\tx_ghs.c +..\..\src\tx_initialize_low_level.a64 +..\..\src\tx_thread_context_restore.a64 +..\..\src\tx_thread_context_save.a64 +..\..\src\tx_thread_fp_disable.c +..\..\src\tx_thread_fp_enable.c +..\..\src\tx_thread_interrupt_control.a64 +..\..\src\tx_thread_interrupt_disable.a64 +..\..\src\tx_thread_interrupt_restore.a64 +..\..\src\tx_thread_schedule.a64 +..\..\src\tx_thread_smp_core_get.a64 +..\..\src\tx_thread_smp_core_preempt.a64 +..\..\src\tx_thread_smp_current_state_get.a64 +..\..\src\tx_thread_smp_current_thread_get.a64 +..\..\src\tx_thread_smp_initialize_wait.a64 +..\..\src\tx_thread_smp_low_level_initialize.a64 +..\..\src\tx_thread_smp_protect.a64 +..\..\src\tx_thread_smp_time_get.a64 +..\..\src\tx_thread_smp_unprotect.a64 +..\..\src\tx_thread_stack_build.a64 +..\..\src\tx_thread_system_return.a64 +..\..\src\tx_thread_timeout.c +..\..\src\tx_timer_interrupt.a64 +..\..\..\..\..\common_smp\src\tx_block_allocate.c +..\..\..\..\..\common_smp\src\tx_block_pool_cleanup.c +..\..\..\..\..\common_smp\src\tx_block_pool_create.c +..\..\..\..\..\common_smp\src\tx_block_pool_delete.c +..\..\..\..\..\common_smp\src\tx_block_pool_info_get.c +..\..\..\..\..\common_smp\src\tx_block_pool_initialize.c +..\..\..\..\..\common_smp\src\tx_block_pool_performance_info_get.c +..\..\..\..\..\common_smp\src\tx_block_pool_performance_system_info_get.c +..\..\..\..\..\common_smp\src\tx_block_pool_prioritize.c +..\..\..\..\..\common_smp\src\tx_block_release.c +..\..\..\..\..\common_smp\src\tx_byte_allocate.c +..\..\..\..\..\common_smp\src\tx_byte_pool_cleanup.c +..\..\..\..\..\common_smp\src\tx_byte_pool_create.c +..\..\..\..\..\common_smp\src\tx_byte_pool_delete.c +..\..\..\..\..\common_smp\src\tx_byte_pool_info_get.c +..\..\..\..\..\common_smp\src\tx_byte_pool_initialize.c +..\..\..\..\..\common_smp\src\tx_byte_pool_performance_info_get.c +..\..\..\..\..\common_smp\src\tx_byte_pool_performance_system_info_get.c +..\..\..\..\..\common_smp\src\tx_byte_pool_prioritize.c +..\..\..\..\..\common_smp\src\tx_byte_pool_search.c +..\..\..\..\..\common_smp\src\tx_byte_release.c +..\..\..\..\..\common_smp\src\tx_event_flags_cleanup.c +..\..\..\..\..\common_smp\src\tx_event_flags_create.c +..\..\..\..\..\common_smp\src\tx_event_flags_delete.c +..\..\..\..\..\common_smp\src\tx_event_flags_get.c +..\..\..\..\..\common_smp\src\tx_event_flags_info_get.c +..\..\..\..\..\common_smp\src\tx_event_flags_initialize.c +..\..\..\..\..\common_smp\src\tx_event_flags_performance_info_get.c +..\..\..\..\..\common_smp\src\tx_event_flags_performance_system_info_get.c +..\..\..\..\..\common_smp\src\tx_event_flags_set.c +..\..\..\..\..\common_smp\src\tx_event_flags_set_notify.c +..\..\..\..\..\common_smp\src\tx_initialize_high_level.c +..\..\..\..\..\common_smp\src\tx_initialize_kernel_enter.c +..\..\..\..\..\common_smp\src\tx_initialize_kernel_setup.c +..\..\..\..\..\common_smp\src\tx_mutex_cleanup.c +..\..\..\..\..\common_smp\src\tx_mutex_create.c +..\..\..\..\..\common_smp\src\tx_mutex_delete.c +..\..\..\..\..\common_smp\src\tx_mutex_get.c +..\..\..\..\..\common_smp\src\tx_mutex_info_get.c +..\..\..\..\..\common_smp\src\tx_mutex_initialize.c +..\..\..\..\..\common_smp\src\tx_mutex_performance_info_get.c +..\..\..\..\..\common_smp\src\tx_mutex_performance_system_info_get.c +..\..\..\..\..\common_smp\src\tx_mutex_prioritize.c +..\..\..\..\..\common_smp\src\tx_mutex_priority_change.c +..\..\..\..\..\common_smp\src\tx_mutex_put.c +..\..\..\..\..\common_smp\src\tx_queue_cleanup.c +..\..\..\..\..\common_smp\src\tx_queue_create.c +..\..\..\..\..\common_smp\src\tx_queue_delete.c +..\..\..\..\..\common_smp\src\tx_queue_flush.c +..\..\..\..\..\common_smp\src\tx_queue_front_send.c +..\..\..\..\..\common_smp\src\tx_queue_info_get.c +..\..\..\..\..\common_smp\src\tx_queue_initialize.c +..\..\..\..\..\common_smp\src\tx_queue_performance_info_get.c +..\..\..\..\..\common_smp\src\tx_queue_performance_system_info_get.c +..\..\..\..\..\common_smp\src\tx_queue_prioritize.c +..\..\..\..\..\common_smp\src\tx_queue_receive.c +..\..\..\..\..\common_smp\src\tx_queue_send.c +..\..\..\..\..\common_smp\src\tx_queue_send_notify.c +..\..\..\..\..\common_smp\src\tx_semaphore_ceiling_put.c +..\..\..\..\..\common_smp\src\tx_semaphore_cleanup.c +..\..\..\..\..\common_smp\src\tx_semaphore_create.c +..\..\..\..\..\common_smp\src\tx_semaphore_delete.c +..\..\..\..\..\common_smp\src\tx_semaphore_get.c +..\..\..\..\..\common_smp\src\tx_semaphore_info_get.c +..\..\..\..\..\common_smp\src\tx_semaphore_initialize.c +..\..\..\..\..\common_smp\src\tx_semaphore_performance_info_get.c +..\..\..\..\..\common_smp\src\tx_semaphore_performance_system_info_get.c +..\..\..\..\..\common_smp\src\tx_semaphore_prioritize.c +..\..\..\..\..\common_smp\src\tx_semaphore_put.c +..\..\..\..\..\common_smp\src\tx_semaphore_put_notify.c +..\..\..\..\..\common_smp\src\tx_thread_create.c +..\..\..\..\..\common_smp\src\tx_thread_delete.c +..\..\..\..\..\common_smp\src\tx_thread_entry_exit_notify.c +..\..\..\..\..\common_smp\src\tx_thread_identify.c +..\..\..\..\..\common_smp\src\tx_thread_info_get.c +..\..\..\..\..\common_smp\src\tx_thread_initialize.c +..\..\..\..\..\common_smp\src\tx_thread_performance_info_get.c +..\..\..\..\..\common_smp\src\tx_thread_performance_system_info_get.c +..\..\..\..\..\common_smp\src\tx_thread_preemption_change.c +..\..\..\..\..\common_smp\src\tx_thread_priority_change.c +..\..\..\..\..\common_smp\src\tx_thread_relinquish.c +..\..\..\..\..\common_smp\src\tx_thread_reset.c +..\..\..\..\..\common_smp\src\tx_thread_resume.c +..\..\..\..\..\common_smp\src\tx_thread_shell_entry.c +..\..\..\..\..\common_smp\src\tx_thread_sleep.c +..\..\..\..\..\common_smp\src\tx_thread_smp_core_exclude.c +..\..\..\..\..\common_smp\src\tx_thread_smp_core_exclude_get.c +..\..\..\..\..\common_smp\src\tx_thread_smp_current_state_set.c +..\..\..\..\..\common_smp\src\tx_thread_smp_debug_entry_insert.c +..\..\..\..\..\common_smp\src\tx_thread_smp_high_level_initialize.c +..\..\..\..\..\common_smp\src\tx_thread_smp_rebalance_execute_list.c +..\..\..\..\..\common_smp\src\tx_thread_smp_utilities.c +..\..\..\..\..\common_smp\src\tx_thread_stack_analyze.c +..\..\..\..\..\common_smp\src\tx_thread_stack_error_handler.c +..\..\..\..\..\common_smp\src\tx_thread_stack_error_notify.c +..\..\..\..\..\common_smp\src\tx_thread_suspend.c +..\..\..\..\..\common_smp\src\tx_thread_system_preempt_check.c +..\..\..\..\..\common_smp\src\tx_thread_system_resume.c +..\..\..\..\..\common_smp\src\tx_thread_system_suspend.c +..\..\..\..\..\common_smp\src\tx_thread_terminate.c +..\..\..\..\..\common_smp\src\tx_thread_time_slice.c +..\..\..\..\..\common_smp\src\tx_thread_time_slice_change.c +..\..\..\..\..\common_smp\src\tx_thread_wait_abort.c +..\..\..\..\..\common_smp\src\tx_time_get.c +..\..\..\..\..\common_smp\src\tx_time_set.c +..\..\..\..\..\common_smp\src\tx_timer_activate.c +..\..\..\..\..\common_smp\src\tx_timer_change.c +..\..\..\..\..\common_smp\src\tx_timer_create.c +..\..\..\..\..\common_smp\src\tx_timer_deactivate.c +..\..\..\..\..\common_smp\src\tx_timer_delete.c +..\..\..\..\..\common_smp\src\tx_timer_expiration_process.c +..\..\..\..\..\common_smp\src\tx_timer_info_get.c +..\..\..\..\..\common_smp\src\tx_timer_initialize.c +..\..\..\..\..\common_smp\src\tx_timer_performance_info_get.c +..\..\..\..\..\common_smp\src\tx_timer_performance_system_info_get.c +..\..\..\..\..\common_smp\src\tx_timer_smp_core_exclude.c +..\..\..\..\..\common_smp\src\tx_timer_smp_core_exclude_get.c +..\..\..\..\..\common_smp\src\tx_timer_system_activate.c +..\..\..\..\..\common_smp\src\tx_timer_system_deactivate.c +..\..\..\..\..\common_smp\src\tx_timer_thread_entry.c +..\..\..\..\..\common_smp\src\tx_trace_buffer_full_notify.c +..\..\..\..\..\common_smp\src\tx_trace_disable.c +..\..\..\..\..\common_smp\src\tx_trace_enable.c +..\..\..\..\..\common_smp\src\tx_trace_event_filter.c +..\..\..\..\..\common_smp\src\tx_trace_event_unfilter.c +..\..\..\..\..\common_smp\src\tx_trace_initialize.c +..\..\..\..\..\common_smp\src\tx_trace_interrupt_control.c +..\..\..\..\..\common_smp\src\tx_trace_isr_enter_insert.c +..\..\..\..\..\common_smp\src\tx_trace_isr_exit_insert.c +..\..\..\..\..\common_smp\src\tx_trace_object_register.c +..\..\..\..\..\common_smp\src\tx_trace_object_unregister.c +..\..\..\..\..\common_smp\src\tx_trace_user_event_insert.c +..\..\..\..\..\common_smp\src\txe_block_allocate.c +..\..\..\..\..\common_smp\src\txe_block_pool_create.c +..\..\..\..\..\common_smp\src\txe_block_pool_delete.c +..\..\..\..\..\common_smp\src\txe_block_pool_info_get.c +..\..\..\..\..\common_smp\src\txe_block_pool_prioritize.c +..\..\..\..\..\common_smp\src\txe_block_release.c +..\..\..\..\..\common_smp\src\txe_byte_allocate.c +..\..\..\..\..\common_smp\src\txe_byte_pool_create.c +..\..\..\..\..\common_smp\src\txe_byte_pool_delete.c +..\..\..\..\..\common_smp\src\txe_byte_pool_info_get.c +..\..\..\..\..\common_smp\src\txe_byte_pool_prioritize.c +..\..\..\..\..\common_smp\src\txe_byte_release.c +..\..\..\..\..\common_smp\src\txe_event_flags_create.c +..\..\..\..\..\common_smp\src\txe_event_flags_delete.c +..\..\..\..\..\common_smp\src\txe_event_flags_get.c +..\..\..\..\..\common_smp\src\txe_event_flags_info_get.c +..\..\..\..\..\common_smp\src\txe_event_flags_set.c +..\..\..\..\..\common_smp\src\txe_event_flags_set_notify.c +..\..\..\..\..\common_smp\src\txe_mutex_create.c +..\..\..\..\..\common_smp\src\txe_mutex_delete.c +..\..\..\..\..\common_smp\src\txe_mutex_get.c +..\..\..\..\..\common_smp\src\txe_mutex_info_get.c +..\..\..\..\..\common_smp\src\txe_mutex_prioritize.c +..\..\..\..\..\common_smp\src\txe_mutex_put.c +..\..\..\..\..\common_smp\src\txe_queue_create.c +..\..\..\..\..\common_smp\src\txe_queue_delete.c +..\..\..\..\..\common_smp\src\txe_queue_flush.c +..\..\..\..\..\common_smp\src\txe_queue_front_send.c +..\..\..\..\..\common_smp\src\txe_queue_info_get.c +..\..\..\..\..\common_smp\src\txe_queue_prioritize.c +..\..\..\..\..\common_smp\src\txe_queue_receive.c +..\..\..\..\..\common_smp\src\txe_queue_send.c +..\..\..\..\..\common_smp\src\txe_queue_send_notify.c +..\..\..\..\..\common_smp\src\txe_semaphore_ceiling_put.c +..\..\..\..\..\common_smp\src\txe_semaphore_create.c +..\..\..\..\..\common_smp\src\txe_semaphore_delete.c +..\..\..\..\..\common_smp\src\txe_semaphore_get.c +..\..\..\..\..\common_smp\src\txe_semaphore_info_get.c +..\..\..\..\..\common_smp\src\txe_semaphore_prioritize.c +..\..\..\..\..\common_smp\src\txe_semaphore_put.c +..\..\..\..\..\common_smp\src\txe_semaphore_put_notify.c +..\..\..\..\..\common_smp\src\txe_thread_create.c +..\..\..\..\..\common_smp\src\txe_thread_delete.c +..\..\..\..\..\common_smp\src\txe_thread_entry_exit_notify.c +..\..\..\..\..\common_smp\src\txe_thread_info_get.c +..\..\..\..\..\common_smp\src\txe_thread_preemption_change.c +..\..\..\..\..\common_smp\src\txe_thread_priority_change.c +..\..\..\..\..\common_smp\src\txe_thread_relinquish.c +..\..\..\..\..\common_smp\src\txe_thread_reset.c +..\..\..\..\..\common_smp\src\txe_thread_resume.c +..\..\..\..\..\common_smp\src\txe_thread_suspend.c +..\..\..\..\..\common_smp\src\txe_thread_terminate.c +..\..\..\..\..\common_smp\src\txe_thread_time_slice_change.c +..\..\..\..\..\common_smp\src\txe_thread_wait_abort.c +..\..\..\..\..\common_smp\src\txe_timer_activate.c +..\..\..\..\..\common_smp\src\txe_timer_change.c +..\..\..\..\..\common_smp\src\txe_timer_create.c +..\..\..\..\..\common_smp\src\txe_timer_deactivate.c +..\..\..\..\..\common_smp\src\txe_timer_delete.c +..\..\..\..\..\common_smp\src\txe_timer_info_get.c diff --git a/ports_smp/cortex_a5x_smp/green/inc/tx_el.h b/ports_smp/cortex_a5x_smp/green/inc/tx_el.h new file mode 100644 index 00000000..5cb71ea5 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/inc/tx_el.h @@ -0,0 +1,764 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** ThreadX/GHS Event Log (EL) */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* tx_el.h PORTABLE SMP */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the ThreadX event log functions for the GHS MULTI */ +/* EventAnalyzer. It is assumed that tx_api.h and tx_port.h have */ +/* already been included. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_EL_H +#define TX_EL_H + + +/* Define Event Log specific data definitions. */ + +#define TX_EL_VERSION_ID 2 /* Event log version ID */ +#define TX_EL_HEADER_SIZE 24 /* Event log header size */ +#define TX_EL_TNIS 16 /* Number of thread names supported */ + /* If the application needs to */ + /* track more thread names, just */ + /* increase this number and re- */ + /* build the ThreadX library. */ +#define TX_EL_TNI_ENTRY_SIZE 44 /* Thread name entries are 44 bytes */ +#define TX_EL_TNI_NAME_SIZE 34 /* Thread name size in TNI */ +#define TX_EL_NO_MORE_TNI_ROOM 1 /* Error return from thread register*/ +#define TX_EL_NAME_NOT_FOUND 2 /* Error return from un-register */ +#define TX_EL_EVENT_SIZE 32 /* Number of bytes in each event */ +#define TX_EL_VALID_ENTRY 1 /* Valid log entry */ +#define TX_EL_INVALID_ENTRY 0 /* Invalid log entry */ + + +/* Define necessary offsets. */ + +#define TX_EL_TNI_VALID_OFFSET 34 +#define TX_EL_TNI_THREAD_ID_OFFSET 36 +#define TX_EL_TNI_THREAD_PRIORITY_OFF 40 +#define TX_EL_EVENT_TYPE_OFFSET 0 +#define TX_EL_EVENT_SUBTYPE_OFFSET 2 +#define TX_EL_EVENT_TIME_UPPER_OFFSET 4 +#define TX_EL_EVENT_TIME_LOWER_OFFSET 8 +#define TX_EL_EVENT_THREAD_OFFSET 12 +#define TX_EL_EVENT_INFO_1_OFFSET 16 +#define TX_EL_EVENT_INFO_2_OFFSET 20 +#define TX_EL_EVENT_INFO_3_OFFSET 24 +#define TX_EL_EVENT_INFO_4_OFFSET 28 + + +/* Undefine constants that might be been defined previously by tx_api.h. */ + +#undef TX_EL_INITIALIZE +#undef TX_EL_THREAD_REGISTER +#undef TX_EL_THREAD_UNREGISTER +#undef TX_EL_THREAD_STATUS_CHANGE_INSERT +#undef TX_EL_BYTE_ALLOCATE_INSERT +#undef TX_EL_BYTE_POOL_CREATE_INSERT +#undef TX_EL_BYTE_POOL_DELETE_INSERT +#undef TX_EL_BYTE_RELEASE_INSERT +#undef TX_EL_BLOCK_ALLOCATE_INSERT +#undef TX_EL_BLOCK_POOL_CREATE_INSERT +#undef TX_EL_BLOCK_POOL_DELETE_INSERT +#undef TX_EL_BLOCK_RELEASE_INSERT +#undef TX_EL_EVENT_FLAGS_CREATE_INSERT +#undef TX_EL_EVENT_FLAGS_DELETE_INSERT +#undef TX_EL_EVENT_FLAGS_GET_INSERT +#undef TX_EL_EVENT_FLAGS_SET_INSERT +#undef TX_EL_INTERRUPT_CONTROL_INSERT +#undef TX_EL_QUEUE_CREATE_INSERT +#undef TX_EL_QUEUE_DELETE_INSERT +#undef TX_EL_QUEUE_FLUSH_INSERT +#undef TX_EL_QUEUE_RECEIVE_INSERT +#undef TX_EL_QUEUE_SEND_INSERT +#undef TX_EL_SEMAPHORE_CREATE_INSERT +#undef TX_EL_SEMAPHORE_DELETE_INSERT +#undef TX_EL_SEMAPHORE_GET_INSERT +#undef TX_EL_SEMAPHORE_PUT_INSERT +#undef TX_EL_THREAD_CREATE_INSERT +#undef TX_EL_THREAD_DELETE_INSERT +#undef TX_EL_THREAD_IDENTIFY_INSERT +#undef TX_EL_THREAD_PREEMPTION_CHANGE_INSERT +#undef TX_EL_THREAD_PRIORITY_CHANGE_INSERT +#undef TX_EL_THREAD_RELINQUISH_INSERT +#undef TX_EL_THREAD_RESUME_INSERT +#undef TX_EL_THREAD_SLEEP_INSERT +#undef TX_EL_THREAD_SUSPEND_INSERT +#undef TX_EL_THREAD_TERMINATE_INSERT +#undef TX_EL_THREAD_TIME_SLICE_CHANGE_INSERT +#undef TX_EL_TIME_GET_INSERT +#undef TX_EL_TIME_SET_INSERT +#undef TX_EL_TIMER_ACTIVATE_INSERT +#undef TX_EL_TIMER_CHANGE_INSERT +#undef TX_EL_TIMER_CREATE_INSERT +#undef TX_EL_TIMER_DEACTIVATE_INSERT +#undef TX_EL_TIMER_DELETE_INSERT +#undef TX_EL_BLOCK_POOL_INFO_GET_INSERT +#undef TX_EL_BLOCK_POOL_PRIORITIZE_INSERT +#undef TX_EL_BYTE_POOL_INFO_GET_INSERT +#undef TX_EL_BYTE_POOL_PRIORITIZE_INSERT +#undef TX_EL_EVENT_FLAGS_INFO_GET_INSERT +#undef TX_EL_MUTEX_CREATE_INSERT +#undef TX_EL_MUTEX_DELETE_INSERT +#undef TX_EL_MUTEX_GET_INSERT +#undef TX_EL_MUTEX_INFO_GET_INSERT +#undef TX_EL_MUTEX_PRIORITIZE_INSERT +#undef TX_EL_MUTEX_PUT_INSERT +#undef TX_EL_QUEUE_INFO_GET_INSERT +#undef TX_EL_QUEUE_FRONT_SEND_INSERT +#undef TX_EL_QUEUE_PRIORITIZE_INSERT +#undef TX_EL_SEMAPHORE_INFO_GET_INSERT +#undef TX_EL_SEMAPHORE_PRIORITIZE_INSERT +#undef TX_EL_THREAD_INFO_GET_INSERT +#undef TX_EL_THREAD_WAIT_ABORT_INSERT +#undef TX_EL_TIMER_INFO_GET_INSERT +#undef TX_EL_BLOCK_POOL_PERFORMANCE_INFO_GET_INSERT +#undef TX_EL_BLOCK_POOL_PERFORMANCE_SYSTEM_INFO_GET_INSERT +#undef TX_EL_BYTE_POOL_PERFORMANCE_INFO_GET_INSERT +#undef TX_EL_BYTE_POOL_PERFORMANCE_SYSTEM_INFO_GET_INSERT +#undef TX_EL_EVENT_FLAGS_PERFORMANCE_INFO_GET_INSERT +#undef TX_EL_EVENT_FLAGS_PERFORMANCE_SYSTEM_INFO_GET_INSERT +#undef TX_EL_EVENT_FLAGS_SET_NOTIFY_INSERT +#undef TX_EL_MUTEX_PERFORMANCE_INFO_GET_INSERT +#undef TX_EL_MUTEX_PERFORMANCE_SYSTEM_INFO_GET_INSERT +#undef TX_EL_QUEUE_PERFORMANCE_INFO_GET_INSERT +#undef TX_EL_QUEUE_PERFORMANCE_SYSTEM_INFO_GET_INSERT +#undef TX_EL_QUEUE_SEND_NOTIFY_INSERT +#undef TX_EL_SEMAPHORE_CEILING_PUT_INSERT +#undef TX_EL_SEMAPHORE_PERFORMANCE_INFO_GET_INSERT +#undef TX_EL_SEMAPHORE_PERFORMANCE_SYSTEM_INFO_GET_INSERT +#undef TX_EL_SEMAPHORE_PUT_NOTIFY_INSERT +#undef TX_EL_THREAD_ENTRY_EXIT_NOTIFY_INSERT +#undef TX_EL_THREAD_RESET_INSERT +#undef TX_EL_THREAD_PERFORMANCE_INFO_GET_INSERT +#undef TX_EL_THREAD_PERFORMANCE_SYSTEM_INFO_GET_INSERT +#undef TX_EL_THREAD_STACK_ERROR_NOTIFY_INSERT +#undef TX_EL_TIMER_PERFORMANCE_INFO_GET_INSERT +#undef TX_EL_TIMER_PERFORMANCE_SYSTEM_INFO_GET_INSERT + + +/* Define Event Types. */ + +#define TX_EL_THREAD_CHANGE 1 +#define TX_EL_INTERRUPT 2 +#define TX_EL_THREADX_CALL 3 +#define TX_EL_USER_EVENT 4 +#define TX_EL_THREAD_STATUS_CHANGE 5 +#define TX_EL_REFRESH 6 /* Not implemented */ +#define TX_EL_TIMER 7 /* Not implemented */ +#define TX_EL_TIMESOURCE_DELTA 8 /* Not implemented */ + + +/* Define TX_EL_THREADX_CALL event sub-types. */ + +#define TX_EL_BYTE_ALLOCATE 0 +#define TX_EL_BYTE_POOL_CREATE 1 +#define TX_EL_BYTE_POOL_DELETE 2 +#define TX_EL_BYTE_RELEASE 3 +#define TX_EL_BLOCK_ALLOCATE 4 +#define TX_EL_BLOCK_POOL_CREATE 5 +#define TX_EL_BLOCK_POOL_DELETE 6 +#define TX_EL_BLOCK_RELEASE 7 +#define TX_EL_EVENT_FLAGS_CREATE 8 +#define TX_EL_EVENT_FLAGS_DELETE 9 +#define TX_EL_EVENT_FLAGS_GET 10 +#define TX_EL_EVENT_FLAGS_SET 11 +#define TX_EL_INTERRUPT_CONTROL 12 +#define TX_EL_QUEUE_CREATE 13 +#define TX_EL_QUEUE_DELETE 14 +#define TX_EL_QUEUE_FLUSH 15 +#define TX_EL_QUEUE_RECEIVE 16 +#define TX_EL_QUEUE_SEND 17 +#define TX_EL_SEMAPHORE_CREATE 18 +#define TX_EL_SEMAPHORE_DELETE 19 +#define TX_EL_SEMAPHORE_GET 20 +#define TX_EL_SEMAPHORE_PUT 21 +#define TX_EL_THREAD_CREATE 22 +#define TX_EL_THREAD_DELETE 23 +#define TX_EL_THREAD_IDENTIFY 24 +#define TX_EL_THREAD_PREEMPTION_CHANGE 25 +#define TX_EL_THREAD_PRIORITY_CHANGE 26 +#define TX_EL_THREAD_RELINQUISH 27 +#define TX_EL_THREAD_RESUME 28 +#define TX_EL_THREAD_SLEEP 29 +#define TX_EL_THREAD_SUSPEND 30 +#define TX_EL_THREAD_TERMINATE 31 +#define TX_EL_THREAD_TIME_SLICE_CHANGE 32 +#define TX_EL_TIME_GET 33 +#define TX_EL_TIME_SET 34 +#define TX_EL_TIMER_ACTIVATE 35 +#define TX_EL_TIMER_CHANGE 36 +#define TX_EL_TIMER_CREATE 37 +#define TX_EL_TIMER_DEACTIVATE 38 +#define TX_EL_TIMER_DELETE 39 +#define TX_EL_BLOCK_POOL_INFO_GET 40 +#define TX_EL_BLOCK_POOL_PRIORITIZE 41 +#define TX_EL_BYTE_POOL_INFO_GET 42 +#define TX_EL_BYTE_POOL_PRIORITIZE 43 +#define TX_EL_EVENT_FLAGS_INFO_GET 44 +#define TX_EL_MUTEX_CREATE 45 +#define TX_EL_MUTEX_DELETE 46 +#define TX_EL_MUTEX_GET 47 +#define TX_EL_MUTEX_INFO_GET 48 +#define TX_EL_MUTEX_PRIORITIZE 49 +#define TX_EL_MUTEX_PUT 50 +#define TX_EL_QUEUE_INFO_GET 51 +#define TX_EL_QUEUE_FRONT_SEND 52 +#define TX_EL_QUEUE_PRIORITIZE 53 +#define TX_EL_SEMAPHORE_INFO_GET 54 +#define TX_EL_SEMAPHORE_PRIORITIZE 55 +#define TX_EL_THREAD_INFO_GET 56 +#define TX_EL_THREAD_WAIT_ABORT 57 +#define TX_EL_TIMER_INFO_GET 58 +#define TX_EL_BLOCK_POOL_PERFORMANCE_INFO_GET 59 +#define TX_EL_BLOCK_POOL_PERFORMANCE_SYSTEM_INFO_GET 60 +#define TX_EL_BYTE_POOL_PERFORMANCE_INFO_GET 61 +#define TX_EL_BYTE_POOL_PERFORMANCE_SYSTEM_INFO_GET 62 +#define TX_EL_EVENT_FLAGS_PERFORMANCE_INFO_GET 63 +#define TX_EL_EVENT_FLAGS_PERFORMANCE_SYSTEM_INFO_GET 64 +#define TX_EL_EVENT_FLAGS_SET_NOTIFY 65 +#define TX_EL_MUTEX_PERFORMANCE_INFO_GET 66 +#define TX_EL_MUTEX_PERFORMANCE_SYSTEM_INFO_GET 67 +#define TX_EL_QUEUE_PERFORMANCE_INFO_GET 68 +#define TX_EL_QUEUE_PERFORMANCE_SYSTEM_INFO_GET 69 +#define TX_EL_QUEUE_SEND_NOTIFY 70 +#define TX_EL_SEMAPHORE_CEILING_PUT 71 +#define TX_EL_SEMAPHORE_PERFORMANCE_INFO_GET 72 +#define TX_EL_SEMAPHORE_PERFORMANCE_SYSTEM_INFO_GET 73 +#define TX_EL_SEMAPHORE_PUT_NOTIFY 74 +#define TX_EL_THREAD_ENTRY_EXIT_NOTIFY 75 +#define TX_EL_THREAD_RESET 76 +#define TX_EL_THREAD_PERFORMANCE_INFO_GET 77 +#define TX_EL_THREAD_PERFORMANCE_SYSTEM_INFO_GET 78 +#define TX_EL_THREAD_STACK_ERROR_NOTIFY 79 +#define TX_EL_TIMER_PERFORMANCE_INFO_GET 80 +#define TX_EL_TIMER_PERFORMANCE_SYSTEM_INFO_GET 81 + + +/* Define ThreadX sub-types. */ + +#define TX_EL_INTERRUPT_SUB_TYPE 1 +#define TX_EL_END_OF_INTERRUPT 3 + + +/* Define event logging filters, which may be used by the application program to + dynamically enable/disable events in run-time. */ + +#define TX_EL_FILTER_STATUS_CHANGE 0x0001 +#define TX_EL_FILTER_INTERRUPTS 0x0002 +#define TX_EL_FILTER_THREAD_CALLS 0x0004 +#define TX_EL_FILTER_TIMER_CALLS 0x0008 +#define TX_EL_FILTER_EVENT_FLAG_CALLS 0x0010 +#define TX_EL_FILTER_SEMAPHORE_CALLS 0x0020 +#define TX_EL_FILTER_QUEUE_CALLS 0x0040 +#define TX_EL_FILTER_BLOCK_CALLS 0x0080 +#define TX_EL_FILTER_BYTE_CALLS 0x0100 +#define TX_EL_FILTER_MUTEX_CALLS 0x0200 +#define TX_EL_FILTER_ALL_EVENTS 0xFFFF +#define TX_EL_ENABLE_ALL_EVENTS 0x0000 + + +/* Define filter macros that are inserted in-line with the other macros below. */ + +#ifdef TX_ENABLE_EVENT_FILTERS +#define TX_EL_NO_STATUS_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_STATUS_CHANGE)) { +#define TX_EL_NO_INTERRUPT_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_INTERRUPTS)) { +#define TX_EL_NO_THREAD_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_THREAD_CALLS)) { +#define TX_EL_NO_TIMER_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_TIMER_CALLS)) { +#define TX_EL_NO_EVENT_FLAG_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_EVENT_FLAG_CALLS)) { +#define TX_EL_NO_SEMAPHORE_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_SEMAPHORE_CALLS)) { +#define TX_EL_NO_QUEUE_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_QUEUE_CALLS)) { +#define TX_EL_NO_BLOCK_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_BLOCK_CALLS)) { +#define TX_EL_NO_BYTE_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_BYTE_CALLS)) { +#define TX_EL_NO_MUTEX_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_MUTEX_CALLS)) { +#define TX_EL_END_FILTER } +#else +#define TX_EL_NO_STATUS_EVENTS +#define TX_EL_NO_INTERRUPT_EVENTS +#define TX_EL_NO_THREAD_EVENTS +#define TX_EL_NO_TIMER_EVENTS +#define TX_EL_NO_EVENT_FLAG_EVENTS +#define TX_EL_NO_SEMAPHORE_EVENTS +#define TX_EL_NO_QUEUE_EVENTS +#define TX_EL_NO_BLOCK_EVENTS +#define TX_EL_NO_BYTE_EVENTS +#define TX_EL_NO_MUTEX_EVENTS +#define TX_EL_END_FILTER +#endif + +/* Define externs and constants for non-event log source modules. This is for + the in-line macros below. */ + +#ifndef TX_EL_SOURCE_CODE +extern UCHAR *_tx_el_tni_start; +extern UCHAR **_tx_el_current_event; +extern UCHAR *_tx_el_event_area_start; +extern UCHAR *_tx_el_event_area_end; +extern UINT _tx_el_maximum_events; +extern ULONG _tx_el_total_events; +extern UINT _tx_el_event_filter; +extern ULONG _tx_el_time_base_upper; +extern ULONG _tx_el_time_base_lower; + + +/* Define macros for event logging functions. */ + +#define TX_EL_THREAD_CREATE_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO4(TX_EL_THREAD_CREATE, thread_ptr, stack_start, stack_size, priority); TX_EL_END_FILTER +#define TX_EL_EVENT_FLAGS_SET_INSERT TX_EL_NO_EVENT_FLAG_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_EVENT_FLAGS_SET, group_ptr, flags_to_set, set_option); TX_EL_END_FILTER +#define TX_EL_THREAD_DELETE_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_DELETE, thread_ptr); TX_EL_END_FILTER +#define TX_EL_THREAD_INFO_GET_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_INFO_GET, thread_ptr); TX_EL_END_FILTER +#define TX_EL_THREAD_TIME_SLICE_CHANGE_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_THREAD_TIME_SLICE_CHANGE, thread_ptr, thread_ptr -> tx_thread_new_time_slice, new_time_slice); TX_EL_END_FILTER +#define TX_EL_THREAD_TERMINATE_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_TERMINATE, thread_ptr); TX_EL_END_FILTER +#define TX_EL_THREAD_SLEEP_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_SLEEP, timer_ticks); TX_EL_END_FILTER +#define TX_EL_THREAD_SUSPEND_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_SUSPEND, thread_ptr); TX_EL_END_FILTER +#define TX_EL_THREAD_RELINQUISH_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_THREAD_RELINQUISH); TX_EL_END_FILTER +#define TX_EL_THREAD_RESUME_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_RESUME, thread_ptr); TX_EL_END_FILTER +#define TX_EL_THREAD_PRIORITY_CHANGE_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_THREAD_PRIORITY_CHANGE, thread_ptr, thread_ptr -> tx_thread_priority, new_priority); TX_EL_END_FILTER +#define TX_EL_THREAD_PREEMPTION_CHANGE_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_THREAD_PREEMPTION_CHANGE, thread_ptr, thread_ptr -> tx_thread_preempt_threshold, new_threshold); TX_EL_END_FILTER +#define TX_EL_THREAD_WAIT_ABORT_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_WAIT_ABORT, thread_ptr); TX_EL_END_FILTER +#define TX_EL_THREAD_ENTRY_EXIT_NOTIFY_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_THREAD_ENTRY_EXIT_NOTIFY, thread_ptr, thread_entry_exit_notify); TX_EL_END_FILTER +#define TX_EL_THREAD_RESET_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_RESET, thread_ptr); TX_EL_END_FILTER +#define TX_EL_THREAD_PERFORMANCE_INFO_GET_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_PERFORMANCE_INFO_GET, thread_ptr); TX_EL_END_FILTER +#define TX_EL_THREAD_PERFORMANCE_SYSTEM_INFO_GET_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_THREAD_PERFORMANCE_SYSTEM_INFO_GET); TX_EL_END_FILTER +#define TX_EL_THREAD_STACK_ERROR_NOTIFY_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_THREAD_STACK_ERROR_NOTIFY, stack_error_handler); TX_EL_END_FILTER +#define TX_EL_TIME_SET_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_TIME_SET, new_time); TX_EL_END_FILTER +#define TX_EL_TIME_GET_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_TIME_GET, _tx_timer_system_clock); TX_EL_END_FILTER +#define TX_EL_TIMER_DELETE_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_TIMER_DELETE, timer_ptr); TX_EL_END_FILTER +#define TX_EL_TIMER_CREATE_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO4(TX_EL_TIMER_CREATE, timer_ptr, initial_ticks, reschedule_ticks, auto_activate); TX_EL_END_FILTER +#define TX_EL_TIMER_CHANGE_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_TIMER_CHANGE, timer_ptr, initial_ticks, reschedule_ticks); TX_EL_END_FILTER +#define TX_EL_THREAD_IDENTIFY_INSERT TX_EL_NO_THREAD_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_THREAD_IDENTIFY); TX_EL_END_FILTER +#define TX_EL_TIMER_DEACTIVATE_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_TIMER_DEACTIVATE, timer_ptr); TX_EL_END_FILTER +#define TX_EL_TIMER_ACTIVATE_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_TIMER_ACTIVATE, timer_ptr); TX_EL_END_FILTER +#define TX_EL_TIMER_INFO_GET_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_TIMER_INFO_GET, timer_ptr); TX_EL_END_FILTER +#define TX_EL_TIMER_PERFORMANCE_INFO_GET_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_TIMER_PERFORMANCE_INFO_GET, timer_ptr); TX_EL_END_FILTER +#define TX_EL_TIMER_PERFORMANCE_SYSTEM_INFO_GET_INSERT TX_EL_NO_TIMER_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_TIMER_PERFORMANCE_SYSTEM_INFO_GET); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_PUT_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_SEMAPHORE_PUT, semaphore_ptr, semaphore_ptr -> tx_semaphore_count); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_GET_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_SEMAPHORE_GET, semaphore_ptr, semaphore_ptr -> tx_semaphore_count); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_DELETE_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_SEMAPHORE_DELETE, semaphore_ptr); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_CREATE_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_SEMAPHORE_CREATE, semaphore_ptr, initial_count); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_INFO_GET_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_SEMAPHORE_INFO_GET, semaphore_ptr); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_PRIORITIZE_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_SEMAPHORE_PRIORITIZE, semaphore_ptr); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_CEILING_PUT_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_SEMAPHORE_CEILING_PUT, semaphore_ptr, semaphore_ptr -> tx_semaphore_count, ceiling); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_PERFORMANCE_INFO_GET_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_SEMAPHORE_PERFORMANCE_INFO_GET, semaphore_ptr); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_PERFORMANCE_SYSTEM_INFO_GET_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_SEMAPHORE_PERFORMANCE_SYSTEM_INFO_GET); TX_EL_END_FILTER +#define TX_EL_SEMAPHORE_PUT_NOTIFY_INSERT TX_EL_NO_SEMAPHORE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_SEMAPHORE_PUT_NOTIFY, semaphore_ptr, semaphore_put_notify); TX_EL_END_FILTER +#define TX_EL_QUEUE_FRONT_SEND_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_QUEUE_FRONT_SEND, queue_ptr, source_ptr); TX_EL_END_FILTER +#define TX_EL_QUEUE_SEND_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_QUEUE_SEND, queue_ptr, source_ptr); TX_EL_END_FILTER +#define TX_EL_QUEUE_RECEIVE_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_QUEUE_RECEIVE, queue_ptr, destination_ptr); TX_EL_END_FILTER +#define TX_EL_QUEUE_FLUSH_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_QUEUE_FLUSH, queue_ptr); TX_EL_END_FILTER +#define TX_EL_QUEUE_DELETE_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_QUEUE_DELETE, queue_ptr); TX_EL_END_FILTER +#define TX_EL_QUEUE_CREATE_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO4(TX_EL_QUEUE_CREATE, queue_ptr, queue_start, queue_size, message_size); TX_EL_END_FILTER +#define TX_EL_QUEUE_INFO_GET_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_QUEUE_INFO_GET, queue_ptr); TX_EL_END_FILTER +#define TX_EL_QUEUE_PRIORITIZE_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_QUEUE_PRIORITIZE, queue_ptr); TX_EL_END_FILTER +#define TX_EL_QUEUE_PERFORMANCE_INFO_GET_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_QUEUE_PERFORMANCE_INFO_GET, queue_ptr); TX_EL_END_FILTER +#define TX_EL_QUEUE_PERFORMANCE_SYSTEM_INFO_GET_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_QUEUE_PERFORMANCE_SYSTEM_INFO_GET); TX_EL_END_FILTER +#define TX_EL_QUEUE_SEND_NOTIFY_INSERT TX_EL_NO_QUEUE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_QUEUE_SEND_NOTIFY, queue_ptr, queue_send_notify); TX_EL_END_FILTER +#define TX_EL_EVENT_FLAGS_GET_INSERT TX_EL_NO_EVENT_FLAG_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_EVENT_FLAGS_GET, group_ptr, requested_flags, get_option); TX_EL_END_FILTER +#define TX_EL_EVENT_FLAGS_DELETE_INSERT TX_EL_NO_EVENT_FLAG_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_EVENT_FLAGS_DELETE, group_ptr); TX_EL_END_FILTER +#define TX_EL_EVENT_FLAGS_CREATE_INSERT TX_EL_NO_EVENT_FLAG_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_EVENT_FLAGS_CREATE, group_ptr); TX_EL_END_FILTER +#define TX_EL_EVENT_FLAGS_INFO_GET_INSERT TX_EL_NO_EVENT_FLAG_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_EVENT_FLAGS_INFO_GET, group_ptr); TX_EL_END_FILTER +#define TX_EL_EVENT_FLAGS_PERFORMANCE_INFO_GET_INSERT TX_EL_NO_EVENT_FLAG_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_EVENT_FLAGS_PERFORMANCE_INFO_GET, group_ptr); TX_EL_END_FILTER +#define TX_EL_EVENT_FLAGS_PERFORMANCE_SYSTEM_INFO_GET_INSERT TX_EL_NO_EVENT_FLAG_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_EVENT_FLAGS_PERFORMANCE_SYSTEM_INFO_GET); TX_EL_END_FILTER +#define TX_EL_EVENT_FLAGS_SET_NOTIFY_INSERT TX_EL_NO_EVENT_FLAG_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_EVENT_FLAGS_SET_NOTIFY, group_ptr, events_set_notify); TX_EL_END_FILTER +#define TX_EL_BYTE_RELEASE_INSERT TX_EL_NO_BYTE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_BYTE_RELEASE, pool_ptr, memory_ptr); TX_EL_END_FILTER +#define TX_EL_BYTE_POOL_DELETE_INSERT TX_EL_NO_BYTE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_BYTE_POOL_DELETE, pool_ptr); TX_EL_END_FILTER +#define TX_EL_BYTE_POOL_CREATE_INSERT TX_EL_NO_BYTE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_BYTE_POOL_CREATE, pool_ptr, pool_start, pool_size); TX_EL_END_FILTER +#define TX_EL_BYTE_POOL_INFO_GET_INSERT TX_EL_NO_BYTE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_BYTE_POOL_INFO_GET, pool_ptr); TX_EL_END_FILTER +#define TX_EL_BYTE_POOL_PRIORITIZE_INSERT TX_EL_NO_BYTE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_BYTE_POOL_PRIORITIZE, pool_ptr); TX_EL_END_FILTER +#define TX_EL_BYTE_ALLOCATE_INSERT TX_EL_NO_BYTE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_BYTE_ALLOCATE, pool_ptr, memory_ptr, memory_size); TX_EL_END_FILTER +#define TX_EL_BYTE_POOL_PERFORMANCE_INFO_GET_INSERT TX_EL_NO_BYTE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_BYTE_POOL_PERFORMANCE_INFO_GET, pool_ptr); TX_EL_END_FILTER +#define TX_EL_BYTE_POOL_PERFORMANCE_SYSTEM_INFO_GET_INSERT TX_EL_NO_BYTE_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_BYTE_POOL_PERFORMANCE_SYSTEM_INFO_GET); TX_EL_END_FILTER +#define TX_EL_BLOCK_RELEASE_INSERT TX_EL_NO_BLOCK_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_BLOCK_RELEASE, pool_ptr, block_ptr); TX_EL_END_FILTER +#define TX_EL_BLOCK_POOL_DELETE_INSERT TX_EL_NO_BLOCK_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_BLOCK_POOL_DELETE, pool_ptr); TX_EL_END_FILTER +#define TX_EL_BLOCK_POOL_CREATE_INSERT TX_EL_NO_BLOCK_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO4(TX_EL_BLOCK_POOL_CREATE, pool_ptr, pool_start, pool_size, block_size); TX_EL_END_FILTER +#define TX_EL_BLOCK_POOL_INFO_GET_INSERT TX_EL_NO_BLOCK_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_BLOCK_POOL_INFO_GET, pool_ptr); TX_EL_END_FILTER +#define TX_EL_BLOCK_POOL_PRIORITIZE_INSERT TX_EL_NO_BLOCK_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_BLOCK_POOL_PRIORITIZE, pool_ptr); TX_EL_END_FILTER +#define TX_EL_BLOCK_ALLOCATE_INSERT TX_EL_NO_BLOCK_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_BLOCK_ALLOCATE, pool_ptr, block_ptr); TX_EL_END_FILTER +#define TX_EL_BLOCK_POOL_PERFORMANCE_INFO_GET_INSERT TX_EL_NO_BLOCK_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_BLOCK_POOL_PERFORMANCE_INFO_GET, pool_ptr); TX_EL_END_FILTER +#define TX_EL_BLOCK_POOL_PERFORMANCE_SYSTEM_INFO_GET_INSERT TX_EL_NO_BLOCK_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_BLOCK_POOL_PERFORMANCE_SYSTEM_INFO_GET); TX_EL_END_FILTER +#define TX_EL_MUTEX_CREATE_INSERT TX_EL_NO_MUTEX_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_MUTEX_CREATE, mutex_ptr, inherit); TX_EL_END_FILTER +#define TX_EL_MUTEX_DELETE_INSERT TX_EL_NO_MUTEX_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_MUTEX_DELETE, mutex_ptr); TX_EL_END_FILTER +#define TX_EL_MUTEX_GET_INSERT TX_EL_NO_MUTEX_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_MUTEX_GET, mutex_ptr, mutex_ptr -> tx_mutex_owner, mutex_ptr -> tx_mutex_ownership_count); TX_EL_END_FILTER +#define TX_EL_MUTEX_INFO_GET_INSERT TX_EL_NO_MUTEX_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_MUTEX_INFO_GET, mutex_ptr); TX_EL_END_FILTER +#define TX_EL_MUTEX_PRIORITIZE_INSERT TX_EL_NO_MUTEX_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_MUTEX_PRIORITIZE, mutex_ptr); TX_EL_END_FILTER +#define TX_EL_MUTEX_PUT_INSERT TX_EL_NO_MUTEX_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(TX_EL_MUTEX_PUT, mutex_ptr, mutex_ptr -> tx_mutex_owner, mutex_ptr -> tx_mutex_ownership_count); TX_EL_END_FILTER +#define TX_EL_MUTEX_PERFORMANCE_INFO_GET_INSERT TX_EL_NO_MUTEX_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(TX_EL_MUTEX_PERFORMANCE_INFO_GET, mutex_ptr); TX_EL_END_FILTER +#define TX_EL_MUTEX_PERFORMANCE_SYSTEM_INFO_GET_INSERT TX_EL_NO_MUTEX_EVENTS TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(TX_EL_MUTEX_PERFORMANCE_SYSTEM_INFO_GET); TX_EL_END_FILTER + + +#endif + + +/* Define Event Log function prototypes. */ + +VOID _tx_el_initialize(VOID); +UINT _tx_el_thread_register(TX_THREAD *thread_ptr); +UINT _tx_el_thread_unregister(TX_THREAD *thread_ptr); +VOID _tx_el_user_event_insert(UINT sub_type, ULONG info_1, ULONG info_2, + ULONG info_3, ULONG info_4); +VOID _tx_el_thread_running(TX_THREAD *thread_ptr); +VOID _tx_el_thread_preempted(TX_THREAD *thread_ptr); +VOID _tx_el_interrupt(UINT interrupt_number); +VOID _tx_el_interrupt_end(UINT interrupt_number); +VOID _tx_el_interrupt_control_call(void); +VOID _tx_el_event_log_on(void); +VOID _tx_el_event_log_off(void); +VOID _tx_el_event_filter_set(UINT filter); + + +/* Define macros that are used inside the ThreadX source code. + If event logging is disabled, these macros will be defined + as white space. */ + +#ifdef TX_ENABLE_EVENT_LOGGING +#ifndef TX_NO_EVENT_INFO +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO4(a, b, c, d, e) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_smp_current_thread_get();\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_1_OFFSET)) =\ + (ULONG) b;\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_2_OFFSET)) =\ + (ULONG) c;\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_3_OFFSET)) =\ + (ULONG) d;\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_4_OFFSET)) =\ + (ULONG) e;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(a, b, c, d) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_smp_current_thread_get();\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_1_OFFSET)) =\ + (ULONG) b;\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_2_OFFSET)) =\ + (ULONG) c;\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_3_OFFSET)) =\ + (ULONG) d;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(a, b, c) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_smp_current_thread_get();\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_1_OFFSET)) =\ + (ULONG) b;\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_2_OFFSET)) =\ + (ULONG) c;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(a, b) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_smp_current_thread_get();\ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_1_OFFSET)) =\ + (ULONG) b;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(a) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_smp_current_thread_get();\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_THREAD_STATUS_CHANGE_INSERT(a, b) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + TX_EL_NO_STATUS_EVENTS \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREAD_STATUS_CHANGE; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) b; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) a;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + TX_EL_END_FILTER \ + } +#define TX_EL_THREAD_REGISTER(a) \ + _tx_el_thread_register(a); +#define TX_EL_THREAD_UNREGISTER(a) \ + _tx_el_thread_unregister(a); +#define TX_EL_INITIALIZE _tx_el_initialize(); +#else +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO4(a, b, c, d, e) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_smp_current_thread_get();\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(a, b, c, d) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_smp_current_thread_get();\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(a, b, c) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_smp_current_thread_get();\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(a, b) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_smp_current_thread_get();\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(a) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREADX_CALL; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) a; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) _tx_thread_smp_current_thread_get();\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + } +#define TX_EL_THREAD_STATUS_CHANGE_INSERT(a, b) \ + { \ + UCHAR *entry_ptr; \ + ULONG upper_tbu; \ + TX_EL_NO_STATUS_EVENTS \ + entry_ptr = *_tx_el_current_event; \ + *((unsigned short *) entry_ptr) = TX_EL_THREAD_STATUS_CHANGE; \ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = (unsigned short) b; \ + do { \ + upper_tbu = read_tbu(); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = upper_tbu; \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) =\ + (ULONG) read_tbl();\ + } while (upper_tbu != read_tbu()); \ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) =\ + (ULONG) a;\ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE;\ + if (entry_ptr >= _tx_el_event_area_end) \ + {\ + entry_ptr = _tx_el_event_area_start;\ + }\ + *_tx_el_current_event = entry_ptr;\ + TX_EL_END_FILTER \ + } +#define TX_EL_THREAD_REGISTER(a) \ + _tx_el_thread_register(a); +#define TX_EL_THREAD_UNREGISTER(a) \ + _tx_el_thread_unregister(a); +#define TX_EL_INITIALIZE _tx_el_initialize(); +#endif +#else +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO4(a, b, c, d, e) +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(a, b, c, d) +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(a, b, c) +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO1(a, b) +#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO0(a) +#define TX_EL_THREAD_STATUS_CHANGE_INSERT(a, b) +#define TX_EL_THREAD_REGISTER(a) +#define TX_EL_THREAD_UNREGISTER(a) +#define TX_EL_INITIALIZE +#endif + +#endif + diff --git a/ports_smp/cortex_a5x_smp/green/inc/tx_ghs.h b/ports_smp/cortex_a5x_smp/green/inc/tx_ghs.h new file mode 100644 index 00000000..ca976916 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/inc/tx_ghs.h @@ -0,0 +1,77 @@ +/* + * ThreadX C/C++ Library Support + * + * Copyright 1983-2019 Green Hills Software LLC. + * + * This program is the property of Green Hills Software LLC., + * its contents are proprietary information and no part of it + * is to be disclosed to anyone except employees of Green Hills + * Software LLC., or as agreed in writing signed by the President + * of Green Hills Software LLC. + */ + +#ifndef _TX_GHS_H_ +#define _TX_GHS_H_ + +#include +#include +#include +#include + +#if defined(__ghs) && (__GHS_VERSION_NUMBER >= 500) +extern void *__ghs_GetThreadLocalStorageItem(int specifier); + +/* Thread-local storage routines for Green Hills releases 5.x and beyond. + The following specifiers are used when calling + __ghs_GetThreadLocalStorageItem. + + If __ghs_GetThreadLocalStorageItem is customized to + return a per-thread errno value, define the preprocessor symbol + USE_THREAD_LOCAL_ERRNO in ind_errn.c. + */ + +enum __ghs_ThreadLocalStorage_specifier { + __ghs_TLS_asctime_buff, + __ghs_TLS_tmpnam_space, + __ghs_TLS_strtok_saved_pos, + __ghs_TLS_Errno, + __ghs_TLS_gmtime_temp, + __ghs_TLS___eh_globals, + __ghs_TLS_SignalHandlers +}; +#else +/* Thread-local storage routines for Green Hills releases 4.x and 3.x . */ +typedef void (*SignalHandler)(int); + +typedef struct +{ + int Errno; /* errno. */ + SignalHandler SignalHandlers[_SIGMAX]; /* signal() buffer. */ + char tmpnam_space[L_tmpnam]; /* tmpnam(NULL) buffer. */ + char asctime_buff[30]; /* . */ + char *strtok_saved_pos; /* strtok() position. */ + struct tm gmtime_temp; /* gmtime() and localtime() buffer. */ + void *__eh_globals; /* Pointer for C++ exception handling. */ +} ThreadLocalStorage; + +ThreadLocalStorage *GetThreadLocalStorage(void); +#endif + + +void __ghsLock(void); +void __ghsUnlock(void); + +int __ghs_SaveSignalContext(jmp_buf); +void __ghs_RestoreSignalContext(jmp_buf); + +/* prototypes for FILE lock routines. */ +void __ghs_flock_file(void *); +void __ghs_funlock_file(void *); +int __ghs_ftrylock_file(void *); +void __ghs_flock_create(void **); +void __ghs_flock_destroy(void *); + +/* prototype for GHS/ThreadX error shell checking. */ +void __ghs_rnerr(char *errMsg, int stackLevels, int stackTraceDisplay, void *hexVal); + +#endif /* _TX_GHS_H_ */ diff --git a/ports_smp/cortex_a5x_smp/green/inc/tx_port.h b/ports_smp/cortex_a5x_smp/green/inc/tx_port.h new file mode 100644 index 00000000..f13360ac --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/inc/tx_port.h @@ -0,0 +1,452 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A5x-SMP/GHS */ +/* 6.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/************* Define ThreadX SMP constants. *************/ + +/* Define the ThreadX SMP maximum number of cores. */ + +#ifndef TX_THREAD_SMP_MAX_CORES +#define TX_THREAD_SMP_MAX_CORES 4 +#endif + + +/* Define the ThreadX SMP core mask. */ + +#ifndef TX_THREAD_SMP_CORE_MASK +#define TX_THREAD_SMP_CORE_MASK 0xF /* Where bit 0 represents Core 0, bit 1 represents Core 1, etc. */ +#endif + + +/* Define INLINE_DECLARE macro. */ + +#define INLINE_DECLARE inline + + +/* Define the TX_MEMSET macro to remove library reference. */ + +#define TX_MEMSET(a,b,c) _tx_memset(a,b,c) +static inline void _tx_memset(void * ptr, int value, unsigned num) +{ + char *p = ptr; + char *pmax = p + num; + while (p < pmax) *p++ = (char) value; +} + + +/* Define ThreadX SMP initialization macro. */ + +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION + + +/* Define ThreadX SMP pre-scheduler initialization. */ + +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION + + +/* Enable the inter-core interrupt logic. */ + +#define TX_THREAD_SMP_INTER_CORE_INTERRUPT + + +/* Determine if there is customer-specific wakeup logic needed. */ + +#ifdef TX_THREAD_SMP_WAKEUP_LOGIC + +/* Include customer-specific wakeup code. */ + +#include "tx_thread_smp_core_wakeup.h" +#else + +#ifdef TX_THREAD_SMP_DEFAULT_WAKEUP_LOGIC + +/* Default wakeup code. */ +#define TX_THREAD_SMP_WAKEUP_LOGIC +#define TX_THREAD_SMP_WAKEUP(i) _tx_thread_smp_core_preempt(i) +#endif +#endif + + +/* Ensure that the in-line resume/suspend define is not allowed. */ + +#ifdef TX_INLINE_THREAD_RESUME_SUSPEND +#undef TX_INLINE_THREAD_RESUME_SUSPEND +#endif + + +/************* End ThreadX SMP constants. *************/ + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef int LONG; +typedef unsigned int ULONG; +typedef unsigned long long ULONG64; +typedef short SHORT; +typedef unsigned short USHORT; +typedef unsigned long long ULONG_PTR; + + +/* Override the alignment type to use 64-bit alignment and storage for pointers. */ + +#define ALIGN_TYPE_DEFINED +typedef unsigned long long ALIGN_TYPE; + + +/* Override the free block marker for byte pools to be a 64-bit constant. */ + +#define TX_BYTE_BLOCK_FREE ((ALIGN_TYPE) 0xFFFFEEEEFFFFEEEE) + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 4096 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#define TX_INT_ENABLE 0x00 /* Enable IRQ & FIQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE _tx_thread_smp_time_get() +#endif +#else +#ifndef TX_TRACE_TIME_SOURCE +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_fp_enable; +#define TX_THREAD_EXTENSION_3 VOID * tx_thread_eh_globals; \ + int Errno; \ + char * strtok_saved_pos; \ + VOID *tx_thread_extension_ptr; + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#include + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + b = (UINT) __CLZ32((ULONG) m); \ + b = 31 - b; + + +#endif + + +/* Define the internal timer extension to also hold the thread pointer such that _tx_thread_timeout + can figure out what thread timeout to process. */ + +#define TX_TIMER_INTERNAL_EXTENSION VOID *tx_timer_internal_extension_ptr; + + +/* Define the thread timeout setup logic in _tx_thread_create. */ + +#define TX_THREAD_CREATE_TIMEOUT_SETUP(t) (t) -> tx_thread_timer.tx_timer_internal_timeout_function = &(_tx_thread_timeout); \ + (t) -> tx_thread_timer.tx_timer_internal_timeout_param = 0; \ + (t) -> tx_thread_timer.tx_timer_internal_extension_ptr = (VOID *) (t); + + +/* Define the thread timeout pointer setup in _tx_thread_timeout. */ + +#define TX_THREAD_TIMEOUT_POINTER_SETUP(t) (t) = (TX_THREAD *) _tx_timer_expired_timer_ptr -> tx_timer_internal_extension_ptr; + + +/************* Define ThreadX SMP data types and function prototypes. *************/ + +struct TX_THREAD_STRUCT; + + +/* Define the ThreadX SMP protection structure. */ + +typedef struct TX_THREAD_SMP_PROTECT_STRUCT +{ + ULONG tx_thread_smp_protect_in_force; + ULONG tx_thread_smp_protect_core; + ULONG tx_thread_smp_protect_count; + ULONG tx_thread_smp_protect_pad_0; + ULONG tx_thread_smp_protect_pad_1; + ULONG tx_thread_smp_protect_pad_2; + ULONG tx_thread_smp_protect_pad_3; +} TX_THREAD_SMP_PROTECT; + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_smp_protect(); +#define TX_RESTORE _tx_thread_smp_unprotect(interrupt_save); + +/************* End ThreadX SMP data type and function prototype definitions. *************/ + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define VFP extension for the Cortex-A5x. Each is assumed to be called in the context of the executing + thread. */ + +#ifndef TX_SOURCE_CODE +#define tx_thread_fp_enable _tx_thread_fp_enable +#define tx_thread_fp_disable _tx_thread_fp_disable +#endif + +VOID tx_thread_fp_enable(VOID); +VOID tx_thread_fp_disable(VOID); + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5x-SMP/GHS Version 6.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + + + + + diff --git a/ports_smp/cortex_a5x_smp/green/readme_threadx.txt b/ports_smp/cortex_a5x_smp/green/readme_threadx.txt new file mode 100644 index 00000000..be70d786 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/readme_threadx.txt @@ -0,0 +1,264 @@ + Microsoft's Azure RTOS ThreadX SMP for Cortex-A5x + + Using the Green Hills Software Tools + +1. Open the ThreadX SMP Project Workspace + +In order to build the ThreadX SMP library and the ThreadX SMP demonstration +first load the ThreadX SMP project workspace azure_rtos_workspace.gpj, which is +located inside your ThreadX SMP directory. + + +2. Building the ThreadX SMP run-time Library + +Building the ThreadX SMP library is easy; simply select the MULTI project file +tx.gpj and then select the build button. You should now observe the +compilation and assembly of the ThreadX SMP library. This project build produces +the ThreadX SMP library file tx.a. + + +3. Demonstration System + +The ThreadX SMP demonstration is designed to execute under the MULTI environment +on the Xilinx UltraScale+ ZCU102 evaluation board. + +Building the demonstration is easy; simply select the MULTI project file +sample_threadx.gpj. At this point, select the "Project Build" button and observe +the compilation, assembly, and linkage of the ThreadX SMP demonstration application. + +You are now ready to download the ELF image using the Xilinx tools on the ZCU102 +evaluation board. + + +4. System Initialization + +The system entry point using the Green Hills tools is at the label _boot. +This is defined within the tx_boot.a64 file. In addition, this is where all static +and global preset C variable initialization processing is called from. + +After the Green Hills startup function returns, ThreadX SMP initialization is +called. The main initialization function is _tx_initialize_low_level and +is located in the file tx_initialize_low_level.a64. This function is responsible +for setting up various system data structures, interrupt vectors, and the +periodic timer interrupt source of ThreadX SMP. + +In addition, _tx_initialize_low_level determines where the first available +RAM memory address is located. This address is supplied to tx_application_define. + +By default, the first available RAM memory address is assumed to start at the +beginning of the ThreadX SMP section .free_mem. If changes are made to the +sample_threadx.ld file, the .free_mem section should remain the last allocated +section in the main RAM area. The starting address of this section is passed +to tx_application_define. + + +5. Register Usage and Stack Frames + +The 64-bit Green Hills compiler assumes that registers x0-x18 are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX SMP takes advantage of this in +situations where a context switch happens as a result of making a ThreadX SMP +service call (which is itself a C function). In such cases, the saved +context of a thread is only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + +FP not enabled and TX_THREAD.tx_thread_fp_enable == 0: + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x000 SPSR DAIF + 0x008 ELR 0 + 0x010 x28 x27 + 0x018 reserved x28 + 0x020 x26 x25 + 0x028 x27 x26 + 0x030 x24 x23 + 0x038 x25 x24 + 0x040 x22 x21 + 0x048 x23 x22 + 0x050 x20 x19 + 0x058 x21 x20 + 0x060 x18 x29 + 0x068 x19 x30 + 0x070 x16 + 0x078 x17 + 0x080 x14 + 0x088 x15 + 0x090 x12 + 0x098 x13 + 0x0A0 x10 + 0x0A8 x11 + 0x0B0 x8 + 0x0B8 x9 + 0x0C0 x6 + 0x0C8 x7 + 0x0D0 x4 + 0x0D8 x5 + 0x0E0 x2 + 0x0E8 x3 + 0x0F0 x0 + 0x0F8 x1 + 0x100 x29 + 0x108 x30 + + +FP enabled and TX_THREAD.tx_thread_fp_enable == 1: + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x000 SPSR DAIF + 0x008 ELR 0 + 0x010 FPSR FPSR + 0x018 FPCR FPCR + 0x020 q30 q14 + 0x030 q31 q15 + 0x040 q28 q12 + 0x050 q29 q13 + 0x060 q26 q10 + 0x070 q27 q11 + 0x080 q24 q8 + 0x090 q25 q9 + 0x0A0 q22 x27 + 0x0A8 x28 + 0x0B0 q23 x25 + 0x0B8 x26 + 0x0C0 q20 x23 + 0x0C8 x24 + 0x0D0 q21 x21 + 0x0D8 x22 + 0x0E0 q18 x19 + 0x0E8 x20 + 0x0F0 q19 x29 + 0x0F8 x30 + 0x100 q16 + 0x110 q17 + 0x120 q14 + 0x130 q15 + 0x140 q12 + 0x150 q13 + 0x160 q10 + 0x170 q11 + 0x180 q8 + 0x190 q9 + 0x1A0 q6 + 0x1B0 q7 + 0x1C0 q4 + 0x1D0 q5 + 0x1E0 q2 + 0x1F0 q3 + 0x200 q0 + 0x210 q1 + 0x220 x28 + 0x228 reserved + 0x230 x26 + 0x238 x27 + 0x240 x24 + 0x248 x25 + 0x250 x22 + 0x258 x23 + 0x260 x20 + 0x268 x21 + 0x270 x18 + 0x278 x19 + 0x280 x16 + 0x288 x17 + 0x290 x14 + 0x298 x15 + 0x2A0 x12 + 0x2A8 x13 + 0x2B0 x10 + 0x2B8 x11 + 0x2C0 x8 + 0x2C8 x9 + 0x2D0 x6 + 0x2D8 x7 + 0x2E0 x4 + 0x2E8 x5 + 0x2F0 x2 + 0x2F8 x3 + 0x300 x0 + 0x308 x1 + 0x310 x29 + 0x318 x30 + + +6. Improving Performance + +The distribution version of ThreadX SMP is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX SMP itself. Of course, this costs some +performance. To make ThreadX SMP run faster, you can change the tx.gpj project +to disable debug information and enable the desired optimizations. + +In addition, you can eliminate the ThreadX SMP basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined before tx_api.h is included. + + +7. Interrupt Handling + +ThreadX SMP provides complete and high-performance interrupt handling for Cortex-A5x +targets. Interrupts handlers for the 64-bit mode of the Cortex-A5x have the following +format: + + .global __irq_handler +__irq_handler: + STP x29, x30, [sp, #-16]! + BL _tx_thread_context_save + + /* Your ISR call goes here! */ + BL application_isr_handler + + B _tx_thread_context_restore + +By default, ThreadX SMP assumes EL3 level of execution. Running and taking exceptions in EL1 +and EL2 can be done by simply building the ThreadX library with either EL1 or EL2 defined. + + +8. ThreadX SMP Timer Interrupt + +ThreadX SMP requires a periodic interrupt source to manage all time-slicing, thread sleeps, +timeouts, and application timers. Without such a timer interrupt source, these services are +not functional. However, all other ThreadX SMP services are operational without a periodic +timer source. + +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt in the IRQ +processing. An example of this can be found in the file tx_initialize_low_level.a64. + + +9. FP Support + +By default, FP support is disabled for each thread. If saving the context of the FP registers +is needed, the following API call must be made from the context of the application thread - before +the FP usage: + +void tx_thread_fp_enable(void); + +After this API is called in the application, FP registers will be saved/restored for this thread if it +is preempted via an interrupt. All other suspension of the this thread will not require the FP registers +to be saved/restored. + +To disable FP register context saving, simply call the following API: + +void tx_thread_fp_disable(void); + + +10. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX SMP: + +09/30/2020 Initial ThreadX SMP version 6.1 of Cortex-A5x/Green Hills port. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_el.c b/ports_smp/cortex_a5x_smp/green/src/tx_el.c new file mode 100644 index 00000000..69f11e54 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/src/tx_el.c @@ -0,0 +1,1166 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** ThreadX/GHS Event Log (EL) */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_EL_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_el.h" +#include "string.h" + + +/* Define global variables used to manage the event pool. */ + +UCHAR *_tx_el_tni_start; +UCHAR **_tx_el_current_event; +UCHAR *_tx_el_event_area_start; +UCHAR *_tx_el_event_area_end; +UINT _tx_el_maximum_events; +ULONG _tx_el_total_events; +UINT _tx_el_event_filter; +ULONG _tx_el_time_base_upper; +ULONG _tx_el_time_base_lower; + +extern char __ghsbegin_eventlog[]; +extern char __ghsend_eventlog[]; + +extern TX_THREAD *_tx_thread_current_ptr[]; +UINT _tx_thread_interrupt_control(UINT new_posture); + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_initialize PORTABLE SMP */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates the Event Log (in the format dictated by the */ +/* GHS Event Analyzer) and sets up various information for subsequent */ +/* operation. The start and end of the Event Log is determined by the */ +/* .eventlog section in the linker control file. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_el_initialize(VOID) +{ + +UCHAR *work_ptr; +UCHAR *read_ptr; +ULONG event_log_size; +UCHAR *end_ptr; +UINT i; + + + /* Clear total event counter. */ + _tx_el_total_events = 0; + + /* Clear event filter. */ + _tx_el_event_filter = 0; + + /* First, pickup the starting and ending address of the Event Log memory. */ + work_ptr = (unsigned char *) __ghsbegin_eventlog; + end_ptr = (unsigned char *) __ghsend_eventlog; + + /* Calculate the event log size. */ + event_log_size = end_ptr - work_ptr; + + /* Subtract off the number of bytes in the header and the TNI area. */ + event_log_size = event_log_size - (TX_EL_HEADER_SIZE + + (TX_EL_TNI_ENTRY_SIZE * TX_EL_TNIS)); + + /* Make sure the event log is evenly divisible by the event size. */ + event_log_size = (event_log_size/TX_EL_EVENT_SIZE) * TX_EL_EVENT_SIZE; + + /* Build the Event Log header. */ + + /* Setup the Event Log Version ID. */ + *((unsigned short *) work_ptr) = (unsigned short) TX_EL_VERSION_ID; + work_ptr = work_ptr + sizeof(unsigned short); + + /* Setup the TNIS (number of thread names) field. */ + *((unsigned short *) work_ptr) = (unsigned short) TX_EL_TNIS; + work_ptr = work_ptr + sizeof(unsigned short); + + /* Setup the EVPS (event pool size) field. */ + *((ULONG *) work_ptr) = event_log_size; + work_ptr = work_ptr + sizeof(ULONG); + + /* Remember the maximum number of events. */ + _tx_el_maximum_events = event_log_size/TX_EL_EVENT_SIZE; + + /* Setup max_events field. */ + *((ULONG *) work_ptr) = _tx_el_maximum_events; + work_ptr = work_ptr + sizeof(ULONG); + + /* Setup the evploc (location of event pool). */ + *((ULONG *) work_ptr) = (ULONG) (((ULONG) __ghsbegin_eventlog) + TX_EL_HEADER_SIZE + + (TX_EL_TNIS * TX_EL_TNI_ENTRY_SIZE)); + work_ptr = work_ptr + sizeof(ULONG); + + /* Save the current event pointer. */ + _tx_el_current_event = (UCHAR **) work_ptr; + + /* Setup event_ptr (pointer to oldest event) field to the start + of the event pool. */ + *_tx_el_current_event = (UCHAR *) (((ULONG) __ghsbegin_eventlog) + TX_EL_HEADER_SIZE + + (TX_EL_TNIS * TX_EL_TNI_ENTRY_SIZE)); + work_ptr = work_ptr + sizeof(ULONG); + + /* Setup tbfreq (the number of ticks in a second) field. */ + *((ULONG *) work_ptr) = TX_EL_TICKS_PER_SECOND; + work_ptr = work_ptr + sizeof(ULONG); + + /* At this point we are pointing at the Thread Name Information (TNI) array. */ + + /* Remember the start of this for future updates. */ + _tx_el_tni_start = work_ptr; + + /* Clear the entire TNI array, this is the initial setting. */ + end_ptr = work_ptr + (TX_EL_TNIS * TX_EL_TNI_ENTRY_SIZE); + memset((void *)work_ptr, 0, (TX_EL_TNIS * TX_EL_TNI_ENTRY_SIZE)); + work_ptr = end_ptr; + + /* At this point, we are pointing at the actual Event Entry area. */ + + /* Remember the start of the actual event log area. */ + _tx_el_event_area_start = work_ptr; + + /* Clear the entire Event area. */ + end_ptr = work_ptr + event_log_size; + memset((void *)work_ptr, 0, event_log_size); + work_ptr = end_ptr; + + /* Save the end pointer for later use. */ + _tx_el_event_area_end = work_ptr; + + /* Setup an entry to resolve all activities from initialization and from + an idle system. */ + work_ptr = _tx_el_tni_start; + read_ptr = (UCHAR *) "Initialization/System Idle"; + i = 0; + while ((i < TX_EL_TNI_NAME_SIZE) && (*read_ptr)) + { + + /* Copy a character of thread's name into TNI area of log. */ + *work_ptr++ = *read_ptr++; + + /* Increment the character count. */ + i++; + } + + /* Determine if a NULL needs to be inserted. */ + if (i < TX_EL_TNI_NAME_SIZE) + { + + /* Yes, insert a NULL into the event log string. */ + *work_ptr = (unsigned char) 0; + } + + /* Setup the thread ID to NULL. */ + *((ULONG *) (_tx_el_tni_start + TX_EL_TNI_THREAD_ID_OFFSET)) = (ULONG) TX_NULL; + + /* Set the valid field to indicate the entry is complete. */ + *((UCHAR *) (_tx_el_tni_start + TX_EL_TNI_VALID_OFFSET)) = (ULONG) TX_EL_VALID_ENTRY; + + /* Clear the time base global variables. */ + _tx_el_time_base_upper = 0; + _tx_el_time_base_lower = 0; +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_thread_register PORTABLE SMP */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers a thread in the event log for future */ +/* display purposes. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SUCCESS Thread was placed in TNI area */ +/* TX_ERROR No more room in the TNI area */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create ThreadX thread create function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _tx_el_thread_register(TX_THREAD *thread_ptr) +{ + +UCHAR *entry_ptr; +UCHAR *work_ptr; +UCHAR *read_ptr; +UINT i; + + + /* First of all, search for a free slot in the TNI area. */ + entry_ptr = _tx_el_tni_start; + i = 0; + while (i < TX_EL_TNIS) + { + + /* Determine if this entry is available. */ + if (*(entry_ptr + TX_EL_TNI_VALID_OFFSET) == TX_EL_INVALID_ENTRY) + break; + + /* Otherwise, increment the associated pointers and indices. */ + i++; + entry_ptr = entry_ptr + TX_EL_TNI_ENTRY_SIZE; + } + + /* Check to see if there were no more valid entries. */ + if (i >= TX_EL_TNIS) + return(TX_EL_NO_MORE_TNI_ROOM); + + /* Otherwise, we have room in the TNI and a valid record. */ + + /* Setup the thread's name. */ + work_ptr = entry_ptr; + read_ptr = (UCHAR *) thread_ptr -> tx_thread_name; + i = 0; + while ((i < TX_EL_TNI_NAME_SIZE) && (*read_ptr)) + { + + /* Copy a character of thread's name into TNI area of log. */ + *work_ptr++ = *read_ptr++; + + /* Increment the character count. */ + i++; + } + + /* Determine if a NULL needs to be inserted. */ + if (i < TX_EL_TNI_NAME_SIZE) + { + + /* Yes, insert a NULL into the event log string. */ + *work_ptr = (unsigned char) 0; + } + + /* Setup the thread ID. */ + *((ULONG *) (entry_ptr + TX_EL_TNI_THREAD_ID_OFFSET)) = (ULONG) thread_ptr; + + /* Setup the thread priority. */ + *((ULONG *) (entry_ptr + TX_EL_TNI_THREAD_PRIORITY_OFF)) = (ULONG) thread_ptr -> tx_thread_priority; + + /* Set the valid field to indicate the entry is complete. */ + *((UCHAR *) (entry_ptr + TX_EL_TNI_VALID_OFFSET)) = (ULONG) TX_EL_VALID_ENTRY; + + /* Thread name has been registered. */ + return(TX_SUCCESS); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_thread_unregister PORTABLE SMP */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function unregisters a thread in the event log for future */ +/* display purposes. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SUCCESS Thread was placed in TNI area */ +/* TX_ERROR No more room in the TNI area */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create ThreadX thread create function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _tx_el_thread_unregister(TX_THREAD *thread_ptr) +{ + +UCHAR *entry_ptr; +UCHAR *work_ptr; +UCHAR *read_ptr; +UINT found; +UINT i, j; + + + /* First of all, search for a match in the TNI area. */ + entry_ptr = _tx_el_tni_start; + i = 0; + while (i < TX_EL_TNIS) + { + + /* Determine if this entry is a match. */ + work_ptr = entry_ptr; + read_ptr = (UCHAR *) thread_ptr -> tx_thread_name; + found = TX_TRUE; + j = 0; + do + { + + /* Determine if this character is the same. */ + if (*work_ptr != *read_ptr) + { + + /* Set found to false and fall out of the loop. */ + found = TX_FALSE; + break; + } + else if (*work_ptr == 0) + { + + /* Null terminated, just break the loop. */ + break; + } + else + { + + /* Copy a character of thread's name into TNI area of log. */ + *work_ptr++ = *read_ptr++; + } + + /* Increment the character count. */ + j++; + + } while(j < TX_EL_TNIS); + + + /* Was a match found? */ + if (found) + { + + /* Yes, mark the entry as available now. */ + *(entry_ptr + TX_EL_TNI_VALID_OFFSET) = TX_EL_INVALID_ENTRY; + + /* Get out of the loop! */ + break; + } + + /* Otherwise, increment the associated pointers and indices. */ + i++; + entry_ptr = entry_ptr + TX_EL_TNI_ENTRY_SIZE; + } + + /* Determine status to return. */ + if (found) + return(TX_SUCCESS); + else + return(TX_EL_NAME_NOT_FOUND); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_user_event_insert PORTABLE SMP */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function inserts a user event into the event log. */ +/* If the event log is full, the oldest event is overwritten. */ +/* */ +/* INPUT */ +/* */ +/* sub_type Event subtype for kernel call */ +/* info_1 First information field */ +/* info_2 Second information field */ +/* info_3 Third information field */ +/* info_4 Fourth information field */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX services */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_el_user_event_insert(UINT sub_type, ULONG info_1, ULONG info_2, + ULONG info_3, ULONG info_4) +{ + +TX_INTERRUPT_SAVE_AREA + +UINT upper_tb; +UCHAR *entry_ptr; + + /* Disable interrupts. */ + TX_DISABLE + + /* Increment total event counter. */ + _tx_el_total_events++; + + /* Setup working entry pointer first. */ + entry_ptr = *_tx_el_current_event; + + /* Store the event type. */ + *((unsigned short *) entry_ptr) = (unsigned short) TX_EL_USER_EVENT; + + /* Store the event subtype. */ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = + (unsigned short) sub_type; + + /* Get time stamp. */ + do + { + + /* Pickup the upper tb. */ + upper_tb = (ULONG) read_tbu(); + + /* Store the upper time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = + (ULONG) upper_tb; + + /* Store the lower time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) = + (ULONG) read_tbl(); + } while (upper_tb != (ULONG) read_tbu()); + + /* Store the current thread. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) = + (ULONG) _tx_thread_current_ptr[TX_SMP_CORE_ID]; + + /* Store the first info field. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_1_OFFSET)) = + (ULONG) info_1; + + /* Store the second info field. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_2_OFFSET)) = + (ULONG) info_2; + + /* Store the third info field. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_3_OFFSET)) = + (ULONG) info_3; + + /* Store the fourth info field. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_4_OFFSET)) = + (ULONG) info_4; + + /* Now move the current event log pointer. */ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE; + + /* Check for a wraparound condition. */ + if (entry_ptr >= _tx_el_event_area_end) + { + + /* Yes, we have wrapped around to the end of the event area. + Start back at the top! */ + entry_ptr = _tx_el_event_area_start; + } + + /* Write the entry pointer back into the header. */ + *_tx_el_current_event = entry_ptr; + + /* Restore interrupts. */ + TX_RESTORE +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_thread_running PORTABLE SMP */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function inserts a thread change event into the event */ +/* log, which indicates that a context switch is taking place. */ +/* If the event log is full, the oldest event is overwritten. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread being */ +/* scheduled */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_schedule ThreadX scheduler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_el_thread_running(TX_THREAD *thread_ptr) +{ + +UINT upper_tb; +UCHAR *entry_ptr; + + TX_EL_NO_STATUS_EVENTS + + /* Increment total event counter. */ + _tx_el_total_events++; + + /* Setup working entry pointer first. */ + entry_ptr = *_tx_el_current_event; + + /* Store the event type. */ + *((unsigned short *) entry_ptr) = (unsigned short) TX_EL_THREAD_CHANGE; + + /* Store the event subtype. */ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = + (unsigned short) 0; + + /* Get time stamp. */ + do + { + + /* Pickup the upper tb. */ + upper_tb = (ULONG) read_tbu(); + + /* Store the upper time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = + (ULONG) upper_tb; + + /* Store the lower time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) = + (ULONG) read_tbl(); + } while (upper_tb != (ULONG) read_tbu()); + + /* Store the current thread. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) = + (ULONG) thread_ptr; + + /* Now move the current event log pointer. */ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE; + + /* Check for a wraparound condition. */ + if (entry_ptr >= _tx_el_event_area_end) + { + + /* Yes, we have wrapped around to the end of the event area. + Start back at the top! */ + entry_ptr = _tx_el_event_area_start; + } + + /* Write the entry pointer back into the header. */ + *_tx_el_current_event = entry_ptr; + + TX_EL_END_FILTER +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_thread_preempted PORTABLE SMP */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function inserts a thread preempted event into the event */ +/* log, which indicates that an interrupt occurred that made a higher */ +/* priority thread ready for execution. In this case, the previously */ +/* executing thread has an event entered to indicate it is no longer */ +/* running. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread being */ +/* scheduled */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_context_restore ThreadX context restore */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_el_thread_preempted(TX_THREAD *thread_ptr) +{ + +UINT upper_tb; +UCHAR *entry_ptr; + + + TX_EL_NO_STATUS_EVENTS + + /* Increment total event counter. */ + _tx_el_total_events++; + + /* Setup working entry pointer first. */ + entry_ptr = *_tx_el_current_event; + + /* Store the event type. */ + *((unsigned short *) entry_ptr) = (unsigned short) TX_EL_THREAD_STATUS_CHANGE; + + /* Store the event subtype. */ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = + (unsigned short) TX_READY; + + /* Get time stamp. */ + do + { + + /* Pickup the upper tb. */ + upper_tb = (ULONG) read_tbu(); + + /* Store the upper time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = + (ULONG) upper_tb; + + /* Store the lower time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) = + (ULONG) read_tbl(); + } while (upper_tb != (ULONG) read_tbu()); + + /* Store the current thread. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) = + (ULONG) _tx_thread_current_ptr[TX_SMP_CORE_ID]; + + /* Now move the current event log pointer. */ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE; + + /* Check for a wraparound condition. */ + if (entry_ptr >= _tx_el_event_area_end) + { + + /* Yes, we have wrapped around to the end of the event area. + Start back at the top! */ + entry_ptr = _tx_el_event_area_start; + } + + /* Write the entry pointer back into the header. */ + *_tx_el_current_event = entry_ptr; + + TX_EL_END_FILTER +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_interrupt PORTABLE SMP */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function inserts an interrupt event into the log, which */ +/* indicates the start of interrupt processing for the specific */ +/* */ +/* INPUT */ +/* */ +/* interrupt_number Interrupt number supplied by */ +/* ISR */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISR processing */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_el_interrupt(UINT interrupt_number) +{ + +UINT upper_tb; +UCHAR *entry_ptr; + + + TX_EL_NO_INTERRUPT_EVENTS + + /* Increment total event counter. */ + _tx_el_total_events++; + + /* Setup working entry pointer first. */ + entry_ptr = *_tx_el_current_event; + + /* Store the event type. */ + *((unsigned short *) entry_ptr) = (unsigned short) TX_EL_INTERRUPT; + + /* Store the event subtype. */ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = + (unsigned short) TX_EL_INTERRUPT_SUB_TYPE; + + /* Get time stamp. */ + do + { + + /* Pickup the upper tb. */ + upper_tb = (ULONG) read_tbu(); + + /* Store the upper time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = + (ULONG) upper_tb; + + /* Store the lower time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) = + (ULONG) read_tbl(); + } while (upper_tb != (ULONG) read_tbu()); + + /* Store the current thread. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) = + (ULONG) _tx_thread_current_ptr[TX_SMP_CORE_ID]; + + /* Store the first info word. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_1_OFFSET)) = + (ULONG) interrupt_number; + + /* Now move the current event log pointer. */ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE; + + /* Check for a wraparound condition. */ + if (entry_ptr >= _tx_el_event_area_end) + { + + /* Yes, we have wrapped around to the end of the event area. + Start back at the top! */ + entry_ptr = _tx_el_event_area_start; + } + + /* Write the entry pointer back into the header. */ + *_tx_el_current_event = entry_ptr; + + TX_EL_END_FILTER +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_interrupt_end PORTABLE SMP */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function inserts an interrupt end event into the log, which */ +/* indicates the end of interrupt processing for the specific */ +/* */ +/* INPUT */ +/* */ +/* interrupt_number Interrupt number supplied by */ +/* ISR */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISR processing */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_el_interrupt_end(UINT interrupt_number) +{ + +UINT upper_tb; +UCHAR *entry_ptr; + + + TX_EL_NO_INTERRUPT_EVENTS + + /* Increment total event counter. */ + _tx_el_total_events++; + + /* Setup working entry pointer first. */ + entry_ptr = *_tx_el_current_event; + + /* Store the event type. */ + *((unsigned short *) entry_ptr) = (unsigned short) TX_EL_INTERRUPT; + + /* Store the event subtype. */ + *((unsigned short *) (entry_ptr + TX_EL_EVENT_SUBTYPE_OFFSET)) = + (unsigned short) TX_EL_END_OF_INTERRUPT; + + /* Get time stamp. */ + do + { + + /* Pickup the upper tb. */ + upper_tb = (ULONG) read_tbu(); + + /* Store the upper time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) = + (ULONG) upper_tb; + + /* Store the lower time stamp. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) = + (ULONG) read_tbl(); + } while (upper_tb != (ULONG) read_tbu()); + + /* Store the current thread. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_THREAD_OFFSET)) = + (ULONG) _tx_thread_current_ptr[TX_SMP_CORE_ID]; + + /* Store the first info word. */ + *((ULONG *) (entry_ptr + TX_EL_EVENT_INFO_1_OFFSET)) = + (ULONG) interrupt_number; + + /* Now move the current event log pointer. */ + entry_ptr = entry_ptr + TX_EL_EVENT_SIZE; + + /* Check for a wraparound condition. */ + if (entry_ptr >= _tx_el_event_area_end) + { + + /* Yes, we have wrapped around to the end of the event area. + Start back at the top! */ + entry_ptr = _tx_el_event_area_start; + } + + /* Write the entry pointer back into the header. */ + *_tx_el_current_event = entry_ptr; + + TX_EL_END_FILTER +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_interrupt_control PORTABLE SMP */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function remaps the tx_interrupt_control service call so that */ +/* it can be tracked in the event log. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt posture */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_interrupt_control Interrupt control service */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX services */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _tx_el_interrupt_control(UINT new_posture) +{ + +TX_INTERRUPT_SAVE_AREA +UINT old_posture; + + + TX_EL_NO_INTERRUPT_EVENTS + + TX_DISABLE + TX_EL_KERNEL_CALL_EVENT_INSERT_INFO2(TX_EL_INTERRUPT_CONTROL, _tx_thread_current_ptr[TX_SMP_CORE_ID], new_posture) + TX_RESTORE + + TX_EL_END_FILTER + + old_posture = _tx_thread_interrupt_control(new_posture); + return(old_posture); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_event_log_on PORTABLE SMP */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function disables all event filters. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_el_event_log_on(void) +{ + + /* Disable all event filters. */ + _tx_el_event_filter = TX_EL_ENABLE_ALL_EVENTS; +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_event_log_off PORTABLE SMP */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets all event filters, thereby turning event */ +/* logging off. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_el_event_log_off(void) +{ + + /* Set all event filters. */ + _tx_el_event_filter = TX_EL_FILTER_ALL_EVENTS; +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_el_event_log_set PORTABLE SMP */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets the events filters specified by the user. */ +/* */ +/* INPUT */ +/* */ +/* filter Events to filter */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_el_event_filter_set(UINT filter) +{ + + /* Apply the user event filter. */ + _tx_el_event_filter = filter; +} + diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_ghs.c b/ports_smp/cortex_a5x_smp/green/src/tx_ghs.c new file mode 100644 index 00000000..6909aa54 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/src/tx_ghs.c @@ -0,0 +1,502 @@ +/* + * ThreadX C/C++ Library Support + * + * Copyright 1983-2019 Green Hills Software LLC. + * + * This program is the property of Green Hills Software LLC., + * its contents are proprietary information and no part of it + * is to be disclosed to anyone except employees of Green Hills + * Software LLC., or as agreed in writing signed by the President + * of Green Hills Software LLC. + */ + +#define TX_THREAD_SMP_SOURCE_CODE + +#include "tx_ghs.h" +#ifndef TX_DISABLE_ERROR_CHECKING +#define TX_DISABLE_ERROR_CHECKING +#endif +#include "tx_api.h" +#include +#include + +/* Allow these routines to access the following ThreadX global variables. */ +extern ULONG _tx_thread_created_count; +extern TX_THREAD *_tx_thread_created_ptr; +/* extern TX_THREAD *_tx_thread_current_ptr[]; Not referenced directly in SMP. */ + +#if defined(__ghs) && (__GHS_VERSION_NUMBER >= 500) +/* Thread-local storage routines for Green Hills releases 5.x and above. */ +/* + Thread-Local (Per-Thread) Library Data Retrieval + ================================================ + + __ghs_ThreadLocalStorage_specifier defines all library data items + that the Green Hills libraries allow to be allocated per-thread. + + An implementation can choose which of these data items to allocate + for each thread. For example, an implementation may choose to + allocate an errno value for each thread, but not the strtok_saved_pos + pointer. The application could then use strtok_r instead of strtok for + correct operation. + + To add per-thread library data, define one of the + TX_THREAD_EXTENSION_* macros in tx_port.h to include the data item + or items in each thread control block TX_THREAD. + + If C++ with exceptions is being used, the __eh_globals entry must be + allocated for each thread. This is typically done by default using + TX_THREAD_EXTENSION_1 in tx_port.h. + + If __ghs_GetThreadLocalStorageItem is customized to return a + per-thread errno value, you should also: + + * Customize the System Library for your project + * Define the preprocessor symbol USE_THREAD_LOCAL_ERRNO in + src/libsys/ind_errn.c + + If you customize the System Library, you should remove ind_thrd.c + from the libsys.gpj subproject. + + */ + +/* Provide global __eh_globals value to support C++ exception handling + outside a thread context. This name also forces this module to be + included in the linked program instead of the ind_thrd.o module from + the System Library libsys.a. + */ +static void *__eh_globals; + +#pragma ghs startnomisra +void *__ghs_GetThreadLocalStorageItem(int specifier) +{ + void *ptlsitem = (void *)0; + TX_THREAD *current_thread_ptr; + + /* Pickup current thread pointer. */ + TX_THREAD_GET_CURRENT(current_thread_ptr) + + switch (specifier) { + case (int)__ghs_TLS_Errno: + /* Set ptslsitem to the address of the per-thread errno value. + The per-thread errno value should have the type int. + + If returning a per-thread errno value, follow the steps + above. + + This item is used by numerous library functions. + */ + break; + case (int)__ghs_TLS_SignalHandlers: + /* Set ptslsitem to the address of the per-thread SignalHandlers + array. The per-thread SignalHandlers array should have the + array type as in the following declaration: + SignalHandler SignalHandlers[_SIGMAX]; + The SignalHandler type and _SIGMAX constant are defined in + ind_thrd.h. + + This item is used by the library functions signal() and + raise(). + */ + break; + case (int)__ghs_TLS_asctime_buff: + /* Set ptslsitem to the address of the per-thread asctime_buff + array. The per-thread asctime_buff array should have the + array type as in the following declaration: + char asctime_buff[30]; + + This item is used by the library functions asctime() and + ctime(). The library provides asctime_r() and ctime_r(), + inherently thread-safe versions of these functions. + */ + break; + case (int)__ghs_TLS_tmpnam_space: + /* Set ptslsitem to the address of the per-thread tmpnam_space + array. The per-thread tmpnam_space array should have the + array type as in the following declaration: + char tmpnam_space[L_tmpnam]; + The constant is defined in + + This item is used by the library function tmpnam() when + passed NULL. The library provides tmpnam_r(), an + inherently thread-safe version of tmpnam(). + */ + break; + case (int)__ghs_TLS_strtok_saved_pos: + /* Set ptslsitem to the address of the per-thread + strtok_saved_pos pointer. The per-thread strtok_saved_pos + pointer should have the type "char *". + + This item is used by the library function strtok(). + The library provides strtok_r(), an inherently thread-safe + version of strtok(). + */ + break; + case (int)__ghs_TLS_gmtime_temp: + /* Set ptslsitem to the address of the per-thread gmtime_temp + value. The per-thread gmtime_temp value should have the + type "struct tm" defined in time.h, included by indos.h. + + This item is used by the library functions gmtime() and + localtime(). The library provides gmtime_r() and + localtime_r(), inherently thread-safe versions of these + functions. + */ + break; + case (int)__ghs_TLS___eh_globals: + /* Set ptslsitem to the address of the per-thread __eh_globals + value. The per-thread __eh_globals value should have the + type "void *". + + This item is used by C++ exception handling. + */ + if (current_thread_ptr) + ptlsitem = (void *)&(current_thread_ptr->tx_thread_eh_globals); + else + /* Use the global __eh_globals pointer. */ + ptlsitem = (void *)&__eh_globals; + break; + } + return ptlsitem; +} + +// Force this file to be pulled into the program when linking with this +// library. +#pragma ghs alias __ghsautoimport_tx_ghs __ghs_GetThreadLocalStorageItem + +#pragma ghs endnomisra +#else +/* Thread-local storage routines for Green Hills releases 4.x and 3.x . */ + +/* + * ThreadX C and C++ thread-safe library support routines. + * + * This implementation merely tries to guarantee thread safety within + * individual C library calls such as malloc() and free(), but it does + * not attempt to solve the problems associated with the following + * multithreaded issues: + * + * 1. Use of errno. This can be made thread-safe by adding errno + * to TX_THREAD_PORT_EXTENSION and using that within a modified + * version of libsys/ind_errno.c. + * + * 2. Thread safety ACROSS library calls. Certain C library calls either + * return pointers to statically-allocated data structures or maintain + * state across calls. These include strtok(), asctime(), gmtime(), + * tmpnam(NULL), signal(). To make such C library routines thread-safe + * would require adding a ThreadLocalStorage struct to the thread control + * block TX_THREAD. Since relatively few applications make use of these + * library routines, the implementation provided here uses a single, global + * ThreadLocalStorage data structure rather than greatly increasing the size + * of the thread control block TX_THREAD. + * + * The ThreadX global variable _tx_thread_current_ptr points to the + * current thread's control block TX_THREAD. If a ThreadLocalStorage struct + * called tx_tls is placed in TX_THREAD, the function GetThreadLocalStorage + * should be modified to return &(_tx_thread_current_ptr->tx_tls). + */ + +static ThreadLocalStorage GlobalTLS; + +ThreadLocalStorage *GetThreadLocalStorage() +{ + return &GlobalTLS; +} +#endif + +/* + * Use a global ThreadX mutex to implement thread safety within C and C++ + * library routines. + * + */ +TX_MUTEX __ghLockMutex; + +/* + * Acquire general lock. Blocks until the lock becomes available. + * Use tx_mutex_get to implement __ghsLock + */ +void __ghsLock(void) +{ + tx_mutex_get(&__ghLockMutex, TX_WAIT_FOREVER); +} + +/* + * Release general lock + * Use tx_mutex_put to implement __ghsUnlock + */ +void __ghsUnlock(void) +{ + tx_mutex_put(&__ghLockMutex); +} + +/* ThreadX Initialization function prototype. */ +void _tx_initialize_kernel_setup(void); + +void __gh_lock_init(void) +{ + /* Initialize the low-level portions of ThreadX. */ + _tx_initialize_kernel_setup(); + + /* Create the global thread lock mutex. */ + tx_mutex_create(&__ghLockMutex, "__ghLockMutex", TX_NO_INHERIT); +} + +/* + Saving State Across setjmp() Calls + ================================== + + These routines can be used to save and restore arbitrary state + across calls to setjmp() and longjmp(). +*/ +int __ghs_SaveSignalContext(jmp_buf jmpbuf) +{ + return 0; +} + +/* Restore arbitrary state across a longjmp() */ +void __ghs_RestoreSignalContext(jmp_buf jmpbuf) +{ +} + +#if defined(__GHS_VERSION_NUMBER) && (__GHS_VERSION_NUMBER < 560) +/* + C++ Exception Handling + ====================== + + These routines allow C++ exceptions to be used in multiple threads. + The default implementation uses __ghs_GetThreadLocalStorageItem + to return a thread-specific __eh_globals pointer. + +*/ + +/* Must be called after __cpp_exception_init() is called to allocate + * and initialize the per-thread exception handling structure */ +void *__get_eh_globals(void) +{ +#if defined(__ghs) && (__GHS_VERSION_NUMBER >= 500) + return *(void **)__ghs_GetThreadLocalStorageItem(__ghs_TLS___eh_globals); +#else +TX_THREAD *current_thread_ptr; + + /* Pickup current thread pointer. */ + TX_THREAD_GET_CURRENT(current_thread_ptr) + + if (current_thread_ptr) + + /* Return thread-specific __eh_globals pointer. */ + return current_thread_ptr->tx_thread_eh_globals; + else + /* Return the global __eh_globals pointer. */ + return GlobalTLS.__eh_globals; +#endif +} +#endif + +#if defined(__ghs) && (__GHS_VERSION_NUMBER >= 500) +#pragma weak __cpp_exception_init +extern void __cpp_exception_init(void **); +#pragma weak __cpp_exception_cleanup +extern void __cpp_exception_cleanup(void **); + +/* __tx_cpp_exception_init retrieves the eh_globals field from + thread-local storage and calls __cpp_exception_init. + */ +void __tx_cpp_exception_init(TX_THREAD *thread_ptr) { + void **peh_globals; + if(__cpp_exception_init) { + if (thread_ptr) + peh_globals = &(thread_ptr->tx_thread_eh_globals); + else + /* Use the global __eh_globals pointer. */ + peh_globals = &__eh_globals; + __cpp_exception_init(peh_globals); + } +} + +/* __tx_cpp_exception_cleanup retrieves the eh_globals field from + thread-local storage and calls __cpp_exception_cleanup. + */ +void __tx_cpp_exception_cleanup(TX_THREAD *thread_ptr) { + void **peh_globals; + if(__cpp_exception_cleanup) { + if (thread_ptr) + peh_globals = &(thread_ptr->tx_thread_eh_globals); + else + /* Use the global __eh_globals pointer. */ + peh_globals = &__eh_globals; + __cpp_exception_cleanup(peh_globals); + } +} + +/* __ghs_cpp_exception_init is called from ind_crt1.o to initialize + exceptions for the global context. + */ +void __ghs_cpp_exception_init() { + __tx_cpp_exception_init((void *)0); +} + +/* __ghs_cpp_exception_cleanup is called from ind_exit.o to clean up + exceptions for the global context. + */ +void __ghs_cpp_exception_cleanup(TX_THREAD *thread_ptr) { + __tx_cpp_exception_cleanup((void *)0); +} +#endif + + +/* + File Locks + ====================== + + These routines can be customized to implement per-file locks to allow + thread-safe I/O. + +*/ + +/* Acquire lock for FILE *addr */ +void __ghs_flock_file(void *addr) +{ + tx_mutex_get((TX_MUTEX *)addr, TX_WAIT_FOREVER); +} + +/* Release lock for FILE *addr */ +void __ghs_funlock_file(void *addr) +{ + tx_mutex_put((TX_MUTEX *)addr); +} + +/* Non blocking acquire lock for FILE *addr. May return -1 if */ +/* not implemented. Returns 0 on success and nonzero otherwise. */ +int __ghs_ftrylock_file(void *addr) +{ + return -1; +} + +/* Calls to initialize local lock data structures before they */ +/* are used. */ +void __ghs_flock_create(void **addr) +{ + *addr = (void *)(&__ghLockMutex); +} +void __ghs_flock_destroy(void *addr) {} + + +/* + * ThreadX Peak Stack Checking support routines. + * + * All of these routines are called by MULTI's ThreadX-aware debugging + * package to determine the peak stack use for one thread or for all threads. + * + * These routines are included in this file in order to guarantee that they will + * be available while debugging with MULTI. These routines are not referenced by + * any other part of the ThreadX system. + * + * _txs_thread_stack_check: return the peak stack usage for a thread. + * + * _txs_thread_stack_check_2: store the peak stack usage for all threads + * in the tx_thread_stack_size field of each thread + * control block, TX_THREAD. This routine takes + * advantage of the redundancy within the TX_THREAD + * structure since tx_thread_stack_size can be computed + * from the tx_thread_stack_start and tx_thread_stack_end + * fields of TX_THREAD. + * + * _txs_thread_stack_check_2_fixup: clean up from the _txs_thread_stack_check_2 + * call by computing the stack size for each + * thread and storing the result in the + * tx_thread_stack_size field of each thread control + * block TX_THREAD. + * + * These three routines do not support architectures such as i960 or StarCore + * where the stack grows up instead of down. + * + */ +#ifndef TX_DISABLE_STACK_CHECKING + +ULONG _txs_thread_stack_check(TX_THREAD *thread_ptr) +{ + CHAR *cp; /* Pointer inside thread's stack. */ + + /* Search through the thread's stack to find the highest address modified. */ + for ( cp = (CHAR *)thread_ptr->tx_thread_stack_start; + cp <= (CHAR *)thread_ptr->tx_thread_stack_end; ++cp ) { + + /* Check if this byte in the stack contains something other than TX_STACK_FILL. */ + if (*cp != (char)TX_STACK_FILL) { + + /* Assume cp points to the locating marking the peak stack use. + Return the number of bytes from cp up to and including the + end of the stack. */ + return (((CHAR *)thread_ptr->tx_thread_stack_end) - (CHAR *)cp + 1); + } + } + return thread_ptr->tx_thread_stack_size; +} + + +int _txs_thread_stack_check_2(void) { + CHAR * cp; /* Pointer inside thread's stack. */ + TX_THREAD * tp; /* Pointer to each thread. */ + + /* If no threads are created, return immediately. */ + if (!_tx_thread_created_count) + return 0; + + /* Start iterating through the threads in the system. Assume that we always + have at least one thread (the system timer thread) in the system. */ + tp = _tx_thread_created_ptr; + + do { + + /* Search through the thread's stack to find the highest address modified. */ + for ( cp = (CHAR *)tp->tx_thread_stack_start; cp <= (CHAR *)tp->tx_thread_stack_end; + ++cp ) { + + /* Check if this byte in the stack contains something other than TX_STACK_FILL. */ + if (*cp != (char)TX_STACK_FILL) { + + /* Assume cp points to the locating marking the peak stack use. + Store the number of bytes from cp up to and including the + end of the stack in the tx_thread_stack_size field. */ + tp->tx_thread_stack_size = ((CHAR *)tp->tx_thread_stack_end) - (CHAR *)cp + 1; + break; + } + + } + + /* Continue with the next thread. */ + tp = tp->tx_thread_created_next; + + /* Loop until we point to the first thread again. */ + } while ( tp != _tx_thread_created_ptr ); + + return 0; +} + +int _txs_thread_stack_check_2_fixup(void) { + TX_THREAD * tp; /* Pointer to each thread. */ + + /* If no threads are created, return immediately. */ + if (!_tx_thread_created_count) + return 0; + + /* Start iterating through the threads in the system. Assume that we always + have at least one thread (the system timer thread) in the system. */ + tp = _tx_thread_created_ptr; + + do { + + /* Compute the tx_thread_stack_size field by using the tx_thread_stack_end and + tx_thread_stack_start fields. */ + tp->tx_thread_stack_size = (CHAR *)tp->tx_thread_stack_end-(CHAR *)tp->tx_thread_stack_start+1; + + /* Continue with the next thread. */ + tp = tp->tx_thread_created_next; + + /* Loop until we point to the first thread again. */ + } while ( tp != _tx_thread_created_ptr ); + + return 0; +} + +#endif /* TX_DISABLE_STACK_CHECKING */ diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_initialize_low_level.a64 b/ports_smp/cortex_a5x_smp/green/src/tx_initialize_low_level.a64 new file mode 100644 index 00000000..4c0a1a83 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/src/tx_initialize_low_level.a64 @@ -0,0 +1,162 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global _tx_thread_context_save + .global _tx_thread_context_restore + .global __ghsbegin_free_mem + +#ifndef TX_PLATFORM_IRQ_MAX +#define TX_PLATFORM_IRQ_MAX 192 // Size of IRQ handlers table +#endif + + .global _tx_platform_initialize_low_level + .global _tx_platform_irq_handlers + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-A5x-SMP/GHS */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_initialize_low_level(VOID) +{ */ + .global _tx_initialize_low_level + .type _tx_initialize_low_level, @function +_tx_initialize_low_level: + + MSR DAIFSet, 0x3 // Lockout interrupts + + + /* Save the system stack pointer. */ + /* _tx_thread_system_stack_ptr = (VOID_PTR) (sp); */ + + LDR x0, =_tx_thread_system_stack_ptr // Pickup address of system stack ptr + MOV x1, sp // Pickup SP + SUB x1, x1, #15 // + AND x1, x1, #~0xF // Get 16-bit alignment + STR x1, [x0] // Store system stack + + /* Save the first available memory address. */ + /* _tx_initialize_unused_memory = (VOID_PTR) _end; */ + + LDR x0, =_tx_initialize_unused_memory // Pickup address of unused memory ptr + LDR x1, =__ghsbegin_free_mem // Pickup unused memory address - A free + STR x1, [x0] // Store unused memory address + + /* Call _tx_platform_initialize_low_level to initialize the interrupt controller and + setup a timer for periodic interrupts. */ + + STP x29, x30, [sp, #-16]! + BL _tx_platform_initialize_low_level + LDP x29, x30, [sp], #16 + + /* Done, return to caller. */ + + RET // Return to caller +/* } */ + + +/* IRQ Handler */ + .global __tx_irq_handler +__tx_irq_handler: + + STP x29, x30, [sp, #-16]! + BL _tx_thread_context_save // save system context + + STP x20, x21, [sp, #-16]! // save working registers + + // acknowledge the interrupt + MRS x20, S3_1_C15_C3_0 // read CBAR + ADD x20, x20, #0x20000 // CPU interface base address + LDR w21, [x20, #0xc] // read interrupt ID from GICC_IAR + LDR w0, =0x3ff + AND w1, w0, w21 // keep only ACKINTID bits + LDR w0, =TX_PLATFORM_IRQ_MAX + CMP w1, w0 + B.GE tx_irq_done // ignore spurious interrupts + + // call interrupt handler + LDR x2, =_tx_platform_irq_handlers // irq_handlers table address + ADD x2, x2, w1, UXTW #4 // irq_handlers + irq_id * 16 + LDR x1, [x2] // handler + LDR x0, [x2, #8] // data + BLR x1 // call handler + +tx_irq_done: + // signal end of interrupt + STR w21, [x20, #0x10] // write interrupt ID to GICC_EOIR + + LDP x20, x21, [sp], #16 // restore working registers + + B _tx_thread_context_restore // restore system context diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_thread_context_restore.a64 b/ports_smp/cortex_a5x_smp/green/src/tx_thread_context_restore.a64 new file mode 100644 index 00000000..21e41ab8 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/src/tx_thread_context_restore.a64 @@ -0,0 +1,317 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + +/* .set ENABLE_ARM_FP,1 */ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore Cortex-A5x-SMP/GHS */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores the interrupt context if it is processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_restore(VOID) +{ */ + .global _tx_thread_context_restore + .type _tx_thread_context_restore, @function +_tx_thread_context_restore: + + /* Lockout interrupts. */ + + MSR DAIFSet, 0x3 // Lockout interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR exit function to indicate an ISR is complete. */ + + BL _tx_execution_isr_exit // Call the ISR exit function +#endif + + /* Pickup the CPU ID. */ + + MRS x8, MPIDR_EL1 // Pickup the core ID + UBFX x8, x8, #0, #8 // Isolate and right justify core ID + + /* Determine if interrupts are nested. */ + /* if (--_tx_thread_system_state) + { */ + + LDR x3, =_tx_thread_system_state // Pickup address of system state var + LDR w2, [x3, x8, LSL #2] // Pickup system state + SUB w2, w2, #1 // Decrement the counter + STR w2, [x3, x8, LSL #2] // Store the counter + CMP w2, #0 // Was this the first interrupt? + B.EQ __tx_thread_not_nested_restore // If so, not a nested restore + + /* Interrupts are nested. */ + + /* Just recover the saved registers and return to the point of + interrupt. */ + + LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL +#ifdef EL1 + MSR SPSR_EL1, x4 // Setup SPSR for return + MSR ELR_EL1, x5 // Setup point of interrupt +#else +#ifdef EL2 + MSR SPSR_EL2, x4 // Setup SPSR for return + MSR ELR_EL2, x5 // Setup point of interrupt +#else + MSR SPSR_EL3, x4 // Setup SPSR for return + MSR ELR_EL3, x5 // Setup point of interrupt +#endif +#endif + LDP x18, x19, [sp], #16 // Recover x18, x19 + LDP x16, x17, [sp], #16 // Recover x16, x17 + LDP x14, x15, [sp], #16 // Recover x14, x15 + LDP x12, x13, [sp], #16 // Recover x12, x13 + LDP x10, x11, [sp], #16 // Recover x10, x11 + LDP x8, x9, [sp], #16 // Recover x8, x9 + LDP x6, x7, [sp], #16 // Recover x6, x7 + LDP x4, x5, [sp], #16 // Recover x4, x5 + LDP x2, x3, [sp], #16 // Recover x2, x3 + LDP x0, x1, [sp], #16 // Recover x0, x1 + LDP x29, x30, [sp], #16 // Recover x29, x30 + ERET // Return to point of interrupt + + /* } */ +__tx_thread_not_nested_restore: + + /* Determine if a thread was interrupted and no preemption is required. */ + /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) + || (_tx_thread_preempt_disable)) + { */ + + LDR x1, =_tx_thread_current_ptr // Pickup address of current thread ptr + LDR x0, [x1, x8, LSL #3] // Pickup actual current thread pointer + CMP x0, #0 // Is it NULL? + B.EQ __tx_thread_idle_system_restore // Yes, idle system was interrupted + LDR x3, =_tx_thread_execute_ptr // Pickup address of execute thread ptr + LDR x2, [x3, x8, LSL #3] // Pickup actual execute thread pointer + CMP x0, x2 // Is the same thread highest priority? + B.EQ __tx_thread_no_preempt_restore // Same thread in the execute list, + // no preemption needs to happen + LDR x3, =_tx_thread_smp_protection // Build address to protection structure + LDR w3, [x3, #4] // Pickup the owning core + CMP w3, w8 // Is it this core? + B.NE __tx_thread_preempt_restore // No, proceed to preempt thread + + LDR x3, =_tx_thread_preempt_disable // Pickup preempt disable address + LDR w2, [x3, #0] // Pickup actual preempt disable flag + CMP w2, #0 // Is it set? + B.EQ __tx_thread_preempt_restore // No, okay to preempt this thread + +__tx_thread_no_preempt_restore: + + /* Restore interrupted thread or ISR. */ + + /* Pickup the saved stack pointer. */ + /* sp = _tx_thread_current_ptr -> tx_thread_stack_ptr; */ + + LDR x4, [x0, #8] // Switch to thread stack pointer + MOV sp, x4 // + + /* Recover the saved context and return to the point of interrupt. */ + + LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL1 +#ifdef EL1 + MSR SPSR_EL1, x4 // Setup SPSR for return + MSR ELR_EL1, x5 // Setup point of interrupt +#else +#ifdef EL2 + MSR SPSR_EL2, x4 // Setup SPSR for return + MSR ELR_EL2, x5 // Setup point of interrupt +#else + MSR SPSR_EL3, x4 // Setup SPSR for return + MSR ELR_EL3, x5 // Setup point of interrupt +#endif +#endif + LDP x18, x19, [sp], #16 // Recover x18, x19 + LDP x16, x17, [sp], #16 // Recover x16, x17 + LDP x14, x15, [sp], #16 // Recover x14, x15 + LDP x12, x13, [sp], #16 // Recover x12, x13 + LDP x10, x11, [sp], #16 // Recover x10, x11 + LDP x8, x9, [sp], #16 // Recover x8, x9 + LDP x6, x7, [sp], #16 // Recover x6, x7 + LDP x4, x5, [sp], #16 // Recover x4, x5 + LDP x2, x3, [sp], #16 // Recover x2, x3 + LDP x0, x1, [sp], #16 // Recover x0, x1 + LDP x29, x30, [sp], #16 // Recover x29, x30 + ERET // Return to point of interrupt + + /* } + else + { */ +__tx_thread_preempt_restore: + + LDR x4, [x0, #8] // Switch to thread stack pointer + MOV sp, x4 // + + LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL1 + STP x20, x21, [sp, #-16]! // Save x20, x21 + STP x22, x23, [sp, #-16]! // Save x22, x23 + STP x24, x25, [sp, #-16]! // Save x24, x25 + STP x26, x27, [sp, #-16]! // Save x26, x27 + STP x28, x29, [sp, #-16]! // Save x28, x29 +#ifdef ENABLE_ARM_FP + LDR w3, [x0, #268] // Pickup FP enable flag + CMP w3, #0 // Is FP enabled? + B.EQ _skip_fp_save // No, skip FP save + STP q0, q1, [sp, #-32]! // Save q0, q1 + STP q2, q3, [sp, #-32]! // Save q2, q3 + STP q4, q5, [sp, #-32]! // Save q4, q5 + STP q6, q7, [sp, #-32]! // Save q6, q7 + STP q8, q9, [sp, #-32]! // Save q8, q9 + STP q10, q11, [sp, #-32]! // Save q10, q11 + STP q12, q13, [sp, #-32]! // Save q12, q13 + STP q14, q15, [sp, #-32]! // Save q14, q15 + STP q16, q17, [sp, #-32]! // Save q16, q17 + STP q18, q19, [sp, #-32]! // Save q18, q19 + STP q20, q21, [sp, #-32]! // Save q20, q21 + STP q22, q23, [sp, #-32]! // Save q22, q23 + STP q24, q25, [sp, #-32]! // Save q24, q25 + STP q26, q27, [sp, #-32]! // Save q26, q27 + STP q28, q29, [sp, #-32]! // Save q28, q29 + STP q30, q31, [sp, #-32]! // Save q30, q31 + MRS x2, FPSR // Pickup FPSR + MRS x3, FPCR // Pickup FPCR + STP x2, x3, [sp, #-16]! // Save FPSR, FPCR +_skip_fp_save: +#endif + STP x4, x5, [sp, #-16]! // Save x4 (SPSR_EL3), x5 (ELR_E3) + + MOV x3, sp // Move sp into x3 + STR x3, [x0, #8] // Save stack pointer in thread control + // block + LDR x3, =_tx_thread_system_stack_ptr // Pickup address of system stack + LDR x4, [x3, x8, LSL #3] // Pickup system stack pointer + MOV sp, x4 // Setup system stack pointer + + + /* Save the remaining time-slice and disable it. */ + /* if (_tx_timer_time_slice) + { */ + + LDR x3, =_tx_timer_time_slice // Pickup time-slice variable address + LDR w2, [x3, x8, LSL #2] // Pickup time-slice + CMP w2, #0 // Is it active? + B.EQ __tx_thread_dont_save_ts // No, don't save it + + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + STR w2, [x0, #36] // Save thread's time-slice + MOV w2, #0 // Clear value + STR w2, [x3, x8, LSL #2] // Disable global time-slice flag + + /* } */ +__tx_thread_dont_save_ts: + + + /* Clear the current task pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + MOV x2, #0 // NULL value + STR x2, [x1, x8, LSL #3] // Clear current thread pointer + + /* Set bit indicating this thread is ready for execution. */ + + MOV x2, #1 // Build ready flag + DMB ISH // Ensure that accesses to shared resource have completed + STR w2, [x0, #260] // Set thread's ready flag + + /* Return to the scheduler. */ + /* _tx_thread_schedule(); */ + + /* } */ + +__tx_thread_idle_system_restore: + + /* Just return back to the scheduler! */ + + LDR x1, =_tx_thread_schedule // Build address for _tx_thread_schedule +#ifdef EL1 + MSR ELR_EL1, x1 // Setup point of interrupt +// MOV x1, #0x4 // Setup EL1 return +// MSR spsr_el1, x1 // Move into SPSR +#else +#ifdef EL2 + MSR ELR_EL2, x1 // Setup point of interrupt +// MOV x1, #0x8 // Setup EL2 return +// MSR spsr_el2, x1 // Move into SPSR +#else + MSR ELR_EL3, x1 // Setup point of interrupt +// MOV x1, #0xC // Setup EL3 return +// MSR spsr_el3, x1 // Move into SPSR +#endif +#endif + ERET // Return to scheduler +/* } */ + + diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_thread_context_save.a64 b/ports_smp/cortex_a5x_smp/green/src/tx_thread_context_save.a64 new file mode 100644 index 00000000..363a0aaa --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/src/tx_thread_context_save.a64 @@ -0,0 +1,236 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save Cortex-A5x-SMP/GHS */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_save(VOID) +{ */ + .global _tx_thread_context_save + .type _tx_thread_context_save, @function +_tx_thread_context_save: + + /* Upon entry to this routine, it is assumed that IRQ/FIQ interrupts are locked + out, x29 (frame pointer), x30 (link register) are saved, we are in the proper EL, + and all other registers are intact. */ + + /* Check for a nested interrupt condition. */ + /* if (_tx_thread_system_state++) + { */ + + STP x0, x1, [sp, #-16]! // Save x0, x1 + STP x2, x3, [sp, #-16]! // Save x2, x3 + + /* Pickup the CPU ID. */ + + MRS x1, MPIDR_EL1 // Pickup the core ID + UBFX x1, x1, #0, #8 // Isolate and right justify core ID + + LDR x3, =_tx_thread_system_state // Pickup address of system state var + LDR w2, [x3, x1, LSL #2] // Pickup system state + CMP w2, #0 // Is this the first interrupt? + B.EQ __tx_thread_not_nested_save // Yes, not a nested context save + + /* Nested interrupt condition. */ + + ADD w2, w2, #1 // Increment the nested interrupt counter + STR w2, [x3, x1, LSL #2] // Store it back in the variable + + /* Save the rest of the scratch registers on the stack and return to the + calling ISR. */ + + STP x4, x5, [sp, #-16]! // Save x4, x5 + STP x6, x7, [sp, #-16]! // Save x6, x7 + STP x8, x9, [sp, #-16]! // Save x8, x9 + STP x10, x11, [sp, #-16]! // Save x10, x11 + STP x12, x13, [sp, #-16]! // Save x12, x13 + STP x14, x15, [sp, #-16]! // Save x14, x15 + STP x16, x17, [sp, #-16]! // Save x16, x17 + STP x18, x19, [sp, #-16]! // Save x18, x19 +#ifdef EL1 + MRS x0, SPSR_EL1 // Pickup SPSR + MRS x1, ELR_EL1 // Pickup ELR (point of interrupt) +#else +#ifdef EL2 + MRS x0, SPSR_EL2 // Pickup SPSR + MRS x1, ELR_EL2 // Pickup ELR (point of interrupt) +#else + MRS x0, SPSR_EL3 // Pickup SPSR + MRS x1, ELR_EL3 // Pickup ELR (point of interrupt) +#endif +#endif + STP x0, x1, [sp, #-16]! // Save SPSR, ELR + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + STP x29, x30, [sp, #-16]! // Save x29, x30 + BL _tx_execution_isr_enter // Call the ISR enter function + LDP x29, x30, [sp], #16 // Recover x29, x30 +#endif + + /* Return to the ISR. */ + + RET // Return to ISR + +__tx_thread_not_nested_save: + /* } */ + + /* Otherwise, not nested, check to see if a thread was running. */ + /* else if (_tx_thread_current_ptr) + { */ + + ADD w2, w2, #1 // Increment the interrupt counter + STR w2, [x3, x1, LSL #2] // Store it back in the variable + LDR x2, =_tx_thread_current_ptr // Pickup address of current thread ptr + LDR x0, [x2, x1, LSL #3] // Pickup current thread pointer + CMP x0, #0 // Is it NULL? + B.EQ __tx_thread_idle_system_save // If so, interrupt occurred in + // scheduling loop - nothing needs saving! + + /* Save minimal context of interrupted thread. */ + + STP x4, x5, [sp, #-16]! // Save x4, x5 + STP x6, x7, [sp, #-16]! // Save x6, x7 + STP x8, x9, [sp, #-16]! // Save x8, x9 + STP x10, x11, [sp, #-16]! // Save x10, x11 + STP x12, x13, [sp, #-16]! // Save x12, x13 + STP x14, x15, [sp, #-16]! // Save x14, x15 + STP x16, x17, [sp, #-16]! // Save x16, x17 + STP x18, x19, [sp, #-16]! // Save x18, x19 +#ifdef EL1 + MRS x4, SPSR_EL1 // Pickup SPSR + MRS x5, ELR_EL1 // Pickup ELR (point of interrupt) +#else +#ifdef EL2 + MRS x4, SPSR_EL2 // Pickup SPSR + MRS x5, ELR_EL2 // Pickup ELR (point of interrupt) +#else + MRS x4, SPSR_EL3 // Pickup SPSR + MRS x5, ELR_EL3 // Pickup ELR (point of interrupt) +#endif +#endif + STP x4, x5, [sp, #-16]! // Save SPSR, ELR + + /* Save the current stack pointer in the thread's control block. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ + + MOV x4, sp // + STR x4, [x0, #8] // Save thread stack pointer + + /* Switch to the system stack. */ + /* sp = _tx_thread_system_stack_ptr; */ + + LDR x3, =_tx_thread_system_stack_ptr // Pickup address of system stack + MRS x1, MPIDR_EL1 // Pickup the core ID + UBFX x1, x1, #0, #8 // Isolate and right justify core ID + LDR x4, [x3, x1, LSL #3] // Pickup system stack pointer + MOV sp, x4 // Setup system stack pointer + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + STP x29, x30, [sp, #-16]! // Save x29, x30 + BL _tx_execution_isr_enter // Call the ISR enter function + LDP x29, x30, [sp], #16 // Recover x29, x30 +#endif + + RET // Return to caller + + /* } + else + { */ + +__tx_thread_idle_system_save: + + /* Interrupt occurred in the scheduling loop. */ + + /* Not much to do here, just adjust the stack pointer, and return to IRQ + processing. */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + STP x29, x30, [sp, #-16]! // Save x29, x30 + BL _tx_execution_isr_enter // Call the ISR enter function + LDP x29, x30, [sp], #16 // Recover x29, x30 +#endif + + ADD sp, sp, #48 // Recover saved registers + RET // Continue IRQ processing + + /* } +} */ + + diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_thread_fp_disable.c b/ports_smp/cortex_a5x_smp/green/src/tx_thread_fp_disable.c new file mode 100644 index 00000000..b616ee89 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/src/tx_thread_fp_disable.c @@ -0,0 +1,95 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fp_disable Cortex-A5x-SMP/GHS */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function disables the FP for the currently executing thread. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_fp_disable(VOID) +{ + +TX_THREAD *thread_ptr; +ULONG system_state; + + + /* Pickup the current thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr); + + /* Get the system state. */ + system_state = TX_THREAD_GET_SYSTEM_STATE(); + + /* Make sure it is not NULL. */ + if (thread_ptr != TX_NULL) + { + + /* Thread is running... make sure the call is from the thread context. */ + if (system_state == 0) + { + + /* Yes, now set the FP enable flag to false in the TX_THREAD structure. */ + thread_ptr -> tx_thread_fp_enable = TX_FALSE; + } + } +} + diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_thread_fp_enable.c b/ports_smp/cortex_a5x_smp/green/src/tx_thread_fp_enable.c new file mode 100644 index 00000000..c43d6f16 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/src/tx_thread_fp_enable.c @@ -0,0 +1,95 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fp_enable Cortex-A5x-SMP/GHS */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function enabled the FP for the currently executing thread. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_fp_enable(VOID) +{ + +TX_THREAD *thread_ptr; +ULONG system_state; + + + /* Pickup the current thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr); + + /* Get the system state. */ + system_state = TX_THREAD_GET_SYSTEM_STATE(); + + /* Make sure it is not NULL. */ + if (thread_ptr != TX_NULL) + { + + /* Thread is running... make sure the call is from the thread context. */ + if (system_state == 0) + { + + /* Yes, now setup the FP enable flag in the TX_THREAD structure. */ + thread_ptr -> tx_thread_fp_enable = TX_TRUE; + } + } +} + diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_thread_interrupt_control.a64 b/ports_smp/cortex_a5x_smp/green/src/tx_thread_interrupt_control.a64 new file mode 100644 index 00000000..0fddefee --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/src/tx_thread_interrupt_control.a64 @@ -0,0 +1,89 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/*#define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control Cortex-A5x-SMP/GHS */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_control(UINT new_posture) +{ */ + .global _tx_thread_interrupt_control + .type _tx_thread_interrupt_control, @function +_tx_thread_interrupt_control: + + /* Pickup current interrupt lockout posture. */ + + MRS x1, DAIF // Pickup current interrupt posture + + /* Apply the new interrupt posture. */ + + MSR DAIF, x0 // Set new interrupt posture + MOV x0, x1 // Setup return value + RET // Return to caller +/* } */ + diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_thread_interrupt_disable.a64 b/ports_smp/cortex_a5x_smp/green/src/tx_thread_interrupt_disable.a64 new file mode 100644 index 00000000..901a42fb --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/src/tx_thread_interrupt_disable.a64 @@ -0,0 +1,87 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_disable Cortex-A5x-SMP/GHS */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for disabling interrupts */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_disable(void) +{ */ + .global _tx_thread_interrupt_disable + .type _tx_thread_interrupt_disable, @function +_tx_thread_interrupt_disable: + + /* Pickup current interrupt lockout posture. */ + + MRS x0, DAIF // Pickup current interrupt lockout posture + + /* Mask interrupts. */ + + MSR DAIFSet, 0x3 // Lockout interrupts + RET // Return to caller +/* } */ + diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_thread_interrupt_restore.a64 b/ports_smp/cortex_a5x_smp/green/src/tx_thread_interrupt_restore.a64 new file mode 100644 index 00000000..3cef4383 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/src/tx_thread_interrupt_restore.a64 @@ -0,0 +1,85 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_restore Cortex-A5x-SMP/GHS */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for restoring interrupts to the state */ +/* returned by a previous _tx_thread_interrupt_disable call. */ +/* */ +/* INPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_restore(UINT old_posture) +{ */ + .global _tx_thread_interrupt_restore + .type _tx_thread_interrupt_restore, @function +_tx_thread_interrupt_restore: + + /* Restore the old interrupt posture. */ + + MSR DAIF, x0 // Setup the old posture + RET // Return to caller + +/* } */ + diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_thread_schedule.a64 b/ports_smp/cortex_a5x_smp/green/src/tx_thread_schedule.a64 new file mode 100644 index 00000000..d70c8696 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/src/tx_thread_schedule.a64 @@ -0,0 +1,254 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + +/* .set ENABLE_ARM_FP,1 */ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule Cortex-A5x-SMP/GHS */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* _tx_thread_context_restore Restore thread's context */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_schedule(VOID) +{ */ + .global _tx_thread_schedule + .type _tx_thread_schedule, @function +_tx_thread_schedule: + + /* Enable interrupts. */ + + MSR DAIFClr, 0x3 // Enable interrupts + + /* Pickup the CPU ID. */ + + MRS x20, MPIDR_EL1 // Pickup the core ID + UBFX x20, x20, #0, #8 // Isolate and right justify core ID + + /* Wait for a thread to execute. */ + /* do + { */ + + LDR x1, =_tx_thread_execute_ptr // Address of thread execute ptr + +#ifdef TX_ENABLE_WFI +__tx_thread_schedule_loop: + MSR DAIFSet, 0x3 // Lockout interrupts + LDR x0, [x1, x20, LSL #3] // Pickup next thread to execute + CMP x0, #0 // Is it NULL? + B.NE _tx_thread_schedule_thread // + MSR DAIFClr, 0x3 // Enable interrupts + WFI // + B __tx_thread_schedule_loop // Keep looking for a thread +_tx_thread_schedule_thread: +#else + MSR DAIFSet, 0x3 // Lockout interrupts + LDR x0, [x1, x20, LSL #3] // Pickup next thread to execute + CMP x0, #0 // Is it NULL? + B.EQ _tx_thread_schedule // Keep looking for a thread +#endif + + /* } + while(_tx_thread_execute_ptr == TX_NULL); */ + + /* Now make sure the thread's ready bit is set. */ + + MOV x3, #0 // Build clear value + LDR w2, [x0, #260] // Pickup the ready bit + CMP w2, #1 // Is it set? + B.NE _tx_thread_schedule // If not, restart the scheduling loop + STR w3, [x0, #260] // Clear the ready bit + DMB ISH // + + /* Yes! We have a thread to execute. Lockout interrupts and + transfer control to it. */ + + /* Setup the current thread pointer. */ + /* _tx_thread_current_ptr = _tx_thread_execute_ptr; */ + + LDR x1, =_tx_thread_current_ptr // Pickup address of current thread + STR x0, [x1, x20, LSL #3] // Setup current thread pointer + + /* Increment the run count for this thread. */ + /* _tx_thread_current_ptr -> tx_thread_run_count++; */ + + LDR w2, [x0, #4] // Pickup run counter + LDR w3, [x0, #36] // Pickup time-slice for this thread + ADD w2, w2, #1 // Increment thread run-counter + STR w2, [x0, #4] // Store the new run counter + + /* Setup time-slice, if present. */ + /* _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; */ + + LDR x2, =_tx_timer_time_slice // Pickup address of time slice + // variable + LDR x4, [x0, #8] // Switch stack pointers + MOV sp, x4 // + STR w3, [x2, x20, LSL #2] // Setup time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread entry function to indicate the thread is executing. */ + + MOV x19, x0 // Save x0 + BL _tx_execution_thread_enter // Call the thread execution enter function + MOV x0, x19 // Restore x0 +#endif + + /* Switch to the thread's stack. */ + /* sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; */ + + /* Determine if an interrupt frame or a synchronous task suspension frame + is present. */ + + LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL1 + CMP x5, #0 // Check for synchronous context switch (ELR_EL1 = NULL) + B.EQ _tx_solicited_return +#ifdef EL1 + MSR SPSR_EL1, x4 // Setup SPSR for return + MSR ELR_EL1, x5 // Setup point of interrupt +#else +#ifdef EL2 + MSR SPSR_EL2, x4 // Setup SPSR for return + MSR ELR_EL2, x5 // Setup point of interrupt +#else + MSR SPSR_EL3, x4 // Setup SPSR for return + MSR ELR_EL3, x5 // Setup point of interrupt +#endif +#endif +#ifdef ENABLE_ARM_FP + LDR w1, [x0, #268] // Pickup FP enable flag + CMP w1, #0 // Is FP enabled? + B.EQ _skip_interrupt_fp_restore // No, skip FP restore + LDP x0, x1, [sp], #16 // Pickup FPSR, FPCR + MSR FPSR, x0 // Recover FPSR + MSR FPCR, x1 // Recover FPCR + LDP q30, q31, [sp], #32 // Recover q30, q31 + LDP q28, q29, [sp], #32 // Recover q28, q29 + LDP q26, q27, [sp], #32 // Recover q26, q27 + LDP q24, q25, [sp], #32 // Recover q24, q25 + LDP q22, q23, [sp], #32 // Recover q22, q23 + LDP q20, q21, [sp], #32 // Recover q20, q21 + LDP q18, q19, [sp], #32 // Recover q18, q19 + LDP q16, q17, [sp], #32 // Recover q16, q17 + LDP q14, q15, [sp], #32 // Recover q14, q15 + LDP q12, q13, [sp], #32 // Recover q12, q13 + LDP q10, q11, [sp], #32 // Recover q10, q11 + LDP q8, q9, [sp], #32 // Recover q8, q9 + LDP q6, q7, [sp], #32 // Recover q6, q7 + LDP q4, q5, [sp], #32 // Recover q4, q5 + LDP q2, q3, [sp], #32 // Recover q2, q3 + LDP q0, q1, [sp], #32 // Recover q0, q1 +_skip_interrupt_fp_restore: +#endif + LDP x28, x29, [sp], #16 // Recover x28 + LDP x26, x27, [sp], #16 // Recover x26, x27 + LDP x24, x25, [sp], #16 // Recover x24, x25 + LDP x22, x23, [sp], #16 // Recover x22, x23 + LDP x20, x21, [sp], #16 // Recover x20, x21 + LDP x18, x19, [sp], #16 // Recover x18, x19 + LDP x16, x17, [sp], #16 // Recover x16, x17 + LDP x14, x15, [sp], #16 // Recover x14, x15 + LDP x12, x13, [sp], #16 // Recover x12, x13 + LDP x10, x11, [sp], #16 // Recover x10, x11 + LDP x8, x9, [sp], #16 // Recover x8, x9 + LDP x6, x7, [sp], #16 // Recover x6, x7 + LDP x4, x5, [sp], #16 // Recover x4, x5 + LDP x2, x3, [sp], #16 // Recover x2, x3 + LDP x0, x1, [sp], #16 // Recover x0, x1 + LDP x29, x30, [sp], #16 // Recover x29, x30 + ERET // Return to point of interrupt + +_tx_solicited_return: + +#ifdef ENABLE_ARM_FP + LDR w1, [x0, #268] // Pickup FP enable flag + CMP w1, #0 // Is FP enabled? + B.EQ _skip_solicited_fp_restore // No, skip FP restore + LDP x0, x1, [sp], #16 // Pickup FPSR, FPCR + MSR FPSR, x0 // Recover FPSR + MSR FPCR, x1 // Recover FPCR + LDP q14, q15, [sp], #32 // Recover q14, q15 + LDP q12, q13, [sp], #32 // Recover q12, q13 + LDP q10, q11, [sp], #32 // Recover q10, q11 + LDP q8, q9, [sp], #32 // Recover q8, q9 +_skip_solicited_fp_restore: +#endif + LDP x27, x28, [sp], #16 // Recover x27, x28 + LDP x25, x26, [sp], #16 // Recover x25, x26 + LDP x23, x24, [sp], #16 // Recover x23, x24 + LDP x21, x22, [sp], #16 // Recover x21, x22 + LDP x19, x20, [sp], #16 // Recover x19, x20 + LDP x29, x30, [sp], #16 // Recover x29, x30 + MSR DAIF, x4 // Recover DAIF + RET // Return to caller +/* } */ + + diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_core_get.a64 b/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_core_get.a64 new file mode 100644 index 00000000..22bc8902 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_core_get.a64 @@ -0,0 +1,83 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_core_get Cortex-A5x-SMP/GHS */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets the currently running core number and returns it.*/ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* Core ID */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Source */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_core_get + .type _tx_thread_smp_core_get, @function +_tx_thread_smp_core_get: + MRS x0, MPIDR_EL1 // Pickup the core ID + UBFX x0, x0, #0, #8 // Isolate and right justify core ID + RET + + diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_core_preempt.a64 b/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_core_preempt.a64 new file mode 100644 index 00000000..9b51cd7c --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_core_preempt.a64 @@ -0,0 +1,90 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_core_preempt Cortex-A5x-SMP/GHS */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function preempts the specified core in situations where the */ +/* thread corresponding to this core is no longer ready or when the */ +/* core must be used for a higher-priority thread. If the specified is */ +/* the current core, this processing is skipped since the will give up */ +/* control subsequently on its own. */ +/* */ +/* INPUT */ +/* */ +/* core The core to preempt */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Source */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_core_preempt + .type _tx_thread_smp_core_preempt, @function +_tx_thread_smp_core_preempt: + DSB ISH + MRS x1, S3_1_C15_C3_0 // read CBAR + LDR x2, =0x10F00 // Build address of GICD_BASE+GICD_SGIR + ADD x1, x1, x2 + MOV x2, #0x10000 // Software Interrupt 0 + LSL x2, x2, x0 // Shift by the core ID + STR x2, [x1, #0] // Issue inter-core interrupt + RET + diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_current_state_get.a64 b/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_current_state_get.a64 new file mode 100644 index 00000000..ca10ecd4 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_current_state_get.a64 @@ -0,0 +1,89 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_current_state_get Cortex-A5x-SMP/GHS */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is gets the current state of the calling core. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_current_state_get + .type _tx_thread_smp_current_state_get, @function +_tx_thread_smp_current_state_get: + + MRS x1, DAIF // Pickup current interrupt posture + MSR DAIFSet, 0x3 // Lockout interrupts + MRS x2, MPIDR_EL1 // Pickup the core ID + UBFX x2, x2, #0, #8 // Isolate and right justify core ID + LDR x3, =_tx_thread_system_state // Pickup the base of the current system state array + LDR w0, [x3, x2, LSL #2] // Pickup the current system state for this core + MSR DAIF, x1 // Restore interrupt posture + RET + + diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_current_thread_get.a64 b/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_current_thread_get.a64 new file mode 100644 index 00000000..ed5f7c62 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_current_thread_get.a64 @@ -0,0 +1,88 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_current_thread_get Cortex-A5x-SMP/GHS */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is gets the current thread of the calling core. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_current_thread_get + .type _tx_thread_smp_current_thread_get, @function +_tx_thread_smp_current_thread_get: + + MRS x1, DAIF // Pickup current interrupt posture + MSR DAIFSet, 0x3 // Lockout interrupts + MRS x2, MPIDR_EL1 // Pickup the core ID + UBFX x2, x2, #0, #8 // Isolate and right justify core ID + LDR x3, =_tx_thread_current_ptr // Pickup the base of the current thread pointer array + LDR x0, [x3, x2, LSL #3] // Pickup the current thread pointer for this core + MSR DAIF, x1 // Restore interrupt posture + RET + diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_initialize_wait.a64 b/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_initialize_wait.a64 new file mode 100644 index 00000000..af3a0b70 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_initialize_wait.a64 @@ -0,0 +1,137 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_initialize_wait Cortex-A5x-SMP/GHS */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is the place where additional cores wait until */ +/* initialization is complete before they enter the thread scheduling */ +/* loop. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* Hardware */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_initialize_wait + .type _tx_thread_smp_initialize_wait, @function +_tx_thread_smp_initialize_wait: + + /* Lockout interrupts. */ + + MSR DAIFSet, 0x3 // Lockout interrupts + + /* Pickup the Core ID. */ + + MRS x2, MPIDR_EL1 // Pickup the core ID + UBFX x2, x2, #0, #8 // Isolate and right justify core ID + + /* Make sure the system state for this core is TX_INITIALIZE_IN_PROGRESS before we check the release + flag. */ + + LDR w1, =0xF0F0F0F0 // Build TX_INITIALIZE_IN_PROGRESS flag + LDR x3, =_tx_thread_system_state // Pickup the base of the current system state array +wait_for_initialize: + LDR w0, [x3, x2, LSL #2] // Pickup the current system state for this core + CMP w0, w1 // Make sure the TX_INITIALIZE_IN_PROGRESS flag is set + B.NE wait_for_initialize // Not equal, just spin here + + /* Save the system stack pointer for this core. */ + + LDR x0, =_tx_thread_system_stack_ptr // Pickup address of system stack ptr + MOV x1, sp // Pickup SP + SUB x1, x1, #15 // + AND x1, x1, #~0xF // Get 16-bit alignment + STR x1, [x0, x2, LSL #3] // Store system stack pointer + + + /* Pickup the release cores flag. */ + + LDR x4, =_tx_thread_smp_release_cores_flag // Build address of release cores flag +wait_for_release: + LDR w0, [x4, #0] // Pickup the flag + CMP w0, #0 // Is it set? + B.EQ wait_for_release // Wait for the flag to be set + + /* Core 0 has released this core. */ + + /* Clear this core's system state variable. */ + + MOV x0, #0 // Build clear value + STR w0, [x3, x2, LSL #2] // Set the current system state for this core to zero + + /* Now wait for core 0 to finish it's initialization. */ + +core_0_wait_loop: + LDR w0, [x3, #0] // Pickup the current system state for core 0 + CMP w0, #0 // Is it 0? + B.NE core_0_wait_loop // No, keep waiting for core 0 to finish its initialization + + /* Initialization is complete, enter the scheduling loop! */ + + B _tx_thread_schedule // Enter the scheduling loop for this core + + RET + diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_low_level_initialize.a64 b/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_low_level_initialize.a64 new file mode 100644 index 00000000..b4ec8a91 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_low_level_initialize.a64 @@ -0,0 +1,80 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_low_level_initialize Cortex-A5x-SMP/GHS */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function performs low-level initialization of the booting */ +/* core. */ +/* */ +/* INPUT */ +/* */ +/* number_of_cores Number of cores */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_high_level ThreadX high-level init */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_low_level_initialize + .type _tx_thread_smp_low_level_initialize, @function +_tx_thread_smp_low_level_initialize: + + RET diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_protect.a64 b/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_protect.a64 new file mode 100644 index 00000000..5185eac4 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_protect.a64 @@ -0,0 +1,122 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_protect Cortex-A5x-SMP/GHS */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets protection for running inside the ThreadX */ +/* source. This is acomplished by a combination of a test-and-set */ +/* flag and periodically disabling interrupts. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* Previous Status Register */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Source */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_protect + .type _tx_thread_smp_protect, @function +_tx_thread_smp_protect: + + MRS x0, DAIF // Pickup current interrupt posture + MSR DAIFSet, 0x3 // Lockout interrupts + + /* Pickup the CPU ID. */ + + MRS x2, MPIDR_EL1 // Pickup the core ID + UBFX x2, x2, #0, #8 // Isolate and right justify core ID + + LDR x1, =_tx_thread_smp_protection // Build address to protection structure + LDR w3, [x1, #4] // Pickup the owning core + CMP w3, w2 // Is it this core? + B.EQ _owned // Yes, the protection is already owned + + LDAXR w4, [x1, #0] // Pickup the protection flag + CBZ w4, _get_protection // Yes, get the protection + MSR DAIF, x0 // Restore interrupts + ISB // +#ifdef TX_ENABLE_WFE + WFE // Go into standby +#endif + B _tx_thread_smp_protect // On waking, restart the protection attempt + +_get_protection: + MOV x4, #1 // Build lock value + STXR w5, w4, [x1] // Attempt to get the protection + CBZ w5, _got_protection // Did it succeed? w5 = 0 means success! + MSR DAIF, x0 // Restore interrupts + B _tx_thread_smp_protect // Restart the protection attempt + +_got_protection: + DMB ISH // + STR w2, [x1, #4] // Save owning core +_owned: + LDR w5, [x1, #8] // Pickup ownership count + ADD w5, w5, #1 // Increment ownership count + STR w5, [x1, #8] // Store ownership count + DMB ISH // + RET + + + diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_time_get.a64 b/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_time_get.a64 new file mode 100644 index 00000000..d4d77a7d --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_time_get.a64 @@ -0,0 +1,83 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_time_get Cortex-A5x-SMP/GHS */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets the global time value that is used for debug */ +/* information and event tracing. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* 32-bit time stamp */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Source */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_time_get + .type _tx_thread_smp_time_get, @function +_tx_thread_smp_time_get: + MOV x0, #0 // Add time source - application specific + RET + + diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_unprotect.a64 b/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_unprotect.a64 new file mode 100644 index 00000000..792250f6 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/src/tx_thread_smp_unprotect.a64 @@ -0,0 +1,115 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_unprotect Cortex-A5x-SMP/GHS */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function releases previously obtained protection. The supplied */ +/* previous SR is restored. If the value of _tx_thread_system_state */ +/* and _tx_thread_preempt_disable are both zero, then multithreading */ +/* is enabled as well. */ +/* */ +/* INPUT */ +/* */ +/* Previous Status Register */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Source */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_unprotect + .type _tx_thread_smp_unprotect, @function +_tx_thread_smp_unprotect: + MSR DAIFSet, 0x3 // Lockout interrupts + LDR x1,=_tx_thread_smp_protection // Build address of protection structure + MRS x8, MPIDR_EL1 // Pickup the core ID + UBFX x8, x8, #0, #8 // Isolate and right justify core ID + LDR w2, [x1, #4] // Pickup the owning core + CMP w2, w8 // Is it this core? + B.NE _still_protected // If this is not the owning core, protection is in force elsewhere + + LDR w2, [x1, #8] // Pickup the protection count + CMP w2, #0 // Check to see if the protection is still active + B.EQ _still_protected // If the protection count is zero, protection has already been cleared + + SUB w2, w2, #1 // Decrement the protection count + STR w2, [x1, #8] // Store the new count back + CMP w2, #0 // Check to see if the protection is still active + B.NE _still_protected // If the protection count is non-zero, protection is still in force + LDR x2,=_tx_thread_preempt_disable // Build address of preempt disable flag + LDR w3, [x2] // Pickup preempt disable flag + CMP w3, #0 // Is the preempt disable flag set? + B.NE _still_protected // Yes, skip the protection release + MOV x2, #0xFFFFFFFF // Build invalid value + STR w2, [x1, #4] // Mark the protected core as invalid + DMB ISH // Ensure that accesses to shared resource have completed + MOV x2, #0 // Build release protection value + STR w2, [x1, #0] // Release the protection + DSB ISH // To ensure update of the protection occurs before other CPUs awake +#ifdef TX_ENABLE_WFE + SEV // Send event to other CPUs, wakes anyone waiting on the protection (using WFE) +#endif +_still_protected: + SEV // Send event to other CPUs + MSR DAIF, x0 // Restore interrupt posture + RET + diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_thread_stack_build.a64 b/ports_smp/cortex_a5x_smp/green/src/tx_thread_stack_build.a64 new file mode 100644 index 00000000..87b22903 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/src/tx_thread_stack_build.a64 @@ -0,0 +1,172 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build Cortex-A5x-SMP/GHS */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +{ */ + .global _tx_thread_stack_build + .type _tx_thread_stack_build, @function +_tx_thread_stack_build: + + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-A5x should look like the following after it is built: + + Stack Top: SSPR Initial SSPR + ELR Point of interrupt + x28 Initial value for x28 + not used Not used + x26 Initial value for x26 + x27 Initial value for x27 + x24 Initial value for x24 + x25 Initial value for x25 + x22 Initial value for x22 + x23 Initial value for x23 + x20 Initial value for x20 + x21 Initial value for x21 + x18 Initial value for x18 + x19 Initial value for x19 + x16 Initial value for x16 + x17 Initial value for x17 + x14 Initial value for x14 + x15 Initial value for x15 + x12 Initial value for x12 + x13 Initial value for x13 + x10 Initial value for x10 + x11 Initial value for x11 + x8 Initial value for x8 + x9 Initial value for x9 + x6 Initial value for x6 + x7 Initial value for x7 + x4 Initial value for x4 + x5 Initial value for x5 + x2 Initial value for x2 + x3 Initial value for x3 + x0 Initial value for x0 + x1 Initial value for x1 + x29 Initial value for x29 (frame pointer) + x30 Initial value for x30 (link register) + 0 For stack backtracing + + Stack Bottom: (higher memory address) */ + + LDR x4, [x0, #24] // Pickup end of stack area + AND x4, x4, #~0xF // Ensure 16-byte alignment + + /* Actually build the stack frame. */ + + MOV x2, #0 // Build clear value + MOV x3, #0 // + + STP x2, x3, [x4, #-16]! // Set backtrace to 0 + STP x2, x3, [x4, #-16]! // Set initial x29, x30 + STP x2, x3, [x4, #-16]! // Set initial x0, x1 + STP x2, x3, [x4, #-16]! // Set initial x2, x3 + STP x2, x3, [x4, #-16]! // Set initial x4, x5 + STP x2, x3, [x4, #-16]! // Set initial x6, x7 + STP x2, x3, [x4, #-16]! // Set initial x8, x9 + STP x2, x3, [x4, #-16]! // Set initial x10, x11 + STP x2, x3, [x4, #-16]! // Set initial x12, x13 + STP x2, x3, [x4, #-16]! // Set initial x14, x15 + STP x2, x3, [x4, #-16]! // Set initial x16, x17 + STP x2, x3, [x4, #-16]! // Set initial x18, x19 + STP x2, x3, [x4, #-16]! // Set initial x20, x21 + STP x2, x3, [x4, #-16]! // Set initial x22, x23 + STP x2, x3, [x4, #-16]! // Set initial x24, x25 + STP x2, x3, [x4, #-16]! // Set initial x26, x27 + STP x2, x3, [x4, #-16]! // Set initial x28 +#ifdef EL1 + MOV x2, #0x5 // Build initial SPSR (EL1) +#else +#ifdef EL2 + MOV x2, #0x9 // Build initial SPSR (EL2) +#else + MOV x2, #0xD // Build initial SPSR (EL3) +#endif +#endif + MOV x3, x1 // Build initial ELR + STP x2, x3, [x4, #-16]! // Set initial SPSR & ELR + + /* Setup stack pointer. */ + /* thread_ptr -> tx_thread_stack_ptr = x2; */ + + STR x4, [x0, #8] // Save stack pointer in thread's + MOV x3, #1 // Build ready flag + STR w3, [x0, #260] // Set ready flag + RET // Return to caller + +/* } */ + + diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_thread_system_return.a64 b/ports_smp/cortex_a5x_smp/green/src/tx_thread_system_return.a64 new file mode 100644 index 00000000..6e908080 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/src/tx_thread_system_return.a64 @@ -0,0 +1,187 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + +/* .set ENABLE_ARM_FP,1 */ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return Cortex-A5x-SMP/GHS */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the ThreadX system. Only a */ +/* minimal context is saved since the compiler assumes temp registers */ +/* are going to get slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_system_return(VOID) +{ */ + .global _tx_thread_system_return + .type _tx_thread_system_return, @function +_tx_thread_system_return: +; +; /* Save minimal context on the stack. */ +; + MRS x0, DAIF // Pickup DAIF + MSR DAIFSet, 0x3 // Lockout interrupts + STP x29, x30, [sp, #-16]! // Save x29 (frame pointer), x30 (link register) + STP x19, x20, [sp, #-16]! // Save x19, x20 + STP x21, x22, [sp, #-16]! // Save x21, x22 + STP x23, x24, [sp, #-16]! // Save x23, x24 + STP x25, x26, [sp, #-16]! // Save x25, x26 + STP x27, x28, [sp, #-16]! // Save x27, x28 + MRS x8, MPIDR_EL1 // Pickup the core ID + UBFX x8, x8, #0, #8 // Isolate and right justify core ID + LDR x5, =_tx_thread_current_ptr // Pickup address of current ptr + LDR x6, [x5, x8, LSL #3] // Pickup current thread pointer + +#ifdef ENABLE_ARM_FP + LDR w7, [x6, #268] // Pickup FP enable flag + CMP w7, #0 // Is FP enabled? + B.EQ _skip_fp_save // No, skip FP save + STP q8, q9, [sp, #-32]! // Save q8, q9 + STP q10, q11, [sp, #-32]! // Save q10, q11 + STP q12, q13, [sp, #-32]! // Save q12, q13 + STP q14, q15, [sp, #-32]! // Save q14, q15 + MRS x2, FPSR // Pickup FPSR + MRS x3, FPCR // Pickup FPCR + STP x2, x3, [sp, #-16]! // Save FPSR, FPCR +_skip_fp_save: +#endif + + MOV x1, #0 // Clear x1 + STP x0, x1, [sp, #-16]! // Save DAIF and clear value for ELR_EK1 + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread exit function to indicate the thread is no longer executing. */ + + MOV x19, x5 // Save x5 + MOV x20, x6 // Save x6 + MOV x21, x8 // Save x2 + BL _tx_execution_thread_exit // Call the thread exit function + MOV x8, x21 // Restore x2 + MOV x5, x19 // Restore x5 + MOV x6, x20 // Restore x6 +#endif + + LDR x2, =_tx_timer_time_slice // Pickup address of time slice + LDR w1, [x2, x8, LSL #2] // Pickup current time slice + + /* Save current stack and switch to system stack. */ + /* _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; */ + /* sp = _tx_thread_system_stack_ptr[core]; */ + + MOV x4, sp // + STR x4, [x6, #8] // Save thread stack pointer + LDR x3, =_tx_thread_system_stack_ptr // Pickup address of system stack + LDR x4, [x3, x8, LSL #3] // Pickup system stack pointer + MOV sp, x4 // Setup system stack pointer + + /* Determine if the time-slice is active. */ + /* if (_tx_timer_time_slice[core]) + { */ + + MOV x4, #0 // Build clear value + CMP w1, #0 // Is a time-slice active? + B.EQ __tx_thread_dont_save_ts // No, don't save the time-slice + + /* Save the current remaining time-slice. */ + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + STR w4, [x2, x8, LSL #2] // Clear time-slice + STR w1, [x6, #36] // Store current time-slice + + /* } */ +__tx_thread_dont_save_ts: + + /* Clear the current thread pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + STR x4, [x5, x8, LSL #3] // Clear current thread pointer + + /* Set ready bit in thread control block. */ + + MOV x3, #1 // Build ready value + STR w3, [x6, #260] // Make the thread ready + DMB ISH // + + /* Now clear protection. It is assumed that protection is in force whenever this routine is called. */ + + LDR x3, =_tx_thread_smp_protection // Pickup address of protection structure + LDR x1, =_tx_thread_preempt_disable // Build address to preempt disable flag + STR w4, [x1, #0] // Clear preempt disable flag + STR w4, [x3, #8] // Cear protection count + MOV x1, #0xFFFFFFFF // Build invalid value + STR w1, [x3, #4] // Set core to an invalid value + DMB ISH // Ensure that accesses to shared resource have completed + STR w4, [x3, #0] // Clear protection + DSB ISH // To ensure update of the shared resource occurs before other CPUs awake + SEV // Send event to other CPUs, wakes anyone waiting on a mutex (using WFE) + B _tx_thread_schedule // Jump to scheduler! + +/* } */ + + diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_thread_timeout.c b/ports_smp/cortex_a5x_smp/green/src/tx_thread_timeout.c new file mode 100644 index 00000000..6b896c4c --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/src/tx_thread_timeout.c @@ -0,0 +1,165 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_timeout Cortex-A5x-SMP */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles thread timeout processing. Timeouts occur in */ +/* two flavors, namely the thread sleep timeout and all other service */ +/* call timeouts. Thread sleep timeouts are processed locally, while */ +/* the others are processed by the appropriate suspension clean-up */ +/* service. */ +/* */ +/* INPUT */ +/* */ +/* timeout_input Contains the thread pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* Suspension Cleanup Functions */ +/* _tx_thread_system_resume Resume thread */ +/* _tx_thread_system_ni_resume Non-interruptable resume thread */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_timer_expiration_process Timer expiration function */ +/* _tx_timer_thread_entry Timer thread function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_timeout(ULONG timeout_input) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_THREAD *thread_ptr; +VOID (*suspend_cleanup)(struct TX_THREAD_STRUCT *suspend_thread_ptr, ULONG suspension_sequence); +ULONG suspension_sequence; + + + /* Pickup the thread pointer. */ + TX_THREAD_TIMEOUT_POINTER_SETUP(thread_ptr) + + /* Disable interrupts. */ + TX_DISABLE + + /* Determine how the thread is currently suspended. */ + if (thread_ptr -> tx_thread_state == TX_SLEEP) + { + +#ifdef TX_NOT_INTERRUPTABLE + + /* Resume the thread! */ + _tx_thread_system_ni_resume(thread_ptr); + + /* Restore interrupts. */ + TX_RESTORE +#else + + /* Increment the disable preemption flag. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Lift the suspension on the sleeping thread. */ + _tx_thread_system_resume(thread_ptr); +#endif + } + else + { + + /* Process all other suspension timeouts. */ + +#ifdef TX_THREAD_ENABLE_PERFORMANCE_INFO + + /* Increment the total number of thread timeouts. */ + _tx_thread_performance_timeout_count++; + + /* Increment the number of timeouts for this thread. */ + thread_ptr -> tx_thread_performance_timeout_count++; +#endif + + /* Pickup the cleanup routine address. */ + suspend_cleanup = thread_ptr -> tx_thread_suspend_cleanup; + +#ifndef TX_NOT_INTERRUPTABLE + + /* Pickup the suspension sequence number that is used later to verify that the + cleanup is still necessary. */ + suspension_sequence = thread_ptr -> tx_thread_suspension_sequence; +#else + + /* When not interruptable is selected, the suspension sequence is not used - just set to 0. */ + suspension_sequence = ((ULONG) 0); +#endif + +#ifndef TX_NOT_INTERRUPTABLE + + /* Restore interrupts. */ + TX_RESTORE +#endif + + /* Call any cleanup routines. */ + if (suspend_cleanup != TX_NULL) + { + + /* Yes, there is a function to call. */ + (suspend_cleanup)(thread_ptr, suspension_sequence); + } + +#ifdef TX_NOT_INTERRUPTABLE + + /* Restore interrupts. */ + TX_RESTORE +#endif + } +} + diff --git a/ports_smp/cortex_a5x_smp/green/src/tx_timer_interrupt.a64 b/ports_smp/cortex_a5x_smp/green/src/tx_timer_interrupt.a64 new file mode 100644 index 00000000..abed1ed9 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/src/tx_timer_interrupt.a64 @@ -0,0 +1,193 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_timer.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt Cortex-A5x-SMP/GHS */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_timer_interrupt(VOID) +{ */ + .global _tx_timer_interrupt + .type _tx_timer_interrupt, @function +_tx_timer_interrupt: + + MRS x2, MPIDR_EL1 // Pickup the core ID + UBFX x2, x2, #0, #8 // Isolate and right justify core ID + CMP x2, #0 // Is this core 0? + B.EQ __tx_process_timer // If desired core, continue processing + RET // Simply return if different core +__tx_process_timer: + + /* Upon entry to this routine, it is assumed that context save has already + been called, and therefore the compiler scratch registers are available + for use. */ + + STP x27, x28, [sp, #-16]! // Save x27, x28 + STP x29, x30, [sp, #-16]! // Save x29 (frame pointer), x30 (link register) + + /* Get inter-core protection. */ + + BL _tx_thread_smp_protect // Get inter-core protection + MOV x28, x0 // Save the return value in preserved register + + /* Increment the system clock. */ + /* _tx_timer_system_clock++; */ + + LDR x1, =_tx_timer_system_clock // Pickup address of system clock + LDR w0, [x1, #0] // Pickup system clock + ADD w0, w0, #1 // Increment system clock + STR w0, [x1, #0] // Store new system clock + + /* Test for timer expiration. */ + /* if (*_tx_timer_current_ptr) + { */ + + LDR x1, =_tx_timer_current_ptr // Pickup current timer pointer addr + LDR x0, [x1, #0] // Pickup current timer + LDR x2, [x0, #0] // Pickup timer list entry + CMP x2, #0 // Is there anything in the list? + B.EQ __tx_timer_no_timer // No, just increment the timer + + /* Set expiration flag. */ + /* _tx_timer_expired = TX_TRUE; */ + + LDR x3, =_tx_timer_expired // Pickup expiration flag address + MOV w2, #1 // Build expired value + STR w2, [x3, #0] // Set expired flag + B __tx_timer_done // Finished timer processing + + /* } + else + { */ +__tx_timer_no_timer: + + /* No timer expired, increment the timer pointer. */ + /* _tx_timer_current_ptr++; */ + + ADD x0, x0, #8 // Move to next timer + + /* Check for wrap-around. */ + /* if (_tx_timer_current_ptr == _tx_timer_list_end) */ + + LDR x3, =_tx_timer_list_end // Pickup addr of timer list end + LDR x2, [x3, #0] // Pickup list end + CMP x0, x2 // Are we at list end? + B.NE __tx_timer_skip_wrap // No, skip wrap-around logic + + /* Wrap to beginning of list. */ + /* _tx_timer_current_ptr = _tx_timer_list_start; */ + + LDR x3, =_tx_timer_list_start // Pickup addr of timer list start + LDR x0, [x3, #0] // Set current pointer to list start + +__tx_timer_skip_wrap: + + STR x0, [x1, #0] // Store new current timer pointer + /* } */ + +__tx_timer_done: + + /* Did a timer expire? */ + /* if (_tx_timer_expired) + { */ + + LDR x1, =_tx_timer_expired // Pickup addr of expired flag + LDR w0, [x1, #0] // Pickup timer expired flag + CMP w0, #0 // Check for timer expiration + B.EQ __tx_timer_dont_activate // If not set, skip timer activation + + /* Process timer expiration. */ + /* _tx_timer_expiration_process(); */ + + BL _tx_timer_expiration_process // Call the timer expiration handling routine + + /* } */ +__tx_timer_dont_activate: + + /* Call time-slice processing. */ + /* _tx_thread_time_slice(); */ + BL _tx_thread_time_slice // Call time-slice processing + + + /* Release inter-core protection. */ + + MOV x0, x28 // Pass the previous status register back + BL _tx_thread_smp_unprotect // Release protection + + LDP x29, x30, [sp], #16 // Recover x29, x30 + LDP x27, x28, [sp], #16 // Recover x27, x28 + RET // Return to caller + +/* } */ + + diff --git a/ports_smp/cortex_a5x_smp/green/src/txr_ghs.c b/ports_smp/cortex_a5x_smp/green/src/txr_ghs.c new file mode 100644 index 00000000..51928e44 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/green/src/txr_ghs.c @@ -0,0 +1,88 @@ +/* + * ThreadX API Runtime Error Support + * + * Copyright 1983-2019 Green Hills Software LLC. + * + * This program is the property of Green Hills Software LLC., + * its contents are proprietary information and no part of it + * is to be disclosed to anyone except employees of Green Hills + * Software LLC., or as agreed in writing signed by the President + * of Green Hills Software LLC. + */ + +/* #include "tx_ghs.h" */ +#ifndef TX_DISABLE_ERROR_CHECKING +#define TX_DISABLE_ERROR_CHECKING +#endif +#include "tx_api.h" + +/* Customized ThreadX API runtime error support routine. */ + +void _rnerr(int num, int linenum, const char*str, void*ptr, ...); + +/* __ghs_rnerr() + This is the custom runtime error checking routine. + This implementation uses the existing __rnerr() routine. + Another implementation could use the .syscall mechanism, + provided MULTI was modified to understand that. + */ +void __ghs_rnerr(char *errMsg, int stackLevels, int stackTraceDisplay, void *hexVal) { + TX_INTERRUPT_SAVE_AREA + int num; + /* + Initialize the stack levels value. + + Add 3 to account for the calls to _rnerr, __rnerr, and + __ghs_rnerr. + + If the implementation changes, calls to __ghs_rnerr + will not need to be changed. + + Zero is not permitted, so substitute 3 in that case. + */ + num = (stackLevels+3) & 0xf; + if (!num) { + num = 3; + } + /* + Shift the stack levels value to bits 12..15 and + insert the stack trace display value in bit 11. + Bits 0..10 are unused. + */ + num = (num << 12) | (stackTraceDisplay ? 0x800 : 0); + + /* This will mask all interrupts in the RTEC code, which is probably + unacceptable for many targets. */ + TX_DISABLE + _rnerr(num, -1, (const char *)hexVal, (void *)errMsg); + TX_RESTORE +} + + +/* ThreadX thread stack checking runtime support routine. */ + +extern char __ghsbegin_stack[]; + +void __stkchk(void) { + int i; + TX_THREAD *current_thread_ptr; + + /* Pickup current thread pointer. */ + TX_THREAD_GET_CURRENT(current_thread_ptr) + + if(current_thread_ptr) + { + if((unsigned)(&i) <= + (unsigned)(current_thread_ptr -> tx_thread_stack_start)) + { + _rnerr(21, -1, 0, 0); + } + } + else + { + if((unsigned)(&i) <= (unsigned)__ghsbegin_stack) + { + _rnerr(21, -1, 0, 0); + } + } +} diff --git a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/tx_initialize_low_level.s b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/tx_initialize_low_level.s index 8f25e519..107673e5 100644 --- a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/tx_initialize_low_level.s +++ b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/tx_initialize_low_level.s @@ -47,7 +47,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level SMP/Cortex-A7/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -80,7 +80,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports_smp/cortex_a7_smp/ac5/inc/tx_port.h b/ports_smp/cortex_a7_smp/ac5/inc/tx_port.h index 8e39e642..57109ab0 100644 --- a/ports_smp/cortex_a7_smp/ac5/inc/tx_port.h +++ b/ports_smp/cortex_a7_smp/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h SMP/Cortex-A7/AC5 */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -394,7 +394,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Cortex-A7/AC5 Version 6.0.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Cortex-A7/AC5 Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a7_smp/ac5/readme_threadx.txt b/ports_smp/cortex_a7_smp/ac5/readme_threadx.txt index 9044e562..3dcb6dca 100644 --- a/ports_smp/cortex_a7_smp/ac5/readme_threadx.txt +++ b/ports_smp/cortex_a7_smp/ac5/readme_threadx.txt @@ -351,7 +351,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A7 using AC5 tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-A7 using AC5 tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_context_restore.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_context_restore.s index 1bdf5d08..425c1cdd 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_context_restore.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_context_restore.s @@ -69,7 +69,7 @@ SVC_MODE EQU 0x93 ; SVC mode ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore SMP/Cortex-A7/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -101,7 +101,7 @@ SVC_MODE EQU 0x93 ; SVC mode ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_context_save.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_context_save.s index 2b547164..7f9ffb23 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_context_save.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_context_save.s @@ -45,7 +45,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save SMP/Cortex-A7/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -76,7 +76,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_interrupt_control.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_interrupt_control.s index 9d3c59ef..8faa21ce 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_interrupt_control.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_interrupt_control.s @@ -42,7 +42,7 @@ INT_MASK EQU 0x80 ; Interrupt bit mask ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control SMP/Cortex-A7/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ INT_MASK EQU 0x80 ; Interrupt bit mask ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_interrupt_disable.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_interrupt_disable.s index cb1c194a..f0c76908 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_interrupt_disable.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_interrupt_disable.s @@ -35,7 +35,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_disable SMP/Cortex-A7/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -64,7 +64,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(void) diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_interrupt_restore.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_interrupt_restore.s index 6b0da839..42256a7a 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_interrupt_restore.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_interrupt_restore.s @@ -35,7 +35,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore SMP/Cortex-A7/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -65,7 +65,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_irq_nesting_end.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_irq_nesting_end.s index 9eae0030..2093cfa8 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_irq_nesting_end.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_irq_nesting_end.s @@ -45,7 +45,7 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_irq_nesting_end SMP/Cortex-A7/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -84,7 +84,7 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_irq_nesting_start.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_irq_nesting_start.s index 47b32481..e849d539 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_irq_nesting_start.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_irq_nesting_start.s @@ -41,7 +41,7 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_irq_nesting_start SMP/Cortex-A7/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_schedule.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_schedule.s index c7d3c22f..b75fab04 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_schedule.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_schedule.s @@ -46,7 +46,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule SMP/Cortex-A7/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -79,7 +79,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_core_get.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_core_get.s index ffb99329..23017905 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_core_get.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_core_get.s @@ -38,7 +38,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_smp_core_get SMP/Cortex-A7/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -67,7 +67,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_core_get diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_core_preempt.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_core_preempt.s index c5ec198e..b9f3dcd5 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_core_preempt.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_core_preempt.s @@ -40,7 +40,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_smp_core_preempt SMP/Cortex-A7/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -73,7 +73,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_core_preempt diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_current_state_get.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_current_state_get.s index 029e03de..c9ca1580 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_current_state_get.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_current_state_get.s @@ -40,7 +40,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_smp_current_state_get SMP/Cortex-A7/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -69,7 +69,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_current_state_get diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_current_thread_get.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_current_thread_get.s index 105b465a..3a38fc02 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_current_thread_get.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_current_thread_get.s @@ -40,7 +40,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_smp_current_thread_get SMP/Cortex-A7/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -69,7 +69,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_current_thread_get diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_initialize_wait.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_initialize_wait.s index fcd2a397..8d41f13f 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_initialize_wait.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_initialize_wait.s @@ -43,7 +43,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_smp_initialize_wait SMP/Cortex-A7/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -74,7 +74,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_initialize_wait diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_low_level_initialize.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_low_level_initialize.s index 482b6655..29821c1d 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_low_level_initialize.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_low_level_initialize.s @@ -38,7 +38,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_smp_low_level_initialize SMP/Cortex-A7/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -68,7 +68,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_low_level_initialize diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_protect.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_protect.s index 5f8ef018..095a3e94 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_protect.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_protect.s @@ -49,7 +49,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_smp_protect SMP/Cortex-A7/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -80,7 +80,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_protect diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_time_get.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_time_get.s index 356c0122..dd34d3c5 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_time_get.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_time_get.s @@ -39,7 +39,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_smp_time_get SMP/Cortex-A7/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -69,7 +69,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_time_get diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_unprotect.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_unprotect.s index f4ed864e..cec2da1b 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_unprotect.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_unprotect.s @@ -43,7 +43,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_smp_unprotect SMP/Cortex-A7/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -75,7 +75,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_unprotect diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_stack_build.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_stack_build.s index 54770103..5fdd520c 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_stack_build.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_stack_build.s @@ -47,7 +47,7 @@ THUMB_BIT EQU 0x20 ; Thumb-bit ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build SMP/Cortex-A7/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -79,7 +79,7 @@ THUMB_BIT EQU 0x20 ; Thumb-bit ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_system_return.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_system_return.s index edb35391..2c4f9cd7 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_system_return.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_system_return.s @@ -47,7 +47,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return SMP/Cortex-A7/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -79,7 +79,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_vectored_context_save.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_vectored_context_save.s index fe7866b8..4f57e834 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_vectored_context_save.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_vectored_context_save.s @@ -44,7 +44,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_vectored_context_save SMP/Cortex-A7/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -75,7 +75,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_timer_interrupt.s b/ports_smp/cortex_a7_smp/ac5/src/tx_timer_interrupt.s index 0aa02c78..bcdcdf7e 100644 --- a/ports_smp/cortex_a7_smp/ac5/src/tx_timer_interrupt.s +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_timer_interrupt.s @@ -55,7 +55,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt SMP/Cortex-A7/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -91,7 +91,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) diff --git a/ports_smp/cortex_a7_smp/gnu/example_build/tx_initialize_low_level.S b/ports_smp/cortex_a7_smp/gnu/example_build/tx_initialize_low_level.S index 9a4b9946..90cb521e 100644 --- a/ports_smp/cortex_a7_smp/gnu/example_build/tx_initialize_low_level.S +++ b/ports_smp/cortex_a7_smp/gnu/example_build/tx_initialize_low_level.S @@ -72,7 +72,7 @@ $_tx_initialize_low_level: @/* FUNCTION RELEASE */ @/* */ @/* _tx_initialize_low_level MPCore/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -105,7 +105,7 @@ $_tx_initialize_low_level: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) diff --git a/ports_smp/cortex_a7_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a7_smp/gnu/inc/tx_port.h index d5d527ec..2498cdd3 100644 --- a/ports_smp/cortex_a7_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a7_smp/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h SMP/Cortex-A7/GNU */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -392,7 +392,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Cortex-A7/GNU Version 6.0.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Cortex-A7/GNU Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a7_smp/gnu/readme_threadx.txt b/ports_smp/cortex_a7_smp/gnu/readme_threadx.txt index 4f421479..ad198141 100644 --- a/ports_smp/cortex_a7_smp/gnu/readme_threadx.txt +++ b/ports_smp/cortex_a7_smp/gnu/readme_threadx.txt @@ -333,7 +333,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A7 using GNU tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-A7 using GNU tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_context_restore.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_context_restore.S index 922132ee..6b270049 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_context_restore.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_context_restore.S @@ -73,7 +73,7 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_restore SMP/Cortex-A7/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -105,7 +105,7 @@ IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_restore(VOID) diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_context_save.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_context_save.S index df02a791..b68ea7f5 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_context_save.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_context_save.S @@ -49,7 +49,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_context_save SMP/Cortex-A7/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -80,7 +80,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_context_save(VOID) diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_interrupt_control.S index 77a5839b..fe1769b0 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_interrupt_control.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_interrupt_control.S @@ -44,7 +44,7 @@ INT_MASK = 0x80 @ Interrupt bit mask @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_control SMP/Cortex-A7/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -74,7 +74,7 @@ INT_MASK = 0x80 @ Interrupt bit mask @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_interrupt_disable.S index b6eb4376..7a3d9d28 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_interrupt_disable.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_interrupt_disable.S @@ -53,7 +53,7 @@ $_tx_thread_interrupt_disable: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_disable SMP/Cortex-A7/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ $_tx_thread_interrupt_disable: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_disable(void) diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_interrupt_restore.S index 85015a6e..339ed1a7 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_interrupt_restore.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_interrupt_restore.S @@ -53,7 +53,7 @@ $_tx_thread_interrupt_restore: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_interrupt_restore SMP/Cortex-A7/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -83,7 +83,7 @@ $_tx_thread_interrupt_restore: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_irq_nesting_end.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_irq_nesting_end.S index 4669e95d..5611c886 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_irq_nesting_end.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_irq_nesting_end.S @@ -50,7 +50,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_irq_nesting_end SMP/Cortex-A7/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -89,7 +89,7 @@ IRQ_MODE_BITS = 0x12 @ IRQ mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_irq_nesting_start.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_irq_nesting_start.S index 47d4c2c8..fd7a56a1 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_irq_nesting_start.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_irq_nesting_start.S @@ -46,7 +46,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_irq_nesting_start SMP/Cortex-A7/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ SYS_MODE_BITS = 0x1F @ System mode bits @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_schedule.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_schedule.S index 23c608e5..12ac8802 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_schedule.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_schedule.S @@ -62,7 +62,7 @@ $_tx_thread_schedule: @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_schedule SMP/Cortex-A7/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -95,7 +95,7 @@ $_tx_thread_schedule: @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_schedule(VOID) diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_core_get.S index 5c49f8c7..2001443e 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_core_get.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_core_get.S @@ -39,7 +39,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_smp_core_get SMP/Cortex-A7/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -68,7 +68,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ .global _tx_thread_smp_core_get diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_core_preempt.S index e8451f10..a779e06c 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_core_preempt.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_core_preempt.S @@ -43,7 +43,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_smp_core_preempt SMP/Cortex-A7/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -76,7 +76,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ .global _tx_thread_smp_core_preempt diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_current_state_get.S index d55e32c0..499b8270 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_current_state_get.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_current_state_get.S @@ -41,7 +41,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_smp_current_state_get SMP/Cortex-A7/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -70,7 +70,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ .global _tx_thread_smp_current_state_get diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_current_thread_get.S index ddc26a35..9955230b 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_current_thread_get.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_current_thread_get.S @@ -41,7 +41,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_smp_current_thread_get SMP/Cortex-A7/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -70,7 +70,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ .global _tx_thread_smp_current_thread_get diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_initialize_wait.S index cd5ef515..9cf6d262 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_initialize_wait.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_initialize_wait.S @@ -44,7 +44,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_smp_initialize_wait SMP/Cortex-A7/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -75,7 +75,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ .global _tx_thread_smp_initialize_wait diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_low_level_initialize.S index 313148a1..c072e591 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_low_level_initialize.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_low_level_initialize.S @@ -39,7 +39,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_smp_low_level_initialize SMP/Cortex-A7/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -69,7 +69,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ .global _tx_thread_smp_low_level_initialize diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_protect.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_protect.S index 16e5c014..08e8e54d 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_protect.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_protect.S @@ -50,7 +50,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_smp_protect SMP/Cortex-A7/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -81,7 +81,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ .global _tx_thread_smp_protect diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_time_get.S index efaf8867..2d61b9d2 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_time_get.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_time_get.S @@ -40,7 +40,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_smp_time_get SMP/Cortex-A7/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -70,7 +70,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ .global _tx_thread_smp_time_get diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_unprotect.s b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_unprotect.s index 97f6fd0f..d1d3b2fa 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_unprotect.s +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_unprotect.s @@ -44,7 +44,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_smp_unprotect SMP/Cortex-A7/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -76,7 +76,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ .global _tx_thread_smp_unprotect diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_stack_build.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_stack_build.S index ec5b3792..0fc7a778 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_stack_build.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_stack_build.S @@ -49,7 +49,7 @@ THUMB_BIT = 0x20 @ Thumb-bit @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_stack_build SMP/Cortex-A7/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -81,7 +81,7 @@ THUMB_BIT = 0x20 @ Thumb-bit @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_system_return.S index 56b13be2..9ab2c9b8 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_system_return.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_system_return.S @@ -48,7 +48,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_system_return SMP/Cortex-A7/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -80,7 +80,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_system_return(VOID) diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_vectored_context_save.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_vectored_context_save.S index e5ffcc69..1c64b4fd 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_vectored_context_save.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_vectored_context_save.S @@ -45,7 +45,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_vectored_context_save SMP/Cortex-A7/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -76,7 +76,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_vectored_context_save(VOID) diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_timer_interrupt.S b/ports_smp/cortex_a7_smp/gnu/src/tx_timer_interrupt.S index e88f4371..2c4aed6a 100644 --- a/ports_smp/cortex_a7_smp/gnu/src/tx_timer_interrupt.S +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_timer_interrupt.S @@ -56,7 +56,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_timer_interrupt SMP/Cortex-A7/GNU */ -@/* 6.0.1 */ +@/* 6.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -92,7 +92,7 @@ @/* */ @/* DATE NAME DESCRIPTION */ @/* */ -@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @/* */ @/**************************************************************************/ @VOID _tx_timer_interrupt(VOID) diff --git a/ports_smp/cortex_a9_smp/ac5/inc/tx_port.h b/ports_smp/cortex_a9_smp/ac5/inc/tx_port.h index a429a7c9..b6c26093 100644 --- a/ports_smp/cortex_a9_smp/ac5/inc/tx_port.h +++ b/ports_smp/cortex_a9_smp/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h SMP/Cortex-A9/AC5 */ -/* 6.0.1 */ +/* 6.1 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,7 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ /* */ /**************************************************************************/ @@ -399,7 +399,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Cortex-A9/AC5 Version Version 6.0.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Cortex-A9/AC5 Version Version 6.1 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a9_smp/ac5/readme_threadx.txt b/ports_smp/cortex_a9_smp/ac5/readme_threadx.txt index ea7708f4..06b2e4e6 100644 --- a/ports_smp/cortex_a9_smp/ac5/readme_threadx.txt +++ b/ports_smp/cortex_a9_smp/ac5/readme_threadx.txt @@ -225,7 +225,7 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A9 using AC5 tools. +09-30-2020 Initial ThreadX 6.1 version for Cortex-A9 using AC5 tools. Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_initialize_low_level.s b/ports_smp/cortex_a9_smp/ac5/src/tx_initialize_low_level.s index bbaa25aa..e00bc63e 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_initialize_low_level.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_initialize_low_level.s @@ -47,7 +47,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_initialize_low_level SMP/Cortex-A9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -80,7 +80,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_context_restore.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_context_restore.s index 7feeb883..3ebd8715 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_context_restore.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_context_restore.s @@ -69,7 +69,7 @@ SVC_MODE EQU 0x93 ; SVC mode ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_restore SMP/Cortex-A9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -101,7 +101,7 @@ SVC_MODE EQU 0x93 ; SVC mode ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_context_save.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_context_save.s index 03cf7557..8f92cfe0 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_context_save.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_context_save.s @@ -45,7 +45,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_context_save SMP/Cortex-A9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -76,7 +76,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_interrupt_control.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_interrupt_control.s index e6c4ff26..a9ff4d80 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_interrupt_control.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_interrupt_control.s @@ -42,7 +42,7 @@ INT_MASK EQU 0x80 ; Interrupt bit mask ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_control SMP/Cortex-A9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -72,7 +72,7 @@ INT_MASK EQU 0x80 ; Interrupt bit mask ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_interrupt_disable.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_interrupt_disable.s index e6270b4a..0515c9a5 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_interrupt_disable.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_interrupt_disable.s @@ -35,7 +35,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_disable SMP/Cortex-A9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -64,7 +64,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_disable(void) diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_interrupt_restore.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_interrupt_restore.s index bcf70846..21a319f3 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_interrupt_restore.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_interrupt_restore.s @@ -35,7 +35,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_interrupt_restore SMP/Cortex-A9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -65,7 +65,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_restore(UINT old_posture) diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_irq_nesting_end.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_irq_nesting_end.s index 792f26be..20a0fa8b 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_irq_nesting_end.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_irq_nesting_end.s @@ -45,7 +45,7 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_irq_nesting_end SMP/Cortex-A9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -84,7 +84,7 @@ IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_end(VOID) diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_irq_nesting_start.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_irq_nesting_start.s index 25e573de..62a774a1 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_irq_nesting_start.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_irq_nesting_start.s @@ -41,7 +41,7 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_irq_nesting_start SMP/Cortex-A9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -77,7 +77,7 @@ SYS_MODE_BITS EQU 0x1F ; System mode bits ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_irq_nesting_start(VOID) diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_schedule.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_schedule.s index 75079b73..3ca23711 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_schedule.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_schedule.s @@ -46,7 +46,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule SMP/Cortex-A9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -79,7 +79,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_core_get.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_core_get.s index fb19d750..283a6c97 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_core_get.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_core_get.s @@ -38,7 +38,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_smp_core_get SMP/Cortex-A9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -67,7 +67,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_core_get diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_core_preempt.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_core_preempt.s index df3044c2..110121f0 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_core_preempt.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_core_preempt.s @@ -40,7 +40,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_smp_core_preempt SMP/Cortex-A9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -73,7 +73,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_core_preempt diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_current_state_get.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_current_state_get.s index bd11797a..7d229a53 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_current_state_get.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_current_state_get.s @@ -40,7 +40,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_smp_current_state_get SMP/Cortex-A9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -69,7 +69,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_current_state_get diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_current_thread_get.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_current_thread_get.s index 8c93e7ed..f9a956bb 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_current_thread_get.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_current_thread_get.s @@ -40,7 +40,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_smp_current_thread_get SMP/Cortex-A9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -69,7 +69,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_current_thread_get diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_initialize_wait.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_initialize_wait.s index 75a09008..ba36f8c5 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_initialize_wait.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_initialize_wait.s @@ -43,7 +43,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_smp_initialize_wait SMP/Cortex-A9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -74,7 +74,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_initialize_wait diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_low_level_initialize.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_low_level_initialize.s index 0d76b8e0..f8b4f494 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_low_level_initialize.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_low_level_initialize.s @@ -38,7 +38,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_smp_low_level_initialize SMP/Cortex-A9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -68,7 +68,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_low_level_initialize diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_protect.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_protect.s index d479faba..ce291ecb 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_protect.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_protect.s @@ -51,7 +51,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_smp_protect SMP/Cortex-A9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -82,7 +82,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_protect diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_time_get.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_time_get.s index 9af508f7..c6faf238 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_time_get.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_time_get.s @@ -39,7 +39,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_smp_time_get SMP/Cortex-A9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -69,7 +69,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_time_get diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_unprotect.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_unprotect.s index 55efe2ad..7dd95444 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_unprotect.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_unprotect.s @@ -43,7 +43,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_smp_unprotect SMP/Cortex-A9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -75,7 +75,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ EXPORT _tx_thread_smp_unprotect diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_stack_build.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_stack_build.s index 5546d93c..3d7f2ccd 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_stack_build.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_stack_build.s @@ -47,7 +47,7 @@ THUMB_BIT EQU 0x20 ; Thumb-bit ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_stack_build SMP/Cortex-A9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -79,7 +79,7 @@ THUMB_BIT EQU 0x20 ; Thumb-bit ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_system_return.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_system_return.s index 47460e3c..4ffb4c00 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_system_return.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_system_return.s @@ -47,7 +47,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_system_return SMP/Cortex-A9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -79,7 +79,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_vectored_context_save.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_vectored_context_save.s index ffe04463..a7814759 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_vectored_context_save.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_vectored_context_save.s @@ -44,7 +44,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_vectored_context_save SMP/Cortex-A9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -75,7 +75,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_vectored_context_save(VOID) diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_timer_interrupt.s b/ports_smp/cortex_a9_smp/ac5/src/tx_timer_interrupt.s index 4f61e37f..6769262c 100644 --- a/ports_smp/cortex_a9_smp/ac5/src/tx_timer_interrupt.s +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_timer_interrupt.s @@ -55,7 +55,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_timer_interrupt SMP/Cortex-A9/AC5 */ -;/* 6.0.1 */ +;/* 6.1 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ @@ -91,7 +91,7 @@ ;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ -;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_timer_interrupt(VOID) diff --git a/ports_smp/cortex_a9_smp/gnu/example_build/MP_GIC.S b/ports_smp/cortex_a9_smp/gnu/example_build/MP_GIC.S new file mode 100644 index 00000000..2ff179fb --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/example_build/MP_GIC.S @@ -0,0 +1,516 @@ +// ------------------------------------------------------------ +// Cortex-A MPCore - Interrupt Controller functions +// +// Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + + + .text + .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + + +// ------------------------------------------------------------ +// GIC +// ------------------------------------------------------------ + + // CPU Interface offset from base of private peripheral space --> 0x0100 + // Interrupt Distributor offset from base of private peripheral space --> 0x1000 + + // Typical calls to enable interrupt ID X: + // disableIntID(X) <-- Disable that ID + // setIntPriority(X, 0) <-- Set the priority of X to 0 (the max priority) + // setPriorityMask(0x1F) <-- Set CPU's priority mask to 0x1F (the lowest priority) + // enableGIC() <-- Enable the GIC (global) + // enableGICProcessorInterface() <-- Enable the CPU interface (local to the CPU) + + + .global enableGIC + // void enableGIC(void) + // Global enable of the Interrupt Distributor + .type enableGIC, "function" + .cfi_startproc +enableGIC: + + // Get base address of private peripheral space + MRC p15, 4, r0, c15, c0, 0 // Read periph base address + ADD r0, r0, #0x1000 // Add the GIC offset + + LDR r1, [r0] // Read the GIC Enable Register (ICDDCR) + ORR r1, r1, #0x01 // Set bit 0, the enable bit + STR r1, [r0] // Write the GIC Enable Register (ICDDCR) + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global disableGIC + // void disableGIC(void) + // Global disable of the Interrupt Distributor + .type disableGIC, "function" + .cfi_startproc +disableGIC: + + // Get base address of private peripheral space + MRC p15, 4, r0, c15, c0, 0 // Read periph base address + ADD r0, r0, #0x1000 // Add the GIC offset + + LDR r1, [r0] // Read the GIC Enable Register (ICDDCR) + BIC r1, r1, #0x01 // Clear bit 0, the enable bit + STR r1, [r0] // Write the GIC Enable Register (ICDDCR) + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global enableIntID + // void enableIntID(uint32_t ID) + // Enables the interrupt source number ID + .type enableIntID, "function" + .cfi_startproc +enableIntID: + + // Get base address of private peripheral space + MOV r1, r0 // Back up passed in ID value + MRC p15, 4, r0, c15, c0, 0 // Read periph base address + + // Each interrupt source has an enable bit in the GIC. These + // are grouped into registers, with 32 sources per register + // First, we need to identify which 32-bit block the interrupt lives in + MOV r2, r1 // Make working copy of ID in r2 + MOV r2, r2, LSR #5 // LSR by 5 places, affective divide by 32 + // r2 now contains the 32-bit block this ID lives in + MOV r2, r2, LSL #2 // Now multiply by 4, to convert offset into an address offset (four bytes per reg) + + // Now work out which bit within the 32-bit block the ID is + AND r1, r1, #0x1F // Mask off to give offset within 32-bit block + MOV r3, #1 // Move enable value into r3 + MOV r3, r3, LSL r1 // Shift it left to position of ID + + ADD r2, r2, #0x1100 // Add the base offset of the Enable Set registers to the offset for the ID + STR r3, [r0, r2] // Store out (ICDISER) + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global disableIntID + // void disableIntID(uint32_t ID) + // Disables the interrupt source number ID + .type disableIntID, "function" + .cfi_startproc +disableIntID: + + // Get base address of private peripheral space + MOV r1, r0 // Back up passed in ID value + MRC p15, 4, r0, c15, c0, 0 // Read periph base address + + // First, we need to identify which 32-bit block the interrupt lives in + MOV r2, r1 // Make working copy of ID in r2 + MOV r2, r2, LSR #5 // LSR by 5 places, affective divide by 32 + // r2 now contains the 32-bit block this ID lives in + MOV r2, r2, LSL #2 // Now multiply by 4, to convert offset into an address offset (four bytes per reg) + + // Now work out which bit within the 32-bit block the ID is + AND r1, r1, #0x1F // Mask off to give offset within 32-bit block + MOV r3, #1 // Move enable value into r3 + MOV r3, r3, LSL r1 // Shift it left to position of ID in 32-bit block + + ADD r2, r2, #0x1180 // Add the base offset of the Enable Clear registers to the offset for the ID + STR r3, [r0, r2] // Store out (ICDICER) + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global setIntPriority + // void setIntPriority(uint32_t ID, uint32_t priority) + // Sets the priority of the specified ID + // r0 = ID + // r1 = priority + .type setIntPriority, "function" + .cfi_startproc +setIntPriority: + + // Get base address of private peripheral space + MOV r2, r0 // Back up passed in ID value + MRC p15, 4, r0, c15, c0, 0 // Read periph base address + + // r0 = base addr + // r1 = priority + // r2 = ID + + // Make sure that priority value is only 5 bits, and convert to expected format + AND r1, r1, #0x1F + MOV r1, r1, LSL #3 + + // Find which register this ID lives in + BIC r3, r2, #0x03 // Make a copy of the ID, clearing off the bottom two bits + // There are four IDs per reg, by clearing the bottom two bits we get an address offset + ADD r3, r3, #0x1400 // Now add the offset of the Priority Level registers from the base of the private peripheral space + ADD r0, r0, r3 // Now add in the base address of the private peripheral space, giving us the absolute address + + + // Now work out which ID in the register it is + AND r2, r2, #0x03 // Clear all but the bottom two bits, leaves which ID in the reg it is (which byte) + MOV r2, r2, LSL #3 // Multiply by 8, this gives a bit offset + + // Read -> Modify -> Write + MOV r12, #0xFF // 8 bit field mask + MOV r12, r12, LSL r2 // Move mask into correct bit position + MOV r1, r1, LSL r2 // Also, move passed in priority value into correct bit position + + + LDR r3, [r0] // Read current value of the Priority Level register + BIC r3, r3, r12 // Clear appropriate field + ORR r3, r3, r1 // Now OR in the priority value + STR r3, [r0] // And store it back again (ICDIPR) + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global getIntPriority + // uint32_t getIntPriority(void) + // Returns the priority of the specified ID + .type getIntPriority, "function" + .cfi_startproc +getIntPriority: + + // TBD + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global setIntTarget + // void setIntTarget(uint32_t ID, uint32_t target) + // Sets the target CPUs of the specified ID + .type setIntTarget, "function" + .cfi_startproc +setIntTarget: + + // Get base address of private peripheral space + MRC p15, 4, r2, c15, c0, 0 // Read periph base address + + // r0 = ID + // r1 = target + // r2 = base addr + + // Clear unused bits + AND r1, r1, #0xF + + // Find which register this ID lives in + BIC r3, r0, #0x03 // Make a copy of the ID, clearing the bottom 2 bits + // There are four IDs per reg, by clearing the bottom two bits we get an address offset + ADD r3, r3, #0x1800 // Now add the offset of the Target registers from the base of the private peripheral space + ADD r2, r2, r3 // Now add in the base address of the private peripheral space, giving us the absolute address + + // Now work out which ID in the register it is + AND r0, r0, #0x03 // Clear all but the bottom two bits, leaves which ID in the reg it is (which byte) + MOV r0, r0, LSL #3 // Multiply by 8, this gives a bit offset + + // Read -> Modify -> Write + MOV r12, #0xFF // 8 bit field mask + MOV r12, r12, LSL r0 // Move mask into correct bit position + MOV r1, r1, LSL r0 // Also, move passed in target value into correct bit position + + LDR r3, [r2] // Read current value of the Target register + BIC r3, r3, r12 // Clear appropriate field + ORR r3, r3, r1 // Now OR in the target value + STR r3, [r2] // And store it back again + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global getIntTarget + // uint32_t getIntTarget(uint32_t ID) + // Returns the target CPUs of the specified ID + .type getIntTarget, "function" + .cfi_startproc +getIntTarget: + + // TBD + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global enableGICProcessorInterface + // void enableGICProcessorInterface(void) + // Enables the processor interface + // Must be done on each core separately + .type enableGICProcessorInterface, "function" + .cfi_startproc +enableGICProcessorInterface: + + MRC p15, 4, r0, c15, c0, 0 // Read periph base address + + LDR r1, [r0, #0x100] // Read the Processor Interface Control register (ICCICR/ICPICR) + ORR r1, r1, #0x03 // Bit 0: Enables secure interrupts, Bit 1: Enables Non-Secure interrupts + BIC r1, r1, #0x08 // Bit 3: Ensure Group 0 interrupts are signalled using IRQ, not FIQ + STR r1, [r0, #0x100] // Write the Processor Interface Control register (ICCICR/ICPICR) + + BX lr + .cfi_endproc + + + +// ------------------------------------------------------------ + + .global disableGICProcessorInterface + // void disableGICProcessorInterface(void) + // Disables the processor interface + // Must be done on each core separately + .type disableGICProcessorInterface, "function" + .cfi_startproc +disableGICProcessorInterface: + + MRC p15, 4, r0, c15, c0, 0 // Read periph base address + + LDR r1, [r0, #0x100] // Read the Processor Interface Control register (ICCICR/ICPICR) + BIC r1, r1, #0x03 // Bit 0: Enables secure interrupts, Bit 1: Enables Non-Secure interrupts + STR r1, [r0, #0x100] // Write the Processor Interface Control register (ICCICR/ICPICR) + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global setPriorityMask + // void setPriorityMask(uint32_t priority) + // Sets the Priority mask register for the CPU run on + // The reset value masks ALL interrupts! + .type setPriorityMask, "function" + .cfi_startproc +setPriorityMask: + MRC p15, 4, r1, c15, c0, 0 // Read periph base address + + STR r0, [r1, #0x0104] // Write the Priority Mask register + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global setBinaryPoint + // void setBinaryPoint(uint32_t priority) + // Sets the Binary Point Register for the CPU run on + .type setBinaryPoint, "function" + .cfi_startproc +setBinaryPoint: + MRC p15, 4, r1, c15, c0, 0 // Read periph base address + + STR r0, [r1, #0x0108] // Write the Priority Mask register (ICCPMR/ICCIPMR) + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global readIntAck + // uint32_t readIntAck(void) + // Returns the value of the Interrupt Acknowledge Register + .type readIntAck, "function" + .cfi_startproc +readIntAck: + MRC p15, 4, r0, c15, c0, 0 // Read periph base address + LDR r0, [r0, #0x010C] // Read the Interrupt Acknowledge Register + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global writeEOI + // void writeEOI(uint32_t ID) + // Writes ID to the End Of Interrupt register + .type writeEOI, "function" + .cfi_startproc +writeEOI: + MRC p15, 4, r1, c15, c0, 0 // Read periph base address + + STR r0, [r1, #0x0110] // Write ID to the End of Interrupt register + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ +// SGI +// ------------------------------------------------------------ + + .global sendSGI + // void sendSGI(uint32_t ID, uint32_t target_list, uint32_t filter_list) + // Send a software generate interrupt + .type sendSGI, "function" + .cfi_startproc +sendSGI: + + AND r3, r0, #0x0F // Mask off unused bits of ID, and move to r3 + AND r1, r1, #0x0F // Mask off unused bits of target_filter + AND r2, r2, #0x0F // Mask off unused bits of filter_list + + ORR r3, r3, r1, LSL #16 // Combine ID and target_filter + ORR r3, r3, r2, LSL #24 // and now the filter list + + // Get the address of the GIC + MRC p15, 4, r0, c15, c0, 0 // Read periph base address + ADD r0, r0, #0x1F00 // Add offset of the sgi_trigger reg + + STR r3, [r0] // Write to the Software Generated Interrupt Register (ICDSGIR) + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ +// TrustZone +// ------------------------------------------------------------ + + .global enableSecureFIQs + // void enableSecureFIQs(void) + // Enables the sending of secure interrupts as FIQs + .type enableSecureFIQs, "function" + .cfi_startproc +enableSecureFIQs: + + MRC p15, 4, r0, c15, c0, 0 // Read periph base address + + LDR r1, [r0, #0x100] // Read the Processor Interface Control register + ORR r1, r1, #0x08 // Bit 3: Controls whether secure interrupts are signalled as IRQs or FIQs + STR r1, [r0, #0x100] // Write the Processor Interface Control register + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global disableSecureFIQs + // void disableSecureFIQs(void) + // Disables the sending of secure interrupts as FIQs + .type disableSecureFIQs, "function" + .cfi_startproc +disableSecureFIQs: + + MRC p15, 4, r0, c15, c0, 0 // Read periph base address + + LDR r1, [r0, #0x100] // Read the Processor Interface Control register + BIC r1, r1, #0x08 // Bit 3: Controls whether secure interrupts are signalled as IRQs or FIQs + STR r1, [r0, #0x100] // Write the Processor Interface Control register + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global makeIntSecure + // void makeIntSecure(uint32_t ID) + // Sets the specified ID as being Secure + // r0 - ID + .type makeIntSecure, "function" + .cfi_startproc +makeIntSecure: + + MRC p15, 4, r1, c15, c0, 0 // Read periph base address + + // Each interrupt source has a secutiy bit in the GIC. These + // are grouped into registers, with 32 sources per register + // First, we need to identify which 32-bit block the interrupt lives in + MOV r2, r0 // Make working copy of ID in r2 + MOV r2, r2, LSR #5 // LSR by 5 places, affective divide by 32 + // r2 now contains the 32-bit block this ID lives in + MOV r2, r2, LSL #2 // Now multiply by 4, to convert offset into an address offset (four bytes per reg) + + // Now work out which bit within the 32-bit block the ID is + AND r0, r0, #0x1F // Mask off to give offset within 32-bit block + MOV r3, #1 // Move enable value into r3 + MOV r3, r3, LSL r0 // Shift it left to position of ID + + ADD r2, r2, #0x1080 // Add the base offset of the Interrupt Configuration registers to the offset for the ID + + LDR r0, [r1, r2] // Read appropriate Interrupt Configuration + BIC r0, r0, r3 // Clear bit (0 = secure) + STR r0, [r1, r2] // Store out + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global makeIntNonSecure + // void makeIntNonSecure(uint32_t ID) + // Sets the specified ID as being non-secure + // r0 - ID + .type makeIntNonSecure, "function" + .cfi_startproc +makeIntNonSecure: + + MRC p15, 4, r1, c15, c0, 0 // Read periph base address + + // Each interrupt source has a secutiy bit in the GIC. These + // are grouped into registers, with 32 sources per register + // First, we need to identify which 32-bit block the interrupt lives in + MOV r2, r0 // Make working copy of ID in r2 + MOV r2, r2, LSR #5 // LSR by 5 places, affective divide by 32 + // r2 now contains the 32-bit block this ID lives in + MOV r2, r2, LSL #2 // Now multiply by 4, to convert offset into an address offset (four bytes per reg) + + // Now work out which bit within the 32-bit block the ID is + AND r0, r0, #0x1F // Mask off to give offset within 32-bit block + MOV r3, #1 // Move enable value into r3 + MOV r3, r3, LSL r0 // Shift it left to position of ID + + ADD r2, r2, #0x1080 // Add the base offset of the Interrupt Configuration registers to the offset for the ID + + LDR r0, [r1, r2] // Read appropriate Interrupt Configuration + ORR r0, r0, r3 // Set bit (1 = secure) + STR r0, [r1, r2] // Store out + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global getIntSecurity + // uint32_t getIntSecurity(uint32_t ID, uint32_t security) + // Returns the security of the specified ID + .type getIntSecurity, "function" + .cfi_startproc +getIntSecurity: + + // TBD + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ +// End of MP_GIC.s +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a9_smp/gnu/example_build/MP_GIC.h b/ports_smp/cortex_a9_smp/gnu/example_build/MP_GIC.h new file mode 100644 index 00000000..1d047611 --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/example_build/MP_GIC.h @@ -0,0 +1,120 @@ +// ------------------------------------------------------------ +// Cortex-A MPCore - Interrupt Controller functions +// Header File +// +// Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#ifndef _CORTEXA_GIC_H +#define _CORTEXA_GIC_H + +#define SPURIOUS (255) + +// PPI IDs: +#define MPCORE_PPI_PRIVATE_TIMER (29) +#define MPCORE_PPI_PRIVATE_WD (30) +#define MPCORE_PPI_GLOBAL_TIMER (27) +#define MPCORE_PPI_LEGACY_IRQ (31) +#define MPCORE_PPI_LEGACY_FIQ (28) + +// ------------------------------------------------------------ +// GIC +// ------------------------------------------------------------ + +// Typical calls to enable interrupt ID X: +// enableIntID(X) <-- Enable that ID +// setIntPriority(X, 0) <-- Set the priority of X to 0 (the max priority) +// setPriorityMask(0x1F) <-- Set Core's priority mask to 0x1F (the lowest priority) +// enableGIC() <-- Enable the GIC (global) +// enableGICProcessorInterface() <-- Enable the CPU interface (local to the core) +// + + +// Global enable of the Interrupt Distributor +void enableGIC(void); + +// Global disable of the Interrupt Distributor +void disableGIC(void); + +// Enables the interrupt source number ID +void enableIntID(unsigned int ID); + +// Disables the interrupt source number ID +void disableIntID(unsigned int ID); + +// Enables the processor interface +// Must be done on each core separately +void enableGICProcessorInterface(void); + +// Disables the processor interface +// Must be done on each core separately +void disableGICProcessorInterface(void); + +// Sets the Priority mask register for the core run on +// The reset value masks ALL interrupts! +// +// NOTE: Bits 2:0 of this register are SBZ, the function does perform any shifting! +void setPriorityMask(unsigned int priority); + +// Sets the Binary Point Register for the core run on +void setBinaryPoint(unsigned int priority); + +// Sets the priority of the specified ID +void setIntPriority(unsigned int ID, unsigned int priority); + +// Returns the priority of the specified ID +unsigned int getIntPriority(unsigned int ID, unsigned int priority); + +#define MPCORE_IC_TARGET_NONE (0x0) +#define MPCORE_IC_TARGET_CPU0 (0x1) +#define MPCORE_IC_TARGET_CPU1 (0x2) +#define MPCORE_IC_TARGET_CPU2 (0x4) +#define MPCORE_IC_TARGET_CPU3 (0x8) + +// Sets the target CPUs of the specified ID +// For 'target' use one of the above defines +void setIntTarget(unsigned int ID, unsigned int target); + +// Returns the target CPUs of the specified ID +unsigned int getIntTarget(unsigned int ID); + +// Returns the value of the Interrupt Acknowledge Register +unsigned int readIntAck(void); + +// Writes ID to the End Of Interrupt register +void writeEOI(unsigned int ID); + +// ------------------------------------------------------------ +// SGI +// ------------------------------------------------------------ + +// Send a software generate interrupt +void sendSGI(unsigned int ID, unsigned int core_list, unsigned int filter_list); + +// ------------------------------------------------------------ +// TrustZone +// ------------------------------------------------------------ + +// Enables the sending of secure interrupts as FIQs +void enableSecureFIQs(void); + +// Disables the sending of secure interrupts as FIQs +void disableSecureFIQs(void); + +// Sets the specified ID as secure +void makeIntSecure(unsigned int ID); + +// Set the specified ID as non-secure +void makeIntNonSecure(unsigned int ID); + +// Returns the security of the specified ID +unsigned int getIntSecurity(unsigned int ID); + +#endif + +// ------------------------------------------------------------ +// End of MP_GIC.h +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a9_smp/gnu/example_build/MP_Mutexes.S b/ports_smp/cortex_a9_smp/gnu/example_build/MP_Mutexes.S new file mode 100644 index 00000000..771e3321 --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/example_build/MP_Mutexes.S @@ -0,0 +1,134 @@ +// ------------------------------------------------------------ +// Armv7-A MPCore - Mutex Code +// +// Copyright (c) 2011-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + + + .text + .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + + + //NOTES + // struct mutex_t defined in MP_Mutexes.h + // typedef struct mutex_t + // { + // unsigned int lock// <-- offset 0 + // } + // + // lock: 0xFF=unlocked 0x0 = Locked by CPU 0, 0x1 = Locked by CPU 1, 0x2 = Locked by CPU 2, 0x3 = Locked by CPU 3 + // + +.equ UNLOCKED, 0xFF + +// ------------------------------------------------------------ + + .global initMutex + // void initMutex(mutex_t* pMutex) + // Places mutex into a known state + // r0 = address of mutex_t + .type initMutex, "function" + .cfi_startproc +initMutex: + + MOV r1, #UNLOCKED // Mark as unlocked + STR r1, [r0] + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global lockMutex + // void lockMutex(mutex_t* pMutex) + // Blocking call, returns once successfully locked a mutex + // r0 = address of mutex_t + .type lockMutex, "function" + .cfi_startproc +lockMutex: + + // Is mutex locked? + // ----------------- + LDREX r1, [r0] // Read lock field + CMP r1, #UNLOCKED // Compare with "unlocked" + + WFENE // If mutex is locked, go into standby + BNE lockMutex // On waking re-check the mutex + + // Attempt to lock mutex + // ----------------------- + MRC p15, 0, r1, c0, c0, 5 // Read CPU ID register + AND r1, r1, #0x03 // Mask off, leaving the CPU ID field. + STREX r2, r1, [r0] // Attempt to lock mutex, by write CPU's ID to lock field + CMP r2, #0x0 // Check whether store completed successfully (0=succeeded) + BNE lockMutex // If store failed, go back to beginning and try again + + DMB + + BX lr // Return as mutex is now locked by this cpu + .cfi_endproc + + +// ------------------------------------------------------------ + + .global unlockMutex + // unsigned int unlockMutex(mutex_t* pMutex) + // Releases mutex, returns 0x0 for success and 0x1 for failure + // r0 = address of mutex_t + .type unlockMutex, "function" + .cfi_startproc +unlockMutex: + + // Does this CPU own the mutex? + // ----------------------------- + MRC p15, 0, r1, c0, c0, 5 // Read CPU ID register + AND r1, r1, #0x03 // Mask off, leaving the CPU ID in r1 + LDR r2, [r0] // Read the lock field of the mutex + CMP r1, r2 // Compare ID of this CPU with the lock owner + MOVNE r0, #0x1 // If ID doesn't match, return "fail" + BXNE lr + + + // Unlock mutex + // ------------- + DMB // Ensure that accesses to shared resource have completed + + MOV r1, #UNLOCKED // Write "unlocked" into lock field + STR r1, [r0] + + DSB // Ensure that no instructions following the barrier execute until + // all memory accesses prior to the barrier have completed. + + SEV // Send event to other CPUs, wakes anyone waiting on a mutex (using WFE) + + MOV r0, #0x0 // Return "success" + BX lr + .cfi_endproc + + + +// ------------------------------------------------------------ + + .global isMutexLocked + // unsigned int isMutexLocked(mutex_t* pMutex) + // Returns 0x0 if mutex unlocked, 0x1 is locked + // r0 = address of mutex_t + .type isMutexLocked, "function" + .cfi_startproc +isMutexLocked: + LDR r0, [r0] + CMP r0, #UNLOCKED + MOVEQ r0, #0x0 + MOVNE r0, #0x1 + BX lr + .cfi_endproc + + + +// ------------------------------------------------------------ +// End of MP_Mutexes.s +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a9_smp/gnu/example_build/MP_Mutexes.h b/ports_smp/cortex_a9_smp/gnu/example_build/MP_Mutexes.h new file mode 100644 index 00000000..e410677b --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/example_build/MP_Mutexes.h @@ -0,0 +1,40 @@ +// ------------------------------------------------------------ +// MP Mutex Header File +// +// Copyright (c) 2011-2014 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#ifndef MP_MUTEX_H +#define MP_MUTEX_H + +// 0xFF = unlocked +// 0x0 = Locked by CPU 0 +// 0x1 = Locked by CPU 1 +// 0x2 = Locked by CPU 2 +// 0x3 = Locked by CPU 3 +typedef struct +{ + unsigned int lock; +}mutex_t; + +// Places mutex into a known state +// r0 = address of mutex_t +void initMutex(mutex_t* pMutex); + +// Blocking call, returns once successfully locked a mutex +// r0 = address of mutex_t +void lockMutex(mutex_t* pMutex); + +// Releases (unlock) mutex. Fails if CPU not owner of mutex. +// returns 0x0 for success, and 0x1 for failure +// r0 = address of mutex_t +unsigned int unlockMutex(mutex_t* pMutex); + +// Returns 0x0 if mutex unlocked, 0x1 is locked +// r0 = address of mutex_t +unsigned int isMutexLocked(mutex_t* pMutex); + +#endif diff --git a/ports_smp/cortex_a9_smp/gnu/example_build/MP_PrivateTimer.S b/ports_smp/cortex_a9_smp/gnu/example_build/MP_PrivateTimer.S new file mode 100644 index 00000000..2077d917 --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/example_build/MP_PrivateTimer.S @@ -0,0 +1,118 @@ +// ------------------------------------------------------------ +// Cortex-A MPCore - Private timer functions +// +// Copyright ARM Ltd 2009. All rights reserved. +// ------------------------------------------------------------ + + .text + .align 3 + + // PPI ID 29 + + + // Typical set of calls to enable Timer: + // init_private_timer(0xXXXX, 0) <-- Counter down value of 0xXXXX, with auto-reload + // start_private_timer() + + // Timer offset from base of private peripheral space --> 0x600 + +// ------------------------------------------------------------ + + .global init_private_timer + .type init_private_timer,function + // void init_private_timer(unsigned int load_value, unsigned int auto_reload) + // Sets up the private timer + // r0: initial load value + // r1: IF 0 (AutoReload) ELSE (SingleShot) +init_private_timer: + + // Get base address of private perpherial space + MOV r2, r0 // Make a copy of r0 before corrupting + MRC p15, 4, r0, c15, c0, 0 // Read periph base address + + // Set the load value + STR r2, [r0, #0x600] + + // Control register bit layout + // Bit 0 - Enable + // Bit 1 - Auto-Reload // see DE681117 + // Bit 2 - IRQ Generation + + // Form control reg value + CMP r1, #0 // Check whether to enable auto-reload + MOVNE r2, #0x04 // No auto-reload + MOVEQ r2, #0x06 // With auto-reload + + // Store to control register + STR r2, [r0, #0x608] + + BX lr + +// ------------------------------------------------------------ + + // void start_private_timer(void) + // Starts the private timer + .global start_private_timer + .type start_private_timer,function +start_private_timer: + + MRC p15, 4, r0, c15, c0, 0 // Read periph base address + + LDR r1, [r0, #0x608] // Read control reg + ORR r1, r1, #0x01 // Set enable bit + STR r1, [r0, #0x608] // Write modified value back + + BX lr + +// ------------------------------------------------------------ + + // void stop_private_timer(void) + // Stops the private timer + .global stop_private_timer + .type stop_private_timer,function +stop_private_timer: + + MRC p15, 4, r0, c15, c0, 0 // Read periph base address + + LDR r1, [r0, #0x608] // Read control reg + BIC r1, r1, #0x01 // Clear enable bit + STR r1, [r0, #0x608] // Write modified value back + + BX lr + +// ------------------------------------------------------------ + + // unsigned int read_private_timer(void) + // Reads the current value of the timer count register + .global get_private_timer_count + .type get_private_timer_count,function +get_private_timer_count: + + MRC p15, 4, r0, c15, c0, 0 // Read periph base address + + LDR r0, [r0, #0x604] // Read count register + + BX lr + +// ------------------------------------------------------------ + + // void clear_private_timer_irq(void) + // Clears the private timer interrupt + .global clear_private_timer_irq + .type clear_private_timer_irq,function +clear_private_timer_irq: + MRC p15, 4, r0, c15, c0, 0 // Read periph base address + + // Clear the interrupt by writing 0x1 to the Timer's Interrupt Status register + MOV r1, #1 + STR r1, [r0, #0x60C] + + BX lr + +// ------------------------------------------------------------ +// End of code +// ------------------------------------------------------------ + +// ------------------------------------------------------------ +// End of MP_PrivateTimer.s +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a9_smp/gnu/example_build/MP_PrivateTimer.h b/ports_smp/cortex_a9_smp/gnu/example_build/MP_PrivateTimer.h new file mode 100644 index 00000000..b0ab212a --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/example_build/MP_PrivateTimer.h @@ -0,0 +1,36 @@ +// ------------------------------------------------------------ +// Cortex-A MPCore - Private timer functions +// Header Filer +// +// Copyright ARM Ltd 2009. All rights reserved. +// ------------------------------------------------------------ + +#ifndef _CORTEXA_PRIVATE_TIMER_ +#define _CORTEXA_PRIVATE_TIMER_ + +// Typical set of calls to enable Timer: +// init_private_timer(0xXXXX, 0) <-- Counter down value of 0xXXXX, with auto-reload +// start_private_timer() + +// Sets up the private timer +// r0: initial load value +// r1: IF 0 (AutoReload) ELSE (SingleShot) +void init_private_timer(unsigned int load_value, unsigned int auto_reload); + +// Starts the private timer +void start_private_timer(void); + +// Stops the private timer +void stop_private_timer(void); + +// Reads the current value of the timer count register +unsigned int get_private_timer_count(void); + +// Clears the private timer interrupt +void clear_private_timer_irq(void); + +#endif + +// ------------------------------------------------------------ +// End of MP_PrivateTimer.h +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a9_smp/gnu/example_build/MP_SCU.S b/ports_smp/cortex_a9_smp/gnu/example_build/MP_SCU.S new file mode 100644 index 00000000..bd4c667b --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/example_build/MP_SCU.S @@ -0,0 +1,188 @@ +// ------------------------------------------------------------ +// Cortex-A MPCore - Snoop Control Unit (SCU) +// Suitable for Cortex-A5 MPCore and Cortex-A9 MPCore +// +// Copyright (c) 2011-2015 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + + + .text + + +// ------------------------------------------------------------ +// Misc +// ------------------------------------------------------------ + + .global getNumCPUs + // uint32_t getNumCPUs(void) + // Returns the number of CPUs in the Cluster + .type getNumCPUs, "function" +getNumCPUs: + + // Get base address of private peripheral space + MRC p15, 4, r0, c15, c0, 0 // Read periph base address + + LDR r0, [r0, #0x004] // Read SCU Configuration register + AND r0, r0, #0x3 // Bits 1:0 gives the number of cores-1 + ADD r0, r0, #1 + BX lr + + +// ------------------------------------------------------------ +// SCU +// ------------------------------------------------------------ + + // SCU offset from base of private peripheral space --> 0x000 + + .global enableSCU + // void enableSCU(void) + // Enables the SCU + .type enableSCU, "function" +enableSCU: + + MRC p15, 4, r0, c15, c0, 0 // Read periph base address + + LDR r1, [r0, #0x0] // Read the SCU Control Register + ORR r1, r1, #0x1 // Set bit 0 (The Enable bit) + STR r1, [r0, #0x0] // Write back modifed value + + BX lr + + +// ------------------------------------------------------------ + + .global getCPUsInSMP + // uint32_t getCPUsInSMP(void) + // The return value is 1 bit per core: + // bit 0 - CPU 0 + // bit 1 - CPU 1 + // etc... + .type getCPUsInSMP, "function" +getCPUsInSMP: + + MRC p15, 4, r0, c15, c0, 0 // Read periph base address + + LDR r0, [r0, #0x004] // Read SCU Configuration register + MOV r0, r0, LSR #4 // Bits 7:4 gives the cores in SMP mode, shift then mask + AND r0, r0, #0x0F + + BX lr + + +// ------------------------------------------------------------ + + .global enableMaintenanceBroadcast + // void enableMaintenanceBroadcast(void) + // Enable the broadcasting of cache & TLB maintenance operations + // When enabled AND in SMP, broadcast all "inner sharable" + // cache and TLM maintenance operations to other SMP cores + .type enableMaintenanceBroadcast, "function" +enableMaintenanceBroadcast: + MRC p15, 0, r0, c1, c0, 1 // Read Aux Ctrl register + MOV r1, r0 + ORR r0, r0, #0x01 // Set the FW bit (bit 0) + CMP r0, r1 + MCRNE p15, 0, r0, c1, c0, 1 // Write Aux Ctrl register + + BX lr + + +// ------------------------------------------------------------ + + .global disableMaintenanceBroadcast + // void disableMaintenanceBroadcast(void) + // Disable the broadcasting of cache & TLB maintenance operations + .type disableMaintenanceBroadcast, "function" +disableMaintenanceBroadcast: + MRC p15, 0, r0, c1, c0, 1 // Read Aux Ctrl register + BIC r0, r0, #0x01 // Clear the FW bit (bit 0) + MCR p15, 0, r0, c1, c0, 1 // Write Aux Ctrl register + + BX lr + + +// ------------------------------------------------------------ + + .global secureSCUInvalidate + // void secureSCUInvalidate(uint32_t cpu, uint32_t ways) + // cpu: 0x0=CPU 0 0x1=CPU 1 etc... + // This function invalidates the SCU copy of the tag rams + // for the specified core. Typically only done at start-up. + // Possible flow: + // - Invalidate L1 caches + // - Invalidate SCU copy of TAG RAMs + // - Join SMP + .type secureSCUInvalidate, "function" +secureSCUInvalidate: + AND r0, r0, #0x03 // Mask off unused bits of CPU ID + MOV r0, r0, LSL #2 // Convert into bit offset (four bits per core) + + AND r1, r1, #0x0F // Mask off unused bits of ways + MOV r1, r1, LSL r0 // Shift ways into the correct CPU field + + MRC p15, 4, r2, c15, c0, 0 // Read periph base address + + STR r1, [r2, #0x0C] // Write to SCU Invalidate All in Secure State + + BX lr + + + +// ------------------------------------------------------------ +// TrustZone +// ------------------------------------------------------------ + + .global setPrivateTimersNonSecureAccess + // void setPrivateTimersNonSecureAccess(uint32_t secure, uint32_t cpu) + // Sets whether the Private Timer & Watchdog can be accessed in NS world + // r0 - IF 0 (secure access only) ELSE (ns access allowed) + .type setPrivateTimersNonSecureAccess, "function" +setPrivateTimersNonSecureAccess: + AND r0, r0, #0x01 // Mask + ADD r1, r1, #0x04 // Adjust r1, as field starts at bit 4 + MOV r0, r0, LSL r1 // Shift bit into correct position for CPU + + MOV r12, #1 + MOV r12, r12, LSL r1 // Form a mask to clear existing bit value + + MRC p15, 4, r2, c15, c0, 0 // Read periph base address + + LDR r3, [r2, #0x54] // Read SCU Secure Access Control (SSAC) register + BIC r3, r3, r12 // Clear current value + ORR r3, r3, r0 // Set to specified value + STR r3, [r2, #0x54] // Write SCU Secure Access Control (SSAC) register + + BX lr + + +// ------------------------------------------------------------ + + .global setGlobalTimerNonSecureAccess + // void setGlobalTimerNonSecureAccess(uint32_t secure, uint32_t cpu) + // Sets whether the Global Timer can be accessed in NS world + // r0 - IF 0 (secure access only) ELSE (ns access allowed) + .type setGlobalTimerNonSecureAccess, "function" +setGlobalTimerNonSecureAccess: + AND r0, r0, #0x01 // Mask + ADD r1, r1, #0x08 // Adjust r1, as field starts at bit 8 + MOV r0, r0, LSL r1 // Shift bit into correct position for CPU + + MOV r12, #1 + MOV r12, r12, LSL r1 // Form a mask to clear existing bit value + + MRC p15, 4, r2, c15, c0, 0 // Read periph base address + + LDR r3, [r2, #0x54] // Read SCU Secure Access Control (SSAC) register + BIC r3, r3, r12 // Clear current value + ORR r3, r3, r0 // Set to specified value + STR r3, [r2, #0x54] // Write SCU Secure Access Control (SSAC) register + + BX lr + + +// ------------------------------------------------------------ +// End of MP_SCU.s +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a9_smp/gnu/example_build/MP_SCU.h b/ports_smp/cortex_a9_smp/gnu/example_build/MP_SCU.h new file mode 100644 index 00000000..af4ccfb8 --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/example_build/MP_SCU.h @@ -0,0 +1,65 @@ +// ------------------------------------------------------------ +// Cortex-A MPCore - Snoop Control Unit (SCU) +// Suitable for Cortex-A5 MPCore and Cortex-A9 MPCore +// +// Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#ifndef _CORTEXA_SCU_H +#define _CORTEXA_SCU_H + +// ------------------------------------------------------------ +// SCU +// ------------------------------------------------------------ + +// Returns the number of cores in the cluster +unsigned int getNumCPUs(void); + +// ------------------------------------------------------------ +// SCU +// ------------------------------------------------------------ + +// Enables the SCU +void enableSCU(void); + +// The return value is 1 bit per core: +// bit 0 (0x1) - CPU 0 +// bit 1 (0x2) - CPU 1 +// bit 2 (0x4) - CPU 2 +// bit 3 (0x8) - CPU 3 +unsigned int getCPUsInSMP(void); + + //Enable the broadcasting of cache & TLB maintenance operations +// When enabled AND in SMP, broadcast all "inner sharable" +// cache and TLM maintenance operations to other SMP cores +void enableMaintenanceBroadcast(void); + +// Disable the broadcasting of cache & TLB maintenance operations +void disableMaintenanceBroadcast(void); + +// cpu: 0x0=CPU 0 0x1=CPU 1 etc... +// This function invalidates the SCU copy of the tag rams +// for the specified core. +void secureSCUInvalidate(unsigned int cpu, unsigned int ways); + +// ------------------------------------------------------------ +// TrustZone +// ------------------------------------------------------------ + +// Sets whether the Private Timer & Watchdog can be accessed in NS world +// secure - IF 0 (secure access only) ELSE (ns access allowed) +void setPrivateTimersNonSecureAccess(unsigned int secure, unsigned int cpu); + + +// Sets whether the Global Timer can be accessed in NS world +// secure - IF 0 (secure access only) ELSE (ns access allowed) +void setGlobalTimersNonSecureAccess(unsigned int secure, unsigned int cpu); + +#endif + +// ------------------------------------------------------------ +// End of MP_SCU.h +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a9_smp/gnu/example_build/build_threadx.bat b/ports_smp/cortex_a9_smp/gnu/example_build/build_threadx.bat new file mode 100644 index 00000000..679240fe --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/example_build/build_threadx.bat @@ -0,0 +1,257 @@ +del tx.a +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 tx_initialize_low_level.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 ../src/tx_thread_context_restore.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 ../src/tx_thread_context_save.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 ../src/tx_thread_interrupt_control.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 ../src/tx_thread_interrupt_disable.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 ../src/tx_thread_interrupt_restore.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 ../src/tx_thread_irq_nesting_end.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 ../src/tx_thread_irq_nesting_start.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 ../src/tx_thread_schedule.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 ../src/tx_thread_smp_core_get.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 ../src/tx_thread_smp_core_preempt.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 ../src/tx_thread_smp_current_state_get.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 ../src/tx_thread_smp_current_thread_get.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 ../src/tx_thread_smp_initialize_wait.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 ../src/tx_thread_smp_low_level_initialize.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 ../src/tx_thread_smp_protect.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 ../src/tx_thread_smp_time_get.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 ../src/tx_thread_smp_unprotect.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 ../src/tx_thread_stack_build.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 ../src/tx_thread_system_return.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 ../src/tx_thread_vectored_context_save.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 ../src/tx_timer_interrupt.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_block_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_block_pool_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_block_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_block_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_block_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_block_pool_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_block_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_block_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_block_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_block_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_byte_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_byte_pool_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_byte_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_byte_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_byte_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_byte_pool_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_byte_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_byte_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_byte_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_byte_pool_search.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_byte_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_event_flags_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_event_flags_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_event_flags_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_event_flags_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_event_flags_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_event_flags_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_event_flags_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_event_flags_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_event_flags_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_event_flags_set_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_initialize_high_level.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_initialize_kernel_enter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_initialize_kernel_setup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_mutex_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_mutex_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_mutex_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_mutex_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_mutex_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_mutex_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_mutex_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_mutex_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_mutex_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_mutex_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_mutex_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_queue_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_queue_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_queue_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_queue_flush.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_queue_front_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_queue_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_queue_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_queue_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_queue_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_queue_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_queue_receive.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_queue_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_queue_send_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_semaphore_ceiling_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_semaphore_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_semaphore_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_semaphore_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_semaphore_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_semaphore_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_semaphore_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_semaphore_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_semaphore_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_semaphore_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_semaphore_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_semaphore_put_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_entry_exit_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_identify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_preemption_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_relinquish.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_reset.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_shell_entry.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_sleep.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_stack_analyze.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_stack_error_handler.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_stack_error_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_system_preempt_check.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_system_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_system_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_terminate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_time_slice.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_time_slice_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_timeout.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_wait_abort.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_time_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_time_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_expiration_process.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_system_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_system_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_thread_entry.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_trace_enable.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_trace_disable.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_trace_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_trace_interrupt_control.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_trace_isr_enter_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_trace_isr_exit_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_trace_object_register.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_trace_object_unregister.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_trace_user_event_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_trace_buffer_full_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_trace_event_filter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_trace_event_unfilter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_block_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_block_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_block_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_block_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_block_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_block_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_byte_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_byte_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_byte_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_byte_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_byte_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_byte_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_event_flags_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_event_flags_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_event_flags_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_event_flags_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_event_flags_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_event_flags_set_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_mutex_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_mutex_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_mutex_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_mutex_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_mutex_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_mutex_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_queue_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_queue_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_queue_flush.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_queue_front_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_queue_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_queue_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_queue_receive.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_queue_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_queue_send_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_semaphore_ceiling_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_semaphore_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_semaphore_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_semaphore_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_semaphore_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_semaphore_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_semaphore_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_semaphore_put_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_thread_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_thread_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_thread_entry_exit_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_thread_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_thread_preemption_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_thread_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_thread_relinquish.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_thread_reset.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_thread_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_thread_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_thread_terminate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_thread_time_slice_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_thread_wait_abort.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_timer_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_timer_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_timer_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_timer_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_timer_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_timer_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_smp_current_state_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_smp_debug_entry_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_smp_high_level_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_smp_rebalance_execute_list.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_smp_core_exclude.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_smp_core_exclude_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_smp_core_exclude.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_smp_core_exclude_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_smp_utilities.c +arm-none-eabi-ar -r tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o +arm-none-eabi-ar -r tx.a tx_initialize_low_level.o tx_thread_interrupt_disable.o +arm-none-eabi-ar -r tx.a tx_thread_interrupt_restore.o tx_thread_irq_nesting_end.o tx_thread_irq_nesting_start.o +arm-none-eabi-ar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o +arm-none-eabi-ar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o +arm-none-eabi-ar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o +arm-none-eabi-ar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o +arm-none-eabi-ar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o +arm-none-eabi-ar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o +arm-none-eabi-ar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o +arm-none-eabi-ar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o +arm-none-eabi-ar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o +arm-none-eabi-ar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o +arm-none-eabi-ar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o +arm-none-eabi-ar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o +arm-none-eabi-ar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o +arm-none-eabi-ar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o +arm-none-eabi-ar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o +arm-none-eabi-ar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o +arm-none-eabi-ar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o +arm-none-eabi-ar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o +arm-none-eabi-ar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o +arm-none-eabi-ar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o +arm-none-eabi-ar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o +arm-none-eabi-ar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o +arm-none-eabi-ar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o +arm-none-eabi-ar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o +arm-none-eabi-ar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o +arm-none-eabi-ar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o +arm-none-eabi-ar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o +arm-none-eabi-ar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o +arm-none-eabi-ar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o +arm-none-eabi-ar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o +arm-none-eabi-ar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o +arm-none-eabi-ar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o +arm-none-eabi-ar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o +arm-none-eabi-ar -r tx.a tx_thread_smp_current_state_set.o tx_thread_smp_debug_entry_insert.o tx_thread_smp_high_level_initialize.o +arm-none-eabi-ar -r tx.a tx_thread_smp_rebalance_execute_list.o tx_thread_smp_core_exclude.o tx_thread_smp_core_exclude_get.o +arm-none-eabi-ar -r tx.a tx_timer_smp_core_exclude.o tx_timer_smp_core_exclude_get.o tx_thread_smp_utilities.o +arm-none-eabi-ar -r tx.a tx_thread_smp_core_get.o tx_thread_smp_core_preempt.o tx_thread_smp_current_state_get.o tx_thread_smp_current_thread_get.o tx_thread_smp_initialize_wait.o +arm-none-eabi-ar -r tx.a tx_thread_smp_low_level_initialize.o tx_thread_smp_protect.o tx_thread_smp_time_get.o tx_thread_smp_unprotect.o diff --git a/ports_smp/cortex_a9_smp/gnu/example_build/build_threadx_sample.bat b/ports_smp/cortex_a9_smp/gnu/example_build/build_threadx_sample.bat new file mode 100644 index 00000000..22d0a618 --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/example_build/build_threadx_sample.bat @@ -0,0 +1,8 @@ +arm-none-eabi-gcc -c -g -I../../../../common_smp/inc -I../inc -mcpu=cortex-a5 sample_threadx.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 startup.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 MP_GIC.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 MP_SCU.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 MP_Mutexes.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 MP_PrivateTimer.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 v7.S +arm-none-eabi-gcc -T sample_threadx.ld -e Vectors -o sample_threadx.axf MP_PrivateTimer.o MP_GIC.o MP_Mutexes.o MP_SCU.o sample_threadx.o startup.o v7.o tx.a -Wl,-M > sample_threadx.map diff --git a/ports_smp/cortex_a9_smp/gnu/example_build/sample_threadx.c b/ports_smp/cortex_a9_smp/gnu/example_build/sample_threadx.c new file mode 100644 index 00000000..1b6df7c2 --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/example_build/sample_threadx.c @@ -0,0 +1,381 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_TIMER timer_0; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +#ifdef TX_ENABLE_EVENT_TRACE + +UCHAR event_buffer[65536]; + +#endif + + + +int main(void) +{ + + /* Enter ThreadX. */ + tx_kernel_enter(); + + return 0; +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + +#ifdef TX_ENABLE_EVENT_TRACE + + tx_trace_enable(event_buffer, sizeof(event_buffer), 32); +#endif + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + diff --git a/ports_smp/cortex_a9_smp/gnu/example_build/sample_threadx.ld b/ports_smp/cortex_a9_smp/gnu/example_build/sample_threadx.ld new file mode 100644 index 00000000..fb1ca03c --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/example_build/sample_threadx.ld @@ -0,0 +1,182 @@ +/* Linker script to place sections and symbol values. + * It references following symbols, which must be defined in code: + * Vectors : Entry point + * + * It defines following symbols, which code can use without definition: + * __code_start + * __exidx_start + * __exidx_end + * __data_start + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __bss_start__ + * __bss_end__ + * __end__ + * __stack + * __irq_stack + * __stack + * __pagetable_start + */ +ENTRY(Vectors) + +SECTIONS +{ + + .vectors 0x80008000: + { + _exec = .; + __code_start = .; + KEEP(*(VECTORS)) + } + + .init : + { + KEEP (*(SORT_NONE(.init))) + } + + .text : + { + KEEP(*(ENABLE_CACHES)) + *(.text*) + } + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } + + .rodata : + { + *(.rodata .rodata.* .gnu.linkonce.r.*) + } + + .eh_frame : + { + KEEP (*(.eh_frame)) + } + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } + + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array )) + PROVIDE_HIDDEN (__init_array_end = .); + } + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array )) + PROVIDE_HIDDEN (__fini_array_end = .); + } + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } + + .jcr : + { + KEEP (*(.jcr)) + } + + .data : + { + __data_start = . ; + *(.data .data.* .gnu.linkonce.d.*) + SORT(CONSTRUCTORS) + } + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } + + .heap (NOLOAD): + { + . = ALIGN(64); + __end__ = .; + PROVIDE(end = .); + . = . + 0xA0000; + } + + .stack (NOLOAD): + { + . = ALIGN(64); + . = . + 4 * 0x4000; + __stack = .; + _stack_init_usr = .; + } + + .irq_stacks (NOLOAD): + { + . = ALIGN(64); + . = . + 4 * 1024; + __irq_stack = .; + _stack_init_irq = .; + } + + _end = .; + + .pagetable 0x80100000 (NOLOAD): + { + _page_table_top = .; + __pagetable_start = .; + . = . + 0x4000; + } +} diff --git a/ports_smp/cortex_a9_smp/gnu/example_build/startup.S b/ports_smp/cortex_a9_smp/gnu/example_build/startup.S new file mode 100644 index 00000000..65b1ba90 --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/example_build/startup.S @@ -0,0 +1,690 @@ +@; ------------------------------------------------------------ +@; Cortex-A15 MPCore SMP Prime Number Generator Example +@; +@; Copyright (c) 2011-2012 ARM Ltd. All rights reserved. +@; ------------------------------------------------------------ +@ +@ PRESERVE8 +@ +@ AREA StartUp,CODE,READONLY +@ +@; Standard definitions of mode bits and interrupt (I&F) flags in PSRs +@ +Mode_USR = 0x10 +Mode_FIQ = 0x11 +Mode_IRQ = 0x12 +Mode_SVC = 0x13 +Mode_ABT = 0x17 +Mode_UNDEF = 0x1B +Mode_SYS = 0x1F + +I_Bit = 0x80 @ when I bit is set, IRQ is disabled +F_Bit = 0x40 @ when F bit is set, FIQ is disabled + +SYS_MODE = 0xDF +SVC_MODE = 0xD3 +IRQ_MODE = 0xD2 + +@; ------------------------------------------------------------ +@; Porting defines +@; ------------------------------------------------------------ +@ +L1_COHERENT = 0x00014c06 @ Template descriptor for coherent memory +L1_NONCOHERENT = 0x00000c1e @ Template descriptor for non-coherent memory +L1_DEVICE = 0x00000c06 @ Template descriptor for device memory + +.section VECTORS, "ax" +.align 3 +.cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + +@; ------------------------------------------------------------ +@ +@ ENTRY +@ + .global Vectors +Vectors: + B Reset_Handler + B Undefined_Handler + B SVC_Handler + B Prefetch_Handler + B Abort_Handler + B Hypervisor_Handler + B IRQ_Handler + B FIQ_Handler + +@; ------------------------------------------------------------ +@; Handlers for unused exceptions +@; ------------------------------------------------------------ +@ +Undefined_Handler: + B Undefined_Handler +SVC_Handler: + B SVC_Handler +Prefetch_Handler: + B Prefetch_Handler +Abort_Handler: + B Abort_Handler +Hypervisor_Handler: + B Hypervisor_Handler +FIQ_Handler: + B FIQ_Handler + +@; ------------------------------------------------------------ +@; Imports +@; ------------------------------------------------------------ + .global readIntAck + .global writeEOI + .global enableGIC + .global enableGICProcessorInterface + .global setPriorityMask + .global enableIntID + .global setIntPriority + .global joinSMP + + .global invalidateCaches + .global disableHighVecs + .global _start +@; [Grape Change Start] +@; IMPORT main_app + + .global _tx_thread_smp_initialize_wait + .global _tx_thread_smp_release_cores_flag + .global _tx_thread_context_save + .global _tx_thread_context_restore + .global _tx_timer_interrupt + .global _tx_thread_smp_inter_core_interrupts + + .global enableBranchPrediction + .global enableCaches + +VFPEnable = 0x40000000 @ VFP enable value + +@;/*------------------------------------------------------------------------*/ +@;/*--- Versatile Express(Timer0) ---*/ +GIC_DIST_CPUTARGET = 0x2C001820 +GIC_DIST_CPUTARGET_VALUE = 0x000f0000 + +GIC_DIST_CONFIG = 0x2C001C08 +GIC_DIST_CONFIG_VALUE = 0x00000000 + +GIC_DIST_PRIO = 0x2C001420 +GIC_DIST_PRIO_VALUE = 0x00a00000 + +GIC_DIST_CONTROL = 0x2C001000 +GIC_DIST_CONTROL_VALUE = 0x00000001 + +GIC_CPU_CONTROL = 0x2C002000 +GIC_CPU_CONTROL_VALUE = 0x00000001 + +GIC_CPU_PRIO_MASK = 0x2C002004 +GIC_CPU_PRIO_MASK_VALUE = 0x000000ff + +GIC_DIST_ENABLE_SET = 0x2C001104 +GIC_DIST_ENABLE_SET_VALUE = 0x00000004 + +GIC_CPU_INTACK = 0x2C00200C +GIC_CPU_EOI = 0x2C002010 +; +; +; +TIMCLK_CTRL = 0x1C020000 +TIMCLK_CTRL_VALUE = 0x00028000 @ Use EXTCLK (1MHz) for TIMCLK not REFCLK32KHZ + +TIMER_LOAD = 0x1C110000 +TIMER_LOAD_VALUE = 0x00000140 @ 10ms + +TIMER_CTRL = 0x1C110008 +TIMER_CTRL_STOP = 0x00000020 +TIMER_CTRL_VALUE = 0x000000E0 +TIMER_ACK = 34 @ Timer0 +TIMER_INT_CLR = 0x1C11000C +; +HANDLER_SET = 0x80000018 +HANDLER_SET_VALUE = 0xE59FF018 +HANDLER_ADDRESS = 0x80000038 @ irq + +@;/*--- Versatile Express(Timer0) ---*/ +@;/*------------------------------------------------------------------------*/ +@; [Grape Change End] + + .global _page_table_top + .global _exec + .global _stack_init_irq + .global _stack_init_usr + +@; ------------------------------------------------------------ +@; Interrupt Handler +@; ------------------------------------------------------------ +@ +@ EXPORT IRQ_Handler + .align 2 + .global IRQ_Handler + .type IRQ_Handler,function +IRQ_Handler: +@; [Grape Change Start] + .global __tx_irq_processing_return +@; SUB lr, lr, #4 ; Pre-adjust lr +@; SRSFD sp!, #Mode_IRQ ; Save lr and SPRS to IRQ mode stack +@; PUSH {r0-r4, r12} ; Save APCS corruptible registers to IRQ mode stack (and maintain 8 byte alignment) +@; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return: + PUSH {r4, r5} @ Save some preserved registers (r5 is saved just for 8-byte alignment) +@; [Grape Change End] + + @ Acknowledge the interrupt + BL readIntAck + MOV r4, r0 + + // + // This example only uses (and enables) one. At this point + // you would normally check the ID, and clear the source. + // + + // + // Additonal code to handler private timer interrupt on CPU0 + // + + CMP r0, #29 // If not Private Timer interrupt (ID 29), by pass + BNE by_pass + +// [EL Change Start] +// MOV r0, #0x04 // Code for SYS_WRITE0 +// LDR r1, =irq_handler_message0 +// SVC 0x123456 +// [EL Change End] + + // Clear timer interrupt + BL clear_private_timer_irq + DSB +// [EL Change Start] + BL _tx_timer_interrupt // Timer interrupt handler +// [EL Change End] + + B by_pass2 + +by_pass: + +// [EL Change Start] + // + // Additional code to handle SGI on CPU0 + // +// +// MRC p15, 0, r0, c0, c0, 5 // Read CPU ID register +// ANDS r0, r0, #0x03 // Mask off, leaving the CPU ID field +// BNE by_pass2 +// +// MOV r0, #0x04 // Code for SYS_WRITE0 +// LDR r1, =irq_handler_message1 +// SVC 0x123456 +// +// /* Just increment the per-thread interrupt count for analysis purposes. */ +// + MRC p15, 0, r0, c0, c0, 5 // Read CPU ID register + AND r0, r0, #0x03 // Mask off, leaving the CPU ID field + LSL r0, r0, #2 // Build offset to array indexes + LDR r1,=_tx_thread_smp_inter_core_interrupts // Pickup base address of core interrupt counter array + ADD r1, r1, r0 // Build array index + LDR r0, [r1] // Pickup counter + ADD r0, r0, #1 // Increment counter + STR r0, [r1] // Store back counter +// +// [EL Change End] + + +by_pass2: + // Write end of interrupt reg + MOV r0, r4 + BL writeEOI + +// [EL Change Start] + +// +// /* Jump to context restore to restore system context. */ + POP {r4, r5} // Recover preserved registers + B _tx_thread_context_restore + +// POP {r0-r4, r12} // Restore stacked APCS registers +// MOV r2, #0x01 // Set r2 so CPU leaves holding pen +// RFEFD sp! // Return from exception +// [EL Change End] + + + +@; ------------------------------------------------------------ +@; Reset Handler - Generic initialization, run by all CPUs +@; ------------------------------------------------------------ +@ +@ EXPORT Reset_Handler + .align 2 + .global $Reset_Handler + .type $Reset_Handler,function +Reset_Handler: + +@ ; +@ ; Set ACTLR.SMP bit +@ ; ------------------ + BL joinSMP + +@; +@; Disable caches, MMU and branch prediction in case they were left enabled from an earlier run +@; This does not need to be done from a cold reset +@; ------------------------------------------------------------ + MRC p15, 0, r0, c1, c0, 0 @ Read CP15 System Control register + BIC r0, r0, #(0x1 << 12) @ Clear I bit 12 to disable I Cache + BIC r0, r0, #(0x1 << 2) @ Clear C bit 2 to disable D Cache + BIC r0, r0, #0x1 @ Clear M bit 0 to disable MMU + BIC r0, r0, #(0x1 << 11) @ Clear Z bit 11 to disable branch prediction + MCR p15, 0, r0, c1, c0, 0 @ Write CP15 System Control register + +@; The MMU is enabled later, before calling main(). Caches and branch prediction are enabled inside main(), +@; after the MMU has been enabled and scatterloading has been performed. +@ +@ ; +@ ; Setup stacks +@ ;--------------- + + MRC p15, 0, r0, c0, c0, 5 @ Read CPU ID register + ANDS r0, r0, #0x03 @ Mask off, leaving the CPU ID field + +@; [Grape Change Start] +@; MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit +@; LDR r1, =_stack_init_irq ; IRQ stacks for CPU 0,1,2,3 +@; SUB r1, r1, r0, LSL #8 ; 256 bytes of IRQ stack per CPU (0,1,2,3) - see scatter.scat +@; MOV sp, r1 +@; +@; MSR CPSR_c, #Mode_SYS:OR:I_Bit:OR:F_Bit ; Interrupts initially disabled +@; LDR r1, =_stack_init_usr ; App stacks for all CPUs +@; SUB r1, r1, r0, LSL #12 ; 0x1000 bytes of App stack per CPU - see scatter.scat +@; MOV sp, r1 + + + MOV r1, #IRQ_MODE @ Build IRQ mode CPSR + MSR CPSR_c, r1 @ Enter IRQ mode +@ MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit + LDR r1, =_stack_init_irq @ IRQ stacks for CPU 0,1,2,3 + SUB r1, r1, r0, LSL #10 @ 1024 bytes of IRQ stack per CPU (0,1,2,3) - see scatter.scat + MOV sp, r1 + + MOV r1, #SYS_MODE @ Build SYS mode CPSR + MSR CPSR_c, r1 @ Enter SYS mode +@ MSR CPSR_c, #Mode_SYS:OR:I_Bit:OR:F_Bit @ Interrupts initially disabled + LDR r1, =_stack_init_usr @ App stacks for all CPUs + SUB r1, r1, r0, LSL #12 @ 0x1000 bytes of App stack per CPU - see scatter.scat + MOV sp, r1 + + MOV r2, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r2 @ Enter SVC mode +@ MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit @ Interrupts initially disabled + MOV sp, r1 +@; [Grape Change End] +@ +@ ; +@ ; Set vector base address +@ ; ------------------------ + LDR r0, =Vectors + MCR p15, 0, r0, c12, c0, 0 @ Write Secure or Non-secure Vector Base Address + BL disableHighVecs @ Ensure that V-bit is cleared + +@ ; +@ ; Invalidate caches +@ ; ------------------ + BL invalidateCaches + +@ ; +@ ; Clear Branch Prediction Array +@ ; ------------------------------ + MOV r0, #0x0 + MCR p15, 0, r0, c7, c5, 6 @ BPIALL - Invalidate entire branch predictor array + +@; [Grape Change Start] +@; ; Disable loop-buffer to fix errata on A15 r0p0 +@; MRC p15, 0, r0, c0, c0, 0 ; Read main ID register MIDR +@; MOV r1, r0, lsr #4 ; Extract Primary Part Number +@; LDR r2, =0xFFF +@; AND r1, r1, r2 +@; LDR r2, =0xC0F +@; CMP r1, r2 ; Is this an A15? +@; BNE notA15r0p0 ; Jump if not A15 +@; AND r5, r0, #0x00f00000 ; Variant +@; AND r6, r0, #0x0000000f ; Revision +@; ORRS r6, r6, r5 ; Combine variant and revision +@; BNE notA15r0p0 ; Jump if not r0p0 +@; MRC p15, 0, r0, c1, c0, 1 ; Read Aux Ctrl Reg +@; ORR r0, r0, #(1 << 1) ; Set bit 1 to Disable Loop Buffer +@; MCR p15, 0, r0, c1, c0, 1 ; Write Aux Ctrl Reg +@; ISB +@;notA15r0p0 +@; [Grape Change End] +@ +@ ; +@ ; Invalidate TLBs +@ ;------------------ + MOV r0, #0x0 + MCR p15, 0, r0, c8, c7, 0 @ TLBIALL - Invalidate entire Unified TLB + +@ ; +@ ; Set up Domain Access Control Reg +@ ; ---------------------------------- +@ ; b00 - No Access (abort) +@ ; b01 - Client (respect table entry) +@ ; b10 - RESERVED +@ ; b11 - Manager (ignore access permissions) + + MRC p15, 0, r0, c3, c0, 0 @ Read Domain Access Control Register + LDR r0, =0x55555555 @ Initialize every domain entry to b01 (client) + MCR p15, 0, r0, c3, c0, 0 @ Write Domain Access Control Register + +@ ;; +@ ;; Enable L1 Preloader - Auxiliary Control +@ ;; ----------------------------------------- +@ ;; Seems to undef on panda? +@ ;MRC p15, 0, r0, c1, c0, 1 ; Read ACTLR +@ ;ORR r0, r0, #0x4 +@ ;MCR p15, 0, r0, c1, c0, 1 ; Write ACTLR +@ +@ ; Page tables +@ ; ------------------------- +@ ; Each CPU will have its own L1 page table. The +@ ; code reads the base address from the scatter file +@ ; the uses the CPUID to calculate an offset for each +@ ; CPU. +@ ; +@ ; The page tables are generated at boot time. First +@ ; the table is zeroed. Then the individual valid +@ ; entries are written in +@ ; +@ +@ ; Calculate offset for this CPU + LDR r0, =_page_table_top + MRC p15, 0, r1, c0, c0, 5 @ Read Multiprocessor Affinity Register + ANDS r1, r1, #0x03 @ Mask off, leaving the CPU ID field + MOV r1, r1, LSL #14 @ Convert core ID into a 16K offset (this is the size of the table) + ADD r0, r1, r0 @ Add offset to current table location to get dst + + @ Fill table with zeros + MOV r2, #1024 @ Set r3 to loop count (4 entries per iteration, 1024 iterations) + MOV r1, r0 @ Make a copy of the base dst + MOV r3, #0 + MOV r4, #0 + MOV r5, #0 + MOV r6, #0 +ttb_zero_loop: + STMIA r1!, {r3-r6} @ Store out four entries + SUBS r2, r2, #1 @ Decrement counter + BNE ttb_zero_loop + +@ ; +@ ; STANDARD ENTRIES +@ ; +@ +@ ; Entry for VA 0x0 +@ ; This region must be coherent +@ ;LDR r1, =PABASE_VA0 ; Physical address +@ ;LDR r2, =L1_COHERENT ; Descriptor template +@ ;ORR r1, r1, r2 ; Combine address and template +@ ;STR r1, [r0] +@ +@ +@ ; If not flat mapping, you need a page table entry covering +@ ; the physical address of the boot code. +@ ; This region must be coherent + LDR r1,=_exec @ Base physical address of code segment + LSR r1,#20 @ Shift right to align to 1MB boundaries + LDR r3, =L1_COHERENT @ Descriptor template + ORR r3, r1, LSL#20 @ Setup the initial level1 descriptor again + STR r3, [r0, r1, LSL#2] @ str table entry + +@; [Grape Change Start] +@;/*------------------------------------------------------------------------*/ +@;/*--- Versatile Express(Timer0) ---*/ + LDR r1, =0x80000000 @ Physical address of HANDLER + LSR r1, r1, #20 @ Clear bottom 20 bits, to find which 1MB block it is in + LSL r2, r1, #2 @ Make a copy, and multiply by four. This gives offset into the page tables + LSL r1, r1, #20 @ Put back in address format + + LDR r3, =L1_COHERENT @ Descriptor template + ORR r1, r1, r3 @ Combine address and template + STR r1, [r0, r2] + + LDR r1, =0x2C000000 @ Physical address of GIC_DIST + LSR r1, r1, #20 @ Clear bottom 20 bits, to find which 1MB block it is in + LSL r2, r1, #2 @ Make a copy, and multiply by four. This gives offset into the page tables + LSL r1, r1, #20 @ Put back in address format + + LDR r3, =L1_DEVICE @ Descriptor template + ORR r1, r1, r3 @ Combine address and template + STR r1, [r0, r2] + + LDR r1, =0x1C000000 @ Physical address of TIMER + LSR r1, r1, #20 @ Clear bottom 20 bits, to find which 1MB block it is in + LSL r2, r1, #2 @ Make a copy, and multiply by four. This gives offset into the page tables + LSL r1, r1, #20 @ Put back in address format + + LDR r3, =L1_DEVICE @ Descriptor template + ORR r1, r1, r3 @ Combine address and template + STR r1, [r0, r2] + + LDR r1, =0x1C100000 @ Physical address of TIMER + LSR r1, r1, #20 @ Clear bottom 20 bits, to find which 1MB block it is in + LSL r2, r1, #2 @ Make a copy, and multiply by four. This gives offset into the page tables + LSL r1, r1, #20 @ Put back in address format + + LDR r3, =L1_DEVICE @ Descriptor template + ORR r1, r1, r3 @ Combine address and template + STR r1, [r0, r2] +@;/*--- Versatile Express(Timer0) ---*/ +@;/*------------------------------------------------------------------------*/ +@; [Grape Change End] +@ +@ ; Entry for private address space +@ ; Needs to be marked as Device memory + MRC p15, 4, r1, c15, c0, 0 @ Get base address of private address space + LSR r1, r1, #20 @ Clear bottom 20 bits, to find which 1MB block it is in + LSL r2, r1, #2 @ Make a copy, and multiply by four. This gives offset into the page tables + LSL r1, r1, #20 @ Put back in address format + + LDR r3, =L1_DEVICE @ Descriptor template + ORR r1, r1, r3 @ Combine address and template + STR r1, [r0, r2] + +@ ; +@ ; OPTIONAL ENTRIES +@ ; You will need additional translations if: +@ ; - No RAM at zero, so cannot use flat mapping +@ ; - You wish to retarget +@ ; +@ ; If you wish to output to stdio to a UART you will need +@ ; an additional entry +@ ;LDR r1, =PABASE_UART ; Physical address of UART +@ ;LSR r1, r1, #20 ; Mask off bottom 20 bits to find which 1MB it is within +@ ;LSL r2, r1, #2 ; Make a copy and multiply by 4 to get table offset +@ ;LSL r1, r1, #20 ; Put back into address format +@ ;LDR r3, =L1_DEVICE ; Descriptor template +@ ;ORR r1, r1, r3 ; Combine address and template +@ ;STR r1, [r0, r2] +@ +@ ; +@ ; Barrier +@ ; -------- + DSB + +@ ; +@ ; Set location of level 1 page table +@ ;------------------------------------ +@ ; 31:14 - Base addr: 0x8050,0000 (CPU0), 0x8050,4000 (CPU1) +@ ; 13:5 - 0x0 +@ ; 4:3 - RGN 0x0 (Outer Noncachable) +@ ; 2 - P 0x0 +@ ; 1 - S 0x0 (Non-shared) +@ ; 0 - C 0x0 (Inner Noncachable) + MCR p15, 0, r0, c2, c0 ,0 + + +@ ; Enable MMU +@ ;------------- +@ ; Leaving the caches disabled until after scatter loading. + MRC p15, 0, r0, c1, c0, 0 @ Read CP15 System Control register + BIC r0, r0, #(0x1 << 12) @ Clear I bit 12 to disable I Cache + BIC r0, r0, #(0x1 << 2) @ Clear C bit 2 to disable D Cache + BIC r0, r0, #0x2 @ Clear A bit 1 to disable strict alignment fault checking + ORR r0, r0, #0x1 @ Set M bit 0 to enable MMU before scatter loading + MCR p15, 0, r0, c1, c0, 0 @ Write CP15 System Control register + +@ ; +@ ; MMU now enabled - Virtual address system now active +@ ; +@; [Grape Change Start] +#ifdef TARGET_FPU_VFP + MRC p15, 0, r1, c1, c0, 2 @ r1 = Access Control Register + ORR r1, r1, #(0xf << 20) @ Enable full access for p10,11 + MCR p15, 0, r1, c1, c0, 2 @ Access Control Register = r1 + MOV r1, #0 + MCR p15, 0, r1, c7, c5, 4 @ Flush prefetch buffer because of FMXR below and + @ CP 10 & 11 were only just enabled + MOV r0, #VFPEnable @ Enable VFP itself + FMXR FPEXC, r0 @ FPEXC = r0 +#endif + + LDR r0, =_tx_thread_smp_release_cores_flag @ Build address of release cores flag + MOV r1, #0 + STR r1, [r0] +@; [Grape Change End] +@ +@ ; +@ ; SMP initialization +@ ; ------------------- + MRC p15, 0, r0, c0, c0, 5 @ Read CPU ID register + ANDS r0, r0, #0x03 @ Mask off, leaving the CPU ID field + BEQ primaryCPUInit + BNE secondaryCPUsInit + + + + +@; ------------------------------------------------------------ +@; Initialization for PRIMARY CPU +@; ------------------------------------------------------------ +@ +@ +@ EXPORT primaryCPUInit + .align 2 + .global primaryCPUInit + .type primaryCPUInit,function +primaryCPUInit: + +@ ; +@ ; GIC Init +@ ; --------- + BL enableGIC + BL enableGICProcessorInterface + + BL enableCaches + + // + // Enable Private Timer for periodic IRQ + // -------------------------------------- + MOV r0, #0x1F + BL setPriorityMask // Set priority mask (local) + + // [EL] Change start - don't enable interrupts here! + //CPSIE i // Clear CPSR I bit + // [EL] Change end + + // Enable the Private Timer Interrupt Source + MOV r0, #29 + MOV r1, #0 + BL enableIntID + + // Set the priority + MOV r0, #29 + MOV r1, #0 + BL setIntPriority + + // Configure Timer + MOV r0, #0xF0000 + MOV r1, #0x0 + BL init_private_timer + BL start_private_timer + + // + // Enable receipt of SGI 0 + // ------------------------ + MOV r0, #0x0 // ID + BL enableIntID + + MOV r0, #0x0 // ID + MOV r1, #0x0 // Priority + BL setIntPriority + +@ ; +@ ; Branch to C lib code +@ ; ---------------------- + B _start + +@; [Grape Change End] + + +@; ------------------------------------------------------------ +@; Initialization for SECONDARY CPUs +@; ------------------------------------------------------------ +@ +@ EXPORT secondaryCPUsInit + .align 2 + .global secondaryCPUsInit + .type secondaryCPUsInit,function +secondaryCPUsInit: + +@ ; +@ ; GIC Init +@ ; --------- + BL enableGICProcessorInterface + + MOV r0, #0x1F @ Priority + BL setPriorityMask + + MOV r0, #0x0 @ ID + BL enableIntID + + MOV r0, #0x0 @ ID + MOV r1, #0x0 @ Priority + BL setIntPriority + + +@ ; +@ ; Holding Pen +@ ; ------------ +@; [Grape Change Start] +@; MOV r2, #0x00 ; Clear r2 +@; CPSIE i ; Enable interrupts +@;holding_pen +@; CMP r2, #0x0 ; r2 will be set to 0x1 by IRQ handler on receiving SGI +@; WFIEQ +@; BEQ holding_pen +@; CPSID i ; IRQs not used in rest of example, so mask out interrupts +@; [Grape Change End] +@ +@ +@ ; +@ ; Branch to application +@ ; ---------------------- +@; [Grape Change Start] +@; B main_app + +@; BL enableBranchPrediction + BL enableCaches + + B _tx_thread_smp_initialize_wait +@; [Grape Change End] +@ + + +@; ------------------------------------------------------------ +@; End of code +@; ------------------------------------------------------------ +@ +@ END +@ +@; ------------------------------------------------------------ +@; End of startup.s +@; ------------------------------------------------------------ diff --git a/ports_smp/cortex_a9_smp/gnu/example_build/tx_initialize_low_level.S b/ports_smp/cortex_a9_smp/gnu/example_build/tx_initialize_low_level.S new file mode 100644 index 00000000..dc6fae8b --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/example_build/tx_initialize_low_level.S @@ -0,0 +1,118 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Initialize */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_initialize.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ +@ +@ + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global _tx_version_id + .global _tx_build_options + .global _end +@ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_initialize_low_level SMP/Cortex-A9/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for any low-level processor */ +@/* initialization, including setting up interrupt vectors, setting */ +@/* up a periodic timer interrupt source, saving the system stack */ +@/* pointer for use in ISR processing later, and finding the first */ +@/* available RAM memory address for tx_application_define. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_initialize_low_level(VOID) +@{ + .global _tx_initialize_low_level + .type _tx_initialize_low_level,function +_tx_initialize_low_level: +@ +@ /* Save the first available memory address. */ +@ _tx_initialize_unused_memory = (VOID_PTR) _end; +@ + LDR r0, =_end @ Get end of non-initialized RAM area + LDR r2, =_tx_initialize_unused_memory @ Pickup unused memory ptr address + ADD r0, r0, #8 @ Increment to next free word + STR r0, [r2, #0] @ Save first free memory address +@ +@ + +@ /* Done, return to caller. */ +@ +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} +@ +BUILD_OPTIONS: + .word _tx_build_options @ Reference to bring in +VERSION_ID: + .word _tx_version_id @ Reference to bring in + + diff --git a/ports_smp/cortex_a9_smp/gnu/example_build/v7.S b/ports_smp/cortex_a9_smp/gnu/example_build/v7.S new file mode 100644 index 00000000..67ddb163 --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/example_build/v7.S @@ -0,0 +1,531 @@ +// ------------------------------------------------------------ +// v7-A Cache and Branch Prediction Maintenance Operations +// +// Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + + .text + .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + + +// ------------------------------------------------------------ +// Interrupt enable/disable +// ------------------------------------------------------------ + + // Could use compiler intrinsics instead of these + + .global enableInterrupts + // void enableInterrupts(void) + .type enableInterrupts, "function" + .cfi_startproc +enableInterrupts: + CPSIE i + BX lr + .cfi_endproc + + + .global disableInterrupts + // void disableInterrupts(void) + .type disableInterrupts, "function" + .cfi_startproc +disableInterrupts: + CPSID i + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ +// Cache Maintenance +// ------------------------------------------------------------ + + .global enableCaches + // void enableCaches(void) + .type enableCaches, "function" + .cfi_startproc +enableCaches: + MRC p15, 0, r0, c1, c0, 0 // Read System Control Register + ORR r0, r0, #(1 << 2) // Set C bit + ORR r0, r0, #(1 << 12) // Set I bit + MCR p15, 0, r0, c1, c0, 0 // Write System Control Register + ISB + BX lr + .cfi_endproc + + + + .global disableCaches + // void disableCaches(void) + .type disableCaches, "function" + .cfi_startproc +disableCaches: + MRC p15, 0, r0, c1, c0, 0 // Read System Control Register + BIC r0, r0, #(1 << 2) // Clear C bit + BIC r0, r0, #(1 << 12) // Clear I bit + MCR p15, 0, r0, c1, c0, 0 // Write System Control Register + ISB + BX lr + .cfi_endproc + + + + .global cleanDCache + // void cleanDCache(void) + .type cleanDCache, "function" + .cfi_startproc +cleanDCache: + PUSH {r4-r12} + + // + // Based on code example given in section 11.2.4 of Armv7-A/R Architecture Reference Manual (DDI 0406B) + // + + MRC p15, 1, r0, c0, c0, 1 // Read CLIDR + ANDS r3, r0, #0x7000000 + MOV r3, r3, LSR #23 // Cache level value (naturally aligned) + BEQ clean_dcache_finished + MOV r10, #0 + +clean_dcache_loop1: + ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel + MOV r1, r0, LSR r2 // bottom 3 bits are the Cache type for this level + AND r1, r1, #7 // get those 3 bits alone + CMP r1, #2 + BLT clean_dcache_skip // no cache or only instruction cache at this level + MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register + ISB // ISB to sync the change to the CacheSizeID reg + MRC p15, 1, r1, c0, c0, 0 // reads current Cache Size ID register + AND r2, r1, #7 // extract the line length field + ADD r2, r2, #4 // add 4 for the line length offset (log2 16 bytes) + LDR r4, =0x3FF + ANDS r4, r4, r1, LSR #3 // R4 is the max number on the way size (right aligned) + CLZ r5, r4 // R5 is the bit position of the way size increment + LDR r7, =0x00007FFF + ANDS r7, r7, r1, LSR #13 // R7 is the max number of the index size (right aligned) + +clean_dcache_loop2: + MOV r9, R4 // R9 working copy of the max way size (right aligned) + +clean_dcache_loop3: + ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11 + ORR r11, r11, r7, LSL r2 // factor in the index number + MCR p15, 0, r11, c7, c10, 2 // DCCSW - clean by set/way + SUBS r9, r9, #1 // decrement the way number + BGE clean_dcache_loop3 + SUBS r7, r7, #1 // decrement the index + BGE clean_dcache_loop2 + +clean_dcache_skip: + ADD r10, r10, #2 // increment the cache number + CMP r3, r10 + BGT clean_dcache_loop1 + +clean_dcache_finished: + POP {r4-r12} + + BX lr + .cfi_endproc + + + .global cleanInvalidateDCache + // void cleanInvalidateDCache(void) + .type cleanInvalidateDCache, "function" + .cfi_startproc +cleanInvalidateDCache: + PUSH {r4-r12} + + // + // Based on code example given in section 11.2.4 of Armv7-A/R Architecture Reference Manual (DDI 0406B) + // + + MRC p15, 1, r0, c0, c0, 1 // Read CLIDR + ANDS r3, r0, #0x7000000 + MOV r3, r3, LSR #23 // Cache level value (naturally aligned) + BEQ clean_invalidate_dcache_finished + MOV r10, #0 + +clean_invalidate_dcache_loop1: + ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel + MOV r1, r0, LSR r2 // bottom 3 bits are the Cache type for this level + AND r1, r1, #7 // get those 3 bits alone + CMP r1, #2 + BLT clean_invalidate_dcache_skip // no cache or only instruction cache at this level + MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register + ISB // ISB to sync the change to the CacheSizeID reg + MRC p15, 1, r1, c0, c0, 0 // reads current Cache Size ID register + AND r2, r1, #7 // extract the line length field + ADD r2, r2, #4 // add 4 for the line length offset (log2 16 bytes) + LDR r4, =0x3FF + ANDS r4, r4, r1, LSR #3 // R4 is the max number on the way size (right aligned) + CLZ r5, r4 // R5 is the bit position of the way size increment + LDR r7, =0x00007FFF + ANDS r7, r7, r1, LSR #13 // R7 is the max number of the index size (right aligned) + +clean_invalidate_dcache_loop2: + MOV r9, R4 // R9 working copy of the max way size (right aligned) + +clean_invalidate_dcache_loop3: + ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11 + ORR r11, r11, r7, LSL r2 // factor in the index number + MCR p15, 0, r11, c7, c14, 2 // DCCISW - clean and invalidate by set/way + SUBS r9, r9, #1 // decrement the way number + BGE clean_invalidate_dcache_loop3 + SUBS r7, r7, #1 // decrement the index + BGE clean_invalidate_dcache_loop2 + +clean_invalidate_dcache_skip: + ADD r10, r10, #2 // increment the cache number + CMP r3, r10 + BGT clean_invalidate_dcache_loop1 + +clean_invalidate_dcache_finished: + POP {r4-r12} + + BX lr + .cfi_endproc + + + + .global invalidateCaches + // void invalidateCaches(void) + .type invalidateCaches, "function" + .cfi_startproc +invalidateCaches: + PUSH {r4-r12} + + // + // Based on code example given in section B2.2.4/11.2.4 of Armv7-A/R Architecture Reference Manual (DDI 0406B) + // + + MOV r0, #0 + MCR p15, 0, r0, c7, c5, 0 // ICIALLU - Invalidate entire I Cache, and flushes branch target cache + + MRC p15, 1, r0, c0, c0, 1 // Read CLIDR + ANDS r3, r0, #0x7000000 + MOV r3, r3, LSR #23 // Cache level value (naturally aligned) + BEQ invalidate_caches_finished + MOV r10, #0 + +invalidate_caches_loop1: + ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel + MOV r1, r0, LSR r2 // bottom 3 bits are the Cache type for this level + AND r1, r1, #7 // get those 3 bits alone + CMP r1, #2 + BLT invalidate_caches_skip // no cache or only instruction cache at this level + MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register + ISB // ISB to sync the change to the CacheSizeID reg + MRC p15, 1, r1, c0, c0, 0 // reads current Cache Size ID register + AND r2, r1, #7 // extract the line length field + ADD r2, r2, #4 // add 4 for the line length offset (log2 16 bytes) + LDR r4, =0x3FF + ANDS r4, r4, r1, LSR #3 // R4 is the max number on the way size (right aligned) + CLZ r5, r4 // R5 is the bit position of the way size increment + LDR r7, =0x00007FFF + ANDS r7, r7, r1, LSR #13 // R7 is the max number of the index size (right aligned) + +invalidate_caches_loop2: + MOV r9, R4 // R9 working copy of the max way size (right aligned) + +invalidate_caches_loop3: + ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11 + ORR r11, r11, r7, LSL r2 // factor in the index number + MCR p15, 0, r11, c7, c6, 2 // DCISW - invalidate by set/way + SUBS r9, r9, #1 // decrement the way number + BGE invalidate_caches_loop3 + SUBS r7, r7, #1 // decrement the index + BGE invalidate_caches_loop2 + +invalidate_caches_skip: + ADD r10, r10, #2 // increment the cache number + CMP r3, r10 + BGT invalidate_caches_loop1 + +invalidate_caches_finished: + POP {r4-r12} + BX lr + .cfi_endproc + + + + .global invalidateCaches_IS + // void invalidateCaches_IS(void) + .type invalidateCaches_IS, "function" + .cfi_startproc +invalidateCaches_IS: + PUSH {r4-r12} + + MOV r0, #0 + MCR p15, 0, r0, c7, c1, 0 // ICIALLUIS - Invalidate entire I Cache inner shareable + + MRC p15, 1, r0, c0, c0, 1 // Read CLIDR + ANDS r3, r0, #0x7000000 + MOV r3, r3, LSR #23 // Cache level value (naturally aligned) + BEQ invalidate_caches_is_finished + MOV r10, #0 + +invalidate_caches_is_loop1: + ADD r2, r10, r10, LSR #1 // Work out 3xcachelevel + MOV r1, r0, LSR r2 // bottom 3 bits are the Cache type for this level + AND r1, r1, #7 // get those 3 bits alone + CMP r1, #2 + BLT invalidate_caches_is_skip // no cache or only instruction cache at this level + MCR p15, 2, r10, c0, c0, 0 // write the Cache Size selection register + ISB // ISB to sync the change to the CacheSizeID reg + MRC p15, 1, r1, c0, c0, 0 // reads current Cache Size ID register + AND r2, r1, #7 // extract the line length field + ADD r2, r2, #4 // add 4 for the line length offset (log2 16 bytes) + LDR r4, =0x3FF + ANDS r4, r4, r1, LSR #3 // R4 is the max number on the way size (right aligned) + CLZ r5, r4 // R5 is the bit position of the way size increment + LDR r7, =0x00007FFF + ANDS r7, r7, r1, LSR #13 // R7 is the max number of the index size (right aligned) + +invalidate_caches_is_loop2: + MOV r9, R4 // R9 working copy of the max way size (right aligned) + +invalidate_caches_is_loop3: + ORR r11, r10, r9, LSL r5 // factor in the way number and cache number into R11 + ORR r11, r11, r7, LSL r2 // factor in the index number + MCR p15, 0, r11, c7, c6, 2 // DCISW - clean by set/way + SUBS r9, r9, #1 // decrement the way number + BGE invalidate_caches_is_loop3 + SUBS r7, r7, #1 // decrement the index + BGE invalidate_caches_is_loop2 + +invalidate_caches_is_skip: + ADD r10, r10, #2 // increment the cache number + CMP r3, r10 + BGT invalidate_caches_is_loop1 + +invalidate_caches_is_finished: + POP {r4-r12} + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ +// TLB +// ------------------------------------------------------------ + + .global invalidateUnifiedTLB + // void invalidateUnifiedTLB(void) + .type invalidateUnifiedTLB, "function" + .cfi_startproc +invalidateUnifiedTLB: + MOV r0, #0 + MCR p15, 0, r0, c8, c7, 0 // TLBIALL - Invalidate entire unified TLB + BX lr + .cfi_endproc + + + .global invalidateUnifiedTLB_IS + // void invalidateUnifiedTLB_IS(void) + .type invalidateUnifiedTLB_IS, "function" + .cfi_startproc +invalidateUnifiedTLB_IS: + MOV r0, #1 + MCR p15, 0, r0, c8, c3, 0 // TLBIALLIS - Invalidate entire unified TLB Inner Shareable + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ +// Branch Prediction +// ------------------------------------------------------------ + + .global flushBranchTargetCache + // void flushBranchTargetCache(void) + .type flushBranchTargetCache, "function" + .cfi_startproc +flushBranchTargetCache: + MOV r0, #0 + MCR p15, 0, r0, c7, c5, 6 // BPIALL - Invalidate entire branch predictor array + BX lr + .cfi_endproc + + + .global flushBranchTargetCache_IS + // void flushBranchTargetCache_IS(void) + .type flushBranchTargetCache_IS, "function" + .cfi_startproc +flushBranchTargetCache_IS: + MOV r0, #0 + MCR p15, 0, r0, c7, c1, 6 // BPIALLIS - Invalidate entire branch predictor array Inner Shareable + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ +// High Vecs +// ------------------------------------------------------------ + + .global enableHighVecs + // void enableHighVecs(void) + .type enableHighVecs, "function" + .cfi_startproc +enableHighVecs: + MRC p15, 0, r0, c1, c0, 0 // Read Control Register + ORR r0, r0, #(1 << 13) // Set the V bit (bit 13) + MCR p15, 0, r0, c1, c0, 0 // Write Control Register + ISB + BX lr + .cfi_endproc + + + .global disableHighVecs + // void disable_highvecs(void) + .type disableHighVecs, "function" + .cfi_startproc +disableHighVecs: + MRC p15, 0, r0, c1, c0, 0 // Read Control Register + BIC r0, r0, #(1 << 13) // Clear the V bit (bit 13) + MCR p15, 0, r0, c1, c0, 0 // Write Control Register + ISB + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ +// Context ID +// ------------------------------------------------------------ + + .global getContextID + // uint32_t getContextIDd(void) + .type getContextID, "function" + .cfi_startproc +getContextID: + MRC p15, 0, r0, c13, c0, 1 // Read Context ID Register + BX lr + .cfi_endproc + + + .global setContextID + // void setContextID(uint32_t) + .type setContextID, "function" + .cfi_startproc +setContextID: + MCR p15, 0, r0, c13, c0, 1 // Write Context ID Register + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ +// ID registers +// ------------------------------------------------------------ + + .global getMIDR + // uint32_t getMIDR(void) + .type getMIDR, "function" + .cfi_startproc +getMIDR: + MRC p15, 0, r0, c0, c0, 0 // Read Main ID Register (MIDR) + BX lr + .cfi_endproc + + + .global getMPIDR + // uint32_t getMPIDR(void) + .type getMPIDR, "function" + .cfi_startproc +getMPIDR: + MRC p15, 0, r0, c0 ,c0, 5 // Read Multiprocessor ID register (MPIDR) + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ +// CP15 SMP related +// ------------------------------------------------------------ + + .global getBaseAddr + // uint32_t getBaseAddr(void) + // Returns the value CBAR (base address of the private peripheral memory space) + .type getBaseAddr, "function" + .cfi_startproc +getBaseAddr: + MRC p15, 4, r0, c15, c0, 0 // Read peripheral base address + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global getCPUID + // uint32_t getCPUID(void) + // Returns the CPU ID (0 to 3) of the CPU executed on + .type getCPUID, "function" + .cfi_startproc +getCPUID: + MRC p15, 0, r0, c0, c0, 5 // Read CPU ID register + AND r0, r0, #0x03 // Mask off, leaving the CPU ID field + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global goToSleep + // void goToSleep(void) + .type goToSleep, "function" + .cfi_startproc +goToSleep: + DSB // Clear all pending data accesses + WFI // Go into standby + B goToSleep // Catch in case of rogue events + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global joinSMP + // void joinSMP(void) + // Sets the ACTRL.SMP bit + .type joinSMP, "function" + .cfi_startproc +joinSMP: + + // SMP status is controlled by bit 6 of the CP15 Aux Ctrl Reg + + MRC p15, 0, r0, c1, c0, 1 // Read ACTLR + MOV r1, r0 + ORR r0, r0, #0x040 // Set bit 6 + CMP r0, r1 + MCRNE p15, 0, r0, c1, c0, 1 // Write ACTLR + ISB + + BX lr + .cfi_endproc + + +// ------------------------------------------------------------ + + .global leaveSMP + // void leaveSMP(void) + // Clear the ACTRL.SMP bit + .type leaveSMP, "function" + .cfi_startproc +leaveSMP: + + // SMP status is controlled by bit 6 of the CP15 Aux Ctrl Reg + + MRC p15, 0, r0, c1, c0, 1 // Read ACTLR + BIC r0, r0, #0x040 // Clear bit 6 + MCR p15, 0, r0, c1, c0, 1 // Write ACTLR + ISB + + BX lr + .cfi_endproc + + .align 2 + .global _exit + .type _exit,function +_exit: + BX lr + + +// ------------------------------------------------------------ +// End of v7.s +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a9_smp/gnu/example_build/v7.h b/ports_smp/cortex_a9_smp/gnu/example_build/v7.h new file mode 100644 index 00000000..5a08b43f --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/example_build/v7.h @@ -0,0 +1,155 @@ +// ------------------------------------------------------------ +// v7-A Cache, TLB and Branch Prediction Maintenance Operations +// Header File +// +// Copyright (c) 2011-2016 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#ifndef _ARMV7A_GENERIC_H +#define _ARMV7A_GENERIC_H + +// ------------------------------------------------------------ +// Memory barrier mnemonics +enum MemBarOpt { + RESERVED_0 = 0, RESERVED_1 = 1, OSHST = 2, OSH = 3, + RESERVED_4 = 4, RESERVED_5 = 5, NSHST = 6, NSH = 7, + RESERVED_8 = 8, RESERVED_9 = 9, ISHST = 10, ISH = 11, + RESERVED_12 = 12, RESERVED_13 = 13, ST = 14, SY = 15 +}; + +// +// Note: +// *_IS() stands for "inner shareable" +// DO NOT USE THESE FUNCTIONS ON A CORTEX-A8 +// + +// ------------------------------------------------------------ +// Interrupts +// Enable/disables IRQs (not FIQs) +void enableInterrupts(void); +void disableInterrupts(void); + +// ------------------------------------------------------------ +// Caches + +void invalidateCaches_IS(void); +void cleanInvalidateDCache(void); +void invalidateCaches_IS(void); +void enableCaches(void); +void disableCaches(void); +void invalidateCaches(void); +void cleanDCache(void); + +// ------------------------------------------------------------ +// TLBs + +void invalidateUnifiedTLB(void); +void invalidateUnifiedTLB_IS(void); + +// ------------------------------------------------------------ +// Branch prediction + +void flushBranchTargetCache(void); +void flushBranchTargetCache_IS(void); + +// ------------------------------------------------------------ +// High Vecs + +void enableHighVecs(void); +void disableHighVecs(void); + +// ------------------------------------------------------------ +// ID Registers + +unsigned int getMIDR(void); + +#define MIDR_IMPL_SHIFT 24 +#define MIDR_IMPL_MASK 0xFF +#define MIDR_VAR_SHIFT 20 +#define MIDR_VAR_MASK 0xF +#define MIDR_ARCH_SHIFT 16 +#define MIDR_ARCH_MASK 0xF +#define MIDR_PART_SHIFT 4 +#define MIDR_PART_MASK 0xFFF +#define MIDR_REV_SHIFT 0 +#define MIDR_REV_MASK 0xF + +// tmp = get_MIDR(); +// implementor = (tmp >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; +// variant = (tmp >> MIDR_VAR_SHIFT) & MIDR_VAR_MASK; +// architecture= (tmp >> MIDR_ARCH_SHIFT) & MIDR_ARCH_MASK; +// part_number = (tmp >> MIDR_PART_SHIFT) & MIDR_PART_MASK; +// revision = tmp & MIDR_REV_MASK; + +#define MIDR_PART_CA5 0xC05 +#define MIDR_PART_CA8 0xC08 +#define MIDR_PART_CA9 0xC09 + +unsigned int getMPIDR(void); + +#define MPIDR_FORMAT_SHIFT 31 +#define MPIDR_FORMAT_MASK 0x1 +#define MPIDR_UBIT_SHIFT 30 +#define MPIDR_UBIT_MASK 0x1 +#define MPIDR_CLUSTER_SHIFT 7 +#define MPIDR_CLUSTER_MASK 0xF +#define MPIDR_CPUID_SHIFT 0 +#define MPIDR_CPUID_MASK 0x3 + +#define MPIDR_CPUID_CPU0 0x0 +#define MPIDR_CPUID_CPU1 0x1 +#define MPIDR_CPUID_CPU2 0x2 +#define MPIDR_CPUID_CPU3 0x3 + +#define MPIDR_UNIPROCESSPR 0x1 + +#define MPDIR_NEW_FORMAT 0x1 + +// ------------------------------------------------------------ +// Context ID + +unsigned int getContextID(void); + +void setContextID(unsigned int); + +#define CONTEXTID_ASID_SHIFT 0 +#define CONTEXTID_ASID_MASK 0xFF +#define CONTEXTID_PROCID_SHIFT 8 +#define CONTEXTID_PROCID_MASK 0x00FFFFFF + +// tmp = getContextID(); +// ASID = tmp & CONTEXTID_ASID_MASK; +// PROCID = (tmp >> CONTEXTID_PROCID_SHIFT) & CONTEXTID_PROCID_MASK; + +// ------------------------------------------------------------ +// SMP related for Armv7-A MPCore processors +// +// DO NOT CALL THESE FUNCTIONS ON A CORTEX-A8 + +// Returns the base address of the private peripheral memory space +unsigned int getBaseAddr(void); + +// Returns the CPU ID (0 to 3) of the CPU executed on +#define MP_CPU0 (0) +#define MP_CPU1 (1) +#define MP_CPU2 (2) +#define MP_CPU3 (3) +unsigned int getCPUID(void); + +// Set this core as participating in SMP +void joinSMP(void); + +// Set this core as NOT participating in SMP +void leaveSMP(void); + +// Go to sleep, never returns +void goToSleep(void); + +#endif + +// ------------------------------------------------------------ +// End of v7.h +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a9_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a9_smp/gnu/inc/tx_port.h new file mode 100644 index 00000000..ab3f9cf9 --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/inc/tx_port.h @@ -0,0 +1,404 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h SMP/Cortex-A9/GNU */ +/* 6.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/************* Define ThreadX SMP constants. *************/ + +/* Define the ThreadX SMP maximum number of cores. */ + +#ifndef TX_THREAD_SMP_MAX_CORES +#define TX_THREAD_SMP_MAX_CORES 4 +#endif + + +/* Define the ThreadX SMP core mask. */ + +#ifndef TX_THREAD_SMP_CORE_MASK +#define TX_THREAD_SMP_CORE_MASK 0xf /* Where bit 0 represents Core 0, bit 1 represents Core 1, etc. */ +#endif + + +/* Define ThreadX SMP initialization macro. */ + +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION + + +/* Define ThreadX SMP pre-scheduler initialization. */ + +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION + + +/* Enable the inter-core interrupt logic. */ + +#define TX_THREAD_SMP_INTER_CORE_INTERRUPT + + +/* Determine if there is customer-specific wakeup logic needed. */ + +#ifdef TX_THREAD_SMP_WAKEUP_LOGIC + +/* Include customer-specific wakeup code. */ + +#include "tx_thread_smp_core_wakeup.h" +#else + +#ifdef TX_THREAD_SMP_DEFAULT_WAKEUP_LOGIC + +/* Default wakeup code. */ +#define TX_THREAD_SMP_WAKEUP_LOGIC +#define TX_THREAD_SMP_WAKEUP(i) _tx_thread_smp_core_preempt(i) +#endif +#endif + + +/* Ensure that the in-line resume/suspend define is not allowed. */ + +#ifdef TX_INLINE_THREAD_RESUME_SUSPEND +#undef TX_INLINE_THREAD_RESUME_SUSPEND +#endif + + +/************* End ThreadX SMP constants. *************/ + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE _tx_thread_smp_time_get() +#endif +#else +#ifndef TX_TRACE_TIME_SOURCE +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#if __TARGET_ARCH_ARM > 4 + +#ifndef __thumb__ + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + asm volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); \ + b = 31 - b; +#endif +#endif +#endif + + +/************* Define ThreadX SMP data types and function prototypes. *************/ + +struct TX_THREAD_STRUCT; + + +/* Define the ThreadX SMP protection structure. */ + +typedef struct TX_THREAD_SMP_PROTECT_STRUCT +{ + ULONG tx_thread_smp_protect_in_force; + struct TX_THREAD_STRUCT * + tx_thread_smp_protect_thread; + ULONG tx_thread_smp_protect_core; + ULONG tx_thread_smp_protect_count; + + /* Implementation specific information follows. */ + + ULONG tx_thread_smp_protect_get_caller; + ULONG tx_thread_smp_protect_sr; + ULONG tx_thread_smp_protect_release_caller; +} TX_THREAD_SMP_PROTECT; + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_smp_protect(); +#define TX_RESTORE _tx_thread_smp_unprotect(interrupt_save); + + +/************* End ThreadX SMP data type and function prototype definitions. *************/ + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define VFP extension for the Cortex-A9. Each is assumed to be called in the context of the executing + thread. */ + +void tx_thread_vfp_enable(void); +void tx_thread_vfp_disable(void); + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Cortex-A9/GNU Version Version 6.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + + + diff --git a/ports_smp/cortex_a9_smp/gnu/readme_threadx.txt b/ports_smp/cortex_a9_smp/gnu/readme_threadx.txt new file mode 100644 index 00000000..26131c9b --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/readme_threadx.txt @@ -0,0 +1,238 @@ + Microsoft's Azure RTOS ThreadX SMP for Cortex-A9 + + Using the GNU Tools + +1. Building the ThreadX run-time Library + +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the GNU +development environment. + +At this point you may run the build_threadx.bat batch file. This will build the +ThreadX run-time environment in the "example_build" directory. + +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your +application in order to use ThreadX. + + +2. Demonstration System + +The ThreadX demonstration is designed to execute under the ARM Cortex-A9x4 FVP. + +Building the demonstration is easy; simply execute the build_threadx_sample.bat +batch file while inside the "example_build" directory. + +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with TX.A. The resulting file DEMO is a binary file +that can be downloaded and executed. + + +3. System Initialization + +The entry point in ThreadX for the Cortex-A9 using GNU tools is at label +Reset_Handler in startup.s. After the basic core initialization is complete, +control will transfer to __main, which is where all static and global pre-set +C variable initialization processing takes place. + +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. By default, the vector area is defined to be located in the Init area, +which is defined at the top of tx_initialize_low_level.s. This area is typically +located at 0. In situations where this is impossible, the vectors at the beginning +of the Init area should be copied to address 0. + +This is also where initialization of a periodic timer interrupt source +should take place. + +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input +parameter to your application definition function, tx_application_define. + + +4. Register Usage and Stack Frames + +The GNU compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread +is only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 CPSR CPSR + 0x08 r0 (a1) r4 (v1) + 0x0C r1 (a2) r5 (v2) + 0x10 r2 (a3) r6 (v3) + 0x14 r3 (a4) r7 (v4) + 0x18 r4 (v1) r8 (v5) + 0x1C r5 (v2) r9 (v6) + 0x20 r6 (v3) r10 (v7) + 0x24 r7 (v4) r11 (fp) + 0x28 r8 (v5) r14 (lr) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) + 0x3C r14 (lr) + 0x40 PC + + +5. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the build_threadx.bat file to +remove the -g option and enable all compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +6. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-A9 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +6.1 Vector Area + +The Cortex-A9 vectors start at address zero. The demonstration system startup +Init area contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. + + +6.2 IRQ ISRs + +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested +IRQ interrupts. The following sub-sections define the IRQ capabilities. + + +6.2.1 Standard IRQ ISRs + +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +is the default IRQ handler defined in tx_initialize_low_level.s: + + EXPORT __tx_irq_handler + EXPORT __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save ; Jump to the context save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Application ISR call(s) go here! */ +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +6.3 FIQ Interrupts + +By default, Cortex-A9 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made +from default FIQ ISRs, which is located in tx_initialize_low_level.s. + + +6.3.1 Managed FIQ Interrupts + +Full ThreadX management of FIQ interrupts is provided if the ThreadX sources +are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built +this way, the FIQ interrupt handlers are very similar to the IRQ interrupt +handlers defined previously. The following is default FIQ handler +defined in tx_initialize_low_level.s: + + + EXPORT __tx_fiq_handler + EXPORT __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Application FIQ handlers can be called here! */ +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +7. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional. However, all other +ThreadX services are operational without a periodic timer source. + +To add the timer interrupt processing, simply make a call to +_tx_timer_interrupt in the IRQ processing. An example of this can be +found in the file tx_initialize_low_level.s in the Integrator sub-directories. + + +8. Thumb/Cortex-A9 Mixed Mode + +By default, ThreadX is setup for running in Cortex-A9 32-bit mode. This is +also true for the demonstration system. It is possible to build any +ThreadX file and/or the application in Thumb mode. If any Thumb code +is used the entire ThreadX source- both C and assembly - should be built +with the "-apcs /interwork" option. + + +9. VFP Support + +By default, VFP support is disabled for each thread. If saving the context of the VFP registers +is needed, the following API call must be made from the context of the application thread - before +the VFP usage: + +void tx_thread_vfp_enable(void); + +After this API is called in the application, VFP registers will be saved/restored for this thread if it +is preempted via an interrupt. All other suspension of the this thread will not require the VFP registers +to be saved/restored. + +To disable VFP register context saving, simply call the following API: + +void tx_thread_vfp_disable(void); + + +10. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +09-30-2020 Initial ThreadX 6.1 version for Cortex-A9 using GNU tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_context_restore.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_context_restore.S new file mode 100644 index 00000000..a8abb27a --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_context_restore.S @@ -0,0 +1,372 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@/* Include macros for modifying the wait list. */ +#include "tx_thread_smp_protection_wait_list_macros.h" + +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS = 0xC0 @ Disable IRQ & FIQ interrupts +IRQ_MODE = 0xD2 @ IRQ mode +SVC_MODE = 0xD3 @ SVC mode +#else +DISABLE_INTS = 0x80 @ Disable IRQ interrupts +IRQ_MODE = 0x92 @ IRQ mode +SVC_MODE = 0x93 @ SVC mode +#endif +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable + .global _tx_timer_interrupt_active + .global _tx_thread_smp_protection + .global _tx_thread_smp_protect_wait_counts + .global _tx_thread_smp_protect_wait_list + .global _tx_thread_smp_protect_wait_list_lock_protect_in_force + .global _tx_thread_smp_protect_wait_list_tail + .global _tx_thread_smp_protect_wait_list_size +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + .global _tx_execution_isr_exit +#endif +@ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_restore SMP/Cortex-A9/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function restores the interrupt context if it is processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs Interrupt Service Routines */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_restore(VOID) +@{ + .global _tx_thread_context_restore + .type _tx_thread_context_restore,function +_tx_thread_context_restore: +@ +@ /* Lockout interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR exit function to indicate an ISR is complete. */ +@ + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif + +@ /* Pickup the CPU ID. */ +@ + MRC p15, 0, r10, c0, c0, 5 @ Read CPU ID register + AND r10, r10, #0x03 @ Mask off, leaving the CPU ID field + LSL r12, r10, #2 @ Build offset to array indexes +@ +@ /* Determine if interrupts are nested. */ +@ if (--_tx_thread_system_state[core]) +@ { +@ + LDR r3, =_tx_thread_system_state @ Pickup address of system state var + ADD r3, r3, r12 @ Build array offset + LDR r2, [r3, #0] @ Pickup system state + SUB r2, r2, #1 @ Decrement the counter + STR r2, [r3, #0] @ Store the counter + CMP r2, #0 @ Was this the first interrupt? + BEQ __tx_thread_not_nested_restore @ If so, not a nested restore +@ +@ /* Interrupts are nested. */ +@ +@ /* Just recover the saved registers and return to the point of +@ interrupt. */ +@ + LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +__tx_thread_not_nested_restore: +@ +@ /* Determine if a thread was interrupted and no preemption is required. */ +@ else if (((_tx_thread_current_ptr[core]) && (_tx_thread_current_ptr[core] == _tx_thread_execute_ptr[core]) +@ || (_tx_thread_preempt_disable)) +@ { +@ + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + ADD r1, r1, r12 @ Build index to this core's current thread ptr + LDR r0, [r1, #0] @ Pickup actual current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_restore @ Yes, idle system was interrupted + + LDR r3, =_tx_thread_smp_protection @ Get address of protection structure + LDR r2, [r3, #8] @ Pickup owning core + CMP r2, r10 @ Is the owning core the same as the protected core? + BNE __tx_thread_skip_preempt_check @ No, skip the preempt disable check since this is only valid for the owning core + + LDR r3, =_tx_thread_preempt_disable @ Pickup preempt disable address + LDR r2, [r3, #0] @ Pickup actual preempt disable flag + CMP r2, #0 @ Is it set? + BNE __tx_thread_no_preempt_restore @ Yes, don't preempt this thread +__tx_thread_skip_preempt_check: + + LDR r3, =_tx_thread_execute_ptr @ Pickup address of execute thread ptr + ADD r3, r3, r12 @ Build index to this core's execute thread ptr + LDR r2, [r3, #0] @ Pickup actual execute thread pointer + CMP r0, r2 @ Is the same thread highest priority? + BNE __tx_thread_preempt_restore @ No, preemption needs to happen +@ +@ +__tx_thread_no_preempt_restore: +@ +@ /* Restore interrupted thread or ISR. */ +@ +@ /* Pickup the saved stack pointer. */ +@ tmp_ptr = _tx_thread_current_ptr[core] -> tx_thread_stack_ptr; +@ +@ /* Recover the saved context and return to the point of interrupt. */ +@ + LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +@ else +@ { +@ +__tx_thread_preempt_restore: +@ +@ /* Was the thread being preempted waiting for the lock? */ +@ if (_tx_thread_smp_protect_wait_counts[this_core] != 0) +@ { +@ + LDR r1, =_tx_thread_smp_protect_wait_counts @ Load waiting count list + LDR r2, [r1, r10, LSL #2] @ Load waiting value for this core + CMP r2, #0 + BEQ _nobody_waiting_for_lock @ Is the core waiting for the lock? +@ +@ /* Do we not have the lock? This means the ISR never got the inter-core lock. */ +@ if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core) +@ { +@ + LDR r1, =_tx_thread_smp_protection @ Load address of protection structure + LDR r2, [r1, #8] @ Pickup the owning core + CMP r10, r2 @ Compare our core to the owning core + BEQ _this_core_has_lock @ Do we have the lock? +@ +@ /* We don't have the lock. This core should be in the list. Remove it. */ +@ _tx_thread_smp_protect_wait_list_remove(this_core); +@ + MOV r0, r10 @ Move the core ID to r0 for the macro + _tx_thread_smp_protect_wait_list_remove @ Call macro to remove core from the list + B _nobody_waiting_for_lock @ Leave +@ +@ } +@ else +@ { +@ /* We have the lock. This means the ISR got the inter-core lock, but +@ never released it because it saw that there was someone waiting. +@ Note this core is not in the list. */ +@ +_this_core_has_lock: +@ +@ /* We're no longer waiting. Note that this should be zero since this happens during thread preemption. */ +@ _tx_thread_smp_protect_wait_counts[core]--; +@ + LDR r1, =_tx_thread_smp_protect_wait_counts @ Load waiting count list + LDR r2, [r1, r10, LSL #2] @ Load waiting value for this core + SUB r2, r2, #1 @ Decrement waiting value. Should be zero now + STR r2, [r1, r10, LSL #2] @ Store new waiting value +@ +@ /* Now release the inter-core lock. */ +@ +@ /* Set protected core as invalid. */ +@ _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF; +@ + LDR r1, =_tx_thread_smp_protection @ Load address of protection structure + MOV r2, #0xFFFFFFFF @ Build invalid value + STR r2, [r1, #8] @ Mark the protected core as invalid + DMB @ Ensure that accesses to shared resource have completed +@ +@ /* Release protection. */ +@ _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0; +@ + MOV r2, #0 @ Build release protection value + STR r2, [r1, #0] @ Release the protection + DSB ISH @ To ensure update of the protection occurs before other CPUs awake +@ +@ /* Wake up waiting processors. Note interrupts are already enabled. */ +@ +#ifdef TX_ENABLE_WFE + SEV @ Send event to other CPUs +#endif +@ +@ } +@ } +@ + +_nobody_waiting_for_lock: + + LDMIA sp!, {r3, r10, r12, lr} @ Recover temporarily saved registers + MOV r1, lr @ Save lr (point of interrupt) + MOV r2, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r2 @ Enter SVC mode + STR r1, [sp, #-4]! @ Save point of interrupt + STMDB sp!, {r4-r12, lr} @ Save upper half of registers + MOV r4, r3 @ Save SPSR in r4 + MOV r2, #IRQ_MODE @ Build IRQ mode CPSR + MSR CPSR_c, r2 @ Enter IRQ mode + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOV r5, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r5 @ Enter SVC mode + STMDB sp!, {r0-r3} @ Save r0-r3 on thread's stack + + MRC p15, 0, r10, c0, c0, 5 @ Read CPU ID register + AND r10, r10, #0x03 @ Mask off, leaving the CPU ID field + LSL r12, r10, #2 @ Build offset to array indexes + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + ADD r1, r1, r12 @ Build index to current thread ptr + LDR r0, [r1, #0] @ Pickup current thread pointer + +#ifdef TARGET_FPU_VFP + LDR r2, [r0, #160] @ Pickup the VFP enabled flag + CMP r2, #0 @ Is the VFP enabled? + BEQ _tx_skip_irq_vfp_save @ No, skip VFP IRQ save + VMRS r2, FPSCR @ Pickup the FPSCR + STR r2, [sp, #-4]! @ Save FPSCR + VSTMDB sp!, {D16-D31} @ Save D16-D31 + VSTMDB sp!, {D0-D15} @ Save D0-D15 +_tx_skip_irq_vfp_save: +#endif + + MOV r3, #1 @ Build interrupt stack type + STMDB sp!, {r3, r4} @ Save interrupt stack type and SPSR + STR sp, [r0, #8] @ Save stack pointer in thread control + @ block +@ +@ /* Save the remaining time-slice and disable it. */ +@ if (_tx_timer_time_slice[core]) +@ { +@ + LDR r3, =_tx_timer_interrupt_active @ Pickup timer interrupt active flag's address +_tx_wait_for_timer_to_finish: + LDR r2, [r3, #0] @ Pickup timer interrupt active flag + CMP r2, #0 @ Is the timer interrupt active? + BNE _tx_wait_for_timer_to_finish @ If timer interrupt is active, wait until it completes + + LDR r3, =_tx_timer_time_slice @ Pickup time-slice variable address + ADD r3, r3, r12 @ Build index to core's time slice + LDR r2, [r3, #0] @ Pickup time-slice + CMP r2, #0 @ Is it active? + BEQ __tx_thread_dont_save_ts @ No, don't save it +@ +@ _tx_thread_current_ptr[core] -> tx_thread_time_slice = _tx_timer_time_slice[core]; +@ _tx_timer_time_slice[core] = 0; +@ + STR r2, [r0, #24] @ Save thread's time-slice + MOV r2, #0 @ Clear value + STR r2, [r3, #0] @ Disable global time-slice flag +@ +@ } +__tx_thread_dont_save_ts: +@ +@ +@ /* Clear the current task pointer. */ +@ _tx_thread_current_ptr[core] = TX_NULL; +@ + MOV r2, #0 @ NULL value + STR r2, [r1, #0] @ Clear current thread pointer +@ +@ /* Set bit indicating this thread is ready for execution. */ +@ + LDR r2, [r0, #152] @ Pickup the ready bit + ORR r2, r2, #0x8000 @ Set ready bit (bit 15) + STR r2, [r0, #152] @ Make this thread ready for executing again + DMB @ Ensure that accesses to shared resource have completed +@ +@ /* Return to the scheduler. */ +@ _tx_thread_schedule(); +@ + B _tx_thread_schedule @ Return to scheduler +@ } +@ +__tx_thread_idle_system_restore: +@ +@ /* Just return back to the scheduler! */ +@ + MOV r3, #SVC_MODE @ Build SVC mode with interrupts disabled + MSR CPSR_c, r3 @ Change to SVC mode + B _tx_thread_schedule @ Return to scheduler +@} +@ + diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_context_save.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_context_save.S new file mode 100644 index 00000000..ba59c30e --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_context_save.S @@ -0,0 +1,204 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global __tx_irq_processing_return +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + .global _tx_execution_isr_enter +#endif +@ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_save SMP/Cortex-A9/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_save(VOID) +@{ + .global _tx_thread_context_save + .type _tx_thread_context_save,function +_tx_thread_context_save: +@ +@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +@ out, we are in IRQ mode, and all registers are intact. */ +@ +@ /* Check for a nested interrupt condition. */ +@ if (_tx_thread_system_state[core]++) +@ { +@ + STMDB sp!, {r0-r3} @ Save some working registers +@ +@ /* Save the rest of the scratch registers on the stack and return to the +@ calling ISR. */ +@ + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} @ Store other registers +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable FIQ interrupts +#endif +@ +@ /* Pickup the CPU ID. */ +@ + MRC p15, 0, r10, c0, c0, 5 @ Read CPU ID register + AND r10, r10, #0x03 @ Mask off, leaving the CPU ID field + LSL r12, r10, #2 @ Build offset to array indexes +@ + LDR r3, =_tx_thread_system_state @ Pickup address of system state var + ADD r3, r3, r12 @ Build index into the system state array + LDR r2, [r3, #0] @ Pickup system state + CMP r2, #0 @ Is this the first interrupt? + BEQ __tx_thread_not_nested_save @ Yes, not a nested context save +@ +@ /* Nested interrupt condition. */ +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3, #0] @ Store it back in the variable +@ +@ /* Return to the ISR. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {r12, lr} @ Save ISR lr & r12 + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {r12, lr} @ Recover ISR lr & r12 +#endif + + B __tx_irq_processing_return @ Continue IRQ processing +@ +__tx_thread_not_nested_save: +@ } +@ +@ /* Otherwise, not nested, check to see if a thread was running. */ +@ else if (_tx_thread_current_ptr[core]) +@ { +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3, #0] @ Store it back in the variable + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + ADD r1, r1, r12 @ Build index into current thread ptr + LDR r0, [r1, #0] @ Pickup current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + @ scheduling loop - nothing needs saving! +@ +@ /* Save the current stack pointer in the thread's control block. */ +@ _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; +@ +@ /* Switch to the system stack. */ +@ sp = _tx_thread_system_stack_ptr; +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {r12, lr} @ Save ISR lr & r12 + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {r12, lr} @ Recover ISR lr & r12 +#endif + + B __tx_irq_processing_return @ Continue IRQ processing +@ +@ } +@ else +@ { +@ +__tx_thread_idle_system_save: +@ +@ /* Interrupt occurred in the scheduling loop. */ +@ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ processing. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {r12, lr} @ Save ISR lr & r12 + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {r12, lr} @ Recover ISR lr & r12 +#endif + + ADD sp, sp, #32 @ Recover saved registers + B __tx_irq_processing_return @ Continue IRQ processing +@ +@ } +@} +@ + diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..dc47995c --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_interrupt_control.S @@ -0,0 +1,104 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT +INT_MASK = 0xC0 @ Interrupt bit mask +#else +INT_MASK = 0x80 @ Interrupt bit mask +#endif +@ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_control SMP/Cortex-A9/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for changing the interrupt lockout */ +@/* posture of the system. */ +@/* */ +@/* INPUT */ +@/* */ +@/* new_posture New interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_control(UINT new_posture) +@{ + .global _tx_thread_interrupt_control + .type _tx_thread_interrupt_control,function +_tx_thread_interrupt_control: +@ +@ /* Pickup current interrupt lockout posture. */ +@ + MRS r3, CPSR @ Pickup current CPSR + BIC r1, r3, #INT_MASK @ Clear interrupt lockout bits + ORR r1, r1, r0 @ Or-in new interrupt lockout bits +@ +@ /* Apply the new interrupt posture. */ +@ + MSR CPSR_c, r1 @ Setup new CPSR + AND r0, r3, #INT_MASK @ Return previous interrupt mask +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@ +@} +@ + diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_interrupt_disable.S new file mode 100644 index 00000000..da48dacc --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_interrupt_disable.S @@ -0,0 +1,97 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_disable SMP/Cortex-A9/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for disabling interrupts */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_disable(void) +@{ + .global _tx_thread_interrupt_disable + .type _tx_thread_interrupt_disable,function +_tx_thread_interrupt_disable: +@ +@ /* Pickup current interrupt lockout posture. */ +@ + MRS r0, CPSR @ Pickup current CPSR +@ +@ /* Mask interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ +#else + CPSID i @ Disable IRQ +#endif + +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} +@ + diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_interrupt_restore.S new file mode 100644 index 00000000..387cb83a --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_interrupt_restore.S @@ -0,0 +1,89 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_restore SMP/Cortex-A9/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for restoring interrupts to the state */ +@/* returned by a previous _tx_thread_interrupt_disable call. */ +@/* */ +@/* INPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_restore(UINT old_posture) +@{ + .global _tx_thread_interrupt_restore + .type _tx_thread_interrupt_restore,function +_tx_thread_interrupt_restore: +@ +@ /* Apply the new interrupt posture. */ +@ + MSR CPSR_c, r0 @ Setup new CPSR +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} +@ + diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_irq_nesting_end.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_irq_nesting_end.S new file mode 100644 index 00000000..ecd0fd3c --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_irq_nesting_end.S @@ -0,0 +1,112 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS = 0xC0 @ Disable IRQ & FIQ interrupts +#else +DISABLE_INTS = 0x80 @ Disable IRQ interrupts +#endif +MODE_MASK = 0x1F @ Mode mask +IRQ_MODE_BITS = 0x12 @ IRQ mode bits +@ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_end SMP/Cortex-A9/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +@/* processing from system mode back to IRQ mode prior to the ISR */ +@/* calling _tx_thread_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_irq_nesting_end(VOID) +@{ + .global _tx_thread_irq_nesting_end + .type _tx_thread_irq_nesting_end,function +_tx_thread_irq_nesting_end: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value + MSR CPSR_c, r0 @ Disable interrupts + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + @ 8-byte alignment logic) + BIC r0, r0, #MODE_MASK @ Clear mode bits + ORR r0, r0, #IRQ_MODE_BITS @ Build IRQ mode CPSR + MSR CPSR_c, r0 @ Re-enter IRQ mode +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_irq_nesting_start.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_irq_nesting_start.S new file mode 100644 index 00000000..df87ff87 --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_irq_nesting_start.S @@ -0,0 +1,106 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +IRQ_DISABLE = 0x80 @ IRQ disable bit +MODE_MASK = 0x1F @ Mode mask +SYS_MODE_BITS = 0x1F @ System mode bits +@ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_start SMP/Cortex-A9/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_context_save has been called and switches the IRQ */ +@/* processing to the system mode so nested IRQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_irq_nesting_start(VOID) +@{ + .global _tx_thread_irq_nesting_start + .type _tx_thread_irq_nesting_start,function +_tx_thread_irq_nesting_start: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + BIC r0, r0, #MODE_MASK @ Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS @ Build system mode CPSR + MSR CPSR_c, r0 @ Enter system mode + STMDB sp!, {r1, lr} @ Push the system mode lr on the system mode stack + @ and push r1 just to keep 8-byte alignment + BIC r0, r0, #IRQ_DISABLE @ Build enable IRQ CPSR + MSR CPSR_c, r0 @ Enter system mode +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} +@ + diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_schedule.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_schedule.S new file mode 100644 index 00000000..1c5f63c3 --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_schedule.S @@ -0,0 +1,315 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_execute_ptr + .global _tx_thread_current_ptr + .global _tx_timer_time_slice +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + .global _tx_execution_thread_enter +#endif +@ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_schedule SMP/Cortex-A9/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function waits for a thread control block pointer to appear in */ +@/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +@/* in the variable, the corresponding thread is resumed. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* _tx_thread_system_return Return to system from thread */ +@/* _tx_thread_context_restore Restore thread's context */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_schedule(VOID) +@{ + .global _tx_thread_schedule + .type _tx_thread_schedule,function +_tx_thread_schedule: +@ +@ /* Enable interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSIE if @ Enable IRQ and FIQ interrupts +#else + CPSIE i @ Enable IRQ interrupts +#endif +@ +@ /* Pickup the CPU ID. */ +@ + MRC p15, 0, r10, c0, c0, 5 @ Read CPU ID register + AND r10, r10, #0x03 @ Mask off, leaving the CPU ID field + LSL r12, r10, #2 @ Build offset to array indexes + + LDR r1, =_tx_thread_execute_ptr @ Address of thread execute ptr + ADD r1, r1, r12 @ Build offset to execute ptr for this core +@ +@ /* Lockout interrupts transfer control to it. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif +@ +@ /* Wait for a thread to execute. */ +@ do +@ { +@ +@ + LDR r0, [r1, #0] @ Pickup next thread to execute + CMP r0, #0 @ Is it NULL? + BEQ _tx_thread_schedule @ If so, keep looking for a thread +@ +@ } +@ while(_tx_thread_execute_ptr[core] == TX_NULL); +@ +@ /* Get the lock for accessing the thread's ready bit. */ +@ + MOV r2, #172 @ Build offset to the lock + ADD r2, r0, r2 @ Get the address to the lock + LDREX r3, [r2] @ Pickup the lock value + CMP r3, #0 @ Check if it's available + BNE _tx_thread_schedule @ No, lock not available + MOV r3, #1 @ Build the lock set value + STREX r4, r3, [r2] @ Try to get the lock + CMP r4, #0 @ Check if we got the lock + BNE _tx_thread_schedule @ No, another core got it first + DMB @ Ensure write to lock completes +@ +@ /* Now make sure the thread's ready bit is set. */ +@ + LDR r3, [r0, #152] @ Pickup the thread ready bit + AND r4, r3, #0x8000 @ Isolate the ready bit + CMP r4, #0 @ Is it set? + BNE _tx_thread_ready_for_execution @ Yes, schedule the thread +@ +@ /* The ready bit isn't set. Release the lock and jump back to the scheduler. */ +@ + MOV r3, #0 @ Build clear value + STR r3, [r2] @ Release the lock + DMB @ Ensure write to lock completes + B _tx_thread_schedule @ Jump back to the scheduler +@ +_tx_thread_ready_for_execution: +@ +@ /* We have a thread to execute. */ +@ +@ /* Clear the ready bit and release the lock. */ +@ + BIC r3, r3, #0x8000 @ Clear ready bit + STR r3, [r0, #152] @ Store it back in the thread control block + DMB + MOV r3, #0 @ Build clear value for the lock + STR r3, [r2] @ Release the lock + DMB +@ +@ /* Setup the current thread pointer. */ +@ _tx_thread_current_ptr[core] = _tx_thread_execute_ptr[core]; +@ + LDR r2, =_tx_thread_current_ptr @ Pickup address of current thread + ADD r2, r2, r12 @ Build index into the current thread array + STR r0, [r2, #0] @ Setup current thread pointer +@ +@ /* In the time between reading the execute pointer and assigning +@ it to the current pointer, the execute pointer was changed by +@ some external code. If the current pointer was still null when +@ the external code checked if a core preempt was necessary, then +@ it wouldn't have done it and a preemption will be missed. To +@ handle this, undo some things and jump back to the scheduler so +@ it can schedule the new thread. */ +@ + LDR r1, [r1, #0] @ Reload the execute pointer + CMP r0, r1 @ Did it change? + BEQ _execute_pointer_did_not_change @ If not, skip handling + + MOV r1, #0 @ Build clear value + STR r1, [r2, #0] @ Clear current thread pointer + + LDR r1, [r0, #152] @ Pickup the ready bit + ORR r1, r1, #0x8000 @ Set ready bit (bit 15) + STR r1, [r0, #152] @ Make this thread ready for executing again + DMB @ Ensure that accesses to shared resource have completed + + B _tx_thread_schedule @ Jump back to the scheduler to schedule the new thread + +_execute_pointer_did_not_change: +@ +@ /* Increment the run count for this thread. */ +@ _tx_thread_current_ptr[core] -> tx_thread_run_count++; +@ + LDR r2, [r0, #4] @ Pickup run counter + LDR r3, [r0, #24] @ Pickup time-slice for this thread + ADD r2, r2, #1 @ Increment thread run-counter + STR r2, [r0, #4] @ Store the new run counter +@ +@ /* Setup time-slice, if present. */ +@ _tx_timer_time_slice[core] = _tx_thread_current_ptr[core] -> tx_thread_time_slice; +@ + LDR r2, =_tx_timer_time_slice @ Pickup address of time slice + @ variable + ADD r2, r2, r12 @ Build index into the time-slice array + LDR sp, [r0, #8] @ Switch stack pointers + STR r3, [r2, #0] @ Setup time-slice +@ +@ /* Switch to the thread's stack. */ +@ sp = _tx_thread_execute_ptr[core] -> tx_thread_stack_ptr; +@ +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the thread entry function to indicate the thread is executing. */ +@ + MOV r5, r0 @ Save r0 + BL _tx_execution_thread_enter @ Call the thread execution enter function + MOV r0, r5 @ Restore r0 +#endif +@ +@ /* Determine if an interrupt frame or a synchronous task suspension frame +@ is present. */ +@ + LDMIA sp!, {r4, r5} @ Pickup the stack type and saved CPSR + CMP r4, #0 @ Check for synchronous context switch + BEQ _tx_solicited_return + MSR SPSR_cxsf, r5 @ Setup SPSR for return +#ifdef TARGET_FPU_VFP + LDR r1, [r0, #160] @ Pickup the VFP enabled flag + CMP r1, #0 @ Is the VFP enabled? + BEQ _tx_skip_interrupt_vfp_restore @ No, skip VFP interrupt restore + VLDMIA sp!, {D0-D15} @ Recover D0-D15 + VLDMIA sp!, {D16-D31} @ Recover D16-D31 + LDR r4, [sp], #4 @ Pickup FPSCR + VMSR FPSCR, r4 @ Restore FPSCR +_tx_skip_interrupt_vfp_restore: +#endif + LDMIA sp!, {r0-r12, lr, pc}^ @ Return to point of thread interrupt + +_tx_solicited_return: +#ifdef TARGET_FPU_VFP + MSR CPSR_cxsf, r5 @ Recover CPSR + LDR r1, [r0, #160] @ Pickup the VFP enabled flag + CMP r1, #0 @ Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_restore @ No, skip VFP solicited restore + VLDMIA sp!, {D8-D15} @ Recover D8-D15 + VLDMIA sp!, {D16-D31} @ Recover D16-D31 + LDR r4, [sp], #4 @ Pickup FPSCR + VMSR FPSCR, r4 @ Restore FPSCR +_tx_skip_solicited_vfp_restore: +#endif + MSR CPSR_cxsf, r5 @ Recover CPSR + LDMIA sp!, {r4-r11, lr} @ Return to thread synchronously + BX lr @ Return to caller +@ +@} +@ + +#ifdef TARGET_FPU_VFP + .global tx_thread_vfp_enable +tx_thread_vfp_enable: + MRS r2, CPSR @ Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif + MRC p15, 0, r1, c0, c0, 5 @ Read CPU ID register + AND r1, r1, #0x03 @ Mask off, leaving the CPU ID field + LSL r1, r1, #2 @ Build offset to array indexes + LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address + ADD r0, r0, r1 @ Build index into the current thread array + LDR r1, [r0] @ Pickup current thread pointer + CMP r1, #0 @ Check for NULL thread pointer + BEQ __tx_no_thread_to_enable @ If NULL, skip VFP enable + MOV r0, #1 @ Build enable value + STR r0, [r1, #160] @ Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_enable: + MSR CPSR_cxsf, r2 @ Recover CPSR + BX LR @ Return to caller + + .global tx_thread_vfp_disable +tx_thread_vfp_disable: + MRS r2, CPSR @ Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif + MRC p15, 0, r1, c0, c0, 5 @ Read CPU ID register + AND r1, r1, #0x03 @ Mask off, leaving the CPU ID field + LSL r1, r1, #2 @ Build offset to array indexes + LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address + ADD r0, r0, r1 @ Build index into the current thread array + LDR r1, [r0] @ Pickup current thread pointer + CMP r1, #0 @ Check for NULL thread pointer + BEQ __tx_no_thread_to_disable @ If NULL, skip VFP disable + MOV r0, #0 @ Build disable value + STR r0, [r1, #160] @ Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_disable: + MSR CPSR_cxsf, r2 @ Recover CPSR + BX LR @ Return to caller +#endif +@ +@} +@ + diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_core_get.S new file mode 100644 index 00000000..75b37b94 --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_core_get.S @@ -0,0 +1,86 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread - Low Level SMP Support */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@#define TX_THREAD_SMP_SOURCE_CODE +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" */ +@ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_core_get SMP/Cortex-A9/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function gets the currently running core number and returns it.*/ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* Core ID */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Source */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ + .global _tx_thread_smp_core_get + .type _tx_thread_smp_core_get,function +_tx_thread_smp_core_get: + MRC p15, 0, r0, c0, c0, 5 @ Read CPU ID register + AND r0, r0, #0x03 @ Mask off, leaving the CPU ID field + +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif + + diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_core_preempt.S new file mode 100644 index 00000000..99fe91c6 --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_core_preempt.S @@ -0,0 +1,102 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread - Low Level SMP Support */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@#define TX_THREAD_SMP_SOURCE_CODE +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" */ +@ +@ + .global sendSGI + + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_core_preempt SMP/Cortex-A9/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function preempts the specified core in situations where the */ +@/* thread corresponding to this core is no longer ready or when the */ +@/* core must be used for a higher-priority thread. If the specified is */ +@/* the current core, this processing is skipped since the will give up */ +@/* control subsequently on its own. */ +@/* */ +@/* INPUT */ +@/* */ +@/* core The core to preempt */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Source */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ + .global _tx_thread_smp_core_preempt + .type _tx_thread_smp_core_preempt,function +_tx_thread_smp_core_preempt: + + STMDB sp!, {r4, lr} @ Save the lr and r4 register on the stack +@ +@ /* Place call to send inter-processor interrupt here! */ +@ + DSB @ + MOV r1, #1 @ Build parameter list + LSL r1, r1, r0 @ + MOV r0, #0 @ + MOV r2, #0 @ + BL sendSGI @ Make call to send inter-processor interrupt + + LDMIA sp!, {r4, lr} @ Recover lr register and r4 +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif + + diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_current_state_get.S new file mode 100644 index 00000000..4dfc815d --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_current_state_get.S @@ -0,0 +1,104 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread - Low Level SMP Support */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@#define TX_THREAD_SMP_SOURCE_CODE +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" */ +@ +@ + .global _tx_thread_system_state + + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_current_state_get SMP/Cortex-A9/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is gets the current state of the calling core. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Components */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ + .global _tx_thread_smp_current_state_get + .type _tx_thread_smp_current_state_get,function +_tx_thread_smp_current_state_get: + + MRS r3, CPSR @ Pickup current CPSR + +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif +@ +@ /* Pickup the CPU ID. */ +@ + MRC p15, 0, r2, c0, c0, 5 @ Read CPU ID register + AND r2, r2, #0x03 @ Mask off, leaving the CPU ID field + LSL r2, r2, #2 @ Build offset to array indexes + + LDR r1, =_tx_thread_system_state @ Pickup start of the current state array + ADD r1, r1, r2 @ Build index into the current state array + LDR r0, [r1] @ Pickup state for this core + MSR CPSR_c, r3 @ Restore CPSR +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif + + diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_current_thread_get.S new file mode 100644 index 00000000..d8d974a3 --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_current_thread_get.S @@ -0,0 +1,104 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread - Low Level SMP Support */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@#define TX_THREAD_SMP_SOURCE_CODE +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" */ +@ +@ + .global _tx_thread_current_ptr + + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_current_thread_get SMP/Cortex-A9/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is gets the current thread of the calling core. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Components */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ + .global _tx_thread_smp_current_thread_get + .type _tx_thread_smp_current_thread_get,function +_tx_thread_smp_current_thread_get: + + MRS r3, CPSR @ Pickup current CPSR + +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif +@ +@ /* Pickup the CPU ID. */ +@ + MRC p15, 0, r2, c0, c0, 5 @ Read CPU ID register + AND r2, r2, #0x03 @ Mask off, leaving the CPU ID field + LSL r2, r2, #2 @ Build offset to array indexes + + LDR r1, =_tx_thread_current_ptr @ Pickup start of the current thread array + ADD r1, r1, r2 @ Build index into the current thread array + LDR r0, [r1] @ Pickup current thread for this core + MSR CPSR_c, r3 @ Restore CPSR +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif + + diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_initialize_wait.S new file mode 100644 index 00000000..cb6f3294 --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_initialize_wait.S @@ -0,0 +1,141 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread - Low Level SMP Support */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@#define TX_THREAD_SMP_SOURCE_CODE +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" */ +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_smp_release_cores_flag + .global _tx_thread_schedule + + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_initialize_wait SMP/Cortex-A9/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is the place where additional cores wait until */ +@/* initialization is complete before they enter the thread scheduling */ +@/* loop. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling loop */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Hardware */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ + .global _tx_thread_smp_initialize_wait + .type _tx_thread_smp_initialize_wait,function +_tx_thread_smp_initialize_wait: + +@ /* Lockout interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif +@ +@ /* Pickup the CPU ID. */ +@ + MRC p15, 0, r10, c0, c0, 5 @ Read CPU ID register + AND r10, r10, #0x03 @ Mask off, leaving the CPU ID field + LSL r10, r10, #2 @ Build offset to array indexes +@ +@ /* Make sure the system state for this core is TX_INITIALIZE_IN_PROGRESS before we check the release +@ flag. */ +@ + LDR r3, =_tx_thread_system_state @ Build address of system state variable + ADD r3, r3, r10 @ Build index into the system state array + LDR r2, =0xF0F0F0F0 @ Build TX_INITIALIZE_IN_PROGRESS flag +wait_for_initialize: + LDR r1, [r3] @ Pickup system state + CMP r1, r2 @ Has initialization completed? + BNE wait_for_initialize @ If different, wait here! +@ +@ /* Pickup the release cores flag. */ +@ + LDR r2, =_tx_thread_smp_release_cores_flag @ Build address of release cores flag + +wait_for_release: + LDR r3, [r2] @ Pickup the flag + CMP r3, #0 @ Is it set? + BEQ wait_for_release @ Wait for the flag to be set +@ +@ /* Core 0 has released this core. */ +@ +@ /* Clear this core's system state variable. */ +@ + LDR r3, =_tx_thread_system_state @ Build address of system state variable + ADD r3, r3, r10 @ Build index into the system state array + MOV r0, #0 @ Build clear value + STR r0, [r3] @ Clear this core's entry in the system state array +@ +@ /* Now wait for core 0 to finish it's initialization. */ +@ + LDR r3, =_tx_thread_system_state @ Build address of system state variable of logical 0 + +core_0_wait_loop: + LDR r2, [r3] @ Pickup system state for core 0 + CMP r2, #0 @ Is it 0? + BNE core_0_wait_loop @ No, keep waiting for core 0 to finish its initialization +@ +@ /* Initialize is complete, enter the scheduling loop! */ +@ + B _tx_thread_schedule @ Enter scheduling loop for this core! + + diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_low_level_initialize.S new file mode 100644 index 00000000..2cd7263b --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_low_level_initialize.S @@ -0,0 +1,85 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread - Low Level SMP Support */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@#define TX_THREAD_SMP_SOURCE_CODE +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" */ +@ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_low_level_initialize SMP/Cortex-A9/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function performs low-level initialization of the booting */ +@/* core. */ +@/* */ +@/* INPUT */ +@/* */ +@/* number_of_cores Number of cores */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_high_level ThreadX high-level init */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ + .global _tx_thread_smp_low_level_initialize + .type _tx_thread_smp_low_level_initialize,function +_tx_thread_smp_low_level_initialize: + +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif + + diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_protect.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_protect.S new file mode 100644 index 00000000..5fa53975 --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_protect.S @@ -0,0 +1,373 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread - Low Level SMP Support */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@#define TX_THREAD_SMP_SOURCE_CODE +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + +@/* Include macros for modifying the wait list. */ +#include "tx_thread_smp_protection_wait_list_macros.h" + + .global _tx_thread_current_ptr + .global _tx_thread_smp_protection + .global _tx_thread_smp_protect_wait_counts + .global _tx_thread_smp_protect_wait_list + .global _tx_thread_smp_protect_wait_list_lock_protect_in_force + .global _tx_thread_smp_protect_wait_list_head + .global _tx_thread_smp_protect_wait_list_tail + .global _tx_thread_smp_protect_wait_list_size + + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_protect SMP/Cortex-A9/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function gets protection for running inside the ThreadX */ +@/* source. This is acomplished by a combination of a test-and-set */ +@/* flag and periodically disabling interrupts. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* Previous Status Register */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Source */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ + .global _tx_thread_smp_protect + .type _tx_thread_smp_protect,function +_tx_thread_smp_protect: +@VOID _tx_thread_smp_protect(VOID) +@{ +@ + PUSH {r4-r6} @ Save registers we'll be using +@ +@ /* Disable interrupts so we don't get preempted. */ +@ + MRS r0, CPSR @ Pickup current CPSR + +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif +@ +@ /* Do we already have protection? */ +@ if (this_core == _tx_thread_smp_protection.tx_thread_smp_protect_core) +@ { +@ + MRC p15, 0, r1, c0, c0, 5 @ Read CPU ID register + AND r1, r1, #0x03 @ Mask off, leaving the CPU ID field + LDR r2, =_tx_thread_smp_protection @ Build address to protection structure + LDR r3, [r2, #8] @ Pickup the owning core + CMP r1, r3 @ Is it not this core? + BNE _protection_not_owned @ No, the protection is not already owned +@ +@ /* We already have protection. */ +@ +@ /* Increment the protection count. */ +@ _tx_thread_smp_protection.tx_thread_smp_protect_count++; +@ + LDR r3, [r2, #12] @ Pickup ownership count + ADD r3, r3, #1 @ Increment ownership count + STR r3, [r2, #12] @ Store ownership count + DMB + + B _return + +_protection_not_owned: +@ +@ /* Is the lock available? */ +@ if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0) +@ { +@ + LDREX r3, [r2, #0] @ Pickup the protection flag + CMP r3, #0 + BNE _start_waiting @ No, protection not available +@ +@ /* Is the list empty? */ +@ if (_tx_thread_smp_protect_wait_list_head == _tx_thread_smp_protect_wait_list_tail) +@ { +@ + LDR r3, =_tx_thread_smp_protect_wait_list_head + LDR r3, [r3] + LDR r4, =_tx_thread_smp_protect_wait_list_tail + LDR r4, [r4] + CMP r3, r4 + BNE _list_not_empty +@ +@ /* Try to get the lock. */ +@ if (write_exclusive(&_tx_thread_smp_protection.tx_thread_smp_protect_in_force, 1) == SUCCESS) +@ { +@ + MOV r3, #1 @ Build lock value + STREX r4, r3, [r2, #0] @ Attempt to get the protection + CMP r4, #0 + BNE _start_waiting @ Did it fail? +@ +@ /* We got the lock! */ +@ _tx_thread_smp_protect_lock_got(); +@ + DMB @ Ensure write to protection finishes + _tx_thread_smp_protect_lock_got @ Call the lock got function + + B _return + +_list_not_empty: +@ +@ /* Are we at the front of the list? */ +@ if (this_core == _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head]) +@ { +@ + LDR r3, =_tx_thread_smp_protect_wait_list_head @ Get the address of the head + LDR r3, [r3] @ Get the value of the head + LDR r4, =_tx_thread_smp_protect_wait_list @ Get the address of the list + LDR r4, [r4, r3, LSL #2] @ Get the value at the head index + + CMP r1, r4 + BNE _start_waiting +@ +@ /* Is the lock still available? */ +@ if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0) +@ { +@ + LDR r3, [r2, #0] @ Pickup the protection flag + CMP r3, #0 + BNE _start_waiting @ No, protection not available +@ +@ /* Get the lock. */ +@ _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1; +@ + MOV r3, #1 @ Build lock value + STR r3, [r2, #0] @ Store lock value + DMB @ +@ +@ /* Got the lock. */ +@ _tx_thread_smp_protect_lock_got(); +@ + _tx_thread_smp_protect_lock_got +@ +@ /* Remove this core from the wait list. */ +@ _tx_thread_smp_protect_remove_from_front_of_list(); +@ + _tx_thread_smp_protect_remove_from_front_of_list + + B _return + +_start_waiting: +@ +@ /* For one reason or another, we didn't get the lock. */ +@ +@ /* Increment wait count. */ +@ _tx_thread_smp_protect_wait_counts[this_core]++; +@ + LDR r3, =_tx_thread_smp_protect_wait_counts @ Load wait list counts + LDR r4, [r3, r1, LSL #2] @ Load waiting value for this core + ADD r4, r4, #1 @ Increment wait value + STR r4, [r3, r1, LSL #2] @ Store new wait value +@ +@ /* Have we not added ourselves to the list yet? */ +@ if (_tx_thread_smp_protect_wait_counts[this_core] == 1) +@ { +@ + CMP r4, #1 + BNE _already_in_list0 @ Is this core already waiting? +@ +@ /* Add ourselves to the list. */ +@ _tx_thread_smp_protect_wait_list_add(this_core); +@ + _tx_thread_smp_protect_wait_list_add @ Call macro to add ourselves to the list +@ +@ } +@ +_already_in_list0: +@ +@ /* Restore interrupts. */ +@ + MSR CPSR_c, r0 @ Restore CPSR +#ifdef TX_ENABLE_WFE + WFE @ Go into standby +#endif +@ +@ /* We do this until we have the lock. */ +@ while (1) +@ { +@ +_try_to_get_lock: +@ +@ /* Disable interrupts so we don't get preempted. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif + + MRC p15, 0, r1, c0, c0, 5 @ Read CPU ID register + AND r1, r1, #0x03 @ Mask off, leaving the CPU ID field +@ +@ /* Do we already have protection? */ +@ if (this_core == _tx_thread_smp_protection.tx_thread_smp_protect_core) +@ { +@ + LDR r3, [r2, #8] @ Pickup the owning core + CMP r3, r1 @ Is it this core? + BEQ _got_lock_after_waiting @ Yes, the protection is already owned. This means + @ an ISR preempted us and got protection +@ +@ } +@ +@ /* Are we at the front of the list? */ +@ if (this_core == _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head]) +@ { +@ + LDR r3, =_tx_thread_smp_protect_wait_list_head @ Get the address of the head + LDR r3, [r3] @ Get the value of the head + LDR r4, =_tx_thread_smp_protect_wait_list @ Get the address of the list + LDR r4, [r4, r3, LSL #2] @ Get the value at the head index + + CMP r1, r4 + BNE _did_not_get_lock +@ +@ /* Is the lock still available? */ +@ if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0) +@ { +@ + LDR r3, [r2, #0] @ Pickup the protection flag + CMP r3, #0 + BNE _did_not_get_lock @ No, protection not available +@ +@ /* Get the lock. */ +@ _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1; +@ + MOV r3, #1 @ Build lock value + STR r3, [r2, #0] @ Store lock value + DMB @ +@ +@ /* Got the lock. */ +@ _tx_thread_smp_protect_lock_got(); +@ + _tx_thread_smp_protect_lock_got +@ +@ /* Remove this core from the wait list. */ +@ _tx_thread_smp_protect_remove_from_front_of_list(); +@ + _tx_thread_smp_protect_remove_from_front_of_list + + B _got_lock_after_waiting + +_did_not_get_lock: +@ +@ /* For one reason or another, we didn't get the lock. */ +@ +@ /* Were we removed from the list? This can happen if we're a thread +@ and we got preempted. */ +@ if (_tx_thread_smp_protect_wait_counts[this_core] == 0) +@ { +@ + LDR r3, =_tx_thread_smp_protect_wait_counts @ Load wait list counts + LDR r4, [r3, r1, LSL #2] @ Load waiting value for this core + CMP r4, #0 + BNE _already_in_list1 @ Is this core already in the list? +@ +@ /* Add ourselves to the list. */ +@ _tx_thread_smp_protect_wait_list_add(this_core); +@ + _tx_thread_smp_protect_wait_list_add @ Call macro to add ourselves to the list +@ +@ /* Our waiting count was also reset when we were preempted. Increment it again. */ +@ _tx_thread_smp_protect_wait_counts[this_core]++; +@ + LDR r3, =_tx_thread_smp_protect_wait_counts @ Load wait list counts + LDR r4, [r3, r1, LSL #2] @ Load waiting value for this core + ADD r4, r4, #1 @ Increment wait value + STR r4, [r3, r1, LSL #2] @ Store new wait value value +@ +@ } +@ +_already_in_list1: +@ +@ /* Restore interrupts and try again. */ +@ + MSR CPSR_c, r0 @ Restore CPSR +#ifdef TX_ENABLE_WFE + WFE @ Go into standby +#endif + B _try_to_get_lock @ On waking, restart the protection attempt + +_got_lock_after_waiting: +@ +@ /* We're no longer waiting. */ +@ _tx_thread_smp_protect_wait_counts[this_core]--; +@ + LDR r3, =_tx_thread_smp_protect_wait_counts @ Load waiting list + LDR r4, [r3, r1, LSL #2] @ Load current wait value + SUB r4, r4, #1 @ Decrement wait value + STR r4, [r3, r1, LSL #2] @ Store new wait value value + +@ +@ /* Restore link register and return. */ +@ +_return: + + POP {r4-r6} @ Restore registers + +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif + + diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h new file mode 100644 index 00000000..26beabbd --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h @@ -0,0 +1,310 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread - Low Level SMP Support */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ + + .macro _tx_thread_smp_protect_lock_got +@ +@ /* Set the currently owned core. */ +@ _tx_thread_smp_protection.tx_thread_smp_protect_core = this_core; +@ + STR r1, [r2, #8] @ Store this core +@ +@ /* Increment the protection count. */ +@ _tx_thread_smp_protection.tx_thread_smp_protect_count++; +@ + LDR r3, [r2, #12] @ Pickup ownership count + ADD r3, r3, #1 @ Increment ownership count + STR r3, [r2, #12] @ Store ownership count + DMB + +#ifdef TX_MPCORE_DEBUG_ENABLE + LSL r3, r1, #2 @ Build offset to array indexes + LDR r4, =_tx_thread_current_ptr @ Pickup start of the current thread array + ADD r4, r3, r4 @ Build index into the current thread array + LDR r3, [r4] @ Pickup current thread for this core + STR r3, [r2, #4] @ Save current thread pointer + STR LR, [r2, #16] @ Save caller's return address + STR r0, [r2, #20] @ Save CPSR +#endif + + .endm + + .macro _tx_thread_smp_protect_remove_from_front_of_list +@ +@ /* Remove ourselves from the list. */ +@ _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head++] = 0xFFFFFFFF; +@ + MOV r3, #0xFFFFFFFF @ Build the invalid core value + LDR r4, =_tx_thread_smp_protect_wait_list_head @ Get the address of the head + LDR r5, [r4] @ Get the value of the head + LDR r6, =_tx_thread_smp_protect_wait_list @ Get the address of the list + STR r3, [r6, r5, LSL #2] @ Store the invalid core value + ADD r5, r5, #1 @ Increment the head +@ +@ /* Did we wrap? */ +@ if (_tx_thread_smp_protect_wait_list_head == TX_THREAD_SMP_MAX_CORES + 1) +@ { +@ + LDR r3, =_tx_thread_smp_protect_wait_list_size @ Load address of core list size + LDR r3, [r3] @ Load the max cores value + CMP r5, r3 @ Compare the head to it + BNE _store_new_head\@ @ Are we at the max? +@ +@ _tx_thread_smp_protect_wait_list_head = 0; +@ + EOR r5, r5, r5 @ We're at the max. Set it to zero +@ +@ } +@ +_store_new_head\@: + + STR r5, [r4] @ Store the new head +@ +@ /* We have the lock! */ +@ return; +@ + .endm + + + .macro _tx_thread_smp_protect_wait_list_lock_get +@VOID _tx_thread_smp_protect_wait_list_lock_get() +@{ +@ /* We do this until we have the lock. */ +@ while (1) +@ { +@ +_tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@: +@ +@ /* Is the list lock available? */ +@ _tx_thread_smp_protect_wait_list_lock_protect_in_force = load_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force); +@ + LDR r1, =_tx_thread_smp_protect_wait_list_lock_protect_in_force + LDREX r2, [r1] @ Pickup the protection flag +@ +@ if (protect_in_force == 0) +@ { +@ + CMP r2, #0 + BNE _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@ @ No, protection not available +@ +@ /* Try to get the list. */ +@ int status = store_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force, 1); +@ + MOV r2, #1 @ Build lock value + STREX r3, r2, [r1] @ Attempt to get the protection +@ +@ if (status == SUCCESS) +@ + CMP r3, #0 + BNE _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@ @ Did it fail? If so, try again. +@ +@ /* We have the lock! */ +@ return; +@ + .endm + + + .macro _tx_thread_smp_protect_wait_list_add +@VOID _tx_thread_smp_protect_wait_list_add(UINT new_core) +@{ +@ +@ /* We're about to modify the list, so get the list lock. */ +@ _tx_thread_smp_protect_wait_list_lock_get(); +@ + PUSH {r1-r2} + + _tx_thread_smp_protect_wait_list_lock_get + + POP {r1-r2} +@ +@ /* Add this core. */ +@ _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_tail++] = new_core; +@ + LDR r3, =_tx_thread_smp_protect_wait_list_tail @ Get the address of the tail + LDR r4, [r3] @ Get the value of tail + LDR r5, =_tx_thread_smp_protect_wait_list @ Get the address of the list + STR r1, [r5, r4, LSL #2] @ Store the new core value + ADD r4, r4, #1 @ Increment the tail +@ +@ /* Did we wrap? */ +@ if (_tx_thread_smp_protect_wait_list_tail == _tx_thread_smp_protect_wait_list_size) +@ { +@ + LDR r5, =_tx_thread_smp_protect_wait_list_size @ Load max cores address + LDR r5, [r5] @ Load max cores value + CMP r4, r5 @ Compare max cores to tail + BNE _tx_thread_smp_protect_wait_list_add__no_wrap\@ @ Did we wrap? +@ +@ _tx_thread_smp_protect_wait_list_tail = 0; +@ + MOV r4, #0 +@ +@ } +@ +_tx_thread_smp_protect_wait_list_add__no_wrap\@: + + STR r4, [r3] @ Store the new tail value. +@ +@ /* Release the list lock. */ +@ _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; +@ + MOV r3, #0 @ Build lock value + LDR r4, =_tx_thread_smp_protect_wait_list_lock_protect_in_force + STR r3, [r4] @ Store the new value + + .endm + + + .macro _tx_thread_smp_protect_wait_list_remove +@VOID _tx_thread_smp_protect_wait_list_remove(UINT core) +@{ +@ +@ /* Get the core index. */ +@ UINT core_index; +@ for (core_index = 0;; core_index++) +@ + EOR r1, r1, r1 @ Clear for 'core_index' + LDR r2, =_tx_thread_smp_protect_wait_list @ Get the address of the list +@ +@ { +@ +_tx_thread_smp_protect_wait_list_remove__check_cur_core\@: +@ +@ /* Is this the core? */ +@ if (_tx_thread_smp_protect_wait_list[core_index] == core) +@ { +@ break; +@ + LDR r3, [r2, r1, LSL #2] @ Get the value at the current index + CMP r3, r0 @ Did we find the core? + BEQ _tx_thread_smp_protect_wait_list_remove__found_core\@ +@ +@ } +@ + ADD r1, r1, #1 @ Increment cur index + B _tx_thread_smp_protect_wait_list_remove__check_cur_core\@ @ Restart the loop +@ +@ } +@ +_tx_thread_smp_protect_wait_list_remove__found_core\@: +@ +@ /* We're about to modify the list. Get the lock. We need the lock because another +@ core could be simultaneously adding (a core is simultaneously trying to get +@ the inter-core lock) or removing (a core is simultaneously being preempted, +@ like what is currently happening). */ +@ _tx_thread_smp_protect_wait_list_lock_get(); +@ + PUSH {r1} + + _tx_thread_smp_protect_wait_list_lock_get + + POP {r1} +@ +@ /* We remove by shifting. */ +@ while (core_index != _tx_thread_smp_protect_wait_list_tail) +@ { +@ +_tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@: + + LDR r2, =_tx_thread_smp_protect_wait_list_tail @ Load tail address + LDR r2, [r2] @ Load tail value + CMP r1, r2 @ Compare cur index and tail + BEQ _tx_thread_smp_protect_wait_list_remove__removed\@ +@ +@ UINT next_index = core_index + 1; +@ + MOV r2, r1 @ Move current index to next index register + ADD r2, r2, #1 @ Add 1 +@ +@ if (next_index == _tx_thread_smp_protect_wait_list_size) +@ { +@ + LDR r3, =_tx_thread_smp_protect_wait_list_size + LDR r3, [r3] + CMP r2, r3 + BNE _tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@ +@ +@ next_index = 0; +@ + MOV r2, #0 +@ +@ } +@ +_tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@: +@ +@ list_cores[core_index] = list_cores[next_index]; +@ + LDR r0, =_tx_thread_smp_protect_wait_list @ Get the address of the list + LDR r3, [r0, r2, LSL #2] @ Get the value at the next index + STR r3, [r0, r1, LSL #2] @ Store the value at the current index +@ +@ core_index = next_index; +@ + MOV r1, r2 + + B _tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@ +@ +@ } +@ +_tx_thread_smp_protect_wait_list_remove__removed\@: +@ +@ /* Now update the tail. */ +@ if (_tx_thread_smp_protect_wait_list_tail == 0) +@ { +@ + LDR r0, =_tx_thread_smp_protect_wait_list_tail @ Load tail address + LDR r1, [r0] @ Load tail value + CMP r1, #0 + BNE _tx_thread_smp_protect_wait_list_remove__tail_not_zero\@ +@ +@ _tx_thread_smp_protect_wait_list_tail = _tx_thread_smp_protect_wait_list_size; +@ + LDR r2, =_tx_thread_smp_protect_wait_list_size + LDR r1, [r2] +@ +@ } +@ +_tx_thread_smp_protect_wait_list_remove__tail_not_zero\@: +@ +@ _tx_thread_smp_protect_wait_list_tail--; +@ + SUB r1, r1, #1 + STR r1, [r0] @ Store new tail value +@ +@ /* Release the list lock. */ +@ _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; +@ + MOV r0, #0 @ Build lock value + LDR r1, =_tx_thread_smp_protect_wait_list_lock_protect_in_force @ Load lock address + STR r0, [r1] @ Store the new value +@ +@ /* We're no longer waiting. Note that this should be zero since, again, +@ this function is only called when a thread preemption is occurring. */ +@ _tx_thread_smp_protect_wait_counts[core]--; +@ + MRC p15, 0, r0, c0, c0, 5 @ Read CPU ID register + AND r0, r0, #0x03 @ Mask off, leaving the CPU ID field + LDR r1, =_tx_thread_smp_protect_wait_counts @ Load wait list counts + LDR r2, [r1, r0, LSL #2] @ Load waiting value + SUB r2, r2, #1 @ Subtract 1 + STR r2, [r1, r0, LSL #2] @ Store new waiting value + .endm + diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_time_get.S new file mode 100644 index 00000000..fd4ff2b5 --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_time_get.S @@ -0,0 +1,89 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread - Low Level SMP Support */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@#define TX_THREAD_SMP_SOURCE_CODE +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" */ +@ +@ + + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_time_get SMP/Cortex-A9/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function gets the global time value that is used for debug */ +@/* information and event tracing. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* 32-bit time stamp */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Source */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ + .global _tx_thread_smp_time_get + .type _tx_thread_smp_time_get,function +_tx_thread_smp_time_get: + + MRC p15, 4, r0, c15, c0, 0 @ Read periph base address + LDR r0, [r0, #0x604] @ Read count register + +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif + + diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_unprotect.S new file mode 100644 index 00000000..6a6e3a6b --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_smp_unprotect.S @@ -0,0 +1,143 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread - Low Level SMP Support */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@#define TX_THREAD_SMP_SOURCE_CODE +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_current_ptr + .global _tx_thread_smp_protection + .global _tx_thread_preempt_disable + .global _tx_thread_smp_protect_wait_counts + + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_unprotect SMP/Cortex-A9/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function releases previously obtained protection. The supplied */ +@/* previous SR is restored. If the value of _tx_thread_system_state */ +@/* and _tx_thread_preempt_disable are both zero, then multithreading */ +@/* is enabled as well. */ +@/* */ +@/* INPUT */ +@/* */ +@/* Previous Status Register */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Source */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ + .global _tx_thread_smp_unprotect + .type _tx_thread_smp_unprotect,function +_tx_thread_smp_unprotect: +@ +@ /* Lockout interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif + + MRC p15, 0, r1, c0, c0, 5 @ Read CPU ID register + AND r1, r1, #0x03 @ Mask off, leaving the CPU ID field + + LDR r2,=_tx_thread_smp_protection @ Build address of protection structure + LDR r3, [r2, #8] @ Pickup the owning core + CMP r1, r3 @ Is it this core? + BNE _still_protected @ If this is not the owning core, protection is in force elsewhere + + LDR r3, [r2, #12] @ Pickup the protection count + CMP r3, #0 @ Check to see if the protection is still active + BEQ _still_protected @ If the protection count is zero, protection has already been cleared + + SUB r3, r3, #1 @ Decrement the protection count + STR r3, [r2, #12] @ Store the new count back + CMP r3, #0 @ Check to see if the protection is still active + BNE _still_protected @ If the protection count is non-zero, protection is still in force + LDR r2,=_tx_thread_preempt_disable @ Build address of preempt disable flag + LDR r3, [r2] @ Pickup preempt disable flag + CMP r3, #0 @ Is the preempt disable flag set? + BNE _still_protected @ Yes, skip the protection release + + LDR r2,=_tx_thread_smp_protect_wait_counts @ Build build address of wait counts + LDR r3, [r2, r1, LSL #2] @ Pickup wait list value + CMP r3, #0 @ Are any entities on this core waiting? + BNE _still_protected @ Yes, skip the protection release + + LDR r2,=_tx_thread_smp_protection @ Build address of protection structure + MOV r3, #0xFFFFFFFF @ Build invalid value + STR r3, [r2, #8] @ Mark the protected core as invalid +#ifdef TX_MPCORE_DEBUG_ENABLE + STR LR, [r2, #16] @ Save caller's return address +#endif + DMB @ Ensure that accesses to shared resource have completed + MOV r3, #0 @ Build release protection value + STR r3, [r2, #0] @ Release the protection + DSB @ To ensure update of the protection occurs before other CPUs awake +#ifdef TX_ENABLE_WFE + SEV @ Send event to other CPUs, wakes anyone waiting on the protection (using WFE) +#endif + +_still_protected: + MSR CPSR_c, r0 @ Restore CPSR + +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif + + diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_stack_build.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_stack_build.S new file mode 100644 index 00000000..af56ff40 --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_stack_build.S @@ -0,0 +1,174 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +SVC_MODE = 0x13 @ SVC mode +#ifdef TX_ENABLE_FIQ_SUPPORT +CPSR_MASK = 0xDF @ Mask initial CPSR, IRQ & FIQ ints enabled +#else +CPSR_MASK = 0x9F @ Mask initial CPSR, IRQ ints enabled +#endif + +THUMB_BIT = 0x20 @ Thumb-bit + +@ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_stack_build SMP/Cortex-A9/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function builds a stack frame on the supplied thread's stack. */ +@/* The stack frame results in a fake interrupt return to the supplied */ +@/* function pointer. */ +@/* */ +@/* INPUT */ +@/* */ +@/* thread_ptr Pointer to thread control blk */ +@/* function_ptr Pointer to return function */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_thread_create Create thread service */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +@{ + .global _tx_thread_stack_build + .type _tx_thread_stack_build,function +_tx_thread_stack_build: +@ +@ +@ /* Build a fake interrupt frame. The form of the fake interrupt stack +@ on the Cortex-A9 should look like the following after it is built: +@ +@ Stack Top: 1 Interrupt stack frame type +@ CPSR Initial value for CPSR +@ a1 (r0) Initial value for a1 +@ a2 (r1) Initial value for a2 +@ a3 (r2) Initial value for a3 +@ a4 (r3) Initial value for a4 +@ v1 (r4) Initial value for v1 +@ v2 (r5) Initial value for v2 +@ v3 (r6) Initial value for v3 +@ v4 (r7) Initial value for v4 +@ v5 (r8) Initial value for v5 +@ sb (r9) Initial value for sb +@ sl (r10) Initial value for sl +@ fp (r11) Initial value for fp +@ ip (r12) Initial value for ip +@ lr (r14) Initial value for lr +@ pc (r15) Initial value for pc +@ 0 For stack backtracing +@ +@ Stack Bottom: (higher memory address) */ +@ + LDR r2, [r0, #16] @ Pickup end of stack area + BIC r2, r2, #7 @ Ensure 8-byte alignment + SUB r2, r2, #76 @ Allocate space for the stack frame +@ +@ /* Actually build the stack frame. */ +@ + MOV r3, #1 @ Build interrupt stack type + STR r3, [r2, #0] @ Store stack type + MOV r3, #0 @ Build initial register value + STR r3, [r2, #8] @ Store initial r0 + STR r3, [r2, #12] @ Store initial r1 + STR r3, [r2, #16] @ Store initial r2 + STR r3, [r2, #20] @ Store initial r3 + STR r3, [r2, #24] @ Store initial r4 + STR r3, [r2, #28] @ Store initial r5 + STR r3, [r2, #32] @ Store initial r6 + STR r3, [r2, #36] @ Store initial r7 + STR r3, [r2, #40] @ Store initial r8 + STR r3, [r2, #44] @ Store initial r9 + LDR r3, [r0, #12] @ Pickup stack starting address + STR r3, [r2, #48] @ Store initial r10 (sl) + MOV r3, #0 @ Build initial register value + STR r3, [r2, #52] @ Store initial r11 + STR r3, [r2, #56] @ Store initial r12 + STR r3, [r2, #60] @ Store initial lr + STR r1, [r2, #64] @ Store initial pc + STR r3, [r2, #68] @ 0 for back-trace + + MRS r3, CPSR @ Pickup CPSR + BIC r3, r3, #CPSR_MASK @ Mask mode bits of CPSR + ORR r3, r3, #SVC_MODE @ Build CPSR, SVC mode, interrupts enabled + BIC r3, r3, #THUMB_BIT @ Clear Thumb-bit by default + AND r1, r1, #1 @ Determine if the entry function is in Thumb mode + CMP r1, #1 @ Is the Thumb-bit set? + ORREQ r3, r3, #THUMB_BIT @ Yes, set the Thumb-bit + STR r3, [r2, #4] @ Store initial CPSR +@ +@ /* Setup stack pointer. */ +@ thread_ptr -> tx_thread_stack_ptr = r2; +@ + STR r2, [r0, #8] @ Save stack pointer in thread's + @ control block + +@ +@ /* Set ready bit in thread control block. */ +@ + LDR r2, [r0, #152] @ Pickup word with ready bit + ORR r2, r2, #0x8000 @ Build ready bit set + STR r2, [r0, #152] @ Set ready bit + +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_system_return.S new file mode 100644 index 00000000..bb2b44ff --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_system_return.S @@ -0,0 +1,206 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_current_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable + .global _tx_thread_smp_protection +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + .global _tx_execution_thread_exit +#endif +@ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_system_return SMP/Cortex-A9/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is target processor specific. It is used to transfer */ +@/* control from a thread back to the ThreadX system. Only a */ +@/* minimal context is saved since the compiler assumes temp registers */ +@/* are going to get slicked by a function call anyway. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling loop */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX components */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_system_return(VOID) +@{ + .global _tx_thread_system_return + .type _tx_thread_system_return,function +_tx_thread_system_return: +@ +@ /* Save minimal context on the stack. */ +@ + STMDB sp!, {r4-r11, lr} @ Save minimal context +@ +@ /* Pickup the CPU ID. */ +@ + MRC p15, 0, r10, c0, c0, 5 @ Read CPU ID register + AND r10, r10, #0x03 @ Mask off, leaving the CPU ID field + LSL r12, r10, #2 @ Build offset to array indexes + + LDR r3, =_tx_thread_current_ptr @ Pickup address of current ptr + ADD r3, r3, r12 @ Build index into current ptr array + LDR r0, [r3, #0] @ Pickup current thread pointer +#ifdef TARGET_FPU_VFP + LDR r1, [r0, #160] @ Pickup the VFP enabled flag + CMP r1, #0 @ Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_save @ No, skip VFP solicited save + VMRS r4, FPSCR @ Pickup the FPSCR + STR r4, [sp, #-4]! @ Save FPSCR + VSTMDB sp!, {D16-D31} @ Save D16-D31 + VSTMDB sp!, {D8-D15} @ Save D8-D15 +_tx_skip_solicited_vfp_save: +#endif + MOV r4, #0 @ Build a solicited stack type + MRS r5, CPSR @ Pickup the CPSR + STMDB sp!, {r4-r5} @ Save type and CPSR +@ +@ /* Lockout interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the thread exit function to indicate the thread is no longer executing. */ +@ + MOV r4, r0 @ Save r0 + MOV r5, r3 @ Save r3 + MOV r6, r12 @ Save r12 + BL _tx_execution_thread_exit @ Call the thread exit function + MOV r3, r5 @ Recover r3 + MOV r0, r4 @ Recover r4 + MOV r12,r6 @ Recover r12 +#endif +@ + LDR r2, =_tx_timer_time_slice @ Pickup address of time slice + ADD r2, r2, r12 @ Build index into time-slice array + LDR r1, [r2, #0] @ Pickup current time slice +@ +@ /* Save current stack and switch to system stack. */ +@ _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; +@ sp = _tx_thread_system_stack_ptr[core]; +@ + STR sp, [r0, #8] @ Save thread stack pointer +@ +@ /* Determine if the time-slice is active. */ +@ if (_tx_timer_time_slice[core]) +@ { +@ + MOV r4, #0 @ Build clear value + CMP r1, #0 @ Is a time-slice active? + BEQ __tx_thread_dont_save_ts @ No, don't save the time-slice +@ +@ /* Save time-slice for the thread and clear the current time-slice. */ +@ _tx_thread_current_ptr[core] -> tx_thread_time_slice = _tx_timer_time_slice[core]; +@ _tx_timer_time_slice[core] = 0; +@ + STR r4, [r2, #0] @ Clear time-slice + STR r1, [r0, #24] @ Save current time-slice +@ +@ } +__tx_thread_dont_save_ts: +@ +@ /* Clear the current thread pointer. */ +@ _tx_thread_current_ptr[core] = TX_NULL; +@ + STR r4, [r3, #0] @ Clear current thread pointer +@ +@ /* Set ready bit in thread control block. */ +@ + LDR r2, [r0, #152] @ Pickup word with ready bit + ORR r2, r2, #0x8000 @ Build ready bit set + DMB @ Ensure that accesses to shared resource have completed + STR r2, [r0, #152] @ Set ready bit +@ +@ /* Now clear protection. It is assumed that protection is in force whenever this routine is called. */ +@ + LDR r3, =_tx_thread_smp_protection @ Pickup address of protection structure + +#ifdef TX_MPCORE_DEBUG_ENABLE + STR lr, [r3, #24] @ Save last caller + LDR r2, [r3, #4] @ Pickup owning thread + CMP r0, r2 @ Is it the same as the current thread? +__error_loop: + BNE __error_loop @ If not, we have a problem!! +#endif + + LDR r1, =_tx_thread_preempt_disable @ Build address to preempt disable flag + MOV r2, #0 @ Build clear value + STR r2, [r1, #0] @ Clear preempt disable flag + STR r2, [r3, #12] @ Clear protection count + MOV r1, #0xFFFFFFFF @ Build invalid value + STR r1, [r3, #8] @ Set core to an invalid value + DMB @ Ensure that accesses to shared resource have completed + STR r2, [r3] @ Clear protection + DSB @ To ensure update of the shared resource occurs before other CPUs awake + SEV @ Send event to other CPUs, wakes anyone waiting on a mutex (using WFE) + + B _tx_thread_schedule @ Jump to scheduler! +@ +@} + diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_thread_vectored_context_save.S b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_vectored_context_save.S new file mode 100644 index 00000000..04f5fb74 --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_thread_vectored_context_save.S @@ -0,0 +1,210 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + .global _tx_execution_isr_enter +#endif +@ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_vectored_context_save SMP/Cortex-A9/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_vectored_context_save(VOID) +@{ + .global _tx_thread_vectored_context_save + .type _tx_thread_vectored_context_save,function +_tx_thread_vectored_context_save: +@ +@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +@ out, we are in IRQ mode, and all registers are intact. */ +@ +@ /* Check for a nested interrupt condition. */ +@ if (_tx_thread_system_state[core]++) +@ { +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#endif +@ +@ /* Pickup the CPU ID. */ +@ + MRC p15, 0, r10, c0, c0, 5 @ Read CPU ID register + AND r10, r10, #0x03 @ Mask off, leaving the CPU ID field + LSL r12, r10, #2 @ Build offset to array indexes + + LDR r3, =_tx_thread_system_state @ Pickup address of system state var + ADD r3, r3, r12 @ Build index into the system state array + LDR r2, [r3, #0] @ Pickup system state + CMP r2, #0 @ Is this the first interrupt? + BEQ __tx_thread_not_nested_save @ Yes, not a nested context save +@ +@ /* Nested interrupt condition. */ +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3, #0] @ Store it back in the variable +@ +@ /* Note: Minimal context of interrupted thread is already saved. */ +@ +@ /* Return to the ISR. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {r12, lr} @ Save ISR lr & r12 + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {r12, lr} @ Recover ISR lr & r12 +#endif + +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@ +__tx_thread_not_nested_save: +@ } +@ +@ /* Otherwise, not nested, check to see if a thread was running. */ +@ else if (_tx_thread_current_ptr[core]) +@ { +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3, #0] @ Store it back in the variable + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + ADD r1, r1, r12 @ Build index into current thread ptr + LDR r0, [r1, #0] @ Pickup current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + @ scheduling loop - nothing needs saving! +@ +@ /* Note: Minimal context of interrupted thread is already saved. */ +@ +@ /* Save the current stack pointer in the thread's control block. */ +@ _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; +@ +@ /* Switch to the system stack. */ +@ sp = _tx_thread_system_stack_ptr[core]; +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {r12, lr} @ Save ISR lr & r12 + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {r12, lr} @ Recover ISR lr & r12 +#endif + +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@ +@ } +@ else +@ { +@ +__tx_thread_idle_system_save: +@ +@ /* Interrupt occurred in the scheduling loop. */ +@ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ processing. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {r12, lr} @ Save ISR lr & r12 + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {r12, lr} @ Recover ISR lr & r12 +#endif + + ADD sp, sp, #32 @ Recover saved registers +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@ +@ } +@} +@ + diff --git a/ports_smp/cortex_a9_smp/gnu/src/tx_timer_interrupt.S b/ports_smp/cortex_a9_smp/gnu/src/tx_timer_interrupt.S new file mode 100644 index 00000000..00d288df --- /dev/null +++ b/ports_smp/cortex_a9_smp/gnu/src/tx_timer_interrupt.S @@ -0,0 +1,230 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Timer */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_timer.h" +@#include "tx_thread.h" +@ +@ +@Define Assembly language external references... +@ + .global _tx_timer_time_slice + .global _tx_timer_system_clock + .global _tx_timer_current_ptr + .global _tx_timer_list_start + .global _tx_timer_list_end + .global _tx_timer_expired_time_slice + .global _tx_timer_expired + .global _tx_thread_time_slice + .global _tx_timer_expiration_process + .global _tx_timer_interrupt_active + .global _tx_thread_smp_protect + .global _tx_thread_smp_unprotect + .global _tx_trace_isr_enter_insert + .global _tx_trace_isr_exit_insert +@ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_timer_interrupt SMP/Cortex-A9/GNU */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function processes the hardware timer interrupt. This */ +@/* processing includes incrementing the system clock and checking for */ +@/* time slice and/or timer expiration. If either is found, the */ +@/* interrupt context save/restore functions are called along with the */ +@/* expiration functions. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_time_slice Time slice interrupted thread */ +@/* _tx_thread_smp_protect Get SMP protection */ +@/* _tx_thread_smp_unprotect Releast SMP protection */ +@/* _tx_timer_expiration_process Timer expiration processing */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* interrupt vector */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_timer_interrupt(VOID) +@{ + .global _tx_timer_interrupt + .type _tx_timer_interrupt,function +_tx_timer_interrupt: +@ +@ /* Upon entry to this routine, it is assumed that context save has already +@ been called, and therefore the compiler scratch registers are available +@ for use. */ +@ + MRC p15, 0, r0, c0, c0, 5 @ Read CPU ID register + AND r0, r0, #0x03 @ Mask off, leaving the CPU ID field + CMP r0, #0 @ Only process timer interrupts from core 0 (to change this simply change the constant!) + BEQ __tx_process_timer @ If the same process the interrupt + BX lr @ Return to caller if not matched +__tx_process_timer: + + STMDB sp!, {r4, lr} @ Save the lr and r4 register on the stack + BL _tx_thread_smp_protect @ Get protection + MOV r4, r0 @ Save the return value in preserved register + + LDR r1, =_tx_timer_interrupt_active @ Pickup address of timer interrupt active count + LDR r0, [r1, #0] @ Pickup interrupt active count + ADD r0, r0, #1 @ Increment interrupt active count + STR r0, [r1, #0] @ Store new interrupt active count + DMB @ Ensure that accesses to shared resource have completed +@ +@ /* Increment the system clock. */ +@ _tx_timer_system_clock++; +@ + LDR r1, =_tx_timer_system_clock @ Pickup address of system clock + LDR r0, [r1, #0] @ Pickup system clock + ADD r0, r0, #1 @ Increment system clock + STR r0, [r1, #0] @ Store new system clock +@ +@ /* Test for timer expiration. */ +@ if (*_tx_timer_current_ptr) +@ { +@ + LDR r1, =_tx_timer_expired @ Pickup addr of expired flag + LDR r0, [r1, #0] @ Pickup timer expired flag + CMP r0, #0 @ Check for previous timer expiration still active + BNE __tx_timer_done @ If so, skip timer processing + LDR r1, =_tx_timer_current_ptr @ Pickup current timer pointer addr + LDR r0, [r1, #0] @ Pickup current timer + LDR r2, [r0, #0] @ Pickup timer list entry + CMP r2, #0 @ Is there anything in the list? + BEQ __tx_timer_no_timer @ No, just increment the timer +@ +@ /* Set expiration flag. */ +@ _tx_timer_expired = TX_TRUE; +@ + LDR r3, =_tx_timer_expired @ Pickup expiration flag address + MOV r2, #1 @ Build expired value + STR r2, [r3, #0] @ Set expired flag + B __tx_timer_done @ Finished timer processing +@ +@ } +@ else +@ { +__tx_timer_no_timer: +@ +@ /* No timer expired, increment the timer pointer. */ +@ _tx_timer_current_ptr++; +@ + ADD r0, r0, #4 @ Move to next timer +@ +@ /* Check for wrap-around. */ +@ if (_tx_timer_current_ptr == _tx_timer_list_end) +@ + LDR r3, =_tx_timer_list_end @ Pickup addr of timer list end + LDR r2, [r3, #0] @ Pickup list end + CMP r0, r2 @ Are we at list end? + BNE __tx_timer_skip_wrap @ No, skip wrap-around logic +@ +@ /* Wrap to beginning of list. */ +@ _tx_timer_current_ptr = _tx_timer_list_start; +@ + LDR r3, =_tx_timer_list_start @ Pickup addr of timer list start + LDR r0, [r3, #0] @ Set current pointer to list start +@ +__tx_timer_skip_wrap: +@ + STR r0, [r1, #0] @ Store new current timer pointer +@ } +@ +__tx_timer_done: +@ +@ +@ /* Did a timer expire? */ +@ if (_tx_timer_expired) +@ { +@ + LDR r1, =_tx_timer_expired @ Pickup addr of expired flag + LDR r0, [r1, #0] @ Pickup timer expired flag + CMP r0, #0 @ Check for timer expiration + BEQ __tx_timer_dont_activate @ If not set, skip timer activation +@ +@ /* Process timer expiration. */ +@ _tx_timer_expiration_process(); +@ + BL _tx_timer_expiration_process @ Call the timer expiration handling routine +@ +@ } +__tx_timer_dont_activate: +@ +@ /* Call time-slice processing. */ +@ _tx_thread_time_slice(); + + BL _tx_thread_time_slice @ Call time-slice processing +@ +@ } +@ + LDR r1, =_tx_timer_interrupt_active @ Pickup address of timer interrupt active count + LDR r0, [r1, #0] @ Pickup interrupt active count + SUB r0, r0, #1 @ Decrement interrupt active count + STR r0, [r1, #0] @ Store new interrupt active count + DMB @ Ensure that accesses to shared resource have completed +@ +@ /* Release protection. */ +@ + MOV r0, r4 @ Pass the previous status register back + BL _tx_thread_smp_unprotect @ Release protection + + LDMIA sp!, {r4, lr} @ Recover lr register and r4 +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@ +@} + diff --git a/ports_smp/linux/gnu/example_build/file_list.mk b/ports_smp/linux/gnu/example_build/file_list.mk new file mode 100644 index 00000000..99c91a29 --- /dev/null +++ b/ports_smp/linux/gnu/example_build/file_list.mk @@ -0,0 +1,219 @@ +LINUX_SRCS = \ +tx_initialize_low_level.c \ +tx_thread_context_restore.c \ +tx_thread_context_save.c \ +tx_thread_interrupt_control.c \ +tx_thread_schedule.c \ +tx_thread_smp_core_get.c \ +tx_thread_smp_core_preempt.c \ +tx_thread_smp_current_state_get.c \ +tx_thread_smp_current_thread_get.c \ +tx_thread_smp_initialize_wait.c \ +tx_thread_smp_low_level_initialize.c \ +tx_thread_smp_protect.c \ +tx_thread_smp_time_get.c \ +tx_thread_smp_unprotect.c \ +tx_thread_stack_build.c \ +tx_thread_system_return.c \ +tx_timer_interrupt.c \ + +LINUX_OBJS = $(LINUX_SRCS:%.c=.tmp/%.o) + + +GENERIC_SRCS = \ +tx_block_allocate.c \ +tx_block_pool_cleanup.c \ +tx_block_pool_create.c \ +tx_block_pool_delete.c \ +tx_block_pool_info_get.c \ +tx_block_pool_initialize.c \ +tx_block_pool_performance_info_get.c \ +tx_block_pool_performance_system_info_get.c \ +tx_block_pool_prioritize.c \ +tx_block_release.c \ +tx_byte_allocate.c \ +tx_byte_pool_cleanup.c \ +tx_byte_pool_create.c \ +tx_byte_pool_delete.c \ +tx_byte_pool_info_get.c \ +tx_byte_pool_initialize.c \ +tx_byte_pool_performance_info_get.c \ +tx_byte_pool_performance_system_info_get.c \ +tx_byte_pool_prioritize.c \ +tx_byte_pool_search.c \ +tx_byte_release.c \ +txe_block_allocate.c \ +txe_block_pool_create.c \ +txe_block_pool_delete.c \ +txe_block_pool_info_get.c \ +txe_block_pool_prioritize.c \ +txe_block_release.c \ +txe_byte_allocate.c \ +txe_byte_pool_create.c \ +txe_byte_pool_delete.c \ +txe_byte_pool_info_get.c \ +txe_byte_pool_prioritize.c \ +txe_byte_release.c \ +txe_event_flags_create.c \ +txe_event_flags_delete.c \ +txe_event_flags_get.c \ +txe_event_flags_info_get.c \ +txe_event_flags_set.c \ +txe_event_flags_set_notify.c \ +txe_mutex_create.c \ +txe_mutex_delete.c \ +txe_mutex_get.c \ +txe_mutex_info_get.c \ +txe_mutex_prioritize.c \ +txe_mutex_put.c \ +txe_queue_create.c \ +txe_queue_delete.c \ +txe_queue_flush.c \ +txe_queue_front_send.c \ +txe_queue_info_get.c \ +txe_queue_prioritize.c \ +txe_queue_receive.c \ +txe_queue_send.c \ +txe_queue_send_notify.c \ +txe_semaphore_ceiling_put.c \ +txe_semaphore_create.c \ +txe_semaphore_delete.c \ +txe_semaphore_get.c \ +txe_semaphore_info_get.c \ +txe_semaphore_prioritize.c \ +txe_semaphore_put.c \ +txe_semaphore_put_notify.c \ +txe_thread_create.c \ +txe_thread_delete.c \ +txe_thread_entry_exit_notify.c \ +txe_thread_info_get.c \ +txe_thread_preemption_change.c \ +txe_thread_priority_change.c \ +txe_thread_relinquish.c \ +txe_thread_reset.c \ +txe_thread_resume.c \ +txe_thread_suspend.c \ +txe_thread_terminate.c \ +txe_thread_time_slice_change.c \ +txe_thread_wait_abort.c \ +txe_timer_activate.c \ +txe_timer_change.c \ +txe_timer_create.c \ +txe_timer_deactivate.c \ +txe_timer_delete.c \ +txe_timer_info_get.c \ +tx_event_flags_cleanup.c \ +tx_event_flags_create.c \ +tx_event_flags_delete.c \ +tx_event_flags_get.c \ +tx_event_flags_info_get.c \ +tx_event_flags_initialize.c \ +tx_event_flags_performance_info_get.c \ +tx_event_flags_performance_system_info_get.c \ +tx_event_flags_set.c \ +tx_event_flags_set_notify.c \ +tx_initialize_high_level.c \ +tx_initialize_kernel_enter.c \ +tx_initialize_kernel_setup.c \ +tx_misra.c \ +tx_mutex_cleanup.c \ +tx_mutex_create.c \ +tx_mutex_delete.c \ +tx_mutex_get.c \ +tx_mutex_info_get.c \ +tx_mutex_initialize.c \ +tx_mutex_performance_info_get.c \ +tx_mutex_performance_system_info_get.c \ +tx_mutex_prioritize.c \ +tx_mutex_priority_change.c \ +tx_mutex_put.c \ +tx_queue_cleanup.c \ +tx_queue_create.c \ +tx_queue_delete.c \ +tx_queue_flush.c \ +tx_queue_front_send.c \ +tx_queue_info_get.c \ +tx_queue_initialize.c \ +tx_queue_performance_info_get.c \ +tx_queue_performance_system_info_get.c \ +tx_queue_prioritize.c \ +tx_queue_receive.c \ +tx_queue_send.c \ +tx_queue_send_notify.c \ +tx_semaphore_ceiling_put.c \ +tx_semaphore_cleanup.c \ +tx_semaphore_create.c \ +tx_semaphore_delete.c \ +tx_semaphore_get.c \ +tx_semaphore_info_get.c \ +tx_semaphore_initialize.c \ +tx_semaphore_performance_info_get.c \ +tx_semaphore_performance_system_info_get.c \ +tx_semaphore_prioritize.c \ +tx_semaphore_put.c \ +tx_semaphore_put_notify.c \ +tx_thread_create.c \ +tx_thread_delete.c \ +tx_thread_entry_exit_notify.c \ +tx_thread_identify.c \ +tx_thread_info_get.c \ +tx_thread_initialize.c \ +tx_thread_performance_info_get.c \ +tx_thread_performance_system_info_get.c \ +tx_thread_preemption_change.c \ +tx_thread_priority_change.c \ +tx_thread_relinquish.c \ +tx_thread_reset.c \ +tx_thread_resume.c \ +tx_thread_shell_entry.c \ +tx_thread_sleep.c \ +tx_thread_smp_core_exclude.c \ +tx_thread_smp_core_exclude_get.c \ +tx_thread_smp_current_state_set.c \ +tx_thread_smp_debug_entry_insert.c \ +tx_thread_smp_high_level_initialize.c \ +tx_thread_smp_rebalance_execute_list.c \ +tx_thread_smp_utilities.c \ +tx_thread_stack_analyze.c \ +tx_thread_stack_error_handler.c \ +tx_thread_stack_error_notify.c \ +tx_thread_suspend.c \ +tx_thread_system_preempt_check.c \ +tx_thread_system_resume.c \ +tx_thread_system_suspend.c \ +tx_thread_terminate.c \ +tx_thread_timeout.c \ +tx_thread_time_slice.c \ +tx_thread_time_slice_change.c \ +tx_thread_wait_abort.c \ +tx_time_get.c \ +tx_timer_activate.c \ +tx_timer_change.c \ +tx_timer_create.c \ +tx_timer_deactivate.c \ +tx_timer_delete.c \ +tx_timer_expiration_process.c \ +tx_timer_info_get.c \ +tx_timer_initialize.c \ +tx_timer_performance_info_get.c \ +tx_timer_performance_system_info_get.c \ +tx_timer_smp_core_exclude.c \ +tx_timer_smp_core_exclude_get.c \ +tx_timer_system_activate.c \ +tx_timer_system_deactivate.c \ +tx_timer_thread_entry.c \ +tx_time_set.c \ +tx_trace_buffer_full_notify.c \ +tx_trace_disable.c \ +tx_trace_enable.c \ +tx_trace_event_filter.c \ +tx_trace_event_unfilter.c \ +tx_trace_initialize.c \ +tx_trace_interrupt_control.c \ +tx_trace_isr_enter_insert.c \ +tx_trace_isr_exit_insert.c \ +tx_trace_object_register.c \ +tx_trace_object_unregister.c \ +tx_trace_user_event_insert.c \ + +GENERIC_OBJS = $(GENERIC_SRCS:%.c=.tmp/generic/%.o) diff --git a/ports_smp/linux/gnu/example_build/sample_threadx.c b/ports_smp/linux/gnu/example_build/sample_threadx.c new file mode 100644 index 00000000..34bdc481 --- /dev/null +++ b/ports_smp/linux/gnu/example_build/sample_threadx.c @@ -0,0 +1,380 @@ +/* This is a small demo of the high-performance ThreadX SMP kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" +#include + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Print results. */ + printf("**** ThreadX SMP Linux Demonstration **** (c) 1996-2020 Microsoft Corporation\n\n"); + printf(" thread 0 events sent: %lu\n", thread_0_counter); + printf(" thread 1 messages sent: %lu\n", thread_1_counter); + printf(" thread 2 messages received: %lu\n", thread_2_counter); + printf(" thread 3 obtained semaphore: %lu\n", thread_3_counter); + printf(" thread 4 obtained semaphore: %lu\n", thread_4_counter); + printf(" thread 5 events received: %lu\n", thread_5_counter); + printf(" thread 6 mutex obtained: %lu\n", thread_6_counter); + printf(" thread 7 mutex obtained: %lu\n\n", thread_7_counter); + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports_smp/linux/gnu/inc/tx_port.h b/ports_smp/linux/gnu/inc/tx_port.h new file mode 100644 index 00000000..7db203d9 --- /dev/null +++ b/ports_smp/linux/gnu/inc/tx_port.h @@ -0,0 +1,678 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h SMP/Linux/GCC */ +/* 6.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + + +/************* Define ThreadX SMP constants. *************/ + +#define TX_DISABLE_INLINE + + +/* Define the ThreadX SMP maximum number of cores. */ + +#ifndef TX_THREAD_SMP_MAX_CORES +#define TX_THREAD_SMP_MAX_CORES 4 +#endif + + + +/* Define the ThreadX SMP core mask. */ + +#ifndef TX_THREAD_SMP_CORE_MASK +#define TX_THREAD_SMP_CORE_MASK 0xF /* Where bit 0 represents Core 0, bit 1 represents Core 1, etc. */ +#endif + +/* Define dynamic number of cores option. When commented out, the number of cores is static. */ + +/* #define TX_THREAD_SMP_DYNAMIC_CORE_MAX */ + + +/* Define ThreadX SMP initialization macro. */ + +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION + + +/* Enable the inter-core interrupt logic. */ + +#define TX_THREAD_SMP_INTER_CORE_INTERRUPT + + +/* Determine if there is customer-specific wakeup logic needed. */ + +#ifdef TX_THREAD_SMP_WAKEUP_LOGIC + +/* Include customer-specific wakeup code. */ + +#include "tx_thread_smp_core_wakeup.h" +#else + +#ifdef TX_THREAD_SMP_DEFAULT_WAKEUP_LOGIC + +/* Default wakeup code. */ +#define TX_THREAD_SMP_WAKEUP_LOGIC +#define TX_THREAD_SMP_WAKEUP(i) _tx_thread_smp_core_preempt(i) +#endif +#endif + + +/* Ensure that the in-line resume/suspend define is not allowed. */ + +#ifdef TX_INLINE_THREAD_RESUME_SUSPEND +#undef TX_INLINE_THREAD_RESUME_SUSPEND +#endif + + +/* Overide inline keyword. */ + +#define INLINE_DECLARE __inline + + +/************* End ThreadX SMP constants. *************/ + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include +#include +#ifndef __USE_POSIX199309 +#define __USE_POSIX199309 +#include +#include +#include +#undef __USE_POSIX199309 +#else /* __USE_POSIX199309 */ +#include +#include +#include +#endif /* __USE_POSIX199309 */ + + +/* Define ThreadX basic types for this port. */ + +typedef void VOID; +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; +typedef uint64_t ULONG64; + + + +/* Define automated coverage test extensions... These are required for the + ThreadX regression test. */ + +typedef unsigned int TEST_FLAG; +extern TEST_FLAG threadx_byte_allocate_loop_test; +extern TEST_FLAG threadx_byte_release_loop_test; +extern TEST_FLAG threadx_mutex_suspension_put_test; +extern TEST_FLAG threadx_mutex_suspension_priority_test; +#ifndef TX_TIMER_PROCESS_IN_ISR +extern TEST_FLAG threadx_delete_timer_thread; +#endif + +extern void abort_and_resume_byte_allocating_thread(void); +extern void abort_all_threads_suspended_on_mutex(void); +extern void suspend_lowest_priority(void); +#ifndef TX_TIMER_PROCESS_IN_ISR +extern void delete_timer_thread(void); +#endif +extern TEST_FLAG test_stack_analyze_flag; +extern TEST_FLAG test_initialize_flag; +extern TEST_FLAG test_forced_mutex_timeout; +extern UINT mutex_priority_change_extension_selection; +extern UINT priority_change_extension_selection; + + +#ifdef TX_REGRESSION_TEST + +/* Define extension macros for automated coverage tests. */ + + +#define TX_PORT_SPECIFIC_MEMORY_SYNCHRONIZATION other_core_status = other_core_status + _tx_thread_system_state[0]; \ + _tx_thread_system_state[0] = 0; + + +#define TX_BYTE_ALLOCATE_EXTENSION if (threadx_byte_allocate_loop_test == ((TEST_FLAG) 1)) \ + { \ + pool_ptr -> tx_byte_pool_owner = TX_NULL; \ + threadx_byte_allocate_loop_test = ((TEST_FLAG) 0); \ + } + +#define TX_BYTE_RELEASE_EXTENSION if (threadx_byte_release_loop_test == ((TEST_FLAG) 1)) \ + { \ + threadx_byte_release_loop_test = ((TEST_FLAG) 0); \ + abort_and_resume_byte_allocating_thread(); \ + } + +#define TX_MUTEX_PUT_EXTENSION_1 if (threadx_mutex_suspension_put_test == ((TEST_FLAG) 1)) \ + { \ + threadx_mutex_suspension_put_test = ((TEST_FLAG) 0); \ + abort_all_threads_suspended_on_mutex(); \ + } + + +#define TX_MUTEX_PUT_EXTENSION_2 if (test_forced_mutex_timeout == ((TEST_FLAG) 1)) \ + { \ + test_forced_mutex_timeout = ((TEST_FLAG) 0); \ + _tx_thread_wait_abort(mutex_ptr -> tx_mutex_suspension_list); \ + } + + +#define TX_MUTEX_PRIORITY_CHANGE_EXTENSION if (threadx_mutex_suspension_priority_test == ((TEST_FLAG) 1)) \ + { \ + threadx_mutex_suspension_priority_test = ((TEST_FLAG) 0); \ + if (mutex_priority_change_extension_selection == 2) \ + original_priority = new_priority; \ + if (mutex_priority_change_extension_selection == 3) \ + original_pt_thread = thread_ptr; \ + if (mutex_priority_change_extension_selection == 4) \ + { \ + execute_ptr = thread_ptr; \ + _tx_thread_preemption__threshold_scheduled = TX_NULL; \ + } \ + suspend_lowest_priority(); \ + } + +#define TX_THREAD_PRIORITY_CHANGE_EXTENSION if (priority_change_extension_selection != ((TEST_FLAG) 0)) \ + { \ + if (priority_change_extension_selection == 1) \ + thread_ptr -> tx_thread_smp_core_mapped = TX_THREAD_SMP_MAX_CORES; \ + else if (priority_change_extension_selection == 2) \ + { \ + original_priority = new_priority; \ + _tx_thread_execute_ptr[0] = TX_NULL; \ + } \ + else if (priority_change_extension_selection == 3) \ + { \ + original_pt_thread = thread_ptr; \ + } \ + else \ + { \ + _tx_thread_preemption__threshold_scheduled = TX_NULL; \ + } \ + priority_change_extension_selection = 0; \ + } + + +#ifndef TX_TIMER_PROCESS_IN_ISR + +#define TX_TIMER_INITIALIZE_EXTENSION(a) if (threadx_delete_timer_thread == ((TEST_FLAG) 1)) \ + { \ + threadx_delete_timer_thread = ((TEST_FLAG) 0); \ + delete_timer_thread(); \ + (a) = ((UINT) 1); \ + } + +#endif + +#define TX_THREAD_STACK_ANALYZE_EXTENSION if (test_stack_analyze_flag == ((TEST_FLAG) 1)) \ + { \ + thread_ptr -> tx_thread_id = ((TEST_FLAG) 0); \ + test_stack_analyze_flag = ((TEST_FLAG) 0); \ + } \ + else if (test_stack_analyze_flag == ((TEST_FLAG) 2)) \ + { \ + stack_ptr = thread_ptr -> tx_thread_stack_start; \ + test_stack_analyze_flag = ((TEST_FLAG) 0); \ + } \ + else if (test_stack_analyze_flag == ((TEST_FLAG) 3)) \ + { \ + *stack_ptr = TX_STACK_FILL; \ + test_stack_analyze_flag = ((TEST_FLAG) 0); \ + } \ + else \ + { \ + test_stack_analyze_flag = ((TEST_FLAG) 0); \ + } + +#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION if (test_initialize_flag == ((TEST_FLAG) 1)) \ + { \ + test_initialize_flag = ((TEST_FLAG) 0); \ + return; \ + } + +#endif + + +/* Add Linux debug insert prototype. */ + +void _tx_linux_debug_entry_insert(char *action, char *file, unsigned long line); + +#ifndef TX_LINUX_DEBUG_ENABLE + +/* If Linux debug is not enabled, turn logging into white-space. */ + +#define _tx_linux_debug_entry_insert(a, b, c) + +#endif + + + +/* Define the TX_MEMSET macro to remove library reference. */ + +#ifndef TX_MISRA_ENABLE +#define TX_MEMSET(a,b,c) { \ + UCHAR *ptr; \ + UCHAR value; \ + UINT i, size; \ + ptr = (UCHAR *) ((VOID *) a); \ + value = (UCHAR) b; \ + size = (UINT) c; \ + for (i = 0; i < size; i++) \ + { \ + *ptr++ = value; \ + } \ + } +#endif + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 400 /* Default timer thread stack size - Not used in Linux port! */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX port. */ + +#define TX_INT_DISABLE 1 /* Disable interrupts */ +#define TX_INT_ENABLE 0 /* Enable interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ((ULONG) (_tx_linux_time_stamp.tv_nsec)) +#endif +#else +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif + +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port-specific trace extension to pickup the Windows timer. */ + +#define TX_TRACE_PORT_EXTENSION clock_gettime(CLOCK_REALTIME, &_tx_linux_time_stamp); + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0 + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Define the Linux-specific initialization code that is expanded in the generic source. */ + +void _tx_initialize_start_interrupts(void); + + +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION _tx_initialize_start_interrupts(); \ + { \ + UINT k; \ + for (k = 1; k < TX_THREAD_SMP_MAX_CORES; k++) \ + { \ + _tx_thread_system_state[k] = 0; \ + } \ + } + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 pthread_t tx_thread_linux_thread_id; \ + sem_t tx_thread_linux_thread_run_semaphore; \ + UINT tx_thread_linux_suspension_type; \ + UINT tx_thread_linux_mutex_access; \ + UINT tx_thread_linux_int_disabled_flag; \ + UINT tx_thread_linux_deferred_preempt; \ + UINT tx_thread_linux_virtual_core; + +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the Linux mutex data structure. */ + +typedef struct +{ + pthread_mutex_t tx_linux_mutex; + pthread_t tx_linux_mutex_owner; + ULONG tx_linux_mutex_nested_count; +} TX_LINUX_MUTEX; + + +/* Define Linux-specific critical section APIs. */ + +void _tx_linux_mutex_obtain(TX_LINUX_MUTEX *mutex); +void _tx_linux_mutex_release(TX_LINUX_MUTEX *mutex); +void _tx_linux_mutex_release_all(TX_LINUX_MUTEX *mutex); + +typedef struct TX_THREAD_STRUCT TX_THREAD; + +/* Define post completion processing for tx_thread_delete, so that the Linux thread resources are properly removed. */ + +void _tx_thread_delete_port_completion(TX_THREAD *thread_ptr, UINT tx_interrupt_save); +#define TX_THREAD_DELETE_PORT_COMPLETION(thread_ptr) _tx_thread_delete_port_completion(thread_ptr, tx_interrupt_save); + + +/* Define post completion processing for tx_thread_reset, so that the Linux thread resources are properly removed. */ + +void _tx_thread_reset_port_completion(TX_THREAD *thread_ptr, UINT tx_interrupt_save); +#define TX_THREAD_RESET_PORT_COMPLETION(thread_ptr) _tx_thread_reset_port_completion(thread_ptr, tx_interrupt_save); + + +/************* Define ThreadX SMP data types and function prototypes. *************/ + +struct TX_THREAD_STRUCT; + + +/* Define the ThreadX SMP protection structure. */ + +typedef struct TX_THREAD_SMP_PROTECT_STRUCT +{ + ULONG tx_thread_smp_protect_in_force; + struct TX_THREAD_STRUCT *tx_thread_smp_protect_thread; + ULONG tx_thread_smp_protect_core; + ULONG tx_thread_smp_protect_count; + pthread_t tx_thread_smp_protect_linux_thread_id; +} TX_THREAD_SMP_PROTECT; + + +/* Define the virtual core structure for ThreadX SMP Linux. This is where we keep the mapping of the core to + the actual thread running. All ISRs are assumed to be running on core 0 for Linux. */ + +typedef struct TX_THREAD_SMP_CORE_MAPPING_STRUCT +{ + pthread_t tx_thread_smp_core_mapping_linux_thread_id; + struct TX_THREAD_STRUCT *tx_thread_smp_core_mapping_thread; +} TX_THREAD_SMP_CORE_MAPPING; + + +/* Define ThreadX SMP low-level assembly routines. */ + +struct TX_THREAD_STRUCT * _tx_thread_smp_current_thread_get(void); +UINT _tx_thread_smp_protect(void); +void _tx_thread_smp_unprotect(UINT interrupt_save); +ULONG _tx_thread_smp_current_state_get(void); +ULONG _tx_thread_smp_time_get(void); + + +/* Determine if SMP Debug is selected. If so, the function prototype is setup. Otherwise, the debug call is + simply mapped to whitespace. */ + +#ifdef TX_THREAD_SMP_DEBUG_ENABLE +void _tx_thread_smp_debug_entry_insert(ULONG id, ULONG suspend, VOID *thread_ptr); +#else +#define _tx_thread_smp_debug_entry_insert(a, b, c) +#endif + + +/* Define the get core ID macro. */ + +#define TX_SMP_CORE_ID _tx_thread_smp_core_get() + + + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#define TX_INTERRUPT_SAVE_AREA unsigned int tx_interrupt_save; + +#define TX_DISABLE tx_interrupt_save = _tx_thread_smp_protect(); +#define TX_RESTORE _tx_thread_smp_unprotect(tx_interrupt_save); + + +/************* End ThreadX SMP data type and function prototype definitions. *************/ + + +#define tx_linux_sem_post(p) sem_post(p) +#define tx_linux_sem_wait(p) sem_wait(p) +#define tx_linux_sem_timedwait(p, t) sem_timedwait(p, t) + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Linux/gcc Version 6.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +/* Define externals for the Linux port of ThreadX. */ + +extern TX_LINUX_MUTEX _tx_linux_mutex; +extern sem_t _tx_linux_scheduler_semaphore; +extern pthread_t _tx_linux_scheduler_id; +extern ULONG _tx_linux_global_int_disabled_flag; +extern struct timespec _tx_linux_time_stamp; +extern ULONG _tx_linux_system_error; +extern TX_THREAD_SMP_CORE_MAPPING _tx_linux_virtual_cores[TX_THREAD_SMP_MAX_CORES]; +extern __thread int _tx_linux_threadx_thread; + +/* Define functions for linux thread. */ +void _tx_linux_thread_suspend(pthread_t thread_id); +void _tx_linux_thread_resume(pthread_t thread_id); +void _tx_linux_thread_init(); +void _tx_linux_thread_sleep(long ns); + +#ifndef TX_LINUX_MEMORY_SIZE +#define TX_LINUX_MEMORY_SIZE 100000 +#endif + +#ifndef TX_TIMER_TICKS_PER_SECOND +#define TX_TIMER_TICKS_PER_SECOND 100UL +#endif + +#ifndef TX_LINUX_THREAD_STACK_SIZE +#define TX_LINUX_THREAD_STACK_SIZE 65536 +#endif + +/* Define priorities of pthreads. */ +#define TX_LINUX_PRIORITY_SCHEDULE (3) +#define TX_LINUX_PRIORITY_ISR (2) +#define TX_LINUX_PRIORITY_USER_THREAD (1) + +#endif + + + + + + + diff --git a/ports_smp/linux/gnu/readme_threadx.txt b/ports_smp/linux/gnu/readme_threadx.txt new file mode 100644 index 00000000..646b8714 --- /dev/null +++ b/ports_smp/linux/gnu/readme_threadx.txt @@ -0,0 +1,155 @@ + Microsoft's Azure RTOS ThreadX SMP for Linux + + Using the GNU GCC Tools + +1. Building the ThreadX SMP run-time Library + +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the GNU +development environment. The following command retrieves and installs GCC +multilib on a Ubuntu system: + +sudo apt-get install gcc-multilib + +At this point you may run the GNU make command to build the ThreadX SMP core +library. This will build the ThreadX SMP run-time environment in the +"example_build" directory. + + make tx.a + +you should now observe the compilation of the ThreadX SMP library source. At the +end of the make, they are all combined into the run-time library file: tx.a. +This file must be linked with your application in order to use ThreadX. + + +2. Demonstration System + +Building the demonstration is easy; simply execute the GNU make command while +inside the "example_build" directory. + + make sample_threadx + +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file DEMO is a binary file +that can be executed. + + +3. System Initialization + +The system entry point is at main(), which is defined in the application. +Once the application calls tx_kernel_enter, ThreadX SMP starts running and +performs various initialization duties prior to starting the scheduler. The +Linux-specific initialization is done in the function _tx_initialize_low_level, +which is located in the file tx_initialize_low_level.c. This function is +responsible for setting up various system data structures and simulated +interrupts - including the periodic timer interrupt source for ThreadX. + +In addition, _tx_initialize_low_level determines the first available +address for use by the application. In Linux, this is basically done +by using malloc to get a big block of memory from Linux. + + +4. Linux Implementation + +ThreadX SMP for Linux is implemented using POSIX pthreads. Each application +thread in ThreadX SMP actually runs as a Linux pthread. The determination of +which application thread to run is made by the ThreadX SMP scheduler, which +itself is a Linux pthread. The ThreadX SMP scheduler is the highest priority +thread in the system. + +Interrupts in ThreadX_SMP Linux are also simulated by pthreads. A good example +is the ThreadX SMP system timer interrupt, which can be found in +tx_initialize_low_level.c. + +ThreadX SMP for linux utilizes the API pthread_setschedparam() which requires +the ThreadX SMP application running with privilege. The following command is used +to run a ThreadX SMP application: + +./sample_threadx + +5. Improving Performance + +The distribution version of ThreadX SMP is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX SMP itself. Of course, this costs some +performance. To make it run faster, you can change the makefile to +enable all compiler optimizations. In addition, you can eliminate the +ThreadX SMP basic API error checking by compiling your application code with the +symbol TX_DISABLE_ERROR_CHECKING defined. + + +6. Interrupt Handling + +ThreadX SMP provides simulated interrupt handling with Linux pthreads. Simulated +interrupt threads may be created by the application or may be added to the +simulated timer interrupt defined in tx_initialize_low_level.c. The following +format for creating simulated interrupts should be used: + +6.1 Data structures + +Here is an example of how to define the Linux data structures and prototypes +necessary to create a simulated interrupt thread: + +pthread_t _sample_linux_interrupt_thread; +void *_sample_linux_interrupt_entry(void *p); + +6.2 Creating a Simulated Interrupt Thread + +Here is an example of how to create a simulated interrupt thread in Linux. +This may be done inside of tx_initialize_low_level.c or from your application code + + +struct sched_param sp; + + /* Create the ISR thread */ + pthread_create(&_sample_linux_interrupt_thread, NULL, _sample_linux_interrupt_entry, &_sample_linux_interrupt_thread); + + /* Set up the ISR priority */ + sp.sched_priority = TX_LINUX_PRIORITY_ISR; + pthread_setschedparam(_sample_linux_interrupt_thread, SCHED_FIFO, &sp); + + + +6.3 Simulated Interrupt Thread Template + +The following is a template for the simulated interrupt thread. This interrupt will occur on +a periodic basis. + +void *_sample_linux_interrupt_entry(void *p) +{ +struct timespec ts; + + while(1) + { + + ts.tv_sec = 0; + ts.tv_nsec = 10000; + while(nanosleep(&ts, &ts)); + + /* Call ThreadX SMP context save for interrupt preparation. */ + _tx_thread_context_save(); + + /* Call the real ISR routine */ + _sample_linux_interrupt_isr(); + + /* Call ThreadX SMP context restore for interrupt completion. */ + _tx_thread_context_restore(); + } +} + + + +7. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +09-30-2020 Initial ThreadX SMP 6.1 version for Linux using GNU GCC tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports_smp/linux/gnu/src/tx_initialize_low_level.c b/ports_smp/linux/gnu/src/tx_initialize_low_level.c new file mode 100644 index 00000000..fb4e654a --- /dev/null +++ b/ports_smp/linux/gnu/src/tx_initialize_low_level.c @@ -0,0 +1,464 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include +#include +#include +#include +#include + + +/* Define various Linux objects used by the ThreadX port. */ + +TX_LINUX_MUTEX _tx_linux_mutex; +sem_t _tx_linux_scheduler_semaphore; +pthread_t _tx_linux_scheduler_id; +ULONG _tx_linux_global_int_disabled_flag; +struct timespec _tx_linux_time_stamp; +ULONG _tx_linux_system_error; +TX_THREAD_SMP_CORE_MAPPING _tx_linux_virtual_cores[TX_THREAD_SMP_MAX_CORES]; +extern UINT _tx_thread_preempt_disable; +extern TX_THREAD *_tx_thread_current_ptr[TX_THREAD_SMP_MAX_CORES]; +extern TX_THREAD *_tx_thread_execute_ptr[TX_THREAD_SMP_MAX_CORES]; +extern ULONG _tx_thread_system_state[TX_THREAD_SMP_MAX_CORES]; +extern TX_THREAD_SMP_PROTECT _tx_thread_smp_protection; + +/* Define signals for linux thread. */ +#define SUSPEND_SIG SIGUSR1 +#define RESUME_SIG SIGUSR2 + +static sigset_t _tx_linux_thread_wait_mask; +static __thread int _tx_linux_thread_suspended; +static sem_t _tx_linux_thread_timer_wait; +static sem_t _tx_linux_thread_other_wait; +static sem_t _tx_linux_sleep_sema; +__thread int _tx_linux_threadx_thread = 0; + +/* Define simulated timer interrupt. This is done inside a thread, which is + how other interrupts may be defined as well. See code below for an + example. */ + +pthread_t _tx_linux_timer_id; +sem_t _tx_linux_timer_semaphore; +sem_t _tx_linux_isr_semaphore; +void *_tx_linux_timer_interrupt(void *p); + + +#ifdef TX_LINUX_DEBUG_ENABLE + + +/* Define the maximum size of the Linux debug array. */ + +#ifndef TX_LINUX_DEBUG_EVENT_SIZE +#define TX_LINUX_DEBUG_EVENT_SIZE 400 +#endif + + +/* Define debug log in order to debug Linux issues with this port. */ + +typedef struct TX_LINUX_DEBUG_ENTRY_STRUCT +{ + char *tx_linux_debug_entry_action; + pthread_t tx_linux_debug_entry_running_id; + UINT tx_linux_debug_entry_core; + struct timespec tx_linux_debug_entry_timestamp; + char *tx_linux_debug_entry_file; + unsigned long tx_linux_debug_entry_line; + TX_LINUX_MUTEX tx_linux_debug_entry_mutex; + TX_THREAD_SMP_PROTECT tx_linux_debug_protection; + unsigned long tx_linux_debug_entry_int_disabled_flag; + UINT tx_linux_debug_entry_preempt_disable; + ULONG tx_linux_debug_entry_system_state[TX_THREAD_SMP_MAX_CORES]; + TX_THREAD *tx_linux_debug_entry_current_thread[TX_THREAD_SMP_MAX_CORES]; + pthread_t tx_linux_debug_entry_current_thread_id[TX_THREAD_SMP_MAX_CORES]; + TX_THREAD *tx_linux_debug_entry_execute_thread[TX_THREAD_SMP_MAX_CORES]; + pthread_t tx_linux_debug_entry_execute_thread_id[TX_THREAD_SMP_MAX_CORES]; +} TX_LINUX_DEBUG_ENTRY; + + +/* Define the circular array of Linux debug entries. */ + +TX_LINUX_DEBUG_ENTRY _tx_linux_debug_entry_array[TX_LINUX_DEBUG_EVENT_SIZE]; + + +/* Define the Linux debug index. */ + +unsigned long _tx_linux_debug_entry_index = 0; + + +/* Now define the debug entry function. */ +void _tx_linux_debug_entry_insert(char *action, char *file, unsigned long line) +{ +UINT i; + + /* Get the time stamp. */ + clock_gettime(CLOCK_REALTIME, &_tx_linux_time_stamp); + + /* Setup the debug entry. */ + _tx_linux_debug_entry_array[_tx_linux_debug_entry_index].tx_linux_debug_entry_action = action; + _tx_linux_debug_entry_array[_tx_linux_debug_entry_index].tx_linux_debug_entry_core = _tx_thread_smp_core_get(); + _tx_linux_debug_entry_array[_tx_linux_debug_entry_index].tx_linux_debug_entry_timestamp = _tx_linux_time_stamp; + _tx_linux_debug_entry_array[_tx_linux_debug_entry_index].tx_linux_debug_entry_file = file; + _tx_linux_debug_entry_array[_tx_linux_debug_entry_index].tx_linux_debug_entry_line = line; + _tx_linux_debug_entry_array[_tx_linux_debug_entry_index].tx_linux_debug_protection = _tx_thread_smp_protection; + _tx_linux_debug_entry_array[_tx_linux_debug_entry_index].tx_linux_debug_entry_preempt_disable = _tx_thread_preempt_disable; + _tx_linux_debug_entry_array[_tx_linux_debug_entry_index].tx_linux_debug_entry_mutex = _tx_linux_mutex; + _tx_linux_debug_entry_array[_tx_linux_debug_entry_index].tx_linux_debug_entry_int_disabled_flag = _tx_linux_global_int_disabled_flag; + _tx_linux_debug_entry_array[_tx_linux_debug_entry_index].tx_linux_debug_entry_running_id = pthread_self(); + for (i = 0; i < TX_THREAD_SMP_MAX_CORES; i++) + { + + _tx_linux_debug_entry_array[_tx_linux_debug_entry_index].tx_linux_debug_entry_system_state[i] = _tx_thread_system_state[i]; + _tx_linux_debug_entry_array[_tx_linux_debug_entry_index].tx_linux_debug_entry_current_thread[i] = _tx_thread_current_ptr[i]; + if (_tx_thread_current_ptr[i]) + _tx_linux_debug_entry_array[_tx_linux_debug_entry_index].tx_linux_debug_entry_current_thread_id[i] = _tx_thread_current_ptr[i] -> tx_thread_linux_thread_id; + else + _tx_linux_debug_entry_array[_tx_linux_debug_entry_index].tx_linux_debug_entry_current_thread_id[i] = 0; + _tx_linux_debug_entry_array[_tx_linux_debug_entry_index].tx_linux_debug_entry_execute_thread[i] = _tx_thread_execute_ptr[i]; + if (_tx_thread_execute_ptr[i]) + _tx_linux_debug_entry_array[_tx_linux_debug_entry_index].tx_linux_debug_entry_execute_thread_id[i] = _tx_thread_execute_ptr[i] -> tx_thread_linux_thread_id; + else + _tx_linux_debug_entry_array[_tx_linux_debug_entry_index].tx_linux_debug_entry_execute_thread_id[i] = 0; + } + + /* Now move to the next entry. */ + _tx_linux_debug_entry_index++; + + /* Determine if we need to wrap the list. */ + if (_tx_linux_debug_entry_index >= TX_LINUX_DEBUG_EVENT_SIZE) + { + + /* Yes, wrap the list! */ + _tx_linux_debug_entry_index = 0; + } +} + +#endif + + +/* Define the ThreadX timer interrupt handler. */ + +void _tx_timer_interrupt(void); + + +/* Define other external function references. */ + +VOID _tx_initialize_low_level(VOID); +VOID _tx_thread_context_save(VOID); +VOID _tx_thread_context_restore(VOID); + + +/* Define other external variable references. */ + +extern VOID *_tx_initialize_unused_memory; + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level SMP/Linux/GCC */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* sched_setaffinity */ +/* getpid */ +/* _tx_linux_thread_init */ +/* pthread_setschedparam */ +/* pthread_mutexattr_init */ +/* pthread_mutex_init */ +/* _tx_linux_thread_suspend */ +/* sem_init */ +/* pthread_create */ +/* printf */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_initialize_low_level(VOID) +{ +UINT i; +struct sched_param sp; +pthread_mutexattr_t attr; + +#ifdef TX_LINUX_MULTI_CORE +cpu_set_t mask; + + /* Limit this ThreadX simulation on Linux to a single core. */ + CPU_ZERO(&mask); + CPU_SET(0, &mask); + if (sched_setaffinity(getpid(), sizeof(mask), &mask) != 0) + { + + /* Error restricting the process to one core. */ + printf("ThreadX Linux error restricting the process to one core!\n"); + while(1) + { + } + } +#endif + + /* Pickup the first available memory address. */ + + /* Save the first available memory address. */ + _tx_initialize_unused_memory = malloc(TX_LINUX_MEMORY_SIZE); + + /* Pickup the unique Id of the current thread, which will also be the Id of the scheduler. */ + _tx_linux_scheduler_id = pthread_self(); + + /* Init Linux thread. */ + _tx_linux_thread_init(); + + /* Set priority and schedual of main thread. */ + sp.sched_priority = TX_LINUX_PRIORITY_SCHEDULE; + pthread_setschedparam(pthread_self(), SCHED_FIFO, &sp); + + /* Create the system mutex. This is used by the + scheduler thread (which is the main thread) to block all + other stuff out. */ + pthread_mutexattr_init(&attr); + pthread_mutexattr_settype(&attr, PTHREAD_MUTEX_ERRORCHECK); + pthread_mutex_init(&_tx_linux_mutex.tx_linux_mutex, &attr); + sem_init(&_tx_linux_scheduler_semaphore, 0, 0); + + /* Loop to clear the virtual core array, which is how we map threads to cores. */ + for (i = 0; i < TX_THREAD_SMP_MAX_CORES; i++) + { + + /* Clear this mapping entry. */ + _tx_linux_virtual_cores[i].tx_thread_smp_core_mapping_thread = TX_NULL; + _tx_linux_virtual_cores[i].tx_thread_smp_core_mapping_linux_thread_id = 0; + } + + /* Initialize the global interrupt disabled flag. */ + _tx_linux_global_int_disabled_flag = TX_FALSE; + + /* Create semaphore for timer thread. */ + sem_init(&_tx_linux_timer_semaphore, 0, 0); + + /* Create semaphore for ISR thread. */ + sem_init(&_tx_linux_isr_semaphore, 0, 0); + + /* Setup periodic timer interrupt. */ + if(pthread_create(&_tx_linux_timer_id, NULL, _tx_linux_timer_interrupt, &_tx_linux_timer_id)) + { + + /* Error creating the timer interrupt. */ + printf("ThreadX Linux error creating timer interrupt thread!\n"); + while(1) + { + } + } + + /* Otherwise, we have a good thread create. Now set the priority to + a level lower than the system thread but higher than the application + threads. */ + sp.sched_priority = TX_LINUX_PRIORITY_ISR; + pthread_setschedparam(_tx_linux_timer_id, SCHED_FIFO, &sp); + + /* Done, return to caller. */ +} + + +/* This routine is called after initialization is complete in order to start + all interrupt threads. Interrupt threads in addition to the timer may + be added to this routine as well. */ + +void _tx_initialize_start_interrupts(void) +{ + + /* Kick the timer thread off to generate the ThreadX periodic interrupt + source. */ + tx_linux_sem_post(&_tx_linux_timer_semaphore); +} + + +/* Define the ThreadX system timer interrupt. Other interrupts may be simulated + in a similar way. */ + +void *_tx_linux_timer_interrupt(void *p) +{ +struct timespec ts; +long timer_periodic_sec; +long timer_periodic_nsec; +int err; + + /* Calculate periodic timer. */ + timer_periodic_sec = 1 / TX_TIMER_TICKS_PER_SECOND; + timer_periodic_nsec = 1000000000 / TX_TIMER_TICKS_PER_SECOND; + nice(10); + + /* Wait startup semaphore. */ + tx_linux_sem_wait(&_tx_linux_timer_semaphore); + + while(1) + { + + clock_gettime(CLOCK_REALTIME, &ts); + ts.tv_nsec += timer_periodic_nsec; + if (ts.tv_nsec > 1000000000) + { + ts.tv_nsec -= 1000000000; + ts.tv_sec++; + } + do + { + if (sem_timedwait(&_tx_linux_timer_semaphore, &ts) == 0) + { + break; + } + err = errno; + } while (err != ETIMEDOUT); + + /* Call ThreadX context save for interrupt preparation. */ + _tx_thread_context_save(); + + /* Call the ThreadX system timer interrupt processing. */ + _tx_timer_interrupt(); + + /* Call ThreadX context restore for interrupt completion. */ + _tx_thread_context_restore(); + } +} + +/* Define functions for linux thread. */ +void _tx_linux_thread_resume_handler(int sig) +{ +} + +void _tx_linux_thread_suspend_handler(int sig) +{ + if(pthread_equal(pthread_self(), _tx_linux_timer_id)) + tx_linux_sem_post(&_tx_linux_thread_timer_wait); + else + tx_linux_sem_post(&_tx_linux_thread_other_wait); + + if(_tx_linux_thread_suspended) + return; + + _tx_linux_thread_suspended = 1; + sigsuspend(&_tx_linux_thread_wait_mask); + _tx_linux_thread_suspended = 0; +} + +void _tx_linux_thread_suspend(pthread_t thread_id) +{ + + /* Send signal. */ + _tx_linux_mutex_obtain(&_tx_linux_mutex); + pthread_kill(thread_id, SUSPEND_SIG); + _tx_linux_mutex_release(&_tx_linux_mutex); + + /* Wait until signal is received. */ + if(pthread_equal(thread_id, _tx_linux_timer_id)) + tx_linux_sem_wait(&_tx_linux_thread_timer_wait); + else + tx_linux_sem_wait(&_tx_linux_thread_other_wait); +} + +void _tx_linux_thread_resume(pthread_t thread_id) +{ + + /* Send signal. */ + _tx_linux_mutex_obtain(&_tx_linux_mutex); + pthread_kill(thread_id, RESUME_SIG); + _tx_linux_mutex_release(&_tx_linux_mutex); +} + +void _tx_linux_thread_init() +{ +struct sigaction sa; + + /* Create semaphore for linux thread. */ + sem_init(&_tx_linux_thread_timer_wait, 0, 0); + sem_init(&_tx_linux_thread_other_wait, 0, 0); + sem_init(&_tx_linux_sleep_sema, 0, 0); + + sigfillset(&_tx_linux_thread_wait_mask); + sigdelset(&_tx_linux_thread_wait_mask, RESUME_SIG); + + sigfillset(&sa.sa_mask); + sa.sa_flags = 0; + sa.sa_handler = _tx_linux_thread_resume_handler; + sigaction(RESUME_SIG, &sa, NULL); + + sa.sa_handler = _tx_linux_thread_suspend_handler; + sigaction(SUSPEND_SIG, &sa, NULL); +} + +void _tx_linux_thread_sleep(long ns) +{ +struct timespec ts; +int err; + + clock_gettime(CLOCK_REALTIME, &ts); + ts.tv_nsec += ns; + if (ts.tv_nsec > 1000000000) + { + ts.tv_nsec -= 1000000000; + ts.tv_sec++; + } + do + { + if (sem_timedwait(&_tx_linux_sleep_sema, &ts) == 0) + { + break; + } + err = errno; + } while (err != ETIMEDOUT); +} diff --git a/ports_smp/linux/gnu/src/tx_thread_context_restore.c b/ports_smp/linux/gnu/src/tx_thread_context_restore.c new file mode 100644 index 00000000..2ff43b75 --- /dev/null +++ b/ports_smp/linux/gnu/src/tx_thread_context_restore.c @@ -0,0 +1,176 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" + +extern sem_t _tx_linux_isr_semaphore; +UINT _tx_linux_timer_waiting = 0; +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore SMP/Linux/GCC */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores the interrupt context if it is processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_linux_debug_entry_insert */ +/* _tx_linux_mutex_obtain */ +/* sem_trywait */ +/* tx_linux_sem_post */ +/* tx_linux_sem_wait */ +/* _tx_linux_thread_resume */ +/* _tx_linux_mutex_release_all */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_context_restore(VOID) +{ + +TX_THREAD *current_thread; + + /* The critical section is already in force at this point. */ + + /* Debug entry. */ + _tx_linux_debug_entry_insert("CONTEXT_RESTORE", __FILE__, __LINE__); + + /* For Linux, ISRs are always mapped to core 0. */ + + /* Decrement the nested interrupt count. */ + _tx_thread_system_state[0]--; + + /* Pickup current thread. */ + current_thread = _tx_thread_current_ptr[0]; + + /* Determine if this is the first nested interrupt and if a ThreadX + application thread was running at the time. */ + if ((!_tx_thread_system_state[0]) && (current_thread)) + { + + /* Yes, this is the first and last interrupt processed. */ + + /* Check to see if preemption is required. */ + if ((_tx_thread_preempt_disable == 0) && (current_thread != _tx_thread_execute_ptr[0])) + { + + /* Preempt the running application thread. We don't need to suspend the + application thread since that is done in the context save processing. */ + + /* Indicate that this thread was suspended asynchronously. */ + current_thread -> tx_thread_linux_suspension_type = 1; + + /* Save the remaining time-slice and disable it. */ + if (_tx_timer_time_slice[0]) + { + + current_thread -> tx_thread_time_slice = _tx_timer_time_slice[0]; + _tx_timer_time_slice[0] = 0; + } + + /* Clear the current thread pointer. */ + _tx_thread_current_ptr[0] = TX_NULL; + + /* Clear this mapping entry. */ + _tx_linux_virtual_cores[0].tx_thread_smp_core_mapping_thread = TX_NULL; + _tx_linux_virtual_cores[0].tx_thread_smp_core_mapping_linux_thread_id = 0; + + /* Indicate that this thread is now ready for scheduling again by another core. */ + current_thread -> tx_thread_smp_core_control = 1; + + /* Make sure semaphore is 0. */ + while(!sem_trywait(&_tx_linux_scheduler_semaphore)); + + /* Indicate it is in timer ISR. */ + _tx_linux_timer_waiting = 1; + + /* Wakeup the system thread by setting the system semaphore. */ + tx_linux_sem_post(&_tx_linux_scheduler_semaphore); + + if(_tx_thread_execute_ptr[0]) + { + if(_tx_thread_execute_ptr[0] -> tx_thread_linux_suspension_type == 2) + { + + /* Unlock linux mutex. */ + _tx_linux_mutex_release_all(&_tx_linux_mutex); + + /* Wait until TX_THREAD start running. */ + tx_linux_sem_wait(&_tx_linux_isr_semaphore); + + _tx_linux_mutex_obtain(&_tx_linux_mutex); + + /* Make sure semaphore is 0. */ + while(!sem_trywait(&_tx_linux_isr_semaphore)); + } + } + + /* Indicate it is not in timer ISR. */ + _tx_linux_timer_waiting = 0; + } + else + { + + /* Since preemption is not required, resume the interrupted thread. */ + _tx_linux_thread_resume(current_thread -> tx_thread_linux_thread_id); + } + } + + /* Unlock linux mutex. */ + _tx_thread_smp_unprotect(TX_INT_ENABLE); +} + diff --git a/ports_smp/linux/gnu/src/tx_thread_context_save.c b/ports_smp/linux/gnu/src/tx_thread_context_save.c new file mode 100644 index 00000000..0dce9434 --- /dev/null +++ b/ports_smp/linux/gnu/src/tx_thread_context_save.c @@ -0,0 +1,128 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save SMP/Linux/GCC */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_linux_debug_entry_insert */ +/* _tx_linux_mutex_obtain */ +/* _tx_linux_thread_suspend */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_context_save(VOID) +{ + +TX_THREAD *thread_ptr; +UINT interrupt_posture; + + /* Loop to perform retries on thread preemption. */ + while(1) + { + + /* Lock mutex to ensure other threads are not playing with + the core ThreadX data structures. */ + interrupt_posture = _tx_thread_smp_protect(); + + /* Check for a system error condition. */ + if (interrupt_posture != TX_FALSE) + { + + /* This should not happen... increment the system error counter. */ + _tx_linux_system_error++; + } + + /* Debug entry. */ + _tx_linux_debug_entry_insert("CONTEXT_SAVE", __FILE__, __LINE__); + + /* All ISRs are assumed to be serviced on core 0. */ + + /* Pickup the current thread pointer. */ + thread_ptr = _tx_thread_current_ptr[0]; + + /* If an application thread is running, suspend it to simulate preemption. */ + if ((thread_ptr) && (_tx_thread_system_state[0] == 0)) + { + + /* Yes, this is the first interrupt and an application thread is running... + suspend it! */ + _tx_linux_thread_suspend(thread_ptr -> tx_thread_linux_thread_id); + + /* Debug entry. */ + _tx_linux_debug_entry_insert("CONTEXT_SAVE-suspend_thread", __FILE__, __LINE__); + } + + /* Increment the nested interrupt condition. */ + _tx_thread_system_state[0]++; + + /* Do not release the protection for ISRs, since in SMP mode other threads might be scheduled on + interrupted virtual core 0, which will confuse ThreadX. */ + + /* Get out of the loop. */ + break; + } +} + diff --git a/ports_smp/linux/gnu/src/tx_thread_interrupt_control.c b/ports_smp/linux/gnu/src/tx_thread_interrupt_control.c new file mode 100644 index 00000000..77cc2e17 --- /dev/null +++ b/ports_smp/linux/gnu/src/tx_thread_interrupt_control.c @@ -0,0 +1,205 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + +/* Define small routines used for the TX_DISABLE/TX_RESTORE macros. */ + +UINT _tx_thread_interrupt_disable(void) +{ + +UINT previous_value; + + + previous_value = _tx_thread_interrupt_control(TX_INT_DISABLE); + return(previous_value); +} + + +VOID _tx_thread_interrupt_restore(UINT previous_posture) +{ + + previous_posture = _tx_thread_interrupt_control(previous_posture); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control SMP/Linux/GCC */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* _tx_linux_mutex_obtain */ +/* pthread_self */ +/* pthread_getschedparam */ +/* _tx_linux_mutex_release_all */ +/* pthread_exit */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _tx_thread_interrupt_control(UINT new_posture) +{ + +UINT old_posture; +TX_THREAD *thread_ptr; +pthread_t thread_id; +int exit_code = 0; +UINT core; + + + /* Lock Linux mutex. */ + _tx_linux_mutex_obtain(&_tx_linux_mutex); + +#ifdef TX_LINUX_DEBUG_ENABLE + + /* Determine if this is a disable or enable request. */ + if (new_posture == TX_INT_ENABLE) + { + + /* Enable. */ + _tx_linux_debug_entry_insert("RESTORE", __FILE__, __LINE__); + } + else + { + + /* Disable. */ + _tx_linux_debug_entry_insert("DISABLE", __FILE__, __LINE__); + } +#endif + + /* Pickup the id of the current thread. */ + thread_id = pthread_self(); + + /* Get the currently running virtual core. */ + core = _tx_thread_smp_core_get(); + + /* Pickup the current thread pointer. */ + thread_ptr = _tx_thread_current_ptr[core]; + + /* Determine if this is a thread and it does not + match the current thread pointer. */ + if ((_tx_linux_threadx_thread) && + ((!thread_ptr) || (!pthread_equal(thread_ptr -> tx_thread_linux_thread_id, thread_id)))) + { + + /* This indicates the Linux thread was actually terminated by ThreadX is only + being allowed to run in order to cleanup its resources. */ + /* Unlock linux mutex. */ + _tx_linux_mutex_release_all(&_tx_linux_mutex); + pthread_exit((void *)&exit_code); + } + + /* Determine the current interrupt lockout condition. */ + if (_tx_linux_mutex.tx_linux_mutex_nested_count == 1) + { + + /* Interrupts are enabled. */ + old_posture = TX_INT_ENABLE; + } + else + { + + /* Interrupts are disabled. */ + old_posture = TX_INT_DISABLE; + } + + /* First, determine if this call is from a non-thread. */ + if (_tx_thread_system_state[core]) + { + + /* Determine how to apply the new posture. */ + if (new_posture == TX_INT_ENABLE) + { + + /* Clear the disabled flag. */ + _tx_linux_global_int_disabled_flag = TX_FALSE; + + /* Determine if the critical section is locked. */ + _tx_linux_mutex_release_all(&_tx_linux_mutex); + } + else if (new_posture == TX_INT_DISABLE) + { + + /* Set the disabled flag. */ + _tx_linux_global_int_disabled_flag = TX_TRUE; + } + } + else if (thread_ptr) + { + + /* Determine how to apply the new posture. */ + if (new_posture == TX_INT_ENABLE) + { + + /* Clear the disabled flag. */ + thread_ptr -> tx_thread_linux_int_disabled_flag = TX_FALSE; + + /* Determine if the critical section is locked. */ + _tx_linux_mutex_release_all(&_tx_linux_mutex); + } + else if (new_posture == TX_INT_DISABLE) + { + + /* Set the disabled flag. */ + thread_ptr -> tx_thread_linux_int_disabled_flag = TX_TRUE; + } + } + + /* Return the previous interrupt disable posture. */ + return(old_posture); +} + diff --git a/ports_smp/linux/gnu/src/tx_thread_schedule.c b/ports_smp/linux/gnu/src/tx_thread_schedule.c new file mode 100644 index 00000000..4e518c63 --- /dev/null +++ b/ports_smp/linux/gnu/src/tx_thread_schedule.c @@ -0,0 +1,519 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +#include +#include + +extern sem_t _tx_linux_isr_semaphore; +extern UINT _tx_linux_timer_waiting; +extern pthread_t _tx_linux_timer_id; +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule SMP/Linux/GCC */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_linux_mutex_obtain */ +/* _tx_linux_debug_entry_insert */ +/* _tx_linux_thread_resume */ +/* tx_linux_sem_post */ +/* sem_trywait */ +/* tx_linux_sem_wait */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_schedule(VOID) +{ +UINT core; +TX_THREAD *current_thread; +TX_THREAD *execute_thread; +struct timespec ts; +UCHAR preemt_retry = TX_FALSE; + + /* Loop forever. */ + while(1) + { + + /* Lock Linux mutex. */ + _tx_linux_mutex_obtain(&_tx_linux_mutex); + + /* Check for a system error condition. */ + if (_tx_linux_global_int_disabled_flag != TX_FALSE) + { + + /* This should not happen... increment the system error counter. */ + _tx_linux_system_error++; + } + + /* Debug entry. */ + _tx_linux_debug_entry_insert("SCHEDULE-wake_up", __FILE__, __LINE__); + + /* Loop through each virtual core to look for an idle core. */ + for (core = 0; core < TX_THREAD_SMP_MAX_CORES; core++) + { + + /* Pickup the current thread pointer for this core. */ + current_thread = _tx_thread_current_ptr[core]; + + /* Determine if the thread's deferred preemption flag is set. */ + if ((current_thread) && (current_thread -> tx_thread_linux_deferred_preempt)) + { + if (_tx_thread_preempt_disable) + { + + /* Preemption disabled. Retry. */ + preemt_retry = TX_TRUE; + break; + } + + if (current_thread -> tx_thread_state != TX_TERMINATED) + { + + /* Suspend the thread to simulate preemption. Note that the thread is suspended BEFORE the protection get + flag is checked to ensure there is not a race condition between this thread and the update of that flag. */ + _tx_linux_thread_suspend(current_thread -> tx_thread_linux_thread_id); + + /* Clear the preemption flag. */ + current_thread -> tx_thread_linux_deferred_preempt = TX_FALSE; + + /* Indicate that this thread was suspended asynchronously. */ + current_thread -> tx_thread_linux_suspension_type = 1; + + /* Save the remaining time-slice and disable it. */ + if (_tx_timer_time_slice[core]) + { + + current_thread -> tx_thread_time_slice = _tx_timer_time_slice[core]; + _tx_timer_time_slice[core] = 0; + } + } + + /* Clear the current thread pointer. */ + _tx_thread_current_ptr[core] = TX_NULL; + + /* Clear this mapping entry. */ + _tx_linux_virtual_cores[core].tx_thread_smp_core_mapping_thread = TX_NULL; + _tx_linux_virtual_cores[core].tx_thread_smp_core_mapping_linux_thread_id = 0; + + /* Indicate that this thread is now ready for scheduling again by another core. */ + current_thread -> tx_thread_smp_core_control = 1; + + /* Debug entry. */ + _tx_linux_debug_entry_insert("SCHEDULE-core_preempt_complete", __FILE__, __LINE__); + } + + /* Determine if this core is idle. */ + if (_tx_thread_current_ptr[core] == TX_NULL) + { + + /* Yes, this core is idle, determine if there is a thread that can be scheduled for it. */ + + /* Pickup the execute thread pointer. */ + execute_thread = _tx_thread_execute_ptr[core]; + + /* Is there a thread that is ready to execute on this core? */ + if ((execute_thread) && (execute_thread -> tx_thread_smp_core_control)) + { + + /* Yes! We have a thread to execute. Note that the critical section is already + active from the scheduling loop above. */ + + /* Setup the current thread pointer. */ + _tx_thread_current_ptr[core] = execute_thread; + + /* Remember the virtual core in the thread control block. */ + execute_thread -> tx_thread_linux_virtual_core = core; + + /* Setup the virtual core mapping structure. */ + _tx_linux_virtual_cores[core].tx_thread_smp_core_mapping_thread = execute_thread; + _tx_linux_virtual_cores[core].tx_thread_smp_core_mapping_linux_thread_id = execute_thread -> tx_thread_linux_thread_id; + + /* Clear the execution control flag. */ + execute_thread -> tx_thread_smp_core_control = 0; + + /* Increment the run count for this thread. */ + execute_thread -> tx_thread_run_count++; + + /* Setup time-slice, if present. */ + _tx_timer_time_slice[core] = execute_thread -> tx_thread_time_slice; + + /* Determine how the thread was last suspended. */ + if (execute_thread -> tx_thread_linux_suspension_type == 1) + { + + /* Clear the suspension type. */ + execute_thread -> tx_thread_linux_suspension_type = 0; + + /* Debug entry. */ + _tx_linux_debug_entry_insert("SCHEDULE-resume_thread", __FILE__, __LINE__); + + /* Pseudo interrupt suspension. The thread is not waiting on + its run semaphore. */ + _tx_linux_thread_resume(execute_thread -> tx_thread_linux_thread_id); + } + else if (execute_thread -> tx_thread_linux_suspension_type == 2) + { + + /* Clear the suspension type. */ + execute_thread -> tx_thread_linux_suspension_type = 0; + + /* Debug entry. */ + _tx_linux_debug_entry_insert("SCHEDULE-release_sem", __FILE__, __LINE__); + + /* Make sure semaphore is 0. */ + while(!sem_trywait(&execute_thread -> tx_thread_linux_thread_run_semaphore)); + + /* Let the thread run again by releasing its run semaphore. */ + tx_linux_sem_post(&execute_thread -> tx_thread_linux_thread_run_semaphore); + + /* Block timer ISR. */ + if(_tx_linux_timer_waiting) + { + + /* It is woken up by timer ISR. */ + /* Let ThreadX thread wake up first. */ + tx_linux_sem_wait(&_tx_linux_scheduler_semaphore); + + /* Wake up timer ISR. */ + tx_linux_sem_post(&_tx_linux_isr_semaphore); + } + else + { + + /* It is woken up by TX_THREAD. */ + /* Suspend timer thread and let ThreadX thread wake up first. */ + _tx_linux_thread_suspend(_tx_linux_timer_id); + tx_linux_sem_wait(&_tx_linux_scheduler_semaphore); + _tx_linux_thread_resume(_tx_linux_timer_id); + + } + } + else + { + + /* System error, increment the counter. */ + _tx_linux_system_error++; + } + } + } + } + + if (preemt_retry) + { + + /* Unlock linux mutex. */ + _tx_linux_mutex_release_all(&_tx_linux_mutex); + + /* Let user thread run to reset _tx_thread_preempt_disable. */ + _tx_linux_thread_sleep(1); + + preemt_retry = TX_FALSE; + + continue; + } + + /* Debug entry. */ + _tx_linux_debug_entry_insert("SCHEDULE-self_suspend_sem", __FILE__, __LINE__); + + /* Unlock linux mutex. */ + _tx_linux_mutex_release_all(&_tx_linux_mutex); + + /* Now suspend the main thread so the application thread can run. */ + clock_gettime(CLOCK_REALTIME, &ts); + ts.tv_nsec += 2000000; + if (ts.tv_nsec >= 1000000000) + { + ts.tv_nsec -= 1000000000; + ts.tv_sec++; + } + tx_linux_sem_timedwait(&_tx_linux_scheduler_semaphore, &ts); + clock_gettime(CLOCK_REALTIME, &ts); + } +} + + +/* Define the ThreadX Linux mutex get, release, and release all functions. */ + +void _tx_linux_mutex_obtain(TX_LINUX_MUTEX *mutex) +{ + +TX_THREAD *thread_ptr; +pthread_t current_thread_id; +UINT i; + + /* Pickup the current thread ID. */ + current_thread_id = pthread_self(); + + /* Is the protection owned? */ + if (mutex -> tx_linux_mutex_owner == current_thread_id) + { + + /* Simply increment the nested counter. */ + mutex -> tx_linux_mutex_nested_count++; + } + else + { + + /* Loop to find a thread matching this ID. */ + i = 0; + do + { + + /* Pickup the thread pointer. */ + thread_ptr = _tx_thread_current_ptr[i]; + + /* Is this thread obtaining the mutex? */ + if ((thread_ptr) && (thread_ptr -> tx_thread_linux_thread_id == current_thread_id)) + { + + /* We have found the thread, get out of the loop. */ + break; + } + + /* Look at next core. */ + i++; + + } while (i < TX_THREAD_SMP_MAX_CORES); + + /* Determine if we found a thread. */ + if (i >= TX_THREAD_SMP_MAX_CORES) + { + + /* Set the thread pointer to NULL to indicate a thread was not found. */ + thread_ptr = TX_NULL; + } + + /* If a thread was found, indicate the thread is attempting to access the mutex. */ + if (thread_ptr) + { + + /* Yes, current ThreadX thread attempting to get the mutex - set the flag. */ + thread_ptr -> tx_thread_linux_mutex_access = TX_TRUE; + } + + /* Get the Linux mutex. */ + pthread_mutex_lock(&mutex -> tx_linux_mutex); + + /* At this point we have the mutex. */ + + /* Clear the mutex access flag for the thread. */ + if (thread_ptr) + { + + /* Yes, clear the current ThreadX thread attempting to get the mutex. */ + thread_ptr -> tx_thread_linux_mutex_access = TX_FALSE; + } + + /* Increment the nesting counter. */ + mutex -> tx_linux_mutex_nested_count = 1; + + /* Remember the owner. */ + mutex -> tx_linux_mutex_owner = pthread_self(); + } +} + + +void _tx_linux_mutex_release(TX_LINUX_MUTEX *mutex) +{ + +pthread_t current_thread_id; + + + /* Pickup the current thread ID. */ + current_thread_id = pthread_self(); + + /* Ensure the caller is the mutex owner. */ + if (mutex -> tx_linux_mutex_owner == current_thread_id) + { + + /* Determine if there is protection. */ + if (mutex -> tx_linux_mutex_nested_count) + { + + /* Decrement the nesting counter. */ + mutex -> tx_linux_mutex_nested_count--; + + /* Determine if the critical section is now being released. */ + if (mutex -> tx_linux_mutex_nested_count == 0) + { + + /* Yes, it is being released clear the owner. */ + mutex -> tx_linux_mutex_owner = 0; + + /* Finally, release the mutex. */ + if (pthread_mutex_unlock(&mutex -> tx_linux_mutex) != 0) + { + + /* Increment the system error counter. */ + _tx_linux_system_error++; + } + + /* Just in case, make sure there the mutex is not owned. */ + while (pthread_mutex_unlock(&mutex -> tx_linux_mutex) == 0) + { + + /* Increment the system error counter. */ + _tx_linux_system_error++; + } + + /* Relinquish to other ready threads. */ + _tx_linux_thread_sleep(1000); + } + } + } + else + { + + /* Increment the system error counter. */ + _tx_linux_system_error++; + } +} + + +void _tx_linux_mutex_release_all(TX_LINUX_MUTEX *mutex) +{ + + /* Ensure the caller is the mutex owner. */ + if (mutex -> tx_linux_mutex_owner == pthread_self()) + { + + /* Determine if there is protection. */ + if (mutex -> tx_linux_mutex_nested_count) + { + + /* Clear the nesting counter. */ + mutex -> tx_linux_mutex_nested_count = 0; + + /* Yes, it is being release clear the owner. */ + mutex -> tx_linux_mutex_owner = 0; + + /* Finally, release the mutex. */ + if (pthread_mutex_unlock(&mutex -> tx_linux_mutex) != 0) + { + + /* Increment the system error counter. */ + _tx_linux_system_error++; + } + + /* Just in case, make sure there the mutex is not owned. */ + while (pthread_mutex_unlock(&mutex -> tx_linux_mutex) == 0) + { + + /* Increment the system error counter. */ + _tx_linux_system_error++; + } + } + } + else + { + + /* Increment the system error counter. */ + _tx_linux_system_error++; + } +} + +void _tx_thread_delete_port_completion(TX_THREAD *thread_ptr, UINT tx_interrupt_save) +{ +INT linux_status; +sem_t *threadrunsemaphore; +pthread_t thread_id; + thread_id = thread_ptr -> tx_thread_linux_thread_id; + threadrunsemaphore = &(thread_ptr -> tx_thread_linux_thread_run_semaphore); + _tx_thread_smp_unprotect(tx_interrupt_save); + do + { + linux_status = pthread_cancel(thread_id); + if(linux_status != EAGAIN) + { + break; + } + _tx_linux_thread_resume(thread_id); + tx_linux_sem_post(threadrunsemaphore); + _tx_linux_thread_sleep(1000000); + } while (1); + pthread_join(thread_id, NULL); + sem_destroy(threadrunsemaphore); + tx_interrupt_save = _tx_thread_smp_protect(); +} + +void _tx_thread_reset_port_completion(TX_THREAD *thread_ptr, UINT tx_interrupt_save) +{ +INT linux_status; +sem_t *threadrunsemaphore; +pthread_t thread_id; + thread_id = thread_ptr -> tx_thread_linux_thread_id; + threadrunsemaphore = &(thread_ptr -> tx_thread_linux_thread_run_semaphore); + _tx_thread_smp_unprotect(tx_interrupt_save); + do + { + linux_status = pthread_cancel(thread_id); + if(linux_status != EAGAIN) + { + break; + } + _tx_linux_thread_resume(thread_id); + tx_linux_sem_post(threadrunsemaphore); + _tx_linux_thread_sleep(1000000); + } while (1); + pthread_join(thread_id, NULL); + sem_destroy(threadrunsemaphore); + tx_interrupt_save = _tx_thread_smp_protect(); +} diff --git a/ports_smp/linux/gnu/src/tx_thread_smp_core_get.c b/ports_smp/linux/gnu/src/tx_thread_smp_core_get.c new file mode 100644 index 00000000..8b4b94b0 --- /dev/null +++ b/ports_smp/linux/gnu/src/tx_thread_smp_core_get.c @@ -0,0 +1,113 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_core_get SMP/Linux/GCC */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets the currently running core number and returns it.*/ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* Core ID */ +/* */ +/* CALLS */ +/* */ +/* pthread_self Get Linux thread ID */ +/* _tx_linux_mutex_obtain */ +/* _tx_linux_mutex_release */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Source */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _tx_thread_smp_core_get(void) +{ + +UINT core; +UINT i; +pthread_t thread_id; + + + /* Lock Linux mutex. */ + _tx_linux_mutex_obtain(&_tx_linux_mutex); + + /* Default to core 0 for ISRs and initialization. */ + core = 0; + + /* Pickup the currently executing thread ID. */ + thread_id = pthread_self(); + + /* Loop through mapping table to find the core running this thread ID. */ + for (i = 0; i < TX_THREAD_SMP_MAX_CORES; i++) + { + + /* Does this core match? */ + if (_tx_linux_virtual_cores[i].tx_thread_smp_core_mapping_linux_thread_id == thread_id) + { + + /* Yes, we have a match. */ + core = i; + + /* Get out of loop. */ + break; + } + } + + /* Unlock linux mutex. */ + _tx_linux_mutex_release(&_tx_linux_mutex); + + /* Return the core ID. */ + return(core); +} + diff --git a/ports_smp/linux/gnu/src/tx_thread_smp_core_preempt.c b/ports_smp/linux/gnu/src/tx_thread_smp_core_preempt.c new file mode 100644 index 00000000..a881087f --- /dev/null +++ b/ports_smp/linux/gnu/src/tx_thread_smp_core_preempt.c @@ -0,0 +1,107 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_core_preempt SMP/Linux/GCC */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function preempts the specified core in situations where the */ +/* thread corresponding to this core is no longer ready or when the */ +/* core must be used for a higher-priority thread. If the specified is */ +/* the current core, this processing is skipped since the will give up */ +/* control subsequently on its own. */ +/* */ +/* INPUT */ +/* */ +/* core The core to preempt */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* ReleaseSemaphore Let scheduler run to preempt */ +/* thread on core */ +/* _tx_win32_debug_entry_insert Make debug log entry */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Source */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +void _tx_thread_smp_core_preempt(UINT core) +{ + +TX_THREAD *preempt_thread; + + + /* Protection is in force at this point. */ + + /* Pickup the thread pointer on the selected core. */ + preempt_thread = _tx_thread_current_ptr[core]; + + /* Determine if there is a thread to preempt. */ + if (preempt_thread) + { + + /* Yes, set the deferred preemption flag for this thread. This preemption will be + completed in the scheduler. */ + preempt_thread -> tx_thread_linux_deferred_preempt = TX_TRUE; + + /* Debug entry. */ + _tx_linux_debug_entry_insert("CORE_PREEMPT_deferred", __FILE__, __LINE__); + + /* Release the semaphore that the main scheduling thread is waiting + on. Note that the main scheduling algorithm will take care of + preempting the thread on this core. */ + tx_linux_sem_post(&_tx_linux_scheduler_semaphore); + } +} + + diff --git a/ports_smp/linux/gnu/src/tx_thread_smp_current_state_get.c b/ports_smp/linux/gnu/src/tx_thread_smp_current_state_get.c new file mode 100644 index 00000000..024c3457 --- /dev/null +++ b/ports_smp/linux/gnu/src/tx_thread_smp_current_state_get.c @@ -0,0 +1,119 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_current_state_get SMP/Linux/GCC */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is gets the current state of the calling core. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* pthread_self Get Linux thread ID */ +/* _tx_linux_mutex_obtain */ +/* _tx_linux_mutex_release */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _tx_thread_smp_current_state_get(void) +{ + +UINT core; +UINT i; +ULONG current_state; +pthread_t thread_id; + + + /* Lock Linux mutex. */ + _tx_linux_mutex_obtain(&_tx_linux_mutex); + + /* Default to core 0 for ISRs and initialization. */ + core = 0; + + /* Pickup the currently executing thread ID. */ + thread_id = pthread_self(); + + /* Loop through mapping table to find the core running this thread ID. */ + for (i = 0; i < TX_THREAD_SMP_MAX_CORES; i++) + { + + /* Does this core match? */ + if (_tx_linux_virtual_cores[i].tx_thread_smp_core_mapping_linux_thread_id == thread_id) + { + + /* Yes, we have a match. */ + core = i; + + /* Get out of loop. */ + break; + } + } + + /* Pickup the current state. */ + current_state = _tx_thread_system_state[core]; + + /* Unlock linux mutex. */ + _tx_linux_mutex_release(&_tx_linux_mutex); + + /* Now return the state for the core. */ + return(current_state); +} + + + diff --git a/ports_smp/linux/gnu/src/tx_thread_smp_current_thread_get.c b/ports_smp/linux/gnu/src/tx_thread_smp_current_thread_get.c new file mode 100644 index 00000000..2b4de4d1 --- /dev/null +++ b/ports_smp/linux/gnu/src/tx_thread_smp_current_thread_get.c @@ -0,0 +1,116 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_current_thread_get SMP/Linux/GCC */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is gets the current thread of the calling core. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* Current Thread Pointer Pointer to the current thread */ +/* */ +/* CALLS */ +/* */ +/* pthread_self Get Linux thread ID */ +/* _tx_linux_mutex_obtain */ +/* _tx_linux_mutex_release */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +TX_THREAD *_tx_thread_smp_current_thread_get(void) +{ +UINT core; +UINT i; +pthread_t thread_id; +TX_THREAD *current_thread; + + + /* Lock Linux mutex. */ + _tx_linux_mutex_obtain(&_tx_linux_mutex); + + /* Default to core 0 for ISRs and initialization. */ + core = 0; + + /* Pickup the currently executing thread ID. */ + thread_id = pthread_self(); + + /* Loop through mapping table to find the core running this thread ID. */ + for (i = 0; i < TX_THREAD_SMP_MAX_CORES; i++) + { + + /* Does this core match? */ + if (_tx_linux_virtual_cores[i].tx_thread_smp_core_mapping_linux_thread_id == thread_id) + { + + /* Yes, we have a match. */ + core = i; + + /* Get out of loop. */ + break; + } + } + + /* Pickup current thread. */ + current_thread = _tx_thread_current_ptr[core]; + + /* Unlock linux mutex. */ + _tx_linux_mutex_release(&_tx_linux_mutex); + + /* Now return the current thread for the core. */ + return(current_thread); +} + diff --git a/ports_smp/linux/gnu/src/tx_thread_smp_initialize_wait.c b/ports_smp/linux/gnu/src/tx_thread_smp_initialize_wait.c new file mode 100644 index 00000000..520ab301 --- /dev/null +++ b/ports_smp/linux/gnu/src/tx_thread_smp_initialize_wait.c @@ -0,0 +1,79 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_initialize_wait SMP/Linux/GCC */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is the place where additional cores wait until */ +/* initialization is complete before they enter the thread scheduling */ +/* loop. */ +/* */ +/* Note: Since Linux uses virtual cores, there is nothing to do here. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Hardware */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +void _tx_thread_smp_initialize_wait(void) +{ + +} diff --git a/ports_smp/linux/gnu/src/tx_thread_smp_low_level_initialize.c b/ports_smp/linux/gnu/src/tx_thread_smp_low_level_initialize.c new file mode 100644 index 00000000..3ce969be --- /dev/null +++ b/ports_smp/linux/gnu/src/tx_thread_smp_low_level_initialize.c @@ -0,0 +1,79 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_low_level_initialize SMP/Linux/GCC */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function performs low-level initialization of the booting */ +/* core. */ +/* */ +/* Note: Since Linux uses virtual cores, there is nothing to do here. */ +/* */ +/* INPUT */ +/* */ +/* number_of_cores Number of cores */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_high_level ThreadX high-level init */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +void _tx_thread_smp_low_level_initialize(UINT number_of_cores) +{ + +} + diff --git a/ports_smp/linux/gnu/src/tx_thread_smp_protect.c b/ports_smp/linux/gnu/src/tx_thread_smp_protect.c new file mode 100644 index 00000000..d5119fc0 --- /dev/null +++ b/ports_smp/linux/gnu/src/tx_thread_smp_protect.c @@ -0,0 +1,255 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_protect SMP/Linux/GCC */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets protection for running inside the ThreadX */ +/* source. This is acomplished by a combination of a test-and-set */ +/* flag and periodically disabling interrupts. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* Previous Status Register */ +/* */ +/* CALLS */ +/* */ +/* pthread_self Get Linux thread ID */ +/* GetThreadPriority Get current thread priority */ +/* _tx_thread_smp_core_get Get the current core ID */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Source */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _tx_thread_smp_protect(void) +{ + +pthread_t current_thread_id; +int exit_code = 0; +struct sched_param sp; +UINT core; +UINT interrupt_posture; +TX_THREAD *current_thread; +UINT current_state; + + /* Loop to attempt to get the protection. */ + do + { + + /* First, get the critical section. */ + do + { + + + /* Lock Linux mutex. */ + _tx_linux_mutex_obtain(&_tx_linux_mutex); + + /* Pickup the current thread ID. */ + current_thread_id = pthread_self(); + + /* Pickup the current core. */ + core = _tx_thread_smp_core_get(); + + /* Pickup the current thread pointer. */ + current_thread = _tx_thread_current_ptr[core]; + + /* Determine if this is a thread (THREAD_PRIORITY_LOWEST) and it does not + match the current thread pointer. */ + if ((_tx_linux_threadx_thread) && + ((!current_thread) || (current_thread -> tx_thread_linux_thread_id != current_thread_id))) + { + + /* This indicates the Linux thread was actually terminated by ThreadX is only + being allowed to run in order to cleanup its resources. */ + _tx_linux_mutex_release_all(&_tx_linux_mutex); + + /* Exit this thread. */ + pthread_exit((void *)&exit_code); + } + + /* Determine if this is not actually a thread. */ + if (!_tx_linux_threadx_thread) + break; + + /* Now check for terminated or completed state... and preempt disable is not set! */ + if ((current_thread) && (_tx_thread_preempt_disable == 0)) + { + + /* Pickup current state. */ + current_state = current_thread -> tx_thread_state; + + /* Now check for terminated or completed state. */ + if ((current_state == TX_TERMINATED) || (current_state == TX_COMPLETED)) + { + + /* Clear the preemption flag. */ + current_thread -> tx_thread_linux_deferred_preempt = TX_FALSE; + + /* Indicate that this thread was suspended asynchronously. */ + current_thread -> tx_thread_linux_suspension_type = 1; + + /* Save the remaining time-slice and disable it. */ + if (_tx_timer_time_slice[core]) + { + + current_thread -> tx_thread_time_slice = _tx_timer_time_slice[core]; + _tx_timer_time_slice[core] = 0; + } + + /* Clear the current thread pointer. */ + _tx_thread_current_ptr[core] = TX_NULL; + + /* Clear this mapping entry. */ + _tx_linux_virtual_cores[core].tx_thread_smp_core_mapping_thread = TX_NULL; + _tx_linux_virtual_cores[core].tx_thread_smp_core_mapping_linux_thread_id = 0; + + /* Indicate that this thread is now ready for scheduling again by another core. */ + current_thread -> tx_thread_smp_core_control = 1; + + /* Debug entry. */ + _tx_linux_debug_entry_insert("SCHEDULE-thread_terminate_preempt_complete", __FILE__, __LINE__); + + /* Release the scheduler's semaphore to immediately try again. */ + tx_linux_sem_post(&_tx_linux_scheduler_semaphore); + + /* This indicates the Linux thread was actually terminated by ThreadX is only + being allowed to run in order to cleanup its resources. */ + _tx_linux_mutex_release_all(&_tx_linux_mutex); + + /* Exit this thread. */ + pthread_exit((void *)&exit_code); + } + } + + /* Determine if the deferred preempt flag is set. */ + if ((current_thread) && (current_thread -> tx_thread_linux_deferred_preempt)) + { + + /* Release the scheduler's semaphore to immediately try again. */ + tx_linux_sem_post(&_tx_linux_scheduler_semaphore); + + /* Release the protection that is nested. */ + _tx_linux_mutex_release_all(&_tx_linux_mutex); + + /* Sleep just to let other threads run. */ + _tx_linux_thread_sleep(1000000); + } + else + { + + /* Get out of the protection loop. */ + break; + } + } while (1); + + /* Setup the returned interrupt posture. */ + interrupt_posture = _tx_linux_global_int_disabled_flag; + + /* Determine if the protection is already active for this core. */ + if (_tx_thread_smp_protection.tx_thread_smp_protect_core == core) + { + + /* Yes, we have the protection already. */ + + /* Increment the protection count. */ + _tx_thread_smp_protection.tx_thread_smp_protect_count++; + + /* Set the global interrupt disable value. */ + _tx_linux_global_int_disabled_flag = TX_TRUE; + + /* Debug entry. */ + _tx_linux_debug_entry_insert("PROTECT-obtained-nested", __FILE__, __LINE__); + + /* Get out of the retry loop. */ + break; + } + /* Determine if the protection is available. */ + else if (_tx_thread_smp_protection.tx_thread_smp_protect_core == 0xFFFFFFFF) + { + + /* At this point we have the protection. Setup the protection structure. */ + _tx_thread_smp_protection.tx_thread_smp_protect_in_force = TX_TRUE; + _tx_thread_smp_protection.tx_thread_smp_protect_thread = current_thread; + _tx_thread_smp_protection.tx_thread_smp_protect_core = core; + _tx_thread_smp_protection.tx_thread_smp_protect_count = 1; + _tx_thread_smp_protection.tx_thread_smp_protect_linux_thread_id = current_thread_id; + + /* Set the global interrupt disable value. */ + _tx_linux_global_int_disabled_flag = TX_TRUE; + + /* Debug entry. */ + _tx_linux_debug_entry_insert("PROTECT-obtained", __FILE__, __LINE__); + + /* Get out of the retry loop. */ + break; + } + else + { + + /* Protection is owned by another core. */ + + /* Release the protection and start over. */ + _tx_linux_mutex_release(&_tx_linux_mutex); + } + } while (1); + + /* Set the global interrupt disable value. */ + _tx_linux_global_int_disabled_flag = TX_TRUE; + + /* Return the interrupt posture. */ + return(interrupt_posture); +} + + diff --git a/ports_smp/linux/gnu/src/tx_thread_smp_time_get.c b/ports_smp/linux/gnu/src/tx_thread_smp_time_get.c new file mode 100644 index 00000000..fa37135d --- /dev/null +++ b/ports_smp/linux/gnu/src/tx_thread_smp_time_get.c @@ -0,0 +1,82 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_time_get SMP/Linux/GCC */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets the global time value that is used for debug */ +/* information and event tracing. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* 32-bit time stamp */ +/* */ +/* CALLS */ +/* */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Source */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _tx_thread_smp_time_get(void) +{ + + /* Get the time stamp. */ + clock_gettime(CLOCK_REALTIME, &_tx_linux_time_stamp); + + /* Return 32-bit time. */ + return(((ULONG) (_tx_linux_time_stamp.tv_nsec))); +} + + diff --git a/ports_smp/linux/gnu/src/tx_thread_smp_unprotect.c b/ports_smp/linux/gnu/src/tx_thread_smp_unprotect.c new file mode 100644 index 00000000..350bb349 --- /dev/null +++ b/ports_smp/linux/gnu/src/tx_thread_smp_unprotect.c @@ -0,0 +1,140 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_unprotect SMP/Linux/GCC */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function releases previously obtained protection. The supplied */ +/* previous interrupt posture is restored. */ +/* */ +/* INPUT */ +/* */ +/* Previous interrupt posture */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* pthread_self */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Source */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +void _tx_thread_smp_unprotect(UINT new_interrupt_posture) +{ + +UINT core; +pthread_t current_thread_id; + + /* Lock Linux mutex. */ + _tx_linux_mutex_obtain(&_tx_linux_mutex); + + /* Pickup the current thread ID. */ + current_thread_id = pthread_self(); + + /* Pickup the current core. */ + core = _tx_thread_smp_core_get(); + + /* Determine if this core owns the protection. */ + if (_tx_thread_smp_protection.tx_thread_smp_protect_core == core) + { + + /* Yes, this core owns the protection. */ + + /* Decrement the protection count. */ + _tx_thread_smp_protection.tx_thread_smp_protect_count--; + + /* Is the protection still in force? */ + if (_tx_thread_smp_protection.tx_thread_smp_protect_count == 0) + { + + /* Restore the global interrupt disable value. */ + _tx_linux_global_int_disabled_flag = new_interrupt_posture; + + /* Determine if the preemption disable flag is set. */ + if (_tx_thread_preempt_disable == 0) + { + + /* Release the protection. */ + + /* Indicate the protection is no longer in force. */ + _tx_thread_smp_protection.tx_thread_smp_protect_in_force = TX_FALSE; + _tx_thread_smp_protection.tx_thread_smp_protect_thread = TX_NULL; + _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF; + _tx_thread_smp_protection.tx_thread_smp_protect_linux_thread_id = 0; + + /* Debug entry. */ + _tx_linux_debug_entry_insert("UNPROTECT-keep", __FILE__, __LINE__); + } + else + { + + /* Debug entry. */ + _tx_linux_debug_entry_insert("UNPROTECT-released", __FILE__, __LINE__); + } + } + else + { + + /* Debug entry. */ + _tx_linux_debug_entry_insert("UNPROTECT-nested", __FILE__, __LINE__); + } + + /* Only release the critical section. */ + _tx_linux_mutex_release(&_tx_linux_mutex); + } + + /* Release the critical section. */ + _tx_linux_mutex_release(&_tx_linux_mutex); + +} diff --git a/ports_smp/linux/gnu/src/tx_thread_stack_build.c b/ports_smp/linux/gnu/src/tx_thread_stack_build.c new file mode 100644 index 00000000..03a9c9bf --- /dev/null +++ b/ports_smp/linux/gnu/src/tx_thread_stack_build.c @@ -0,0 +1,160 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include +#include + + +/* Prototype for new thread entry function. */ + +void *_tx_linux_thread_entry(void *ptr); + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build SMP/Linux/GCC */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* pthread_create */ +/* pthread_setschedparam */ +/* _tx_linux_thread_suspend */ +/* sem_init */ +/* printf */ +/* _tx_linux_thread_resume */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* _tx_thread_reset Reset thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +{ +struct sched_param sp; +pthread_attr_t attrs; + + /* Create the run semaphore for the thread. This will allow the scheduler + control over when the thread actually runs. */ + if(sem_init(&thread_ptr -> tx_thread_linux_thread_run_semaphore, 0, 0)) + { + + /* Display an error message. */ + printf("ThreadX Linux error creating thread running semaphore!\n"); + while(1) + { + } + } + + /* Create a Linux thread for the application thread. */ + pthread_attr_init(&attrs); + pthread_attr_setstacksize(&attrs, TX_LINUX_THREAD_STACK_SIZE); + if(pthread_create(&thread_ptr -> tx_thread_linux_thread_id, &attrs, _tx_linux_thread_entry, thread_ptr)) + { + + /* Display an error message. */ + printf("ThreadX Linux error creating thread!\n"); + while(1) + { + } + } + + /* Otherwise, we have a good thread create. */ + sp.sched_priority = TX_LINUX_PRIORITY_USER_THREAD; + pthread_setschedparam(thread_ptr -> tx_thread_linux_thread_id, SCHED_FIFO, &sp); + + /* Setup the thread suspension type to solicited thread suspension. + Pseudo interrupt handlers will suspend with this field set to 1. */ + thread_ptr -> tx_thread_linux_suspension_type = 2; + + /* Clear the disabled count that will keep track of the + tx_interrupt_control nesting. */ + thread_ptr -> tx_thread_linux_mutex_access = TX_FALSE; + + /* Setup a fake thread stack pointer. */ + thread_ptr -> tx_thread_stack_ptr = (VOID *) (((CHAR *) thread_ptr -> tx_thread_stack_end) - 8); + + /* Clear the first word of the stack. */ + *(((ULONG *) thread_ptr -> tx_thread_stack_ptr) - 1) = 0; + + /* Indicate that this thread is now ready for scheduling again by another core. */ + thread_ptr -> tx_thread_smp_core_control = 1; +} + + +void *_tx_linux_thread_entry(void *ptr) +{ + +TX_THREAD *thread_ptr; + + /* Pickup the current thread pointer. */ + thread_ptr = (TX_THREAD *) ptr; + _tx_linux_threadx_thread = 1; + nice(20); + + /* Now suspend the thread initially. If the thread has already + been scheduled, this will return immediately. */ + tx_linux_sem_wait(&thread_ptr -> tx_thread_linux_thread_run_semaphore); + tx_linux_sem_post(&_tx_linux_scheduler_semaphore); + + /* Call ThreadX thread entry point. */ + _tx_thread_shell_entry(); + + return EXIT_SUCCESS; +} + diff --git a/ports_smp/linux/gnu/src/tx_thread_system_return.c b/ports_smp/linux/gnu/src/tx_thread_system_return.c new file mode 100644 index 00000000..207582ff --- /dev/null +++ b/ports_smp/linux/gnu/src/tx_thread_system_return.c @@ -0,0 +1,237 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +#include + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return SMP/Linux/GCC */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the system. Only a minimal context */ +/* is saved since the compiler assumes temp registers are going to get */ +/* slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_linux_debug_entry_insert */ +/* _tx_linux_mutex_obtain */ +/* pthread_self */ +/* pthread_getschedparam */ +/* pthread_equal */ +/* _tx_linux_mutex_release_all */ +/* pthread_exit */ +/* tx_linux_sem_post */ +/* sem_trywait */ +/* tx_linux_sem_wait */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_system_return(VOID) +{ + +TX_THREAD *temp_thread_ptr; +sem_t *temp_run_semaphore; +UINT temp_thread_state; +pthread_t thread_id; +int exit_code = 0; +UINT core; + + + /* Lock Linux mutex. */ + _tx_linux_mutex_obtain(&_tx_linux_mutex); + + /* Pickup current core. */ + core = _tx_thread_smp_core_get(); + + /* Debug entry. */ + _tx_linux_debug_entry_insert("SYSTEM_RETURN", __FILE__, __LINE__); + + /* First, determine if the thread was terminated. */ + + /* Pickup the id of the current thread. */ + thread_id = pthread_self(); + + /* Pickup the current thread pointer. */ + temp_thread_ptr = _tx_thread_current_ptr[core]; + + /* Determine if this is a thread (0) and it does not + match the current thread pointer. */ + if ((_tx_linux_threadx_thread) && + ((!temp_thread_ptr) || (!pthread_equal(temp_thread_ptr -> tx_thread_linux_thread_id, thread_id)))) + { + + /* This indicates the Linux thread was actually terminated by ThreadX is only + being allowed to run in order to cleanup its resources. */ + /* Unlock linux mutex. */ + _tx_linux_mutex_release_all(&_tx_linux_mutex); + pthread_exit((void *)&exit_code); + } + + /* Determine if the time-slice is active. */ + if (_tx_timer_time_slice[core]) + { + + /* Preserve current remaining time-slice for the thread and clear the current time-slice. */ + temp_thread_ptr -> tx_thread_time_slice = _tx_timer_time_slice[core]; + _tx_timer_time_slice[core] = 0; + } + + /* Save the run semaphore into a temporary variable as well. */ + temp_run_semaphore = &temp_thread_ptr -> tx_thread_linux_thread_run_semaphore; + + /* Pickup the current thread state. */ + temp_thread_state = temp_thread_ptr -> tx_thread_state; + + /* Setup the suspension type for this thread. */ + temp_thread_ptr -> tx_thread_linux_suspension_type = 2; + + /* Set the current thread pointer to NULL. */ + _tx_thread_current_ptr[core] = TX_NULL; + + /* Clear this mapping entry. */ + _tx_linux_virtual_cores[core].tx_thread_smp_core_mapping_thread = TX_NULL; + _tx_linux_virtual_cores[core].tx_thread_smp_core_mapping_linux_thread_id = 0; + + /* Debug entry. */ + _tx_linux_debug_entry_insert("SYSTEM_RETURN-release_sem", __FILE__, __LINE__); + + /* Determine if there is a system error. */ + if (temp_thread_ptr != _tx_thread_smp_protection.tx_thread_smp_protect_thread) + { + + /* This should not happen... increment the system error counter. */ + _tx_linux_system_error++; + } + + /* Clear the protection structure. */ + _tx_thread_smp_protection.tx_thread_smp_protect_count = 0; + _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF; + _tx_thread_smp_protection.tx_thread_smp_protect_thread = TX_NULL; + _tx_thread_smp_protection.tx_thread_smp_protect_in_force = TX_FALSE; + _tx_thread_smp_protection.tx_thread_smp_protect_linux_thread_id = 0; + + /* Indicate that this thread is now ready for scheduling again by another core. */ + temp_thread_ptr -> tx_thread_smp_core_control = 1; + + /* Clear the interrupt disable flag. */ + _tx_linux_global_int_disabled_flag = TX_FALSE; + + /* Clear the preempt disable flag. */ + _tx_thread_preempt_disable = 0; + + /* Make sure semaphore is 0. */ + while(!sem_trywait(&_tx_linux_scheduler_semaphore)); + + /* Release the semaphore that the main scheduling thread is waiting + on. Note that the main scheduling algorithm will take care of + setting the current thread pointer to NULL. */ + tx_linux_sem_post(&_tx_linux_scheduler_semaphore); + + /* Unlock Linux mutex. */ + _tx_linux_mutex_release_all(&_tx_linux_mutex); + + /* Determine if the thread was self-terminating. */ + if (temp_thread_state == TX_TERMINATED) + { + + /* Exit the thread instead of waiting on the semaphore! */ + pthread_exit((void *)&exit_code); + } + + /* Wait on the run semaphore for this thread. This won't get set again + until the thread is scheduled. */ + tx_linux_sem_wait(temp_run_semaphore); + tx_linux_sem_post(&_tx_linux_scheduler_semaphore); + + /* Lock Linux mutex. */ + _tx_linux_mutex_obtain(&_tx_linux_mutex); + + /* Debug entry. */ + _tx_linux_debug_entry_insert("SYSTEM_RETURN-wake_up", __FILE__, __LINE__); + + /* Determine if the thread was terminated. */ + + /* Pickup current core. */ + core = _tx_thread_smp_core_get(); + + /* Pickup the current thread pointer. */ + temp_thread_ptr = _tx_thread_current_ptr[core]; + + /* Determine if this is a thread and it does not + match the current thread pointer. */ + if ((_tx_linux_threadx_thread) && + ((!temp_thread_ptr) || (!pthread_equal(temp_thread_ptr -> tx_thread_linux_thread_id, thread_id)))) + { + + /* Unlock Linux mutex. */ + _tx_linux_mutex_release_all(&_tx_linux_mutex); + + /* This indicates the Linux thread was actually terminated by ThreadX and is only + being allowed to run in order to cleanup its resources. */ + pthread_exit((void *)&exit_code); + } + + /* Now determine if the application thread last had interrupts disabled. */ + + /* Debug entry. */ + _tx_linux_debug_entry_insert("SYSTEM_RETURN-finish", __FILE__, __LINE__); + + /* Unlock Linux mutex. */ + _tx_linux_mutex_release_all(&_tx_linux_mutex); +} + diff --git a/ports_smp/linux/gnu/src/tx_timer_interrupt.c b/ports_smp/linux/gnu/src/tx_timer_interrupt.c new file mode 100644 index 00000000..4cc62e89 --- /dev/null +++ b/ports_smp/linux/gnu/src/tx_timer_interrupt.c @@ -0,0 +1,138 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_timer.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt SMP/Linux/GCC */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_linux_debug_entry_insert */ +/* _tx_timer_expiration_process */ +/* _tx_thread_time_slice */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_timer_interrupt(VOID) +{ + +UINT saved_posture; + + + /* Get the protection. */ + saved_posture = _tx_thread_smp_protect(); + + /* Increment the system active counter. */ + _tx_timer_interrupt_active++; + + /* Debug entry. */ + _tx_linux_debug_entry_insert("TIMER INTERRUPT", __FILE__, __LINE__); + + /* Increment the system clock. */ + _tx_timer_system_clock++; + + /* Test for timer expiration. */ + if (*_tx_timer_current_ptr) + { + + /* Set expiration flag. */ + _tx_timer_expired = TX_TRUE; + } + else + { + + /* No timer expired, increment the timer pointer. */ + _tx_timer_current_ptr++; + + /* Check for wrap-around. */ + if (_tx_timer_current_ptr == _tx_timer_list_end) + { + + /* Wrap to beginning of list. */ + _tx_timer_current_ptr = _tx_timer_list_start; + } + } + + /* See if anything has expired. */ + if (_tx_timer_expired) + { + + /* Did a timer expire? */ + if (_tx_timer_expired) + { + + /* Process timer expiration. */ + _tx_timer_expiration_process(); + } + } + + /* Call time-slice processing to process time-slice for all threads on each core. */ + _tx_thread_time_slice(); + + /* Increment the system active counter. */ + _tx_timer_interrupt_active++; + + /* Release the protection. */ + _tx_thread_smp_unprotect(saved_posture); +}